SEMICONDUCTOR TECHNICAL DATA

  
   
High–Performance Silicon–Gate CMOS
The MC54/74HC08A is identical in pinout to the LS08. The device J SUFFIX
inputs are compatible with Standard CMOS outputs; with pullup resistors, CERAMIC PACKAGE
14 CASE 632–08
they are compatible with LSTTL outputs.
1

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS and TTL N SUFFIX
PLASTIC PACKAGE
• Operating Voltage Range: 2 to 6V 14 CASE 646–06
• Low Input Current: 1µA
1
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance With the JEDEC Standard No. 7A Requirements
D SUFFIX
• Chip Complexity: 24 FETs or 6 Equivalent Gates 14 SOIC PACKAGE
1 CASE 751A–03

LOGIC DIAGRAM DT SUFFIX

14 TSSOP PACKAGE
1 CASE 948B–03
1
A1 3
2 Y1 ORDERING INFORMATION
B1
MC54HCXXAJ Ceramic
4 MC74HCXXAN Plastic
A2 6
5 Y2 MC74HCXXAD SOIC
B2 MC74HCXXADT TSSOP
Y = AB
9
A3 8
10 Y3
B3 FUNCTION TABLE
12 Inputs Output
A4 11
13 Y4
B4 A B Y

PIN 14 = VCC L L L
PIN 7 = GND L H L
H L L
H H H

Pinout: 14–Lead Packages (Top View)

VCC B4 A4 Y4 B3 A3 Y3
14 13 12 11 10 9 8

1 2 3 4 5 6 7
A1 B1 Y1 A2 B2 Y2 GND

10/95

 Motorola, Inc. 1995 1 REV 6

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MC54/74HC08A
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MAXIMUM RATINGS*

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Symbol Parameter Value Unit This device contains protection

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VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage

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due to high static voltages or electric
Vin DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V fields. However, precautions must

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Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
be taken to avoid applications of any

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voltage higher than maximum rated
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

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cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA

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Vout should be constrained to the
ICC DC Supply Current, VCC and GND Pins ± 50 mA v
range GND (Vin or Vout) VCC. v
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Unused inputs must always be
PD Power Dissipation in Still Air, Plastic or Ceramic DIP† 750 mW

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tied to an appropriate logic voltage
SOIC Package† 500 level (e.g., either GND or VCC).

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TSSOP Package† 450
Unused outputs must be left open.

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Tstg Storage Temperature – 65 to + 150 _C

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TL Lead Temperature, 1 mm from Case for 10 Seconds _C
Plastic DIP, SOIC or TSSOP Package 260

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Ceramic DIP 300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C

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SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C

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For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

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RECOMMENDED OPERATING CONDITIONS

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Symbol Parameter Min Max Unit

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VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

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Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

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TA Operating Temperature, All Package Types – 55 + 125 _C

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tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns

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(Figure 1) VCC = 4.5 V 0 500

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VCC = 6.0 V 0 400

MOTOROLA 2 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC08A

DC CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
VCC
Symbol Parameter Condition V –55 to 25°C ≤85°C ≤125°C Unit
VIH Minimum High–Level Input Voltage Vout = 0.1V or VCC –0.1V 2.0 1.50 1.50 1.50 V
|Iout| ≤ 20µA 3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum Low–Level Input Voltage Vout = 0.1V or VCC – 0.1V 2.0 0.50 0.50 0.50 V
|Iout| ≤ 20µA 3.0 0.90 0.90 0.90
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
Voltage |Iout| ≤ 20µA 4.5 4.4 4.4 4.4
6.0 5.9 5.9 5.9
Vin =VIH or VIL |Iout| ≤ 2.4mA 3.0 2.48 2.34 2.20
|Iout| ≤ 4.0mA 4.5 3.98 3.84 3.70
|Iout| ≤ 5.2mA 6.0 5.48 5.34 5.20
VOL Maximum Low–Level Output Vin = VIH or VIL 2.0 0.1 0.1 0.1 V
Voltage |Iout| ≤ 20µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
Vin = VIH or VIL |Iout| ≤ 2.4mA 3.0 0.26 0.33 0.40
|Iout| ≤ 4.0mA 4.5 0.26 0.33 0.40
|Iout| ≤ 5.2mA 6.0 0.26 0.33 0.40
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 1.0 10 40 µA
Current (per Package) Iout = 0µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)

Guaranteed Limit
VCC
Symbol Parameter V –55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Input A or B to Output Y 2.0 75 95 110 ns
tPHL (Figures 1 and 2) 3.0 30 40 55
4.5 15 19 22
6.0 13 16 19
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns
tTHL (Figures 1 and 2) 3.0 27 32 36
4.5 15 19 22
6.0 13 16 19
Cin Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V, VEE = 0 V

CPD Power Dissipation Capacitance (Per Buffer)* 20 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).

High–Speed CMOS Logic Data 3 MOTOROLA

DL129 — Rev 6
MC54/74HC08A

tr tf
VCC
90%
INPUT 50%
A OR B
10% GND

tPLH tPHL

90%
OUTPUT Y 50%
10%

tTLH tTHL

Figure 1. Switching Waveforms

TEST
POINT

OUTPUT
DEVICE
UNDER
TEST CL*

*Includes all probe and jig capacitance

Figure 2. Test Circuit

A
Y
B

Figure 3. Expanded Logic Diagram

(1/4 of the Device)

MOTOROLA 4 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC08A

OUTLINE DIMENSIONS

J SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y

-A-
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
14 8 Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
-B- 3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
1 7 4. DIMESNION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
C L BODY.

INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.94
B 0.245 0.280 6.23 7.11
C 0.155 0.200 3.94 5.08
-T-
SEATING K D 0.015 0.020 0.39 0.50
PLANE F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
F G N M J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
D 14 PL J 14 PL L 0.300 BSC 7.62 BSC
M 0° 15° 0° 15°
0.25 (0.010) M T A S 0.25 (0.010) M T B S
N 0.020 0.040 0.51 1.01

N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
14 8 MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
1 7 FLASH.
4. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J J 0.008 0.015 0.20 0.38
N K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
SEATING
PLANE K M 0_ 10_ 0_ 10_
H G D M N 0.015 0.039 0.39 1.01

High–Speed CMOS Logic Data 5 MOTOROLA

DL129 — Rev 6
MC54/74HC08A

OUTLINE DIMENSIONS

D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
14 8 MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
–B– P 7 PL PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G MILLIMETERS INCHES
R X 45° F
DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
SEATING K M J F 0.40 1.25 0.016 0.049
PLANE
D 14 PL G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S
K 0.10 0.25 0.004 0.009
M 0° 7° 0° 7°
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948B–03
ISSUE A
A
14X K REF

0.200 (0.008) M T
NOTES:
1 DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 8 2 CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L B 4. DIMENSION B DOES NOT INCLUDE INTERLEAD
PIN 1 FLASH OR PROTRUSION. INTERLEAD FLASH OR
IDENTIFICATION PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
1 7 PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSIONS A AND B ARE TO BE DETERMINED
C AT DATUM PLANE –U–.

MILLIMETERS INCHES
–U– DIM MIN MAX MIN MAX
A ––– 5.10 ––– 0.200
B 4.30 4.50 0.169 0.177
0.100 (0.004) C ––– 1.20 ––– 0.047
D G H
–T– SEATING D 0.05 0.25 0.002 0.010
PLANE F 0.45 0.55 0.018 0.022
G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
A J 0.09 0.24 0.004 0.009
K
J1 0.09 0.18 0.004 0.007
K1 K 0.16 0.32 0.006 0.013
J1 K1 0.16 0.26 0.006 0.010
M L 6.30 6.50 0.248 0.256
M 0° 10 ° 0° 10 °
J
A

SECTION A–A F

MOTOROLA 6 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC08A

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*MC54/74HC08A/D*
◊ CODELINE MC54/74HC08A/D
High–Speed CMOS Logic Data 7 MOTOROLA
DL129 — Rev 6