2022

Digital Logic Design (EC-4002)

Switching Circuits and Logic Design (EC-4010)
Digital Electronics and Logic Design (EC-4006)

Laboratory File
B. Tech. (Computer Engineering)
B. Tech. (Information Technology)
B. Tech. (Information & Communication Technology)
B. Tech. (Electronics & Communication)
B. Tech. (Mechatronics)

Submitted to:
Department of Electronics and Communication
C. G. Patel Institute of Technology,
Bardoli.
 DEPARTMENT OF CE/IT/EC/ICT/MECHTRONICS

This is to certify that Mr/Ms____________________________________________

Roll No. _______________________________ has satisfactorily completed his/her term

work and practical work in the subject “DLD/SCLD/DELD” for the term

ending in DEC 2022 at CGPIT, Bardoli for the partial fulfilment of B.Tech.

degree to be awarded by Uka Tarsadia University.

Internal Examiner Head of Department

Subject Teacher Ms. Krupa Dave
(EC/ICT Dept.) Head (EC/ICT Dept.)

SEAL OF DEPARTMENT
Nov./Dec. 2022
 Index

Sr.
Title Date Signature
No.

1 To study and verify truth tables of all logic gates.

To design and implement all gates using NAND & NOR

2
universal gates.
To design and implement half adder, half subtractor and
3
both with a select input line.
To design and implement full adder, full subtractor and both
4
with a select input line.
To design and implement parity generator and checker
5
circuits.

To study & verify the code conversion circuits.

6 1. Binary to Gray code.
2. Gray to Binary code.

To study the following circuit and verify their truth table:

7 1. 4 To 1 Line Multiplexer.
2. 1 To 4 Line De-Multiplexer.
To study the following circuit and verify their truth table:
8 1. 3×8 Decoder
2. 8×3 Encoder
To study the following circuit and verify their truth table:
9 1. R-S flip flop 3. D flip flop
2. J-K flip flop 4. T flip flop

10 To study and implement shift registers using D flip-flop.

11 To study and implement Up-Down synchronous counter.

12 To study and implement Johnson counter.

 PRACTICAL: 1

AIM:To study and verify truth tables of all logic gates.

APPARATUS:DC Supply, Trainer, Logic Inputs, Connectors, IC 7400, IC 7402, IC 7404,IC

7408, IC 7432 and IC 7486. (Logic 1 = +5V; Logic 0 = GND)

THEORY:

Any Gate is a logic circuit with one output and one or more inputs. The output signal of
any gate occurs only for certain combination of input signals. AND, OR and NOT are the
basic gates. Such gates can be prepared by using discrete components like diodes,
transistors, resistors but nowadays different types of IC’s are used to have different
gates. A power supply of +5V is used to give input. This supply is also used to drive ICs.
When power supply to the input is ‘ON’, the logic level is said to be at ‘1’ level and when
power supply to the input is ‘OFF’, the logic level is said to be at ‘0’ level.

 AND GATE:

AND gate is a gate, which gives output only when all inputs are present. Here IC7408 is
used which has 2-inputs AND gate. The truth table of AND gate is given in the table.

Internal IC Diagram: Truth Table

A B Y

 OR GATE:

OR gate is a gate which gives output when any one of the input is present. Here IC7432
is used which has two input OR gate. The truth table of OR gate is given in the table.

Internal IC Diagram: Truth Table

A B Y

Digital Logic Design 1 CGPIT-Bardoli

 NOT GATE:

This is also known as INVERTOR gate. This gate has one input and one output. All it does
is invert the input signal i.e. if the input is at high level, the output will be at low level
and vice versa. IC’s 7404 or 7406 can be used to get NOT gate. This IC has one input NOT
gates. The truth table of NOT gate is given in the table.

Internal IC Diagram: Truth Table

A Y

 NAND GATE:

It is a sequence of series combination of AND gate & NOT gate, known as NAND gate.
The output of NAND gate is at ‘0’ level only when all inputs are at ‘1’ level. In rest of all
the conditions of inputs the output will be at ‘1’ level. IC 7400 can be used to get NAND
gate. This IC has two inputs NAND gate. The truth table of NAND gate is given in the
table.

Internal IC Diagram: Truth Table

A B Y

 NOR GATE:

It is a sequence series combination of OR gate & NOT gate. The output on NOR gate is at
‘1’ level on when all inputs are at ‘0’ level. In rest all conditions of inputs the output is at
‘0’ level. IC 7402 can be used for NOR gate. The truth table of NOR gate is given in the
table.

Internal IC Diagram: Truth Table

A B Y

Digital Logic Design 2 CGPIT-Bardoli

 EX-OR GATE:

EX-OR gate is a gate, which gives output only when both inputs are different. Here
IC74136 is used which has 2-inputs EX-OR gate. The truth table of EX-OR gate is given in
the table.

Internal IC Diagram: Truth Table

A B Y

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. Connect inputs 00, 01, 10, 11 as per truth table to pin A and B of AND Gate.
3. Switch on the power supply.
4. Observe output Y of AND Gates on logic probe or on LED display and prove truth
tables.
5. Repeat above steps for remaining logic gates

CONCLUSION:

Digital Logic Design 3 CGPIT-Bardoli

 PRACTICAL: 2

AIM:Design and implementation of all gates using NAND & NOR gates.

APPARATUS:DC Supply, trainer, logic inputs, IC 7400, IC 7402, Connectors.

THEORY:

The basic building block of digital systems is known as gates because they control the
passage of signals. Gate is digital circuit with one or more input but only one output. The
gates by use of which the work of other gates can be performed are known as “Universal
gates”. NAND & NOR gates are universal gates.

The gates can be defined as follows:

AND : The output is high when all the inputs are high.
OR : The output is high when either of the input is high.
NOT : The output is compliment of the input.
NAND : The output is high if any of the inputs is/are low.
NOR : The output is high only if all the inputs are low..
XOR : The output is high if high inputs are in odd number.
XNOR : The output is high if low inputs are in even number.
CIRCUIT DIAGRAM:

USING NAND GATE USING NOR GATE

NOT LOGIC NOT LOGIC

AND LOGIC AND LOGIC

Digital Logic Design 4 CGPIT-Bardoli

OR LOGIC OR LOGIC

XOR LOGIC XOR LOGIC

XNOR LOGIC XNOR LOGIC

PROCEDURE:

1. Connect the logic gates as shown in the diagrams.

2. Feed the logic signals 0 or 1 from the logic input switches in different combinations
at the inputs A & B.
3. Monitor the output using logic output LED indicators.
4. Repeat steps 1 to 3 for NOT, AND, OR, EX – OR & EX-NOR operations and compare
the outputs with the truth tables.

CONCLUSION:

Digital Logic Design 5 CGPIT-Bardoli

 PRACTICAL: 3

AIM:To design and implement half adder, half subtractor and both with a select input
circuit.

APPARATUS:DC supply, Trainer, Logic Inputs, IC 7408, IC 7404, IC 7486, connectors.

THEORY:

Digital computers perform variety of tasks. Among them basic arithmetic operations are
additions, subtraction, & multiplication of two binary no. In a combinational circuit, the
addition of two bits without taking into account previous carry is called half adder
circuit.

A combinational circuit that performs subtraction between two bits without taking
borrow is called a half subtractor. It has two inputs and two outputs.

Four inputs are given –Two are the binary inputs for which the sum or the difference is
to be found, one input as end carry &the fourth is the select input. When the select input
is ”1”, the circuit act as half adder & When the select input is ”0”, the circuit act as half
subtractor.

CIRCUIT DIAGRAM:

 HALF ADDER

 HALF SUBTRACTOR

Digital Logic Design 6 CGPIT-Bardoli

  HALF ADDER & SUBTRACTOR USING SELECT LINE

PROCEDURE:

1. Make the connections as per the circuit diagram.

2. Switch on VCC and apply various combinations of input according to truth table.
3. Note down the output readings for half adder and half subtractor, Sum/difference
and the carry/borrow bit for different combinations of inputs verify their truth
tables.

OBSERVATION:

TRUTH TABLE:

 HALF ADDER  HALF SUBTRACTOR

SUM= DIFFERENCE=
CARRY= BORROW=

A B SUM CARRY A B DIFF. BORROW

Digital Logic Design 7 CGPIT-Bardoli

 HALF ADDER AND HALF SUBTRACTOR USING SELECT LINE

M
A B
(SELECT SUM/DIFFERENCE CARRY/BORROW
(INPUT-1) (INPUT-2)
LINE)

CONCLUSION:

Digital Logic Design 8 CGPIT-Bardoli

 PRACTICAL: 4

AIM:To design and implement full adder, full subtractor and both with a select input
circuit.

APPARATUS:DC supply, trainer, logic inputs, IC 7408, IC 7432, IC 7486, IC 7404,

connectors

THEORY:

Digital computers perform variety of tasks. Among them basic arithmetic operations are
additions, subtraction, & multiplication of two binary no. A combinational circuit the
addition of three bits is called full adder circuit (2 significant bits and one end carry).
The third input represents the carry from the lower previous significant position.

A combinational circuit that performs subtraction between two bits taking into account
that “1” may be borrowed by a lower significant stage is called a full subtractor. It has 3
inputs & 2 outputs.

CIRCUIT DIAGRAM:

 FULL ADDER

 FULL SUBTRACTOR

Digital Logic Design 9 CGPIT-Bardoli

 FULL ADDER & SUBTRACTOR USING SELECT LINE

PROCEDURE:

1. Make the connections as per the circuit diagram.

2. Switch on VCC and apply various combinations of input according to truth table.
3. Note down the output readings for full adder and full subtractor, Sum/difference
and the carry/borrow bit for different combinations of inputs verify their truth
tables.

OBSERVATION:

TRUTH TABLE:

 FULL ADDER  FULL SUBTRACTOR

S= D=
C= BR=

A B CN-1 S C A B CN-1 D BR

Digital Logic Design 10 CGPIT-Bardoli

 FULL ADDER AND FULL SUBTRACTOR USING SELECT LINE

E A B CN-1 S/D C/BR

CONCLUSION:

Digital Logic Design 11 CGPIT-Bardoli

 PRACTICAL: 5

AIM:To implement the parity generator and checker circuits.

APPARATUS:DC Supply, trainer, logic inputs, connectors

THEORY:

Binary informationmay be transmitted through some form of communication medium

such as wires or radio waves. Any external noise introduced into physical
communication medium changes the bit values 0 & 1or vice versa. An error detection
code can be used to detect error using transmission. The detected error cannot be
corrected, but its presence is indicated.

A parity bit is an extra bit included with message to make the total no. of 1’s either even
or odd. In the sending end, the message applied to a parity generator network where the
required P bit is generated. The message including the parity bit is transferred to its
destination. In the receiving end, all the incoming bits are applied to a parity checker
network to check the proper parity adopted.

CIRCUIT DIAGRAM:

 3 BIT EVEN PARITY GENERATOR:

 3 BIT EVEN PARITY CHECKER:

Digital Logic Design 12 CGPIT-Bardoli

PROCEDURE:

1. Make necessary connections for the parity generator and checker.

2. Provide inputs and check the corresponding outputs to verify the truth table.

OBSERVATION:

 3 BIT EVEN PARITY GENERATOR:

Input Output
X Y Z Pe

 3 BIT EVEN PARITY CHECKER:

Input Output
X Y Z Pe Ce

CONCLUSION:

Digital Logic Design 13 CGPIT-Bardoli

 PRACTICAL: 6

AIM: To study & verify the code conversion circuits.

1. Binary to Gray code.
2. Gray to Binary code.

APPARATUS:DC Supply, trainer, logic inputs, IC 7486, connectors

THEORY:

The availability of a large variety of codes for the same discrete elements of information
results in the use of different codes by different digital system. It is sometimes
necessary to use the output of one system as the input to another. A conversion circuit
must be inserted between the two systems if each uses different codes for the same
information. Thus, a code converter is a circuit that makes the two systems compatible
even though each uses a different binary code.

When there is continuous information with fixed interval it is better to use gray code as
it changes only in one bit if we move from one code to other. Hence it is also known as
reflected gray code. Binary code are given by b3, b2, b1, b0 & Gray code are given by g3,
g2, g1, g0

CIRCUIT DIAGRAM:

 CONVERTING BINARY TO GRAY:

 CONVERTING GRAY TO BINARY:

Digital Logic Design 14 CGPIT-Bardoli

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. In the case of binary to gray conversion, the inputs B0, B1, B2 and B3 are given at
respective pins and outputs G0, G1, G2, and G3 are taken for all the 16 combinations
of the input.
3. In the case of gray to binary conversion, the inputs G0, G1, G2 and G3 are given at
respective pins and outputs B0, B1, B2, and B3 are taken for all the 16 combinations
of inputs.
4. The values of the outputs are tabulated.

OBSERVATION:

 TRUTH TABLE OF CONVERTING BINARY TO GRAY:

Decimal Binary Code Gray Code

B3 B2 B1 B0 G3 G2 G1 G0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Digital Logic Design 15 CGPIT-Bardoli

 TRUTH TABLE OF CONVERTING GRAY TO BINARY:

Decimal Gary Code Binary Code

G3 G2 G1 G0 B3 B2 B1 B0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

CONCLUSION:

Digital Logic Design 16 CGPIT-Bardoli

 PRACTICAL: 7

AIM:To study the following circuit and verify their truth table.
1. 4 To 1 line Multiplexer.
2. 1 To 4 line De-Multiplexer.

APPARATUS: Digital board of Multiplexer-De-Multiplexer, DC power supply,

connectors

THEORY:

Multiplexing means transmitting a large number of information units over a smaller

number of channels or lines. A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a single output line.
The selection of a particular input line is controlled by a set of selection lines. There are
2n input lines and n selection lines whose bit combinations determine which input is
selected.

A De-multiplexer is a circuit that receives information on a single line and transmits this
information on one of 2n possible output lines. The selection of a specific output line is
controlled by the bit values of n selection lines.

CIRCUIT DIAGARAM:

 4 TO 1 LINE MULTIPLEXER

 1 TO 4 LINE DE-MULTIPLEXER

Digital Logic Design 17 CGPIT-Bardoli

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. Switch on the power supply.
3. Apply different combinations of inputs and observe the outputs and compare the
outputs with the truth tables.

OBSERVATION:

 4 TO 1 LINE MULTIPLEXER  1 TO 4 LINE DE-MULTIPLEXER

INPUT OUTPUT INPUT OUTPUT

E S1 S0 Y E S1 S0 D0 D1 D2 D3

CONCLUSION:

Digital Logic Design 18 CGPIT-Bardoli

 PRACTICAL: 8

AIM: To study the following circuit and verify their truth table.
1. 3×8 Decoder
2. 8×3 Encoder

APPARATUS: Digital board of Multiplexer-De-Multiplexer, DC power, connectors

THEORY:

Discrete quantities of information are represented in digital systems with binary codes.
2n distinct elements can be represented by a binary code of n bits. An encoder has 2n
input lines and n output lines. The output lines generate the binary code for the 2 n input
variables. The 8 to 3 line encoder consists of eight inputs D0-D7, and three outputs X, Y,
Z that generates the corresponding binary number.

A decoder is a digital function that produces a reverse operation from that of an

encoder. A decoder is a combinational circuit that converts binary information from n
input lines to a maximum of 2n unique output lines. In 3 to 8 line decoder, three inputs
X, Y, Z are decoded in to eight outputs D0-D7.

CIRCUIT DIAGRAM:

 8 TO 3 LINE ENCODER

Digital Logic Design 19 CGPIT-Bardoli

 3 TO 8 LINE DECODER

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. Switch on the power supply.
3. Apply different combinations of inputs and observe the outputs and compare the
outputs with the truth tables.

OBSERVATION:

 8 TO 3 LINE ENCODER

INPUT OUTPUT
D0 D1 D2 D3 D4 D5 D6 D7 X Y Z

Digital Logic Design 20 CGPIT-Bardoli

 3 TO 8 LINE DECODER

INPUT OUTPUT
X Y Z D0 D1 D2 D3 D4 D5 D6 D7

CONCLUSION:

Digital Logic Design 21 CGPIT-Bardoli

 PRACTICAL: 9

AIM: To study following flip-flops and prove their truth tables:

1. R-S flip flop
2. J-K flip flop
3. D flip flop
4. T flip flop

APPARATUS:DC Supply, trainer, logic inputs, IC 7400, IC 7402, IC 7404.

THEORY:

 S-R FLIP FLOP:

In this flip flop three inputs are used i.e. S, R and clock input. Here negative triggering is
used i.e. flip flop will be activated when the clock goes from ‘1’ to ‘0’. Now when both S-R
inputs are same the output will remain in the previous state. When S=1 and R=0, flip
flop will be in set mode i.e. Q=1. When R=1 and S=0, it will be in reset mode i.e. Q=0.
Now when both are 1, then basic definition of output is violated and consider the state
as indeterminate.

 J-K FLIP FLOP:

The inputs to this flip flop are J, K, CLK, preset and clear. The two outputs are
complement of each other. This requires four 3 input gates for implementation. For
working of this flip flop the preset and clear should be at logic 1. The JK flip flop IC 7476
is a negative edge triggered. The state will change only when the clock pulse changes
from 1 to 0.

Characteristic Equation: Qn+1 = JQ’+K’Q

 D FLIP FLOP:

In this flip flop one signal is provided to one input and its inverted version is given to
other input. The D flip-flop captures the value of the D-input at a definite portion of the
clock cycle (such as the rising edge of the clock). That captured value becomes the Q
output. i.e. when D=1, Q=1 and when D=0, Q=0.

 T FLIP FLOP:

When both input of JK flip flop are 1 then output will toggle between 0 and 1. This is
called T- flip flop.

Digital Logic Design 22 CGPIT-Bardoli

CIRCUIT DIAGRAM:

 S-R FLIP-FLOP:

 J-K FLIP-FLOP:

 D FLIP-FLOP:

 T FLIP-FLOP:

Digital Logic Design 23 CGPIT-Bardoli

PROCEDURE:

1. Connect the Flip-flop circuits as shown above.

2. Apply different combinations of inputs and observe the outputs.

OBSERVATION:

 S-R FLIP-FLOP:  J-K FLIP-FLOP:

S R Qn+1 J K Qn+1

 D FLIP-FLOP:  T FLIP-FLOP:

D Qn+1 T Qn+1

CONCLUSION:

Digital Logic Design 24 CGPIT-Bardoli

 PRACTICAL: 10

AIM:To study shift registers using D flip-flop.

APPARATUS:DC Supply, trainer, logic inputs, IC 7474, connectors.

THEORY:

A register is a group of binary storage cells suitable for holding binary information. A
group of flip-flops constitute a register, since each flip flop is a binary cell capable of
storing one bit of information. An n-bit register has a group of n flip-flops and is capable
of storing any binary information containing n bits. In addition to the flip flops, a
register may have combinational gates that perform certain data processing tasks like
when and how new information is transferred in to the register.

A register is capable of shifting its binary information either to the right or to the left is
called a shift register. The logical configuration of a shift register consists of a chain of
flip-flops connected in cascade, with the output of one flip-flop connected to the input of
next flip-flop. All flip flops receive a common clock pulse, which causes the shift from
one stage to the next.

In 4 bit serial in -parallel out shift register the, Q output of a given flip-flop is connected
to the D input of the flip-flop at its right. Each clock pulse shifts the contents of the
register one bit position to the right. The serial input determines what goes into the
leftmost flip flop during the shift. The serial output is taken from the output of rightmost
flip-flop prior to the application of pulse. The register shifts its contents with every
clock during the positive edge of the pulse transition.

CIRCUIT DIAGRAM:

 SERIAL IN PARALLEL OUT SHIFT REGISTER

Digital Logic Design 25 CGPIT-Bardoli

PROCEDURE:

1. Connections are made as per circuit diagram.

2. Apply the data at input.
3. Apply one clock pulse and observe this data at FF0.
4. Apply the next data at input.
5. Apply one clock pulse and observe that the data on FF0 will shift to FF1 and the new
data applied will appear at FF0.
6. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the shift
register.

OBSERVATION:

Clock pulse No. Serial Input FF0 FF1 FF2 FF3

0
1
2
3
4
5

CONCLUSION:

Digital Logic Design 26 CGPIT-Bardoli

 PRACTICAL: 11

To study Up-Down synchronous counter.

APPARATUS:DC Supply, Trainer, Logic Inputs, IC 74193, IC 7408, IC 7476, IC 7400, IC

7432, connectors.

THEORY:

In synchronous counter, the clock pulse is applied to all the flip flops and triggers them
simultaneously. The design of such counter is carried out using synchronous sequential
circuit. When counting reaches at 10 the next state will be 00. Then the counting
sequence starts again.

In synchronous counter, the external clock signal is connected to the clock input of
every individual flip-flop within the counter so that all of the flip-flops are clocked
together simultaneously (in parallel) at the same time giving a fixed time relationship.
In other words, changes in the output occur in "synchronization" with the clock signal.
This results in all the individual output bits changing state at exactly the same time in
response to the common clock signal with no ripple effect and therefore, no propagation
delay.

Synchronous counters can be made from Toggle or D-type flip flops. They are called
synchronous counters because the clock input of the flip flops are clocked with the same
clock signal. Due to the same clock pulse all outputs change simultaneously.
Synchronous counters are also called parallel counters as the clock is fed in parallel to
all flip flops. Synchronous binary counters use both sequential and combinational logic
elements. The memory section keeps track of the present state. The sequence of the
count is controlled by combinational logic.

CIRCUIT DIAGRAM

 3-BIT UP COUNTER

Digital Logic Design 27 CGPIT-Bardoli

 3-BIT DOWN COUNTER

PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Switch on the power supply.
3. Apply clock pulses and note the outputs after each clock pulse.

OBSERVATION:

 3-BIT UP COUNTER:

PRESENT STATE NEXT STATE INPUTS

QA QB QC QA QB QC JA KA JB KB JC KC

 DESIGN CALCULATION:

Digital Logic Design 28 CGPIT-Bardoli

 3-BIT DOWN COUNTER:

PRESENT STATE NEXT STATE INPUTS

QA QB QC QA QB QC JA KA JB KB JC KC

 DESIGN CALCULATION:

CONCLUSION:

Digital Logic Design 29 CGPIT-Bardoli

 PRACTICAL: 12

AIM: To study and implement Johnson counter.

APPARATUS: DC Supply, trainer, logic inputs, IC 7474, connectors.

THEORY:

A Johnson counter is a modified twisted ring counter, where the output from the last
stage is inverted and fed back as input to the first stage. A pattern of bits equal in length
to twice the length of the shift register thus circulates indefinitely. These counters find
specialist applications, including those similar to the decade counter, digital to analog
conversion, etc.

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connections are made as per the circuit diagram.

2. Switch on the power supply.
3. Apply clock pulses and note the outputs after each clock pulse.

Digital Logic Design 30 CGPIT-Bardoli

OBSERVATION:

CLOCK Q1 Q2 Q3 Q4
0
1
2
3
4
5
6
7
8

CONCLUSION:

Digital Logic Design 31 CGPIT-Bardoli