DLD Assignment 5

1. What is Arithmetic and Logical Unit (ALU)?

An arithmetic logic unit (ALU) is a multioperation, combinational- logic unit digital
function. It can perform a set of basic arithmetic operation and a set of logic operation.

2. Explain Accumulator briefly.

• Some processor units separate one register from all other and call it an accumulator
register, abbreviated AC or A register. The name of this register is derived from the
arithmetic addition process encountered in digital computer.
• The accumulator register in a processor unit is a multipurpose register capable of
performing not only the add microoperation, but many other microoperation as well. In
fact, the gates associated with an accumulator register provide all the digital function
found in an ALU.

Input Data

Processor registers
Select
or
B source
Memory unit

A B

ALU

Accumulator
Register (A)

Output Data
3. Which is the fundamental combinational circuit in Arithmetic unit?

Function X Y F Function
Select
S1 S0 Cin
0 0 0 A 0 A Transfer A
0 0 1 A 0 A+1 Increment A
0 1 0 A B A+B Add B to A
0 1 1 A B A+B+1 Add B to A plus 1
1 0 0 A 𝐵̅ A + 𝐵̅ Add 1’s complement of B to A
1 0 1 A 𝐵̅ A + 𝐵̅ + 1 Add 2’s complement of B to A
1 1 0 A All bit 1 A-1 Decrement A
1 1 1 A All bit 1 A Transfer A

4. Draw block diagram of ALU and explain ALU in detail.

• An arithmetic logic unit (ALU) is a multioperation, combinational-logic digital function
It can perform a set of basic arithmetic operations and a set of logic operations. The
ALU has a number of selection lines to select a particular operation in the unit The
selection lines are decoded within the ALU so that k selection variables can specify
up to 2 distinct operations Figure shows the block diagram of a 4-bit ALU The four
data inputs from A are combined with the four inputs from & to generate an operation
at the outputs.
5. Design an adder/Subtractor circuit with one selection variable S and two inputs A
and B. When S=0 the circuit performs the addition operation F=A+B. When S=1 the
circuit performs the subtraction operation F=A–B by taking 2’s complement of B.

S C X Y F S B X-OR
0 0 A B A+B 0 0 0 B
1 1 A 𝐵̅ A + 𝐵̅ + 1 0 1 1
1 0 1 𝐵̅
1 1 0

S Cin

A1 X
FA F1
B1 Y

A2 X
FA F2
B2
Y

A3 X
FA F3
B3
Y

A4 X
FA F4
B4
Y

Cout
6. Design an arithmetic circuit with one selection variable S and two inputs A and B.
When S = 0 the circuit performs the addition operation F=A+B. When S = 1 the
circuit performs the increment operation F=A+1.
S B ̅
𝑺B
S C X Y F
0 0 A B A+B 0 0 0 B
1 1 A 0 A+1 0 1 1
1 0 0 0
1 1 0
S Cin

A1 X
FA F1
B1 Y

A2 X
FA F2
B2
Y

A3 X
FA F3
B3
Y

A4 X
FA F4
B4
Y

Cout
7. Design logical unit which perform (a) AND (b) OR (c) Ex-OR (d) NOT operation on
number A and B.
8. Design Arithmetical unit which perform following operations on two bits numbers
A and B.
(i) Addition of A and B.(A+B)
(ii) Addition of A and B with carry. (A+B+1)
(iii) Subtraction of A and B using 1’s complement method. (A+B’)
(iv) Subtraction of A and B using 2’s complement method. (A+B’+1)
S B X-OR
S C X Y F 0 0 0 B
0 0 A B A+B 0 1 1
0 1 A B A+B+1 1 0 1 𝐵̅
1 0 A 𝐵̅ A + 𝐵̅ 1 1 0
1 1 A 𝐵̅ A + 𝐵̅ + 1

Cin

S Cin

A1 X
FA F1
B1 Y

A2 X
FA F2
B2
Y

A3 X
FA F3
B3
Y

A4 X
FA F4
B4
Y

Cout
9. Design Arithmetical unit which perform following eight operations on two numbers
A and B of two bits. The operations are:
(v) Transfer of A (or A)
(vi) Increment A by 1 (or A+1)
(vii) Addition of A and B. (or A+B)
(viii) Addition of A and B with carry. (or A+B+1)
(ix) Subtraction of A and B using 1’s complement method (or A+B’)
(x) Subtraction of A and B using 2’s complement method (or A+B’+1)
(xi) Decrement A by 1. (or A-1)
(xii) Transfer of A. (or A)
 Refer Question #3….

10. Design an arithmetic circuit with two selection variables, S1 and S0, that generates
the following arithmetic operations. Draw the logic diagram of one typical stage.
S1 S0 Cin=0 Cin=1
0 0 F=A+B F=A+B+1
0 1 F=A F=A+1
1 0 F=B’ F=B’+1
1 1 F=A+B’ F=A+B’+1

Function X Y F
Select
S1 S0 Cin
0 0 0 A B A+B
0 0 1 A B A+B+1
0 1 0 A 0 A
0 1 1 A 0 A+1
1 0 0 0 𝐵̅ 𝐵̅
1 0 1 0 𝐵̅ ̅
𝐵+1
1 1 0 A 𝐵̅ A + 𝐵̅
1 1 1 A 𝐵̅ A + 𝐵̅ + 1

X = A𝑆̅1 + AS1S0
Y = 𝑆̅1 𝑆̅0 B + S1 𝐵̅
 For 1 bit……

Cin
S0
S1

Cin
A
X

FA F
B
Y
Cout
11. What is micro-operation? Enlist the micro-operation performed by accumulator.
• The set of microoperations for the accumulator is given in Table Control variables p,
through p, are generated by control logic circuits and should be considered as control
functions that initiate the corresponding register-transfer operations.
• Register A is a source register in all the listed microoperations. In essence, this
represents the present state of the sequential circuit.
• The B register is used as a second source register for microoperations that need two
operands. The B register is assumed to be connected to the accumulator and
supplies the inputs to the sequential circuit. The destination register for all
microoperations is always register A.
• The new information transferred to A constitutes the next state of the sequential
circuit. The nine control variables are also considered as inputs to the sequential
circuit. These variables are mutually exclusive and only one variable must be
enabled when a clock pulse occurs.
• The last entry in Table is a conditional control statement. It produces a binary I in an
output variable Z when the content of register A is 0, i.e., when all flip-flops in the
register are cleared.
Control variable Microoperation Name
P1 A←A+B Add
P2 A←0 Clear
P3 A ← 𝐴̅ Complement
P4 A←A˄B And
P5 A←A˅B OR
P6 A←A¤B E-OR
P7 A ← A shr B Shift-right
P8 A ← A shl B Shift-left
P9 A←A+1 Increment
If (A = 0) then (Z = 1) Check for zero

12. What is status register?

• The relative magnitudes of two numbers may be determined by subtracting one
number from the other and then checking certain bit conditions in the resultant
difference. If the two numbers are unsigned, the hit conditions of interest are the
output carry and a possible zero result. If the two numbers include a sign bit in the
highest-order position, the bit conditions of interest are the sign of the result, a zero
indication, and an overflow condition. It is sometimes convenient to supplement the
ALU with a status register where these status-bit conditions are stored for further
analysis. Status-bit conditions are sometimes called condition-code bits or flag bits.
• Figure shows the block diagram of an 8-bit ALU with a 4-bit status register. The four
status bits are symbolized by C, S, Z, and V. The bits are set or cleared as a result
of an operation performed in the ALU.

1. Bit Cis set if the output carry of the ALU is 1. It is cleared if the output carry is 0.
2. Bit S is set if the highest-order bit of the result in the output of the ALU (the sign
bit) is 1. It is cleared if the highest-order bit is 0.
3. Bit Z is set if the output of the ALU contains all O's, and cleared otherwise. Z -If
the result is zero, and Z = 0 if the result is nonzero.
 4. Bit V is set if the exclusive-OR of carries C, and C, is 1, and cleared otherwise.
This is the condition for overflow when the numbers are in sign-2's-complement
representation For the 8-bit ALU, V is set if the result is greater than 127 or less
than 128.
• The status bits can be checked after an ALU operation to determine certain
relationships that exist between the values of A and B. Ir bit V is set after the addition
of two signed numbers, it indicates an overflow condition. If Z is set after an exclusive-
OR operation, it indicates that A- B. This is so because x ex- 0, and the exclusive-OR
of two equal operands gives an all-0's result which sets the Z bit. A single bit in A can
be checked to determine if it is 0 or I by masking all bits except the bit in question and
then checking the Z status bit. For example, let A-101 x1100, where x is the bit B-
00010000 produces a result 000x0000. If x-0, the Z status bit is set, but if x-1, the Z
bit is cleared since the result is not zero.

13. Draw and explain use of status register.

• The compare operation is a subtraction of B from A, except that the result of the
operation is not transferred into a destination register, bar the status bits are affected.
The status register then provides the information about the relative magnitudes of A
and B. The status bits to consider depend on whether we take the two numbers to be
unsigned or signed and in 2’s-complement representation.
• Consider the operation A - B done with two unsigned binary numbers. The relative
magnitudes of A and B can be determined from the values transferred to the C and Z
status bits. If Z = 1, then we know that A = B, since A – B = 0. If Z = 0, then we know
that A ≠ B. From Table, we have that C = 1, if A > B and C = 0, if A <B. These
conditions are listed in Table. The table lists two other conditions. For A to be greater
than but not equal to B (A > B), we must have C = 1 and Z = 0 Since C is set when
the result is 0, we must check Z to ensure that the result is not 0. For A to be less than
or equal to B (A < B), the C bit must be 0 (for A < B) or the Z bit must be 1 (for A = the
Boolean functions that must be satisfied for each of the six relationships.
• Some computers consider the C bit to be a borrow bit after a subtraction operation A -
B. An end borrow does not occur if A > B, but an extra bit must be borrowed when A <
B. The condition for a borrow is the complement of the output carry obtained when the
subtraction is done by taking the 2's complement of B. For this reason, a processor
that considers the C bit to be a borrow after a subtraction will complement the C bit
after a subtraction or compare operation and denote this bit as a borrow.

A – B (unsign)
Relation Condition of Status bits Boolean function
A>B C =1 and Z = 0 CZ’
A≥B C=1 C
A<B C=0 C’
A≤B C = 0 or Z =1 C’ + Z
A=B Z=1 Z
A≠B Z =0 Z’

• Now consider the operation A - B done with two signed binary numbers when
negative numbers are in 2's-complement form. The relative magnitudes of A and B
can be determined from the values transferred to the Z, S, and V status bits. If Z = 1,
then we know that A = B; when Z = 0, we have that A + B. If S = 0, the sign of the
result is positive, so A must be greater than B. This is true if there was no overflow
and V = 0. If the result overflows, we obtain an erroneous result. It was shown in
Section 8-5 that an overflow condition changes the sign of the result. Therefore, if S 1
and V = 1, it indicates that the result should have been positive and therefore A must
be greater than B.
• Table lists the six possible relationships that can exist between A and B and the
corresponding values of Z, S, and V in each case. For A-B to be greater than but not
equal to zero (A>B), the result must be positive and nonzero. Since a zero result
gives a positive sign, we must ensure that the Z bit is 0 to exclude the possibility of A
= B. For A> B, it is sufficient to check for a positive sign when no overflow occurs or a
negative sign when an overflow occurs. For A<B, the result must be negative. If the
result is negative or zero, we have that A< B. The Boolean functions listed in the table
express the status-bit conditions in algebraic form.
A – B (sign-2’s Complement)
Relation Condition of Status bits Boolean function
A>B Z = 0 and (S = 0, V= 0 or S = 1, V = 1) Z’ (S ʘ V)
A≥B S = 0, V = 0 or S = 1, V = 1 SʘV
A<B S = 1, V = 0 or S = 0, V = 1 S¤V
A≤B S = 1, V = 0 or S = 0, V = 1 or Z =1 (S ¤ V) + Z
A=B Z=1 Z
A≠B Z =0 Z’
 14. Explain control word format for processor unit.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A B D F Cin H

Binary Function of selection variables

Code A B D F with F with H
Cin = 0 Cin = 1
0 0 0 Input Data Input Data None A, C ← 0 A+1 No shift
0 0 1 R1 R1 R1 A+B A+B+1 Shift-right, IR = 0
0 1 0 R2 R2 R2 A–B–1 A–B Shift-left, IL = 0
0 1 1 R3 R3 R3 A–1 A, C ← 1 0’s to output bus
1 0 0 R4 R4 R4 A˅B - -
1 0 1 R5 R5 R5 A¤B - Circulate-right with C
1 1 0 R6 R6 R6 A˄B - Circulate-left with C
1 1 1 R7 R7 R7 𝐴̅ - -

Example,

Microoperation Control word Function

A B D F Cin H
R1 ← R1 – R2 0 0 1 0 1 0 0 0 1 0 1 0 1 0 0 0 Subtract R2 from R1
R3 – R4 0 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 Compare R3 and R4
R5 ← R4 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 Transfer R4 to R5
R6 ← Input 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 Input data to R6
Output ← R7 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Output data from R7
R1 ← R1,C ← 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 Clear carry bit C
R3 ← shl R3 0 1 1 0 1 1 0 1 1 1 0 0 0 0 1 0 Shift-left R3 with IL=0
R1 ← crc R1 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 1 Circulate-right R1 with carry
R2 ← 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 Clear R2