ReconfigurableComputing

AELZG 554 / MELZG 554 / ES ZG554

Session 9 (Review Session)
Pawan Sharma
BITSPilani [email protected]
Pilani Campus
Today’s Lecture

• Review Session

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PAL

• Implement the following four functions using PAL.

Number of AND gates per OR gate are 3.
– w = ABC’ + A’B’CD’
– x = A + BCD
– y = A’B + CD + B’D’
– z = ABC’ + ACD + A’B’CD’ + ABCD

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BITS Pilani, Pilani Campus
• Show how to implement on two 3-input 2-output
lookup tables the following functions:
– F(x,y,z) = x’y + xyz’ and G(w,x,y,z) = w’x’y + w’xyz’.

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BITS Pilani, Pilani Campus
• Implement a 25 input even parity checker
function using two level LUTs. Choose required
size of LUTs.

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BITS Pilani, Pilani Campus
Q

Implement the two functions using ONLY three 4-input lookup tables. Show what logic
function will be implemented in each of the three lookup tables by giving the logic expression
as a function of its labeled inputs. Use the simplest logic expressions possible for each lookup
table, using AND, OR, and NOT operators. Show how the lookup tables are connected
together.
F = x1.x2.x3.x4.x5.x6
G = x1’x2’x3’x4’x5’x6’
Sol
Q

Small sized LUTs can implement big-sized

functions. Using only 3-input, 1-output lookup tables
(LUTs), implement the circuit using minimum
number of LUTs. Do not simplify the gate-level
circuit before mapping it to LUTs. How many LUTs
are required to implement the design? Using the truth
table approach, show the inputs and output of each
LUT. If any input is not used, mark it as “X”.
Sol
Q
• Deciding on the in-degree or size of the
LUTs has always been a big challenge for
FPGA designers. For the circuit shown in
figure, you have to suggest on appropriate
size and choice of LUTs at each level to
implement the circuit so as to minimize
overall area and delay. You are allowed to
choose different or same sized LUT at each
level. You are given a set of LUTs with
inputs ranging from 2 to 8 to select from.
Each LUT has a single output. The cost
function for the area is given by a relation
“2n + n” and delay by ‘n’ where ‘n’ is the
number of inputs of LUT. Remember, large
fan-in LUTs may not always yield optimal
area and delay. Give proper justification for
the choice you made by computing the
area and delay.

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Q

• The Xilinx FPGA devices contain configurable logic blocks that can
be used to implement any Boolean logic. Let’s explore the
advantages of using CLB over a set of using individual logic gates
for implementing Boolean functions. Assume, there are four CLBs
in the device and each CLB has a 4-LUT that can implement any
function of four inputs. If you were to replace these four CLBs
with two input gates, how many gates will you require? Explain
using an example. (Hint: take an arbitrary four input function and
implement it using a PLA and find maximum possible min terms
that you can generate and compute max fan- in of each AND
gate and OR gate. Then compute how many two input gates (fan-
in of 2) will be required to implement those big AND and OR
gates with large fan-ins.)

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Sol

• The number of gates that are “replaced” by any programmable

logic chip completely depends on the design.
• Each CLB contains four 4-LUTs. Lets try implementing each 4-LUT
with a PLA structure. Each 4-LUT implements a 4-input function
making 16 entries in the truth table. If in K-map, none of the
entries form a pair, then you end up having 8 min terms.
(assuming alternate 1’s and 0’s in truth table output). So each 4-
LUT will require eight 8-input AND gate and one 8-input OR gate.
Each 8-input AND/OR gate requires seven 2-input AND/OR gates.
The total number of 2-input gates per 4-LUT is equal to
8*7+7=63. As there are four 4-LUTs per CLB, so the total number
of 2-input gates per CLB is 4*63=252.

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 Serial adder using SPLD with OE
input
Flip-flop input equation: D = Q(t+1) = xy + xQ + yQ
Output equation: S = x ⊕ y ⊕ Q
S = x’y’Q + x’yQ’ + xyQ + xy’Q’

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SPLD = PAL + D flip flop

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Q.
For the XC4000 CLB, given a possible list of
configurations, indicate how each of the
control signals should be programmed, which
of the input lines (C1-C4, F1-F4, and G1-G4)
are used, and what output lines (X, Y, or Z) the
result(s) appear on.
a. An arbitrary function F of up to four input
variables, plus another arbitrary function G
of up to four unrelated input variables,
plus a third arbitrary function H of up to
three unrelated input variables.
b. An arbitrary single function of five
variables.
c. An arbitrary function of four variables
together with some functions of six
variables. Characterize the functions of
six variables that can be implemented.
d. Some functions of up to nine variables.
Characterize the functions of up to nine
variables that can be implemented.

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Solution

a. An arbitrary function F of up to four input variables, plus another arbitrary function G of up to

four unrelated input variables, plus a third arbitrary function H of up to three unrelated input
variables. Let X = F(F1, F2, F3, F4), Z = G(G1, G2, G3, G4), Y = H(C1, C2, C3). The necessary
control signals are:
MA =1
MB =1
MC = 0 (select C1)
MD = 1 (select C2)
ME = 2 (select C3)

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b. An arbitrary single function of five variables. Let Y = F(A1, A2, A3, A4, A5). This can be implemented using both
4-input logic functions, and selecting between the two outputs with the 3-input logic function.
Z=F(A1, A2, A3, A4, 0),
X=F(A1, A2, A3, A4, 1),
Y= Z if A5=0, else Y=X
So Z is calculating F for the case when A5 = 0, X is calculating F for the case when A5 = 1, and Y is selecting
between X and Z with a multiplexer function. A1-A4 represents F1-F4 and G1-G4 (they're connected to the same 4
inputs) and A5 represents C1. The necessary control signals are:
MA = 0
MB = 0
MC = X (value doesn't matter)
MD = X (value doesn't matter)
ME = 0 (select C1)

A5

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c. An arbitrary function of four variables together with some functions of six variables. Characterize the functions of six variables
that can be implemented. Let Z = G(G1, G2, G3, G4) - any function of 4 variables.
X = F(F1, F2, F3, F4)
Y = H(C1, C2, X) = H(C1, C2, F(F1, F2, F3,F4))
The functions of six variables which can be implemented (along with the 4-variable function) are all those functions that can be re-
written as a function of 3 variables. The inputs to this function of three variables must be 2 of the original variables and some
function of the remaining four variables. The necessary control signals are:
MA =0
MB =1
MC = X (value doesn't matter)
MD = 0 (select C1)
ME = 1 (select C2)

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d. Some functions of up to nine variables. Characterize the functions of up to nine variables that can be implemented. Let
X = F(F1, F2, F3, F4)
Z = G(G1, G2, G3, G4)
Y = H(C1, X, Z) = H(C1, F(F1, F2, F3, F4), G(G1, G2, G3, G4))

The functions of nine variables that can be implemented are all those functions that can be re-written as a function of 3 variables.
The inputs to this three-variable function will be one of the original variables, plus two separate functions of 4 variables (these two
4-variable functions will have the remaining 8 original variables as inputs).
MA =0
MB =0
MC = X (value doesn't matter)
MD = X (value doesn't matter)
ME = 0 (select C1)

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Question

• Map the following functions to the PLA below:

– W = AB + A’C’ + BC’ A B C

– X = ABC + AB’ + A’B

– Y = ABC’ + BC + B’C’

W X Y

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 Solution
9 terms won’t fit in a 7 term PLA
can apply concensus theorem to W to simplify to:

W = AB + A’C’
A B C
Consensus theorem states:
ABC
XY + X’Z + YZ = XY +X’Z
ABC’
The YZ term is called the consensus term and is
redundant. The consensus term is formed from a A’C’
PAIR OF TERMS in which a variable (X) and its
complement (X’) are present; the consensus term AB’
is formed by multiplying the two terms and
leaving out the selected variable and its A’B
complement.
The consensus of XY, X’Z is YZ BC
8 terms wont’ fit in a 7 term PLA
observe that AB = ABC + ABC’ B’C’
can rewrite W to reuse terms:

W = ABC + ABC’ + A’C’

Now it fits
W = ABC + ABC’ +A’C’ W X Y
X = ABC + AB’ +A’B
Y = ABC’ + BC + B’C’

21
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 Question
Show how the function

w1w3’ + w1’w3 + w2w3’ + w1w2’w3

can be realized using Act 1 logic blocks.

Note that there are no NOT gates in the
chip; hence complements of signals have to
be generated using the multiplexers in the
logic block.

Act1 Logic Module: It is a multiplexer-based logic module. Logic functions are implemented by interconnecting signals from the routing
tracks to the data inputs and select lines of the multiplexers. Inputs can also be tied to a logical 1 or 0 if required, since these signals are
always available in the routing channel. A surprising number of useful logic functions can be implemented with this module. Clearly,
multiplexing is very efficient, but random logic and sequential logic functions are also efficient. These options provide the designer with
an excellent mix of logic capabilities, required for applications demanding a variety of logic functions

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Solution

F = A’B + ABC’ + A’B’C

Using Shannon expansion, F can be expressed as:

F = A (A’B + ABC’ + A’B’C) + A’ (A’B + ABC’ + A’B’C) A

F = ABC’ + A’B + A’B’C
F = A (BC’) + A’ (B + C)
F1
0
F
F2
1

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 MUX
0
1

F1 = B . C F2 = B + C Control
These functions can be broken down further into:
F1 = B ( B . C ) + B ( B . C )

= B . C + B.0
C Overall Function
0 F2
F1 1 F
C B
B A

F2 = B ( B + C ) + B ( B + C)
0
= B . 1 + B .C F1
C
C B
F2
1
B

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Therefore 2-1 multiplexer is a general block that can represent any gate:
AND Gate OR Gate Ex-OR
F =A.B F =A. B + A. B
F =A(A+ B ) +A’(A+ B )
F =A. (A. B ) +A(A. B ) =A+AB +A’. B
=A. 1 +A’. B
=A. B + A. 0
B B
0 C
F F
1 B
B
A A
A

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F=W1W3’+W1’W3+W2W3’+W1W2’W3
F=W3’(W1+W2) + W3(W1’+ W1W2’)

W1+W2=W1(W1+W2) + W1’(W1+W2) W1.1 + W1’(W2)

W1+W2=W1.1 + W1’(W2)

W1’ + W1W2’

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Question

F = A.B + B’.C + D
= B [A.B + B’.C + D] + B’[A.B + B’.C + D]
= A.B + B.D + B’.C + B’.D
D

= B.(A+D) + B’ (C+D) ‘1’

0
1
F1
0
1
F

M2
D 0
Implement using Act 1 logicmodule ‘1’ 1
F2
A

‘0’ O1
B

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Question

• Consider the function

– f (x1, x2, x3) = x1x2’ + x1x3 + x2x3’ .
• Show a circuit using two-input lookup-tables
(LUTs) to implement this expression. Give the
truth table implemented in each LUT. You do not
need to show the wires in the FPGA

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Solution

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 x1x3
+x2x3’

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Implement the following functions on a single CLB of the XC4000FPGA:
• X = A’B’ (C + D)
• Y = A’B’CK + A’B’DK + AEJLK’

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 X = A’B’ (C + D)
Y = A’B’CK + A’B’DK + AEJLK’

Use look up table F to implementX

Use look up table G for AEJL
Use F, G and H for Y:
A Y = KF+K’G
E
J 1
L K

A
B 1

C
D

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Implementation

REGISTERED ‘Y’
OUTPUT IFNEEDED

REGISTERED ‘X’
OUTPUT IFNEEDED

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Using only 4-input lookup tables (LUTs), partition the circuit shown below into as few LUTs as
possible. Do not attempt to simplify the gate-level circuit before mapping it to LUTs. Indicate
your answer by drawing boundaries around your partitions.

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