6.

INSTRUCTION EXECUTION AND TIMING DIAGRAM:

Each instruction in 8085 microprocessor consists of two part- operation code (opcode) and
operand. The opcode is a command such as ADD and the operand is an object to be
operated on, such as a byte or the content of a register.

Instruction Cycle: The time taken by the processor to complete the execution of an
instruction. An instruction cycle consists of one to six machine cycles.

Machine Cycle: The time required to complete one operation; accessing either the memory
or I/O device. A machine cycle consists of three to six T-states.

T-State: Time corresponding to one clock period. It is the basic unit to calculate execution
of instructions or programs in a processor.

To execute a program, 8085 performs various operations as:

Opcode fetch
Operand fetch
Memory read/write
I/O read/write

External communication functions are:

Memory read/write
I/O read/write
Interrupt request acknowledge

Opcode Fetch Machine Cycle:

It is the first step in the execution of any instruction. The timing diagram of this cycle is
given in Fig. 7.

The following points explain the various operations that take place and the signals that are
changed during the execution of opcode fetch machine cycle:

T1 clock cycle

i. The content of PC is placed in the address bus; AD0 - AD7 lines contains lower bit
address and A8 A15 contains higher bit address.
ii. IO/M signal is low indicating that a memory location is being accessed. S1 and S0
also changed to the levels as indicated in Table 1.
iii. ALE is high, indicates that multiplexed AD0 AD7 act as lower order bus.

T2 clock cycle

i. Multiplexed address bus is now changed to data bus.

ii. The RD signal is made low by the processor. This signal makes the memory device
load the data bus with the contents of the location addressed by the processor.
T3 clock cycle

i. The opcode available on the data bus is read by the processor and moved to the
instruction register.
ii. The RD signal is deactivated by making it logic 1.

T4 clock cycle

i. The processor decode the instruction in the instruction register and generate the
necessary control signals to execute the instruction. Based on the instruction further
operations such as fetching, writing into memory etc takes place.

Fig. 7 Timing diagram for opcode fetch cycle

Memory Read Machine Cycle:

The memory read cycle is executed by the processor to read a data byte from memory. The
machine cycle is exactly same to opcode fetch except: a) It has three T-states b) The S0
signal is set to 0. The timing diagram of this cycle is given in Fig. 8.
 Fig. 8 Timing diagram for memory read machine cycle

Memory Write Machine Cycle:

The memory write cycle is executed by the processor to write a data byte in a memory
location. The processor takes three T-states and WR signal is made low. The timing
diagram of this cycle is given in Fig. 9.

I/O Read Cycle:

The I/O read cycle is executed by the processor to read a data byte from I/O port or from
peripheral, which is I/O mapped in the system. The 8-bit port address is placed both in the
lower and higher order address bus. The processor takes three T-states to execute this
machine cycle. The timing diagram of this cycle is given in Fig. 10.
Fig. 9 Timing diagram for memory write machine cycle

Fig. 10 Timing diagram I/O read machine cycle

I/O Write Cycle:

The I/O write cycle is executed by the processor to write a data byte to I/O port or to a
peripheral, which is I/O mapped in the system. The processor takes three T-states to execute
this machine cycle. The timing diagram of this cycle is given in Fig. 11.

Fig. 11 Timing diagram I/O write machine cycle

Ex: Timing diagram for IN 80H.

The instruction and the corresponding codes and memory locations are given in Table 5.

Table 5 IN instruction

Address Mnemonics Opcode

800F IN 80H DB
8010 80

i. During the first machine cycle, the opcode DB is fetched from the memory, placed
in the instruction register and decoded.
ii. During second machine cycle, the port address 80H is read from the next memory
location.
iii. During the third machine cycle, the address 80H is placed in the address bus and the
data read from that port address is placed in the accumulator.

The timing diagram is shown in Fig. 12.

 Fig. 12 Timing diagram for the IN instruction

7. 8085 INTERRUPTS

Interrupt Structure:

Interrupt is the mechanism by which the processor is made to transfer control from its
current program execution to another program having higher priority. The interrupt signal
may be given to the processor by any external peripheral device.

The program or the routine that is executed upon interrupt is called interrupt service routine
(ISR). After execution of ISR, the processor must return to the interrupted program. Key
features in the interrupt structure of any microprocessor are as follows:

i. Number and types of interrupt signals available.

ii. The address of the memory where the ISR is located for a particular interrupt signal.
This address is called interrupt vector address (IVA).
iii. Masking and unmasking feature of the interrupt signals.
iv. Priority among the interrupts.
v. Timing of the interrupt signals.
vi. Handling and storing of information about the interrupt program (status
information).

Types of Interrupts:

Interrupts are classified based on their maskability, IVA and source. They are classified as:
 i. Vectored and Non-Vectored Interrupts
Vectored interrupts require the IVA to be supplied by the external device that
gives the interrupt signal. This technique is vectoring, is implemented in
number of ways.
Non-vectored interrupts have fixed IVA for ISRs of different interrupt
signals.
ii. Maskable and Non-Maskable Interrupts
Maskable interrupts are interrupts that can be blocked. Masking can be done
by software or hardware means.
Non-maskable interrupts are interrupts that are always recognized; the
corresponding ISRs are executed.
iii. Software and Hardware Interrupts
Software interrupts are special instructions, after execution transfer the
control to predefined ISR.
Hardware interrupts are signals given to the processor, for recognition as an
interrupt and execution of the corresponding ISR.

Interrupt Handling Procedure:

The following sequence of operations takes place when an interrupt signal is recognized:

i. Save the PC content and information about current state (flags, registers etc) in the
stack.
ii. Load PC with the beginning address of an ISR and start to execute it.
iii. Finish ISR when the return instruction is executed.
iv. Return to the point in the interrupted program where execution was interrupted.

Interrupt Sources and Vector Addresses in 8085:

Software Interrupts:

8085 instruction set includes eight software interrupt instructions called Restart (RST)
instructions. These are one byte instructions that make the processor execute a subroutine at
predefined locations. Instructions and their vector addresses are given in Table 6.

Table 6 Software interrupts and their vector addresses

Instruction Machine hex code Interrupt Vector Address

RST 0 C7 0000H
RST 1 CF 0008H
RST 2 D7 0010H
RST 3 DF 0018H
RST 4 E7 0020H
RST 5 EF 0028H
RST 6 F7 0030H
RST 7 FF 0032H
The software interrupts can be treated as CALL instructions with default call locations. The
concept of priority does not apply to software interrupts as they are inserted into the
program as instructions by the programmer and executed by the processor when the
respective program lines are read.

Hardware Interrupts and Priorities:

8085 have five hardware interrupts INTR, RST 5.5, RST 6.5, RST 7.5 and TRAP. Their
IVA and priorities are given in Table 7.

Table 7 Hardware interrupts of 8085

Interrupt Interrupt vector Maskable or non- Edge or level priority

address maskable triggered
TRAP 0024H Non-makable Level 1
RST 7.5 003CH Maskable Rising edge 2
RST 6.5 0034H Maskable Level 3
RST 5.5 002CH Maskable Level 4
INTR Decided by hardware Maskable Level 5

Masking of Interrupts:

Masking can be done for four hardware interrupts INTR, RST 5.5, RST 6.5, and RST 7.5.
The masking of 8085 interrupts is done at different levels. Fig. 13 shows the organization of
hardware interrupts in the 8085.

Fig. 13 Interrupt structure of 8085

The Fig. 13 is explained by the following five points:

 i. The maskable interrupts are by default masked by the Reset signal. So no interrupt is
recognized by the hardware reset.
ii. The interrupts can be enabled by the EI instruction.
iii. The three RST interrupts can be selectively masked by loading the appropriate word
in the accumulator and executing SIM instruction. This is called software masking.
iv. All maskable interrupts are disabled whenever an interrupt is recognized.
v. All maskable interrupts can be disabled by executing the DI instruction.

RST 7.5 alone has a flip-flop to recognize edge transition. The DI instruction reset interrupt
enable flip-flop in the processor and the interrupts are disabled. To enable interrupts, EI
instruction has to be executed.

SIM Instruction:

The SIM instruction is used to mask or unmask RST hardware interrupts. When executed,
the SIM instruction reads the content of accumulator and accordingly mask or unmask the
interrupts. The format of control word to be stored in the accumulator before executing SIM
instruction is as shown in Fig. 14.

Fig. 14 Accumulator bit pattern for SIM instruction

In addition to masking interrupts, SIM instruction can be used to send serial data on the
SOD line of the processor. The data to be send is placed in the MSB bit of the accumulator
and the serial data output is enabled by making D6 bit to 1.

RIM Instruction:

RIM instruction is used to read the status of the interrupt mask bits. When RIM instruction
is executed, the accumulator is loaded with the current status of the interrupt masks and the
pending interrupts. The format and the meaning of the data stored in the accumulator after
execution of RIM instruction is shown in Fig. 15.

In addition RIM instruction is also used to read the serial data on the SID pin of the
processor. The data on the SID pin is stored in the MSB of the accumulator after the
execution of the RIM instruction.
 Fig. 15 Accumulator bit pattern after execution of RIM instruction

Ex: Write an assembly language program to enables all the interrupts in 8085 after reset.

EI : Enable interrupts

MVI A, 08H : Unmask the interrupts

SIM : Set the mask and unmask using SIM instruction

Timing of Interrupts:

The interrupts are sensed by the processor one cycle before the end of execution of each
instruction. An interrupts signal must be applied long enough for it to be recognized. The
longest instruction of the 8085 takes 18 clock periods. So, the interrupt signal must be
applied for at least 17.5 clock periods. This decides the minimum pulse width for the
interrupt signal.

The maximum pulse width for the interrupt signal is decided by the condition that the
interrupt signal must not be recognized once again. This is under the control of the
programmer.