Scribd
Upload
44 views32 pages

3.design With Vivado

Uploaded by

aho
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
44 views32 pages

3.design With Vivado

Uploaded by

aho
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 32

DEPARTMENT OF ELECTRICAL &ELECTRONICS ENGINEERING

DIGITAL DESIGN
Dr. Alper SARIKAN
Spring 2023
OUTLİNE

○ Digilent Basys3
○ Project Creation
○ Design
○ Elaborating
○ Simulation
○ Implementation
○ Real-Time Operation

Design with Vivado 2


DİGİLENT BASYS3

○ Xilinx Artix-7™ Family


○ Free of charge Xilinx WebPACK™ license

Design with Vivado 3


DİGİLENT BASYS3

○ 1: Power good LED ○ 10: Programming mode


○ 2: PMOD Connector jumper
○ 3: Analog signal PMOD ○ 11: USB Host Connector
Connector ○ 12: USB Host Busy LED
○ 4: Seven-Segment Display ○ 13: VGA Connector
○ 5: Slide Switches ○ 14: Micro-USB for
○ 6: LEDs programming, power, UART
○ 7: Push Buttons ○ 15: Optional 5V external
power supply input
○ 8: FPGA Programming done
LED ○ 16: Power Switch
○ 9: FPGA Configuration ○ 17: Power Select Switch
Reset Button
Design with Vivado 4
CREATE NEW PROJECT

○ Vivado Design Environment


● At the first time startup
window opens
● After that last project will be
loaded automatically
○ Startup Window
● Divided into three parts
● Quick Start
● Tasks
● Information Center

Design with Vivado 5


CREATE NEW PROJECT

○ Create New Project wizard helps for initial creation of a


project

Design with Vivado 6


CREATE NEW PROJECT

○ Select RTL Project for new projects


○ Select target language either VHDL or Verilog

Design with Vivado 7


CREATE NEW PROJECT

○ VHDL or Verilog design file


can also be added after this
step.

Design with Vivado 8


CREATE NEW PROJECT

○ Click Next at “Add Existing IP”


○ Default constraint file can be downloaded from Digilent
website.

Design with Vivado 9


CREATE NEW PROJECT

○ Basys3_Master.xdc constraint file contains information


regarding to I/O connections and etc.
○ Basys3 FPGA is “xc7a35tcpg236-1”

Design with Vivado 10


CREATE NEW PROJECT

○ After the “New Project Summary”, define module window


opens.
○ I/O information of modules can also be entered after this
step

Design with Vivado 11


VİVADO MAİN WİNDOW

Design with Vivado 12


DESİGN ENTRY

○ VHDL or Verilog design is entered using


text editor.
○ Physical connections of input and output
is defined in the constraint file.
○ For example, V17 pin is connected to the
sw(0) on the PCB. This connection can
not be changed by software. To change
this connection, the PCB must be
redesigned.

Design with Vivado 13


ELABORATE

○ RTL code is converted to


hardware using generic
cells, such as registers,
adders, comparators.
○ The generated netlist is
technology independent.
○ No logic optimization is
performed.
○ Constraints are applied to
this generated netlist.
○ Synthesis always starts with
elaboration.

Design with Vivado 14


SİMULATİON

○ Simulation is used to check the operation of a physical


system using its mathematical model.
○ During simulation the system is not built physically, so any
mistake only costs time.
○ The functionality of any system must be checked using
simulation.
○ If any system does not meet specification during simulations,
it does not meet specification after realizations.
○ All HDL based system must be verified using simulations
regardless of the system complexity.

Design with Vivado 15


SİMULATİON

Design with Vivado 16


SİMULATİON

Design with Vivado 17


SİMULATİON

Design with Vivado 18


SİMULATİON

Design with Vivado 19


SİMULATİON

○ Testbench applies signals to


inputs to test the operation.

Design with Vivado 20


SİMULATİON

Design with Vivado 21


SİMULATİON

○ Simulation shows signals with respect to time.


○ Inputs and corresponding outputs are drawn.

Design with Vivado 22


IMPLEMENTATİON

Design with Vivado 23


IMPLEMENTATİON

○ Synthesis ○ Place & Route


● Elaborate ➔ Netlist ● Placement
● Apply Design Constraints ○ Timing driven
○ Optimization
● High Level Optimization
○ Rewiring
○ Algorithm optimization
○ Register Combining ● Routing
○ And etc. ○ Global signal routing
● Clocks, reset, I/O
● Technology Mapping
○ Data signal routing
● Low Level Optimization
○ Power optimization
○ Timing optimization

Design with Vivado 24


POST IMPLEMENTATİON TİMİNG
SİMULATİON

Design with Vivado 25


POST IMPLEMENTATİON TİMİNG
SİMULATİON
○ Cell delays and routing delays are taken into account.
○ Most accurate simulation ➔ Close to physical performance

Design with Vivado 26


STATİC TİMİNG ANALYSİS

○ Checking all setup-hold


time violations using
simulation is impossible.
○ Static timing analyzer
checks setup and hold
slacks automatically.

Design with Vivado 27


BİTSTREAM GENERATİON

○ Bitstream is the data file that have the connection


information among the FPGA internal circuits
○ Hardware Manager is used to load the bit data file to the
FPGA. It is also used for debugging purposes.

Design with Vivado 28


REAL-TİME OPERATİON

Design with Vivado 29


REAL-TİME OPERATİON

Design with Vivado 30


REAL-TİME OPERATİON

Design with Vivado 31


REAL-TİME OPERATİON

Design with Vivado 32

You might also like