Lecture # 7

Engr. Dr. Muhammad Aqeel Aslam

Department of Electrical Engineering Assistant Professor
GIFT University, Gujranwala
Pakistan
GIFT University, Gujranwala

Digital Systems Design EE - 417

 FPGA Architecture
• Available choice for digital designer
• FPGA – A detailed look
• Interconnection Framework
 FPGAs and CPLDs
• Field programmability and programming technologies
 SRAM, Anti-fuse, EPROM and EEPROM
• Design steps
• Commercially available devices
I. Xilinx XC4000
II. Altera MAX 5000

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 Designer’s Choice
 Digital designer has various options
 SSI (small scale integrated circuits) or MSI (medium
scale integrated circuits) components
 Difficulties arises as design size increases
 Interconnections grow with complexity resulting in a prolonged
testing phase
 Simple programmable logic devices
 PALs (programmable array logic)
 PLAs (programmable logic array)
 Architecture not scalable; Power consumption and delays play an
important role in extending the architecture to complex designs
 Implementation of larger designs leads to same difficulty as that
of discrete components
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 Designer’s Choice
Quest for high capacity; Two choices available
 MPGA (Masked Programmable Logic Devices)
Customized during fabrication
Low volume expensive
Prolonged time-to-market and high financial risk
 FPGA (Field Programmable Logic Devices)
Customized by end user
Implements multi-level logic function
Fast time to market and low risk

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 FPGA – A Quick Look
 Two dimensional array of customizable logic block
placed in an interconnect array
 Like PLDs programmable at users site
 Like MPGAs, implements thousands of gates of logic
in a single device
 Employs logic and interconnect structure capable of
implementing multi-level logic
 Scalable in proportion with logic removing many of the size
limitations of PLD derived two level architecture
 FPGAs offer the benefit of both MPGAs and PLDs!
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 FPGA – A Detailed Look
 Based on the principle of functional completeness
 FPGA: Functionally complete elements (Logic
Blocks) placed in an interconnect framework
 Interconnection framework comprises of wire
segments and switches; Provide a means to
interconnect logic blocks
 Circuits are partitioned to logic block size, mapped
and routed
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 A Fictitious FPGA Architecture
(With Multiplexer As Functionally Complete Cell)
 Basic building block

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 Interconnection Framework
 Granularity and interconnection structure has
caused a split in the industry
 FPGA
 Fine Grained
 Variable Length interconnect segments
 Timing in general is not predictable;
Timing extracted after placement and
route

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 Interconnection Framework
 CPLD
–Coarse grained
(SPLD like blocks)
–Programmable crossbar
interconnect structure
–Interconnect structure
uses continuous metal lines
–The switch matrix may or
may not be fully populated
–Timing predictable if fully
populated
–Architecture does not
scale well

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 Field Programmability
 Field programmability is achieved through switches
(Transistors controlled by memory elements or fuses)
 Switches control the following aspects
 Interconnection among wire segments
 Configuration of logic blocks
 Distributed memory elements controlling the switches and
configuration of logic blocks are together called
“Configuration Memory”

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 Technology of Programmable Elements
 Vary from vendor to vendor. All share the common
property: Configurable in one of the two positions –
‘ON’ or ‘OFF’
 Can be classified into three categories:
 SRAM based
 Fuse based
 EPROM/EEPROM/Flash based
 Desired properties:
 Minimum area consumption
 Low on resistance; High off resistance
 Low parasitic capacitance to the attached wire
 Reliability in volume production 11
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 FPGA Implementation of Modulo-4 Counter

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 Design Steps Involved in Designing With FPGAs
 Understand and define design
requirements
 Design Description
 Behavioral Simulation (Source Code
Implementation)
 Synthesis
 Functional or Gate-Level Simulation
 Implementation
 Fitting
 Place and Route
 Timing or Post Layout Simulation
 Programming, Test and Debug

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 Taxanomy of FPGAs

FPGA

SRAM EPROM
Programmed Antifuse Programmed Programmed
channeled Array

Island Cellular

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 FPGA/ASIC Crossover Changes

Cost

FPGA Cost Advantage

Production Volume

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 Commercially Available Devices
 Architecture differs from vendor to vendor
 Characterized by
 Structure and content of logic block
 Structure and content of routing resources
 To examine, look at some of available devices
 FPGA: Xilinx (XC4000)
 CPLD: Altera (MAX 5K)

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 Xilinx FPGAs
 Symmetric Array based; Array  Generic Xilinx Architecture
consists of CLBs with LUTs and D-
Flip-Flops
 N-input LUTs can implement any
n-input Boolean function
 Array embedded within the
periphery of IO blocks
 Array elements interleaved with
routing resources (wire segments,
switch matrix and single
connection points)
 Employs SRAM technology

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 XC 4000
 3 LUTs and 2 Flip-flops in a two  XC 4000
stage arrangement
 2 Outputs: Can be registered or
combinational
 External signals can also be
registered
 More of internal signals are
available for connections
 Can implement any two
independent functions of four
variables or any single function of
five variables

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 XC 4000
 XC4000 Routing Architecture

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 XC 4000
 XC4000 Routing Architecture
 Wire segments
 Single length lines
 Spans single CLB
 Connects adjacent CLBs
 Used to connect signals that do not have critical timing requirements
 Double length lines
 Spans two CLBs
 Uses half as much switch as a single length connection
 Long lines
 Low skew; Used for signals such as clock
 Relatively rare resource
 Switch Matrix
 Every line is connected to lines on the other three direction
 Each connection requires six transistors

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