Flipchip Implementation—

Peripheral IO Application Note

Product Version Innovus18.1
July, 2018
Copyright Statement

© 2018 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the
Cadence logo are registered trademarks of Cadence Design Systems, Inc. All others are the
property of their respective holders.

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Contents

Purpose ............................................................................. 5
Audience ........................................................................... 5
Acronym List...................................................................... 5
1. Introduction to Flipchip Methodology ............................. 6
1.1 Implementation Methodologies ........................................................................... 6
1.1.1 Peripheral IO ................................................................................................... 6
1.1.2 Area IO ............................................................................................................ 7
1.1.3 Mix Peripheral IO and Area IO ........................................................................ 8
1.2 Flow Methodologies ............................................................................................... 8
1.2.1 Innovus driven floorplaning ............................................................................. 8
1.2.2 Package-driven floorplaning ............................................................................ 9
1.2.3 Co-Design driven floorplaning ......................................................................... 9
2. Innovus Tool Introduction ............................................ 11
3. Data preparation .......................................................... 12
3.1 LEF ...................................................................................................................... 12
3.1.1 RDL layer ...................................................................................................... 12
3.1.2 BUMP ............................................................................................................ 12
3.1.3 IO pad ........................................................................................................... 14
3.1.4 Hard macro ................................................................................................... 14
3.1.5 CLASS BUMP Attribute ................................................................................. 15
3.2 NETLIST .............................................................................................................. 21
3.2.1 Signal pads ................................................................................................... 21
3.2.2 Power and ground pads ................................................................................ 22
4. Flipchip Floorplaning ................................................... 24
4.1 Peripheral IO placement and die size setting ...................................................... 24
4.2 Bump creation and assignment ........................................................................... 30
4.2.1 Bump creation ............................................................................................... 30
4.2.2 Bump assignment ......................................................................................... 34
4.2.3 Port numbering approach in assignment ....................................................... 40
4.3 Bump Assignment Optimization ........................................................................... 43
4.3.1 Automatic bump assignment optimization ..................................................... 43
4.3.2 Manual bump assignment optimization ......................................................... 45
4.4.3 Use Bump Assignment Constraint ................................................................ 46

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4.4 IO PAD Optimization............................................................................................ 56

5. Power Planning ........................................................... 58
6. RDL Routing ................................................................ 61
6.1 Introduction .......................................................................................................... 61
6.2 Useful constraints for flipchip routing ................................................................... 66
6.2.1 Global Constraints ......................................................................................... 66
6.2.2 SPLIT Constraint ........................................................................................... 68
6.2.3 NETS Constraint ........................................................................................... 70
6.2.4 Differential Routing Constraint ...................................................................... 71
6.2.5 Match Routing Constraint .............................................................................. 73
6.2.6 Shielding Routing Constraint ......................................................................... 73
6.2.7 PAIR Constraint ............................................................................................ 76
6.2.8 Resistance Driven Constraint ........................................................................ 78
6.3 Useful extra configurations for flipchip routing ..................................................... 79
6.4 Power Routing ..................................................................................................... 80
6.4.1 PG bumps connect to IO pads ...................................................................... 80
6.4.2 PG bumps connect to rings or stripes ........................................................... 81
6.5 P2P router ........................................................................................................... 83
6.6 Wire editing.......................................................................................................... 87
7. Conclusions ................................................................. 90

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Purpose
This document is targeted to users who want to create an initial flipchip floorplan using
Innovus (Innovus™ Implementation System). It will describe the different
methodologies and Cadence Design Systems, Inc. recommendations for a successful
chip implementation.

Audience
The document is intended for users with and without experience in Innovus™
Implementation System Flipchip. It will describe in detail the flow involved in the
implementation of a peripheral IO flipchip.

Acronym List
Acronym Full version
SiP System in Package
Innovus Innovus™ Implementation System
RDL Redistribution Layer (metal routing)
IOP IO Planner based on Innovus technology
Pkg abbreviation for package
PCB Printed Circuit Board
DEF design exchange format
LEF library exchange format
OA Open Access database
PIO Peripheral IO
AIO Area IO
HM Hard Macros
fcroute Flip Chip Route
EPS Encounter Power System
CPF Common Power Format
GUI Graphical User Interface
ECO Engineering Change Order
APD Allegro Package Designer
P2P Point to point
PG Power and ground
SI Signal Integrity
TSV Through silicon via

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1. Introduction to Flipchip Methodology

1.1 Implementation Methodologies

1.1.1 Peripheral IO

IO PADs are placed on the periphery of the die. If the design is severely pad limited it
could have multiple IO rings around the core area. The pin of the pad is routed to the
bumps using the RDL layer. These bumps are located in the core area of the chip. This is
essentially what a peripheral design looks like.

Example of a peripheral IO design

The recommendation is to floorplan the design including the bump location,

assignment and RDL routing. The benefit is that the designer can take the advantage
of having more freedom when moving IO pads and bumps. Moving IO pads that are not
related to analog blocks can be feasible at this stage. Bump movement needs to be
verified for routing purposes in SiP. SiP will verify that there is no routing congestion
between bumps and package balls using the current bump assignment.

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It is not recommended to implement the flipchip features as a post process after design
closure. During full chip implementation, the designer could choose not to use the RDL
layer for signal or power routing and reserve this layer for the flipchip router. In this case
the bump assignment and routing can be performed in parallel to the implementation
flow or as a post step after final timing signoff. This methodology restricts the movement
of the IO pads as they are fixed after implementing the design closure flow. In addition,
the package tool (SiP) can limit the bump location. In this case is common to face routing
congestion and hotspots.

A peripheral IO design has no impact on the default timing/area/power/DFM-DFY closure

implementation flow.

This application note will focus on the peripheral IO methodology only.

1.1.2 Area IO

In this type of design, the IO PADs are placed in the core area. The user will define IO
pad row clusters in the core where these IO pads will be placed and routed from. With
this implementation, the routing is much less constrained and rarely do routing
congestion issues arise. The bumps can be defined and placed close to the IO pads
shortening the net length.

The disadvantage of this methodology is that the IO pad placement affects the standard
cell placement and therefore the full timing closure flow. The power routing is also more
demanding in this implementation as dedicated power stripes must be routed to feed the
power requirement for the IOs.

In general, this implementation style is more complex but offers much less net delay from
IO pad to the bump. In addition, the SI effect is greatly reduced as the net length is much
shorter.

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Example of an area IO design

1.1.3 Mix Peripheral IO and Area IO

The design uses the above two methodologies during implementation. There could be
some signals with tight constraints in net delay, which can be candidates for the area IO
methodology. The other signals can be implemented in the periphery. These designs
share the advantages and disadvantages of the methodologies already described.

1.2 Flow Methodologies

The design of an IC and its package/carrier has traditionally been two separate
development processes done in succession (Serial Design Flow), driven from a common
specification.

1.2.1 Innovus driven floorplaning

The digital implementation engineer has an initial and rough floorplan to start with, for
example:
• The size of the chip might be given as a constraint from marketing or from the
customer.
• The location and ordering of some or all the I/O’s may already be known. This
information may come from the PCB or package designer, or there may be some
inherent placement requirements imposed by an analog block in the core.

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All this information can be fed into Innovus during the implementation. In this case,
Innovus can drive the flipchip implementation by placing these PADs and then creating
and assigning the bumps. After this implementation, the design needs to go to SiP
Layout (Cadence’s package implementation tool) to verify that the bump placement can
be routed to the package balls. This is becoming very critical as users are trying to
reduce the size of the package which is limiting the routing resources.

This application note will describe this flow methodology.

1.2.2 Package-driven floorplaning

In this case the bump creation and assignment are driven by the package tool and by the
constraints from the PCB. This information is fed into Innovus to drive the IO pad
placement. In this flow, the I/O pad and bump planning needs to be done before much of
the digital implementation steps, as the bump assignment is driven by package
requirements. Once the placement of these IOs is fixed the digital implementation in
Innovus can start. There will be no need to come back to SiP to check the bump
assignment as these should not have been modified during the design closure steps.
The downside of this approach is that the package engineer does not have knowledge of
the limitations and constraints coming from the logic in the design. It is probable that
analog blocks have specific placement constraints, which drive the pad placement and
therefore the bump assignment.

1.2.3 Co-Design driven floorplaning

This is the best method to achieve a quick compromise between the digital
implementation and the package/PCB board design.

The advantage is that one engineer can move between the digital implementation and
the package implementation by using SiP Layout and Innovus. This methodology allows
the engineer to see IO pads and bumps by die abstract file in Sip Layout System and by
IO file in Innovus which can help to achieve a quicker floorplaning closure.

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High-level flow diagram for co-design

In the above flow chart graphic, the starting point in the flow is Innovus. However, the
methodology is flexible enough for the engineer to choose whatever tool, Innovus or SiP
Layout as the starting point. Once the compromise between the two design domains is
achieved in terms of routing feasibility, designers in two domains can work on their own
design issue separately and in parallel

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2. Innovus Tool Introduction

Innovus delivers a complete solution for variation- and manufacturing-aware design
closure, low power, mixed-signal implementation, and integrated signoff in a single,
scalable multi-CPU-enabled design environment for high-capacity, high- performance
digital implementation. This application note will focus on a limited feature set from
Innovus mostly revolving around the “Flip Chip” feature set.

Innovus was initially created as a physical tool and as such the minimum data required to
start implementing a design in Innovus are

• A valid Verilog netlist

• LEF files describing the technology to use, which need to be read in first, followed
by the physical description of all the instances described in the netlist - both
standard cells and hard macros (HM). A LEF description of the bump macro will
also be needed.

However, if the user would like to have a more meaningful and realistic floorplaning
result it is advisable to add timing and power information into the database. In this case
there are several files required:

• Timing libraries for all the cells in the design – libs

• Timing constraints in SDC or PT format.
• RC extraction libraries - captables, QRC tech file, …
• Power analysis libraries - .cl for Voltus™

Innovus provides a full solution for users who want to implement a flipchip design using
all the implementation methodologies described previously, peripheral IO, area IO or a
mixed methodology.

It offers a full bump and IO pad optimization based of global routing results. The routing
can be implemented in Manhattan or 45 degree fashion. Innovus also offers the
possibility for the user to use specific routing constraints like differential routing, shielding,
splitting, etc.

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3. Data preparation

3.1 LEF
Innovus relies on the LEF files to identify the bumps cells and flipchip pads. The cells
involved in a flipchip design must have the corresponding keywords.

3.1.1 RDL layer

The definition of RDL layer for flipchip flow is similar as other layers’ in LEF. One
example is as below,
LAYER metalRDL
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 0.800 ;
OFFSET 0.100 ;
HEIGHT 3.7350 ;
THICKNESS 0.9000 ;
MINSTEP 0.400 ;
FILLACTIVESPACING 0.600 ;
WIDTH 0.400 ;
MAXWIDTH 12.0 ;
SPACINGTABLE
PARALLELRUNLENGTH 0.00 1.50 4.50
WIDTH 0.00 0.40 0.40 0.40
WIDTH 1.50 0.40 0.50 0.50
WIDTH 4.50 0.40 0.50 1.50 ;
AREA 0.565 ;
MINENCLOSEDAREA 0.565 ;
…
END metalRDL

3.1.2 BUMP

The macro type of BUMP cells need to be CLASS COVER BUMP. This is an example of
a bump cell,

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MACRO BUMPCELL
CLASS COVER BUMP ;
ORIGIN 0 0 ;
SIZE 60.0 BY 60.0 ;
SYMMETRY X Y ;
PIN PAD
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M9 ;
POLYGON 17.25 0.0 42.75 0.0 60.0 17.25 60.0 42.75 42.75 60.0
17.25 60.0 0.0 42.75 0.0 17.25 ;
END
END PAD

OBS
LAYER via89 ;
POLYGON 17.25 0.0 42.75 0.0 60.0 17.25 60.0 42.75 42.75 60.0 17.25
60.0 0.0 42.75 0.0 17.25 ;

END

END BUMPCELL

In the example above,

• The bump has an octagonal shape of RDL layer. Innovus also supports rectangle
bumps.
• OBS can also be defined on the macro of BUMP cells and is honored by flipchip
router (fcroute).
• Innovus will display the geometry shape of pin’s last layer defined in LEF in GUI.
The picture below is shown how bump will be displayed in Innovus.

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Note,
• Polygon shapes are supported from LEF 5.6.
• Special shapes are supported by being replaced with an octagonal shape.

3.1.3 IO pad

The macro type of IO pads need to be CLASS PAD AREAIO. This is an example,

MACRO iopad
CLASS PAD AREAIO ;
ORIGIN 0.000 0.000 ;
SIZE 35.000 BY 246.000 ;
SYMMETRY x y r90 ;
SITE pad ;
PIN PAD
PORT
CLASS BUMP ;
……………

In the example above,

• The port of PIN PAD has CLASS BUMP attribute, which is an optional attribute
for IO pads with CLASS PAD AREAIO.

More information about CLASS BUMP is in 3.1.4 CLASS BUMP.

3.1.4 Hard macro

If there are hard macros in the design which have pins to be connected to bumps directly
at the top design, these hard macros will keep their original CLASS BLOCK and the
PORTS definition will be enhanced to have a CLASS BUMP associated to them. This is
an example of how the LEF will look:
MACRO Dummy_HM
CLASS BLOCK ;
SIZE 2661.1200 BY 696.6000 ;
ORIGIN 0 0 ;
SYMMETRY X Y R90 ;
PIN A1
DIRECTION OUTPUT ;
USE SIGNAL ;
PORT
CLASS BUMP ;
LAYER top_layer ;
RECT 2469.1800 0.0000 2490.1800
83.0000 ;
END
PORT
….
END Dummy_HM

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In the example above,

• If hard macro doesn’t have any port with CLASS BUMP, it won’t be considered for
flip chip flow even the pin A1 is on an IO net.

More information about CLASS BUMP is in 3.1.4 CLASS BUMP.

3.1.5 CLASS BUMP Attribute

CLASS BUMP is one type of the port. It explicitly indicates that the port is a bump
connection point and it can help user to distinguish which ports in one pin are for flip chip
flow.

Only CLASS PAD AREAIO and CLASS BLOCK can have CLASS BUMP attribute.
• For CLASS PAD AREAIO, this attribute is optional. Following definitions are
correct for flip chip flow.
MACRO iopad MACRO iopad MACRO iopad
CLASS PAD CLASS PAD CLASS PAD
AREAIO ; AREAIO ; AREAIO ;
… … …
PIN PAD PIN PAD PIN PAD
PORT PORT PORT
CLASS #CLASS #CLASS
BUMP ; BUMP ; BUMP ;
… … …
END END END

PORT PORT PORT

CLASS #CLASS CLASS
BUMP ; BUMP ; BUMP ;
… … …
END END END
… … …

END PAD END PAD END PAD

…• For CLASS BLOCK without… this attribute, they won’t be
… considered for flip chip
flow even there are IO pins connected to them.

CLASS BUMP will affect assignment and routing results.

From PORT level,
• If none of the ports in one pin has CLASS BUMP attribute,
 For CLASS BLOCK macro, this pin will be excluded for flipchip flow.

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MACRO iopad
CLASS BLOCK ;
… This pin is not for flipchip flow and
PIN PAD will be excluded for assignment and
PORT
#CLASS
flipchip routing.
BUMP ;
…
END
PORT
#CLASS
BUMP ;
…
END
PORT
#CLASS
BUMP ;
…
END
END PAD
 For
… CLASS PAD AREAIO macro, all ports will be considered as one object for
assignment and flipchip routing.
✓ Only assign one bump to the pin.
✓ Flipchip router will pick one port for routing based on its intelligence.
MACRO iopad
CLASS PAD
AREAIO ;
…
PIN PAD
PORT
#CLASS
BUMP ;
… All 3 ports are for flipchip flow.
END Only assign one bump to pin PAD.
PORT
#CLASS
BUMP ;
…
END
PORT
#CLASS
BUMP ;
…
END
• All ports with
END CLASS
PAD BUMP attribute are equal in one pin.
 It …
applies to both CLASS PAD AREAIO and CLASS BLOCK macros in terms
of assignment and routing.
 Each port will be assigned to one bump.
 Every port can be routed to one or multiple bump, which depends on the setup
of fcroute. User can control the paring of ports and bumps using port
numbering approach.

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MACRO iopad
CLASS PAD AREAIO ;
…
PIN PAD
PORT
CLASS BUMP ;
…
END
PORT
All 3 ports are for flipchip flow. Each
CLASS BUMP ;
… port will be assigned to one bump.
END
PORT
CLASS BUMP ;
…
END
END PAD
…

• Other ports in the same pin without CLASS BUMP attribute will be excluded for
assignment and flipchip routing.
 It applies to both CLASS PAD AREAIO and CLASS BLOCK macros in terms
of assignment and routing.
 Here is an example to explain some ports have CLASS BUMP attribute and
some don’t.

MACRO iopad
CLASS PAD
AREAIO ;
…
PIN PAD This port will be excluded for assignment
PORT and routing.
# CLASS
BUMP ;
…
END
PORT
Both 2 ports are for flipchip flow.
CLASS
BUMP ; Each port will be assigned to one bump.
…
END
PORT
CLASS
BUMP ;
…
END
• PORT withEND PAD
CLASS BUMP attribute with multiple geometries or port shapes is
…
considered as one object for assignment and flipchip routing.

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 It applies to both CLASS PAD AREAIO and CLASS BLOCK macros in terms
of assignment and routing.
 Flipchip router will pick one geometry for routing based on its intelligence since
there is no mechanism to link specific geometry in one port to specific bump.
In case of very close geometries, fcroute will merge some geometries then
choose better one for routing.

MACRO iopad
CLASS PAD AREAIO ;
…
PIN PAD
PORT
# CLASS
BUMP ;
…
END This port with 3 geometries is considered
PORT as one object and will be assigned to one
CLASS bump.
BUMP ;
RECT x x x x ;
RECT x x x x ;
RECT x x x x ;
END
PORT
CLASS
BUMP ;
…
END
END PAD
From PIN…level, assume all pins are
correctly defined as I/O port in netlist and need to be
connected to bumps.
• If none of pins have CLASS BUMP ports,
 For CLASS BLOCK macro, these pins will be excluded for flipchip flow.

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MACRO iopad
CLASS BLOCK ;
…
PIN PAD_1
PORT
#CLASS BUMP ;
…
END
END PAD_1
PIN PAD_2 All 3 pins have no CLASS BUMP ports
PORT and will be excluded for flip chip flow.
#CLASS BUMP ;
…
END
END PAD_2
PIN PAD_3
PORT
#CLASS BUMP ;
…
END
END PAD_3
…

 For CLASS PAD AREAIO macro, each pin will be assigned to one bump.
MACRO iopad
CLASS PAD AREAIO ;
…
PIN PAD_1
PORT
#CLASS BUMP ;
…
END
END PAD_1
PIN PAD_2 All 3 pins have no CLASS BUMP ports.
PORT Each pin will be assigned to one bump.
#CLASS BUMP ;
…
END
END PAD_2
PIN PAD_3
PORT
#CLASS BUMP ;
…
END
END PAD_3
…

• All pins with CLASS BUMP ports are equal in one macro.
 It applies to both CLASS PAD AREAIO and CLASS BLOCK macros in terms
of assignment and routing.
 Each port with CLASS BUMP in one pin will be assigned to one bump.

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 Every port with CLASS BUMP in one pin can be routed to one or multiple
bump.
MACRO iopad
CLASS PAD AREAIO ;
…
PIN PAD_1 Assign PAD_1 to one bump.
PORT
CLASS BUMP ;
…
END
END PAD_1 PAD_2 has two ports but only one
PIN PAD_2 has CLASS BUMP attribute, which
PORT
CLASS BUMP ;
will be assigned to one bump.
…
END
PORT The port without CLASS BUMP in
#CLASS BUMP ;
…
PAD_2 will be excluded for flipchip
END flow.
END PAD_2
…

• Other pins in the same macro without CLASS BUMP ports will be excluded for
assignment and flipchip routing.
 It applies to both CLASS PAD AREAIO and CLASS BLOCK macros in terms
of assignment and routing.

MACRO iopad
CLASS PAD AREAIO ;
…
PIN PAD_1 PAD_1 will be excluded for flipchip flow.
PORT
#CLASS BUMP ;
…
END
END PAD_1
PIN PAD_2
PORT
CLASS BUMP ;
… PAD_2 and PAD_3 will be assigned to
END bumps.
END PAD_2
PIN PAD_3
PORT
CLASS BUMP ;
…
END
END PAD_3
…

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3.2 NETLIST

Bump is physical cell, which must not be defined in netlist. The relationship between
bump and pad is constructed during bump assignment which is based on the shortest
distance. Then use flipchip router to connect IO pad to its assigned bump. Defining
bumps in netlist and assigning nets to these bumps is not a compatible approach to
Innovus and cannot be handled by Innovus.

IO pads must be defined in netlist.

3.2.1 Signal pads

To be able to assign signal pads to bumps and connect them to their assigned bumps,
the netlist needs to have their connection. This is an example,

module top (
pin_1,
pin_2,
pin_3,
pin_4);

input pin_1;
output pin_2; IO ports in top module can be assigned to
inout pin_3; bumps.
inout pin_4;

wire signal_1; Internal signal cannot be assigned to bumps.

iopad_1 iopad_1(.PAD(pin_1));
iopad_2 iopad_2 (.PAD(pin_2));
iopad_3 iopad_3 (.PAD(pin_3)); iopad_1~4 have been defined as
CLASS PAD AREAIO in LEF.
iopad_4 iopad_4(.PAD(signal_1));

endmodule

In the example above,

• IO ports pin_1~3 have related IO pads iopad_1~3 to be connected. So signal
pads iopad_1~3 can be connected to their assigned bumps by flipchip router.

• IO port pin_4 doesn’t have IO pad to be connected. You can get following
WARNING message after assignment and flipchip router will not route net pin_4.
**WARN: (ENCSP-6014): I/O pin 'pin_4' does not connect to placed Area I/O
instance or hard macro.

• Internal wire signal_1 cannot be assigned to bumps, so iopad_4 with signal_1

doesn’t have assigned bumps and flipchip router will not route the net signal_1.

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3.2.2 Power and ground pads

To be able to assign PG pads to bumps and connect them to their assigned bumps, the
netlist could have their connection. This is an example,

module top (
pin_1,
pin_2,
pin_3,
pin_4);

input pin_1;
output pin_2; IO port in top module can be assigned to
inout pin_3;
inout pin_4;
bumps.
…

power_pad power_pad (.VDD());

ground_pad ground_pad (.VSS()); The power_pad and ground_pad have been
defined as CLASS PAD AREAIO in LEF.
endmodule

In the example above, you can find the pin VDD of power_pad or the pin VSS of
ground_pad doesn’t have any related IO port.

If the initial netlist does not have physical IO pads (e.g. power and ground IO pads), the
engineer has the option to add them (addIoInstance) during floorplaning.

In order to create the PG connections,

• First, the power and ground net names must be defined in the power and ground
fields in the Innovus config file or .globals file.
setUserDataValue init_pwr_net {VDD}
setUserDataValue init_gnd_net {VSS}
• Then user needs to run the globalNetConnect command or read the CPF
file(read_power_intent -cpf/commit_power_intent)

After the PG connection created, user can assign PG pads to bumps and connect them
to their assigned bumps by flipchip router.

If the PG connection is not created, flipchip router won’t route these PG nets.

Note,
 PG nets definition is various. Some users have these nets defined as logical nets
in netlist without declaration in *.globals file. In such a case, Innovus cannot

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correctly recognize these nets as special nets and therefore some feature may
not work properly.

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4. Flipchip Floorplaning
4.1 Peripheral IO placement and die size setting
After initiating design in Innovus, the GUI will initially show the floorplan with no
PADs, hard macros or standard cell placed in the die/core area.

Before setting the size of the chip, it is recommended to first place the peripheral IO pads
in the design because automatic pad placement will change the size of the chip. For this,
the user has three choices,
• Read an IO file (loadIoFile) provided by the floorplanner architect or package
engineer.
The IO file, provided by the architect, should be driven by the digital
implementation initial studies or prototyping. The package engineer can also
provide the IO placement and this information is driven by bump/ball routing
constraints. The ball position is likely to be driven also by PCB constraints.

• Load floorplan file (loadFPlan) provided by the floorplanner architect

The command loadFPlan can load pads and hard macros from the floorplan file.

• Automatic peripheral IO pad placement (placePIO).

It is now time to use the automatic pad placement features of Innovus to generate
our initial pad-ring. Innovus supports IO placement for Area or Peripheral IOs. For
peripheral IOs, Innovus supports many advanced features such multi-ring
placement, which can be defined before or after this step.

Let us assume the common case for the backend engineer, which is that the digital
implementation is not constrained by the architect or by the package engineer. Then the
user can issue the command placePIO This will perform and initial random placement,
which can be refined later.

After running the command placePIO, the result is shown as below,

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The picture below shows that the asymmetric rings and IO pads with different heights.

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Example of asymmetric multi-ring initial floorplan

The tool supports the creation of IO Rows for placing the IO PADs. The user can define
IO rows for more customized IO pad placement. To enable this feature the user must
create the IO Rows before placing IO pads (placePIO) by calling the command
createIoRow. The command placePIO will honor IO rows to distribute IO pads into IO
rows. User could call the command, snapFPlanIO –toIoRow, to do automatically
snapping.

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(a) (b)

The picture (a) shows the result of after placePIO in IO row flow, IO pads are not
snapped into IO row sites. After calling “snapFPlanIO –toIoRow”, IO pads are
automatically snapped as shown as picture (b).

Once the IO pads are placed, the user can now set the size of the chip. This can be set
by using the pull-down menu Floorplan -> Specify Floorplan.

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In above form, the user can specify the die size, which can be driven by marketing or
customer requirement. The tool can also derive the dimension of the chip from the
desired final utilization. The designer can specify the distance between the Core and the
IO boundary. This gap, between the core and the inner IO pad ring (in the case of
multiple IO rings), can be used for routing the power rings around the core placement
area.

At this point, the engineer can do the following:

• If the initial design does not have physical IO pads (e.g. power and ground IO
pads), the engineer has the option to add them (addIoInstance) now. The
number of power/ground IOs will depend on the estimated power consumption for
the chip.
• Another option, but recommended step is to add the corner cells using the same
command as above, addIoInstance.
 At this point of the flow, it is not recommended to add the IO filler cells as the
IO pads are likely to be moved and their placement optimized.

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Corner and PG pads added

• Modify the IO PAD placement based on hard macro placement. The design can
have very specific requirements about analog blocks, i.e. PLL or ADC, placement
that eventually will drive some IO pad positions. These pads and hard macros
(HMs) will be selected and set as fixed after manual placement
(setInstancePlacementStatus –name <IO_name> -status fixed). The rest of
the pads are just placed and they are potential candidates for automatic
optimization based on the bump assignment.

Example where hard macros drive the IO pads placement

This is the flow implemented,

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Notes,
• It is very important that the new power and ground pads are assigned to the
correct power and ground nets. The user must create and apply the global net
connections to achieve this, otherwise flipchip router will not route the net from
these pads to the assigned bumps. The global net connections can be done
through the GUI Power->Connect Global Nets, through the command line
globalNetConnect or through reading a CPF file (load_power_intent -cpf)

At the end of these steps, all the hard macros of the design are placed and fixed. The IO
pads are mostly fixed but with a certain degree of freedom in their placement.

4.2 Bump creation and assignment

Flip chip die requires solder bumps for attachment to the package substrate. Bump
generation is typically a two-step process --- placement and signal assignment.

4.2.1 Bump creation

There are multiple ways to create bumps in the Cadence tools, the user can create a
single bump or bump array by using the command create_bump.

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Usually, bumps are created in a regular pattern with fixed pitch. The create_bump
command can support the following bump patterns in the chip:
• -pattern_full_chip
• -pattern_side {side width}
• -pattern_array {row column}
• -pattern_ring width
• -pattern_center {row column}

create_bump is a very flexible command,

• It can create a single bump by using the command as below,
create_bump -cell <cell_name> -loc <x y>
• It also can create multiple types of bump arrays in the same floorplan using
different shapes of bumps. The only requirement is to have valid bump cell names,
which are taken from the LEF file.

Example of peripheral matrix plus core, matrix and stagger bump placement.
Note,
 All these different bump patterns can coexist in the same floorplan.

For bump creation, the GUI form Tool -> Flip Chip Toolbox-> Bump Creation can
produce the same result with the command create_bump.

Here’s how bump creation GUI form looks like:

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During bump array creation, the tool will issue a warning and will not create bumps
where there are overlaps with other bumps based on bump geometry or where bumps
are to be placed outside the die area. The bump arrays do not look into any type of
routing blockages or obstruction in hard macro LEFs. The command deleteBumps has
the options “–overlap_blockages” and “–overlap_macros” which can be used to
“clean up” the placement of the bumps before signal assignment.

Currently verifyGeometry will not highlight overlaps between bumps and routing
blockages. The bumps need to be assigned (committed) in order for verifyGeometry to

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flag the short violation. It is a normal procedure to delete the unassigned bumps after a
flipchip design implementation.

A bump has four location types as specified below. create_bump provides you the
capability to specify which location type is used for bump creation:
• Bump cell center
• Bump cell lower left location
This location can be obtained from bump attribute editor or by using the following
command:
dbGet [dbGet top.bumps.name $Bump_name -p].pt
• Bump geometry (bounding box) center
This location can be obtained with the following command:
dbGet top.bumps.bump_shape_center
• Bump geometry (bounding box) lower left location
This location can be obtained with the following command:
dbGet top.bumps.bump_shape_bbox

From Release 15.2, bump placement supports undo. During bump placement trials, if
you click the Undo button (or use the undo command) after running create_bump, the
bump floorplan will return to the state it was in before create_bump. If you then click
the Redo button (or use the redo command), the bump floorplan will reapply the
changes made by create_bump.
Similarly, if you click Undo after running deleteBumps, the changes made
by deleteBumps are cancelled out and the following bump properties are recovered:
• Name
• Location
• Port number properties
• Fixed status
• Placement status
On clicking Redo, the bump floorplan will revert to the status before undo.

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4.2.2 Bump assignment

After creating bumps, the user can now assign signal and PG bumps.

For signal assignment, the designer can automatically assign the signal bumps to the
closest pad IO. This normally gives a suboptimal assignment for routing.
• Automatic signal assignment
The user can use the command assignBump for signal assignment, this is fully
automatic assignment and it will assign all available signals for flipchip to bumps
based on the shortest distance. The user also can go to Tools -> Flip Chip
Toolbox -> Bump Assignment -> Setting for Bump Assignment and click on
Assign. The GUI form looks as below,

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• Manual signal assignment

 The above GUI form also allows the manual assignment of the bumps. For
manual assignment, user can go to Tools -> Flip Chip Toolbox -> Bump
Assignment -> Assign/Unassign Signals to assignment bump by specified
setting, which is default by Closet. User can also type the bump names or
select a signal name from the list then select a bump in the floorplan GUI or
choose “In Created Order”. The next step will be to click on the “Assign”
button.

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 The user also can type the command assignSigToBump to assign the bumps
manually.

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Example of signal bumps assignment

For PG assignment, the tool accepts the possibility of associating PG pads to specific
bumps with signal assignment together. The user can choose to assign PG and signal
pads to bumps together or just separately do the assignment.
• Assign PG and signal pads to bump together
The assignment can be done automatically by using the command, assignBump
–pgnet {net_name1 net_name2…}, with this usage it will consider PG nets with
signal nets together and distribute appropriate bumps resource from global view
based on the shortest distance.
• Assign PG nets only
 The tool also allows the user to automatically only assign PG nets to bumps by
the command, assignBump –pgonly –pgnet {net_name1 net_name2…}

 If the designer wants to have more control of the assignment of the power and
ground nets, the tool offers a manual assignment by the command

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assignPGBumps or by the GUI form. The user can access to it through GUI
form Tools -> Flip Chip Toolbox -> Bump Assignment -> Setting for PG
Bump Assignment.

 The user can select the bumps and associate them to power or ground nets
using the above

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Example of only PG bump assignment

Notes,
• Notice how the bumps change color once they are assigned. By default, blue for
an assigned signal bump, red for a power bump and yellow for ground bump.

• The designer can change the color of the assignment by supplying the net name
and a valid color, which can be obtained from the link
http://www.w3.org/TR/SVG/types.html#ColorKeywords.
This is useful when the user wants to track the assignment of very specific critical
nets. The command to read this text file is ciopLoadBumpColorMapFile . This is
an example of the file.

Clk green
Address* magenta

It can support wildcards for ease of use.

• After assignment, the user can use the command viewBumpConnection , which
can display the connection as a flight-line between IO pads and bumps.
 The user can use the command “viewBumpConnection –bumpType
signal/power” to only display the flight-lines of signal or PG connections.
 The user can use the command “viewBumpConnection -multiBumpsToPad”
or “viewBumpConnection -multiPadsToBumps” to turn on multiple

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connections. Without these two options, this command will only display
one-to-one connection.

4.2.3 Port numbering approach in assignment

For signal assignment, usually one net is related to one bump and flipchip router can find
the connection based on nets; however, for PG assignment, many PG pads are
connected to the same net. Therefore, the user needs to explicitly specify the paring for
PG connection. It means for such vey customized pattern of multiple pads to multiple
pads, fcroute needs to exactly know which pin or ports need to be routed to which
bump.

Port numbering approach allows user explicitly to specify connection between pads to
bumps during the assignment stage.

• Allow user explicitly specify connection from bump to which port

For example: bump B_100 and Inst_A, Inst_B
• Allow user to explicitly specify which pad to be connected to which bump in case
of multiple pads to multiple bumps
For example: bump B_102 B103 and DDR

The user can add “CLASS BUMP” attribute in LEF onto pins/ports to explicitly tell which
pin/port is for flipchip assignment and routing. This attribute has been introduced in the
section 3.1.5 CLASS BUMP Attribute.

PORTs are numbered uniquely per cell in Innovus database, so that they can be referred
during assignment and routing based on instance.
• Numbers are reference for ports
• Regardless of CLASS BUMP attribute, numbers will be created
• CLASS PAD AREAIO and CLASS BLOCK type of instances only
• The user can instantly see port number by checking Miscellaneous -> Port
Number as shown as following.

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The picture below shows how the tool display port number based on LEF definition.

MACRO iopad
CLASS PAD AREAIO ;
…
PIN VDD
PORT
CLASS BUMP ;
LAYER METAL8 ;
RECT 5 15 15
35 ;
END
PORT
CLASS BUMP ;
LAYER
METAL8 ;
RECT 25 0 35 10 ;
END
PORT
CLASS BUMP ;
LAYER METAL7 ;
RECT 25 15 35 35 ;
END
END VDD
…
The user can use the command, addBumpConnectTargetConstraint to turn on port
numbering feature for automatic assignment, which can be used for both signal and PG
assignment. It will add port number property onto bumps and you can open Bump
Attribute Editor to see the added property values after assignment. The value takes the
following format,

Property name bump_connect_target

Type string

Property string inst_name or inst_name:pin_name or

format inst_name:pin_name:port_num

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Note that before the user can use port numbering related commands, they must turn the
GUI, otherwise ports are not numbered yet so the commands cannot run.

For editing, save/restore the property, they are listed as below,

Assignment Editing property Property save/restore Routing

assignBump addBumpConnectTargetConstraint writeFlipChipProperty fcroute

unassignBump editBumpConnectTargetConstraint readFlipChipProperty

swapSignal deleteBumpConnectTargetConstraint

viewBumpConnection findPinPortNumber

Note,
• Set “setFlipChipMode -honer_bump_connect_target_constraint true” to turn
on port numbering feature for flipchip router(fcroute)
• The number of pin port can be obtained using the dbGet command.
 dbget selected.instTerms.cellTerm.pins.?
pin: allShapes class layerShapeShapes objType shapeViaShapes
portNumber
 dbget ${instCellpgTerm_gnd}. pins.portNumber
1 2 3 4 … 10 11

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 dbget ${instCellpgTerm_gnd}. pins.??

4.3 Bump Assignment Optimization

The tool offers two methods for bump assignment optimization.

• Automatic optimization
• Manual optimization
• Use bump assignment constraint

4.3.1 Automatic bump assignment optimization

At this point in the flow, the power and ground bumps have been assigned. Possibly the
user has also assigned some critical signal bumps close to their IO pads. The rest of the
pads have been assigned to the bumps based on the shortest distance which in some
cases is not the optimal result for routing. At this stage Innovus can optimize the bump
assignment using the command placePIO –assignBump -noRandomPlacement. This
command will call global flipchip router for optimal results in routability.

The above command respects the fix attribute for the bump assignment. The command
to specify the fixed bumps is setBumpFixed. Note that this constraint will affect the
overall routability of the design.

As mentioned earlier, bump and IO pad placement optimization algorithms call the global
flipchip router to obtain an optimal placement. Having constraint information up front will
provide a more realistic scenario for the tool and therefore better results. The full list of
constraints affecting the bump and IO pad placement algorithm is:

• FIXNETPAD
 The syntax is as below,
FIXNETPAD
net_name_list
END FIXNETPAD

 All the pads associated with given nets are fixed.

• FIXPAD
 The syntax is as below,
FIXPAD

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pad_name_list
END FIXPAD
 All the pads in the list are fixed

• FIXPADSIDE
 The syntax is as below,
FIXPADSIDE {EAST WEST SOUTH NORTH}
pad_name_list
END FIXPADSIDE
 The side of all the pads in the list is fixed as specified.

• FIXNETPADSIDE
 The syntax is as below,
FIXNETPADSIDE {EAST WEST SOUTH NORTH}
net_name_list
END FIXNETPADSIDE
 The side of all the pads associated with given nets is fixed as specified.

• GROUPNET
 The syntax is as below,
GROUPNET
net_name_list
END GROUPNET
 The tool will try to place the grouped pads associated with given nets together.

• GROUP
 The syntax is as below,
GROUP
pad_name_list
END GROUP
 The tool will try to place the grouped pads together.

• FIXBUMP
 The syntax is as below,
FIXBUMP
net_name_list
END FIXBUMP
 All the bumps associated with given nets are fixed.

• BUMPREGION
 The syntax is as below,
BUMPREGION
AREA x1 y1 x2 y2
net_name_list
END AREA

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END BUMPREGION
 All the bumps associated with given nets are limited in the specified region.

• PAIR
 The syntax is as below,
PAIR
net_name pad_name_list bump_name_list
END PAIR
 It specifies the connection between bumps and pads based on the net.

These constraints can be given to the tool through setFlipChipMode –constraintFile

command. At this point, the design has an optimized bump assignment. If IO pads are
not allowed to be moved then the design is ready for RDL routing.
This is the flow implemented:

4.3.2 Manual bump assignment optimization

If the designer needs to perform minor ECOs on the assigned bumps, the command
swapSignal can be used or go to Tools ->Flip Chip Toolbox -> Assignment Opt.

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The picture below shows an example.

swapSignal

Swap Signal

Note,
• It supports multiple bumps to multiple bumps.
• Swap signals will not swap bump assignments if these bumps are routed. The
designer will need first to delete the wire with editDelete command.

4.4.3 Use Bump Assignment Constraint

User also can use constraint file for bump assignment to filter ports of pad pin. The bump
assignment constraint file is loaded using the assignBump -constraint_file option.

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At present, the following types of bump assignment constraint are supported:

• SHARE_FIND_PORT constraint to filter unnecessary ports

The syntax for the SHARE_FIND_PORT constraint is as follows:

SHARE_FIND_PORT
PIN pin_name_list
MACRO macro_name_list
LAYERS top_layer[: bottom_layer]
GEOMETRY_SHORT_EDGE min_value [:max_value]
GEOMETRY_LONG_EDGE min_value [: max_value]
net_name_list
END SHARE_FIND _PORT

The SHARE_FIND_PORT constraint can help you find a specific port. However,
the property of CLASS BUMP port in the LEF file is higher priority than this
constraint, which means the SHARE_FIND_PORT constraint cannot filter the port
with CLASS BUMP in the LEF file.

 Net name and at least one of the parameters -

LAYERS, GEOMETRY_SHORT_EDGE, and GEOMETRY_LONG_EDGE
- must be specified to filter unnecessary pin ports
 PIN pin_name_list
✓ Specifies the list of the constraint pins connected with the specified net.
✓ Is optional. If not specified, the constraints for the specified net work on all
available pin ports for the flip chip design.
✓ Supports wildcard matching.
 MACRO macro_name_list
✓ Specifies the list of the constraint MACROs whose pins are connected with
the specified net.
✓ Is optional. If not specified, the constraints for the specified net work on all
available MACROs for the flip chip design.
✓ Supports wildcard matching.
 LAYERS top_layer[: bottom_layer]
✓ Specifies the layer or the layer region on which the pin connected with the
specified net is located.
✓ The name of the layer must support layer ID and layer name in LEF.
 GEOMETRY_SHORT_EDGE min_value [:max_value]
✓ Specifies the value or the region of the short edge length of the pin
geometry connected to the specified net. If only one value is specified, it
means the expected short edge length of pin geometry equals the value.
Otherwise, the expected short edge length is between min_value and
max_value.
✓ The unit is micron.

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CGEOMETRY_SHORT_EDGE means the length of the short edge.

✓ assignBump ignores the geometries with a short edge length that does
not meet the rule.
✓ For example, pin VDD has following different ports:
o port1: 5x25
o port2: 15x10
o port3: 5x5
o port4: 10x20
o port5: 15x25
If constraint file specifies GEOMETRY_SHORT_EDGE 10:20,
then port2, port4 and port5 can become candidates for assignment.
On the other hand, if constraint file specifies GEOMETRY_SHORT_EDGE
5, port1 and port3 can become candidates for assignment.
 GEOMETRY_LONG_EDGE min_value [: max_value ]
✓ Specifies the value or the region of the long edge length of the pin
geometry connected to the specified net. If only one value is specified, it
means the expected long edge length of pin geometry equals the value.
Otherwise, the expected long edge length is between min_value and
max_value.
✓ The unit is micron.
✓ GEOMETRY_LONG_EDGE means the length of the long edge.
✓ assignBump ignores those geometries with a long edge length that does
not meet the rule.
 net_name_list
✓ Specifies the list of the nets. This is a mandatory parameter.
✓ Supports wildcard matching and also @signal, @power and @ground.

Here’s an example of the SHARE_FIND_PORT constraint:

SHARE_FIND_PORT
PIN VDD
MACRO VDD_PAD DDR_VDD_PAD
LAYERS metalALP
GEOMETRY_SHORT_EDGE 20:25
GEOMETRY_LONG_EDGE 15
@power
END SHARE_FIND _PORT

If this constraint is specified in the assignBump constraint file, only those pins
that meet the following requirements are available for bump
assignment. assignBump ignores all bumps that do not meet these
requirements:
 To be connected to the power net in the design
 The name in LEF is VDD
 Belongs to the macros VDD_PAD or DDR_VDD_PAD
 On the layer metalALP

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 Has short edge between 20 and 25 microns and long edge equals 15 microns

• ASSIGN_ANALOG_PG_NETS constraint to specify which signal nets are analog

PG nets
The syntax for the ASSIGN_ANALOG_PG_NETS constraint is as follows:

ASSIGN_ANALOG_PG_NETS
net_name_list
END ASSIGN_ANALOG_PG_NETS

 net_name_list
✓ Specifies the list of nets that are defined as signal nets in LEF or netlist but
are actually analog PG nets.
✓ Supports wildcard matching.

Note:
✓ The nets specified with the ASSIGN_ANALOG_PG_NETS constraint are
still signal nets but are used for auto power/ground
assignment. assignBump treats these nets in the same way as other
normal power/ground nets.
a. These nets can be specified as arguments of the assignBump -pgnet
{net_list} or -exclude_pgnet {net_list} options.
b. These nets are considered when the assignBump -pginst
{instance_list} is used.
c. These nets are excluded from signal assignment of assignBump.
✓ assignBump does not modify the property of specified nets
in ASSIGN_ANALOG_PG_NETS. Therefore, after assignment, the bumps
that are assigned with the specified nets
in ASSIGN_ANALOG_PG_NETS must be signal bumps instead of
power/ground ones.

• SHARE_IGNORE_* and ASSIGN_IGNORE_* constraints to exclude instances,

macros, pins, or nets for assignment.
The SHARE_IGNORE_* and ASSIGN_IGNORE_* constraints can be used to
exclude instances, macros, pins, or nets for assignment. The syntax of the
constraint varies depending on what is being excluded.

 Excluding Instances
Use the following syntax to specify list of instances to be excluded from
assignment:

SHARE_IGNORE_INSTANCE
instance_name_list
END SHARE_IGNORE_INSTANCE

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Here, instance_name_list specifies the list of instances that are to be excluded

during assignment. It supports wildcards.

 Excluding Macros
Use the following syntax to specify list of macros to be excluded from
assignment:

SHARE_IGNORE_MACRO
macro_name_list
END SHARE_IGNORE_MACRO
Here, macro_name_list specifies the list of macros that are to be excluded
during assignment. It supports wildcards.

 Excluding Instance Pins

ASSIGN_IGNORE_INSTANCE_PIN
instance_name:pin_name
...
END ASSIGN_IGNORE_INSTANCE_PIN

Here instance_name:pin_name :
✓ Specifies which pin of the specified instance is to be excluded during
assignment.
✓ Supports multiple parameters.
✓ Supports wildcards.
✓ Does not allow any blank spaces before or after “:”

 Excluding Macro Pins

ASSIGN_IGNORE_MACRO_PIN
macro_name:pin_name
...
END ASSIGN_IGNORE_MACRO_PIN

Here macro_name:pin_name :
✓ Specifies which pin of the specified macro is to be excluded during
assignment.
✓ Supports multiple parameters.
✓ Supports wildcards.
✓ Does not allow any blank spaces before or after “:”

 Excluding Nets
ASSIGN_IGNORE_NET
net_name_list
END ASSIGN_IGNORE_NET
Here, net_name_list specifies the list of nets that are to be excluded during
assignment. It supports wildcards.

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• ASSIGN_PAD2BUMP_RATIO constraint to specify the pad to bump ratio per net,

macro, or instance.
The syntax for the ASSIGN_PAD2BUMP_RATIO constraint is as follows:

ASSIGN_PAD2BUMP_RATIO
TOLERANCE net_name integer
PGNET net_name ratio
PGMACRO macro:pin ratio
PGINST inst:pin ratio
END ASSIGN_PAD2BUMP_RATIO

The ASSIGN_PAD2BUMP_RATIO constraint specifies the pad to bump ratio per

net, macro, or instance.

 Parameters for Ratio Greater than 1

The following parameters work with a pad to bump ratio greater than 1.
✓ TOLERANCE net_name integer
✓ PGNET net_name ratio
When the pad to bump ratio is greater than 1, assignBump calculates the
number of groups of multiple PG ports to multiple bumps and the maximum
number of ports in each group based on the specified ratio per net.

Assume the total number of ports is total_port, and the ratio

is port_num:bump_num.
✓ If total_port is an integer multiple of the ratio:
Number of groups = total_port÷(port_num/bump_num) + TOLERANCE
Else:
Number of groups = [total_port÷(port_num/bump_num)] + 1 +
TOLERANCE
✓ If port_num is an integer multiple of bump_num:
Maximum number of ports in each group = port_num ÷ bump_num
Else:
Maximum number of ports in each group = [port_num ÷ bump_num] + 1

For example, if there are 5 pads with VDD and the VDD pin of each pad has
only one port and the pad to bump ratio is 3:2. Then:
Number of groups = Round off {5÷ (3/2) + 0} = 4
Maximum number of ports in each group = Round off {3/2} = 2

This feature tries to provide the best assignment result in following conditions:
✓ The number of groups remains unchanged.
✓ In each group, the number of ports must be no more than the maximum
number of ports.

Following is the description of the parameters for ratio greater than 1:

✓ TOLERANCE net_name integer

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o Specifies the tolerance value for specific nets. It only supports positive
integers. With this option, the number of pad/port groups will be
counted by the tolerance value.
o The default value is zero.
o It works only for PGNET net_name ratio
o net_name supports wildcard matching.

✓ PGNET net_name ratio

o Specifies the ratio for specific nets.
o net_name supports wildcard matching.
o The ratio must be more than 1. If you specify a ratio less than
1, assignBump issues an ERROR message and ignores the ratio.
o If the ratio is not in the simplest form, the tool will simplify it and give a
WARNING.
o For different PG nets, define the ratio per net separately. If you specify
more than 1 ratio for the same net, assignBump issues a WARNING
message and chooses the last specified ratio for the net.

Example1:
If the ratio for both VDD and VDD0 is 2:1 and the ratio for VSS is 3:2, the
syntax is as below:
PGNET VDD 2:1 #The ratio for VDD is 2:1
PGNET VDDO 2:1 #The ratio for VDDO is 2:1
PGNET VSS 3:2 #The ratio for VSS is 3:2
PGNET VSS 3:2 #As this is the second and last ratio for VSS,
assignBump
#issues a WARNING message and use it as the ratio
of
#net VSS.
PGNET VSSO 1:2 #As the ratio for VSSO is less than 1, assignBump
issues
#an ERROR message and ignores it.

Example 2
PGNET * 2:1 #The ratio for all PG nets specified in the assignBump
command is 2:1

Example 3
In the ratio.const constraint file, following is specified:
PGNET VDD 4:2
PGNET VSS 4:2

Run the following command:

assignBump -constraint_file ratio.const -pgnet {VDD VSS}

a. The tool first simplifies the ratio to 2:1.

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b. The tool calculates the number of pad/port groups and maximum

number of ports in each group as follows:
o For VDD, as the total number of ports with VDD (5) is not an integer
multiple of port_num (2), therefore:
Number of groups = [total_port÷(port_num/bump_num)]+1 +0
= [5÷(2/1)]+1 = [2.5] + 1 = 2 + 1 = 3
o For VSS, as the total number of ports with VSS (3) is not an integer
multiple of port_num (2), therefore:
Number of groups = [total_port÷(port_num/bump_num)]+1 +0
= [3÷(2/1)]+1 = [1.5] + 1 = 1 + 1 = 2
o Both VDD and VSS use the same ratio 2:1. As in this
ratio, port_num(2) is an integer multiple of bump_num (1),
therefore:
Maximum number of ports in each group for VDD and VSS
= port_num÷bump_num = 2/1 = 2

The multi-PG pad to bump assignment is depicted below.

 Parameters for Ratio Less than 1

The following parameters work with a ratio less than 1.
✓ PGMACRO macro:pin ratio
o Specifies the ratio for the specific MACRO cell.
o macro:pin supports wildcard.
o The ratio must be less than 1. Otherwise, assignBump issues an
ERROR message and ignores it.
o If you specify more than 1 ratio for the same pin, assignBump issues
a WARNING message and chooses the last specified ratio for it.
o Choose the out-most geometry as the target and record the port
number into bump_connect_target.

Example 1
PGMACRO DDR1:VDD 1:2 #The ratio for VDD pin in DDR1 is 1:2
PGMACRO DDR2:VDD 1:2 #The ratio for VDD pin in DDR2 is 1:2

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PGMACRO DDR2:VDD 1:3 #As this is the second ratio and last
ratio for
#VDD pin in DDR2, assignBump
issues a WARNING
#message and uses it as the ratio of
VDD pin in DDR2.
PGMACRO DDR3:VSS 2:1 #As the ratio is more than 1,
#assignBump issues an ERROR
message and ignores it.

Example 2
PGMACRO * 1:2 #The ratio for all pg pins in all macros of the
#intances specified in the assignBump
command
#1:2.
PGMACRO DDR1:* 1:2 #The ratio for all pg pins in DDR1 is 1:2.
PGMACRO *:VDD 1:2 #The ratio for VDD pin in all macros of the
#instances specified in the assignBump
command
#is 1:2.

✓ PGINST inst:pin ratio

o Specifies the ratio for the specific instance.
o inst:pin supports wildcard.
o The ratio must be less than 1. Otherwise, assignBump issues an
ERROR message and ignores it
o If you specify more than 1 ratio for the same pin, assignBump issues
a WARNING message and chooses the last specified ratio for it.
o Choose the out-most geometry as the target and record the port
number into bump_connect_target.

Example 1
PGINST inst1:VDD 1:2 #The ratio for VDD pin in inst1 is 1:2
PGINST inst2:VDD 1:2 #The ratio for VDD pin in inst2 is 1:2
PGINST inst2:VDD 1:3 #As this is the second and last ratio for VDD
pin
#in inst2, assignBump issues a WARNING
message
#and uses it as the ratio of VDD pin in inst2.
PGINST inst3:VSS 2:1 #As the ratio is more than 1, assignBump
issues
#an ERROR message and ignores it.

Example 2
PGINST * 1:2 #The ratio for all pg pins of all instances

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#specified in the assignBump command is 1:2.

PGINST inst1:* 1:2 #The ratio for all pg pins in inst1 is 1:2.
PGINST *:VDD 1:2 #The ratio for VDD pin of all instances
#specified in the assignBump command is 1:2.

If there is some conflict over ratio, the priority order is PGINST > PGMACRO >
PGNET as shown in the following example.

ASSIGN_PAD2BUMP_RATIO
PGNET VDD 2:1 #The ratio for VDD is 2:1.
PGMACRO DDR:VDD 1:2 #If the VDD pin in DDR is connected to VDD,
#the ratio for VDD pin in DDR is 1:2 as the priority
#of PGMACRO is higher than PGNET.
PGINST inst:VDD 1:3 #The MACRO cell of inst is DDR. As the priority of
PGINST
#is higher than PGMACRO, the ratio for VDD pin in inst
#is 1:3
PGNET VSS 3:1
PGINST inst1:VSS 1:3 #If the VSS pin in inst1 is connected to VSS, the ratio
#for VSS pin in inst1 is 1:3 as the priority of
#PGINST is higher than PGNET.
END ASSIGN_PAD2BUMP_RATIO

The usage of ASSIGN_PAD2BUMP_RATIO is as below:

o It turns on the feature of pads to bumps assignment by ratio.
o If used with -pgnet, ASSIGN_PAD2BUMP_RATIO works on only the
specified PG nets.
o If used with -exclude_pgnet, ASSIGN_PAD2BUMP_RATIO ignores the
constraints for the specified excluded PG nets.
o If used with -pginst, ASSIGN_PAD2BUMP_RATIO works on only the
instances specified by PGMACRO and PGINST.
o If used with -pgnet and -pginst, ASSIGN_PAD2BUMP_RATIO works on
only the specified PG nets of the instances specified by PGMACRO and
PGINST.
o If used with -exclude_pgnet and -pginst, ASSIGN_PAD2BUMP_RATIO
works on the PG nets of the instances specified by PGMACRO and PGINST,
with the exception of the specified excluded PG nets.
o If the objects specified by -pgnet, -exclude_pgnet and -pginst are not
included in ASSIGN_PAD2BUMP_RATIO, assingBump issues a warning
message and uses 1 as the ratio value.
o If not used with -pgnet, -exclude_pgnet or -pginst,
ASSIGN_PAD2BUMP_RATIO ignores all the defined constraints.

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4.4 IO PAD Optimization

The automatic bump assignment optimization flow describes the process when the
implementation designer has full freedom for placing and assigning bumps.
The designer still has the possibility of optimizing the IO PADs for improving routability of
the RDL layer. Innovus provides this possibility in an automatic way.
The command to use is placePIO –optIOs –noRandomPlacement. Again, the global
flipchip router will be called to improve the pad placement.

This function requires a close collaboration with the package engineer as the bumps
created in the above flow need to be routed to the package balls. The package routing
can be very demanding and resource hungry. It is very likely that there will be some
constraints (in terms of bump placement and assignment) coming from the APD/SiP tool.
This bump placement and assignments can be fed into Innovus by reading an IO file
provided by the package tool. Innovus and SiP provides features, which help this
communication between the tools.

After reading the new bump assignment from the APD tool, the following scenarios/flows
are supported by Innovus:

• If there are bump assignments which are still allowed to be optimized, then the
above described flow can be used. As it was described earlier on, the command
placePIO –assignBump –noRandomPlacement will optimize the bump
assignment. The user should instruct the tool which assignments are fixed by
using the constraint file together with the command setFlipChipMode.

• All the bumps in the design are fixed and assigned by the package engineer. No
new assignments are allowed. In this case the only available methodology for the

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engineer is to optimize the IO pad placement. Remember that some of these pads
may only be placed (and not fixed). To optimize these pads, the user will need to
run the following command, placePIO –optIOs –noRandomPlacement.

This command respects the fix attribute applied to the IO pads.

• Some bumps can be optimized together with some of the IO pads. For this
scenario, Innovus can optimize the placement of IOs and the assignment of the
bumps at the same time. The command placePIO –assignBump –optIOs
–noRandomPlacement can be used to achieve this.
For this case, again, the user needs to supply the fixed bumps by using the
command setFlipChipMode. The IO pads which are not allowed to move should
be set as fixed.

As a golden rule, the sooner the flipchip floorplaning is tackled the easier it is for the
engineer to find a viable solution. Once the design enters into the digital implementation
there is a small chance that the IO pads can be moved.

This flow chart graphic will describe the flow for optimizing the IO pads and/or bump
assignments.

At this point after any modification in the bump assignment the design needs to be
checked in APD for routability. After step C the design is ready for power planning and
RDL routing.

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5. Power Planning
The general power planning step does not differ from a non-flipchip design. However,
there are flow recommendations worth mentioning.

It is advisable NOT to use the RDL layer before pad to bump routing, as flipchip router is
very sensitive to routing obstructions. The power routing, i.e. stripe generation, with the
RDL layer can be done after IO pads to bumps routing.

The command addStripe provides 2 options for easier flipchip design support. These
options are:
• -over_bumps
 This option will create a power stripe over PG bumps.
 The stripe generation will STOP at the end of a valid PG bump.
 The picture below shows power stripes in metal 8 generated over bumps in
metal 9. The command will automatically drop the generated vias if bumps
don’t have OBS to prevent via under bump as defined in LEF.

• -between_bumps
 This option will create a power stripe between PG bumps.
 The stripes will NOT be created in areas where there are no PG bumps.
 The picture below shows the result of running the command addStripe with
the –between_bumps option. Notice the missing stripes where there are no
PG bumps.

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Single stripes of VSS and VDD are created between the bumps.

These options allow for the possibility of providing an area (rectangular or rectilinear) for
stripe routing. This is very flexible and improves the usability of the command when there
are multiple power domains in your design.

At this stage, it is not recommended to route/create the connection between power

bumps and power routing/power pads using the RDL layer. This step will be performed
during or as a post step of the signal routing. This will be explained in the signal and
power routing sections of this application notes.

Notes:
• The command addStripe will create stripes over unassigned bumps. It is
recommended that after pad and bump optimization the user deletes all the spare
bumps. verifyGeometry will not highlight these shorts as violations as the bump is
not assigned.
• If the user is planning to create power/ground stripes in the same layer as the
RDL routing then it is recommended to do this after the signal routing by fcroute.

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6. RDL Routing
6.1 Introduction
Flipchip router (fcroute) is mainly used for routing the nets between bumps and IO
PADs.

The command fcroute supports two types for routing,

• fcroute -type power
 This type can connect PG bumps to rings or stripes.
 It only supports Manhattan routing style.
 It doesn’t honor the setting given by the command setFlipChipMode.

• fcroute -type signal

 This type can connect bumps to IO pads
 The router under this type supports two routing styles Manhattan and 45
degree routing.And 45 degree routing is the default routing style.
 It honors all the setting given by the command setFlipChipMode.
 Used with the option –connectPowerCellToBump, it can route PG bumps to
IO pads. It also can be turned on by the command “setFlipChipMode –
connectPowerCellToBump true”
 Used with the option –preventViaUnderBump, it can prevent via generated
on the bump.

The command, fcroute –type signal, accepts two design styles – peripheral IO (PIO)
and area IO (AIO). But it’s not limited by design styles, which means the user can
use AIO mode for some specific purpose in PIO design.

Note, AIO or PIO mode will be used to describe which design style is specified for
fcroute in this document.

• fcroute –type signal –designStyle aio

This command will only use detail router to finish the connections between bumps
to IO pads and it routes nets one by one, so it’s incremental.

• fcroute –type signal –designStyle pio

 This command will first use global router to distribute all routing resource then
use detail router to finish the connections between bumps to IO pads followed
by a post processing step to finalize routing.
 It partially supports area-based routing in the specified coordinates (fcroute
–type signal –designStyle pio –area {x1 y1 x2 y2} -incremental) for the
area in which the net is routed. And the option –incremental is required for
area-based PIO mode routing.

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Usually flipchip router connects one bump to one pad. However, fcroute is able to
connect bump to multiples pad or multiple bumps to pad. The related commands are
shown as below.
• Multiple bumps to pad
setFlipChipMode -multipleConnection multiBumpsToPad helps user route
multiple bumps to one pad in parallel.

• Multiple pads to bump

setFlipChipMode -multipleConnection multiBumpsToPad helps user route
multiple bumps to one pad in parallel.

From version 18.1, Innovus enable serial pad routing (bump-pad-pad routing)
by setFlipChipMode -serial_pad_routing true. The routing results is shown
as below. Please note, only PIO mode support serial pad routing.

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Also fcoute can support TSV routing, which can route TSV to bumps/stripes/instance
pins. The related commands are listed as below,
• Connect TSV to bumps, fcroute -type signal –connectTsvToBump
 Since TSV has front side bump and back side bump, fcroute should route
them separately. Add “srouteExcludeBumpType bump_cell_name” in extra
configure file to tell fcroute to know exclude which bumps for routing.
✓ When connect TSV to back side bump, please use extra config file to
exclude the front bump
✓ when connect TSV front side bump, please exclude the back side bump

• Connect TSV to IO pads, fcroute -type signal –connectTsvToPad

• Connect power TSV to stripes, fcroute -type power –connectTsvToRingStripe

TSV routing result is shown as below,

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Flipchip route (fcroute) is an intelligent and predictable RDL router and it can help the
designer evaluate floorplan change based on the quick flipchip routing result. In the initial
floorplan stage, the user can use following general setting to get a quick routing result,
• Set routing layers
 Use the command setFlipChipMode to set
setFlipChipMode –layerChangeBotLayer bot_layer_name\
-layerChangeTopLayer top_layer_name
 Use the command fcroute to set
fcroute –layerChangeBotLayer bot_layer_name\
-layerChangeTopLayer top_layer_name

• Set routing width

 Use the command setFlipChipMode to set
setFlipChipMode -routeWidth value
 Use the command fcroute to set
fcroute -routeWidth value

You can use following commands with the setting above,

• Use setFlipChipMode for settings then run fcroute for routing,
 Step1: specify routing setting for fcroute
setFlipChipMode –layerChangeBotLayer bot_layer_name\
-layerChangeTopLayer top_layer_name -routeWidth value

 Step2: get routing setting for fcroute to make sure all the settings are
expected.
getFlipChipMode

 Step3: run fcroute with PIO mode as an example

fcroute –type signal –designStyle pio

• Use fcroute for both setting and routing,

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 Step1: get routing setting before routing to make sure all the settings are
expected.
getFlipChipMode

 Step2: run fcroute with PIO mode with general settings as an example,
fcroute –type signal –designStyle pio -routeWidth value\
–layerChangeBotLayer bot_layer_name\
-layerChangeTopLayer top_layer_name

Note that the difference between the settings for setFlipChipMode and fcroute is as
below,
• All the settings set by the command setFlipChipMode can be saved/ restored by
saveDesign/restoreDesign. And they can work on fcroute if they’re not reset or
overwrite by the options of fcroute.
• All the setting set by the command fcroute cannot be saved after running fcroute.
And they only works when they’re used in fcroute.

Generally, fcroute can well handle typical pin shape shown as below,
• Only one geometry for fcroute
• Width/height of pin geometry won’t be different greatly from each other.
• At least one of width/height is larger than routing width.

Note, fcroute also can route some special pin shape such as one slim geometry and
multiple geometries. But the routing quality is not so well and we’re tuning the quality.
All above is for the basic function of fcroute and it’s greatly extended by constraints and
extra configure options for customized requirements.
• All constraints are specified in a text file and they can be given as an input to the
command fcroute –constraintFile or setFlipChipMode –constraintFile.
• All extra configure options are specified in a text file and they can be given as an
input to the command fcroute –extraConfig or setFlipChipMode –extraConfig.

Some useful constraints and extra configure options for fcroute will be described in
detailed in this module.

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6.2 Useful constraints for flipchip routing

Flipchip router (fcroute) provides the user the capability to specify routing constraints
into a text file, which can be given as an input to the command fcroute –constraintFile
or setFlipChipMode –constraintFile.

Note,
• For all length constraints, they take micron.
• For all resistance constraint, they take ohm.
• All values can take floating ones.

What follows is a detailed explanation of the routing constraints supported by fcroute.

6.2.1 Global Constraints

The user can specify general constraints affecting all the nets in the design. These
general constraints need to be declared at the top of the file. The accepted constraints
are as below,

• WIDTH <value>
 It specifies the global width for all the nets.
 The unit is micron.
 Both AIO and PIO modes support this constraint.
 Both Manhattan and 45 degree routing support this constraint.
 If the user also specifies routing width in the command setFlipChipMode or
fcroute, fcroute will use the width specified in the command.
 It can also be applied into the NETS constraint which is a local constraint and
the specified width value only works on the associated nets in NETS
constraint.

• WIDTHRANGE min_value:max_value
 It only works for PIO modes.
 It specifies a width range and allows fcroute to optimize wire width by
considering MAXRES constraints.
 The unit is micron.
 It can also be applied into the NETS constraint which is a local constraint and
the specified width range only works on the associated nets in NETS
constraint.

• MAXRES <value>
 It specifies the maximum resistance allowed to all the specified nets.
 The unit is ohm.
 Only PIO mode supports this constraint.
 Both Manhattan and 45 degree routing support this constraint.

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 The command fcroute can report the resistance with the setting
“srouteFCReportRes res_file_name” in the extra configure file.
 It can also be applied into the NETS constraint which is a local constraint and
the specified resistance only works on the associated nets in NETS constraint.

• SPACING <value>
 It specifies the distance in microns between the net routed by the flipchip
router and all other routes.
 The unit is micron.
 Both AIO and PIO modes support this constraint.
 Both Manhattan and 45 degree routing support this constraint.
 The router uses the spacing value to limit the effect of coupling capacitance on
the total capacitance of the net.
 It can also be applied into the NETS constraint which is a local constraint and
the specified spacing only works on the associated nets in NETS

• PIOLAYERCHANGE PAD
 It turns on layer change feature.
 Only PIO mode supports this constraint.
 Both Manhattan and 45 degree routing support this constraint.
 Different setting for routing layers will have following behaviors, assume top
RDL is TOP_RDL and the second top RDL is 2nd_RDL.
✓ Use TOP_RDL as much as possible and 2nd_RDL is only used when
single layer cannot finish routing in case of cross-over.
–layerChangeBotLayer TOP_RDL -layerChangeTopLayer TOP_RDL

✓ Freely change layers, so that the tool will use layer resources by its
intelligence.
–layerChangeBotLayer 2nd_RDL -layerChangeTopLayer TOP_RDL

• FINDPINLAYERS <layer_name>
 It specifies the layer of the pin geometry for connection.
 Both AIO and PIO modes support this constraint.
 Both Manhattan and 45 degree routing support this constraint.

• MINPINSIZE <width height>

 It specifies the minimum geometry of the pin for connection.
 The unit is micron.
 Both AIO and PIO modes support this constraint.
 Both Manhattan and 45 degree routing support this constraint.

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6.2.2 SPLIT Constraint

SPLIT constraint is to split wires when routing width is larger than MAXWIDTH defined in
LEF or the specified value by the user.

SPLIT constraint works for AIO and PIO modes. Also it supports both Manhattan and 45
degree routing.

The syntax of SPLIT constraint is as below,

SPLITSTYLE RIVER|MESH
SPLITWIDTH <value>
SPLITGAP <value>
SPLITKEEPTOTALWIDTH TRUE/FALSE

• SPLITSTYLE RIVER/MESH
 It specifies the interleaving style used for the split wires.
 The default value is RIVER.
 RIVER: The split wires do not have an interleaving pattern.

 MESH: The split wires interleave with one another, as shown in the following
illustration:

• SPLITWIDTH <value>
 It specifies the width of the split wire segment. If routing width is larger than
this value, fcroute will auto split them.
 The unit is micron.
 Default value: MAXWIDTH defined in LEF

• SPLITGAP <value>
 It specifies the gap between split wire segments.
 The unit is micron.
 If you specify this constraint, ensure that the distance between the split wire
segments must be greater than the specified gap value.
 If you do not specify this constraint, the distance between split wire segments
is the default minimum spacing value that does not cause DRC violations.

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• SPLITKEEPTOTALWIDTH TRUE/FALSE
 It’s used to control different formula to compute the width of splitting wires.
 FALSE
✓ This is the default value.
✓ The splitting wire width is calculated using the follow formula
Total_wire_width = split_wire_width x n + split_gap x (n - 1)
✓ For example, routing width=13, MAXWIDTH in LEF=10, split_gap=1.5.
Therefore, split_wire_wdith=(13-1.5)/2=5.75

 TRUE
✓ The splitting wire width is calculated using the follow formula
Total_wire_width = split_wire_width X n
✓ For example, routing width=13, MAXWIDTH in LEF=10, split_gap=1.5.
Therefore, split_wire_wdith=13/2=6.5
✓ The difference from FALSE is to take the split gap out of the wire width
calculation so that splitting wire width can be controlled by the user.

• It can also be applied into the NETS constraint which is a local constraint and
SPLIT feature only works on the associated nets in NETS constraint.

• One example for different split style,

 SPLITSTYLE RIVER

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 SPLITSTYLE MESH

6.2.3 NETS Constraint

The user can use NETS constraint to set some specific constraint for nets. It can work for
AIO and PIO modes. Also it supports both Manhattan and 45 degree routing.

The syntax of NETS constraint is as below,

NETS
WIDTH <value>
ROUTELAYERS <bottom_layer:top_layer>
SPACING <value>
<net_name_list>
END NETS

• “WIDTH <value>” and “SPACING <value>” are the same as the one in 6.2.1
Global Constraints

• ROUTELAYERS <bottom_layer:top_layer>
 It specifies a layer range for routing.
 The name of layer could be specified the layer number or the layer name in
LEF.

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✓ For example, bottom_layer is metal7(METG2 in LEF) and top_layer is

metal8(METTOP in LEF), following usages are acceptable for fcroute,
ROUTELAYERS 7:8;
ROUTELAYERS metal7:metal8;
ROUTELAYERS METG2:METTOP.// This is recommended usage.

• <net_name_list>
 It specifies the names of nets.
 It supports general matching methods as below,
✓ It supports “~”, which negates the specified net.
✓ It supports wildcard matching(*)
✓ It supports “@SIGNAL, @POWER, @GROUND”,
@SIGNAL means all signal nets;
@POWER means all power nets;
@GROUND means all ground nets.

6.2.4 Differential Routing Constraint

Differential routing is aimed at providing similar net delays and it applies to pairs of nets.
It only works for AIO mode and also it supports both Manhattan and 45 degree routing.

To route these nets, fcroute will try,

• Balance pair routing (matching routing length), if it fails then
• Topological pair routing, if it fails then
• Match L/W routing

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(a) (b)
(c)

The same constraints have been used to create the above three routing results, the
differences were on the nets selected for routing. In these routing examples,
• Picture (a) has balanced routing matching the length and topology of both nets.
• Picture (b) cannot match the length but keeps the topological matching.
• Picture (c) cannot match the topological so fcroute matches the length and the
width of both nets.

All these methodologies guarantee a similar net delay.

The syntax of DIFFPAIR constraint is as below,

DIFFPAIR
[THRESHOLD <value>]
<Net1>
<Net2>
END DIFFPAIR

• THERSHOLD <value>
 It specifies the percentage threshold between normal and balance routing for
extra wire length.
 For example, “THERSHOLD 0.2” means to specify the threshold as 20%.

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6.2.5 Match Routing Constraint

For a group of nets (more than 2) the router tries to match routing length. It only works for
AIO mode. Also it supports both Manhattan and 45 degree routing.

The syntax of MATCH constraint is as below,

MATCH
<Net1>
<Net2>
…
<Netn>
END MATCH

In the picture below the user has selected 4 nets to MATCH the length of the routing.

6.2.6 Shielding Routing Constraint

Flipchip router supports the capability of shielding nets during routing. To enable the
feature the recommendation is to use the constraint file. Both AIO and PIO modes
support this feature. Also both Manhattan and 45 degree routing support it.

The syntax of SHIELDING constraint is as below,

SHIELDING
SHIELDBUMP TRUE/FALSE

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SHIELDWIDTH <value>
SHIELDGAP <value>
SHIELDSTYLE a|b|c
SHIELDNET <net_name>
<net_name_list>
END SHIELDING

• SHIELDBUMP TRUE/FALSE
 TRUE
✓ Shield bump with the specified shield net.
✓ It only works in aio mode and Manhattan routing style.
 FALSE
✓ Don’t shield bump.
✓ It’s the default value for SHIELDBUMP.

• SHIELDWIDTH <value>
 It specifies the width of the Shield Net, measured in microns.

• SHIELDGAP <value>
 It specifies the distance in microns between the shield (the special net) and the
shielded net (the signal net).

• SHIELDSTYLE a|b|c
 It specifies where you want the shield to be placed, Above or Below or on the
Common layer.
✓ a = above the layer containing bumps
✓ b = below the layer containing bumps
✓ c = on the layer containing bumps ("common layer")

• SHIELDNET <net_name>
 It specifies a special net (typically VSS) used to shield the net.

• <net_name_list>
 It specifies the shielded nets.

In the picture below, the left net doesn’t have SHIELDBUMP and the right net can be
achieved by using “SHIELDBUMP TRUE”.

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Note, the shielding created will be floating. The user will need to connect the shielding to
the correct power/ground supply by using the editPowerVia command.

When using the fcroute shielding option, the defOut marks the shielded nets as
`SHIELD', while displaying the SHAPE and ROUTED status of the metal shield wire.

Example
Consider the following example in which the fcroute command connects signal bumps
to I/O cells using 90 degree signal routing for AIO; The command adds a side shield
(VSS) on both sides of the signal route.

setFlipChipMode - route_style manhattan

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fcroute -type signal -designStyle aio -layerChangeToplayer 8

-layerChangeBotLayer 7 -routeWidth 8 -constraintFile CFG/aio.constr

Constraint File CFG/aio.constr: Shield Net Description

SHIELDING
SHIELDBUMP true
SHIELDWIDTH 0.4
SHIELDLAYERS abc
SHIELDNET VSS
scan_out_2
port_pad_data_out[15]
END SHIELDING

DEF Syntax
The defOut contains the SHIELD syntax as follows:

-scan_out_2 ( Bump_27_6_2 PAD ) (IOPADS_INST/Pscanout2op PAD)

+ ROUTED METAL8 16000 + SHAPE IOWIRE (1255310 541920 ) ( 1369310 *)
NEW METAL8 16000 + SHAPE IOWIRE (1263310 533920 ) ( * 695760 )
+ PROPERTY BUMP_ASSIGNMENT "ASSIGNED"
;
-VSS ( * VSS )
+ SHIELD scan_out_2 METAL8 800 + SHAPE IOWIRE ( 1275310 554320 ) ( 1315310
*)
NET METAL7 16000 + SHAPE IOWIRE ( 1255310 541920 ) ( 1315310 * )
NET METAL8 800 + SHAPE IOWIRE ( 1250510 529520 ) ( 1315310 * )
+ ROUTED METAL6 16000 + SHAPE STRIPE ( 1553200 109600 ) ( * 186800 )
NET METAL6 16000 + SHAPE STRIPE ( 1753200 109600 ) ( * 186800 )
+ SHIELD scan_out_2 METAL8 800 + SHAPE IOWIRE ( 1275710 553920 ) ( *
675760 )
METAL7 16000 + SHAPE IOWIRE ( 1263310 533920 ) ( * 695760 )
METAL8 800 + SHAPE IOWIRE ( 1250910 529120 ) ( * 675760 )

6.2.7 PAIR Constraint

PAIR constraint is used to control the paring between bumps and pads, especially for
PG connection because it’s common case for PG bumps and pads to have multiple
bumps to multiple pads connection requirements and the user need to define the paring.
Both AIO and PIO modes support this constraint. Also both Manhattan and 45 degree
routing support it.

The syntax of PAIR constraint is as below,

PAIR

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<net_name> <pad_name_list> <bump_name_list>

END PAIR

• This constraint supports following pairing pattern.

 One pad to one bump pairing

 Multiple pads to one bump pairing

✓ Turn on this feature with the option “-multiPadsToBump” in fcroute or
“-multipleConnection multiPadsToBump” in setFlipChipMode.

 Multiple bumps to one pad pairing

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✓ Turn on this feature with the option “-multiBumpsToPad” in fcroute or

“-multipleConnection multiBumpsToPad” in setFlipChipMode.

• If the specified bump is not assigned or assigned to another net which is different
from the specified net, fcroute will ignore it.

• For those IO pads or bumps not in the list but needed to be connected to the
specified net, fcroute will ignore them and only route the specified ones by PAIR
constraint for the same net.

6.2.8 Resistance Driven Constraint

The designer may constrain the net resistance during routing. Both AIO and PIO modes
support this feature. Also both Manhattan and 45 degree routing support it.

The syntax of Resistance Driven Constraint is as below,

NETS
MAXRES <value>
WIDTHRANGE min_value: max_value
<net_name_list >
END NETS

• MAXRES is the maximum resistance value allowed for the nets defined in the
constraint.
• WIDTHRANGE specifies a variable width. The router is allowed to use any width
value between these two limits to avoid violating the max resistance.

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It’s recommended to add “srouteFCReportRes res_file_name” in the extra configure

file.

The resistance values achieved after routing will be written to this file. This file will report
the resistances in a table as follows:

#================================
#........Resistance Table........
# resSQ: 0.100 for METAL8
#================================
'int' 0.875
…
'port_pad_data_out[15]' Actual:3.159 Constraint:3.000

This information can be useful for debugging purposes. For accurate values of
resistance, it is recommended to run QRC (Cadence Signoff Extraction Tool). QRC can
be run from Innovus.

6.3 Useful extra configurations for flipchip routing

Flipchip router (fcroute) provides the user the capability to specify extra options into a
text file, which can be given as an input to the command fcroute –extraConfig or
setFlipChipMode –extraConfig. Because of the rich patterns in flipchip routing and
extensive customization of RDL routing, this file defines more options that are needed for
RDL routing when needed apart from general settings. The user can choose the ones
that can fit in their requests.

The options mentioned here are not completed but some options that usually asked by
customers. For special needs, please contact Cadence support.

• srouteFcroutePadPinTagging [TRUE | FALSE]

 It enables port numbering routing if it’s set to TRUE
 The default value is FALSE.

• srouteFcReportRes file_name
 It will write the resistance report into the specified file to help checking the
result with MAXRES constraint

• sroutePrevent45ForLowerLayer [TRUE | FALSE]

 It can prevent 45-degree routing for lower layer if it’s set to TRUE.
 The default value is FALSE.

• srouteRouteWidthForLowerLayer <value>
 It specifies different value for lower routing layer.
 The unit is DB unit.

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✓ For example, if DB unit is 2000 and the width for lower layer is 8 micro,
then this value should be set as 2000*8=16000.

• srouteConnectToEdgeOfBump [TRUE | FALSE]

 It specifies to connect wire to the edge of bump if it’s set to TRUE.
 The default value is FALSE.

• srouteConnectToAnyOfBump [TRUE | FALSE]

 If it’s set to TRUE, it means that it’s unnecessary for fcoute to route to the
center of bump but it’s acceptable to touch anywhere of bump geometry.
 The default value is FALSE.

• srouteConnectToCenterOfPin [TRUE | FALSE]

 If it’s set to TRUE, fcroute can connect to the center of any pin except bump.
 The default value is FALSE.
 It’s usually used when the width of the wire is less than the width of the pin.

• srouteExcludeBumpType <bump_cell_name>
 It specifies which bump cell will be excluded from fcroute.

• srouteExcludeRegion “llx1 lly1 ur1 ur1 llx2 lly2 urx2 ury2 …”

 It specifies the region to exclude bumps and pads from fcroute.
 It takes a string quoted by “” and in the string, multiple rectangular shapes are
defined even they are disjointed.
 The format of the string is like below,
"rect_ll_x rect_ll_y rect_ur_x rect_ur_y [more_rects]"
 The unit is DB unit.

6.4 Power Routing

There are two methodologies for connecting the power and ground bumps that can
coexist in the same design:
• PG bumps connect to the IO pads.
• PG bumps connect to rings or stripes.

6.4.1 PG bumps connect to IO pads

It is recommended that these connections are done at the same time as the signal
routing. Flipchip router (fcroute) has an option called –connectPowerCellToBump.
This option will tell the router to connect the bumps to the IO pads at the same time that
the signal routing is being done. The designer can also use the command
“setFlipChipMode – connectPowerCellToBump true” to turn on this feature.

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Example of power bump routing to IO pads

The command fcroute will automatically pair PG bumps with PG pads based on
routability with some intelligence if there are no specific pairing constraints by the user.
Also fcroute will choose the suitable pin for routing based on its intelligence if there is no
constraint by the user.

For more control of the connection between PG bumps and PG pads, the designer can
use the PAIR constraint in the constraint file or use port numbering feature.

6.4.2 PG bumps connect to rings or stripes

The command “fcroute –type power” can directly connect PG bumps to rings or stripes.
The connection between the bump and the stripes is done using fcroute.

The user can create some extra power and ground bumps are created to reduce the IR
drop. This is one of the advantages of the flipchip design.

The picture below shows the difference between “fcroute –type signal –designStyle
pio –connectPowerCellToBump”, “fcroute –type power” and “addStripe”.

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• Connect ground bump to IO pad by “fcroute –type signal –designStyle pio

-connectPowerCellToBump”, shown as (a)
• Connect power bump to block ring by “fcroute –type power”, shown as (b).

(a) (b)

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• Connect PG bumps to stripe by “fcroute –type power”, shown as (c).

• Connect PG bumps to stripe by “addStripe”, shown as (d).

(c) (d)

6.5 P2P router

Innovus supports a semi-automatic point-2-point router. The point-2-point router can be
accessed as following,

P2P router can be used for customized and special routing pattern generation.
• The usage is as below,

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 Select the widget of P2P router as above.

 Press F3 to set up P2P router.
 Click 1st object for the source.
 Click 2nd object for the target.

• How to set up P2P router

Press F3 for setting, and the GUI form is as below,

If not set net name, p2pRoute automatically picks up the net name based on the
objects selected in the GUI.

If not select “Use exact location”, p2pRoute performs an auto search to find an
acess point.
 “Use exact location” specifies to use the exact location clicked by user.
 “-offset x y” defines the maximum search offset from the original click location.
 The comparison of auto selection and “use exact location”

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“Guide points” allows the user to define a customized routing pattern and the user
can use this feature in following ways,
 Click “Draw” button in the form “Point to Point” -> click guide points in GUI ->
press “Esc” to return the locations of guide points to the text line of “Guide
points”-> click two objects for the source and target.
 Press “Shift” to turn on “Guide points”- > click guide points in GUI -> click two
objects for the source and target.
 Directly input the locations of the guide points to the text line of “Guide points” ->
click two objects for the source and target.

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6.6 Wire editing

Innovus supports a manual router wire editing. Wire editing can be accessed by
following,

Wire Edit Widge

• Edit Wire
 When you click this widget, the cursor changes to a pencil when moved into
the design area. You can add power or signal wires. Click at a start point and
move the cursor. A second click makes a turn. To end the route, double-click
the left mouse button. Click the Select widget or press the “a” keyboard
shortcut to return to select mode.
 Equivalent keyboard shortcut: Shift + A.
 Press F3 keyboard shortcut to set up “Edit Wire”
✓ If the user wants to use 45 degree routing, select the button “Allow 45
degree”.

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• Add Via
 When you click this widget, the cursor changes to a set of concentric squares
when moved into the design area. Press the F3 key to open the Edit Via form.
Click the Select widget or press the “a” keyboard shortcut to return to select
mode.
 Equivalent keyboard shortcut: o

• Move Wire
 When you click this widget, the cursor changes to a cross when moved into
the design area. Use the mouse or the arrow keys to move the wires. You can
move horizontal wires vertically and vertical wires horizontally. Click the Select
widget or press the “a” keyboard shortcut to return to select mode.
 Equivalent keyboard shortcut: m

• Cut Wire
 When you click this widget, the cursor changes to scissors when moved into
the design display area. Move the cursor to draw a draw a line indicating
where to cut a wire. The cut must go all the way through the wire. You can cut
special wires horizontally and vertically. The results retain the same direction
as the original wire. You can also cut rectangles. Signal wires maintain a
one-half wire width extension after being cut. Power wires do not maintain an
extension. Click the Select widget or press the “a” keyboard shortcut to return
to select mode.
 Equivalent keyboard shortcut: Shift + X

• Stretch Wire
 Click this widget to snap selected wires to the next manufacturing grid in the
direction that you move the cursor. Click the Select widget or press the “a”
keyboard shortcut to return to select mode.
 Equivalent keyboard shortcut: s

• Add Polygon
 When you click this widget, the cursor changes to a pencil whenmoved into the
design area. Click in the main window at the start point of the polygon and
move the cursor. Click once for each turn. Backspace to cancel the last point
in the wire. Double-click to commit the wire. Click the Select widget or press
the “a” keyboard shortcut to return to select mode.
 No equivalent keyboard shortcut.

The flow for flip chip routing is as below,

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7. Conclusions
The whole flipchip flow includes following parts,

• Data preparation
 LEF definition
✓ RDL layer
Its definition is similar as other layers’ in LEF.
✓ BUMP
The macro type of BUMP cells need to be CLASS COVER BUMP.
✓ IO pad
The macro type of IO pads need to be CLASS PAD AREAIO.
✓ Hardmacro
It keeps its original CLASS BLOCK and the PORTS definition is enhanced
to have a CLASS BUMP associated to it.
✓ CLASS BUMP attribute
It’s one type of the port. It explicitly indicates that the port is a bump
connection point and it can help user to distinguish which ports in one pin
are for flip chip flow. Only CLASS PAD AREAIO and CLASS BLOCK can
have CLASS BUMP attribute.

 Netlist
Bumps must not be defined in netlist while IO pads must be defined in netlist.
The relationship between bump and pad is constructed during bump
assignment. Then use flipchip router to connect IO pad to its assigned bump.
Defining bumps in netlist and assigning nets to these bumps is not a
compatible approach to Innovus and cannot be handled by Innovus.

• Flipchip floorplaning
 IO pads placement
The user has three choices to place peripheral IO pads,
✓ Read an IO file (loadIoFile) provided by the floorplanner architect or
package engineer.
✓ Load floorplan file (loadFPlan) provided by the floorplanner architect
✓ Automatic peripheral IO pad placement (placePIO), which also support IO
row flow.

 Bump creation
There are multiple ways to create bumps in the Cadence tools, the user can
create a single bump or bump array by using the command create_bump

 Bump assignment
The user can use automatic assignment (assignBump) or manual
assignment (assignSigToBump for signal assignment, assignPGBumps for

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power assignment). And port numbering approach allows user explicitly to

specify connection between pads to bumps during the assignment stage

 Bump assignment optimization

The tool offers two methods for bump assignment optimization.
✓ Automatic optimization (placePIO –assignBump -noRandomPlacement)
It will consider the constraints given by the command setFlipChipMode
–constraintFile and call global flipchip router for optimal results in
routability

✓ Manual optimization(swapSignal)
It helps the user to perform minor ECOs on the assigned bumps. It
supports multiple bumps to multiple bumps.

 IO pad optimization ( placePIO –optIOs –noRandomPlacement)

The global flipchip router will be called to improve the pad placement and it
respects the fix attribute applied to the IO pads.

• Power planning
 It is advisable NOT to use the RDL layer before pad to bump routing, as
flipchip router is very sensitive to routing obstructions. The power routing, i.e.
stripe generation, with the RDL layer can be done after IO pads to bumps
routing
 The command addStripe provides 2 options for easier flipchip design support.
These options are:
✓ -over_bumps
This option will create a power stripe over PG bumps and the stripe
generation will STOP at the end of a valid PG bump.

✓ -between_bumps
This option will create a power stripe between PG bumps and the stripes
will NOT be created in areas where there are no PG bumps.

• RDL routing
 Flipchip router (fcroute) is mainly used for routing the nets between bumps
and IO PADs. And fcroute supports both signal and power routing. Also it
accepts two design styles – peripheral IO (PIO) and area IO (AIO). But it’s not
limited by design styles, which means the user can use AIO mode for some
specific purpose in PIO design. So usually AIO/PIO mode is used to describe
which design style is used for fcroute. Besides, fcoute can support TSV
routing, which can route TSV to bumps/stripes/instance pins.

 Flipchip router (fcroute) is an intelligent and predictable RDL router and it can
help the designer evaluate floorplan change based on the quick flip chip
routing result with some general setting such as routing layers and routing
width.

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 Flipchip router (fcroute) is also greatly extended by constraints and extra

configures options for customized requirements.
✓ All constraints are specified in a text file and they can be given as an input
to the command fcroute –constraintFile or setFlipChipMode
–constraintFile.
✓ All extra configure options are specified in a text file and they can be given
as an input to the command fcroute –extraConfig or setFlipChipMode
–extraConfig.

 The tool offers the user a semi-automatic point-2-point router.

✓ “Guide points” allows the user to define a customized routing pattern.
✓ “Use exact location” specifies to use the exact location clicked by the user.

 The tool also supports a manual router wire editing, which allows the user to
use 45 degree routing also move/cut/stretch wires.

The whole flipchip flow is shown as below,

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Verilog Netlist LEF Timing RC cdb

init_design IO file Digital SIP Layout

Yes
IO row flow createIoRow

No
placePIO
placePIO

floorplan snapFPlanIO –toIoRow

Manual HM/IO pad

placement and refinement

Fix manually placed pads and HMs

Automatic HM placement and floorplaning

Bump creation Digital SIP Layout

create_bump

Bump assignment
(assignBump) IO file

Can bumps Yes Yes

Can IO pads
be optimized? be optimized?

No No
Signal bump assignment &
IO pad placement opt Signal bump assignment opt IO pad placement opt
placePIO –optIOs placePIO –assignment placePIO –optIOs –assignment
-noRandomPlacement -noRandomPlacement -noRandomPlacement

Power planning
addRing/addStripe/sroute

Wire editing Flipchip routing Point to point router

• Manuel routing • Auto routing • Semi-auto routing
• 45 degree routing • High completion rate • Route with guide points
• Move/Cut/Stretch wires • Various constraints and • Route with the exact location
extra configure options

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