Dell Latitude 7290 LA-F311P R20 SBMLK12 13 AR MB
Uploaded by
Marcelo AmorettiDell Latitude 7290 LA-F311P R20 SBMLK12 13 AR MB
Uploaded by
Marcelo AmorettiA B C D E
COMPAL CONFIDENTIAL
Vinafix.com
1 MODEL NAME : DAZ20 (SBMLK 12) / DAZ30 (SBMLK 13) 1
PCB NO : LA-F311P
BOM P/N : 431A8V31L0X (12_AR)
431A8V31L5X (13_AR)
Steamboat MLK 12"/13" AR
Kabylake-U U22 & Kabylake-R U42
2017-12-29
REV : 2.0 (A01)
2
@ : Nopop Component 2
EMI@ : EMI Component
@EMI@ : EMI Nopop Component
ESD@ : ESDComponent
@ESD@ : ESD Nopop Component
RF@ : RF Component
@RF@ : RF Nopop Component
CXDP@ : XDP Component
3
CONN@ : Connector Component 3
ESPI@ : ESPI interface Component
LPC@ : External ESPI Component (SHD)
MB PCB
U42@ : KBL-R U42 Component
Part Number
DAA000EJ010
Description
PCB 263 LA-F311P REV0 MB AR 1
U22@ : KBL-R U22 Component
SB12@ : For SB12 System ID
Layout Dell logo
SB13@ : For SB13 System ID
4
DS3@ : Deep sleep Component 4
NDS3@ : Non Deep sleep Component DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
COPYRIGHT 2017
ALL RIGHT RESERVED
REV:A01
Power CKT : 0919 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Size Document Number
Cover Sheet
Rev
PWB: GD1PC GPIO map : 0821 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-F311P 2.0
Date: Friday, December 29, 2017 Sheet 1 of 58
A B C D E
A B C D E
Steamboat MLK 12&13 w/ AR Block Diagram Steamboat MLK 12&13 only support one DIMM
Reverse Type
Memory BUS (DDR4) DDR4-SO-DIMM X1
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eDP 14": Lane x 4; 12" :Lane x 2
2133 MHz on KBL-U
BANK 0, 1, 2, 3
EDP CONN 2400 MHz on KBL-R P20
1 1
P27 up to 16GB
USB2.0[8]
LCD Touch
P27
PCIE[5][6][7][8] USB2.0[5]
HDMI 1.4 HDMI INTEL Camera
CONN P21 DDI[1] P27 Trough eDP Cable
USB2.0[9] SLGC55544CVTR USB2.0[9]_PS
AR-SP DDI[2] USB POWER SHARE
TBT P22-23 P36 USB3.0 Conn
TypeC USB
P26 KABYLAKE_U MCP PS(Ext Port 1)
Right
U22 USB3.0[6] USB3.0[6] P36
PD Solution
USB2.0/SMBus TPS65982DC SMBus KABYLAKE_R MCP USB2.0[2] USB3.0 Conn
USB2.0[1] from PCH (Reserve) P24-25
U42 USB3.0[3]
(Ext Port 2)
Lef t Fr ont P37
2 2
PAGE 6~19
PCIE[1] PCIE[4] PCIE[3]
only 14"
HD Audio I/F
Card reader Intel Jacksonville M.2,3042 Key B
RTS5242 P29 WGI219LM P28 M.2,3030 Key A
WWAN/LTE SATA[2]/PCIE[9][10][11][12]
SPI
P30 WLAN+BT
P30
USB2.0[4] W25Q128JVSIQ
SD4.0 Transformer USB2.0[7] P8
ESPI
P29 P28 USB3.0[2] 128M 4K sector INT.Speaker
W25Q128JVSIQ P31
RJ45 P28 P8
128M 4K sector HDA Codec Universal Jack
reserve P31
ALC3246 P31
TPM1.2/2.0 Nuvoton
NPCT750JAAYX Dig. MIC
P27
P34
Trough eDP Cable
3 3
KB/TP CONN
SMSC KBC P38 LID SWITCH
LED board
MEC5105 M.2 2280
P32-33 SSD Conn P35
FAN CONN USH CONN
P33 P34
CPU&PCH XDP Port
P14
AUTOMATIC POWER
SWITCH(APS) P11
Smart Card TDA8034HN
USH TPM1.2 USB2.0[10]
BCM58102
RFID/NFC SPI
DC/DC Interface
P40
Fingerprint SPI
CONN POWER ON/OFF
4 SW & LED P39
4
USH board P34
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Block diagram
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 2 of 58
A B C D E
5 4 3 2 1
POWER STATES AR config
Signal SLP SLP SLP SLP ALWAYS M SUS RUN CLOCKS
USB3.0 SSIC PCIE SATA DESTINATION USB PORT# DESTINATION
S3# S4# S5# A# PLANE PLANE PLANE PLANE
State USB3.0-1 N/A 1 Reserve for Type C
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON
USB3.0-2 SSIC M.2 3042(LTE) 2 JUSB2-->Lef t Fr ont
S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH
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ON ON ON OFF OFF
USB3.0-3 JUSB2-->Lef t Fr ont 3 JUSB3-->Lef t Rear ( SB14 onl y)
D
USB3.0-4 JUSB3-->Lef t Rear ( SB14 onl y) 4 M2 3042(WWAN) D
S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF USB3.0-5 PCIE-1 Card Reader (PCIE) 5 Camera
S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF
USB3.0-6 PCIE-2 JUSB1-->Right 6 NA
PCIE-3 M.2 3030(WLAN) 7 M.2 3030(BT)
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF
PCIE-4 LOM 8 Touch Screen
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF PCIE-5 9 JUSB1-->Right
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF
PCIE-6 10 USH
Alpine Ridge - SP
PCIE-7 SATA-0
PM TABLE PCIE-8 SATA-1
+5V_ALW
PCIE-9
+3.3V_ALW PCIE-10 M.2 2280 SSD
+3.3V_ALW_DSW +3.3V_CV2 +5V_RUN (PCIex4 or SATA)
+3.3V_ALW_PCH +1.2V_MEM +3.3V_RUN
PCIE-11 SATA-1*
power
C plane +RTC_CELL +2.5V_MEM +0.6V_DDR_VTT PCIE-12 SATA-2 C
+1.8V_PRIM +1.0V_VCCST +1.8V_RUN
12" not support JUSB3
+1.0V_PRIM +VCC_CORE
+1.0V_PRIM_CORE +VCC_GT
+5V_ALW 2 +VCC_SA
State
+3.3V_ALW2 +1.0VS_VCCIO
+3.3V_RTC_LDO
+1.0V_MPHYGT
S0 ON ON ON
S3 ON ON OFF
S5 S4/AC ON OFF OFF
S5 S4/AC doesn't exist OFF OFF OFF
B B
A A
AR use 1086PP (10L)
Non AR use 1080PP (8L) DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Port assignment
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 3 of 58
5 4 3 2 1
5 4 3 2 1
CPU PWR
VCCSTG_EN
SIO_SLP_S4# TPS22961 PCH PWR
+1.2V_MEM (UZ26) +VCC_SFR_OC
GT3 PWR
SY8210A
(PU200) Peripheral Device PWR
0.6V_DDR_VTT_ON RUN_ON
TPS22961 SIO_SLP_S0# TYPE-C Power
Barrel Type-C +0.6V_DDR_VTT (UZ19) +1.0V_VCCSTG
ADAPTER ADAPTER
Vinafix.com TPS22961 SIO_SLP_S4#
(UZ21) +1.0V_VCCST
D D
PCH_PRIM_EN
SY8286R (SIO_SLP_SUS#)
(PU301) +1.0V_PRIM
RUN_ON
CHARGER TPS62134C
ISL9538 +PWR_SRC +5V_ALW (PU401) +1.0VS_VCCIO
ALW ON
(PU901) SYV828C
(PU102) TPS62134D PCH_PRIM_EN
(SIO_SLP_SUS#)
(PU402) +1.0V_PRIM_CORE
+5V_ALW2
RUN_ON AUD_PWR_EN
EM5209 EM5209
(UZ4) +5V_RUN (@UZ5) +5V_RUN_AUDIO
BATTERY
USB_PWR_SHR_VBUS_EN
SY8288B +3.3V_RTC_LDO SLGC55544C
(PU100) (UI3) +5V_USB_CHG_PWR
C C
ALW ON
USB_PWR_EN1#
+3.3V_ALW2 SY6288
(UI1) +USB_EX2_PWR
+3.3V_ALW
PCH_PRIM_EN RUN_ON
RT8097A (SIO_SLP_SUS#) AOZ1336
(PU501) +1.8V_PRIM (UZ8) +1.8V_RUN
CSD97396Q
ISL95808 CSD97396Q (PU610) AO6405 SIO_SLP_LAN#
(PU614) (PU612) CSD97396Q (QV1) +3.3V_LAN
EM5209
(PU613) (UZ2)
IMVP_VR_ON
AUX_EN_WOWL
IMVP_VR_ON
IMVP_VR_ON
U42@
EN_INVPWR
+3.3V_WLAN
@SIO_SLP_WLAN#
PCH_PRIM_EN
(SIO_SLP_SUS#)
+3.3V_ALW_PCH
B EM5209 @PCH_ALW_ON B
(UZ3)
RUN_ON 3.3V_TS_EN
+VCC_SA +VCC_GT +VCC_CORE +BL_PWR_SRC LP2301
+3.3V_RUN (QV8) +3.3V_TSP
3.3V_WWAN_EN
EM5209 3.3V_CAM_EN#
(UZ4) +3.3V_WWAN LP2301A
(QZ1) +3.3V_CAM
AUD_PWR_EN
EM5209
(@UZ5) +3.3V_RUN_AUDIO
ENVCC_PCH
G524B1T11U
TYPE-C (UV24) +LCDVDD
+5V_ALW
TPS65982D
(UT5)
+TBTA_Vbus_1(5V~20V)
+PP_HV(5V~20V)
A
+5V_ALW SIO_SLP_S4#
A
AP7361C
AP2204 AP2112K (PU503) +2.5V_MEM
(UT8) (UT7) +3.3V_VDD_PIC for DDR4
+5V_TBT_VBUS
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Power rails
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 4 of 58
5 4 3 2 1
5 4 3 2 1
1K 2.2K
1K
+3.3V_ALW_PCH 2.2K
+3.3V_RUN
AW44 MEM_SMBCLK 202
MEM_SMBDATA
DMN65D8LDW-7
BB43 200 DIMMA
DMN65D8LDW-7
KBL-R Vinafix.com 499
KBL-U 499
+3.3V_ALW_PCH
D D
AY44 SML0_SMBCLK 28
SML0_SMBDATA 31 LOM
BB39
AW45 AW42 53
51 XDP
1K
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH
1K
E11 D8
03 03
D7 UPD2_SMBCLK
2.2K
00
+3.3V_ALW
00 E7 UPD2_SMBDAT 2.2K
@2.2K 2.2K
+3.3V_ALW +3.3V_CV2
@2.2K 2.2K
01 B3 USH_SMBCLK M9
C E5 USH_SMBDAT USH C
01 L9
C12
2.2K USH/B
2.2K
02
E10
02 2.2K +3.3V_ALW +3.3V_TBTA_FLASH
KBC 2.2K
C3 UPD1_SMBCLK B5
04 DMN66D0LDW-7
B4 UPD1_SMBDAT PD
A5
04 DMN66D0LDW-7
MEC 5105
F7
05
B6
05
06 A12
06 N10
B B
07 M4
07 M7
08 C5
08 C8
09 F6
09 E9 2.2K
Charger
+3.3V_ALW
2.2K
10
100 ohm 7
N2 PBAT_CHARGER_SMBCLK
100 ohm 6
BATTERY
10 M3 PBAT__CHARGER_SMBDAT CONN
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Port assignment
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 5 of 58
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
UC1A CPU@ KBL-R U4+2
Rev_0.1
2 1 CPU_DP1_CTRL_CLK E55 C47
RC175
2
RC178
1
2.2K_0402_5%
CPU_DP1_CTRL_DATA
2.2K_0402_5%
AR (AR)/
Vinafix.com
<22>
<22>
<22>
CPU_DP1_N0
CPU_DP1_P0
CPU_DP1_N1
F55
E58
F58
DDI1_TXN[0]
DDI1_TXP[0]
DDI1_TXN[1]
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
C46
D46
C45
EDP_TXN0
EDP_TXP0
EDP_TXN1
<27>
<27>
<27>
2 1 CPU_DP2_CTRL_CLK <22> CPU_DP1_P1 F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TXP1 <27>
D RC176 2.2K_0402_5% HDMI(Non AR) <22> CPU_DP1_N2 G53 DDI1_TXN[2] EDP_TXN[2] B45 D
2 1 CPU_DP2_CTRL_DATA <22> CPU_DP1_P2 F56 DDI1_TXP[2] EDP_TXP[2] A47
RC177 2.2K_0402_5% <22> CPU_DP1_N3 G56 DDI1_TXN[3] EDP_TXN[3] B47
<22> CPU_DP1_P3 DDI1_TXP[3] EDP_TXP[3]
C50 E45
<22> CPU_DP2_N0 D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 EDP_AUXN <27>
<22> CPU_DP2_P0 C52 DDI2_TXP[0] EDP_AUXP EDP_AUXP <27>
<22> CPU_DP2_N1 D52 DDI2_TXN[1] B52
<22> CPU_DP2_P1 A50 DDI2_TXP[1] EDP_DISP_UTIL
AR (AR) <22> CPU_DP2_N2 B50 DDI2_TXN[2] G50 CPU_DP1_AUXN
<22> CPU_DP2_P2 D51 DDI2_TXP[2] DDI1_AUXN F50 CPU_DP1_AUXP CPU_DP1_AUXN <22>
<22> CPU_DP2_N3 C51 DDI2_TXN[3] DDI1_AUXP E48 CPU_DP1_AUXP <22>
<22> CPU_DP2_P3 DDI2_TXP[3] DDI2_AUXN F48 CPU_DP2_AUXN <22>
DDI2_AUXP G46 CPU_DP3_AUXN CPU_DP2_AUXP <22>
DISPLAY SIDEBANDS RSVD F46 CPU_DP3_AUXP PAD~D @ T1
CPU_DP1_CTRL_CLK L13 RSVD PAD~D @ T2
<22> CPU_DP1_CTRL_CLK CPU_DP1_CTRL_DATA L12 GPP_E18/DDPB_CTRLCLK L9
<22> CPU_DP1_CTRL_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 CPU_DP1_HPD <22>
CPU_DP2_CTRL_CLK N7 GPP_E14/DDPC_HPD1 L6 CPU_DP2_HPD <22> EDP_HPD 1 2
CPU_DP2_CTRL_DATA N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9 RC1 100K_0402_5%
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10
N11 GPP_E17/EDP_HPD EDP_HPD <27>
GPP_E23 N12 GPP_E22 R12
T120@ PAD~D GPP_E23 EDP_BKLTEN PANEL_BKLEN <27>
R11
RC2 2 1 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 EDP_BIA_PWM <27>
+1.0VS_VCCIO EDP_RCOMP EDP_VDDEN ENVDD_PCH <27>
KBL-RU42_BGA1356 1 OF 20
COMPENSATION PU FOR eDP
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
C C
UC1I CPU@ KBL-R U4+2
Rev_0.1
CSI-2
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
B B38 CSI2_DN3 CSI2_CLKN3 A26 B
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC3 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7
CSI2_DP4 GPP_D4/FLASHTRIG TBT_FORCE_PWR <22>
C33
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
CSI2_DP11 GPP_F12/EMMC_CMD
AT1 EMMC_RCOMP 1 2
EMMC_RCOMP RC4 200_0402_1%
KBL-RU42_BGA1356 9 OF 20
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (1/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 6 of 58
5 4 3 2 1
5 4 3 2 1
For DDR4
<20> DDR_A_DQS#[0..7]
DDR4, Ballout for side by side(Interleave) Vinafix.com <20> DDR_A_D[0..63]
<20> DDR_A_DQS[0..7]
D UC1C CPU@ KBL-R U4+2 D
<20> DDR_A_MA[0..16] Rev_0.1
UC1B CPU@ KBL-R U4+2
Interleave / Non-Interleaved
Rev_0.1 AF65 AN45
DDR_A_D0 AL71 AU53 DDR_A_CLK#0 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46
DDR_A_D1 AL68 DDR0_DQ[0] DDR0_CKN[0] AT53 DDR_A_CLK0 DDR_A_CLK#0 <20> AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45
DDR_A_D2 AN68 DDR0_DQ[1] DDR0_CKP[0] AU55 DDR_A_CLK#1 DDR_A_CLK0 <20> AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46
DDR_A_D3 AN69 DDR0_DQ[2] DDR0_CKN[1] AT55 DDR_A_CLK1 DDR_A_CLK#1 <20> AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1]
DDR_A_D4 AL70 DDR0_DQ[3] DDR0_CKP[1] DDR_A_CLK1 <20> AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56
DDR_A_D5 AL69 DDR0_DQ[4] BA56 DDR_A_CKE0 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55
DDR_A_D6 AN70 DDR0_DQ[5] DDR0_CKE[0] BB56 DDR_A_CKE1 DDR_A_CKE0 <20> AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55
DDR_A_D7 AN71 DDR0_DQ[6] DDR0_CKE[1] AW56 DDR_A_CKE2 DDR_A_CKE1 <20> AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDR_A_D8 AR70 DDR0_DQ[7] DDR0_CKE[2] AY56 DDR_A_CKE3 PAD~D @ T3 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDR_A_D9 AR68 DDR0_DQ[8] DDR0_CKE[3] PAD~D @ T4 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
DDR_A_D10 AU71 DDR0_DQ[9] AU45 DDR_A_CS#0 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42
DDR_A_D11 AU68 DDR0_DQ[10] DDR0_CS#[0] AU43 DDR_A_CS#1 DDR_A_CS#0 <20> AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42
DDR_A_D12 AR71 DDR0_DQ[11] DDR0_CS#[1] AT45 DDR_A_ODT0 DDR_A_CS#1 <20> AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42
DDR_A_D13 AR69 DDR0_DQ[12] DDR0_ODT[0] AT43 DDR_A_ODT1 DDR_A_ODT0 <20> AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1]
DDR_A_D14 AU70 DDR0_DQ[13] DDR0_ODT[1] DDR_A_ODT1 <20> AH69 DDR1_DQ[14]/DDR0_DQ[30]
DDR_A_D15 DDR0_DQ[14] DDR1_DQ[15]/DDR0_DQ[31] DDR3L / LPDDR3 / DDR4
AU69 AT66 AY48
DDR0_DQ[15] DDR3L / LPDDR3 / DDR4
BA51 DDR_A_MA5 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] BB54 DDR_A_MA9 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48
DDR_A_D16 Interleave / Non-Interleaved DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR_A_MA6 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
BB65 BA52 AN65 BB48
DDR_A_D17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDR_A_MA8 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48
DDR_A_D18 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDR_A_MA7 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52
DDR_A_D19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDR_A_BG0 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50
DDR_A_D20 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 DDR_A_MA12 DDR_A_BG0 <20> AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48
DDR_A_D21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 DDR_A_MA11 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53
DDR_A_D22 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDR_A_ACT# AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52
DDR_A_D23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDR_A_BG1 DDR_A_ACT# <20> AP60 DDR1_DQ[25]/DDR0_DQ[57] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] BA43
DDR_A_D24 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] AU46 DDR_A_MA13 DDR_A_BG1 <20> AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43
DDR_A_D25 AW61 DDR0_DQ[24]/DDR0_DQ[40] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDR_A_MA15 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44
C DDR_A_D26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDR_A_MA14 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 C
DDR_A_D27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDR_A_MA16 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44
DDR_A_D28 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDR_A_BA0 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47
DDR_A_D29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] AY51 DDR_A_MA2 DDR_A_BA0 <20> AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44
DDR_A_D30 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDR_A_BA1 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46
DDR_A_D31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 DDR_A_MA10 DDR_A_BA1 <20> AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46
DDR_A_D32 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 DDR_A_MA1 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46
DDR_A_D33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 DDR_A_MA0 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR_A_D34 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] AP40 DDR1_DQ[36]/DDR1_DQ[20] BB46
DDR_A_D35 AW37 DDR0_DQ[34]/DDR1_DQ[2] BA50 DDR_A_MA3 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[3] BA47
DDR_A_D36 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDR_A_MA4 AR37 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[4]
DDR_A_D37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] AM70 DDR_A_DQS#0 AT33 DDR1_DQ[39]/DDR1_DQ[23]
DDR_A_D38 DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQSN[0] DDR_A_DQS0 DDR1_DQ[40]/DDR1_DQ[24] Interleave / Non-Interleaved
BA37 AM69 AU33 AH66
DDR_A_D39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSP[0] AT69 DDR_A_DQS#1 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[0]/DDR0_DQSN[2] AH65
DDR_A_D40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSN[1] AT70 DDR_A_DQS1 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[0]/DDR0_DQSP[2] AG69
DDR_A_D41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSP[1] AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[1]/DDR0_DQSN[3] AG70
DDR_A_D42 AY33 DDR0_DQ[41]/DDR1_DQ[9] AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[1]/DDR0_DQSP[3] AR66
DDR_A_D43 DDR0_DQ[42]/DDR1_DQ[10] Interleave / Non-Interleaved DDR_A_DQS#2 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[2]/DDR0_DQSN[6]
AW33 BA64 AR30 AR65
DDR_A_D44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDR_A_DQS2 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[2]/DDR0_DQSP[6] AR61
DDR_A_D45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDR_A_DQS#3 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[3]/DDR0_DQSN[7] AR60
DDR_A_D46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDR_A_DQS3 AU27 DDR1_DQSP[3]/DDR0_DQSP[7] AT38
DDR_A_D47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDR_A_DQS#4 AT27 DDR1_DQ[48] DDR1_DQSN[4]/DDR1_DQSN[2] AR38
DDR_A_D48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDR_A_DQS4 AT25 DDR1_DQ[49] DDR1_DQSP[4]/DDR1_DQSP[2] AT32
DDR_A_D49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDR_A_DQS#5 AU25 DDR1_DQ[50] DDR1_DQSN[5]/DDR1_DQSN[3] AR32
DDR_A_D50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDR_A_DQS5 AP27 DDR1_DQ[51] DDR1_DQSP[5]/DDR1_DQSP[3]
DDR_A_D51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDR_A_DQS#6 AN27 DDR1_DQ[52] AR25
DDR_A_D52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDR_A_DQS6 AN25 DDR1_DQ[53] DDR1_DQSN[6] AR27
DDR_A_D53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDR_A_DQS#7 AP25 DDR1_DQ[54] DDR1_DQSP[6] AR22
DDR_A_D54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDR_A_DQS7 AT22 DDR1_DQ[55] DDR1_DQSN[7] AR21
DDR_A_D55 BB29 DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQSP[7]/DDR1_DQSP[5] AU22 DDR1_DQ[56] DDR1_DQSP[7] AN43
DDR1_PAR,DDR1_ALERT# for DDR4
DDR_A_D56 AY27 DDR0_DQ[55]/DDR1_DQ[39] AW50 DDR_A_ALERT# DDR0_PAR,DDR0_ALERT# for DDR4 AU21 DDR1_DQ[57] DDR1_ALERT# AP43
DDR_A_D57 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_ALERT# AT52 DDR_A_PARITY DDR_A_ALERT# <20> AT21 DDR1_DQ[58] DDR1_PAR AT13 DDR_DRAMRST#
B DDR_A_D58 AY25 DDR0_DQ[57]/DDR1_DQ[41] DDR0_PAR DDR_A_PARITY <20> AN22 DDR1_DQ[59] DDR CH - B DRAM_RESET# AR18 SM_RCOMP0 DDR_DRAMRST# <20> B
DDR_A_D59 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR CH - A AY67 AP22 DDR1_DQ[60] DDR_RCOMP[0] AT18 SM_RCOMP1
DDR_A_D60 DDR0_DQ[59]/DDR1_DQ[43] DDR_VREF_CA +DDR_VREF_A_DQ +DDR_VREF_CA DDR1_DQ[61] DDR_RCOMP[1] SM_RCOMP2
BB27 AY68 AP21 AU18
DDR_A_D61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR0_VREF_DQ BA67 +DDR_VREF_B_DQ PAD~D @ T132 AN21 DDR1_DQ[62] 3 OF 20 DDR_RCOMP[2]
DDR_A_D62 BA25 DDR0_DQ[61]/DDR1_DQ[45] DDR1_VREF_DQ PAD~D @ T226 DDR1_DQ[63]
DDR_A_D63 BB25 DDR0_DQ[62]/DDR1_DQ[46] 2 OF 20 AW67 KBL-RU42_BGA1356
DDR0_DQ[63]/DDR1_DQ[47] DDR_VTT_CNTL DDR_VTT_CTRL <20>
KBL-RU42_BGA1356
DDR4 COMPENSATION SIGNALS
SM_RCOMP0 RC5 1 2 121_0402_1%
SM_RCOMP1 RC6 1 2 80.6_0402_1%
SM_RCOMP2 RC7 1 2 100_0402_1%
CAD Note:
Trace width=12~15 mil, Spacing=20 mils
Max trace length= 500 mil
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (2/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 7 of 58
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
SPI_MOSI= SPI_IO0
SPI_MISO= SPI_IO1
PCH EDS R0.7 p.235~236
For BR/SB
2
UC1E CPU@ KBL-R U4+2
Rev_0.1
SPI - FLASH
SMBUS, SMLINK
MEM_SMBCLK 6 1
PCH_SPI_CLK AV2 R7 MEM_SMBCLK DDR_XDP_WAN_SMBCLK <14,20>
Vinafix.com
PCH_SPI_D1 AW3 SPI0_CLK
SPI0_MISO
GPP_C0/SMBCLK
GPP_C1/SMBDATA
R8 MEM_SMBDATA QC2A
5
CXDP@RC10 1 2 1K_0402_1% PCH_SPI_D0 AV3 R10 PCH_SMB_ALERT# DMN65D8LDW-7_SOT363-6
<14> PCH_SPI_DO_XDP CXDP@RC11 1 2 1K_0402_1% PCH_SPI_D2 AW2 SPI0_MOSI GPP_C2/SMBALERT#
<14> PCH_SPI_DO2_XDP PCH_SPI_D3 AU4 SPI0_IO2 R9 SML0_SMBCLK MEM_SMBDATA 3 4
D PCH_SPI_CS#0 AU3 SPI0_IO3 GPP_C3/SML0CLK W2 SML0_SMBDATA SML0_SMBCLK <28> DDR_XDP_WAN_SMBDAT <14,20> D
PCH_SPI_CS#1 AU2 SPI0_CS0# GPP_C4/SML0DATA W1 GPP_C5 SML0_SMBDATA <28> QC2B
PCH_SPI_CS#2 AU1 SPI0_CS1# GPP_C5/SML0ALERT# DMN65D8LDW-7_SOT363-6 +3.3V_RUN
<34> PCH_SPI_CS#2 SPI0_CS2# SML1_SMBCLK
W3
GPP_C6/SML1CLK V3 SML1_SMBDATA SML1_SMBCLK <32>
SPI - TOUCH GPP_C7/SML1DATA AM7 GPP_B23 SML1_SMBDATA <32> DDR_XDP_WAN_SMBDAT1 2
M2 GPP_B23/SML1ALERT#/PCHHOT# RC318 2.2K_0402_5%
M3 GPP_D1/SPI1_CLK DDR_XDP_WAN_SMBCLK1 2
J4 GPP_D2/SPI1_MISO RC319 2.2K_0402_5%
V1 GPP_D3/SPI1_MOSI +3.3V_ALW_PCH
V2 GPP_D21/SPI1_IO2 AY13 ESPI_IO0_R RC3661 2 15_0402_5%
M1 GPP_D22/SPI1_IO3 GPP_A1/LAD0/ESPI_IO0 BA13 ESPI_IO1_R ESPI_IO0 <32,33>
LPC RC3671 2 15_0402_5%
GPP_D0/SPI1_CS# GPP_A2/LAD1/ESPI_IO1 BB13 ESPI_IO2_R ESPI_IO1 <32,33> MEM_SMBCLK
RC3681 2 15_0402_5% ESPI_IO2 <32,33>
1 2
GPP_A3/LAD2/ESPI_IO2 AY12 ESPI_IO3_R RC3691 2 15_0402_5% RC12 1K_0402_5%
C LINK GPP_A4/LAD3/ESPI_IO3 BA12 ESPI_IO3 <32,33> MEM_SMBDATA 1 2
G3 GPP_A5/LFRAME#/ESPI_CS# BA11 ESPI_CS# <32,33> RC14 1K_0402_5%
<30> PCH_CL_CLK1 G2 CL_CLK GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# <32,33> SML1_SMBCLK 1 2
<30> PCH_CL_DATA1 G1 CL_DATA RC15 1K_0402_5%
<30> PCH_CL_RST1# CL_RST# AW9 ESPI_CLK EMI@ RC16 1 2 15_0402_5% SML1_SMBDATA 1 2
GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 PCI_CLK_LPC1 @ RC22 1 2 22_0402_5% ESPI_CLK_5105 <32,33> RC17 1K_0402_5%
AW13 GPP_A10/CLKOUT_LPC1 AW11 CLKRUN# SML0_SMBCLK 1 2
GPP_A0/RCIN# GPP_A8/CLKRUN# RC347 499_0402_1%
AY11 SML0_SMBDATA 1 2
<32> ESPI_ALERT# GPP_A6/SERIRQ CHECK,LPC_CLK FOR DEBUG CARD? RC348 499_0402_1%
RC21 2 1 8.2K_0402_1%
+3.3V_1.8V_ESPI 5 OF 20
KBL-RU42_BGA1356 Reserve
+3.3V_LAN
SML0_SMBCLK 1 2
C @ RC19 499_0402_1% C
SML0_SMBDATA 1 2
SOFTWARE TAA RF Request
@ RC20 499_0402_1%
PCH_SPI_CLK_1_R PCH_SPI_CLK_0_R ESPI_CLK_5105 1 2
@RF@ CC316 33P_0402_50V8J
33_0402_5%
33_0402_5%
1
1
@EMI@
@EMI@
RPC1 CLKRUN# 1 2
RC28
RC29
LPC@ RC27 8.2K_0402_5%
PCH_SPI_D1_R1 1 8 PCH_SPI_D1_0_R SML0_SMBCLK 1 2
<34> PCH_SPI_D1_R1 PCH_SPI_D0_R1 2 7 PCH_SPI_D0_0_R
+3.3V_SPI @RF@ CC318 33P_0402_50V8J
2
<34> PCH_SPI_D0_R1 PCH_SPI_CLK_R1 3 6 PCH_SPI_CLK_0_R
<34> PCH_SPI_CLK_R1
33P_0402_50V8J
33P_0402_50V8J
PCH_SPI_D3_R1 4 5 PCH_SPI_D3_0_R SML1_SMBCLK 1 2 +3.3V_ALW_PCH
2 1 PCH_SPI_D2_R1 @RF@ CC319 33P_0402_50V8J
@EMI@
@EMI@
1
@ RC30 1K_0402_5% 33_0804_8P4R_5%
2 1 PCH_SPI_D3_R1 MEM_SMBCLK 1 2
CC7
CC8
@ RC31 1K_0402_5% @RF@ CC320 33P_0402_50V8J PCH_SMB_ALERT# 1 2
2
RC23 2.2K_0402_5%
2 1 PCH_SPI_D3_R1
@ RC316 1K_0402_5% TLS CONFIDENTIALITY
Place close CPU side HIGH ENABLE
03/02:follow Intel MOW_2015WW06
PCH_SPI_D3_R1 @ RC407 1 2 33_0402_5% PCH_SPI_D3_1_R LOW(DEFAULT) DISABLE
PCH_SPI_CLK_R1@ RC408 1 2 33_0402_5% PCH_SPI_CLK_1_R WEAK INTERNAL 20K PD
PCH_SPI_D0_R1 @ RC409 1 2 33_0402_5% PCH_SPI_D0_1_R
PCH_SPI_D1_R1 @ RC410 1 2 33_0402_5% PCH_SPI_D1_1_R
+3.3V_ALW_PCH
B B
GPP_C5 1 2
ESPI@RC25 4.7K_0402_5%
+3.3V_SPI
EC interface
JSPI1 CONN@
CC9 2 1 PCH_SPI_CS#1_R1 1
HIGH ESPI
1 2 @RC32 0_0402_5% PCH_SPI_CS#1 2 1 LOW(DEFAULT) LPC
1 2 PCH_SPI_D0_R1 3 2 WEAK INTERNAL 20k PD
128Mb Flash ROM 0.1U_0201_10V6K @ RC33 0_0402_5% PCH_SPI_D0 4 3
UC5 1 2 PCH_SPI_D1_R1 5 4
PCH_SPI_CS#0_R1 @ RC37 1 2 0_0402_5% PCH_SPI_CS#0_R2 1 8 @ RC34 0_0402_5% PCH_SPI_D1 6 5
PCH_SPI_D1_0_R 2 /CS VCC 7 PCH_SPI_D3_0_R 1 2 PCH_SPI_CLK_R1 7 6
PCH_SPI_D2_R1 RC39 1 2 33_0402_5% PCH_SPI_D2_0_R 3 IO1 IO3 6 PCH_SPI_CLK_0_R @ RC35 0_0402_5% PCH_SPI_CLK 8 7 +3.3V_ALW_PCH
4 IO2 CLK 5 PCH_SPI_D0_0_R 1 2 PCH_SPI_CS#0_R1 9 8
GND IO0 @ RC36 0_0402_5% PCH_SPI_CS#0 10 9
W25Q128JVSIQ_SO8 1 2 PCH_SPI_D2_R1 11 10
@ RC38 0_0402_5% PCH_SPI_D2 12 11 GPP_B23 1 2
+3.3V_SPI 1 2 PCH_SPI_D3_R1 13 12 RC317 150K_0402_5%
@ RC40 0_0402_5% PCH_SPI_D3 14 13
@ CC10 15 14
+3.3V_SPI 15
1 2 16
128Mb Flash ROM +3.3V_ALW_PCH
17 16 EXI BOOT STALL BYPASS
0.1U_0201_10V6K 1 2 18 17
@ RC41 19 18 HIGH ENABLED
@ UC6 0_0402_5%
PCH_SPI_CS#1_R1 @ RC42 1 2 0_0402_5% PCH_SPI_CS#1_R2 1 8 20 19 LOW(DEFAULT) DIABLED
PCH_SPI_D1_1_R 2 /CS VCC 7 PCH_SPI_D3_1_R 21 20 WEAK INTERNAL PD
PCH_SPI_D2_R1 @ RC43 1 2 33_0402_5% PCH_SPI_D2_1_R 3 IO1 IO3 6 PCH_SPI_CLK_1_R 22 GND1
4 IO2 CLK 5 PCH_SPI_D0_1_R GND2
GND IO0 CVILU_CF5020FD0R0-05-NH
A W25Q128JVSIQ_SO8 A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (3/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 8 of 58
5 4 3 2 1
5 4 3 2 1
For BR/SB
UC1F CPU@ KBL-R U4+2
+3.3V_RUN Rev_0.1
<29> MEDIACARD_IRQ#
Vinafix.com AN8
LPSS ISH
P2 MEM_INTERLEAVED
ONE_DIMM# AP7 GPP_B15/GSPI0_CS# GPP_D9 P3
D RC5601 2 0_0402_5% TPM_PIRQ#_R AP8 GPP_B16/GSPI0_CLK GPP_D10 P4 AR_DET# D
<34> TPM_PIRQ# GPP_B17/GSPI0_MISO GPP_D11
2 1 PCH_3.3V_TS_EN NRB_BIT AR7 P1
@ RC282 100K_0402_5% GPP_B18/GSPI0_MOSI GPP_D12
AM5 M4
@ RC5611 2 0_0402_5% SIO_EXT_SCI# AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3
2 1 SIO_EXT_SCI# AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
<27> PCH_3.3V_TS_EN BBS_BIT6 AN5 GPP_B21/GSPI1_MISO N1
RC237 10K_0402_5%
2 1 LPSS_UART2_RXD GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
@ RC402 49.9K_0402_1% @ RC4052 1 100K_0402_5% GPP_C8 AB1 GPP_D8/ISH_I2C1_SCL
2 1 LPSS_UART2_TXD AB2 GPP_C8/UART0_RXD AD11 ISH_I2C2_SDA +1.8V_RUN
@ RC403 49.9K_0402_1%
<33> SBIOS_TX TYPEC_CON_SEL1 W4 GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12 ISH_I2C2_SCL ISH_I2C2_SDA <30> WWAN
TYPEC_CON_SEL2 AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL ISH_I2C2_SCL <30>
GPP_C11/UART0_CTS#
LPSS_UART2_RXD AD1 U1
9/24: Reserve for embedded locat i on,r ef er I nt el PDG 0. 9 ISH_I2C2_SDA 1 2
LPSS_UART2_TXD AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2 ISH_UART0_RXD <30>
RC363 1K_0402_5%
AD3 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3 ISH_UART0_TXD <30> ISH_I2C2_SCL 1 2
AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4 ISH_UART0_RTS# <30> WLAN RC362 1K_0402_5%
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# ISH_UART0_CTS# <30>
+3.3V_ALW_PCH AC1
U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2 SIO_EXT_WAKE# <32>
GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD RTD3_CIO_PWR_EN <22> +3.3V_RUN
U6 AC3
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4 LCD_CBL_DET# <27>
2 1 SIO_EXT_WAKE# <38> I2C1_SDA_TP U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
RC283 10K_0402_5% U9 GPP_C18/I2C1_SDA AY8 CLKDET#
2 1 LPSS_UART2_RXD <38> I2C1_SCK_TP GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8 PAD~D @ T258 LCD_CBL_DET# 1 2
@ RC330 49.9K_0402_1% AH9 GPP_A19/ISH_GP1 BB7 RC287 100K_0402_5%
2 1 LPSS_UART2_TXD AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7
@ RC331 49.9K_0402_1% GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7 TPM_TYPE
AH11 GPP_A22/ISH_GP4 AW7 LID_CL#_PCH
AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13 PAD~D @ T268 TPM_TYPE 1 2
Reserved
GPP_F7/I2C3_SCL Sx_EXIT_HOLDOFF# / GPP_A12 / BM_BUSY# / ISH_GP6 @ RC349 100_0402_1%
AF11
C AF12 GPP_F8/I2C4_SDA GPP_A GROUP is +1.8V C
GPP_F9/I2C4_SCL
KBL-RU42_BGA1356 6 OF 20
+3.3V_ALW_PCH +3.3V_ALW_PCH
+3.3V_RUN
2
+3.3V_RUN
2 1 NRB_BIT RC371 @ RC400
10K_0402_5%
@ RC186 4.7K_0402_5% 10K_0402_5% 10K_0402_5%
2
RC267
1
NO REBOOT STRAP
CONN@ MEM_INTERLEAVED AR_DET#
HIGH No REBOOT
1
JUART1
LOW(DEFAULT) REBOOT ENABLE ONE_DIMM# 1
LPSS_UART2_RXD 2 1
Weak IPD 2
1
LPSS_UART2_TXD
10K_0402_5%
3
3
1
@ RC268
4
+5V_ALW 4 @
5 10K_0402_5% 10K_0402_5%
6 GND RC372 RC401
2
GND
2
CVILU_CI1804M1VRA-NH DIMM TYPE AR_DET#
B +3.3V_ALW_PCH HIGH Interleave HIGH NON AR B
DIMM Detect
2 1 BBS_BIT6 LOW Non-Interleave LOW AR
@ RC184 8.2K_0402_5%
HIGH 1 DIMM
LOW 2 DIMM
BOOT BIOS Dest i nat i on(Bi t 6
) +3.3V_ALW_PCH +3.3V_ALW_PCH
HIGH LPC
LOW(DEFAULT) SPI
2
Internal 20k PD @ RC555 @ RC553
10K_0402_5% 10K_0402_5%
1
TYPEC_CON_SEL1 TYPEC_CON_SEL2
1
@ RC556 @ RC554
10K_0402_5% 10K_0402_5%
2
2
A Vendor JAE FOXCON TBD TBD A
TYPEC_CON_SEL1 LOW LOW HIGH HIGH
TYPEC_CON_SEL2 LOW HIGH LOW HIGH DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (4/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 9 of 58
5 4 3 2 1
5 4 3 2 1
Steamboat MLK 12&13 AR
UC1H CPU@ KBL-R U4+2
Rev_0.1
Vinafix.com PCIE / USB3 / SATA
SSIC / USB3
H8
USB3_1_RXN G8
D H13 USB3_1_RXP C13 D
<29> PCIE_PRX_DTX_N1 G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13
<29> PCIE_PRX_DTX_P1 B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP
Card Reader RTS5242-----> <29> PCIE_PTX_DRX_N1 A17 PCIE1_TXN/USB3_5_TXN J6
<29> PCIE_PTX_DRX_P1 PCIE1_TXP/USB3_5_TXP USB3_2_RXN / SSIC_RXN H6 USB3_PRX_DTX_N2 <30>
G11 USB3_2_RXP / SSIC_RXP B13 USB3_PRX_DTX_P2 <30>
<36> USB3_PRX_DTX_N6 F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN / SSIC_TXN A13 USB3_PTX_DRX_N2 <30> -----> M.2 3042(LTE)
Ext USB3 Port 1 Charge (Right) -----> <36> USB3_PRX_DTX_P6 D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP / SSIC_TXP USB3_PTX_DRX_P2 <30>
<36> USB3_PTX_DRX_N6 C16 PCIE2_TXN/USB3_6_TXN J10
<36> USB3_PTX_DRX_P6 PCIE2_TXP/USB3_6_TXP USB3_3_RXN H10 USB3_PRX_DTX_N3 <37>
H16 USB3_3_RXP B15 USB3_PRX_DTX_P3 <37>
<30> PCIE_PRX_DTX_N3 G16 PCIE3_RXN USB3_3_TXN A15 USB3_PTX_DRX_N3 <37> -----> Ext USB3 Port 2 (Lef t Fr ont)
M.2 3030(WLAN) ---> <30> PCIE_PRX_DTX_P3 D17 PCIE3_RXP USB3_3_TXP USB3_PTX_DRX_P3 <37>
<30> PCIE_PTX_DRX_N3 C17 PCIE3_TXN E10
<30> PCIE_PTX_DRX_P3 PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
<28> PCIE_PRX_DTX_N4 F15 PCIE4_RXN USB3_4_TXN D15
<28> PCIE_PRX_DTX_P4 B19 PCIE4_RXP USB3_4_TXP
10/100/1G LAN ---> <28> PCIE_PTX_DRX_N4 A19 PCIE4_TXN AB9
<28> PCIE_PTX_DRX_P4 PCIE4_TXP USB2N_1 AB10 USB20_N1 <24>
F16 USB2P_1 USB20_P1 <24> -----> Opt i on t o t ype C ( P D)
<22> PCIE_PRX_DTX_N5 E16 PCIE5_RXN AD6
<22> PCIE_PRX_DTX_P5 C19 PCIE5_RXP USB2N_2 AD7 USB20_N2 <37>
<22> PCIE_PTX_DRX_N5 D19 PCIE5_TXN USB2P_2 USB20_P2 <37> -----> Ext USB Port 2 (Lef t Fr ont)
<22> PCIE_PTX_DRX_P5 PCIE5_TXP AH3
G18 USB2N_3 AJ3
<22> PCIE_PRX_DTX_N6 F18 PCIE6_RXN USB2P_3
<22> PCIE_PRX_DTX_P6 D20 PCIE6_RXP AD9
<22> PCIE_PTX_DRX_N6 C20 PCIE6_TXN USB2N_4 AD10 USB20_N4 <30>
<22> PCIE_PTX_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 <30> -----> M2 3042(WWAN)
F20 AJ1
AR(PCIE5~8) ---> <22> PCIE_PRX_DTX_N7 E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2 USB20_N5 <27>
C <22> PCIE_PRX_DTX_P7 B21 PCIE7_RXP/SATA0_RXP
USB2
USB2P_5 USB20_P5 <27> -----> Camera C
<22> PCIE_PTX_DRX_N7 A21 PCIE7_TXN/SATA0_TXN AF6
<22> PCIE_PTX_DRX_P7 PCIE7_TXP/SATA0_TXP USB2N_6 AF7
G21 USB2P_6
<22> PCIE_PRX_DTX_N8 F21 PCIE8_RXN/SATA1A_RXN AH1
<22> PCIE_PRX_DTX_P8 D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2 USB20_N7 <30>
<22> PCIE_PTX_DRX_N8 C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 <30> -----> M.2 3030(BT)
<22> PCIE_PTX_DRX_P8 PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9 USB20_N8 <27>
<35> PCIE_PRX_DTX_N9 E23 PCIE9_RXN USB2P_8 USB20_P8 <27> -----> LCD Touch
<35> PCIE_PRX_DTX_P9 B23 PCIE9_RXP AG1
<35> PCIE_PTX_DRX_N9 A23 PCIE9_TXN USB2N_9 AG2 USB20_N9 <36>
<35> PCIE_PTX_DRX_P9 PCIE9_TXP USB2P_9 USB20_P9 <36> -----> Ext USB Port 1 Charge (Right)
F25 AH7
<35> PCIE_PRX_DTX_N10 E25 PCIE10_RXN USB2N_10 AH8 USB20_N10 <34>
<35> PCIE_PRX_DTX_P10 D23 PCIE10_RXP USB2P_10 USB20_P10 <34> -----> USH
<35> PCIE_PTX_DRX_N10 C23 PCIE10_TXN AB6 USBCOMP RC44 1 2 113_0402_1%
<35> PCIE_PTX_DRX_P10 PCIE10_TXP USB2_COMP AG3 USB2_ID @ RC337 1 2 0_0402_5%
PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC338 1 2 1K_0402_5%
RC45 1 2 100_0402_1% PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9
D56 GPP_E9/USB2_OC0# C9 USB_OC0# <36>
<14> CPU_XDP_PRDY# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC2# USB_OC1# <37>
<14> CPU_XDP_PREQ# BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9 USB_OC3# Reserve
GPP_A7/PIRQA# GPP_E12/USB2_OC3#
E28 J1
<35> PCIE_PRX_DTX_N11 E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2
<35> PCIE_PRX_DTX_P11 D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 M3042_DEVSLP <30>
<35> PCIE_PTX_DRX_N11 C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2 M2280_DEVSLP <35>
<35> PCIE_PTX_DRX_P11 E30 PCIE11_TXP/SATA1B_TXP H2 SATAGP0 Reserve
M2 2280 SSD (4 Lane) ---> <35> PCIE_PRX_DTX_N12 F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 M3042_PCIE#_SATA
<35> PCIE_PRX_DTX_P12 A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 M2280_PCIE_SATA# M3042_PCIE#_SATA <32>
NEED DOUBLE CHECK
B <35> PCIE_PTX_DRX_N12 B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 M2280_PCIE_SATA# <35> B
<35> PCIE_PTX_DRX_P12 PCIE12_TXP/SATA2_TXP H1 SATALED#
GPP_E8/SATALED# SATALED# <35,39>
KBL-RU42_BGA1356 8 OF 20 +3.3V_ALW_PCH
RPC3
USB_OC3# 4 5
USB_OC0# 3 6
USB_OC1# 2 7
USB_OC2# 1 8
10K_8P4R_5%
+3.3V_RUN
RPC4
M2280_PCIE_SATA# 4 5
SATALED# 3 6
2 7
SATAGP0 1 8
10K_8P4R_5%
M3042_PCIE#_SATA 2 1
RC412 10K_0402_5%
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (5/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 10 of 58
5 4 3 2 1
5 4 3 2 1
For KBL-R U22 CC21
U22@
1 2
U22@RC46
12P_0402_50V8J
2
1M_0402_1%
UC1J CPU@ KBL-R U4+2
3
4
Rev_0.1
CLOCK SIGNALS U22@YC1
KBL-U / KBL-R U4+2 XTAL24_IN_U42_CPU XTAL24_IN_U42
E3 U42@ RC417 1 2 0_0402_5% 24MHZ_12PF_X3G024000DC1H
D42 RSVD_E3/XTAL24_IN C7 XTAL24_OUT_U42_CPU U42@ RC418 1 2 0_0402_5% XTAL24_OUT_U42
<29> CLK_PCIE_N0
1
2
CLKOUT_PCIE_N0 RSVD_C7/XTAL24_OUT XTAL24_IN_U22_CPU XTAL24_IN_U22
Vinafix.com
C42 E37 U22@ RC419 1 2 0_0402_5%
<29> CLK_PCIE_P0 CLKREQ_PCIE#0_R CLKOUT_PCIE_P0 XTAL24_IN/NC_2 XTAL24_OUT_U22_CPU XTAL24_OUT_U22 XTAL24_IN_U22
@RF@ RC373 1 2 0_0402_5% AR10 E35 U22@ RC420 1 2 0_0402_5% CC22
U22@
Cardreader---> <29> CLKREQ_PCIE#0
RC189 2 1 10K_0402_5% GPP_B5/SRCCLKREQ0# XTAL24_OUT/NC_1 XTAL24_OUT_U22 1 2
+3.3V_RUN
B42
D <30> CLK_PCIE_N1 CLKOUT_PCIE_N1 CLK_ITPXDP_N D
A42 F43 @ RC297 1 2 0_0402_5% For Skylake,YC1 24 MHz (50 Ohm ESR) 12P_0402_50V8J
<30> CLK_PCIE_P1 CLKREQ_PCIE#1_R CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N CLK_ITPXDP_P CLK_ITPXDP_N_R <14> For Cannonlake,YC1 38.4 MHz (30 Ohm ESR)
WLAN---> @RF@ RC374 1 2 0_0402_5% AT7 E43 @ RC298 1 2 0_0402_5%
<30> CLKREQ_PCIE#1 GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P CLK_ITPXDP_P_R <14>
+3.3V_RUN RC47 2 1 10K_0402_5% 546765_546765_2014WW48_Skylake_MOW_Rev_1_0
D41 BA17 SUSCLK
CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK <30,35>
C41
RC50 2 1 10K_0402_5% CLKREQ_PCIE#2_R AT8 CLKOUT_PCIE_P2
+3.3V_RUN
<35> CLK_PCIE_N3
<35> CLK_PCIE_P3 CLKREQ_PCIE#3_R
D40
C40
GPP_B7/SRCCLKREQ2#
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3 XCLK_BIASREF
E42 XCLK_BIASREF 1 2 +1.0V_CLK5
For KBL-R U42 CC334
U42@
1 2
M.2 SDD---> @RF@ RC376 1 2 0_0402_5% AT10 RC52 2.7K_0402_1%
<35> CLKREQ_PCIE#3 GPP_B8/SRCCLKREQ3# PCH_RTCX1
U42@RC415
+3.3V_RUN RC59 2 1 10K_0402_5% AM18 1 2 For Skylake, pop RC52,depop RC324 12P_0402_50V8J
RTCX1
2
PCH_RTCX2
1M_0402_1%
B40 AM20 @ RC324 59_0402_1% For Cannonlake, pop RC324,depop RC52
<28> CLK_PCIE_N4 CLKOUT_PCIE_N4 RTCX2
3
4
A40 546765_546765_2014WW48_Skylake_MOW_Rev_1_0
<28> CLK_PCIE_P4 CLKREQ_PCIE#4_R CLKOUT_PCIE_P4
LAN---> @RF@ RC377 1 2 0_0402_5% AU8 AN18 SRTCRST# RC56 1 2 20K_0402_5% +RTC_CELL_PCH
U42@YC3
<28> CLKREQ_PCIE#4 GPP_B9/SRCCLKREQ4# SRTCRST#
+3.3V_RUN RC51 2 1 10K_0402_5% AM16 24MHZ_12PF_X3G024000DC1H
E40 RTCRST# CC24 1 2 1U_0402_6.3V6K
1
2
<22> CLK_PCIE_N5 E38 CLKOUT_PCIE_N5
<22> CLK_PCIE_P5 CLKREQ_PCIE#5_R CLKOUT_PCIE_P5 PCH_RTCRST# <32> XTAL24_IN_U42
@RF@ RC378 1 2 0_0402_5% AU7 CC335
U42@
AR ---> <22> CLKREQ_PCIE#5
RC190 2 1 10K_0402_5% GPP_B10/SRCCLKREQ5# PCH_RTCRST# RC57 1 2 20K_0402_5% XTAL24_OUT_U42 1 2
+3.3V_RUN
CC25 1 2 1U_0402_6.3V6K For Skylake,YC3 24 MHz (50 Ohm ESR) 12P_0402_50V8J
KBL-RU42_BGA1356 10 OF 20
CC23
1 2 PCH_RTCX1 1 2
1 2 PCH_RTCX2
PCH_PLTRST# @ RC62 1 2 0_0402_5% 15P_0402_50V8J
PLTRST_LAN# <28>
SHORT PADS~D
1
+3.3V_LAN
@ RC244 1 2 0_0402_5% @ CMOS1 RC54 YC2
PCH_PLTRST#_EC <33>
32.768KHZ_12.5PF_9H03200042
CMOS1 must take care short & touch risk on layout placement 10M_0402_5%
ESR MAX=50k ohm
2
C 2 1 LAN_WAKE# +3.3V_ALW_PCH C
1
@ RL70 10K_0402_5% CC26
PCH_PLTRST# 1 2 1 2PCH_RTCX2_R 1 2
+3.3V_ALW_DSW PLTRST_TPM# <34>
@ RC60 0_0402_5% @ RC296 0_0402_5%
5
12P_0402_50V8J
1 PCH_PLTRST#_AND 1 2
P
2 1 B 4 PCH_PLTRST#_AND @ RC325 0_0402_5% +3.3V_ALW_DSW
O PCH_PLTRST#_AND <22,29,30,34,35>
RC323 10K_0402_5% 2 8/21 can change to 10K for merge to RP
A
1
G
UC7
2 1 PCH_PCIE_WAKE# TC7SH08FU_SSOP5~D @ RC65 PCH_BATLOW# 1 2
3
RC67 1K_0402_5% 100K_0402_5% @DS3@ RC441 RC72 8.2K_0402_5%
SIO_SLP_SUS# 1 2 AC_PRESENT 1 2
<18> VCCDSW_EN_GPIO PCH_PRIM_EN <17,40,44,45,46> RC243 10K_0402_5%
2
+1.0V_VCCST 0_0402_5%
RC445 NDS3@ DC1 NDS3@ RC442 +RTC_CELL_PCH
2 1 VCCST_PWRGD H_CPUPWRGD VCCST_PWRGD 1 2 2 1 VCCDSW_EN_Q 1 2
<32> VCCDSW_EN
RC71 1K_0402_5%
100P_0402_50V8J
ESD@
100P_0402_50V8J
ESD@
0_0402_5% RB751S40T1G_SOD523-2 0_0402_5% INTRUDER# 1 2
+3.3V_ALW_PCH RC69 1M_0402_5%
1
NDS3@ DC2
2 1 ME_SUS_PWR_ACK 1 2 +3.3V_ALW_PCH
<38,42> ALW_PWRGD_3V_5V MPHYP_PWR_EN
CC300
CC301
@ RC74 10K_0402_5% 1 2
2
10/6 depop, prevent singal step. RB751S40T1G_SOD523-2 @ RC387 10K_0402_5%
VRALERT# 1 2
2 1 PCH_PWROK @ RC73 10K_0402_5%
@ RC411 10K_0402_5% UC1K CPU@ KBL-R U4+2
Rev_0.1 RC439RC440RE536RC215RC441RC442 1 2
ESD Request:place near CPU side SYSTEM POWER MANAGEMENT @ RC344 10K_0402_5%
AT11 SIO_SLP_S0#
GPP_B12/SLP_S0# SIO_SLP_S0# <17,34,45> +3.3V_ALW
AP15 Support DS3 V X V X V X
PCH_PLTRST# GPD4/SLP_S3# SIO_SLP_S3# <22,32,33>
AN10 BA16
SYS_RESET# GPP_B13/PLTRST# GPD5/SLP_S4# SIO_SLP_S4# <17,32,43,46> SIO_SLP_LAN#
B5 AY16 1 2
B PCH_RSMRST#_AND SYS_RESET# GPD10/SLP_S5# SIO_SLP_S5# <32> B
AY17 No Support DS3 X V X V X V @ RC68 10K_0402_5%
<14,38> PCH_RSMRST#_AND RSMRST# AN15
H_CPUPWRGD_R @ RC77 1 2 1K_0402_5% H_CPUPWRGD A68 SLP_SUS# AW15 SIO_SLP_SUS# <32>
T9 @ PAD~D PROCPWRGD SLP_LAN# SIO_SLP_LAN# <32,40>
RC78 1 2 60.4_0402_1% VCCST_PWRGD_CPU B65 BB17 'V' mean POP, 'X' mean DE-POP SUSCLK 1 2
<14,32,33> VCCST_PWRGD VCCST_PWRGD GPD9/SLP_WLAN# SIO_SLP_WLAN# <32,40>
AN16 @ RC48 1K_0402_5%
B6 GPD6/SLP_A# SIO_SLP_A# <32>
<14,32> SYS_PWROK SYS_PWROK
BA20 BA15
<47> PCH_PWROK PCH_PWROK GPD3/PWRBTN# SIO_PWRBTN# <14,32>
BB20 AY15
<32> PCH_DPWROK DSW_PWROK GPD1/ACPRESENT PCH_BATLOW# AC_PRESENT <32>
AU13
@ RC444 1 2 0_0402_5% ME_SUS_PWR_ACK_R AR13 GPD0/BATLOW# JAPS1 CONN@
<32> ME_SUS_PWR_ACK SUSACK#_R GPP_A13/SUSWARN#/SUSPWRDNACK
@ RC443 1 2 0_0402_5% AP11 +3.3V_ALW_PCH 1
<32> SUSACK# GPP_A15/SUSACK# SIO_SLP_S3# 1
AU11 PME# 2
GPP_A11/PME# PAD~D @ T115 2
BB15 AP16 INTRUDER# +3.3V_ALW 3
<32,33> PCH_PCIE_WAKE# WAKE# INTRUDER# SIO_SLP_S5# 3
AM15 4
<28,32> LAN_WAKE# GPD2/LAN_WAKE# MPHYP_PWR_EN SIO_SLP_S4# 4
AW17 AM10 5
<28> PM_LANPHY_ENABLE GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# SIO_SLP_A# 5
AT15 AM11 VRALERT# 6
+3.3V_1.8V_PGPPA <27> 3.3V_CAM_EN# GPD7/RSVD GPP_B2/VRALERT# 6
+3.3V_ALW 7
connect to VCCMPHYGTAON_1P0 enable pin 8 7
2 1 SUSACK#_R 2 1 KBL-RU42_BGA1356 11 OF 20 PCH_RTCRST# 9 8
@ RC550 1K_0402_5% RC311 10K_0402_5% 10 9
11 10
<33,39> POWER_SW#_MB 11
12
SYS_RESET# 13 12
SYS_RESET# 14 13
1 2 +3.3V_RUN SIO_SLP_S0# 15 14
RC215 15
0.1U_0402_25V6
@ESD@
@ RC290 0_0402_5% 16
17 16
10K_0402_5%
POP NO Support Deep sleep 17
2
1
18
RC291 @
DE-POP Support Deep sleep +3.3V_RUN 18
XDP_DBRESET# 19
<14> XDP_DBRESET#
2
PCH_DPWROK 1 2 PCH_RSMRST#_AND GND
CC302
20
GND
5
NDS3@ RC215 0_0402_5%
1
A +3.3V_RUN 1 A
P
B
1
SYS_RESET#_R 1 SYS_RESET#
0.01UF_0402_25V7K
100K_0402_1%
1 4 2 CVILU_CF4218FH0R0-05-NH
ME_RESET# 2 O
@ CC266
RC75 2 1 RC224 1K_0402_5%
A
G
RC220
10K_0402_5% @ RC225 8.2K_0402_5% @ UC12 ESD Request:place near CPU side
2 1 74AHC1G09GW_TSSOP5
DELL CONFIDENTIAL/PROPRIETARY
3
2 @ RC227 8.2K_0402_5%
2
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
if pop UC12, RC291 also need pop(74AHC1G09GW is OD output)
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (6/14)
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 11 of 58
5 4 3 2 1
5 4 3 2 1
+1.0V_VCCSTG
PCH_JTAG_TDI 1 2
RC81 51_0402_5%
PCH_JTAG_TDO 1 2
RC82 100_0402_5%
PCH_JTAG_TMS 1 2
Vinafix.com H_CATERR# D63
UC1D CPU@ KBL-R U4+2
Rev_0.1 CPU_XDP_TCLK
@ RC328
1 2 XDP_JTAGX
0_0402_5%
RC130 51_0402_5%
A54 CATERR#
D <32> PECI_EC 1 2 PROCHOT#_R C65 PECI D
<32,47,50> PROCHOT# PROCHOT# JTA G
RC84 499_0402_1% H_THERMTRIP# C63
<20,33> H_THERMTRIP# A65 THERMTRIP#
SKTOCC# B61 CPU_XDP_TCLK
CPU MISC PROC_TCK CPU_XDP_TCLK <14>
C55 D60 CPU_XDP_TDI
<14> XDP_OBS0_R D55 BPM#[0] PROC_TDI A61 CPU_XDP_TDO CPU_XDP_TDI <14>
<14> XDP_OBS1_R XDP_OBS2_R B54 BPM#[1] PROC_TDO C60 CPU_XDP_TMS CPU_XDP_TDO <14>
T10 @ PAD~D XDP_OBS3_R BPM#[2] PROC_TMS CPU_XDP_TRST# CPU_XDP_TMS <14>
C56 B59
T11 @ PAD~D BPM#[3] PROC_TRST# CPU_XDP_TRST# <14> 1 2
+1.0V_VCCST SIO_EXT_SMI# A6 B56 PCH_JTAG_TCK @ RC86 51_0402_5%
A7 GPP_E3/CPU_GP0 PCH_JTAG_TCK D59 PCH_JTAG_TDI PCH_JTAG_TCK <14>
2 1 H_CATERR# <27> TOUCH_SCREEN_PD# TOUCHPAD_INTR# BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDI A56 PCH_JTAG_TDO PCH_JTAG_TDI <14>
<32,38> TOUCHPAD_INTR# AY5 GPP_B3/CPU_GP2 PCH_JTAG_TDO C59 PCH_JTAG_TMS PCH_JTAG_TDO <14>
@ RC79 49.9_0402_1%
2 1 H_THERMTRIP# <27> TOUCH_SCREEN_DET# GPP_B4/CPU_GP3 PCH_JTAG_TMS C61 CPU_XDP_TRST# PCH_JTAG_TMS <14>
RC80 1K_0402_5% CPU_POPIRCOMP AT16 PCH_TRST# A59 XDP_JTAGX 1 2
PCH_POPIRCOMP PROC_POPIRCOMP JTAGX +1.0V_VCCSTG
AU16 @ RC87 1K_0402_5%
+1.0V_VCCSTG EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
EOPIO_RCOMP H65 OPCE_RCOMP
2 1 PROCHOT# OPC_RCOMP
1
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
RC83 1K_0402_5%
RC88
RC89
RC90
RC91
KBL-RU42_BGA1356 4 OF 20
Service Mode Switch:
+3.3V_RUN Add a switch to ME_FWP signal to unlock the ME region and
2
allow the ent ir e r egi on of t he SPI f l ash to be updat ed us i ng FPT.
2 1 TOUCHPAD_INTR# +3.3V_ALW_PCH
RC414 10K_0402_5%
2 1 CAM_MIC_CBL_DET# ME_FWP 1 2 ME_FWP_PCH
RC413 10K_0402_5% @ RC221 0_0402_5%
2
PT,ST pop RC222 and SW1; MP pop RC221
@ RC222
C 2 1 CONTACTLESS_DET# 1K_0402_5% C
RC278 10K_0402_5%
2 1 TOUCH_SCREEN_PD# TOUCH_SCREEN_PD# don't move to RPC,
1
@RC272 10K_0402_5% @ SW1
2 1 AUD_PWR_EN 1
<32> ME_FWP A
RC279 10K_0402_5% 2
2 1 IR_CAM_DET# ME_FWP_PCH 3 B
RC345 100K_0402_5% 4 C
2 1 HOST_SD_WP# 5 G1
RC292 10K_0402_5% G2
SS3-CMFTQR9_3P
+3.3V_ALW_PCH ME_FWP PCH has internal 20K PD.
2 1 SIO_EXT_SMI# (suspend power rail)
RC346 10K_0402_5% FLASH DESCRIPTOR SECURITY OVERRIDE
UC1G CPU@ KBL-R U4+2
2 1 KB_DET# Rev_0.1
RC288 10K_0402_5%
LOW = ENABLE (DEFAULT) -->Pin1 & Pin3 short
AUDIO
HIGH = DISABLE (ME can update) -->Pin2 & Pin3 short
RC92 1 2 33_0402_5% HDA_SYNC BA22
<31> HDA_SYNC_R 1 2 HDA_BIT_CLK AY22 HDA_SYNC/I2S0_SFRM
EMI@ RC93 33_0402_5%
<31> HDA_BIT_CLK_R 1 2 HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
RC94 33_0402_5% SDIO / SDXC
<31> HDA_SDOUT_R ME_FWP_PCH 1 2 BA21 HDA_SDO/I2S0_TXD
RC223 1K_0402_5%
<31> HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11
1 2 33_0402_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13 CAM_MIC_CBL_DET# <27>
RC95
<31> HDA_RST#_R J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12 TBT_CIO_PLUG_EVENT#
AY20 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 W12 TBT_CIO_PLUG_EVENT# <22>
AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11 CONTACTLESS_DET#
HDA_BIT_CLK_R I2S1_TXD GPP_G4/SD_DATA3 W10 CONTACTLESS_DET# <34>
AK7 GPP_G5/SD_CD# W8 AUD_PWR_EN HOST_SD_WP# <29>
GPP_F1/I2S2_SFRM GPP_G6/SD_CLK AUD_PWR_EN <31>
47P_0402_50V8J
RF@ CC27
AK6 W7
GPP_F0/I2S2_SCLK GPP_G7/SD_WP
1
AK9
B AK10 GPP_F2/I2S2_TXD BA9 B
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
2
GPP_A16/SD_1P8_SEL
IR_CAM_DET# H5 AB7 SD_RCOMP RC96 1 2 200_0402_1%
<27> IR_CAM_DET# TBT_PWR_EN D7 GPP_D19/DMIC_CLK0 SD_RCOMP
T269@ PAD~D GPP_D20/DMIC_DATA0
Close to RC93
KB_DET# D8 AF13
<38> KB_DET# C8 GPP_D17/DMIC_CLK1 GPP_F23
GPP_D18/DMIC_DATA1
AW5
<31> SPKR GPP_B14/SPKR
KBL-RU42_BGA1356 7 OF 20
PCH_JTAG_TDO PCH_JTAG_TDI XDP_JTAGX H_THERMTRIP# PROCHOT#
0.1U_0402_25V6
@ESD@ CC303
0.1U_0402_25V6
@ESD@ CC304
0.1U_0402_25V6
@ESD@ CC305
0.1U_0402_25V6
@ESD@ CC312
0.1U_0402_25V6
@ESD@ CC310
1
1
RF Request. Place near CPU side (Intel MOW)
2
HDA_RST# HDA_SDIN0 HDA_SDOUT
+3.3V_ALW_PCH +3.3V_ALW_PCH
2 1 SPKR 2 1 HDA_SDOUT
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
@ RC183 8.2K_0402_5% @ RC187 4.7K_0402_5% 1 1 1 ESD request,Place near CPU side.
RF@ CC331
RF@ CC332
RF@ CC333
2 2 2
A TOP SWAP STRAP Flash Descriptor Security override A
HIGH ENABLE HIGH DISABLE
LOW(DEFAULT) DISABLE LOW(DEFAULT) ENABLE
Internal 20k PD
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (7/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 12 of 58
5 4 3 2 1
5 4 3 2 1
<14> CFG[0..19]
Vinafix.com
D D
CFG[2][5][6][7] for SKYLAKE-H CPU CFG strap pin
UC1S CPU@ KBL-R U4+2
Rev_0.1 UC1T CPU@ KBL-R U4+2
RESERVED SIGNALS-1 Rev_0.1
2 1 CFG0 SPARE
@ RC113 10K_0402_1% CFG0 E68 BB68 1/5 2014WW52 MOW reserve to support
2 1 CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 PAD~D @ T12 Cannonlake-U PCH compatibility AW69 F6
CFG2 D65 CFG[1] RSVD_TP_BB69 PAD~D @ T13 AW68 RSVD_AW69 RSVD_F6
@ RC112 10K_0402_1% close UC1.U11/U12 and <400mil
2 1 CFG3 D67 CFG[2] AK13 AU56 RSVD_AW68 C11
CFG4 E70 CFG[3] RSVD_TP_AK13 AK12 PAD~D @ T14 +1.8V_PRIM +VCC_1P8 AW48 RSVD_AU56 RSVD_C11 B11
@ RC110 10K_0402_1%
C68 CFG[4] RSVD_TP_AK12 PAD~D @ T15 RSVD_AW48 RSVD_B11 A11
CFG5
CFG6 D68 CFG[5] BB2 1 2 U12 RSVD_A11 D12
Stall reset sequence CFG7 C67 CFG[6] RSVD_BB2 BA3 @ RC313 0_0402_5% U11 RSVD_U12 RSVD_D12 C12
CFG[7] RSVD_BA3 RSVD_U11 RSVD_C12
1U_0402_6.3V6K
CFG8 F71 H11 F52
HIGH(DEFAULT) No stall(Normal Operat i on) CFG9 G69 CFG[8] 1 RSVD_H11 RSVD_F52
LOW stall CFG[9]
CC222
CFG10 F70 AU5
CFG11 G68 CFG[10] TP5 AT5
CFG12 H70 CFG[11] TP6 2 KBL-RU42_BGA1356 20 OF 20
CFG13 G71 CFG[12] @
CFG14 H69 CFG[13] D5
CFG15 G70 CFG[14] RSVD_D5 D4
CFG[15] RSVD_D4 B2
CFG16 E63 RSVD_B2 C2
CFG17 F63 CFG[16] RSVD_C2
CFG[17] B3
CFG18 E66 RSVD_B3 A3
CFG19 F66 CFG[18] RSVD_A3
C 2 1 CFG4 CFG[19] AW1 C
RC109 1K_0402_5% 2 1 CFG_RCOMP E60 RSVD_AW1
RC114 49.9_0402_1% CFG_RCOMP E1
2 1 ITP_PMODE E8 RSVD_E1 E2
+1.0V_PRIM_XDP ITP_PMODE RSVD_E2
RC115 1.5K_0402_5%
AY2 BA4
AY1 RSVD_AY2 RSVD_BA4 BB4
<14> ITP_PMODE RSVD_AY1 RSVD_BB4
eDP enable D1 A4
D3 RSVD_D1 RSVD_A4 C4
HIGH(DEFAULT) Disabled RSVD_D3 RSVD_C4
LOW Enabled K46 BB5
K45 RSVD_K46 TP4 PAD~D @ T130
RSVD_K45 A69
AL25 RSVD_A69 B69
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3
C71 RSVD_AY3
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54
BA70 AY4
T16 @ PAD~D RSVD_TP_BA70 TP1 PAD~D @ T126
BA68 BB3
T17 @ PAD~D RSVD_TP_BA68 TP2 PAD~D @ T127
J71 AY71
J68 RSVD_J71 VSS_AY71 AR56
RSVD_J68 ZVM#
1 2 F65 AW71
U42@RC436 G65 VSS_F65 RSVD_TP AW70 PAD~D @ T113
0_0402_5%
B VSS_G65 RSVD_TP PAD~D @ T114 B
F61 AP56
E61 RSVD_F61 MSM# C64 1 2
RSVD_E61 PROC_SELECT# +1.0V_VCCST
@ RC120 100K_0402_5%
For Skylake , RC120 depop
KBL-RU42_BGA1356 19 OF 20 For Cannonlake, RC120 pop
546765_546765_2014WW48_Skylake_MOW_Rev_1_0
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (8/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 13 of 58
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM +1.0V_PRIM_XDP
@ RC216 1 2 0_0603_5% +1.0V_PRIM_XDP CXDP@
CPU XDP XDP_PRSNT_PIN1 1
RC121
2 CFG3
0_0402_5% +1.0V_PRIM_XDP
<13> CFG[0..19]
1 2 +3.3V_RUN
@ RC122 0_0402_5%
+1.0V_PRIM_XDP JXDP1 CONN@ CC30
1 2 2 1
<10> CPU_XDP_PREQ#
CPU_XDP_PREQ# 3 1 2 4 CFG17 UC8
CPU_XDP_PRDY# 5 3 4 6
0.1U_0201_10V6K
0.1U_0201_10V6K
CFG16 0.1U_0201_10V6K
Vinafix.com
<10> CPU_XDP_PRDY# 5 6 8
@ CC28
@ CC29
1 1 7 14
CFG0 9 7 8 10 CFG8 VCC
CFG1 11 9 10 12 CFG9 TDO_XDP 2 3 CPU_XDP_TDO <12>
13 11 12 14 1A 1B
D 2 2 CFG2 15 13 14 16 CFG10 D
CFG3 17 15 16 18 CFG11 1
19 17 18 20 1OE
CXDP@ RC239 1 2 0_0402_5% XDP_OBS0 21 19 20 22 CFG19 TDI_XDP 5 6 CPU_XDP_TDI <12>
<12> XDP_OBS0_R XDP_OBS1 23 21 22 24 2A 2B
CXDP@ RC240 1 2 0_0402_5% CFG18
<12> XDP_OBS1_R 25 23 24 26
Place near CFG4 27 25 26 28 CFG12 4
JXDP1 CFG5 29 27 28 30 CFG13 2OE
31 29 30 32 XDP_TMS 9 8
RC5 need to close to JCPU1 31 32 34 3A 3B CPU_XDP_TMS <12>
CFG6 33 CFG14
@ RC123 1 2 1K_0402_5% CFG7 35 33 34 36 CFG15
<11,32,33> VCCST_PWRGD 37 35 36 38 10
<11,38> PCH_RSMRST#_AND CXDP@ RC1241 2 H_VCCST_PWRGD_XDP 39 37 38 40 3OE
41 39 40 42 CLK_ITPXDP_P_R <11> TRST#_XDP 12 11
1K_0402_5% CPU_XDP_TRST# <12>
FIVR_EN <11,32> SIO_PWRBTN# 41 42 44 CLK_ITPXDP_N_R <11> 4A 4B
@ RC2171 2 0_0402_5% 43
CFG0 @ RC1261 2 1K_0402_5% FIVR_EN_R 45 43 44 46 ITP_PMODE
RESET_OUT#_R 45 46 48 XDP_DBRESET# ITP_PMODE <13>
CXDP@ RC1281 2 0_0402_5% 47 XDP_DBRESET# <11> 13 7
<8> PCH_SPI_DO_XDP 49 47 48 50 <32> RUNPWROK 4OE GND
@ RC1291 2 0_0402_5%
<11,32> SYS_PWROK 51 49 50 52 TDO_XDP 15
<8,20> DDR_XDP_WAN_SMBDAT 53 51 52 54 TRST#_XDP GND PAD
<8,20> DDR_XDP_WAN_SMBCLK 55 53 54 56 TDI_XDP
<12> PCH_JTAG_TCK CPU_XDP_TCLK 57 55 56 58 XDP_TMS
<12> CPU_XDP_TCLK 57 58 60 74CBTLV3126BQ_DHVQFN14_2P5X3
59
61 59 60 PCH_SPI_DO2_XDP <8>
61
62 63
GND GND
+1.0V_VCCSTG
+1.0VS_VCCIO JXT_FP270H-061G1AM
CPU_XDP_TMS 1 2
2 1 FIVR_EN_R RC131 51_0402_5%
C RC132 150_0402_5% CPU_XDP_TDI 1 2 C
+1.0V_VCCST RC134 51_0402_5%
CPU_XDP_TDO 1 2
2 1 FIVR_EN RC135 100_0402_5%
@ RC218 150_0402_5%
2 1 FIVR_EN CPU_XDP_TRST# 1 2
@ RC219 10K_0402_5% @ RC136 51_0402_5%
CPU_XDP_TCLK 1 2
+3.3V_ALW_PCH RC139 51_0402_5%
1.5K_0402_5%
CXDP@ RC133
2
+3.3V_ALW_DSW
1.5K_0402_5%
+3.3V_RUN
2
XDP_TMS
@ RC241
1 2
@ RC228
PCH_JTAG_TMS <12>
0_0402_5%
1
2 1 XDP_DBRESET# TDI_XDP 1 2
@ RC229
PCH_JTAG_TDI <12>
RC137 3K_0402_5% 0_0402_5%
+1.0V_PRIM_XDP PCH_SPI_DO_XDP TDO_XDP 1 2
Place near JXDP1.48 PCH_JTAG_TDO <12>
1
@ RC230 0_0402_5%
RESET_OUT#_R XDP_DBRESET# SIO_PWRBTN#
CPU_XDP_PREQ#
0.1U_0402_25V6
2 1
0.1U_0402_25V6
CXDP@ CC32
0.1U_0402_25V6
@ RC138 51_0402_5%
1
@ CC33
CC269
@
1
Place near JXDP1.41
2
2
2
TDO_XDP H_VCCST_PWRGD_XDP CPU_XDP_TRST#
B B
0.1U_0402_25V6
@ESD@ CC306
0.1U_0402_25V6
@ESD@ CC307
0.1U_0402_25V6
@ESD@ CC308
Place near JXDP1.47
1
2
2
ESD request,Place near JXDP1 side. ESD request,Place near UC8 side.
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (9/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 14 of 58
5 4 3 2 1
5 4 3 2 1
+VCC_CORE: 0.3~1.35V +VCC_CORE +VCC_CORE
PSC(Primary side cap) : Place as close to the package as possible
UC1L CPU@ KBL-R U4+2 BSC(Backside cap) : Place on secondary side, underneath the package
Rev_0.1
CPU POWER 1 OF 4
A30 G32
A34 VCC_A30 VCC_G32 G33
Component placement order:
A39 VCC_A34 VCC_G33 G35 Package edge > 0402 caps > 0805 caps > Bulk caps >Power source
A44 VCC_A39 VCC_G35 G37
AK33
AK35
AK37
VCC_A44
Vinafix.com
VCC_AK33
VCC_AK35
VCC_G37
VCC_G38
VCC_G40
G38
G40
G42
AK38 VCC_AK37 VCC_G42 J30
D AK40 VCC_AK38 VCC_J30 J33 D
AL33 VCC_AK40 VCC_J33 J37
AL37 VCC_AL33 VCC_J37 J40
AL40 VCC_AL37 VCC_J40 K33 +VCC_CORE
AM32 VCC_AL40 VCC_K33 K35
AM33 VCC_AM32 VCC_K35 K37
100_0402_1%
VCC_AM33 VCC_K37
2
AM35 K38
RC140
AM37 VCC_AM35 VCC_K38 K40
AM38 VCC_AM37 VCC_K40 K42
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43
1
+VCC_CORE_G0 K32 E32 VCCSENSE
T122@ PAD~D RSVD VCC_SENSE VCCSENSE <47>
E33 VSSSENSE
+VCC_CORE_G1 AK32 VSS_SENSE VSSSENSE <47>
T123@ PAD~D RSVD
1
H_CPU_SVIDALRT#
100_0402_1%
B63
AB62 VIDALERT# A63 VIDSCLK
VCCOPC_AB62 VIDSCK VIDSCLK <47>
RC141
P62 D64 VIDSOUT
V62 VCCOPC_P62 VIDSOUT
VCCOPC_V62 G20
2
H63 VCCSTG_G20
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
AE63 VCCOPC_SENSE
VSSOPC_SENSE +1.0V_VCCSTG_R@ RC143 1 2 0_0603_5%
+1.0V_VCCSTG
AE62
AG62 VCCEOPIO
VCCEOPIO
AL63
AJ62 VCCEOPIO_SENSE
VSSEOPIO_SENSE
C C
12 OF 20
RF Request
KBL-RU42_BGA1356
VIDSCLK 1 2
@RF@ CC321 33P_0402_50V8J
Place close CPU side
B B
+1.0V_VCCST
SVID ALERT
56_0402_1%
2
RC152
CAD Note: Place the PU resistors close to CPU
RC204 close to CPU 300 - 1500mils
1
2 1 H_CPU_SVIDALRT#
<47> VIDALERT_N
220_0402_5% RC153
+1.0V_VCCST
SVID DATA
2
100_0402_1%
CAD Note: Place the PU resistors close to CPU
RC157
RC208close to CPU 300 - 1500mils
1
A VIDSOUT A
<47> VIDSOUT
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (10/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 15 of 58
5 4 3 2 1
5 4 3 2 1
+VCCGT: 0.3~1.35V
+VCCGTX : 0.3~1.35V
KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on po wer page)
+VCC_GT_+VCC_CORE
Vinafix.com +VCC_GT
UC1M CPU@ KBL-R U4+2
D Rev_0.1 D
CPU POWER 2 OF 4
A48 KBL-U / KBL-R U4+2 N70
A53 VCCGT/VCCCORE_5 VCCGT N71
J43 VCCGT/VCCCORE_6 VCCGT R63
J45 VCCGT/VCCCORE_44 VCCGT R64
J46 VCCGT/VCCCORE_45 VCCGT R65
J48 VCCGT/VCCCORE_46 VCCGT R66
J50 VCCGT/VCCCORE_47 VCCGT R67
Follow KBL-R_U42_Processor_Line_BGA1356_Ballout_Rev1p0
J52 VCCGT/VCCCORE_48 VCCGT R68
K48 VCCGT/VCCCORE_49 VCCGT R69
K50 VCCGT/VCCCORE_57 VCCGT R70
1 2 K52 VCCGT/VCCCORE_58 VCCGT R71
+VCC_GT VCCGT/RSVD_6 VCCGT
@ RC437 0_0402_5% T62
A58 VCCGT U65
+VCC_GT VCCGT VCCGT
A62 U68
A66 VCCGT VCCGT U71
AA63 VCCGT VCCGT W63
AA64 VCCGT VCCGT W64
AA66 VCCGT VCCGT W65
AA67 VCCGT VCCGT W66
AA69 VCCGT VCCGT W67
AA70 VCCGT VCCGT W68
AA71 VCCGT VCCGT W69
AC64 VCCGT VCCGT W70
AC65 VCCGT VCCGT W71
KBL-R 4+2 and KBL-U 2+2&2+3e opt i on ( pl ace on po wer page)
AC66 VCCGT VCCGT Y62 +VCC_GT_+VCC_CORE
AC67 VCCGT VCCGT
AC68 VCCGT KBL-U / KBL-R U4+2 AK42
AC69 VCCGT VCCGTX_AK42/VCCCORE_12 AK43
AC70 VCCGT VCCGTX_AK43/VCCCORE_13 AK45
AC71 VCCGT VCCGTX_AK45/VCCCORE_14 AK46
C J53 VCCGT VCCGTX_AK46/VCCCORE_15 AK48 C
J55 VCCGT VCCGTX_AK48/VCCCORE_16 AK50
J56 VCCGT VCCGTX_AK50/VCCCORE_17 AL43
J58 VCCGT VCCGTX_AL43/VCCCORE_21 AL46
J60 VCCGT VCCGTX_AL46/VCCCORE_22 AL50
K53 VCCGT VCCGTX_AL50/VCCCORE_23 AM48
K55 VCCGT VCCGTX_AM48/VCCCORE_29 AM50
K56 VCCGT VCCGTX_AM50/VCCCORE_30 AM52
K58 VCCGT VCCGTX_AM52/VCCCORE_31 AK52 1 2
VCCGT VCCGTX_AK52/RSVD_5 +VCC_GT
K60 @ RC438 0_0402_5%
L62 VCCGT AK53
L63 VCCGT VCCGTX_AK53 AK55
+VCC_GTUS Reserve for soldering
L64 VCCGT VCCGTX_AK55 AK56
L65 VCCGT VCCGTX_AK56 AK58
L66 VCCGT VCCGTX_AK58 AK60
L67 VCCGT VCCGTX_AK60 AK70
L68 VCCGT VCCGTX_AK70 AL53
+VCC_GT L69 VCCGT VCCGTX_AL53 AL56
L70 VCCGT VCCGTX_AL56 AL60
L71 VCCGT VCCGTX_AL60 AM53
M62 VCCGT VCCGTX_AM53 AM56
100_0402_1%
VCCGT VCCGTX_AM56
2
N63 AM58
RC161
N64 VCCGT VCCGTX_AM58 AU58
N66 VCCGT VCCGTX_AU58 AU63
N67 VCCGT VCCGTX_AU63 BB57
N69 VCCGT VCCGTX_BB57 BB66
1
VCCGT VCCGTX_BB66
VCC_GT_SENSE J70 AK62
<47> VCC_GT_SENSE VSS_GT_SENSE J69 VCCGT_SENSE VCCGTX_SENSE AL61
<47> VSS_GT_SENSE VSSGT_SENSE VSSGTX_SENSE
1
100_0402_1%
KBL-RU42_BGA1356 13 OF 20
B B
RC163
2
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (11/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 16 of 58
5 4 3 2 1
5 4 3 2 1
+1.2V_MEM +VCC_SFR_OC
+VCCPLL_OC source 1 2
@ RZ119 0_0402_5%
+1.2V_MEM_CPUCLK +1.2V_MEM
UZ26
@ RC231
1 2
0_0402_5%
VDDQ: 8.45A
Vinafix.com
+1.2V_MEM 2
CZ102
1
1U_0402_6.3V6K
1
2 VIN1
VIN2
7 6 1 2
D PSC VIN thermal VOUT CZ103 0.1U_0201_10V6K D
3
+5V_ALW VBIAS
VCCSTG_EN
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 2 4 5
@ RZ120 0_0402_5% ON GND
1 1 1 1
CC176
CC177
CC178
CC179
+3.3V_ALW TPS22961DNYR_WSON8
+1.0VS_VCCIO @ CZ104
2 2 2 2 UC1N CPU@ KBL-R U4+2 1 2
Rev_0.1
5
CPU POWER 3 OF 4 0.1U_0402_10V7K
AU23 AK28 1
P
AU28 VDDQ_AU23 VCCIO AK30 <11,40,44,45,46> PCH_PRIM_EN B 4
PSC AU35 VDDQ_AU28 VCCIO AL30 2 O
VDDQ_AU35 VCCIO <11,17,32,43,46> SIO_SLP_S4# A
G
AU42 AL42
BB23 VDDQ_AU42 VCCIO AM28 @ UZ34
3
VDDQ_BB23 VCCIO
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 BB32 AM30 TC7SH08FU_SSOP5~D
VDDQ_BB32 VCCIO +VCC_SA
CC294
CC295
CC296
BB41 AM42
+1.2V_MEM_CPUCLK BB47 VDDQ_BB41 VCCIO
BB51 VDDQ_BB47 AK23
2 2 2 VDDQ_BB51 VCCSA AK25
PSC VCCSA G23
AM40 VCCSA G25
VDDQC VCCSA G27
VCCSA +1.0VS_VCCIO
10U_0402_6.3V6M
A18 G28
VCCST VCCSA J22
1 VCCSA
CC297
A22 J23
VCCSTG_A22 VCCSA J27
100_0402_1%
VCCSA
2
AL23 K23
2 VCCPLL_OC VCCSA K25
RC165
+1.0V_VCCST K20 VCCSA K27
K21 VCCPLL_K20 VCCSA K28 +1.0VS_VCCIO
C PSC VCCPLL_K21 VCCSA K30 C
1
VCCSA
AM23 VCCIO_SENSE
VCCIO_SENSE AM22 VSSIO_SENSE VCCIO_SENSE <45> PSC
+1.0V_VCCSTG VSSIO_SENSE VSSIO_SENSE <45>
1U_0402_6.3V6K
1
H21
BSC VSSSA_SENSE
CC195
H20
VCCSA_SENSE
1
100_0402_1%
100_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2 1 1 1 1
RC166
RC167
CC252
CC253
CC250
CC251
KBL-RU42_BGA1356 14 OF 20
+VCC_SFR_OC
1U_0402_6.3V6K
1 1 2
+VCC_SA 2 2 2 2
CC199
RC168 100_0402_1%
2
+1.0V_VCCST
2@ PSC
22U_0603_6.3V6M
22U_0402_6.3V6M
1U_0402_6.3V6K
2.2P_0402_50V8C
U22@ CC202
1 1
1 1 VSA_SEN- <47>
CC288
RF@ CC322
U42@CC341
VSA_SEN+ <47>
@ CC202
S0 S0Ix S3
2 2
2 2
1U_0402_6.3V6K SIO_SLP_S0# HIGH LOW LOW
SIO_SLP_S3# HIGH HIGH LOW
RF Request
AND HIGH LOW LOW
B B
+1.0V_VCCST source +1.0V_VCCSTG source
+1.0V_VCCSTG +1.0V_VCCST
1 2
@ RZ151 0_0603_5%
pop option with UZ19
1
+1.0V_PRIM
PJP2
UZ19 PAD-OPEN1x1m
+1.0V_PRIM PJP1 2 1 1
UZ21 2 1 CZ105 1U_0402_6.3V6K 2 VIN1
+1.0V_VCCST VIN2
2 1 1
2
CZ100 1U_0402_6.3V6K 2 VIN1 +5V_ALW 7 6 +1.0V_VCCSTG_C1 2
VIN2 PAD-OPEN1x1m VIN thermal VOUT CZ106 0.1U_0201_10V6K
+5V_ALW 7 6 +1.0V_VCCST_C 1 2 3
VIN thermal VOUT CZ101 0.1U_0201_10V6K VBIAS
3 +3.3V_ALW 4 5
VBIAS ON GND
4 5
<11,17,32,43,46> SIO_SLP_S4# ON GND TPS22961DNYR_WSON8
4.4mohm/6A
5
TPS22961DNYR_WSON8
1 TR=12.5us@Vin=1.05V
P
<11,34,45> SIO_SLP_S0# B 4 VCCSTG_EN
4.4mohm/6A 2 O
TR=12.5us@Vin=1.05V <32,33,40,45> RUN_ON
UZ35 A G
TC7SH08FU_SSOP5~D
3
A A
@ RZ320 1 2 0_0402_5%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (12/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 17 of 58
5 4 3 2 1
5 4 3 2 1
close UC1.AL1 and <120mil +1.0V_MPHYGT
+1.0V_PRIM
+1.0V_MPHYAON +1.0V_PRIM
+1.0VO_DSW +1.0V_PRIM_CORE
close UC1.K17 and <120mil close UC1.AB19 and <400mil
PCH PWR close UC1.Y16 and <400mil +1.0V_SRAM
+3.3V_PGPPB @ RC309 1 2 0_0603_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 close UC1.AG15 and <120mil
+3.3V_PGPPC +3.3V_PGPPE
@ CC205
@ CC206
Vinafix.com +1.0V_APLLEBB
CC203
CC204
1U_0402_6.3V6K
1
@ CC265
+1.0V_MPHYAON UC1O KBL-R U4+2 close UC1.T16 and <400mil
Imax : 2.57A 2 2 2 2
1U_0402_6.3V6K
1U_0402_6.3V6K
Rev_0.1 1 1 @ RC310 1 2 0_0603_5%
CPU POWER 4 OF 4
@ CC207
@ CC208
@ RC299 1 2 0_0603_5%
D AB19 Must be +1.8V 2 D
AB20 VCCPRIM_1P0 AK15
VCCPRIM_1P0 VCCPGPPA +3.3V_1.8V_PGPPA 2 2
+1.0V_CLK6 P18 AG15
VCCPRIM_1P0 VCCPGPPB Y16 +3.3V_1.8V_PGPPG
close UC1.AF18 and <400mil VCCPGPPC
@ RC300 1 2 0_0402_5% AF18 Y15
VCCPRIM_CORE VCCPGPPD +3.3V_PGPPD
AF19 T16 close UC1.AD15 and <400mil
VCCPRIM_CORE VCCPGPPE
1U_0402_6.3V6K
V20 AF16 1
VCCPRIM_CORE VCCPGPPF +1.8V_PGPPF +3.3V_ALW_PCH
CC326
+1.0V_DTS V21 AD15
VCCPRIM_CORE VCCPGPPG +3.3V_1.8V_PGPPG
@ RC301 1 2 0_0402_5% AL1 V19
DCPDSW_1P0 VCCPRIM_3P3_V19 2
+1.8V_PRIM
1U_0402_6.3V6K
K17 T1 1
VCCMPHYAON_1P0 VCCPRIM_1P0_T1 +1.0V_DTS
@ CC209
+1.0V_CLK1 L1
VCCMPHYAON_1P0 AA1
VCCATS_1P8 close UC1.AA1 and <400mil
@ RC302 1 2 0_0402_5% +1.0V_MPHYGT N15
VCCMPHYGT_1P0_N15 +RTC_CELL_PCH 2
1U_0402_6.3V6K
N16 AK17 1
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +3.3V_ALW_PCH
close UC1.N15 and CC210 <400mil, CC211 <120mil N17
VCCMPHYGT_1P0_N17
CC212
+1.0V_CLK3 P15 AK19
P16 VCCMPHYGT_1P0_P15 VCCRTC_AK19 BB14
VCCMPHYGT_1P0_P16 VCCRTC_BB14 close UC1.AK19 and <120mil 2
close UC1.V19 and <120mil
47U_0805_6.3V6M
1U_0402_6.3V6K
0.1U_0201_10V6K
1U_0402_6.3V6K
@ RC303 1 2 0_0402_5% 1 1 1 1
@ CC210
K15 BB10 +DCPRTC
+1.0V_AMPHYPLL VCCAMPHYPLL_1P0 DCPRTC
CC211
CC270
CC213
L15 close UC1.BB10 and <120mil
VCCAMPHYPLL_1P0
0.1U_0201_10V6K
A14 1
2 2 VCCCLK1 +1.0V_CLK1 2 2
V15
+1.0V_APLL VCCAPLL_1P0
CC214
K19
+1.8V_PRIM VCCCLK2 +1.0V_CLK2
+1.8V_PGPPF AB17
+1.0V_PRIM VCCPRIM_1P0_AB17 2
Y18 L21
VCCPRIM_1P0_Y18 VCCCLK3 +1.0V_CLK3
@ RC304 1 2 0_0402_5%
AD17 N20
+3.3V_ALW_DSW VCCDSW_3P3_AD17 VCCCLK4 +1.0V_CLK4
AD18 RF Request
+3.3V_1.8V_PGPPG AJ17 VCCDSW_3P3_AD18 L19 +1.0V_CLK6
VCCDSW_3P3_AJ17 VCCCLK5 +1.0V_CLK5
C @ RC234 1 2 0_0402_5% AJ19 A10 +1.0V_APLL +3.3V_VCCHDA +1.0V_APLLEBB C
+3.3V_VCCHDA VCCHDA VCCCLK6
close UC1.A10 and <120mil
+1.0V_SRAM
1U_0402_6.3V6K
AJ16 AN11 CORE_VID0 <45> 1
+3.3V_ALW_PCH +3.3V_SPI VCCSPI GPP_B0/CORE_VID0
@ CC216
AN13 CORE_VID1 <45>
AF20 GPP_B1/CORE_VID1
close UC1.AF20 and <400mil VCCSRAM_1P0
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
@ RC235 1 2 0_0402_5% AF21 1 1 1
+3.3V_ALW_PCH VCCSRAM_1P0 2
1U_0402_6.3V6K
T19
1 VCCSRAM_1P0 Take care!!! Note1 on Page 19
@ CC217
RF@ CC323
RF@ CC324
RF@ CC325
T20
+3.3V_1.8V_PGPPA +1.0V_PRIM VCCSRAM_1P0
AJ21 2 2 2
LPC@ RC211 1 2 0_0402_5% 2 +1.0V_APLLEBB VCCPRIM_3P3_AJ21
AK20
+3.3V_1.8V_ESPI VCCPRIM_1P0_AK20
+1.8V_PRIM N18
PJP4 VCCAPLLEBB_1P0
1U_0402_6.3V6K
@ESPI@ RC212 1 2 0_0402_5% 1 2 1 close UC1.N18 and <120mil
KBL-RU42_BGA1356 15 OF 20
CC218
PAD-OPEN1x1m
+3.3V_ALW_PCH +3.3V_PGPPB
2
@ RC305 1 2 0_0402_5% Must be +1.8V for eSPI I/F
+3.3V_PGPPC
@ RC306 1 2 0_0402_5% +3.3V_ALW_PCH
+1.0V_MPHYGT +1.0V_AMPHYPLL +1.0V_PRIM +1.0V_CLK5 close UC1.AK17 and <120mil
close UC1.K15, UC1.L15 and <100mil
+3.3V_PGPPD +3.3V_ALW_DSW +3.3V_ALW_PCH
@ RC169 1 2 0_0603_5% @ RC171 1 2 0_0402_5%
0.1U_0201_10V6K
1U_0402_6.3V6K
@ RC307 1 2 0_0402_5% close UC1.K15 and <120mil 1 1
+3.3V_ALW
47U_0805_6.3V6M
47U_0805_6.3V6M
0.1U_0201_10V6K
1U_0402_6.3V6K
CC223
1 1 1 1 2 close UC1.L19 and <100mil 1
B B
@ CC219
@ CC221
CC224
NDS3@ RC440 0_0402_5%
+3.3V_PGPPE
@ CC281
@ CC264
1 2 2 2
@ RC308 1 2 0_0402_5% 2 2 2 @ RC214 0_0402_5% 2
DS3@ QC7
LP2301ALT1G_SOT23-3
8/28 schematic review
1 2 +3.3V_ALW_DSW_R 1 3
S
@DS3@ RC439 0_0402_5%
499K_0402_1%
1
22U_0603_6.3V6M
@ CC279
22U_0603_6.3V6M
@ CC280
1 1
G
2
+1.0V_APLL
RC432
DS3@
+3.3V_ALW_PCH +1.0V_PRIM
+3.3V_VCCHDA +1.0V_PRIM +1.0V_MPHYGT
2 2 @ PJP3
2
LC1 1 2 BLM15GA750SN1D_2P LC2 1 2 BLM15GA750SN1D_2P 1 2
100K_0402_5%
0.1U_0201_10V6K
0.1U_0201_10V6K
2
47U_0805_6.3V6M
1U_0402_6.3V6K
1 1 1 1 PAD-OPEN1x3m
0.1U_0402_25V6K
49.9K_0402_1%
RC431
DS3@
@ CC215
CC313
@ CC225
CC314
RC433
DS3@
@
CC340
2 2 2 2
+1.0V_MPHYGT source
2
1
2
RC439RC440RE536RC215RC441RC442
close UC1.AJ19 and <400mil close UC1.V15 and <100mil 561280_561280_KBL_UY_PDG_Rev0p9 :
L2N7002WT1G_SC-70-3
Support DS3 V X V X V X MPHY has defeature
1
QC6 D
DS3@ 2
+1.0V_PRIM +1.0V_CLK2
No Support DS3 X V X V X V VCCDSW_EN_GPIO <11>
G
A +1.0V_PRIM +1.0V_CLK4 S
3 A
'V' mean POP, 'X' mean DE-POP
@ RC170 1 2 0_0402_5%
@ RC173 1 2 0_0402_5%
47U_0805_6.3V6M
1
DELL CONFIDENTIAL/PROPRIETARY
47U_0805_6.3V6M
@ CC220
close UC1.N20 and <100mil 1
@ CC226
close UC1.K19 and <100mil 2 Compal Electronics, Inc.
2 Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (13/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 18 of 58
5 4 3 2 1
5 4 3 2 1
Note1: VCCPRIM_CORE Implementat i on wit h PC H C ORE_VI D Rec o mmendat i on
R1: PR408,PR411 ; R2: PR417,PR418 ; R3,PR419,PR420 ; R4: PR423 ; R5: PR424
CPU@ CPU@
UC1P KBL-R U4+2 UC1Q KBL-R U4+2 CPU@
Rev_0.1 Rev_0.1 UC1R KBL-R U4+2
GND 1 OF 3 GND 2 OF 3 Rev_0.1
A5
A67 VSS VSS
AL65
AL66
Vinafix.com
AT63
AT68 VSS VSS
BA49
BA53
F8
G10 VSS
GND 3 OF 3
VSS
L18
L2
A70 VSS VSS AM13 AT71 VSS VSS BA57 G22 VSS VSS L20
D AA2 VSS VSS AM21 AU10 VSS VSS BA6 G43 VSS VSS L4 D
AA4 VSS VSS AM25 AU15 VSS VSS BA62 G45 VSS VSS L8
AA65 VSS VSS AM27 AU20 VSS VSS BA66 G48 VSS VSS N10
AA68 VSS VSS AM43 AU32 VSS VSS BA71 G5 VSS VSS N13
AB15 VSS VSS AM45 AU38 VSS VSS BB18 G52 VSS VSS N19
AB16 VSS VSS AM46 AV1 VSS VSS BB26 G55 VSS VSS N21
AB18 VSS VSS AM55 AV68 VSS VSS BB30 G58 VSS VSS N6
AB21 VSS VSS AM60 AV69 VSS VSS BB34 G6 VSS VSS N65
AB8 VSS VSS AM61 AV70 VSS VSS BB38 G60 VSS VSS N68
AD13 VSS VSS AM68 AV71 VSS VSS BB43 G63 VSS VSS P17
AD16 VSS VSS AM71 AW10 VSS VSS BB55 G66 VSS VSS P19
AD19 VSS VSS AM8 AW12 VSS VSS BB6 H15 VSS VSS P20
AD20 VSS VSS AN20 AW14 VSS VSS BB60 H18 VSS VSS P21
AD21 VSS VSS AN23 AW16 VSS VSS BB64 H71 VSS VSS R13
AD62 VSS VSS AN28 AW18 VSS VSS BB67 J11 VSS VSS R6
AD8 VSS VSS AN30 AW21 VSS VSS BB70 J13 VSS VSS T15
AE64 VSS VSS AN32 AW23 VSS VSS C1 J25 VSS VSS T17
AE65 VSS VSS AN33 AW26 VSS VSS C25 J28 VSS VSS T18
AE66 VSS VSS AN35 AW28 VSS VSS C5 J32 VSS VSS T2
AE67 VSS VSS AN37 AW30 VSS VSS D10 J35 VSS VSS T21
AE68 VSS VSS AN38 AW32 VSS VSS D11 J38 VSS VSS T4
AE69 VSS VSS AN40 AW34 VSS VSS D14 J42 VSS VSS U10
AF1 VSS VSS AN42 AW36 VSS VSS D18 J8 VSS VSS U63
AF10 VSS VSS AN58 AW38 VSS VSS D22 K16 VSS VSS U64
AF15 VSS VSS AN63 AW41 VSS VSS D25 K18 VSS VSS U66
AF17 VSS VSS AP10 AW43 VSS VSS D26 K22 VSS VSS U67
AF2 VSS VSS AP18 AW45 VSS VSS D30 K61 VSS VSS U69
AF4 VSS VSS AP20 AW47 VSS VSS D34 K63 VSS VSS U70
AF63 VSS VSS AP23 AW49 VSS VSS D39 K64 VSS VSS V16
AG16 VSS VSS AP28 AW51 VSS VSS D44 K65 VSS VSS V17
AG17 VSS VSS AP32 AW53 VSS VSS D45 K66 VSS VSS V18
AG18 VSS VSS AP35 AW55 VSS VSS D47 K67 VSS VSS W13
C AG19 VSS VSS AP38 AW57 VSS VSS D48 K68 VSS VSS W6 C
AG20 VSS VSS AP42 AW6 VSS VSS D53 K70 VSS VSS W9
AG21 VSS VSS AP58 AW60 VSS VSS D58 K71 VSS VSS Y17
AG71 VSS VSS AP63 AW62 VSS VSS D6 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW64 VSS VSS D62 L16 VSS VSS Y20
AH6 VSS VSS AP70 AW66 VSS VSS D66 L17 VSS VSS Y21
AH63 VSS VSS AR11 AW8 VSS VSS D69 VSS VSS
AH64 VSS VSS AR15 AY66 VSS VSS E11
AH67 VSS VSS AR16 B10 VSS VSS E15
AJ15 VSS VSS AR20 B14 VSS VSS E18
AJ18 VSS VSS AR23 B18 VSS VSS E21 KBL-RU42_BGA1356 18 OF 20
AJ20 VSS VSS AR28 B22 VSS VSS E46
AJ4 VSS VSS AR35 B30 VSS VSS E50
AK11 VSS VSS AR42 B34 VSS VSS E53
AK16 VSS VSS AR43 B39 VSS VSS E56
AK18 VSS VSS AR45 B44 VSS VSS E6
AK21 VSS VSS AR46 B48 VSS VSS E65
AK22 VSS VSS AR48 B53 VSS VSS E71
AK27 VSS VSS AR5 B58 VSS VSS F1
AK63 VSS VSS AR50 B62 VSS VSS F13
AK68 VSS VSS AR52 B66 VSS VSS F2
AK69 VSS VSS AR53 B71 VSS VSS F22
AK8 VSS VSS AR55 BA1 VSS VSS F23
AL2 VSS VSS AR58 BA10 VSS VSS F27
AL28 VSS VSS AR63 BA14 VSS VSS F28
AL32 VSS VSS AR8 BA18 VSS VSS F32
AL35 VSS VSS AT2 BA2 VSS VSS F33
AL38 VSS VSS AT20 BA23 VSS VSS F35
AL4 VSS VSS AT23 BA28 VSS VSS F37
AL45 VSS VSS AT28 BA32 VSS VSS F38
AL48 VSS VSS AT35 BA36 VSS VSS F4
AL52 VSS VSS AT4 F68 VSS VSS F40
B AL55 VSS VSS AT42 BA45 VSS VSS F42 B
AL58 VSS VSS AT56 VSS VSS BA41
AL64 VSS VSS AT58 VSS
VSS VSS
KBL-RU42_BGA1356 16 OF 20 KBL-RU42_BGA1356 17 OF 20
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
CPU (14/14)
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 19 of 58
5 4 3 2 1
5 4 3 2 1
For DDR4
<7> DDR_A_DQS#[0..7]
JDIMM1 REV Type H=9.2
+1.2V_MEM +1.2V_MEM
JDIMM1
<7> DDR_A_D[0..63]
1 2
<7> DDR_A_DQS[0..7] DDR_A_D4 VSS1 VSS2 DDR_A_D1
3 4
5 DQ5 DQ4 6
<7> DDR_A_MA[0..16] DDR_A_D0 VSS3 VSS4 DDR_A_D5
7 8
9 DQ1 DQ0 10
Vinafix.com
DDR_A_DQS#0 11 VSS5 VSS6 12
DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_A_D3
Layout Note: DDR_A_D2 17 VSS8 DQ6 18
DQ7 VSS9 DDR_A_D7
D
Place near JDIMM1 DDR_A_D6
19
21 VSS10 DQ2
20
22
+1.2V_MEM
D
23 DQ3 VSS11 24 DDR_A_D11
DDR_A_D9 25 VSS12 DQ12 26
DQ13 VSS13 DDR_A_D12
1
470_0402_1%
27 28
DDR_A_D8 29 VSS14 DQ8 30
DQ9 VSS15 DDR_A_DQS#1
RD11
31 32
+1.2V_MEM 33 VSS16 DQS1_c 34 DDR_A_DQS1
35 DM1_n/DBI_n DQS1_t 36
2
DDR_A_D10 37 VSS17 VSS18 38 DDR_A_D13
39 DQ15 DQ14 40
DDR_A_D14 41 VSS19 VSS20 42 DDR_A_D15 DDR_DRAMRST#_R 1 2 DDR_DRAMRST#
DQ10 DQ11 DDR_DRAMRST# <7>
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
10U_0603_10V6M
330U_D3_2.5VY_R6M
43 44 @ RD12 0_0402_5%
DDR_A_D21 45 VSS21 VSS22 46 DDR_A_D17
47 DQ21 DQ20 48
VSS23 VSS24
1
DDR_A_D20 DDR_A_D16
@ CD17
49 50
DQ17 DQ16
1
1
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
+ 51 52
DDR_A_DQS#2 53 VSS25 VSS26 54
DDR_A_DQS2 55 DQS2_c DM2_n/DBI2_n 56
2
2
57 DQS2_t VSS27 58 DDR_A_D18
DDR_A_D19 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_A_D22 +1.2V_MEM
DDR_A_D23 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_A_D29
VSS32 DQ28
1K_0402_1%
DDR_A_D28
1
67 68
69 DQ29 VSS33 70 DDR_A_D25
DDR_A_D24 VSS34 DQ24
RD15
71 72
+1.2V_MEM +2.5V_MEM 73 DQ25 VSS35 74 DDR_A_DQS#3
75 VSS36 DQS3_c 76 DDR_A_DQS3 +DDR_VREF_A_CA +DDR_VREF_CA
2
77 DM3_n/DBI3_n DQS3_t 78
DDR_A_D26 79 VSS37 VSS38 80 DDR_A_D27
DQ30 DQ31
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_10V6M
10U_0603_10V6M
81 82 1 2
DDR_A_D30 83 VSS39 VSS40 84 DDR_A_D31 RD17 2_0402_1%
1 1 1 1 DQ26 DQ27
1
0.022U_0402_16V7K
85 86
VSS41 VSS42
CD9
CD10
CD11
CD12
CD13
CD14
CD15
CD16
CD18
CD19
CD20
CD21
1K_0402_1%
87 88
CB5/NC CB4/NC
1
89 90
2
VSS43 VSS44
1
2 2 2 2
RD16
CD31
91 92
93 CB1/NC CB0/NC 94
95 VSS45 VSS46 96
2
97 DQS8_c DM8_n/DBI_n/NC 98
2
99 DQS8_t VSS47 100
VSS48 CB6/NC
1
24.9_0402_1%
101 102
CB2/NC VSS49
RD18
103 104
C VSS50 CB7/NC C
105 106
107 CB3/NC VSS51 108 DDR_DRAMRST#_R
DDR_A_CKE0 109 VSS52 RESET_n 110 DDR_A_CKE1
<7> DDR_A_CKE0 DDR_A_CKE1 <7> 1
2
111 CKE0 CKE1 112
DDR_A_BG1 113 VDD1 VDD2 114 DDR_A_ACT# CD29 @
<7> DDR_A_BG1 DDR_A_BG0 BG1 ACT_n DDR_A_ALERT# DDR_A_ACT# <7>
115 116 0.1U_0402_25V6
<7> DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT# <7> 2
117 118
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
123 A9 A7 124
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5
Layout Note: DDR_A_MA6 127 A8 A5 128 DDR_A_MA4
A6 A4
Place near DDR_A_MA3
129
131 VDD7 VDD8
130
132 DDR_A_MA2 JDIMM1_EVENT# 1 2
JDIMM1.258 DDR_A_MA1 133 A3 A2 134 JDIMM1_EVENT# @ RD14 1K_0402_5%
H_THERMTRIP# <12,33>
135 A1 EVENT_n/NF 136
DDR_A_CLK0 137 VDD9 VDD10 138 DDR_A_CLK1
<7> DDR_A_CLK0 DDR_A_CLK#0 CK0_t CK1_t/NF DDR_A_CLK#1 DDR_A_CLK1 <7>
139 140
<7> DDR_A_CLK#0 CK0_c CK1_c/NF DDR_A_CLK#1 <7>
141 142
DDR_A_PARITY 143 VDD11 VDD12 144 DDR_A_MA0
<7> DDR_A_PARITY PARITY A0
+DDR_VREF_A_CA DDR_A_BA1 145 146 DDR_A_MA10
<7> DDR_A_BA1 BA1 A10/AP
+0.6V_DDR_VTT 147 148
DDR_A_CS#0 149 VDD13 VDD14 150 DDR_A_BA0
<7> DDR_A_CS#0 DDR_A_MA14 CS0_n BA0 DDR_A_MA16 DDR_A_BA0 <7>
151 152
<7> DDR_A_MA14 WE_n/A14 RAS_n/A16
153 154
DDR_A_ODT0 VDD15 VDD16 DDR_A_MA15
0.1U_0402_10V6K
155 156
<7> DDR_A_ODT0 DDR_A_CS#1 ODT0 CAS_n/A15 DDR_A_MA13
10U_0603_10V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
2.2U_0402_6.3V6M
1 1 157 158
<7> DDR_A_CS#1 CS1_n A13 +DDR_VREF_A_CA
@ CD26
1 1 159 160
VDD17 VDD18
1
DDR_A_ODT1
CD22
CD23
CD24
CD25
161 162 T50 @ PAD~D
<7> DDR_A_ODT1 ODT1 C0/CS2_n/NC +DDR_VREF_A_CA
163 164
2 2 PAD~D @ T51 165 VDD19 VREFCA 166 DIMM1_SA2
2
2 2 167 C1, CS3_n,NC SA2 168
DDR_A_D32 169 VSS53 VSS54 170 DDR_A_D37
171 DQ37 DQ36 172
DDR_A_D36 173 VSS55 VSS56 174 DDR_A_D33
175 DQ33 DQ32 176
DDR_A_DQS#4 177 VSS57 VSS58 178
DDR_A_DQS4 179 DQS4_c DM4_n/DBI4_n 180
181 DQS4_t VSS59 182 DDR_A_D38
DDR_A_D35 183 VSS60 DQ39 184
B B
185 DQ38 VSS61 186 DDR_A_D39
DDR_A_D34 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_A_D41
DDR_A_D40 191 VSS64 DQ45 192
193 DQ44 VSS65 194 DDR_A_D45
DDR_A_D44 195 VSS66 DQ41 196
197 DQ40 VSS67 198 DDR_A_DQS#5
DIMM Select +3.3V_RUN +3.3V_RUN +3.3V_RUN
+3.3V_RUN DDR_A_D42
199
201
203
VSS68
DM5_n/DBI5_n
VSS69
DQS5_c
DQS5_t
VSS70
200
202
204
DDR_A_DQS5
DDR_A_D46 +1.2V_MEM
DQ46 DQ47
1
205 206
@ RD4 @ RD6 @ RD8 DDR_A_D47 207 VSS71 VSS72 208 DDR_A_D43 UD1
1
0_0402_5% 0_0402_5% 0_0402_5% 209 DQ42 DQ43 210 1 5 1 2
@RD10 DDR_A_D52 211 VSS73 VSS74 212 DDR_A_D49 NC VCC @ CD32 0.1U_0201_10V6K
213 DQ52 DQ53 214 2
0_0603_5%
2
DDR_A_D48 VSS75 VSS76 DDR_A_D53 <7> DDR_VTT_CTRL A
215 216 4
DIMM1_SA0 DQ49 DQ48 Y 0.6V_DDR_VTT_ON <43>
217 218 3
2
DIMM1_SA1 +3.3V_RUN_DIMM1 DDR_A_DQS#6 219 VSS77 VSS78 220 GND 1 2
DIMM1_SA2 DDR_A_DQS6 DQS6_c DM6_n/DBI6_n +3.3V_RUN
0.1U_0201_10V6K
SA0 SA1 SA2 221 222 74AUP1G07SE-7_SOT353_5P RD19 100K_0402_5%
DQS6_t VSS79 DDR_A_D54
2.2U_0402_6.3V6M
1 1 223 224
VSS80 DQ54
1
DDR_A_D55
CD28
225 226 CHECK
* DIMM1 0 0 0 DQ55 VSS81 DDR_A_D50
CD27
@ RD5 @ RD7 @ RD9 227 228
0_0402_5% 0_0402_5% 0_0402_5% DDR_A_D51 229 VSS82 DQ50 230
DIMM2 1 0 0 2 2 231 DQ51 VSS83 232 DDR_A_D56
DDR_A_D59 233 VSS84 DQ60 234
DIMM3 0 1 0
2
235 DQ61 VSS85 236 DDR_A_D57
DDR_A_D58 237 VSS86 DQ57 238
DIMM4 1 1 0 239 DQ56 VSS87 240 DDR_A_DQS#7
241 VSS88 DQS7_c 242 DDR_A_DQS7
243 DM7_n/DBI7_n DQS7_t 244
DDR_A_D62 245 VSS89 VSS90 246 DDR_A_D60
247 DQ62 DQ63 248
DDR_A_D63 249 VSS91 VSS92 250 DDR_A_D61
251 DQ58 DQ59 252
253 VSS93 VSS94 254
<8,14> DDR_XDP_WAN_SMBCLK +3.3V_RUN_DIMM1 SCL SDA DIMM1_SA0 DDR_XDP_WAN_SMBDAT <8,14>
255 256
257 VDDSPD SA0 258
+2.5V_MEM VPP1 VTT DIMM1_SA1 +0.6V_DDR_VTT
259 260
261 VPP2 SA1 262
GND1 GND2
A A
LCN_DAN05-Q0406-0103
CONN@
LINK SP07001D200 DONE
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDR4
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 20 of 58
5 4 3 2 1
5 4 3
For2 passive level shifter
1
+5V_RUN
from AR
0.1U_0201_10V6K
1
1
CV39
+VHDMI_VCC
2
IN
AP2330W-7_SC59-3
Vinafix.com
UV2
0.1U_0201_10V6K
10U_0603_10V6M
EMI@ LV31 12NH_LQG15HN12NJ02D_5% 1
CV41
1 2
GND
OUT
HDMI_L_TX_P2 @
HCM1012GH900BP_4P
CV40
D D
2
2
1 2 HDMI_TX_P2 2 3 EMI@ 2
<22> AR_DP1_P0
3
CV31 0.1U_0402_25V6 2 3 RV26
<22> AR_DP1_N0
1 2 HDMI_TX_N2 1
4 1
4
300_0402_5% HDMI connector
CV32 0.1U_0402_25V6
1
@EMI@ HDMI_L_TX_N2
LV3
2 1 ACON_HMRBL-A41L0F
EMI@ LV32
12NH_LQG15HN12NJ02D_5%
EMI@ LV33
12NH_LQG15HN12NJ02D_5% HDMI_HPD 19
1 2 18 HPD
HDMI_L_TX_P1 17 +5V
HCM1012GH900BP_4P +3.3V_RUN HDMI_CTRL_DATA 16 DDC/CEC GND 23
SDA GND
2
1 2 HDMI_TX_P1 2 3 EMI@ HDMI_CTRL_CLK 15 22
<22> AR_DP1_P1 2 3 SCL GND
CV33 0.1U_0402_25V6 RV29 14 21
2 1 HDMI_CEC 13 Reserved GND 20
300_0402_5% CEC GND
1 2 HDMI_TX_N1 1 4 10K_0402_5% @ RV19 HDMI_L_CLKN 12
<22> AR_DP1_N1 1 4 11 CK-
CV34 0.1U_0402_25V6
1
@EMI@ LV6 HDMI_L_TX_N1 HDMI_L_CLKP 10 CK_Shield
1 2 HDMI_L_TX_N0 9 CK+
EMI@ LV34 12NH_LQG15HN12NJ02D_5% 8 D0-
EMI@ LV35 12NH_LQG15HN12NJ02D_5% HDMI_L_TX_P0 7 D0_Shield
1 2 HDMI_L_TX_N1 6 D0+
HDMI_L_TX_P0 5 D1-
HCM1012GH900BP_4P HDMI_L_TX_P1 4 D1_Shield
D1+
2
1 2 HDMI_TX_P0 2 3 EMI@ HDMI_L_TX_N2 3
<22> AR_DP1_P2 2 3 D2-
CV35 0.1U_0402_25V6 RV32 2
HDMI_L_TX_P2 1 D2_Shield
300_0402_5% D2+
1 2 HDMI_TX_N0 1 4
<22> AR_DP1_N2 1 4
CV36 0.1U_0402_25V6
1
@EMI@ LV9 HDMI_L_TX_N0 CONN@
JHDMI1
1 2
EMI@ LV36 12NH_LQG15HN12NJ02D_5%
EMI@ LV37 12NH_LQG15HN12NJ02D_5% LINK DC231604012 (temp) DONE
1 2
HDMI_L_CLKP
HDMI_TX_P2 HDMI_OB
C HCM1012GH900BP_4P RV10 1 2 470_0402_1%
C
2
2 1 HDMI_CLKP 2 3 EMI@ HDMI_TX_N2 RV11 1 2 470_0402_1%
<22> AR_DP1_P3 0.1U_0402_25V6 2 3 HDMI_TX_P1
CV37 RV35 RV12 1 2 470_0402_1%
HDMI_TX_N1 RV13 1 2 470_0402_1%
300_0402_5%
2 1 HDMI_CLKN 1 4 HDMI_TX_P0 RV14 1 2 470_0402_1%
<22> AR_DP1_N3 0.1U_0402_25V6 1 4 HDMI_TX_N0 1 2
CV38 RV15 470_0402_1%
1
@EMI@ LV12 HDMI_L_CLKN HDMI_CLKP RV16 1 2 470_0402_1%
HDMI_CLKN RV17 1 2 470_0402_1%
1 2
EMI@ LV38 12NH_LQG15HN12NJ02D_5%
1
D
RV18 1 2 10K_0402_5% 2 QV4
+3.3V_RUN
G L2N7002WT1G_SC-70-3
S
3
+3.3V_RUN
1M_0402_5%
2
RV20
2
G
1
3 1 HDMI_HPD 1 2
B <22> AR_DP1_HPD RV21 20K_0402_5%
B
S
QV5
L2N7002WT1G_SC-70-3
+3.3V_RUN
QV3A +VHDMI_VCC
2
DMN65D8LDW-7_SOT363-6
1 6 HDMI_CTRL_CLK 1 2
<22> AR_DP1_CTRL_CLK
RV22 2.2K_0402_5%
5
4 3 HDMI_CTRL_DATA 1 2
<22> AR_DP1_CTRL_DATA
RV23 2.2K_0402_5%
QV3B
DMN65D8LDW-7_SOT363-6
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
HDMI CONN
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 21 of 58
5 4 3 2 1
5 4 3 2 1
+3.3V_TBT_LC
For Steamboat 12/14
+3.3V_TBT_FLASH_R +3.3V_TBT_FLASH_R
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
+3.3V_TBT_FLASH_R +3.3V_TBT_LC +3.3V_TBTA_FLASH
2
+3.3V_ALW_PCH
RT5
RT6
RT7
RT8
0_0402_5% 1 2 @ RT9
0.1U_0201_10V6K
1
2.2K_0402_5%
2.2K_0402_5%
2
2
TBT_JTAG_TDI
3.3K_0402_5%
3.3K_0402_5%
1
TBT_JTAG_TMS TBT_CIO_PLUG_EVENT#
CT1
0_0402_5% 2 1 @ RT10 RT391 1 2 10K_0402_5%
TBT_JTAG_TCK For backdrive issue
Vinafix.com TBT_JTAG_TDO
RT1
RT2
RT3
RT4
2
1
1
Rework Debug Pin1 +3.3V_TBT_LC, Pin6 GND
UT2
D 8 1 TBT_ROM_CS# D
TBT_ROM_HOLD# 7 VCC CS# 2 TBT_ROM_DO
TBT_ROM_CLK 6 HOLD#(IO3) DO(IO1) 3 TBT_ROM_WP# +3.3V_TBT
TBT_ROM_DI 5 CLK WP#(IO2) 4
DI(IO0) GND
W25Q80DVSSIG_SO8 TBT_RESET_N_EC @ RT11 1 2 10K_0402_5%
UT1A
CT2 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P8 Y23 V23 PCIE_PRX_C_DTX_P8 CT6 1 2 0.22U_0201_6.3V6K
<10> PCIE_PTX_DRX_P8 PCIE_RX0_P PCIE_TX0_P PCIE_PRX_DTX_P8 <10>
CT3 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N8 Y22 V22 PCIE_PRX_C_DTX_N8 CT7 1 2 0.22U_0201_6.3V6K AR_DP1_CTRL_DATA RT12 1 2 2.2K_0402_5%
<10> PCIE_PTX_DRX_N8 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_DTX_N8 <10> AR_DP1_CTRL_CLK RT13 1 2 2.2K_0402_5%
CT4 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P7 T23 P23 PCIE_PRX_C_DTX_P7 CT8 1 2 0.22U_0201_6.3V6K DPSNK0_DDC_CLK @ RT14 1 2 2.2K_0402_5%
PCIe GEN3
<10> PCIE_PTX_DRX_P7 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N7 T22 PCIE_RX1_P PCIE_TX1_P P22 PCIE_PRX_C_DTX_N7 1 2 0.22U_0201_6.3V6K PCIE_PRX_DTX_P7 <10> DPSNK0_DDC_DATA
CT5 CT9 @ RT15 1 2 2.2K_0402_5%
<10> PCIE_PTX_DRX_N7 PCIE_RX1_N PCIE_TX1_N PCIE_PRX_DTX_N7 <10> DPSNK1_DDC_CLK @ RT336 1 2 2.2K_0402_5%
CT123 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P6 M23 K23 PCIE_PRX_C_DTX_P6 CT127 1 2 0.22U_0201_6.3V6K SNK0_CONFIG1 @ RT337 1 2 2.2K_0402_5%
<10> PCIE_PTX_DRX_P6 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N6 M22 PCIE_RX2_P PCIE_TX2_P K22 PCIE_PRX_C_DTX_N6 1 2 0.22U_0201_6.3V6K PCIE_PRX_DTX_P6 <10>
CT124 CT128
<10> PCIE_PTX_DRX_N6 PCIE_RX2_N PCIE_TX2_N PCIE_PRX_DTX_N6 <10>
SNK0_DDC_data/clk – connect to 2k PU only if
CT125 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_P5 H23 F23 PCIE_PRX_C_DTX_P5 CT129 1 2 0.22U_0201_6.3V6K SRC0 is connected and support HDMI (a.i HDMI
<10> PCIE_PTX_DRX_P5 PCIE_RX3_P PCIE_TX3_P PCIE_PRX_DTX_P5 <10>
CT126 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N5 H22 F22 PCIE_PRX_C_DTX_N5 CT130 1 2 0.22U_0201_6.3V6K or DP++ connector). Otherwise can be 100k PD.
<10> PCIE_PTX_DRX_N5 PCIE_RX3_N PCIE_TX3_N PCIE_PRX_DTX_N5 <10>
PCH_PLTRST#_AND SNK1_DDC_data – connect to 100k PD. If SRC0
V19 L4
<11> CLK_PCIE_P5 T19 PCIE_REFCLK_100_IN_P PERST_N PCH_PLTRST#_AND <11,29,30,34,35> support HDMI, connect as SNK0_CFG1 to GPU
<11> CLK_PCIE_N5
AC5 PCIE_REFCLK_100_IN_N N16 TBT_PCIE_RBIAS 1 2
and/or appropriate AUX/DDC demux control
<11> CLKREQ_PCIE#5 PCIE_CLKREQ_N PCIE_RBIAS RT34 3.01K_0402_1% SNK1_DDC_clk – connect to 100k PD.
CT10 1 2 0.1U_0201_10V6K CPU_DP1_P0_C AB7 R2 AR_DP1_P0
<6> CPU_DP1_P0 CPU_DP1_N0_C DPSNK0_ML0_P DPSRC_ML0_P AR_DP1_N0 AR_DP1_P0 <21> AR_DP1_P0 AR_DP1_N0
CT11 1 2 0.1U_0201_10V6K AC7 R1 1 2
<6> CPU_DP1_N0 DPSNK0_ML0_N DPSRC_ML0_N AR_DP1_N0 <21> @ CT201 1P_0201_50V8C
CT12 1 2 0.1U_0201_10V6K CPU_DP1_P1_C AB9 N2 AR_DP1_P1 AR_DP1_P1 1 2 AR_DP1_N1
<6> CPU_DP1_P1 CPU_DP1_N1_C DPSNK0_ML1_P DPSRC_ML1_P AR_DP1_N1 AR_DP1_P1 <21> +3.3V_TBT_SX
CT13 1 2 0.1U_0201_10V6K AC9 N1 @ CT202 1P_0201_50V8C
SOURCE PORT 0
<6> CPU_DP1_N1 DPSNK0_ML1_N DPSRC_ML1_N AR_DP1_N1 <21> AR_DP1_P2 AR_DP1_N2
CPU 1 2
SINK PORT 0
CT14 1 2 0.1U_0201_10V6K CPU_DP1_P2_C AB11 L2 AR_DP1_P2 @ CT203 1P_0201_50V8C
<6> CPU_DP1_P2 CPU_DP1_N2_C DPSNK0_ML2_P DPSRC_ML2_P AR_DP1_N2 AR_DP1_P2 <21> AR_DP1_P3 AR_DP1_N3 TBTA_I2C_INT
CT15 1 2 0.1U_0201_10V6K AC11 L1 1 2 RT16 1 2 10K_0402_5%
<6> CPU_DP1_N2 DPSNK0_ML2_N DPSRC_ML2_N AR_DP1_N2 <21> TBTB_I2C_INT
@ CT204 1P_0201_50V8C RT17 1 2 10K_0402_5%
CT16 1 2 0.1U_0201_10V6K CPU_DP1_P3_C AB13 J2 AR_DP1_P3
<6> CPU_DP1_P3 CPU_DP1_N3_C DPSNK0_ML3_P DPSRC_ML3_P AR_DP1_N3 AR_DP1_P3 <21> TBT_I2C_SDA
CT17 1 2 0.1U_0201_10V6K AC13 J1 RT18 1 2 2.2K_0402_5%
<6> CPU_DP1_N3 DPSNK0_ML3_N DPSRC_ML3_N AR_DP1_N3 <21> Close UT1 TBT_I2C_SCL RT19 1 2 2.2K_0402_5%
CPU_DP1_AUXP_C
<6> CPU_DP1_AUXP CT18 1
CT19 1
2 0.1U_0201_10V6K
2 0.1U_0201_10V6K CPU_DP1_AUXN_C
Y11
W11 DPSNK0_AUX_P DPSRC_AUX_P
W19
Y19
Intel Review request
C <6> CPU_DP1_AUXN DPSNK0_AUX_N DPSRC_AUX_N 20160324 TDOCK_BATLOW# RT20 1 2 10K_0402_5% C
AA2 G1 AR_DP1_HPD
<6> CPU_DP1_HPD DPSNK0_HPD DPSRC_HPD AR_DP1_HPD <21> TBT_SRC_CFG1 RT338 1 2 10K_0402_5%
1 2 DPSNK0_DDC_CLK Y5 N6 TBT_DP_RBIAS 1 2
<6> CPU_DP1_CTRL_CLK @ RT341 1 DPSNK0_DDC_DATA DPSNK0_DDC_CLK DPSRC_RBIAS TBT_CIO_PLUG_EVENT# @ RT371 1
2 0_0402_5% R4 RT35 14K_0402_1% 2 10K_0402_5%
<6> CPU_DP1_CTRL_DATA @ RT342 0_0402_5% DPSNK0_DDC_DATA U1 TBT_I2C_SDA RTD3_CIO_PWR_EN @ RT372 1 2 10K_0402_5% Intel review request
CPU_DP2_P0_C GPIO_0 TBT_I2C_SCL TBT_I2C_SDA <24>
<6> CPU_DP2_P0
CT177 1 2 0.1U_0201_10V6K
CPU_DP2_N0_C
AB15
DPSNK1_ML0_P GPIO_1
U2
TBT_ROM_WP# TBT_I2C_SCL <24> TBTA_LSRX
20160324
CT176 1 2 0.1U_0201_10V6K AC15 V1 RT21 1 2 1M_0402_5%
LC GPIO
<6> CPU_DP2_N0 DPSNK1_ML0_N GPIO_2 V2 TBT_TMU_CLK_OUT TBTA_LSTX 1 2
RT22 1M_0402_5%
CT172 1 2 0.1U_0201_10V6K CPU_DP2_P1_C AB17 GPIO_3 W1 PCIE_WAKE# TBTA_HPD RT23 1 2 100K_0402_5%
<6> CPU_DP2_P1 CPU_DP2_N1_C DPSNK1_ML1_P GPIO_4 TBT_CIO_PLUG_EVENT# PCIE_WAKE# <30,33,35> CPU_DP1_HPD
CT171 1 2 0.1U_0201_10V6K AC17 W2 RT24 1 2 100K_0402_5%
<6> CPU_DP2_N1 DPSNK1_ML1_N GPIO_5 AR_DP1_CTRL_DATA TBT_CIO_PLUG_EVENT# <12> RTD3_CIO_PWR_EN
Y1 RT25 1 2 100K_0402_5%
CPU_DP2_P2_C GPIO_6 AR_DP1_CTRL_CLK AR_DP1_CTRL_DATA <21> RTD3_USB_PWR_EN
CPU CT174 1 2 0.1U_0201_10V6K AB19 Y2 RT26 1 2 100K_0402_5%
SINK PORT 1
<6> CPU_DP2_P2 CPU_DP2_N2_C DPSNK1_ML2_P GPIO_7 TBT_SRC_CFG1 AR_DP1_CTRL_CLK <21> TBT_FORCE_PWR
CT168 1 2 0.1U_0201_10V6K AC19 AA1 RT27 1 2 10K_0402_5%
<6> CPU_DP2_N2
DDI2 CPU_DP2_P3_C
DPSNK1_ML2_N GPIO_8
POC_GPIO_0
J4 TBTA_I2C_INT
TBTB_I2C_INT TBTA_I2C_INT <24>
TBT_TMU_CLK_OUT
CPU_DP2_HPD
RT28 1 2 100K_0402_5%
CT173 1 2 0.1U_0201_10V6K AB21 E2 RT29 1 2 100K_0402_5%
POC GPIO
<6> CPU_DP2_P3 CPU_DP2_N3_C DPSNK1_ML3_P POC_GPIO_1 RTD3_USB_PWR_EN
CT170 1 2 0.1U_0201_10V6K AC21 D4
<6> CPU_DP2_N3 DPSNK1_ML3_N POC_GPIO_2 TBT_FORCE_PWR
H4
CT169 1 2 0.1U_0201_10V6K CPU_DP2_AUXP_C Y12 POC_GPIO_3 F2 TDOCK_BATLOW# TBT_FORCE_PWR <6> TBT_SRC_CFG1 @ RT30 1 2 1M_0402_5%
<6> CPU_DP2_AUXP CPU_DP2_AUXN_C DPSNK1_AUX_P POC_GPIO_4 SIO_SLP_S3# TBTB_LSTX
<6> CPU_DP2_AUXN CT175 1 2 0.1U_0201_10V6K W12 D2 RT31 1 2 100K_0402_5%
DPSNK1_AUX_N POC_GPIO_5 F1 RTD3_CIO_PWR_EN_R 1 SIO_SLP_S3#
2 <11,32,33> TBTB_LSRX RT32 1 2 100K_0402_5%
CPU_DP2_HPD Y6 POC_GPIO_6 @ RT392 0_0402_5% RTD3_CIO_PWR_EN <9> TBTB_HPD RT33 1 2 100K_0402_5%
<6> CPU_DP2_HPD DPSNK1_HPD E1 TEST_EN 1 2
DPSNK1_DDC_CLK Y8 TEST_EN RT36 100_0402_5%
Misc
SNK0_CONFIG1 N4 DPSNK1_DDC_CLK AB5 TEST_PWRGD 1 2
DPSNK1_DDC_DATA TEST_PWR_GOOD RT37 100_0402_5%
2 1 DPSNK_RBIAS Y18 F4 TBT_RESET_N_EC
DPSNK_RBIAS RESET_N TBT_RESET_N_EC <24,32> AR_DP1_CTRL_DATA
RT38 14K_0402_1% @ RT124 1 2 100K_0402_5%
TBT_JTAG_TDI Y4 D22 XTAL_25_IN 1 2 XTAL_25_IN_R AR_DP1_CTRL_CLK @ RT125 1 2 100K_0402_5%
TBT_JTAG_TMS V4 TDI XTAL_25_IN D23 XTAL_25_OUT @ RT394 1 2 0_0402_5% XTAL_25_OUT_R DPSNK0_DDC_CLK @ RT126 1 2 100K_0402_5%
TBT_JTAG_TCK T4 TMS XTAL_25_OUT @ RT40 0_0402_5% DPSNK0_DDC_DATA @ RT127 1 2 100K_0402_5%
TBT_JTAG_TDO W4 TCK AB3 TBT_ROM_DI DPSNK1_DDC_CLK RT128 1 2
TDO MISC EE_DI
YT1 100K_0402_5%
AC4 TBT_ROM_DO 3 1 SNK0_CONFIG1 RT129 1 2 100K_0402_5%
1 2 TBT_RBIAS H6 EE_DO AC3 TBT_ROM_CS# OUT IN
RT39 4.75K_0402_0.5% TBT_RSENSE J6 RBIAS EE_CS_N AB4 TBT_ROM_CLK 4 2
RSENSE EE_CLK GND GND
27P_0402_50V8J
27P_0402_50V8J
1
1
A15 B7 25MHZ 20PF FL2500123Z
<26> TBTA_RX2P PA_RX1_P PB_RX1_P
CT20
CT21
B15 A7
<26> TBTA_RX2N PA_RX1_N PB_RX1_N
B B
2
A17 A9
<26> TBTA_TX2P B17 PA_TX1_P PB_TX1_P B9
<26> TBTA_TX2N PA_TX1_N PB_TX1_N
A19 A11
<26> TBTA_TX1P B19 PA_TX0_P PB_TX0_P B11
<26> TBTA_TX1N PA_TX0_N PB_TX0_N
TBT PORTS
B21 A13
<26> TBTA_RX1P PA_RX0_P PB_RX0_P
A21 B13
Port A
PORT B
<26> TBTA_RX1N PA_RX0_N PB_RX0_N
Type C Y15 Y16
<24> TBTA_AUXP W15 PA_DPSRC_AUX_P PB_DPSRC_AUX_P W16
<24> TBTA_AUXN PA_DPSRC_AUX_N PB_DPSRC_AUX_N
E20 E19
<24> TBTA_USB20_P PA_USB2_D_P PB_USB2_D_P
D20 D19
<24> TBTA_USB20_N PA_USB2_D_N PB_USB2_D_N
TBTA_LSTX A5 B4 TBTB_LSTX
<24> TBTA_LSTX TBTA_LSRX PA_LSTX PB_LSTX TBTB_LSRX
POC
POC
A4 B5
<24> TBTA_LSRX TBTA_HPD PA_LSRX PB_LSRX TBTB_HPD
M4 G2
<24> TBTA_HPD PA_DPSRC_HPD PB_DPSRC_HPD
2 1 TBTA_USB2_RBIAS H19 F19 TBTB_USB2_RBIAS 1 2
RT41 499_0402_1% PA_USB2_RBIAS PB_USB2_RBIAS RT42 499_0402_1%
AC23 D6
AB23 THERMDA MONDC_SVR
THERMDA A23
V18 ATEST_P B23
PCIE_ATEST ATEST_N
AC1 DEBUG E18
TEST_EDM USB2_ATEST
L15 W13
N15 FUSE_VQPS_64 MONDC_DPSNK_0
FUSE_VQPS_128 W18
C23 MONDC_DPSNK_1
C22 MONDC_CIO_0 AB2
MONDC_CIO_1 MONDC_DPSRC
ALPINE-RIDGE_BGA337
A A
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
TBT-AR-SP(1/2) DP, PCIE
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 22 of 58
5 4 3 2 1
A B C D E
For Steamboat 12/14 &kirkwood,For AR
+0.9V_TBT_DP +0.9V_TBT_USB
1U_0201_6.3V6M Vinafix.com
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
+3.3V_ALW
PJP6
+3.3V_VDD_PIC +3.3V_TBT_SX +3.3V_TBT
1 1 1 1 1 1 1 1 1 1 2 1 2
CT25
CT26
CT27
CT28
CT29
CT30
CT31
CT32
CT33
1 @ RT48 0_0603_5% VCC3P3_SVR:3.3V @ 0.6A max 1
PAD-OPEN1x1m +3.3V_TBT_LC 1 2
@ RT49 0_0603_5%
2 2 2 2 2 2 2 2 2 +3.3V_TBT_S0
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
CT44
CT45
CT46
CT47
1 1 1 1 1 1 1
CT41
CT42
CT43
2 2 2 2 2 2 2
<BOM Structure>
R13
+0.9V_TBT_PCIE +0.9V_TBT_CIO +0.9V_TBT_DP
R6
H9
F8
UT1B
L8 A2 VCC0P9_SVR:0.9V @ 1.8A max
VCC3P3_LC
VCC3P3_SX
VCC3P3A
VCC3P3_S0
L11 VCC0P9_DP VCC3P3_SVR A3
VCC0P9_DP VCC3P3_SVR Minimum of 4vias must be used
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
L12 B3
M8 VCC0P9_DP VCC3P3_SVR +0.9V_TBT_SVR
T11 VCC0P9_DP
1 1 1 1 1 1 1 VCC0P9_DP
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
CT34
CT35
CT36
CT37
CT38
CT39
CT40
T12 L9
L6 VCC0P9_DP VCC0P9_SVR M9
M6 VCC0P9_ANA_DPSRC VCC0P9_SVR E12
VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA 1 1 1 1 1 1 1
2 2 2 2 2 2 2
CT48
CT49
CT50
CT51
CT52
CT53
CT54
V11 E13
V12 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F11
+0.9V_TBT_PCIE V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12
VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13 2 2 2 2 2 2 2
M13 VCC0P9_SVR_ANA F15
M15 VCC0P9_PCIE VCC0P9_SVR_ANA J9
M16 VCC0P9_PCIE VCC0P9_SVR_SENSE
L19 VCC0P9_PCIE
N19 VCC0P9_ANA_PCIE_1 C1 +TBT_SVR_IND LT1 1 2 0.6UH_MND-04ABIR60M-XGL_20%
VCC0P9_ANA_PCIE_1 SVR_IND
47U_0603_6.3V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
L18 C2
VCC0P9_ANA_PCIE_2 SVR_IND
CT55
CT56
CT57
M18 D1 1 1 1
+0.9V_TBT_USB N18 VCC0P9_ANA_PCIE_2 SVR_IND Share Same GND plane
VCC
VCC0P9_ANA_PCIE_2 with SVR_VSS of AR
R15 A1
R16 VCC0P9_USB SVR_VSS B1 2 2 2
+0.9V_TBT_CIO VCC0P9_USB SVR_VSS B2 Intel review request
SVR_VSS
R8 Change 10U*4 to 47U*3
2 TBT Power circuit R9
R11
VCC0P9_CIO
VCC0P9_CIO
VCC0P9_CIO
SVR_VSS:Minimum of 4 vias must be used. +0.9V_TBT_LVR_OUT
20160324 2
1U_0201_6.3V6M
1U_0201_6.3V6M
R12 F18
VCC0P9_CIO VCC0P9_LVR
10U_0402_6.3V6M
10U_0402_6.3V6M
H18
+3.3V_RUN +3.3V_TBT +VCC3V3_ANA_PCIE L16 VCC0P9_LVR J11
+VCC3V3_ANA_USB2 J16 VCC3P3_ANA_PCIE VCC0P9_LVR 1 1 1 1
1U_0201_6.3V6M
1U_0201_6.3V6M
CT59
CT60
CT61
CT62
H11
VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE
PJP5 1 1 A6 V5
VSS_ANA VSS_ANA 2 2 2 2
CT63
CT64
2 1 A8 V6
2 1 A10 VSS_ANA VSS_ANA V8
JUMP_43X79 A12 VSS_ANA VSS_ANA V9
2 2 A14 VSS_ANA VSS_ANA V15
A16 VSS_ANA VSS_ANA V16
A18 VSS_ANA VSS_ANA V20
A20 VSS_ANA VSS_ANA W5
A22 VSS_ANA VSS_ANA W6
B6 VSS_ANA VSS_ANA W8
B8 VSS_ANA VSS_ANA W9
B10 VSS_ANA VSS_ANA W20
B12 VSS_ANA VSS_ANA W22
B14 VSS_ANA VSS_ANA W23
B16 VSS_ANA VSS_ANA Y9
B18 VSS_ANA VSS_ANA Y13
B20 VSS_ANA VSS_ANA Y20
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
D9 VSS_ANA VSS_ANA AB6
D11 VSS_ANA VSS_ANA AB8
D12 VSS_ANA VSS_ANA AB10
D13 VSS_ANA VSS_ANA AB12
D15 VSS_ANA VSS_ANA AB14
D16 VSS_ANA VSS_ANA AB16
GND
D18 VSS_ANA VSS_ANA AB18
E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
E11 VSS_ANA VSS_ANA AC6
E15 VSS_ANA VSS_ANA AC8
E16 VSS_ANA VSS_ANA AC10
E22 VSS_ANA VSS_ANA AC12
E23 VSS_ANA VSS_ANA AC14
3 3
F9 VSS_ANA VSS_ANA AC16
F16 VSS_ANA VSS_ANA AC18
F20 VSS_ANA VSS_ANA AC20
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
+3.3V_TBT_S0 change pn to SHI0000N600 +3.3V_TBT H1 VSS_ANA VSS E4
H2 VSS_ANA VSS E5
1 2 H12 VSS_ANA VSS E6
LT2 1UH_LQM18NN1R0K00D_10% H13 VSS_ANA VSS F5
VSS_ANA VSS
47U_0805_6.3V6M
47U_0805_6.3V6M
1U_0402_6.3V6K
H15 F6
VSS_ANA VSS
CT67
1 1 H16 H5
VSS_ANA VSS
1
CT68
CT69
H20 H8
J5 VSS_ANA VSS J8
J18 VSS_ANA VSS J12
2
2 2 J19 VSS_ANA VSS J13
J20 VSS_ANA VSS J15
J22 VSS_ANA VSS L13
J23 VSS_ANA VSS M11
K1 VSS_ANA VSS M12
K2 VSS_ANA VSS N8
L5 VSS_ANA VSS N9
L20 VSS_ANA VSS N11
L22 VSS_ANA VSS N12
L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
N5 VSS_ANA VSS T16
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
N20 VSS_ANA VSS T18
N22 VSS_ANA VSS AB1
N23 VSS_ANA VSS AC2
VSS_ANA VSS
P1
P2
R5
R18
R19
R20
R22
R23
T1
T2
T5
T20
U22
U23
4 4
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE:
Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
TBT-AR-SP(2/2) PWR,VSS
Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 23 of 58
A B C D E
5 4 3 2 1
+3.3V_TBTA_FLASH +3.3V_TBTA_FLASH
+3.3V_VDD_PIC
For AR port1
2
.1U_0402_16V7K
2
2
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
3.3K_0402_5%
CT70
1
1 6 UPD1_SMBCLK_Q
<32> UPD1_SMBCLK
RT50
RT51
RT52
RT53
@ QT1A
2 DMN66D0LDW-7_SOT363-6
1
1
@ RT58 1 2 0_0402_5%
UT6
TBTA_ROM_CS#_PD_R
5
8 1
TBTA_ROM_HOLD#_PD 7 VCC CS# 2 TBTA_ROM_DO_PD_R
Vinafix.com
TBTA_ROM_CLK_PD_R 6 HOLD#(IO3) DO(IO1) 3 TBTA_ROM_WP#_PD 4 3 UPD1_SMBDAT_Q
TBTA_ROM_DI_PD_R CLK WP#(IO2) <32> UPD1_SMBDAT
5 4
DI(IO0) GND @ QT1B
GD25Q80CSIGR_SO8 DMN66D0LDW-7_SOT363-6
@ RT59 1 2 0_0402_5%
D D
TBTA_ROM_CLK_PD_R @ RT54 1 2 0_0402_5% TBTA_ROM_CLK_PD
TBTA_ROM_DI_PD_R @ RT55 1 2 0_0402_5% TBTA_ROM_DI_PD
TBTA_ROM_DO_PD_R @ RT56 1 2 0_0402_5% TBTA_ROM_DO_PD @ RT60 1 2 0_0402_5% UPD1_SMBINT#_R
TBTA_ROM_CS#_PD_R <32> UPD1_SMBINT#
@ RT57 1 2 0_0402_5% TBTA_ROM_CS#_PD
+3.3V_TBTA_FLASH
JDB1
1
1 2 TBTA_ROM_CLK_PD_R
2 3 TBTA_ROM_DI_PD_R
3 4 TBTA_ROM_DO_PD_R
7 4 5 TBTA_ROM_CS#_PD_R
8 GND 5 6
GND 6
ACES_50506-00641-P01
CONN@ +5V_ALW
+TBTA_Vbus_1
PJP8 TI is 1x47uf+1x0.1uf
1 2
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
22U_0805_25V6M
PAD-OPEN 1x3m
1 1 1 1
CT75
CT76
CT77
CT78
2 2 2 2
DIV = R2/(R1+R2)
Factory Device Description
DIV_min DIV_max Configuration
UFP only +TBTA_LDO_BMC
5V @0.9A Sink capability with "Ask for Max/" for +VCC1V8D_TBTA_LDO RT64 @ 1 2 0_0402_5%
0.00 0.08 0 anything from 0.9 -3.0A +VCC1V8A_TBTA_LDO
TBT Alternate Modes not supported RT65 @ 1 2 0_0402_5%
DisplayPort Alternate Modes not supported +3.3V_VDD_PIC +3.3V_VDD_PIC_PDA
HV_GATE1_A
HV_GATE2_A
2.2U_0402_16V6K
2.2U_0402_16V6K
2.2U_0402_16V6K
TI VID supported PJP7
C 1 1 1 C
TI is 3x1uf 1 2
+5V_ALW_PDA
CT71
CT72
CT73
UFP only
5V @0.9A Sink capability with "Ask for Max/" for PAD-OPEN1x1m
1U_0402_10V6K
1
anything from 0.9 -3.0A 2 2 2
CT74
0.10 0.18 1 @ RT63 1 2 0_0402_5%
TBT Alternate Modes not supported +3.3V_TBTA_FLASH
DisplayPort Alternate Modes -Sink, C and D pin configuration
TI VID supported
H10
C11
D11
A11
B11
B10
A10
2
H1
B1
K1
A2
E1
A6
A7
A8
B7
B9
A9
UT5
2
UFP only F1
VIN_3V3
PP_5V0
PP_5V0
PP_5V0
PP_5V0
HV_GATE1
HV_GATE2
LDO_1V8A
PP_CABLE
SENSEP
VDDIO
LDO_1V8D
LDO_BMC
GND
GND
GND
GND
SENSEN
0.20 0.28 2 5V @3.0A Source capability I2C_ADDR
TBT Alternate Modes not supported 10K_0402_1% D1
DisplayPort Alternate Modes not supported <22> TBT_I2C_SDA I2C_SDA1 +TBTA_Vbus_1
RT76 D2
TI VID supported +3.3V_TBTA_FLASH <22> TBT_I2C_SCL I2C_SCL1
C1
<22> TBTA_I2C_INT
1
PD1_GPIO8 I2C_IRQ1_N TI has 1x1uf
UFP only +3.3V_ALW
1
0.30 0.38 3 5V @3.0A Source capability 3.3K_0402_5% 2 1 RT66 @ UPD1_SMBDAT_Q A5 +3.3V_PDA_VOUT +3.3V_TBTA_FLASH
TBT Alternate Modes not supported RT377 3.3K_0402_5% 2 1 RT67 @ UPD1_SMBCLK_Q B5 I2C_SDA2 H11
UPD1_SMBINT#_R I2C_SCL2 VBUS
1
DisplayPort Alternate Modes -Sink, C and D pin configuration
CT82
10K_0402_5% 2 1 RT68 @ B6 J10
1U_0603_50V6K
TI VID supported 43K_0402_1%
I2C_IRQ2_N VBUS J11
10U_0603_6.3V6M
1U_0402_10V6K
PD1_GPIO0 VBUS 1 1
@ RT69 2 1 B2 K11
CT83
0_0402_5%
2
2
@ RT70 1 2 EN_PD_HV_1_R C2 GPIO0 VBUS
CT84
DRP 0_0402_5%
5V @0.9-3.0A Sink capability <51> EN_PD_HV_1 PD1_GPIO2 GPIO1
RT71 2 1 1M_0402_5% D10
0.40 0.48 5V @3.0A Source capability @ RT72 1 2 0_0402_5% AC1_DISC#_R G11 GPIO2 2 2
TBT Alternate Modes not supported <50,51> AC1_DISC# TBTA_HPD_R GPIO3
4 @ RT73 1 2 0_0402_5% C10
DisplayPort Alternate Modes not supported <22> TBTA_HPD PD1_GPIO5 GPIO4
@ RT74 2 1 0_0402_5% E10 H2
TI VID supported PD1_GPIO6 GPIO5 VOUT_3V3
Accepts data and power role swaps, but does not @ RT75 2 1 0_0402_5% G10
@ RT339 2 1 0_0402_5% PD1_GPIO7 D7 GPIO6
initiate. PD1_GPIO8 GPIO7
H6
GPIO8 G1
GPIO8: USB_TYPEC_FAULT# TBTA_ROM_CLK_PD LDO_3V3
DRP A3
5V @0.9-3.0A Sink capability TBTA_ROM_DI_PD B4 SPI_CLK
5V @3.0A Source capability TBTA_ROM_DO_PD A4 SPI_MOSI
0.50 0.58 5 TBT Alternate Modes not supported 1 2 TBTA_ROM_CS#_PD B3 SPI_MISO K6
DisplayPort Alternate Modes - Source, C, D, and E <10> USB20_P1 SPI_SS_N C_USB_TP TBTA_TOP_P <26>
@ RT400 1 2 0_0402_5% L6 TBTA_TOP_N <26>
pin configurations. <10> USB20_N1 TBTA_USB20_P_R C_USB_TN
TI VID supported @ RT401 1 2 0_0402_5% L5
<22> TBTA_USB20_P @ RT402 1 TBTA_USB20_N_R USB_RP_P
Accepts power role swaps but will not initiate. 2 0_0402_5% K5
<22> TBTA_USB20_N @ RT403 UART_MOSI USB_RP_N
Accepts data role swap to UFP and can initiate. 0_0402_5%
1 2 E2 K7
UART_MISO UART_TX C_USB_BP TBTA_BOT_P <26>
DRP @ RT83 0_0402_5% F2 L7 TBTA_BOT_N <26>
5V @0.9-3.0A Sink capability UART_RX C_USB_BN
5V @3.0A Source capability 0_0402_5% 2 1 @ RT84 F4
TBT Alternate Modes not supported @ T219 PAD~D SWD_DATA
B 0.60 0.68 6 0_0402_5% 2 1 @ RT85 G4 TI has 2x220pf B
DisplayPort Alternate Modes - Source, C, D, and E @ T220 PAD~D SWD_CLK TBTA_CC1 <26>
L9
pin configurations. C_CC1 L10
TI VID supported UART_MOSI C_CC2 WHEN
2 1 CONNECT BUSPOWERZ TO GND,
820PF_0402_50V7K
820PF_0402_50V7K
Accepts power role swaps but will not initiate. TBTA_MRESET TBTA_CC2 <26>
Accepts data role swap to DFP and can initiate. 100K_0402_5% RT81 RT86 2 1 1M_0402_5% E11 CONNECT ALSO RPD_Gn to C_CCn 1 1
2 1 UART_MISO MRESET
CT85
CT86
0.70 1.00 7 Infinite boot retry from Flash to Host I/F cycles. 1M_0402_5% @ RT82 K9 1 2
TBTA_LSTX 1 2 TBTA_LSTX_R L4 RPD_G1 K10 @ RT104 1 2 0_0402_5%
<22> TBTA_LSTX TBTA_LSRX @ RT87 1 2 0_0402_5% TBTA_LSRX_R K4 TBT_LSTX/R2P RPD_G2 @ RT105 0_0402_5% +3.3V_TBTA_FLASH 2 2
TI ref ckt: 100k <22> TBTA_LSRX @ RT88 0_0402_5% TBT_LSRX/P2R
Intel ref ckt: 1M
TBTA_LSTX 1 2 TBTA_DEBUG3 L3 E4 TBTA_DBG_CTL1 RT106 1 2 10K_0402_5%
TBTA_LSRX @ RT89 1 2 0_0402_5% TBTA_DEBUG4 K3 DIG_AUD_P/DEBUG3 DEBUG_CTL1 D5 TBTA_DBG_CTL2 RT107 1 2 10K_0402_5%
@ RT90 0_0402_5% DIG_AUD_N/DEBUG4 DEBUG_CTL2
UPD1_SMBCLK_Q 1 2 TBTA_DEBUG1 L2
UPD1_SMBDAT_Q @ RT92 1 2 0_0402_5% TBTA_DEBUG2 K2 DEBUG1
@ RT93 0_0402_5% DEBUG2
K8 TBTA_SBU1_R 1 2
TBTA_AUXP_C C_SBU1 TBTA_SBU1 <26>
CT80 1 2 0.1U_0201_10V6K J1 @ RT108 0_0402_5%
<22> TBTA_AUXP TBTA_AUXN_C AUX_P TBTA_SBU2_R
CT81 1 2 0.1U_0201_10V6K J2 L8 1 2
<22> TBTA_AUXN AUX_N C_SBU2 @ RT109
TBTA_SBU2 <26>
0_0402_5%
+3.3V_TBTA_FLASH
F10
BUSPOWER_N F11 TBTA_RESET_N_EC_R @ RT110 1 2 0_0402_5%
+3.3V_TBTA_FLASH RESET_N TBT_RESET_N_EC <22,32>
TBTA_AUXN_C TBTA_ROSC
HRESET
2 1 G2
100K_0402_5% RT95 R_OSC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
15K_0402_1%
SS
TBTA_AUXP_C
2
2 1 @
0_0402_5%
RT100
100K_0402_5% RT96 TPS65982DC_BGA96
A1
D6
E5
E6
E7
F5
G5
H4
H5
B8
D8
E8
F6
F7
F8
G6
G7
G8
H7
H8
L1
L11
RT98
2
1
+VCC1V8D_TBTA_LDO 1 2
@ RT97 0_0402_5%
100K_0402_5%
1
0_0402_5%
1
2
RT101
@ RT103
CT87
@RT99
0_0402_5% 0.22U_0402_16V7K
2
2
2
A A
1
Need Link TPS65982D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
[Type C]PD Controller TI
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Rev
LA-F311P 2.0
Date: Wednesday, December 20, 2017 Sheet 24 of 58
5 4 3 2 1
5 4 3 2 1
+5V_ALW
DT1 +5V_PD_VDD
+5V_TBT_VBUS
2 1
1N4148WS-L_SOD323-2
Vinafix.com 1
UT7
5
+3.3V_VDD_PIC
DT2 VCC VOUT
D 2 1 2 D
100K_0402_5%
GND
1
@
0.1U_0201_10V6K
1U_0402_10V6K
1N4148WS-L_SOD323-2 3 4
RT393
1 1 EN ADJ/NC
2.2U_0603_25V6K
0.1U_0402_25V6K
1
1
CT88
CT89
@
CT91
CT92
1 2 AP2112K-3.3TRG1_SOT23-5
2
2 2 RT111 100K_0402_5%
2
1
CT90
1U_0402_10V6K
2
+TBTA_VBUS_1
UT8
place near UT7
1
VCC
1U_0603_50V6K
DT3 1
1 2+5V_TBTA_VBUS_D3
VOUT
CT94
2
1N4148WS-L_SOD323-2 GND
AP2204R-5.0TRG1_SOT89-3 2
1U_0402_10V6K
1
CT93
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD [Type C]PD Power
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number R ev
LA-F311P 2.0
Date: Wednesday, December 20, 2017 Sheet 25 of 58
5 4 3 2 1
5 4 3 2 1
For AR Config
Vinafix.com
D D
Check ,FROM PWR PAGE
+TBTA_VBUS +TBTA_VBUS
RF Request
JUSBC1 +TBTA_VBUS
A1 B12
GND_A1 GND_B12 +TBTA_VBUS
1 2 TBTA_TX1P_C A2 B11 TBTA_RX1P
<22> TBTA_TX1P SSTXp1 SSRXp1 TBTA_RX1P <22>
CT95 1 2 0.22U_0201_6.3V6K TBTA_TX1N_C A3 B10 TBTA_RX1N
<22> TBTA_TX1N SSTXn1 SSRXn1 TBTA_RX1N <22>
CT96 0.22U_0201_6.3V6K
2 1 A4 B9 1 2
CT99 0.47U_0201_25V VBUS_A4 VBUS_B9 CT100 0.47U_0201_25V
2
TBTA_CC1 A5 B8 TBTA_SBU2
<24> TBTA_CC1 CC1 SBU2 TBTA_SBU2 <24>
ESD@ DT4
TBTA_TOP_P_R TBTA_BOT_N_R
12P_0402_50V8J
RF@ CT189
@EMI@ RT120 1 2 0_0402_5% A6 B7 @EMI@ RT122 1 2 0_0402_5% AZ4024-02S_SOT23-3
<24> TBTA_TOP_P TBTA_TOP_N_R Dp1 Dn2 TBTA_BOT_P_R TBTA_BOT_N <24> 1
@EMI@ RT121 1 2 0_0402_5% A7 B6 @EMI@ RT123 1 2 0_0402_5%
Bottom
C <24> TBTA_TOP_N Dn1 Dp2 TBTA_BOT_P <24> C
TOP
TBTA_SBU1 A8 B5 TBTA_CC2
<24> TBTA_SBU1 SBU1 CC2 TBTA_CC2 <24> 2
2 1 A9 B4 1 2
0.47U_0201_25V CT101 VBUS_A9 VBUS_B4 CT102 0.47U_0201_25V
1
TBTA_RX2N A10 B3 TBTA_TX2N_C 2 1
<22> TBTA_RX2N TBTA_RX2P A11 SSRXn2 SSTXn2 B2 TBTA_TX2P_C 0.22U_0201_6.3V6K 2 1 CT98 TBTA_TX2N <22>
<22> TBTA_RX2P SSRXp2 SSTXp2 TBTA_TX2P <22>
0.22U_0201_6.3V6K CT97
A12 B1
GND_A12 GND_B1
1 2
3 GND1 GND2 4
GND3 GND4
JAE_DX07B024XJ1R1300~D
CONN@
Premium 12/14/15 UMA:Check SBU1/SBU2 connect to PD or PS8740B
Link DC23300MEBL Done
ESD@ DT5 ESD@ DT13
B
TBTA_TX1P_C 1 2 TBTA_RX1P 1 2 B
AZ5B75-01B AZ5B75-01B
ESD@ DT6 ESD@ DT14
TBTA_TX1N_C 1 2 TBTA_RX1N 1 2
AZ5B75-01B AZ5B75-01B
ESD@ DT9
ESD@ DT17
TBTA_RX2N 1 2
TBTA_TX2P_C 1 2
AZ5B75-01B
AZ5B75-01B
ESD@ DT10
ESD@ DT18
TBTA_RX2P 1 2
TBTA_TX2N_C 1 2
AZ5B75-01B
AZ5B75-01B
DT39 ESD@ DT40 ESD@
TBTA_CC1 1 1 TBTA_CC1 TBTA_SBU2 TBTA_SBU2
10 9 1 1 10 9
TBTA_TOP_P_R 2 2 9 8
TBTA_TOP_P_R TBTA_BOT_N_R 2 9 8
TBTA_BOT_N_R
2
TBTA_TOP_N_R 4 4 7 7
TBTA_TOP_N_R TBTA_BOT_P_R 4 7 7
TBTA_BOT_P_R
A 4 A
TBTA_SBU1 5 5 6 6
TBTA_SBU1 TBTA_CC2 5 5 6 6
TBTA_CC2
3 3 3 3
8 8
AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
PROPRIETARY NOTE: Compal Electronics, Inc.
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USB 3.0 CONN TYPE C
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 26 of 58
5 4 3 2 1
5 4 3 2 1
LINK 50398-04041-001 DONE
JEDP1
1
+3.3V_TSP
TOUCH_PANEL_INTR#:
Close lid >> TP_EN = 0 >> Disable touch events
Open lid >> TP_EN = 1 >> Enable touch events 4
EXC24CQ900U_4P
3
For 2LANE EDP &3.3V_TSP
1 USB20_N8_R USB20_N8 <10>
2
2
3
4
3
4
5
USB20_P8_R
1 2
USB20_P8 <10>
For Breckenridge&Steamboat 12
5 6 TOUCH_SCREEN_PD# <12> LV27 EMI@
6
AZC199-02SPR7G_SOT23-3
7
7 DMIC0 <31>
@ESD@
8
8 9
3
9 10 DMIC_CLK0 <31>
10 +3.3V_RUN
11 RF Request
11 USB20_N5_R +3.3V_CAM
Vinafix.com
1
100P_0402_50V8J
@EMI@ CA5
100P_0402_50V8J
@EMI@ CA6
12
12 USB20_P5_R +3.3V_TSP
DV4
13
1
13
1
14
14 CAM_MIC_CBL_DET# <12>
15
15 Pin15: LOOP_BACK
D 16 D
2
16 17
17 +BL_PWR_SRC
18
18 19 +3.3V_RUN
19 ESD depop locat i on
20
20 BIA_PWM
12P_0402_50V8J
RF@ CV18
82P_0402_50V8J
RF@ CV19
10K_0402_5%
21 EMI@ LV1 1 2 1 1
21
2
22 DISP_ON BLM15PX221SN1D_2P EMI Request
RV8
22 23
23 24
24 25 2 2
25 26 +LCDVDD
EDP_HPD <6>
1
26 27 TOUCH_SCREEN_DET#
27 28 EDP_HPD 1 2
28 29 @ RV7 100K_0402_5%
29 30 LCD_TST <32> Due to SB12/14 Mic. receive path is dif f er ent
30 31 +LCDVDD Reserve for EA between Touch and Non-Touch Panel, so add
31 TOUCH_SCREEN_DET#
32 TOUCH_SCREEN_DET# pin for dif f er ent ver b
32 33 EDP_AUXN_C CV1 2 1TOUCH_SCREEN_DET#
0.1U_0402_25V6
<12>
table
33 34 EDP_AUXP_C 2 1 0.1U_0402_25V6 EDP_AUXN <6>
CV2
34 EDP_TXP0_C EDP_AUXP <6>
35 CV3 2 1 0.1U_0402_25V6
41 35 36 EDP_TXN0_C 2 1 0.1U_0402_25V6 EDP_TXP0 <6>
CV4
G1 36 EDP_TXP1_C EDP_TXN0 <6> USB20_N5_R
42 37 CV5 2 1 0.1U_0402_25V6
43 G2 37 38 EDP_TXN1_C 2 1 0.1U_0402_25V6 EDP_TXP1 <6> USB20_P5_R
CV6
G3 38 EDP_TXN1 <6>
44 39
45 G4 39 40
G5 40 LCD_CBL_DET# <9>
ACES_50398-04041-001
@ESD@
@ESD@
CONN@
ESD8011MUT5G_X3DFN2-2
ESD8011MUT5G_X3DFN2-2
CONN@ JIR1
1
1 +PWR_SRC
1 2
2 RF Request
+BL_PWR_SRC +LCDVDD +3.3V_CAM +3.3V_TSP +3.3V_RUN 3
3 +PWR_SRC
DV7
DV8
4
4
0.1U_0603_50V7K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
7 5
8 GND 5 6
1 1 1 1 GND 6 IR_CAM_DET# <12>
1
100P_0402_50V8J
RF@ CZ3
@
@ @ @ @
1
CV11
CV12
CZ1
CZ2
CA7
E-T_4251K-F06N-40L
2
2
2 2 2 2
C 2 C
Close to JEDP1.17~19 Close to JEDP1.30~31 Close to JEDP1.11 Close to JEDP1.1 Close to JEDP1.10
ESD depop locat i on
DV1 DV2
3 EDP_BIA_PWM 3
EDP_BIA_PWM <6> PANEL_BKLEN <6>
BIA_PWM 1 DISP_ON 1
2 BIA_PWM_EC 2
BIA_PWM_EC <32> PANEL_BKEN_EC <32>
1
4.7K_0402_5%
4.7K_0402_5%
1
BAT54CW_SOT323-3 BAT54CW_SOT323-3
For Touchscreen
RV1
RV2
2
+3.3V_RUN +3.3V_TSP +3.3V_RUN
2
QV8
10K_0402_5%
LP2301ALT1G_SOT23-3
2
+3.3V_RUN 1 3
RV6
S
100K_0402_5%
G
1
2
1
RF Request
RV326
+LCDVDD +3.3V_CAM +BL_PWR_SRC 1 2
RV400 0_0402_5%
L2N7002WT1G_SC-70-3
1
D
0.1U_0402_25V6K
1
3.3V_TS_EN_R
QV7
@ RV323 1 2 0_0402_5% 2 @
<32> 3.3V_TS_EN
CV635
G
@ RV324 1 2 0_0402_5% S
<9> PCH_3.3V_TS_EN
2
12P_0402_50V8J
RF@ CV20
82P_0402_50V8J
RF@ CV21
12P_0402_50V8J
RF@ CV22
82P_0402_50V8J
RF@ CV23
12P_0402_50V8J
RF@ CV24
82P_0402_50V8J
RF@ CV25
B 1 1 1 1 1 1 B
2 2 2 2 2 2
LCDVDD POWER +LCDVDD +EDP_VDD
+3.3V_ALW
@
CV16 PJP13 UV24
2 1 1 2 1
WebCAM +3.3V_CAM +3.3V_RUN
Backlight POWER +BL_PWR_SRC 10U_0603_10V6M
VOUT
VIN
5
PAD-OPEN1x1m 2
GND
0.01UF_0402_25V7K
QZ1 +PWR_SRC QV1 4
EN
@
LP2301ALT1G_SOT23-3
CV17
6 3
D
1 3 4 5 /OC
D
2 G524B1T11U_SOT23-5
2
1 DV3
1000P_0402_50V7K
0.1U_0603_50V7K
G
G
270K_0402_5%
2
AO6405_TSOP6 2
<32> LCD_VCC_TEST_EN
CV13
3
2
1 EN_LCDPWR
RV4
CV15
1 2
<11> 3.3V_CAM_EN#
RZ380 0_0402_5% 3
<6> ENVDD_PCH
1
2
0.1U_0402_25V6K
100K_0402_5%
1
1
RV3
@
CZ200
BAT54CW_SOT323-3
BL_PWR_SRC_ON
2
1
QV2
A A
L2N7002WT1G_SC-70-3
0.01U_0402_50V7K
1
1 2 1 3
D
S
CV14
RV5 47K_0402_5%
EXC24CQ900U_4P
4 3 USB20_P5_R 2
G
<10> USB20_P5
2
<10> USB20_N5
1 2 USB20_N5_R
<32> EN_INVPWR
DELL CONFIDENTIAL/PROPRIETARY
LZ1 EMI@
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, eDP CONN & Touch screen
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 27 of 58
5 4 3 2 1
5 4 3 2 1
Layout Not i ce : Pl ace bead as
+3.3V_LAN UL1 close UL4 as possible
2 1 TP_LAN_JTAG_TMS CLKREQ_PCIE#4 48 13 LAN_MDIP0 RL71 1 2 2.2_0603_5% LAN_MDIP0_L
<11> CLKREQ_PCIE#4 CLK_REQ_N MDI_PLUS0 LAN_MDIN0 LAN_MDIN0_L
@ RL1 10K_0402_5% 36 14 RL72 1 2 2.2_0603_5%
TP_LAN_JTAG_TCK <11> PLTRST_LAN# PE_RST_N MDI_MINUS0
2 1
@ RL2 10K_0402_5% 44 17 LAN_MDIP1 RL73 1 2 2.2_0603_5% LAN_MDIP1_L
CLKREQ_PCIE#4 <11> CLK_PCIE_P4 PE_CLKP MDI_PLUS1 LAN_MDIN1 LAN_MDIN1_L
2 1 45 18 RL74 1 2 2.2_0603_5%
<11> CLK_PCIE_N4
PCIE
1 2 PCIE_PRX_C_DTX_P4 PE_CLKN MDI_MINUS1
MDI
@ RL4 4.7K_0402_5%
<10> PCIE_PRX_DTX_P4 LAN_MDIP2 LAN_MDIP2_L
CL1 0.1U_0402_25V6 38 20 RL75 1 2 2.2_0603_5%
1 2 PCIE_PRX_C_DTX_N4 39 PETp MDI_PLUS2 21 LAN_MDIN2 RL76 1 2 2.2_0603_5% LAN_MDIN2_L
<10> PCIE_PRX_DTX_N4 PETn MDI_MINUS2
CL2 0.1U_0402_25V6
+3.3V_LAN 1 2 PCIE_PTX_C_DRX_P4 41 23 LAN_MDIP3 RL77 1 2 2.2_0603_5% LAN_MDIP3_L
Vinafix.com
<10> PCIE_PTX_DRX_P4 PERp MDI_PLUS3 LAN_MDIN3 LAN_MDIN3_L
CL5 0.1U_0402_25V6 42 24 RL78 1 2 2.2_0603_5%
1 2 PCIE_PTX_C_DRX_N4 PERn MDI_MINUS3
<10> PCIE_PTX_DRX_N4
CL6 0.1U_0402_25V6
2
28 6 VCT_LAN_R1 1 2
10K_0402_5%
<8> SML0_SMBCLK
SMBUS
31 SMB_CLK SVR_EN_N @ RL3
D <8> SML0_SMBDATA SMB_DATA
0_0402_5%
+RSVD_VCC3P3_1
RF Request D
1 4.7K_0402_5% 1 2 RL6
RL5 @
RSVD_VCC3P3_1 +3.3V_LAN +3.3V_LAN_OUT
2 5
1
1 2 <11,32> LAN_WAKE# LAN_DISABLE#_R 3 LANWAKE_N VDD3P3_IN
<11> PM_LANPHY_ENABLE LAN_DISABLE_N +3.3V_LAN_OUT
@ RL7 0_0402_5% SMBus Device Address 0xC8 4 1 2
VDD3P3_4 +3.3V_LAN
0_0603_5% @ RL8
10K_0402_5%
0.1U_0201_10V6K
22U_0805_6.3V6M
15 1
VDD3P3_15
1
LOM_ACTLED_YEL#
1
@ RL9
26 19
LOM_SPD100LED_ORG# LED0 VDD3P3_19
CL7
CL28
@RF@ CL29
@RF@ CL30
27 29 Place CL28 close to UL1.5
LOM_SPD10LED_GRN# LED1 VDD3P3_29
LED
+0.9V_LAN
12P_0402_50V8J
82P_0402_50V8J
25 1 1
2
LED2 2
2 47 +3.3V_LAN
VDD0P9_47 46
@ T88 PAD~D TP_LAN_JTAG_TDI 32 VDD0P9_46 37 2 2
@ T89 PAD~D TP_LAN_JTAG_TDO 34 JTAG_TDI VDD0P9_37
JTAG_TDO
JTAG
+0.9V_LAN TP_LAN_JTAG_TMS 33 43
TP_LAN_JTAG_TCK 35 JTAG_TMS VDD0P9_43
JTAG_TCK 11
VDD0P9_11
470P_0402_50V7K
XTALO_R
0.1U_0201_10V6K
1 2 XTALO 9 40 1
XTAL_OUT VDD0P9_40
1
22U_0603_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
@ RL34 0_0402_5% XTALI 10 22
1
XTAL_IN VDD0P9_22
CL18
CL19
1 1 1 1 16
VDD0P9_16
1
+0.9V_LAN
CL9
CL10
CL11
CL8
8
RJ45 LOM circuit
2
LAN_TEST_EN VDD0P9_8 2
CL12
RL11 30
1M_0402_5% TEST_EN
2
2 2 2 2 YL1 RES_BIAS 12 7 +REGCTL_PNP10 1 2
+3.3V_LAN:20mils
2
3 1 RBIAS CTRL0P9 4.7UH +-20% MPB201210T-4R7M-NA2 LL1
OUT IN
0.1U_0201_10V6K
10U_0603_10V6M
49 Idc_min=500mA
VSS_EPAD
27P_0402_50V8J
1
1K_0402_5%
3.01K_0402_1%
4 2 DCR=100mohm 1 @ JLOM1 CONN@
GND GND
27P_0402_50V8J
1
CL3
CL4
WGI219LM-QREF- A0_QFN48_6X6~D
CL14
1
1
LAN_ACTLED_YEL# LAN_ACTLED_YEL_R#
RL12
RL13
Note: 25MHZ_18PF_7V25000034 1 2 10
Yellow LED-
CL13
+1.0V_LAN will work at 0.95V to 1.15V RL14 150_0402_5%
2
change to SA000081G1L ,(S IC WGI219LM SLKJ2 A0 QFN 48P PHY A31 !) 2 9
2
2
Yellow LED+
RJ45_MDIN3 8
PR4-
RJ45_MDIP3 7
Place CL3, CL4 and LL1 close to UL1 PR4+
RJ45_MDIN1 6
PR2-
RJ45_MDIN2 5
PR3-
C RJ45_MDIP2 C
4
PR3+ 17
RJ45_MDIP1 3 GND
PR2+ 16
RJ45_MDIN0 2 GND
PR1- 15
RJ45_MDIP0 1 GND
PR1+ 14
LED_10_GRN# 1 2 LED_10_GRN_R# 11 GND
RL19 150_0402_5% Green LED-
LED_100_ORG# 1 2 LED_100_ORG_R# 13
RL20 150_0402_5% Orange LED-
12
Green-Orange LED+
SANTA_130470-19
Link DC231603220 (temp) DONE
TL1
LAN_MDIN3_L 1 1:1 24 RJ45_MDIN3
TD1+ TX1+
When LAN & WLAN are exist at the same time, WLAN will disable
LAN_MDIP3_L 2
TD1- 23 RJ45_MDIP3
TX1-
+3.3V_LAN
3 22 Z2805
@ CL15 TDCT1 TXCT1
1 2
4 21 Z2807
LAN_MDIN1_L TDCT2 TXCT2 20 RJ45_MDIN1
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K 5 1:1
TD2+ TX2+
5
LOM_SPD100LED_ORG#
1
1
P
B
CL16
CL17
4
LOM_SPD10LED_GRN# 2 O LOM_CABLE_DETECT# <32>
2
A LAN_MDIP1_L 19 RJ45_MDIP1
G
UL2 6
TC7SH08FU_SSOP5~D TD2- TX2-
B B
3
LAN_MDIN2_L 7 1:1 18 RJ45_MDIN2
QL1A TD3+ TX3+
DMN65D8LDW-7_SOT363-6
LOM_ACTLED_YEL# 1 6 LAN_ACTLED_YEL#
LAN_MDIP2_L 8
TD3- 17 RJ45_MDIP2
+3.3V_LAN TX3-
2
LED_MASK# 9 16 Z2806
LED_MASK# <32,39> TDCT3 TXCT3
1
RL29
1M_0402_5% 10 15 Z2808
LAN_MDIN0_L TDCT4 TXCT4 14 RJ45_MDIN0
0.1U_0201_10V6K
0.1U_0201_10V6K
QL1B 11 1:1
TD4+ TX4+
1 75_0402_1%
1 75_0402_1%
1 75_0402_1%
1 75_0402_1%
DMN65D8LDW-7_SOT363-6
2
LOM_SPD100LED_ORG#
4 3 LED_100_ORG#
1
+3.3V_LAN
CL20
CL21
LAN_MDIP0_L 12 13 RJ45_MDIP0
5
TD4- TX4-
1
LED_MASK#
RL30
1M_0402_5% MHPC_NS692417
QL2A
DMN65D8LDW-7_SOT363-6
2
RL15 2
RL16 2
RL17 2
RL18 2
LOM_SPD10LED_GRN# 1 6 LED_10_GRN#
GND 1 2 +GND_CHASSIS
2
EMI@ CL22 10P_1808_3KV8J
LED_MASK# CHASSIS use 40mil trace if necessary
For WLAN can't recognize during enable
Unobtrusive mode(BITS152312) 0601:EMI ask to change 150pF
QL2B
DMN65D8LDW-7_SOT363-6
4 3
A A
5
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LAN Clarkvillie & RJ45
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 28 of 58
5 4 3 2 1
A B C D E
For PCIE Interface
Vinafix.com
1 1
+3.3V_RUN +3.3V_MMI_IN
PJP14
1 2
RF Request +3.3V_MMI_AUX +3.3V_MMI_IN
+3.3V_MMI_AUX +3.3V_MMI_IN PAD-OPEN1x2m
+3.3V_MMI_IN +3.3V_MMI_AUX
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0402_6.3V6M
@ RR274 1 2 0_0603_5%
support D3 Hot(if D3 cold PIN11,PIN27 need Add MOS on/of f 3V3AUX)
1 1 1 1
CR4
CR3
CR1
CR2
@RF@ CR27
@RF@ CR28
@RF@ CR25
@RF@ CR26
2 2 2 2
12P_0402_50V8J
82P_0402_50V8J
12P_0402_50V8J
82P_0402_50V8J
1 1 1 1
+3.3V_MMI_AUX
2 2 2 2
2 1 MEDIACARD_IRQ# 7/18 Vender suggest.
RR19 10K_0402_5%
27
11
UR1
3V3aux
3V3_IN
1 12
<11,22,30,34,35> PCH_PLTRST#_AND PERST# CARD_3V3 +DV33_18 +3.3V_RUN_CARD
2 18 1 2
<11> CLKREQ_PCIE#0 CLK_REQ# DV33_18 CR22 1U_0402_6.3V6K
5
<11> CLK_PCIE_P0 REFCLKP SD/MMCDAT1/RCLK-_R
6 15 SD/MMCDAT1/RCLK- @ RR9 1 2 0_0402_5%
<11> CLK_PCIE_N0 REFCLKN SP1 SD/MMCDAT0/RCLK+_R
16 SD/MMCDAT0/RCLK+ @ RR10 1 2 0_0402_5%
CR11 1 2 0.1U_0402_25V6 PCIE_PTX_C_DRX_P1 3 RTS5242 SP2 17 SD/MMCCLK @EMI@ RR5 1 2 0_0402_5% SD/MMCCLK_R
<10> PCIE_PTX_DRX_P1 PCIE_PTX_C_DRX_N1 HSIP SP3 SD/MMCCMD_R
@EMI@ CR21
CR12 1 2 0.1U_0402_25V6 4 19 SD/MMCCMD @ RR6 1 2 0_0402_5%
<10> PCIE_PTX_DRX_N1 PCIE_PRX_C_DTX_P1 HSIN SP4 SD/MMCDAT3_R
5P_0402_50V8C
CR13 1 2 0.1U_0402_25V6 7 20 SD/MMCDAT3 @ RR7 1 2 0_0402_5%
<10> PCIE_PRX_DTX_P1 CR14 1 2 0.1U_0402_25V6 PCIE_PRX_C_DTX_N1 8 HSOP SP5 21 SD/MMCDAT2 @ RR8 1 2 0_0402_5% SD/MMCDAT2_R
<10> PCIE_PRX_DTX_N1 HSON SP6
1
29 SDWP
SP7
32
2
2 <9> MEDIACARD_IRQ# WAKE# 2
31
SD/MMCCD# 30 MS_INS#
+1.2V_LDO SD_CD#
7/18 Vender suggest
CR13 close to UR2.10 22 SD_UHS2_D1P EMI depop locat i on
CR9 CR10 close to UR2.14
SD_LN1_P 23 SD_UHS2_D1N
10 SD_LN1_M
14 AV12 26 SD_UHS2_D0P
DV12S SD_LN0_P 25 SD_UHS2_D0N
SD_LN0_M
4.7U_0603_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
+1.8V_RUN_CARD 13
SD_VDD2 24 +SDREG2 CR15 1 2
1 1 SDREG2
E-PAD
1
+RREF 9 28
CR5
1U_0402_6.3V6K
CR6
CR7
RREF GPIO SD_GPIO 2 1 +3.3V_MMI_AUX
10K_0402_5% RR3
2
2 2 RTS5242-GR_QFN32_4X4
33
1
6.2K_0402_1%
RR4
2
3 3
QR1
L2N7002WT1G_SC-70-3 JSD1 CONN@
HOST_SD_W P# SDW P_Q SDW P STATUS 4
SDWP_Q +3.3V_RUN_CARD VDD1
SDWP 1 3 15
S
+1.8V_RUN_CARD SD/MMCCMD_R VDD2
3
High Low Low Write Enable SD/MMCCLK_R 5 CMD
CLK
G
2
SD/MMCCD# 9
Low Low High Write Protect(FW LOCK) 16 CD
<12> HOST_SD_WP# SWIO
SD/MMCDAT0/RCLK+_R 7
SD/MMCDAT1/RCLK-_R 8 DAT0/RCLK+
SD/MMCDAT2_R 1 DAT1/RCLK-
SD/MMCDAT3_R 2 DAT2
CD/DAT3
+3.3V_RUN_CARD +1.8V_RUN_CARD
SD_UHS2_D0P 18
SD_UHS2_D0N 19 D0+
SD_UHS2_D1P 22 D0-
SD_UHS2_D1N 21 D1+
0.1U_0201_10V6K
0.1U_0201_10V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
D1-
2 2
2
10
CR17
CR19
CR20
6 GND1 11
CR18
17 VSS1 GND2 12
1
1 1 20 VSS2 GND3 13
23 VSS3 GND4 14
VSS4 GND5
T-SOL_158-1240902600
CR38,CR39 near JSD1.4 CR40,CR41 near JSD1.14
LINK SP071603151 (temp) DONE
4 4
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Card Reader RTS5242
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 29 of 58
A B C D E
5 4 3 2 1
+3.3V_WWAN for AR Steamboat
NGFF slot B Key B
2 1 WWAN_PWR_EN +3.3V_WWAN
NGFF slot A Key A
RZ43 47K_0402_5%
100P_0402_50V8J
JNGFF2 CONN@
RF@ CZ198
1 2
<32> NGFF_CONFIG_3 1 2
3 4 +3.3V_WLAN
3 4
1
5 6 WWAN_PWR_EN
Vinafix.com
USB20_P4_L 7 5 6 8 WWAN_RADIO_DIS#_R JNGFF1 CONN@
USB20_N4_L 9 7 8 10 1 2
2
11 9 10 USB20_P7_L 3 1 2 4
11 USB20_N7_L 5 3 4 6
7 5 6
D 7 D
12
13 12 14 16
<32> NGFF_CONFIG_0 13 14 16
15 16 17 18
<32> WWAN_WAKE# 15 16 GPS_DISABLE#_R 17 18
2 1 17 18 19 20
@RF@ RZ326 0_0402_5% 19 17 18 20 21 19 20 22
USB3_PRX_L_DTX_N2 21 19 20 22 UIM_RESET 23 21 22 24
USB3_PRX_L_DTX_P2 23 21 22 24 UIM_CLK 25 23 24 26
25 23 24 26 UIM_DATA 27 25 26 28
Drop HCA function in DVT1.0 USB3_PTX_L_DRX_N2 27 25 26 28 29 27 28 30
USB3_PTX_L_DRX_P2 27 28 +SIM_PWR 29 30
29 30 31 32
29 30 ISH_I2C2_SCL_R M3042_DEVSLP <10> 31 32
31 32 2 1 33 34
31 32 ISH_I2C2_SDA_R ISH_I2C2_SCL <9> PCIE_PTX_C_DRX_P3 33 34
33 34 @ RZ76 2 1
0_0402_5% CZ12 1 2 0.1U_0402_25V6 35 36
33 34 ISH_I2C2_SDA <9> <10> PCIE_PTX_DRX_P3 PCIE_PTX_C_DRX_N3 35 36
35 36 @ RZ77 0_0402_5% CZ13 1 2 0.1U_0402_25V6 37 38
35 36 <10> PCIE_PTX_DRX_N3 37 38 PCH_CL_RST1# <8>
37 38 9/24: Reserve for embedded locat i on , r ef er I nt el P DG 0. 9WLAN 39 40
37 38 39 40 PCH_CL_DATA1 <8>
39 40 41 42
39 40 PCH_PLTRST#_AND <10> PCIE_PRX_DTX_P3 41 42 WLAN_COEX3 PCH_CL_CLK1 <8>
41 42 43 44
43 41 42 44 <10> PCIE_PRX_DTX_N3 45 43 44 46 WLAN_COEX2
45 43 44 46 PCIE_WAKE# 47 45 46 48 WLAN_COEX1
45 46 <11> CLK_PCIE_P1 47 48 WIGIG_32KHZ
47 48 49 50 @ RZ56 1 2 0_0402_5%
47 48 <11> CLK_PCIE_N1 49 50 PCH_PLTRST#_AND SUSCLK <11,35>
49 50 @ RZ132 2 1 0_0402_5% 51 52
HOST_DEBUG_TX WLAN_COEX3
2 0_0201_5% <32,33>
49 50 WWAN_COEX3 51 52 BT_RADIO_DIS#_R PCH_PLTRST#_AND <11,22,29,34,35>
51 52 @RF@ RZ128 1 53 54
51 52 WWAN_COEX2 <11> CLKREQ_PCIE#1 53 54
53 54 @RF@ RZ129 1 2 0_0201_5% WLAN_COEX2 PCIE_WAKE# 55 56 WLAN_WIGIG60GHZ_DIS#_R
55 53 54 56 WWAN_COEX1 @RF@ RZ130 1 2 0_0201_5% WLAN_COEX1 <22,33,35> PCIE_WAKE# 57 55 56 58 ISH_UART0_RXD_R 2 1
55 56 SIM_DET 57 58 ISH_UART0_TXD_R @ RZ78 2 ISH_UART0_RXD <9>
57 58 59 60 1 0_0402_5%
57 58 59 60 ISH_UART0_CTS#_R @ RZ79 2 ISH_UART0_TXD <9>
PAD~D @ T225 59 60 61 62 1 0_0402_5%
59 60 61 62 ISH_UART0_RTS#_R @ RZ80 2 ISH_UART0_CTS# <9>
61 62 63 64 1 0_0402_5%
<32> NGFF_CONFIG_1 61 62 63 64 PCH_PLTRST#_AND @ RZ81 ISH_UART0_RTS# <9>
63 64 65 66 0_0402_5%
65 63 64 66 67 65 66 68
67 65 66 69 67 68 70 PCIE_WAKE#
<32> NGFF_CONFIG_2 67 69 70
71 72
73 71 72 74
69 68 75 73 74
GND GND 75 9/24: Reserve for embedded locat i on , r ef er I nt el P DG 0. 9
RF Request BELLW_80149-3221 76 77
+3.3V_WWAN +3.3V_WWAN GND GND
8
0
1
4
9
-
3
2
2
1
L
I
N
K
D
O
N
E
LCN_DAN05-67306-0100
.047U_0402_16V7K
.047U_0402_16V7K
33P_0402_50V8J
33P_0402_50V8J
S
P
0
7
0
0
1
9
F
0
0
L
I
N
K
D
O
N
E
C C
22U_0603_6.3V6M
47P_0402_50V8J
100P_0402_50V8J
2200P_0402_50V7K
RF@
1
RF@ CZ24
100U_B2_6.3VM_R35M
RF@CZ26
1
RF@ CZ25
CZ17
CZ18
CZ19
CZ20
CZ21
+
2
CZ23
2
1 2 WWAN_RADIO_DIS#_R
<32> WWAN_RADIO_DIS#
DZ5
RB751S40T1G_SOD523-2 1 2 WLAN_WIGIG60GHZ_DIS#_R +3.3V_WLAN
<32> WLAN_WIGIG60GHZ_DIS#
DZ1
RB751S40T1G_SOD523-2
1 2 GPS_DISABLE#_R
<32> GPS_DISABLE#
0.01UF_0402_25V7K
0.1U_0201_10V6K
10U_0603_10V6M
0.01UF_0402_25V7K
0.1U_0201_10V6K
4.7U_0603_6.3V6K
DZ6
RB751S40T1G_SOD523-2
1 2 1 1 1
1
@RF@ RI27 0_0402_5%
CZ28
CZ30
CZ27
CZ29
CZ31
CZ32
LI16 RF@ 1 2 BT_RADIO_DIS#_R
<32> BT_RADIO_DIS#
2
1 2 USB3_PRX_L_DTX_P2 2 2 2
<10> USB3_PRX_DTX_P2 DZ2
RB751S40T1G_SOD523-2
4 3 USB3_PRX_L_DTX_N2
<10> USB3_PRX_DTX_N2
RF Request
HCM1012GH900BP_4P
2 1 RF Request Place near JNGFF1.72/JNGFF1.74 Place near JNGFF1.2/JNGFF1.4
@RF@ RI28 0_0402_5% 1 2
1 2 @RF@ RI49 0_0402_5%
@RF@ RI29 0_0402_5% 1 2
HCM1012GH900BP_4P @RF@ RI47 0_0402_5%
2 1 USB3_PTX_C_DRX_P2 4 3 USB3_PTX_L_DRX_P2
<10> USB3_PTX_DRX_P2
CI30 0.1U_0402_25V6
MCM1012B900F06BP_4P
2 1 USB3_PTX_C_DRX_N2 1 2 USB3_PTX_L_DRX_N2
<10> USB3_PTX_DRX_N2 USB20_P7_L
RF Request
B CI29 0.1U_0402_25V6 MCM1012B900F06BP_4P 4 3 B
LI17 RF@ <10> USB20_P7
+3.3V_WLAN
4 3 USB20_P4_L
<10> USB20_P4 USB20_N7_L
1 2 1 2
<10> USB20_N7
@RF@ RI30 0_0402_5%
1 2 USB20_N4_L LI9 RF@
<10> USB20_N4
15P_0402_50V8J
15P_0402_50V8J
15P_0402_50V8J
15P_0402_50V8J
LI8 RF@
RF@ CZ33
RF@ CZ34
RF@ CZ35
RF@ CZ36
SIM Card Push-Push
1
1 2
@RF@ RI50 0_0402_5%
1 2
2
@RF@ RI48 0_0402_5%
JSIM1 CONN@
C8 3
UIM_DATA C7 RFU1 GND1 4
C6 IO GND2 5
C5 VPP GND3 6
C4 GND GND4 7
UIM_CLK C3 RFU2 GND5 8
UIM_RESET C2 CLK GND6 9
C1 RST GND7
+SIM_PWR VCC
4.7U_0402_6.3V6M
STATE # CONFIG_0 CONFIG_1 CONFIG_2 CONFIG_3 Module Type
1
1
SIM_DET DLSW
CZ37
2 0 GND GND GND GND SSD-SATA
DTSW
Power Rating TBD
2
S
P
0
7
0
0
1
7
I
0
0
L
I
N
K
D
O
N
E
JAE_SF51S006V4DR1000Q 1 GND HIGH GND GND SSD-PCIE(2 lane)
Primary Power Aux Power
PWR Voltage
8 HIGH GND GND GND W WAN Rail Tolerance
Peak Normal Normal
+SIM_PWR
14 HIGH GND HIGH HIGH HCA-PCIE(1 lane)
+3.3V
UIM_CLK 15 HIGH HIGH HIGH HIGH NA
@RF@ RZ335
1
15K_0402_5%
47P_0402_50V8J
@RF@ CZ38
A A
1
+SIM_PWR
UIM_DATA UIM_RESET
2
33P_0402_50V8J
33P_0402_50V8J
@RF@ RZ334
@RF@ CZ39
@RF@ CZ40
1
51_0402_5%
0.1U_0402_25V6
RF@ CZ41
1
1
DELL CONFIDENTIAL/PROPRIETARY
2
2
Compal Electronics, Inc.
2
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT NGFF Card
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size
RF Request Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 30 of 58
5 4 3 2 1
5 4 3 2 1
SPKR_R
100P_0402_50V8J
10K_0402_5%
1
1
BEEP_R
@ CA72
@ RA51
+5V_RUN_AUDIO
100P_0402_50V8J
10K_0402_5%
LA13
+5V_RUN_PVDD_Lplace close to pin41 place close to pin46
1
@ CA62
@ RA45
1W x 1ch, 4ohm (Transducer spec is 8Ohm/0.5Watt per unit, there are two transducer units in one speaker box.) 1 2
HCB2012VF-601T20_2P
Internal Speakers Header
2
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
0.1U_0201_10V6K
10U_0603_10V6M
1 1 1 1 600 Ohm/2A 1 1
2
CA45
CA47
CA60
CA46
CA48
CA59
40 mils trace keep 20 mil spacing
2
JSPK1 CONN@
Vinafix.com
INT_SPK_L+ EMI@ LA6 1 2 BLM15PX330SN1D_2P INT_SPKR_L+ 1 2 2 2 2 2 2
INT_SPK_L- EMI@ LA7 1 2 BLM15PX330SN1D_2P INT_SPKR_L- 2 1
INT_SPK_R+ EMI@ LA8 1 2 BLM15PX330SN1D_2P INT_SPKR_R+ 3 2
INT_SPK_R- EMI@ LA9 1 2 BLM15PX330SN1D_2P INT_SPKR_R- 4 3
4 +3.3V_RUN_AUDIO
D D
L03ESDL5V0CC3-2_SOT23-3
L03ESDL5V0CC3-2_SOT23-3
5
3
6 GND +5V_RUN_AUDIO
GND +3.3V_RUN_AUDIO_IO
@ESD@
@ESD@
2 1 LA5
ACES_50278-0040N-001 LA12 BLM15PX600SN1D_2P +VDDA_AVDD1 1 2
place close to pin26
@EMI@ CA22
@EMI@ CA23
@EMI@ CA19
@EMI@ CA24
0.1U_0201_10V6K
10U_0603_10V6M
BLM15PX600SN1D_2P
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
10U_0603_10V6M
0.1U_0201_10V6K
Link SP02001CE00 DONE 1 RF Request
1
1
CA55
CA56
2 1 1
1
+5V_RUN_AUDIO
DA6
DA7
CA8
LA14 BLM15PX600SN1D_2P
CA9
2
2
2
0.1U_0201_10V6K
10U_0603_10V6M
1
2
2
1
1
CA10
CA61
place close to pin9
+1.8V_RUN
2
2 +3.3V_RUN_AUDIO_DVDD
100P_0402_50V8J
@RF@ CA78
+1.8V_RUN_AUDIO
12P_0402_50V8J
RF@ CA63
68P_0402_50V8J
RF@ CA64
place close to pin40 1 2 1 1
1
Close to UA1 @ RA3 0_0603_5%
10U_0603_10V6M
0.1U_0201_10V6K
place close to pin1 1
2
1
2 2
CA58
CA57
2
2
41
46
26
40
36
1
9
UA1
Close to UA1 pin6
PVDD1
PVDD2
AVDD1
AVDD2
DVDD-IO
DVDD
CPVDD
HDA_BIT_CLK_R DMIC_CLK0 11
I2C_SDA AUD_HP_OUT_L
@EMI@ RA17
12 31 +LINE1-VREFO-L RA57 1 2 4.7K_0402_5%
I2C_SCL LINE1-VREFO-L AUD_HP_OUT_R
82P_0402_50V8J
RF@ CA54
30 +LINE1-VREFO-R RA58 1 2 4.7K_0402_5% AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
1
LINE1-VREFO-R
33_0402_5%
10 29 +MIC2-VREFO
<12> HDA_SYNC_R HDA_BIT_CLK_R SYNC MIC2-VREFO
6 28 1 2 RF Request
<12> HDA_BIT_CLK_R HDA_SDOUT_R BIT-CLK VREF
Place RA9 close to codec 5 35 CA35 2.2U_0402_6.3V6M
2
<12> HDA_SDOUT_R HDA_SDIN0_R SDATA-OUT CBN +1.8V_RUN_AUDIO +1.8V_RUN
1 2 8 37 2 1
<12> HDA_SDIN0 RA9 33_0402_5% SDATA-IN CBP CA29 1U_0603_10V6K
Place CA29 close to Codec
2
100K_0402_5%1 2 RA52 4 20 @ RA53 1 2 0_0402_5%
+5V_ALW
EAPD/DC DET 5VSTB
10P_0402_50V8J
@EMI@ CA33
2 @ RA54 1 2 0_0402_5%
<27> DMIC0 DMIC_CLK0 1 GPIO0/DMIC-DATA12 +RTC_CELL
place close to UA1 pin3 2 DMIC_CLK_CODEC 3 34 1 2 1 2 RING2
<27> DMIC_CLK0 GPIO1/DMIC-CLK CPVEE
1
EMI@ RA14 22_0402_5% 47 CA49 1U_0603_10V6K RA5 2.2K_0402_5%
PDB
RF@ CA69
+3.3V_RUN_AUDIO 10K_0402_5% 2 1 RA18 PD# 48 +MIC2-VREFO 1 2 SLEEVE
SPDIFO/GPIO2/DMIC-DATA-34/DMIC-CLK-In/MIC-GPI
33P_0402_50V8J
2 1 SLEEVE/RING2 please keep 40 mils trace width RA6 2.2K_0402_5%
2
C C
12P_0402_50V8J
RF@ CA65
68P_0402_50V8J
RF@ CA66
100K_0402_5% 2 1 RA44 27 1 1 1
1U_0603_10V6K 2 1 CA31 10U_0603_10V6M 2 1 CA51 39 LDO1-CAP 17 RING2 AUD_PC_BEEP 2 1 SPKR_R 1 2
LDO2-CAP MIC2-L/RING2 BEEP_R SPKR <12>
10U_0603_10V6M 2 1 CA52 7 18 SLEEVE CA27 2 1 0.1U_0402_25V6 RA12 1 2 1K_0402_5%
LDO3-CAP MIC2-R/SLEEVE BEEP <32>
10U_0603_10V6M CA53 19 1 2 CA28 0.1U_0402_25V6 RA13 1K_0402_5%
MIC-CAP 24 10U_0603_10V6M CA25 2 2 2
INT_SPK_L+ 42 LINE2-L 23
INT_SPK_L- 43 SPK-L+ LINE2-R 22 LINE1_L 1 2 HP_OUT_L
INT_SPK_R- 44 SPK-L- LINE1-L 21 LINE1_R 10U_0603_10V6M 1 2 CA43 HP_OUT_R AUD_HP_OUT_L/ AUD_HP_OUT_Rplease keep 15 mils trace width
+3.3V_RUN_AUDIO INT_SPK_R+ 45 SPK-R- LINE1-R 16 AUD_PC_BEEP
10U_0603_10V6M CA44
SPK-R+ PCBEEP 32 HP_OUT_L 1 2 AUD_HP_OUT_L
AUD_SENSE_A 13 HP-OUT-L 33 HP_OUT_R 16.2_0402_1% 1 2 RA7 AUD_HP_OUT_R
+3.3V_RUN_AUDIO AUD_SENSE_B 14 HP/LINE1 JD1 HP-OUT-R 16.2_0402_1% RA8
MIC2/LINE2 JD2
1
15 25
SPDIFO/FRONT JD3/GPIO3 AVSS1 38
Place closely to Pin 13. 100K_0402_5% AVSS2 49
100K_0402_1% 200K_0402_1%
THERMAL PAD
1
RA61
RA59
AUD_SENSE_B ALC3246-CG_MQFN48_6X6 RF Request
+3.3V_RUN_AUDIO
2
AUD_SENSE_A
0.1U_0402_25V6
1
@ CA41
RA60
2
2
12P_0402_50V8J
RF@ CA67
68P_0402_50V8J
RF@ CA68
AUD_HP_NB_SENSE
Add for solve 1 1
pop noise and
detect issue
2 2
CLASS-D POWER DOWN CONTROL CIRCUIT
Add this Filter to avoid other HP-Out-Right Nokia-MIC
place at AGND and DGND plane components/chips be influenced
1 2
HP-Out-Lef t iPhone-MIC
B B
@ RA35 0_0402_5%
1 2 1 2
@ RA36 0_0402_5% @ RA48 0_0402_5%
680P_0402_50V7K
@ESD@ CA13
1 2 @ DA8 1 2 1
@ RA37
<32> NB_MUTE#
0_0402_5% Global Headset
RB751S40T1G_SOD523-2 PD#
1
@ RA38
2
1
PJP19
2 <12> HDA_RST#_R
1 2 2 Universal Jack
0_0402_5% @ RA50 0_0402_5%
HDA_Link is 3.3V,no need level shift circuit
PAD-OPEN1x1m JHP1 CONN@
1 2 7
@ RA39 0_0402_5% RE313@one control line if DVDD is 3.3V RING2 ESD@ LA10 1 2 BLM15PX330SN1D_2P RING2_R 4 GND
DE2@two control lines1 AUD_HP_OUT_L @EMI@RA55 1 2 0_0402_5% AUD_HP_OUT_L1 1 #4 G/M
#1 L/R Normal
Open
5
Only BR15U UMA use LA2,LA3,because 6L #5
AUD_HP_NB_SENSE 6
#6 AGND
AUD_HP_OUT_R @EMI@RA56 1 2 0_0402_5% AUD_HP_OUT_R1 2
SLEEVE ESD@ LA11 1 2 BLM15PX330SN1D_2P SLEEVE_R 3 #2 R/L
PJP17 #3 M/G
Power sequence +5V_RUN_AUDIO(501us) > +3.3V_RUN_AUDIO(1204 us) > +1.5V_RUN 1 2 SINGA_2SJ3095-085111F
680P_0402_50V7K
+5V_RUN +5V_RUN_AUDIO
ESD@
EMI@
EMI@
ESD@
ESD@ ESD@ ESD@
3
+3.3V_RUN_AUDIO PAD-OPEN1x2m DA1 DA2 DA3
2.5A Link DC23000DG10 DONE
330P_0402_50V8J
330P_0402_50V8J
680P_0402_50V7K
AZ5123-02S.R7G_SOT23-3
AZ5123-02S.R7G_SOT23-3
680P_0402_50V7K
@ESD@ CA12
2 1 1 1 1
AZ5125-02S.R7G_SOT23-3
Reserve for support D3 cold
1
CA1
CA2
CA3
CA4
PJP18
@ PJP15 1 2
+3.3V_RUN +3.3V_RUN_AUDIO 1 2 2 2 2
PAD-OPEN1x1m
+3.3V_RUN PAD-OPEN1x1m
500mA
@ UZ5
2
1
1 14 +3.3V_RUN_AUDIO_UZ5 1 2
2 VIN1 VOUT1 13 @ CZ125 0.1U_0201_10V6K
A VIN1 VOUT1 A
3 12 1 2
<12> AUD_PWR_EN ON1 CT1 1000P_0402_50V7K
@ CZ126
4 11
+5V_ALW VBIAS GND
5 10 1 2
ON2 CT2 @ CZ127 220P_0402_50V7K
6 9 @ PJP16
+5V_RUN VIN2 VOUT2 +5V_RUN_AUDIO_UZ5
7 8 1 2
VIN2 VOUT2 +5V_RUN_AUDIO
15
EM5209VF_SON14_2X3
GPAD PAD-OPEN1x1m
1 2
DELL CONFIDENTIAL/PROPRIETARY
@ CZ128 0.1U_0201_10V6K Security Classification Compal Secret Data
Title
Compal Electronics, Inc.
Issued Date 2016/01/01 Deciphered Date 2017/01/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Codec ALC3246
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 31 of 58
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
+RTC_CELL
@ RE32
1 2
0_0402_5%
+RTC_CELL_VBAT eSPI
LPC
GPIO223
NA
SHD_IO0
GPIO224 GPIO227
NA *PRIM_PW RGD
SHD_IO1 SHD_IO2
GPIO016
NA
SHD_IO3
GPIO056
NA
SHD_CLK
GPIO055
PCH_RSMRST#
SHD_CS#
For SB
UPD1_SMBDAT
0.1U_0201_10V6K
1 * For Version B IC 1 2
CE11
RE302 2.2K_0402_5%
GPIO204 GPIO011 GPIO100 GPIO021 GPIO067 UPD1_SMBCLK 1 2
+3.3V_ALW_UE1
eSPI NA NA NA SIO_RCIN# NA RE303 2.2K_0402_5%
2 UPD1_SMBINT#
0.1U_0201_10V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
PJP22 LPC RSMRST# SIO_EXT_SMI# SIO_EXT_SCI# LPCPD# CLKRUN# 1 2
+3.3V_ALW 1 2 1 1 RE91 100K_0402_5%
1
UPD2_SMBINT#
CE13
CE14
CE23
1 2
10U_0603_6.3V6M
PAD-OPEN1x1m RE92 100K_0402_5%
1
SIO_SLP_SUS#_R 1 2
For EVT/DVT1.0 Only,SA00009GL10, S IC MEC5105K-TMP2-TN WFBGA 169P EC
2
2 2
CE16
NDS3@RE561 100K_0402_5%
After DVT1.1,SA00009GL00, S IC MEC5105K-D1-TN WFBGA 169P EC
Vinafix.com
PBAT_CHARGER_SMBDAT 1 2
2
UE1 RE37 2.2K_0402_5%
F2 TYPEC_ID PBAT_CHARGER_SMBCLK 1 2
GPIO033/RC_ID0 SYSTEM_ID TYPEC_ID <33>
A2 J10 SYSTEM_ID <33> RE43 2.2K_0402_5%
+3.3V_ALW_UE1 VBAT GPIO034/RC_ID1/SPI0_CLK J13 BOARD_ID
D GPIO036/RC_ID2/SPI0_MISO UPD2_SMBDAT BOARD_ID <33> D
B7 E7 RPE12
2 1 VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# D7 UPD2_SMBCLK GPU_SMCLK 1 8
+3.3V_ALW_UE1 GPIO004/SMB00_CLK/SPI0_MOSI GPU_SMDAT
0.1U_0201_10V6K
0.1U_0201_10V6K
100_0402_1% RE314 K2 2 7
VREF_ADC UPD2_SMBCLK
22U_0603_6.3V6M
0.1U_0201_10V6K
1 1 1 1 G3 3 6
+3.3V_EC_PLL GPIO057/VCC_PWRGD GPS_DISABLE# RUNPWROK <14> UPD2_SMBDAT
CE19
CE20
@ CE17
F1 H5 4 5
VTR_PLL GPIO060/KBRST/48MHZ_OUT GPS_DISABLE# <30>
CE18
G11
GPIO104/UART0_TX HOST_DEBUG_TX <30,33>
H1 G12 2.2K_0804_8P4R_5%
2 2 2 2 VTR_REG GPIO105/UART0_RX ME_FWP <12>
B13
GPIO127/A20M/UART0_CTS# UPD1_SMBINT# ME_SUS_PWR_ACK <11>
G8 F10
M9 VTR1 GPIO225/UART0_RTS# UPD1_SMBINT# <24> 100K_0804_8P4R_5%
+VSS_PLL +3.3V_ALW_UE1 VTR2 PCIE_WAKE#_R NGFF_CONFIG_0
close to pin G8/M9 +1.8V_3.3V_ALW_VTR3 N5 N13 4 5
VTR3 GPIO025/TIN0/nEM_INT/UART_CLK N12 PCIE_WAKE#_R <33> NGFF_CONFIG_1 3 6
+3.3V_ALW_UE1 PCH_DPWROK_EC GPIO026/TIN1 SIO_SLP_S4# <11,17,43,46> NGFF_CONFIG_2
1 2 F8 M11 2 7
<11> PCH_DPWROK RUN_ON_EC GPIO020 GPIO027/TIN2 SIO_SLP_A# <11> NGFF_CONFIG_3
RF Request @DS3@RE536 0_0402_5% E8 H9 1 8
<33> RUN_ON_EC GPIO045 GPIO030/TIN3 SIO_SLP_LAN# <11,40>
0.1U_0201_10V6K
1 M12
+3.3V_ALW <9> SIO_EXT_WAKE# BT_RADIO_DIS# GPIO120 VGA_IDENTIFY RPE9
C2 L9
<30> BT_RADIO_DIS# GPIO166 GPIO017/GPTP-IN5
CE15
F9 M10 RPE11
<41,50> PBAT_PRES# SIO_SLP_SUS#_R GPIO175 GPIO151/ICT4 NGFF_CONFIG_1 <30> USB_POWERSHARE_VBUS_EN
1 2 N4 N9 1 8
2 <11> SIO_SLP_SUS# PCH_ALW_ON GPIO230 GPIO152/GPTP-OUT3 NGFF_CONFIG_0 <30> USB_POWERSHARE_EN#
DS3@ RE349 43K_0402_1% M8 2 7
<40> PCH_ALW_ON GPIO231 USB_PWR_EN1#
K8 C11 3 6
<11> AC_PRESENT GPIO233 GPIO156/LED0 BREATH_LED# <39> USB_PWR_EN2#
D10 4 5
GPIO157/LED1 BAT1_LED# <39>
<8> SML1_SMBDATA
E11 D11
GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 BAT2_LED# <39>
Close to pin H1 D8 E1 100K_0804_8P4R_5%
<8> SML1_SMBCLK WWAN_WAKE# GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 LCD_VCC_TEST_EN <27>
12P_0402_50V8J
RF@ CE59
68P_0402_50V8J
RF@ CE60
1 1 M13
<30> WWAN_WAKE# K12 GPIO110/PS2_CLK2 E5 AC_DIS 1 2
<11> SUSACK# GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 USH_EXPANDER_SMBDAT <34>
<30> WLAN_WIGIG60GHZ_DIS# L13 B3 @ RE83 100K_0402_5%
GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 USH_EXPANDER_SMBCLK <34> VCCDSW_EN GPS_DISABLE#
K11 M7 1 2
2 2 <11,14> SIO_PWRBTN# VCCST_PWRGD_EC K10 GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 DGPU_PWROK VCCDSW_EN <11>
0.1U_0402_25V6
1 2 M4 RE12 100K_0402_5%
<11,14,33> VCCST_PWRGD GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 PBAT_CHARGER_SMBDAT PAD~D @ T147
RE308 @ 0_0402_5% N11 M3
<33> LID_CL_SIO# GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PBAT_CHARGER_SMBCLK PBAT_CHARGER_SMBDAT <41,50>
@ CE66
1 2 E10 N2
<40> SLP_WLAN#_GATE <38> CLK_TP_SIO_I2C_DAT GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 PBAT_CHARGER_SMBCLK <41,50>
1
@ RE552 0_0402_5% C12 N10 WLAN_WIGIG60GHZ_DIS# 1 2
<38> DAT_TP_SIO_I2C_CLK GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA NGFF_CONFIG_2 <30>
A12 RE8 100K_0402_5%
change to PS2 JTAG_TDI E9 GPIO140/SMB06_CLK/ICT5 B6 GPU_SMDAT LED_MASK# <28,39> WWAN_WAKE# 1 2
2
<33> JTAG_TDI JTAG_TDO F6 GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD# F7 GPU_SMCLK RE38 10K_0402_5%
<33> JTAG_TDO JTAG_CLK C8 GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR# B4 UPD1_SMBDAT LED_MASK# 1 2
<33> JTAG_CLK JTAG_TMS GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR# UPD1_SMBCLK UPD1_SMBDAT <24>
C5 C3 RE21 10K_0402_5%
<33> JTAG_TMS JTAG_RST# GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI# UPD1_SMBCLK <24>
G13 THERMTRIP1# 1 2
PJP20 JTAG_RST# J4 I_BATT_R RE64 1 2 300_0402_5% RE301 10K_0402_5%
GPIO200/ADC00 I_SYS_R I_BATT <50>
1 2 E3 J5 RE312 1 2 300_0402_5%
+1.8V_PRIM +1.8V_3.3V_ALW_VTR3 <33> TACH_FAN1
GPIO051 D1 GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 J6 DCIN3_EN I_SYS <47,50>
SB12 only for wireless charger
1 T141 @ PAD~D LCD_TST GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 PAD~D @ T262 LOM_CABLE_DETECT#
PAD-OPEN1x1m M2 G2 @ RE318 1 2 0_0402_5% 1 2
<27> LCD_TST GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 USH_PWR_STATE# TOUCHPAD_INTR# <12,38>
CE22 L10 H2 @ RE505 100K_0402_5%
C <33> PWM_FAN1 GPIO053/PWM0/GPWM0 GPIO204/ADC04 USB_POWERSHARE_VBUS_EN USH_PWR_STATE# <34> PCIE_WAKE#_R C
0.1U_0201_10V6K GPIO054 L11 J2 1 2
2 T142 @ PAD~D PCH_RSMRST# GPIO054/PWM1/GPWM1 GPIO205/ADC05 USB_POWERSHARE_EN# USB_POWERSHARE_VBUS_EN <36>
M5 J3 RE35 10K_0402_5%
<38> PCH_RSMRST# GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06 USB_PWR_EN1# USB_POWERSHARE_EN# <36> GPU_PWR_LEVEL
1 CE21 J8 K3 1 2
<41> PS_ID GPIO056/PWM3/SHD_CLK GPIO207/ADC07 USB_PWR_EN1# <37>
@ PJP21 0.1U_0201_10V6K <27> BIA_PWM_EC N1 D3 RE5 10K_0402_5%
TBT_RESET_N_EC_R L8 GPIO001/PWM4 GPIO210/ADC08 AUX_EN_WOWL <40>
+3.3V_ALW
1 2 <22,24> TBT_RESET_N_EC
1 2 D2 LOM_CABLE_DETECT# <28>
Close to pin N5 @ RE506 0_0402_5% N6 GPIO002/PWM5 GPIO211/ADC09 E2 BC_DAT_ECE1117 1 2
PAD-OPEN1x1m 2 <41,50,51> HW_ACAVIN_NB J9 GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 G5 USB_PWR_EN2# BC_INT#_ECE1117 <38> RE365 100K_0402_5%
<27> PANEL_BKEN_EC H11 GPIO015/PWM7 GPIO213/ADC11 F5 UPD2_SMBINT# WWAN_RADIO_DIS# 1 2
<31> BEEP D9 GPIO035/PWM8/CTOUT1 GPIO214/ADC12 K4 RE10 100K_0402_5%
<11,40> SIO_SLP_WLAN# AC_DIS GPIO133/PWM9 GPIO215/ADC13 DCIN1_EN <51> BT_RADIO_DIS#
<50> AC_DIS
H12 L1 1 2
GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 PCH_PCIE_WAKE# <11,33>
G10 L3 RE11 100K_0402_5%
<34> BCM5882_ALERT# GPIO135/UART1_CTS# GPIO217/ADC15 LAN_WAKE# <11,28>
MSCLK H10
<33> MSCLK GPIO170/TFDP_CLK/UART1_TX CV2_ON_R
MSDATA G9 H8 RE539 1 2 100_0402_5%
<33> MSDATA GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ 3.3V_TS_EN CV2_ON <34> +3.3V_RUN
J7
RPE10 A4 GPIO223/SHD_IO0 L6 MASK_SATA_LED# 3.3V_TS_EN <27>
8 1 CV2_ON_R <31> NB_MUTE# EN_INVPWR B2 GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 L7 1.8V_PRIM_PWRGD MASK_SATA_LED# <39>
1.8V_PRIM_PWRGD <46>
7 2 IMVP_VR_ON_EC RE362 1 2 100K_0402_5% <27> EN_INVPWR RESET_IN# C1 GPIO023/GPTP-IN1 GPIO227/SHD_IO2 M6 VBUS1_ECOK
PCH_ALW_ON +3.3V_ALW IMVP_VR_ON_EC GPIO024/nRESETI GPIO016/GPTP-IN7/SHD_IO3/ICT3 VBUS1_ECOK <51> 3.3V_TS_EN
6 3 N7 1 2
5 4 RUN_ON_EC <33> IMVP_VR_ON_EC K9 GPIO031/GPTP-OUT1 D6 @ RE547 100K_0402_5%
<11,22,33> SIO_SLP_S3# GPIO032/GPTP-OUT0 BGPO0 EC_FPM_EN <34>
N8 C7
<11> SIO_SLP_S5# GPI0040/GPTP-OUT2 GPIO164/VCI_OVRD_IN ACAV_IN <50>
100K_0804_8P4R_5% A5 RE59 close to UE2 at least 250mils
VBUS3_ECOK VCI_OUT ALWON <42> +PECI_VREF I_BATT_R
SB12 only for wireless charger F13 D5 1 2 CE3 1 2 2200P_0402_50V7K
T264 @ PAD~D GPIO121/PVT_IO0 GPIO163/VCI_IN0# VCI_IN1# POWER_SW_IN# <33> +1.0V_VCCST
E13 B5 @ RE59 0_0402_5%
<41,51> AC_DISC# C13 GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1# D4 VCI_IN2# I_SYS_R CE4 1 2 2200P_0402_50V7K
<34> USH_DET# GPU_PWR_LEVEL GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2# POA_WAKE#
E12 E4
GPIO126/PVT_IO3 GPIO000/VCI_IN3# POA_WAKE# <34>
+3.3V_ALW RTCRST_ON
0.1U_0201_10V6K
F11
WWAN_RADIO_DIS# F12 GPIO122/BCM0_DAT/PVT_IO1 C6
<30> WWAN_RADIO_DIS# GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0 3.3V_WWAN_EN <40>
1
PCH_RSMRST#
CE25
D12 1 2
<38> BC_DAT_ECE1117 GPIO046/BCM1_DAT 32KHZ_OUT
D13 F3 @ CE54 1 2 10P_0402_50V8J RE342 10K_0402_5%
USH_DET# <38> BC_CLK_ECE1117 GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT SYS_PWROK
1 2 1 2
2
@ RE526 10K_0402_5% F4 RE56 10K_0402_5%
BCM5882_ALERT# 3.3V_ALW2 <30> NGFF_CONFIG_3 GPIO041/SYS_SHDN# +PECI_VREF I_SYS_R
1 2 @ RE57 2 1 1K_0402_5% B1 J11 1 2
+3.3V_ALW2 SYSPWR_PRES GPIO044/VREF_VTT PECI_EC_R
@
RE532 4.7K_0402_5% T143 @ PAD~D GPIO011 K7 K13 RE60 1 2 43_0402_5% RE313 10K_0402_5%
PECI_EC <12>
1
VBUS2_ECOK N3 GPIO011/nSMI GPIO042/PECI_DAT/SB-TSI_DAT J12 M3042_PCIE#_SATA LCD_TST 1 2
<41,51> VBUS2_ECOK GPIO021/LPCPD# GPIO043/SB-TSI_CLK REM_DIODE1_N M3042_PCIE#_SATA <10>
REM_DIODE1_N
100K_0402_5%
K6 A8 CE24 1 2 2200P_0402_50V7K RE20 100K_0402_5%
<8,33> ESPI_RESET# GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A REM_DIODE1_P REM_DIODE1_P REM_DIODE1_N <33> EN_INVPWR
RE58
H7 A7 1 2
<8> ESPI_ALERT# GPIO063/SER_IRQ/ESPI_ALERT# DP1_DN1A REM_DIODE2_N REM_DIODE2_N REM_DIODE1_P <33>
K1 A10 CE26 1 2 2200P_0402_50V7K RE55 100K_0402_5%
<33> PCH_PLTRST#_5105 GPIO064/LRESET# DN2_DP2A REM_DIODE2_P REM_DIODE2_P REM_DIODE2_N <33> TBT_RESET_N_EC_R
G7 A9 1 2
REM_DIODE2_P <33>
2
<8,33> ESPI_CLK_5105 H6 GPIO065/PCI_CLK/ESPI_CLK DP2_DN2A B9 RE95 100K_0402_5%
<8,33> ESPI_CS# K5 GPIO066/LFRAME#/ESPI_CS# DN3_DP3A B8
<8,33> ESPI_IO0 GPIO070/LAD0/ESPI_IO0 DP3_DN3A REM_DIODE4_N REM_DIODE4_N
B L4 A11 CE27 1 2 2200P_0402_50V7K B
<8,33> ESPI_IO1 GPIO071/LAD1/ESPI_IO1 DN4_DP4A REM_DIODE4_P REM_DIODE4_P REM_DIODE4_N <33>
G6 B10
<8,33> ESPI_IO2 GPIO072/LAD2/ESPI_IO2 DP4_DN4A +VR_CAP REM_DIODE4_P <33>
L5 C10
<8,33> ESPI_IO3 ENABLE_DS# GPIO073/LAD3/ESPI_IO3 VIN VSET_5105 +RTC_CELL
L2 C9 VSET_5105 <33>
GPIO100 M1 GPIO067/CLKRUN# VSET B11
T144 @ PAD~D SYS_PWROK @ RE548 1 RESET_OUT GPIO100/nEC_SCI VCP I_ADP <50> VCI_IN1#
2 0_0402_5% G4 H3 THERMTRIP2# 1 2
VSS_ANALOG
<11,14> SYS_PWROK GPIO106/PWROK GPIO103/THERMTRIP2# THERMTRIP2# <33>
L12 B12 THERMTRIP1# RE507 100K_0402_5%
<41> DCIN2_EN GPIO107/nSMI THERMTRIP1# PROCHOT#_R1 VCI_IN2#
H13 1 2 1 2
VSS_ADC
VSS_PLL
MEC_XTAL1 GPIO160/PWM11/PROCHOT# PROCHOT# <12,47,50>
VR_CAP
A1 RE288 100_0402_5% RE508 100K_0402_5%
MEC_XTAL2_R A3 XTAL1 POA_WAKE# 1 2
VSS1
VSS2
VSS3
XTAL2 RE324 100K_0402_5%
+1.8V_3.3V_ALW_VTR3
MEC5105_WFBGA169_11X11
A6
A13
E6
H4
1+VR_CAP J1
C4
G1
1U_0402_6.3V6K
1
@ +3.3V_ALW
RE549
100K_0402_5%
+VSS_PLL
VGA_IDENTIFY 1 2
RE84 100K_0402_5%
2
ENABLE_DS# Deep Sleep support +RTC_CELL_PCH +RTC_CELL VGA_IDENTIFY 1 2
QE15 @ RE85 100K_0402_5%
+RTC_CELL_PCH +RTC_CELL
CE31
LP2301ALT1G_SOT23-3
non Deep Sleep 1
2
1
1 3
S
RE550 Deep Sleep 0 1 2
1U_0402_6.3V6K
10K_0402_5%
100K_0402_5% @RE551 0_0402_5%
1
VGA_IDENTIFY
G
2
1
RE546
2
+3.3V_RUN
CE63
Discrete 0
2 DE2 UMA 1
2
2
+3.3V_ALW 2 1
10K_0402_5% DMN65D8LDW-7_SOT363-6
+3.3V_ALW
100K_0402_5%
RE67
RB751S40T1G_SOD523-2
2
@RE94
RE63
1
D 1 2
For EMI request RE543
100K_0402_5%
MEC_XTAL2_R PCH_RTCRST# <11>
2
RUNPWROK QE17 2RTCRST_ON_R 1 2 1 2 RTCRST_ON 75_0402_5%
ESPI_CLK_5105
1
D
L2N7002WT1G_SC-70-3 G RE565 0_0402_5%
RE68
RTCRST_ON
0.1U_0402_25V6
S 1M_0402_5% 2 QE12 @
1
22P_0402_50V8J
100K_0402_5%
G L2N7002WT1G_SC-70-3
33_0402_5%
1
1
@ CE64
@EMI@
S
1
3
JTAG_RST#
1
QE2B
RE541
@RE290 @RE93
32 KHz Clock
RE350
CE65
A 0_0402_5% A
RUN_ON# 5 100K_0201_5%
2
2
<40> RUN_ON#
1
2
2
1U_0402_6.3V6K
DMN65D8LDW-7_SOT363-6
1
YE1
4
33P_0402_50V8J
1
@SHORT PADS~D
JTAG1 CONN@
100_0402_1%
MEC_XTAL1 MEC_XTAL2
1
6
@ RE65
1 2 8/28 schematic review
@EMI@
1
CE30
QE2A
10P_0402_50V8J
10P_0402_50V8J
CE57
2
32.768KHZ_9PF_X1A000141000200 2
2
<17,33,40,45> RUN_ON
1
DELL CONFIDENTIAL/PROPRIETARY
CE28
CE29
1
2
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT EC MEC5105
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 32 of 58
5 4 3 2 1
5 4 3 2 1
+1.8V_3.3V_ALW_VTR3
+3.3V_ALW
For SB
2
UE6
RE340
1 5 10K_0402_5%
NC VCC
2
<11> PCH_PLTRST#_EC
1
A 4
3 Y PCH_PLTRST#_5105 <32>
GND
74AUP1G07GW_TSSOP5 +RTC_CELL
PCIE_WAKE# <22,30,35>
1
100K_0402_5%
RE31
@ CE10
1 2 1 2 1 2
Vinafix.com
<32> PCIE_WAKE#_R PCH_PCIE_WAKE# <11,32>
@ RE275 0_0402_5% 0_0402_5% @ RE274
1U_0402_6.3V6K
2
1 2 Stuff RE275 and no stuff RE274 keep E5 design
<32> POWER_SW_IN# POWER_SW#_MB <11,39>
RE33 1K_0402_5% Stuff RE274 and no stuff RE275 to save two GPIOs on EC(PCH_PCIE_WAKE# should be output with OD)
ESPI LPC
2.2U_0402_6.3V6M
1
PAGE
D D
CE12
2 1
2
0_0402_5% @ RE304
CONN@ JESPI
1
+3.3V_RUN
8 RC25_10K RC8_15ohm +3.3V_ALW
+3.3V_ALW
@ CE53
1 2
1 2
RC13/RC27_8.2K
+3.3V_ALW
100K_0402_5%
UE4
2 3
1
RE25
ESPI_IO0 <8,32> 0.1U_0402_25V6K
3 4
5
ESPI_IO1 <8,32> 1 5
4 5 IMVP_VR_ON_EC 1 NC VCC
ESPI_IO2 <8,32>
P
5 6 <32> IMVP_VR_ON_EC B IMVP_VR_ON
4 2
6 7 ESPI_IO3 <8,32> SIO_SLP_S3# 2 O A 4
RE26 <11,22,32,33> SIO_SLP_S3#
ESPI_CS# <8,32>
2
7 8 20_0402_5% PCH_PLTRST#_EC LID_CL_SIO# A Y VCCST_PWRGD <11,14,32>
G
LPC@ RE375 1 2 1 UE3 3
8 9 20_0402_5% ESPI_RESET# <32> LID_CL_SIO# LID_CL# <39> GND
.047U_0402_16V7K
@ RE560 1 TC7SH08FU_SSOP5~D
ESPI_RESET# <8,32>
3
9 10
10 ESPI_CLK_5105 <8,32>
18 RC212_0ohm RC211_0ohm 10_0402_5% 74AUP1G07GW_TSSOP5
CE8
11
2
GND1 IMVP_VR_ON <47>
GND2
12
0603 0603 0_0402_5%
1 2
@ RE280
ACES_50506-01041-P01
RUN_ON_EC 2 1
<32> RUN_ON_EC RUN_ON <17,32,40,45>
0_0402_5% @ RE292
RE337,RE338 RF Request +3.3V_ALW
@ CE52
RE339,RE340, +3.3V_ALW 1 2
31 0.1U_0402_25V6K
5
68P_0402_50V8J
RE341
1
1
P
B
RF@ CE61
4
2 O
LPC 80Port Debug LPC ESPI A
G
2 UE5
0_ohm TC7SH08FU_SSOP5~D
3
1 +3.3V_RUN +3.3V_RUN
2 +3.3V_RUN +3.3V_RUN
3 LPC_LAD0 ESPI_IO0 SB13@
RE2 / RE3
+3.3V_ALW +3.3V_ALW +3.3V_ALW
RE300
2
4 LPC_LAD1 ESPI_IO1
32 SB12@
2
0_ohm
C RE79 RE300 C
RE343 2K_0402_5% 130K_0402_5%
5 LPC_LAD2 ESPI_IO2 130K_0402_5%
1
BOARD_ID SYSTEM_ID
<32> BOARD_ID <32> SYSTEM_ID 62K_0402_5%
1
6 LPC_LAD3 ESPI_IO3 <32> TYPEC_ID
1
1
CE40 CE47
7 LPC_FRAME# ESPI_CS# CE62 4700P_0402_25V7K 4700P_0402_25V7K
2
4700P_0402_25V7K
2
8 PCH_PLTRST# NA
RE79 CE40 REV RE300 CE47 PANEL SIZE
RE343 CE62 REV
9 GND GND 240K 4700p X00 240K 4700p 11"
240K 4700p Single Port ACE w/o AR
10 LPC_CLOCK ESPI_CLK Single Port ACE w/AR 130K 4700p X01 * 130K 4700p 12"
* 130K 4700p
Dual Port ACE w/o AR 62K 4700p X02 62K 4700p 13"
62K 4700p
Dual Port ACE w/AR 33K 4700p X03 33K 4700p 14"
33K 4700p
Dual Port ACE (w/AR +w/o AR) 8.2K 4700p X04 8.2K 4700p 15"
8.2K 4700p
4.3K 4700p A00 4.3K 4700p 17"
4.3K 4700p
2K 4700p * 2K 4700p A01 2K 4700p 15P
1K 4700p 1K 4700p
1K 4700p
PD_ACE_DET# rise t i mei s meas ur ed fr o m5 %~68 %. BOARD_ID rise t i mei s meas ur ed fr o m5 %~68 %. SYSTEM_ID rise t i mei s meas ur ed fr o m5 %~68 %.
VSET_5105
VSET_5105 <32>
0.1U_0402_25V6
1
1.58K_0402_1%
1
CE38
RE77
2
+3.3V_ALW
2
1
8
7
6
5
10_0402_1%
10K_8P4R_5%
RE71
RPE7
Rest=1.58K , Tp=96 degree
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
Rest=1.33K , Tp=93 degree
@ RE75
CONN@
1
2
3
4
RE72
RE73
RE74
B JDEG1 B
1 +EC_DEBUG_VCC
1 2 JTAG_TDI Link 50271-0040N-001 DONE
JTAG_TDI <32>
2
2 3 JTAG_TMS JFAN1
3 4 JTAG_CLK JTAG_TMS <32> 1
4 5 JTAG_TDO JTAG_CLK <32> 1 2 PWM_FAN1
RE86
11 5 6 JTAG_TDO <32> 2 3 TACH_FAN1 PWM_FAN1 <32>
MSCLK 10K_0402_5%
12 G1 6 7 1 2 +3.3V_RUN 3 4 TACH_FAN1 <32>
MSDATA +5V_RUN
G2 7 8 HOST_DEBUG_TX 4
8 DEBUG_TX
10U_0603_6.3V6M
9 5
9 GND1
1
10 6 @
10 PWM_FAN1 GND2
1
1 2 1 2 DE1
<9> SBIOS_TX
CE32
ACES 50506-01041-P01 RE306 RE48 10K_0402_5% ACES_50271-0040N-001 BZV55-B5V6_SOD80C2
0_0402_5% 1 2 TACH_FAN1 CONN@
2
@ RE51 10K_0402_5%
HOST_DEBUG_TX <30,32>
2
MSDATA <32>
1 2 MSCLK <32>
@ RE30
0_0402_5%
Thermal diode mapping
5105 Channel Locat i on
Place under CPU
Place CE35 close to the QE3 as possible
DP1/DN1 CPU (QE3)
REM_DIODE1_P <32>
100P_0402_50V8J
DP2/DN2 WiGig (QE5)
1
C
@ CE35
2
DN2a/DP2a DDR (QE7) B
1
E QE3
3
LMBT3904WT1G SC70-3
DP3/DN3 NA REM_DIODE1_N <32>
DP2/DN2 for WiGig on QE5, place QE5 close
DP4/DN4 CPU VR (QE6) to WiGig and CE37 close to QE5
DP4/DN4 for Skin on
CHECK RE69 QE6, place QE6 close to DN2a/DP2a for DDR on QE7, place QE7 close
Vcore VR choke. to DDR and CE46 close to QE7
0.1U_0402_25V6
1 2
+1.0VS_VCCIO +3.3V_ALW THERMTRIP2# <32>
REM_DIODE4_P <32> REM_DIODE2_P <32>
LMBT3904WT1G SC70-3
SIO_SLP_S3# <11,22,32,33> 8.2K_0402_5%
1
LMBT3904WT1G SC70-3
CE36
100P_0402_50V8J
@ QE11
2
1
100P_0402_50V8J
100P_0402_50V8J
@ CE37
QE7
E C
G
1
@ CE46
C C B
2 2
2
QE4
@CE39
A 1 3 1 2 2 2 B A
2
RE70 2.2K_0402_5% B B C E QE5
D
3
+1.0V_VCCST E E QE6 LMBT3904WT1G SC70-3
3
L2N7002WT1G_SC-70-3 LMBT3904WT1G SC70-3
@ RE90 1 2 0_0402_5% REM_DIODE2_N <32>
<12,20> H_THERMTRIP# REM_DIODE4_N <32>
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MEC5105 support
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Re v
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Friday, December 29, 2017 Sheet 33 of 58
5 4 3 2 1
5 4 3 2 1
Close to UZ12
For NUVOTON TPM RF Request RF Request RF Request
+3.3V_ALW +3.3V_M_TPM +3.3V_RUN
Vinafix.com +3.3V_M_TPM
@ RZ367 1 2 0_0402_5%
12P_0402_50V8J
RF@ CZ57
68P_0402_50V8J
RF@ CZ58
12P_0402_50V8J
RF@ CZ59
68P_0402_50V8J
RF@ CZ60
12P_0402_50V8J
RF@ CZ76
68P_0402_50V8J
RF@ CZ77
+UZ12_TPM
place CZ50, CZ75 as close as UZ12.8 1 1 1 1 1 1
D @ RZ89 1 2 0_0402_5% D
+3.3V_RUN
10U_0402_6.3V6M
0.1U_0201_10V6K
2 2 2 2 2 2
1 1
CZ75
CZ50
+3.3V_ALW 2 2
@ RZ369 1 2 0_0402_5%
+3.3V_ALW_PCH +3.3V_ALW
@ RZ368 1 2 0_0402_5%
+3.3V_M_TPM
2
PJP391
1 2 TPM_PIRQ#
PAD-OPEN1x1m
RZ69 10K_0402_5% +3.3V_ALW
1 2 USH_EXPANDER_SMBCLK
1
RZ8 4.7K_0402_5%
+3.3V_ALW_UZ12 1 2 USH_EXPANDER_SMBDAT
RZ9 4.7K_0402_5%
0.1U_0201_10V6K
10U_0603_10V6M
1 2 USH_PWR_STATE#
1 1 place CZ51,CZ52 as close as UZ12.1
+3.3V_RUN RZ10 100K_0402_5%
CZ51
CZ52
1
2 2
@ RZ362
10K_0402_5%
USH CONN
UZ12
1
2
C 1 2 TPM_GPIO0 29 VSB 1 2 RF@ CZ78 1 2 100P_0402_50V8J C
<11,17,45> SIO_SLP_S0# GPIO0/SDA/XOR_OUT +UZ12_TPM +3.3V_M_TPM
@ RZ112 0_0402_5% 30 8 @ RZ366 0_0402_5% JUSH1 CONN@
1 2 TPM_LPM# 3 GPIO1/SCL VDD 14 +UZ12_VHIO 1 2 @ RZ85 1 2 0_0402_5% +PWR_SRC_R 1
GPIO2/GPX VHIO +3.3V_RUN +PWR_SRC 1
@ RZ363 0_0402_5% 6 22 @ RZ365 0_0402_5% 2
GPIO3/BADD VHIO 2
0.1U_0201_10V6K
0.1U_0201_10V6K
10U_0603_10V6M
3
2 33_0402_5% PCH_SPI_D1_2_R <32> CV2_ON POA_WAKE#_R 3
RZ58 1 24 2 1 1 1 RZ364 1 2 100_0402_5% 4
<8> PCH_SPI_D1_R1 RZ59 1 2 33_0402_5% PCH_SPI_D0_2_R 21 LAD0/MISO NC 7 <32> POA_WAKE# 5 4
<8> PCH_SPI_D0_R1 LAD1/MOSI NC <32> EC_FPM_EN 5
CZ54
CZ53
CZ55
18 10 6
<9> TPM_PIRQ# 15 LAD2/SPI_IRQ# NC 11 7 6
LAD3 NC 25 2 2 2 8 7
2 33_0402_5% PCH_SPI_CLK_2_R 19 NC <10> USB20_N10 8
EMI@ RZ60 1 26 9
<8> PCH_SPI_CLK_R1 @ RZ61 1 2 0_0402_5% PCH_SPI_CS#2_R 20 LCKL/SCLK NC 31 <10> USB20_P10 10 9
<8> PCH_SPI_CS#2 17 LFRAME#/SCS# NC 11 10
<11> PLTRST_TPM# 27 LRESET#/SPI_RST#/SRESET# 9 <32> USH_EXPANDER_SMBCLK 12 11
TPM_GPIO4 13 SERIRQ GND 16 <32> USH_EXPANDER_SMBDAT 13 12
T283@ PAD~D CLKRUN#/GPIO4/SINT# GND <32> BCM5882_ALERT# 13
28 23 CZ53,CZ55 as close as UZ12.14 14
LPCPD# GND 14
1
10K_0402_5%
@ RZ62
32 CZ54 as close as UZ12.22 15
4 GND 33 16 15
PP PGND +3.3V_ALW 16
5 12 17
TEST Reserved 18 17
+5V_ALW 18
NPCT750JAAYX_QFN32_5X5 19
+3.3V_RUN
2
20 19
+5V_RUN USH_RST#_R 20
@ RZ114 1 2 0_0402_5% 21
<11,22,29,30,35> PCH_PLTRST#_AND DZ8 22 21
2 1 <32> USH_PWR_STATE#
CONTACTLESS_DET#_R 23 22
<12> CONTACTLESS_DET# 24 23
RB751S40T1G_SOD523-2 25 24
@ RZ87 1 2 0_0402_5% USH_DET#_R 26 25
<32> USH_DET# 26
@ DZ7 27
2 1 28 GND1
PCH_SPI_CLK_2_R Pop Depop Comment GND2
B RB751S40T1G_SOD523-2 B
VDD - V_RUN Power CVILU_CF5026FD0RK-05-NH
33_0402_5%
NPCT65x RZ89, RZ366, RZ62, RZ363 RZ365, RZ367, RZ112 VHIO - V_SPI Power
2
@EMI@
RZ63
Option1 (recommended) Update to LTCX007Q600 (DVT1.0)
NPCT75x RZ89, RZ365, RZ112 RZ367, RZ366, RZ62, RZ363 VDD and VHIO - V_RUN power
Option2 (for Z1 sample [early sample])
1
0.1U_0402_25V6
NPCT75x RZ367, RZ366 RZ89, RZ365, RZ62 VDD and VHIO - V_SPI power PCH_PLTRST#_AND Close to JUSH1
1
+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW
@EMI@
CZ56
.047U_0402_16V7K
ESD@ CZ61
2
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1
@
2
CZ64
CZ66
CZ67
CZ68
For ESD solution 2 2 2 2
RF Request
+5V_ALW +5V_RUN +3.3V_RUN +3.3V_ALW
RF Request
68P_0402_50V8J
RF@ CZ69
68P_0402_50V8J
RF@ CZ71
68P_0402_50V8J
RF@ CZ72
68P_0402_50V8J
RF@ CZ73
USH_EXPANDER_SMBCLK 1 2 1 1 1 1
@RF@CZ62 68P_0402_50V8J
USH_EXPANDER_SMBDAT 1 2
A @RF@CZ63 68P_0402_50V8J 2 2 2 2 A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
USH & TPM
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 34 of 58
5 4 3 2 1
5 4 3 2 1
For Brekenridge 12/14/15 UMA/Steamboat
Vinafix.com
RF Request
+3.3V_HDD_M2 +3.3V_HDD_M2
D D
0.1U_0201_10V6K
0.1U_0201_10V6K
68P_0402_50V8J
@RF@CN60
22U_0603_6.3V6M
22U_0603_6.3V6M
@
1 1
1
CN61
CN62
1
CN63
CN64
2
2
2 2
2
2280 SSD
NGFF slot C Key M
Place near HDD CONN
+3.3V_HDD_M2 2.8A
JNGFF3 CONN@
PJP31
1 2 1 2
GND 3.3VAUX +3.3V_RUN
3 4
5 GND 3.3VAUX 6 PAD-OPEN1x3m
<10> PCIE_PRX_DTX_N9 7 PERn3 N/C 8
<10> PCIE_PRX_DTX_P9 9 PERp3 N/C 10 NVME_LED# 1 2
PCIE_PTX_C_DRX_N9 GND DAS/DSS# SATALED# <10,39>
CN65 2 1 0.22U_0402_10V6K 11 12 @ RN100 0_0402_5%
<10> PCIE_PTX_DRX_N9 PCIE_PTX_C_DRX_P9 PETp3 3.3VAUX
CN66 2 1 0.22U_0402_10V6K 13 14
<10> PCIE_PTX_DRX_P9 15 PETn3 3.3VAUX 16
17 GND 3.3VAUX 18
<10> PCIE_PRX_DTX_N10 19 PERn2 3.3VAUX 20
<10> PCIE_PRX_DTX_P10 21 PERp2 N/C 22
C CN67 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N10 23 GND N/C 24 C
<10> PCIE_PTX_DRX_N10 PCIE_PTX_C_DRX_P10 PETp2 N/C
CN68 2 1 0.22U_0402_10V6K 25 26
<10> PCIE_PTX_DRX_P10 27 PETn2 N/C 28
29 GND N/C 30
<10> PCIE_PRX_DTX_N11 31 PERn1 N/C 32
<10> PCIE_PRX_DTX_P11 33 PERp1 N/C 34
CN69 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N11 35 GND N/C 36
<10> PCIE_PTX_DRX_N11 PCIE_PTX_C_DRX_P11 PETn1 N/C
CN70 2 1 0.22U_0402_10V6K 37 38
<10> PCIE_PTX_DRX_P11 39 PETp1 DEVSLP 40 M2280_DEVSLP <10>
41 GND N/C 42
<10> PCIE_PRX_DTX_P12 43 PERn0/SATA-B+ N/C 44
<10> PCIE_PRX_DTX_N12 45 PERp0/SATA-B- N/C 46
CN71 2 1 0.22U_0402_10V6K PCIE_PTX_C_DRX_N12 47 GND N/C 48
<10> PCIE_PTX_DRX_N12 PCIE_PTX_C_DRX_P12 PETn0/SATA-A- N/C
CN72 2 1 0.22U_0402_10V6K 49 50
<10> PCIE_PTX_DRX_P12 51 PETp0/SATA-A+ PERST# 52 PCH_PLTRST#_AND <11,22,29,30,34>
53 GND CLKREQ# 54 PCIE_WAKE# CLKREQ_PCIE#3 <11>
<11> CLK_PCIE_N3 55 REFCLKN PEWake# 56 PCIE_WAKE# <22,30,33>
<11> CLK_PCIE_P3 57 REFCLKP N/C 58
GND N/C
+3.3V_HDD_M2
1 2 M2280_DEVSLP 67 68 SUSCLK_R 1 2
69 N/C SUSCLK(32kHz) (O)(0/3.3V) 70 @ RN99
SUSCLK <11,30>
@ RN37 10K_0402_5% if signal is PCIE GEN3/SATA GEN3 maybe change C value 0_0402_5%
<10> M2280_PCIE_SATA# 71 PEDET (OC-PCIe/GND-SATA) 3.3VAUX 72
or no need for DG0.9 SATA EXPRESS HDD GND 3.3VAUX
73 74
75 GND 3.3VAUX
GND
77 76
GND GND
B LOTES_APCI0170-P001A B
Link DC04000LI00 DONE
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
M2 2280 Socket
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 35 of 58
5 4 3 2 1
5 4 3 2 1
+5V_USB_CHG_PWR
Vinafix.com USB3_PRX_DTX_N6
DI4 ESD@
1 1 10 9 USB3_PRX_DTX_N6 1
JUSB1 CONN@
<10> USB3_PRX_DTX_N6 USB20_N9_R VBUS
150U_B2_6.3VM_R35M
2
USB3_PRX_DTX_P6 USB3_PRX_DTX_P6 USB20_P9_R D-
100U_1206_6.3V6M
0.1U_0201_10V6K
D 2 2 9 8 3 D
<10> USB3_PRX_DTX_P6 @ 4 D+
USB3_PTX_C_DRX_N6 USB3_PTX_C_DRX_N6 1 1 1 USB3_PRX_DTX_N6 GND
CI17
2 1 4 4 7 7 5
<10> USB3_PTX_DRX_N6 USB3_PRX_DTX_P6 SSRX-
CI32
CI14
PESD5V0U2BT_SOT23-3
CI13 0.1U_0402_25V6 + 6 10
SSRX+ GND
2
2 1 USB3_PTX_C_DRX_P6 5 5 6 6 USB3_PTX_C_DRX_P6 7 11
<10> USB3_PTX_DRX_P6 2 2 USB3_PTX_C_DRX_N6 GND GND
ESD@ DI5
CI16 0.1U_0402_25V6 8 12
2
3 3 2 USB3_PTX_C_DRX_P6 9 SSTX- GND 13
SSTX+ GND
1
8 ACON_TCRA2-9U1U93
1
AZ1045-04F_DFN2510P10E-10-9
LINK DC231604011 DONE
RF Request
+5V_USB_CHG_PWR
LI7 EMI@
SW_USB20_N9 1 2 USB20_N9_R
SW_USB20_P9 4 3 USB20_P9_R
12P_0402_50V8J
RF@ CI43
68P_0402_50V8J
RF@ CI44
1 1
EXC24CQ900U_4P
C C
+5V_ALW
+5V_USB_CHG_PWR 2 2
UI3
1 12
VIN VOUT
2
<10> USB20_N9 3 DM_OUT
<10> USB20_P9 DP_OUT 10 SW_USB20_P9
13 DP_IN 11 SW_USB20_N9
<10> USB_OC0# FAULT# DM_IN
ILIM_SEL 4
ILIM_SEL
5 15
<32> USB_POWERSHARE_VBUS_EN EN ILIM_L 16 2 1
RI14
ILIM_HI 22.1K_0402_1%
6
<32> USB_POWERSHARE_EN# 7 CTL1 9
8 CTL2 NC 14
CTL3 GND 17
Thermal Pad
+5V_ALW SLGC55544CVTR_TQFN16_3X3
RI13 2 1 ILIM_SEL SA000097E10 Link Done
10K_0402_5%
B +5V_ALW B
47U_0603_6.3V6M
47U_0603_6.3V6M
10U_0402_6.3V6M
0.1U_0201_10V6K
1 1 1 1
@ CI34
@ CI33
@ CI31
CI19
2 2 2 2
Place near UI3.1
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
JUSB1+PS
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 36 of 58
5 4 3 2 1
5 4 3 2 1
For Breckenridge/Steamboat 12&Kirkwood
DI1 ESD@
USB3_PRX_DTX_N3 1 1 USB3_PRX_DTX_N3
10 9
<10> USB3_PRX_DTX_N3
USB3_PRX_DTX_P3 2 2 9 8 USB3_PRX_DTX_P3
<10> USB3_PRX_DTX_P3
2 1 USB3_PTX_C_DRX_N3 4 4 7 USB3_PTX_C_DRX_N3 +USB_EX2_PWR
<10> USB3_PTX_DRX_N3 7 RF Request
CI5 0.1U_0402_25V6
2 1 USB3_PTX_C_DRX_P3 5 5 6 6 USB3_PTX_C_DRX_P3 +USB_EX2_PWR JUSB2 CONN@
<10> USB3_PTX_DRX_P3
CI4 0.1U_0402_25V6 1
USB20_N2_R VBUS
Vinafix.com
3 3 2
USB20_P2_R 3 D-
D+
0.1U_0201_10V6K
8 4
USB3_PRX_DTX_N3 GND
100U_1206_6.3V6M
1 5
SSRX-
1
USB3_PRX_DTX_P3
CI3
D
AZ1045-04F_DFN2510P10E-10-9 6 10 D
SSRX+ GND
CI1
PESD5V0U2BT_SOT23-3
7 11
GND GND
2
USB3_PTX_C_DRX_N3
12P_0402_50V8J
RF@ CI45
68P_0402_50V8J
RF@ Part Reference
1 1 8 12
2
2 USB3_PTX_C_DRX_P3 SSTX- GND
ESD@ DI2
9 13
2
EXC24CQ900U_4P SSTX+ GND
USB20_P2 4 3 USB20_P2_R ACON_TCRA2-9U1U93
<10> USB20_P2 2 2
1
1
USB20_N2 1 2 USB20_N2_R
<10> USB20_N2
LI3 EMI@ LINK DC231604011 DONE
DFB request:
main SM070003Z00 (INPAQ_MCM1012B900F06BP_4P)
Footprint use 2nd source SM070004400 (PANAS_EXC24CQ900U_4P) +USB_EX2_PWR
Pitch change from 0.5mm to 0.55mm
+5V_ALW
UI1
1
5 OUT
IN 2
GND
10U_0603_10V6M
0.1U_0201_10V6K
4
<32> USB_PWR_EN1# EN
1 3 USB_OC1# <10>
OCB
@ CI6
CI7
SY6288D20AAC_SOT23-5
2
2
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
JUSB2
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 37 of 58
5 4 3 2 1
5 4 3 2 1
RF Request
+3.3V_TP
Touch Pad +3.3V_RUN +3.3V_TP
1
+3.3V_TP PJP35 RF@CZ83
1 2 68P_0402_50V8J
2
Vinafix.com PAD-OPEN1x1m
4.7K_0402_5%
4.7K_0402_5%
1
1
RZ18
RZ19
D D
PS2
2
2 1 DAT_TP_SIO_R CVILU_CF5020FD0RK-05-NH
<32> DAT_TP_SIO_I2C_CLK
@ RZ22 0_0402_5%
2 1 CLK_TP_SIO_R
<32> CLK_TP_SIO_I2C_DAT 22
@ RZ23 0_0402_5%
21 GND
GND
10P_0402_50V8J
10P_0402_50V8J
Keyboard
1
I2C1_SDA_TP_R KB_DET#
CZ80
CZ81
1 2 20
@ RZ346 0_0402_5% <12> KB_DET# 19 20
2
1 2 I2C1_SCK_TP_R 18 19
@ RZ347 0_0402_5% 17 18
16 17
+5V_RUN 16
15
+3.3V_ALW BC_INT#_ECE1117 15 +3.3V_TP +3.3V_ALW +5V_RUN
I2C From EC 14
<32> BC_INT#_ECE1117 BC_DAT_ECE1117 13 14
<32> BC_DAT_ECE1117 12 13
BC_CLK_ECE1117 11 12
<32> BC_CLK_ECE1117 11
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
10 1 1 1
10
@
9
+3.3V_TP DAT_TP_SIO_R 9
CZ90
CZ91
CZ92
8
+3.3V_TP +3.3V_TP CLK_TP_SIO_R 7 8
6 7 2 2 2
5 6
<12,32> TOUCHPAD_INTR# 5
10K_0402_5%
10K_0402_5%
4
4
1
@ @ I2C1_SDA_TP_R 3
3
1
I2C1_SCK_TP_R
2.2K_0402_5%
2.2K_0402_5%
RZ116
RZ117
2
2
RZ20
RZ21
1
C Reserve for future use 1 Place close to JKBTP1 C
JKBTP1 CONN@
2
2
2
1 2 I2C1_SDA_TP_R
<9> I2C1_SDA_TP @ RZ26 0_0402_5% CHECK PIN DEFINE
1 2 I2C1_SCK_TP_R
<9> I2C1_SCK_TP @ RZ29 0_0402_5%
I2C From CPU Update to LTCX007Q500 (DVT1.0)
Plan is for I2C to be driven by the EC for Win7 and Pre-OS (will utilize Intel I2C drivers for Win7)
For Win8.1 and 10 the EC will control TP over I2C Pre-OS and then the PCH will drive I2C when in Windows
Route PS2 from EC to the touch pad also for contingency plan if I2C has issues
B B
RSMRST circuit
+3.3V_ALW
@ CZ82
1 2
0.1U_0201_10V6K
5
1
P
<32> PCH_RSMRST# B 4
O PCH_RSMRST#_AND <11,14>
2
<11,42> ALW_PWRGD_3V_5V A
G
UZ6
3
TC7SH08FU_SSOP5~D
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Keyboard
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 38 of 58
5 4 3 2 1
5 4 3 2 1
HDD LED MUX Bat t er y LE D
means EC can switch battery white led and HDD LED by hot key “ Fn+ H”
<32> MASK_SATA_LED#
Vinafix.com
BATT_WHITE#
5
1 2 BATT_WHITE#
D BAT2_LED#_R <32,39> BAT2_LED# D
4 3 RZ361 100_0402_5%
<10,35> SATALED#
@ QZ2B
3
DMN65D8LDW-7_SOT363-6
1 2 BATT_YELLOW#
<32> BAT1_LED#
R1=10K/R2=10K RZ28 330_0402_5%
2 Change back to SB000002T00 4/25
+3.3V_ALW DDTA144VCA-7-F_SOT23-3
@ QZ3
1
2
1 6 BAT2_LED#_R
<32,39> BAT2_LED#
1 2
@ QZ2A @ RZ25 150_0402_5%
DMN65D8LDW-7_SOT363-6
LED P/N change to SC50000FL00 from SC50000BA00
Breath LED
+5V_ALW
QZ7B LED3
DMN65D8LDW-7_SOT363-6 LTW-C193DC-C_WHITE
4 3 BREATH_LED#_Q 1 2 BREATH_WHITE_LED_SNIFF# 1 2
C <32> BREATH_LED# C
RZ32 330_0402_5%
Place LED3 close to SW3
5
+3.3V_ALW
MASK_BASE_LEDS#
@ CZ93
1 2
0.1U_0201_10V6K
5
1
P
<28,32> LED_MASK# B MASK_BASE_LEDS#
4
2 O
<33,39> LID_CL# A
G
UZ10
TC7SH08FU_SSOP5~D
3
POWER & INSTANT ON SWITCH LED board CONN
+5V_ALW
2 SW3 1 JLED1 CONN@
<11,33> POWER_SW#_MB 1
BATT_YELLOW# 2 1
BATT_WHITE# 3 2
4 3
4 3 5 4
<33,39> LID_CL# 5
6
+3.3V_ALW 6
SKRBACE010_4P 7
8 GND
GND
B ACES_50209-0060N-P01 B
LED Circuit Control Table
Fiducial Mark
@ FD1
1
LED_MASK# LID_CL#
FIDUCIAL MARK~D
@ FD2
Mask All LEDs (Unobtrusive mode) 0 X
1
Mask Base MB LEDs (Lid Closed) 1 0
FIDUCIAL MARK~D
Do not Mask LEDs (Lid Opened) 1 1
@ FD3
1
CLIP1 CONN@
FIDUCIAL MARK~D 1
P1
@ FD4
CPU NGFF FAN
1 @ H1 @ H2 @ H3 @ H4 @ H5 @ H6 @ H7 @ H8 @ H25 @ H26 @ H9 @ H10 @ H12 @ H29 @ H16 @ H20 @ H37 @ H38 @ H39 @ H21 @ H22 CLIP_14P0X2P6
H_3P4 H_3P4 H_3P4 H_3P4 H_1P0N H_1P0N H_3P2 H_3P2 H_3P2 H_3P2 H_2P6 H_3P8 H_3P5 H_2P6 H_2P6 H_3P1 H_3P1 H_2P6 H_2P3N H_3P5 H_3P5
FIDUCIAL MARK~D
CLIP2 CONN@ SHDCAN CONN@
1
1
P1 1
P1
CLIP_7P7X4P2
@ H23 @ H24 @ H14 @ H15 @ H27 @ H28 @ H18 @ H33 SION_SUS304_1P-T
A H_2P6 H_2P6 H_2P6 H_2P6 H_3P5 H_3P5 H_2P6 H_2P6 @ H30 A
H_2P3X2P7N
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PAD, LED
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 39 of 58
5 4 3 2 1
5 4 3 2 1
+3.3V_WLAN/+3.3V_LAN source +1.8V_RUN source
2A
PJP36
1 2 +3.3V_WLAN
+3.3V_ALW
PAD-OPEN1x2m PJP42 0.013A
UZ2 1 2 +1.8V_RUN
+3.3V_WLAN_UZ2
Vinafix.com
1 14 1 2 +1.8V_PRIM UZ8
2 VIN1 VOUT1 13 CZ122 0.1U_0201_10V6K PAD-OPEN1x1m
VIN1 VOUT1 1 7
WLAN_PWR_EN 3 12 1 2 2 VIN VOUT 8 +1.8V_RUN_UZ8 1 2
ON1 CT1 CZ109 470P_0402_50V7K VIN VOUT CZ120 0.1U_0201_10V6K
D D
+5V_ALW
4 11 1 2 3 6 1 2
VBIAS GND <17,32,33,40,45> RUN_ON @ RZ345 ON CT
0_0402_5% CZ121 470P_0402_50V7K
5 10 1 2
<11,32> SIO_SLP_LAN# ON2 CT2 4
CZ110 470P_0402_50V7K +5V_ALW
6 9 VBIAS 5
7 VIN2 VOUT2 8 +3.3V_LAN_UZ2 1 2 GND 9
VIN2 VOUT2 GND
1
CZ111 0.1U_0201_10V6K @
15 CZ197
GPAD PJP37 470P_0402_50V7K AOZ1336_DFN8_2X2
2
EM5209VF_SON14_2X3 1 2 +3.3V_LAN
PAD-OPEN1x1m
1A
Reserve R/C for Audio power sequence, +5V->+3.3V->+1.8V
+3.3V_ALW
+3.3V_ALW_PCH/+3.3V_RUN source
1
RZ518
10K_0402_5%
0.63A
2
PJP38 1 2
<32> SLP_WLAN#_GATE
1 2 +3.3V_ALW_PCH @ RZ71 0_0402_5%
2
PAD-OPEN1x1m DZ9
G
+3.3V_ALW QZ15
UZ3 1 3 SLP_WLAN#_M 3
C +3.3V_ALW_PCH_UZ3 <11,32> SIO_SLP_WLAN# C
1 14 1 2
S
2 VIN1 VOUT1 13 CZ112 0.1U_0201_10V6K S TR BSS138W 1N SOT-323-3 1 WLAN_PWR_EN
VIN1 VOUT1 2
<32> AUX_EN_WOWL
1
@ RZ65 1 2 0_0402_5% 3 12 1 2
<32> PCH_ALW_ON ON1 CT1
@ RZ64 1 2 0_0402_5% CZ113 470P_0402_50V7K RZ38
<11,17,44,45,46> PCH_PRIM_EN 4 11
+5V_ALW BAT54CW_SOT323-3 100K_0402_5%
VBIAS GND
RUN_ON 5 10 1 2 1 2
2
ON2 CT2 CZ114 1000P_0402_50V7K @ RZ70 0_0402_5%
6 9 EC request to reserve OR gate for WLAN power enable
7 VIN2 VOUT2 8 +3.3V_RUN_UZ3 1 2
VIN2 VOUT2 CZ115 0.1U_0201_10V6K
15
GPAD
EM5209VF_SON14_2X3 PJP39
1 2 +3.3V_RUN
PAD-OPEN1x3m
3.435A
+5V_RUN
+5V_RUN/+3.3V_WWAN source
1
@
RZ370
100_0603_5%
2
B B
+5V_RUN_CHG
PJP40 2A
1 2 +5V_RUN
+5V_ALW
UZ4 PAD-OPEN1x2m
1 14 +5V_RUN_UZ4 1 2
2 VIN1 VOUT1 13 CZ116 0.1U_0201_10V6K
VIN1 VOUT1 1
3 12 1 2 D
<17,32,33,40,45> RUN_ON ON1 CT1 CZ117 470P_0402_50V7K 2 @
<32> RUN_ON#
4 11 G QZ4
VBIAS GND L2N7002WT1G_SC-70-3
S
3
3.3V_WWAN_EN 5 10 1 2
<32> 3.3V_WWAN_EN ON2 CT2 CZ118 470P_0402_50V7K
6 9 +3.3V_WWAN_UZ4
+3.3V_ALW VIN2 VOUT2
7 8 1 2
1 2 3.3V_WWAN_EN VIN2 VOUT2 CZ119 0.1U_0201_10V6K
RZ40 100K_0402_5% 15
GPAD PJP41
EM5209VF_SON14_2X3 1 2
+3.3V_WWAN Reserve for S3 no power issue (+5V_RUN discharge circuit)
PAD-OPEN1x3m 2.5A
+3.3V_WWAN_UZ4
A 1 A
RF@ CZ124
2200P_0402_50V7K
2
DELL CONFIDENTIAL/PROPRIETARY
RF Request Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Power control
Size Document Number R ev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 2.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 40 of 58
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
2200P_0402_50V7K
1
PR2
1
EMC@ PC2
1K_0402_5%
+3.3V_RTC_LDO
+Z4012 2
2
Vinafix.com +COINCELL
@ JRTC1
1
2 1 G 4
3
2 G
D D
ACES_50271-0020N-001
2
+RTC_CELL
1
EMC@ PD1 EMC@ PD2
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
EMC@ PL1 PD3
1
FBMJ4516HS720NT_2P
+3.3V_ALW BAS40CW SOT-323 1
3
1 2 PC3
Primary Battery Connector 1U_0603_25V6K
EMC@ PL2
1
FBMJ4516HS720NT_2P 2
PBATT+_C 1 2 +PBATT
@PBATT1 PR1
1
1 2 100K_0402_5%
2
2 3 PRP1
3 4 PBAT_SMBCLK_C 8 1
2200P_0402_50V7K
4 5 PBAT_SMBDAT_C 7 2
5 PBAT_PRES#_C PBAT_CHARGER_SMBDAT <32,50>
6 6 3
6 PBAT_CHARGER_SMBCLK <32,50> PBAT_PRES# <32,50>
1
EMC@ PC1
7 5 4
7 8
8 9 100_0804_8P4R_5%
2
9 10
10 11
GND 12
GND
DEREN_40-42251-01001RHF +3.3V_ALW
@ PR3
2
GND 1 2
0_0402_5%
PR4
2.2K_0402_5%
C EMC@ PL3 PR5 C
1
BLM15AG102SN1D_2P 33_0402_5%
NB_PSID 2 1 1 3 1 2 PS_ID
S
PS_ID <32>
PQ2
2
FDV301N-G_SOT23-3 +5V_ALW
G
2
PR6
100K_0402_1%
3
PD4 EMC@
1
PESD5V0U2BT_SOT23-3 C
2 PQ3 PR7
B MMST3904-7-F_SOT323~D 10K_0402_1%
E
1
3
2
2
PR8
15K_0402_1%
1
PD5
S SCH DIO 5A 100V 15UA 0.88V TO227-3
2
DC_IN+ Source 1 +3.3V_VDD_DCIN +DC_IN
3
+DC_IN
PU2
S1 S2 +SDC_IN 1
VCC
+DC_IN_SS
1000P 50V K X7R 0603
PQ9 PQ4 1
3
EMZB08P03VL 1P EDFN3X3-8 EMZB08P03VL 1P EDFN3X3-8 VOUT
PC11
2
EMC@ PL4 1 1 +SDC_IN GND
2
82P 50V +-5% NPO 0402
FBMJ4516HS720NT_2P 2 2
AO3409 P-CHANNEL SOT-23
AP2204R-3.3TRG1 SOT-89 3P LDO
1
PC12
1 2 3 5 5 3
0.022U_0603_50V7K
PR10 PC10
PC4
PR11
1
PQ5
499K +-1% 0402
PC7 can't over 1000P 300K +-5% 0402 2.2U 10V M X5R 0402 footprint use SA00008HO00
DFLS160-7_POWERDI123-2
2
1
PN use SA0000AVC00
4
4
1
3
B S B
1M +-5% 0402
@
0.022U_0603_50V7K
@RF@
2
1
G
2
2 PR12
2
PD6
PC6
100K_0402_5%
1000P_0603_50V7K
10U_0805_25V6K
2
1
1
@ PJPDC1 +3.3V_VDD_DCIN
0.1U_0603_25V7K
D
4.7K_0805_5%
1
1
PC8
7 PR15
GND
1
PR14
EMC@ PC5
PC7
6 100K_0402_5%
2
GND 5 -DCIN_JACK
PR13
5 4 RF reserved
DMN65D8LDW-7_SOT363-6
PR16
2
2
4
1
3 +DCIN_JACK
49.9K +-1% 0402
@EMC@
3 2 PR17
@
2 1
1 100K_0402_5%
6
1
CVILU_CI0805M1HRC-NH
PR19
2
2
PQ1A
2 1 2
DMN65D8LW-7_SOT323-3
PR18
PC9
+3.3V_VDD_DCIN PR20
1
2 1 1M +-5% 0402 D
2
1
0_0402_5%
PQ7
2 1 2
0.1U_0402_10V7K
DMN65D8LDW-7_SOT363-6
G
S
3
0_0402_5% VBUS2_ECOK <32,51>
DMN65D8LW-7_SOT323-3
0_0402_5% PU1
PR21
5
MC74VHC1G08DFT2G SC70 5P AND
PR23
1
3
<32,50,51> HW_ACAVIN_NB 1 2 1 D
P
PR22 B
PQ6
4 1 2 2
O PR25
PQ1B
1 2 2 G
A
G
S PR24 5 1 2
AC_DISC# <32,51>
3
0_0402_5% 100K_0402_5%
3
0_0402_5%
4
0_0402_5%
PQ8
1
DMN65D8LW-7_SOT323-3
@ PR26
S
1 2 3 1 PR30
<32> DCIN2_EN
100K_0402_1%
2
0_0402_5%
G
1 2
1
100K_0402_5%
A A
1
PR28
@
PR29
0_0402_5%
PR27
2
100K_0402_5%
2
DELL CONFIDENTIAL/PROPRIETARY
+3.3V_VDD_DCIN
+3.3V_ALW Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 2.0
LA-F311P
Date: Wednesday, December 20, 2017 Sheet 41 of 58
5 4 3 2 1
A B C D E
PR119
PGOOD_3V 1 2
Vinafix.com 0_0402_5%
PR120
ALW_PWRGD_3V_5V <11,38>
PGOOD_5V 1 2
1 1
0_0402_5%
PR102
499K_0402_1%
ENLDO_3V5V 1 2
+PWR_SRC PR100
+PWR_SRC
PJP100 PC102
1
3V_VIN BST_3V
499K_0402_1%
1 2 1 2 1 2
PR103
PAD-OPEN 1x2m~D 0.1U_0603_25V7K
0_0603_5%
100P 50V J NPO 0402
1
1U_0402_25V6K
1U_0402_25V6K
1000P_0402_50V7K
1000P_0402_50V7K
PU100
2
10U_0603_25V6M
10U_0603_25V6M
@EMC@ PC100
@EMC@ PC103
100P 50V J NPO 0402
BS
IN
IN
IN
IN
1
1
@EMC@PC135
@EMC@PC136
LX_3V 6
@EMC@ PC133
@EMC@ PC134
PC105
PC104
20 PL100
LX LX 1.5UH +-20% 9A 7X7X3 MOLDING
2
2
7 19 LX_3V 1 2
GND LX +3.3V_ALWP
@EMC@ PR106
8 18
GND GND PR104
100P_0402_50V8J
4.7 +-5% 1206
SY8288BRAC_QFN20_3X3
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
9 17 1 2
PG LDO +3.3V_ALW2
RF@ PC141
PC106
PC107
PC108
PC109
PC129
PC110
10 16 PR105
NC NC 1 0_0402_5%
2 +3.3V_RTC_LDO
OUT
1
EN2
EN1
21
NC
3VALWP
FF
GND
1 3V_SN 2
0_0402_5%
PR107 TDC 6.5 A
11
12
13
14
15
680P_0603_50V7K
100K_0402_5%
Peak Current 9.29 A
@EMC@ PC112
2 1 2 3.3V LDO 150mA~300mA 2
+3.3V_ALW
1
OCP Current 11.04A
ENLDO_3V5V
PC111 Vout is 3.234V~3.366V RF reserved
4.7U_0603_6.3V6K
2
PGOOD_3V
PJP102
PC113 PR108 +3.3V_ALWP 1 2 +3.3V_ALW
1000P_0402_50V7K 1K_0402_5% 1 2
3V5V_EN 3V_FB 1 2 1 2 JUMP_43X118
PJP103
+PWR_SRC PR111 +5V_ALWP 1 2 +5V_ALW
PJP101 PC114 1 2
1 2 5V_VIN BST_5V 1 2 1 2 JUMP_43X118
PAD-OPEN 1x2m~D 0.1U_0603_25V7K
0_0603_5%
2200P_0402_50V7K
1U_0402_25V6K
1U_0402_25V6K
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
1
10U_0805_25V6K
10U_0805_25V6K
@EMC@ PC115
@EMC@ PC116
0.1U_0402_25V6
PU102
1
RF@ PC143
@EMC@PC139
@EMC@PC140
BS
IN
IN
IN
IN
@EMC@ PC137
@EMC@ PC138
PC117
PC118
LX_5V 6 20 PL101
2
LX LX 1.5UH +-20% 9A 7X7X3 MOLDING
7 19 LX_5V 1 2
3 GND LX +5V_ALWP 3
100P_0402_50V8J
8 18
GND GND
1
PR112
680P_0603_50V7K 4.7_1206_5%
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
22UF_0805_6.3V6M
SYV828CRAC QFN 20P PWM PC119
2
@EMC@
RF@ PC142
9 17 1 2
PC120
PC121
PC122
PC123
PC130
PC124
PG VCC
10 16
1
NC NC 4.7U_0603_6.3V6K
1 5V_SN
OUT
LDO
2
EN2
EN1
21
FF
GND
11
12
13
14
15
PC125
E9 delete PD100 PR113
@EMC@
100K_0402_5%
+5V_ALW2 RF reserved
2
1 2
+3.3V_ALW
ENLDO_3V5V
5V LDO 150mA~300mA
3V5V_EN
PGOOD_5V
PC126
4.7U_0603_6.3V6K
PR114
5VALWP
2
1 2
<32> ALWON
TDC 7.6 A
0_0402_5% Peak Current 8.06A
3V5V_EN
OCP Current 9.67 A
1M_0402_1%
4.7U_0603_6.3V6K
1
1
PR116
PC128
PC127 PR117
1000P_0402_50V7K 1K_0402_5%
5V_FB 1 2 1 2
2
2
4 4
EN1 and EN2 dont't floating
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +5V_ALW/3.3V_ALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 42 of 58
A B C D E
5 4 3 2 1
Vinafix.com
D D
+PWR_SRC
PJP202
1 2 +1.2V_DDR_B+
@EMC@
@EMC@
10U_0805_25V6K
10U_0805_25V6K
PU200
100P_0402_50V8J
100P 50V J NPO 0402
100P 50V J NPO 0402
PAD-OPEN 1x2m~D @EMC@ @EMC@
1
2
PC200
PC201
PC224 +3.3V_ALW 10 19 PR202 PC204
IN OT
PC202
PC203
4.7_1206_5% 680P_0603_50V7K
13 18 @ 1 2SNU_DDR
1 2
PR203
2
BYP PG
1U_0402_6.3V6K
14 12 1 2BST_DDR
1
PC205
2
+1.2V_DDRP
RF@
VCC BS
1
PC206
C 0.1U_0603_16V7K PL201 C
1
LX_DDR
2.2U_0402_6.3V6M
4 11 1 2
VTTGND LX 0_0603_5%
PC207
1UH +-20% 11A 7X7X3 MOLDING, A.2
2
330P_0402_50V7K
2 9 16
PGND FB
1
102K_0402_1%
RF reserved
@EMC@
@EMC@
1
+1.2V_DDRP
PC208
PR204
15 8 PC209
+3.3V_ALW SGND VDDQSNS
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
100P 50V J NPO 0402
22U_0603_6.3V6M
R1
100P_0402_50V8J
7 1 2
2
VLDOIN
1
PC210
PC211
PC212
PC213
PC223
PC214
PC216
PC217
2
2
@ ILMT_DDR 17 6
PR205 ILMT VTT +0.6VSP
2
The current limit is 0_0402_5% 1 5
S5 VTTSNS
set to 8A, 12A or 16A
1
100K_0402_1%
2 3
1
when this pin is pull S3 VTTREF
22U_0603_6.3V6M
PR206
R2
1
ILMT_DDR
1U_0402_10V6K
PC218
low, floating or pull
PC219
high SY8210AQVC_QFN19_4X3
EN_1.2V
+1.2V_DDR OCP set 8A
2
2
EN_0.6V
@PR207
0_0402_5%
1
PR208
1 2
B B
0.1U_0402_10V7K
<11,17,32,46> SIO_SLP_S4#
1M_0402_5%
0_0402_5%
1
1
PC221
PR209
+1.2V_DDRP +1.2V_MEM +0.6VSP +0.6V_DDR_VTT
2
@
PJP200 PJP201
2
JUMP_43X118 JUMP_43X39
1 2 1 2
1 2 1 2
PR210
<20> 0.6V_DDR_VTT_ON
1 2
0.1U_0402_10V7K
1M_0402_5%
0_0402_5% Mode S3 S5 VOUT VTT
1
@ PC222
Normal H H on on 0.6Volt +/- 5%
PR212
Stadby L H on off +1.2V_DDR TDC 1.05 A
2
Shutdown L L off off TDC 6.5A Peak Current 1.5 A
Peak Current 9.4A
2
Note: S3 - sleep ; S5 - power off OCP Current 2A (fix)
OCP Current 11.2A
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.2V_MEN/+0.6V_DDR_VTT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 43 of 58
5 4 3 2 1
5 4 3 2 1
Vinafix.com
D D
PJP302
+1VALWP 1
1 2
2 +1.0V_PRIM
JUMP_43X118
RF@ PR303 RF@ PC302
4.7_1206_5% 680P_0603_50V7K
2 SNB_+1VALWP 1
+PWR_SRC PJP301
+1VALW P_B+
PU301
1 2
1 2 2 9 @
0.1U_0402_25V6
PC304
100P 50V J NPO 0402
IN PG PR304
10U_0603_25V6M
10U_0603_25V6M
0.1U_0603_25V7K
PAD-OPEN 1x2m~D 3 1 BST_+1VALWP 1 2BST_+1VALWP_C
1 2 PL301
IN BS
1
1
PC305
PC306
0.68UH_7.9A_20%_5X5X3_M
SW _+1VALW P +1VALWP
RF@ PC301
RF@ PC303
4 6 1 2
IN LX 0_0603_5%
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
5 19
IN LX
100P_0402_50V8J
100P_0402_50V8J
330P_0402_50V7K
1
1
PC314
PC315
7 20
GND LX
21.5K_0402_1%
PC307
PC308
PC309
PC310
PC311
1
8 14 FB_+1VALWP
2
GND FB
PR306
C C
@ 18 17
RF@
RF@
4.7U_0603_6.3V6K
PR312 GND VCC
1
1K_0402_5%
1
EN_+1VALWP
PC313
PR308
1 2 11 10
<11,17,40,45,46> PCH_PRIM_EN
2
EN NC
1
13 12
2
0_0402_5% ILMT NC
2
1M_0402_1% 15 16
PR302 +3.3V_ALW BYP NC
4.7U_0603_6.3V6K
21
2
PAD
1
1
PC312
100P_0402_50V8J
SY8286RAC_QFN20_3X3 PR311
PC316
31.6K_0402_1%
2
+3.3V_ALW
2
@RF@
1
@ PR307
0_0402_5% RF reserved
2
ILMT_+1VALWP
+1.0V_PRIM
1
@ PR310
The current limit is set to 6A, 9A or 12A TDC 4.9A
when this pin is pull low, floating or pull high Peak Current 7.1 A
0_0402_5%
B B
OCP Current 8.6A
2
TYP MAX
Choke DCR 11.0mohm , 12.0mohm
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-F311P
Date: Wednesday, December 20, 2017 Sheet 44 of 58
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE
1
@ PR425
PR404 @ 0 X X 0(LPM)
<11,17,34,45> SIO_SLP_S0# 1 2 0_0402_5%
PJP401
TPS62134C 1 0 0 0.80
2
0_0402_5% JUMP_43X79
1 2
1 0 1 0.95
PR402 +1VS_VCCIOP 1 2 +1.0VS_VCCIO 1 1 0 1.00
<17,32,33,40> RUN_ON
Vinafix.com 1 2
1 1 1 1.05
EN_1VS_VCCIO
0.1U_0402_25V6
0_0402_5%
1
@ PC402
@ PR403
D 1M_0402_1% D
2
@ PL405
3A_Z120_40M_0603_2P
2
1 2
13
14
15
16
17
PU401
Vin=3~17V
TP
LPM
EN
PGND
PGND
PJP403
+1.0VS_VCCIO
+5V_ALW 1 2 VIN_1VS_VCCIO 12
PVIN VOS
1
+1VS_VCCIOP TDC 1.9 A
Peak Current 2.7 A
10U_0603_10V6M
10U_0603_10V6M
PL402
PAD-OPEN1x1m 1UH_1277AS-H-1R0N-P2_3.3A_30% OCP Current 3.3 A
1
LX_1VS_VCCIO
+3.3V_ALW +1VS_VCCIOP
PC403
PC404
11 2 1 2
PVIN SW TYP MAX
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
Choke DCR 48.0mohm
2
TPS62134CRGT_QFN16_3X3
1
PC425
PC426
PC406
PC407
10 3
AVIN SW
2
2200P_0402_50V7K
SNUB_1VS_VCCIO
0.1U_0402_25V6
1
1
VID0_VCCIO 9 4
PC408
@EMC@ PC409
VID0 PG @EMC@ PR405
1
AGND
4.7_0603_5%
VID1
FBS
@ PR413 PR414 @EMC@
SS
2
10K_0402_1% 10K_0402_1%
2
5
VID0_VCCIO
1
@EMC@ PC401
SS_1VS_VCCIO
VID1_VCCIO +1VS_VCCIOP
VID1_VCCIO
0 +-5% 0402
470P_0402_50V7K
1
1
PR421
470P_0402_50V7K
PR415 @ PR416
10K_0402_1% 10K_0402_1% @ PR422
2
1
1
C 0_0402_5%
0_0402_5%
C
2
@ PR427
PC410
1 2
VCCIO_SENSE <17>
2
@
PR412
2
1 2
VSSIO_SENSE <17>
0_0402_5%
"R" for SILERGY
+3.3V_ALW
1
@ PR410
@ PR426
0_0402_5%
1 2
<11,17,34,45> SIO_SLP_S0#
2
0_0402_5%
PJP402
@ JUMP_43X79
EN_1.0V_PRIM_COREP
PR406 1 2
<11,17,40,44,46> PCH_PRIM_EN 1 2 +1.0V_PRIM_COREP 1 2 +1.0V_PRIM_CORE
0.1U_0402_25V6
0_0402_5%
1
1
@ PC411
PR407
@ PL406 1M_0402_1%
2
3A_Z120_40M_0603_2P
1 2
2
13
14
15
16
17
PU402
B Vin=3~17V B
TP
LPM
EN
PGND
PGND
PJP404
VIN_1V_PRIM
+5V_ALW 1 2 12
PVIN VOS
1
+1.0V_PRIM_COREP
+3.3V_ALW
10U_0603_10V6M
10U_0603_10V6M
PL404
PAD-OPEN1x1m 1UH_1277AS-H-1R0N-P2_3.3A_30%
1
LX_1V_PRIM
+1.0V_PRIM_COREP
PC412
PC413
11 2 1 2
PVIN SW
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2
TPS62134DRGT_QFN16_3X3
1
PC427
PC428
PC424
PC415
10 3
AVIN SW
Rup
LPM LOGIC VID1 LOGIC VID0 LOGIC OUTPUT VOLTAGE
2
2200P_0402_50V7K
0.1U_0402_25V6
1
9 4
PC417
0 X X 0.7(LPM)
@EMC@ PC418
VID0 PG
1SNUB_1V_PRIM
@EMC@ PR409
PR417 PR418 TPS62134D 1 0 0 0.85
2
AGND
VID0_PRIM_CORE
10K_0402_1% 10K_0402_1% 4.7_0603_5%
VID1
FBS
@EMC@
1 0 1 0.90
SS
2
VID0_PRIM_CORE
1 1 0 0.95
8
VID1_PRIM_CORE @EMC@
PC419 1 1 1 1.00
1
VID1_PRIM_CORE
470P_0402_50V7K
2
@ PR408
@ PR419 @ PR420 0_0402_5%
SS_1V_PRIM
10K_0402_1% 10K_0402_1% 1 2
<18> CORE_VID0
2
@ PR411 @ +1.0V_PRIM_CORE
PR423
0_0402_5% TDC 1.8 A
1 2 1 2
<18> CORE_VID1 Peak Current 2.6 A
OCP Current 3.1 A
470P_0402_50V7K
0_0402_5%
1
1M_0402_1%
1
1
PR428
A A
TYP MAX
PC420
@ PR424
100K_0402_1%
Choke DCR 48.0mohm
2
@
2
DELL CONFIDENTIAL/PROPRIETARY
"R" for SILERGY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1VS_VCCIOP/+1.0V_PRIM_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-F311P
Date: Wednesday, December 20, 2017 Sheet 45 of 58
5 4 3 2 1
5 4 3 2 1
PC531
2 1
@ PL502
3A_Z120_40M_0603_2P 10U_0603_6.3V6M
1 2 PJP502
PC530
2 1 1 2
+1.8VALWP +1.8V_PRIM
PJP501 10U_0603_6.3V6M PAD-OPEN1x1m
Vinafix.com 1 2 VIN_1.8VALW
+3.3V_ALW Imax= 2A, Ipeak= 3A
PAD-OPEN1x1m
FB=0.6V
D D
PR517 PU501
PL501
2 1 1UH_1277AS-H-1R0N-P2_3.3A_30%
+3.3V_ALW 4 3 LX_1.8VALW 1 2
100K_0402_5% IN LX +1.8VALWP
1
5 2
68P_0402_50V8J
<32> 1.8V_PRIM_PWRGD PG GND
1SNUB_1.8VALW
22U_0603_6.3V6M
22U_0603_6.3V6M
@EMC@ PR502
1
PC503
6 1
FB EN
1
PC501
PC504
4.7_0603_5%
PR501
2
@ RT8097ALGE_SOT23-6
PR504
2
20K_0402_1%
1 2 EN_1.8VALW
<11,17,40,44,45> PCH_PRIM_EN Rup
2
@EMC@ PC506
0_0402_5%
1
680P_0402_50V7K
2
1
PR505 @ PC505
1M_0402_1% 0.1U_0402_16V7K
2
FB_1.8VALW
1
PR506
Rdown +1.8V_PRIM
10K_0402_1% TDC 0.7 A
Peak Current 1.0 A
2
OCP Current 1.2 A
Note:
When design Vin=5V, please stuff snubber Vout=0.6V* (1+Rup/Rdown)
to prevent Vin damage
C C
B B
+2.5V_MEN
TDC 0.3A by power budget
AP7361 U-DFN3030-8 Pd limit=1.7W
Peak loading=1.1A.
Pd=(3.3-2.5)*1.1=0.88W < 1.7W
OCP is 1.1~1.5A
PU503
PJP505
AP7361C-FGE-7-01 U-DFN3030 8P LDO PJP506
1 2 +2.5V_VIN 9
+3.3V_ALW GND 1 2.5VSP 1 2
OUT
+2.5V_MEM
1
8
PAD-OPEN1x1m PC514 IN 2
NC PAD-OPEN1x1m
1
4.7U_0603_6.3V6K 7 PR515
2
NC 3 21.5K_0402_1% PC515
6 ADJ/NC 0.01UF_0402_25V7K
PR513
2
@ NC 4 1
1 2 EN_2.5V 5 GND PC516
<11,17,32,43> SIO_SLP_S4# EN 22U_0603_6.3V6M
2
0_0402_5%
1
@
A PC513 A
PR514 PR516
2
1M_0402_1% .1U_0402_16V7K 10.2K_0402_1%
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VALWP/+1.5VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
LA-F311P
Date: Wednesday, December 20, 2017 Sheet 46 of 58
5 4 3 2 1
5 4 3 2 1
+1.0V_VCCST VCC_SA U22
TDC 4.0A VCC_SA U42
Peak Current 4.5A TDC 4.0A
@
OCP current 10A Peak Current 5A
PR602
OCP current 10A
0.1U_0402_25V6
Choke DCR 6.2 m ohm
1
45.3_0402_1%
100_0402_1%
75_0402_1%
1 2
PC602
+5V_ALW Choke DCR 6.2 m ohm
PR605
PR601
PR604
Local sense put on HW site Vinafix.com 0_0402_5%
2
PJP603
@ 1 2CPU_B+
0.22U_0603_25V7K
2
2
1 2
1U_0603_10V6K
D 1 2 @ PR603 VCCSA_B+ CPU_B+ D
<15> VIDSCLK
1
49.9_0402_1% PR618
PC603
PC604
PAD-OPEN1x1m
<15> VIDALERT_N 1 2 0_0402_5%
@ PR625 0_0402_5%
2
<15> VIDSOUT 1 2
10_0402_1% PR626
PR678 VCCSA_B+
VIDALERT_N_B
<12,32,50> PROCHOT#
VIDSOUT_B
VIDSCLK_B
100_0402_1%
1 2 1 2
1 2
PC605 47P_0402_50V8J~D
470K_0402_5%_B25/50 4700K PR608
PR610 88.7K_0402_1%
10U 25V 0603 ZRB
10U 25V 0603 ZRB
PH601
10K_0402_1% 1 2
1 2 1 2 @ PR613 1.91K_0402_1% PR612
1
1 2
PC612
PC608
90.9K +-1% 0402 PR611
1 2 1 2 +3.3V_RUN 1.87K +-1% 0402
PR631 PC613 <11> PCH_PWROK
@ 1
PR614 2
2
27.4K_0402_1% 330P_0402_50V7K 0_0402_5%
1 2 1 2
<33> IMVP_VR_ON
PC614 PR617
2200P_0402_50V7K 4.3K_0402_1% @ PR616
1 2 1 2 0_0402_5%
40
39
38
37
36
35
34
33
32
31
PU602 SA_UGATE
@ PC616 PR619 2.2_0603_5%
VR_ENABLE
VR_READY
SCLK
SDA
VCC
VIN
VR_HOT#
ALERT#
PROG1
PROG2
33P_0402_50V8J 1 2
PR620
1 2 @ PC617 @ PR621 @
BST_SA
1200P_0402_50V7K 316_0402_1% 1 2 1 30 PWM_VSA PU614
<32,50> I_SYS PSYS PWM_C
1
1 2 1 2 2 29 FCCM_VSA S IC ISL95808HRZ-TS2778 DFN MOSFET DRIVE PQ614
<15> VCCSENSE IMON_B FCCM_C
@ PR622 3 28 PE642DT 2N PDFN3X3S
D1
D1
D1
G1
@ PC618 1.91K_0402_1% 0_0402_5% 4 NTC_B ISUMN_C 27 PC611 1 8 PL614
1 2 1 2 5 COMP_B ISUMP_C 26 0.22U_0603_16V7K UGATE PHASE 0.47UH_MMD05CZR47M_12A_20%
0.082U_0402_16V7K
6 FB_B RTN_C 25 FB_VSA 1 2 2 7 10 9 SA_SW 4 1
PC620
RTN_B FB_C BOOT FCCM D1 D2/S1
+VCC_SA
1
330P_0402_50V7K 7 24 COMP_VSA
ISUMP_B COMP_C IMON_VSA PWM_SA
RF@
PC621 PR623 8 23 3 6 3 2
C
PC619 680P_0402_50V7K 2K_0402_1% 9 ISUMN_B IMON_C 22 PWM VCC C
G2
S2
S2
S2
2
ISEN1_B PWM_A PWM_GT <48>
1
SA_LGATE
100P_0402_50V8J
1 2 @ 1 2 1 2 10 21 4 5
4.7_1206_5%
ISEN2_B FCCM_A FCCM_GT <48> GND LGATE
1
@PR606
TP
ISUMN_A
ISUMP_A
PR624
PWM1_B
PWM2_B
COMP_A
8
FCCM_B
2
IMON_A
41
PR627
RF@ PC695
0.01UF_0402_25V7K 0_0402_5%
NTC_A
RTN_A
AGND 3.65K_0603_1%
FB_A
PWM_VSA
<15> VSSSENSE
1
1
1
@PR679
ISUMP_VSA 2
0_0402_5%
+5V_ALW
1SA_SNUB
ISUMN_VSA
11
12
13
14
15
16
17
18
19
20
12P 50V J NPO 0402
68P 50V J NPO 0402
ISL95857AHRTZ-T TQFN 40P PWM
1
PC700
PC701
680P_0603_50V7K
<48> ISUMP_IA
2
IMON_GT
FB_GT
FCCM_VSA
NTC_GT
COMP_GT
<48> FCCM_IA
RF@ PC622
4.99K_0402_1%
<48> PWM1_IA
2
2
RF@
<48> PWM2_IA RF reserved
RF@
PR628
@ PR658 PC625
20M_0402_5% 330P_0402_50V7K
2
1 2
PC685
1U_0402_10V6K
0.047U_0402_25V7K
.022U 16V K X7R 0402
PR629
1
86.6K +-1% 0402
1
1
1 2
PC624
PC626
RF reserved
2.49K_0402_1%
33P 50V J NPO 0402
PH603
PR630
10K_0402_5%_B25/50 4250K
1
PR632 PC627 470K_0402_5%_B25/50 4700K
11K_0402_1%
2200P_0402_50V7K
4700P 25V 0402
2
2
1
2200P_0402_50V7K
PR633
@ @ 1 2 1 2
PC628
1K_0402_1%
1 2 1 2 ISUMP_VSA
PH602
2
PR647 PR635 1 2
374_0402_1%
1
@ PR638 27.4K_0402_1% 10K_0402_1%
2.61K_0402_1%
2
1
1 2
PC630
PR640
374_0402_1% PR636 665 +-1% 0402
2
1 2
PC631
PC629 PR639
PR642
<48> ISUMN_IA 2200P_0402_50V7K 3.09K_0402_1% 1 2 1 2
2
@U42 PC635 1 2 1 2
10KB_0402_5%
2
0.022U_0402_16V7K PC632 PR641
0.033U 25V K X7R 0402
2
2
1 2 ISEN1_IA PC636 1000P_0402_50V7K 1K_0402_1%
1K_0402_1%
11K_0402_1%
33P_0402_50V8J
PR643
4700P 50V K X7R 0402
1
1
1 2
PR644
PC633
PC637
@U42 PC638
1
B 0.022U_0402_16V7K PC639 PR645 PR646 PC640 B
1
1 2 ISEN2_IA 1500P_0402_50V7K 316_0402_1% 1 2 1 2
@U22PR634 1 2 1 2
330P_0402_50V7K
2
PH604
0_0402_5% 316_0402_1% 2200P_0402_50V7K
1 2
2
1 2 PR649
.1U_0402_16V7K
+5V_ALW
1
1
1 2 PR648 1 2
113K_0402_1%
1
ISUMN_VSA
PC641
1.91K_0402_1% PC642
<48> ISEN1_IA @U22PR615
PC643
PR651
.022U 16V K X7R 0402 1.62K_0402_1% PC644
680P_0402_50V7K 2K_0402_1%
2
1
0_0402_5% 1 2 .1U_0402_16V7K
2K_0402_1%
<48> ISEN2_IA
2
1 2
PR652
.1U_0402_16V7K
2
1
PR650
PC645
2
1 2
PC646 @
680P_0402_50V7K
0.047U_0402_25V7K
2
1 2 VSA_SEN- <17>
PC647
PC601
2
1
PC649
@ 0.01UF_0402_25V7K
0.082U_0402_16V7K
1 2
<16> VCC_GT_SENSE
PR656
11K_0402_1%
2
1 2
PC650
@
PC652
PR657
1
@ PC651 @ 330P_0402_50V7K
PH605
1 2 4.42K_0402_1% 1 2
1 2 1 2
0.082U_0402_16V7K
330P_0402_50V7K
PC653
1
@ PR653 10K_0402_5%_B25/50 4250K VSA_SEN+ <17>
2 1 ISUMN_GT <48>
2
PC654 @ 20M_0402_5%
A A
1 2
ISUMP_GT <48>
0.01UF_0402_25V7K
<16> VSS_GT_SENSE
DELL CONFIDENTIAL/PROPRIETARY
Local sense put on HW site
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_VCORE_ISL95857
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 47 of 58
5 4 3 2 1
5 4 3 2 1
U42
VCC_core (U22) VCC_core (U42)
TDC 21A TDC 42A +VCC_CORE +VCC_GT_+VCC_CORE
@U42 PR682 PC626 @U42 PR613 @U42 PR621 @U42 PC624 @U42
Peak Current 32A Peak Current 64A 1 2
1 2
OCP current 38.4A OCP current 76.8A SOLDER_PREFORMS_0603
Choke DCR 0.9 +-5%m ohm Choke DCR 0.9 +-5%m ohm +VCC_GT
Vinafix.com @U22 PR683
1
1 2
2
0.1U 25V 0402 93.1K +-1% 0402 1K +-1% 0402 0.015U 25V K X7R 0402
D SOLDER_PREFORMS_0603 PR638 @U42 PR622 @U42 PC616 @U42 PC617 @U42 D
PJP601
+PWR_SRC
1 2 +VCC_CORE +VCC_GT_+VCC_CORE
CPU_B+ PAD-OPEN 4x4m
@U42 PR684 475 +-1% 0402 3.09K_0402_1% 68P 50V J 0402 220P 50V 0402
1U_0402_25V6K
1U_0402_25V6K
1000P_0402_50V7K
1000P_0402_50V7K
@EMC@ PL602 1 2
1 2
1
1 2
@EMC@PC691
@EMC@PC692
9A Z80 10M 1812_2P SOLDER_PREFORMS_0603
@EMC@ PC689
@EMC@ PC690
U22
PC659 RF@
RF@
100U_D_20VM_R55M
0.1U_0402_25V6K~D
2
100U_D_20VM_R55M
1 1
2200P_0402_50V7K
1
+ +
PC606
PC607
10U 25V 0603 ZRB
10U 25V 0603 ZRB
10U 25V 0603 ZRB
10U 25V 0603 ZRB
PC626 @U22 PR613 @U22 PR621 @U22 PC617 @U22
PC658
1
1
PC682
PC656
PC657
PC660
2
2 2
For KBL U42 : Pop PR682 and PR684
2
For KBL U22 : Pop PR683 and PR685
RF demand 0.047U_0402_25V7K 90.9K +-1% 0402 316 +-1% 0402 1200P 50V 0402
PR638 @U22 PR622 @U22 PC616 @U22 PC624 @U22
PL610
0.15UH 20% MMD-06CZER15MEX5L 35A
PU610 +VCC_CORE 383 +-1% 0402 1.5K +-1% 0402 33P 50V J 0402 .022U 16V K X7R 0402
10 11 4 1
PGND SW
RF@
9 12
VIN SW 3 2
4.7_1206_5%
100P_0402_50V8J
PC655 8 13
0.1U 25V K X5R 0402
VIN GL
IA1P
0.22U_0603_16V7K IA1N
+5V_ALW
1
2
C C
1 2 7 14
PC680
PR663
RF@ PC696
6 PHASE PGND 15 PR667 @U42 PR668 PR666
N/C PVCC 3.65K_0603_1% 100K_0402_1% 10_0402_1% VCC_GT (U22) VCC_GT (U42)
2
1
1 PR660 2 5 16 1 2 1 2
1U_0402_10V6K
2
BOOT N/C
TDC 18A TDC 12A
1
3.9 +-1% 0603 4 17
10K_0402_1%
2
AGND N/C
1
@ PR686
PC661
<47> ISEN1_IA Peak Current 31A Peak Current 28A
IA_SNUB1
3
VCC
2 19 @ PR670 OCP current 37.2A OCP current 33.6A
2
PR688 1 FCCM GL 18 IA2N 2 1
+5V_ALW Choke DCR 0.9 +-5%m ohm Choke DCR 0.9 +-5%m ohm
2
1_0603_5% PWM AGND 100K_0402_1% RF reserved
1 2 VCC_IA1 FDMF3035_PQFN31_5X5 GPU_B+
680P_0603_50V7K
1U_0402_10V6K
RF@ PC662
1
<47,48>
<47,48>
ISUMP_IA
ISUMN_IA
PC676
2
PJP602
1 2
GPU_B+ CPU_B+
10U 25V 0603 ZRB
10U 25V 0603 ZRB
10U 25V 0603 ZRB
10U 25V 0603 ZRB
1
1
@
PC675
PC674
PC664
PC665
PAD-OPEN 1x2m~D
<47,48> FCCM_IA 1 PR659 2
2
0_0402_5%
@ PR687
1 2
<47> PWM1_IA
0_0402_5%
RF@ PR669 RF@ PC670
4.7_1206_5% 680P_0603_50V7K
1 2 GT_SNUB 1 2
10U 25V 0603 ZRB
10U 25V 0603 ZRB
10U 25V 0603 ZRB
10U 25V 0603 ZRB
B B
1
1
PC683
PC684
PC672
PC673
PL612
RF reserved PU612 0.15UH 20% MMD-06CZER15MEX5L 35A
10 11 GT_SW 4 1
2
9 PGND SW 12
VIN SW 3 2 +VCC_GT
0.1U 25V K X5R 0402
100P_0402_50V8J
100P_0402_50V8J
PC663 8 13
@U42 @U42 @U42 @U42 VIN GL
1
1
PC702
PC681
0.22U_0603_16V7K
+5V_ALW
2
@U42 1 2 7 14
RF@ PC703
PL613 PR661
0.15UH 20% MMD-06CZER15MEX5L 35A 6 PHASE PGND 15
2
2
N/C PVCC 3.65K_0603_1%
@RF@
1
@U42 PU613 1 PR665 2 5 16
1U_0402_10V6K
BOOT N/C
1
10 11 IA_SW2 4 1 3.9 +-1% 0603 4 17
10K_0402_1%
2
PGND SW AGND N/C
1
RF@
9 12
PR681
PC668
VIN SW +VCC_CORE
<47>
<47>
ISUMP_GT
ISUMN_GT
3 2 3
@U42 PC671 8 13 2 VCC 19
4.7_1206_5%
2
VIN GL FCCM GL
1
IA2P
0.22U_0603_16V7K IA2N 1 18 @
+5V_ALW
0.1U 25V K X5R 0402
2
PWM AGND
1
1 2 7 14
PR676
PR680
RF reserved
PHASE PGND
1
6 15
@U42 PC679
@U42
PR674 @U42 PR675 @U42 PR673 FDMF3035_PQFN31_5X5
N/C PVCC 3.65K_0603_1% 100K_0402_1% 1 2 VCC_GT
10_0402_1%
1 2 5 16 1 2 1 2
1U_0402_10V6K
2
BOOT N/C
1
@U42 PR672 4 17
10K_0402_1%
AGND N/C 1_0603_5%
1
@ PR689
@U42 PC697
3.9 +-1% 0603
1U_0402_10V6K
<47> ISEN2_IA
+5V_ALW
1
3 PC669
IA_SNUB2
2 VCC 19 @ PR677
2
1 FCCM GL 18 IA1N 1 2
2
PWM AGND 100K_0402_1%
@U42 PR691 FDMF3035_PQFN31_5X5
+5V_ALW 1_0603_5%
1 2 VCC_IA2
<47,48>
<47,48>
ISUMP_IA
ISUMN_IA
1U_0402_10V6K
PR662
1
@U42 PC677
@
680P_0603_50V7K
1
RF@ PC678
1 2
<47> FCCM_GT
2
0_0402_5%
2
A A
1 2
<47> PWM_GT
@ PR664
@U42 PR671 0_0402_5%
0_0402_5%
<47,48> FCCM_IA 1 2
@U42 PR692 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
0_0402_5%
1 2 Title
<47> PWM2_IA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR_VCORE_ISL95857
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 48 of 58
5 4 3 2 1
4
+VCC_CORE
22U_0603 * 6 pcs +1U_0201*5 pcs
VCC_GT_+VCC_CORE Place on CPU
+VCC_GT_+VCC_CORE
+330u_D2*2 pcs
22U_0603 * 33 pcs +1U_0201*31 pcs
VCC_CORE Place on CPU
Vinafix.com
A
A
2 1 2 1 2 1
1
+
330U_D2_2.5VM_R9M
PC1099 PC1083 PC1076
PC1127
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
1
+
330U_D3_2VM_R6M
PC1062 PC1095 PC1030 PC1081 PC1078
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
2 1
1
+
220U_D7_2VM_R4.5M
PC1094 PC1031 PC1080 PC1077
@U42 PC1321
PC1326 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
for U42
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1096 PC1032 PC1082 PC1079
(U22)
PC1325 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1090 PC1033 PC1067 PC1001
PC1324 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1093 PC1034 PC1072 PC1002
PC1323 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1091 PC1035 PC1069 PC1003
PC1322 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1097 PC1036 PC1074 PC1004
+330u_D2*2 pcs+220u_D7*1 pcs
22U_0603 * 33 pcs +1U_0201*31 pcs
VCC_CORE Place on CPU
PC1327 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
follow intel spec
22U_0603_6.3V6M 2 1 2 1 2 1 2 1
B
B
2 1
PC1092 PC1037 PC1070 PC1005
PC1330 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1098 PC1038 PC1061 PC1006
PC1331 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1050 PC1039 PC1071 PC1007
PC1332 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1051 PC1084 PC1066 PC1008
PC1333 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
2 1
PC1052 PC1086 PC1073 PC1009
PC1334 1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1 2 1 2 1
PC1053 PC1085 PC1068 PC1010
(U42)
for U42
1U_0201_6.3V6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PC1088 PC1075 PC1011
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
PC1087 PC1064 PC1012
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
PC1089 PC1065 PC1013
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
C
C
22U_0603*12 pcs + 1U_0201*7 pcs
VCC_SA Place on CPU (U22/U42)
+VCC_GT
+330u_D2*2 pcs
22U_0603 * 19 pcs +1U_0201*14 pcs
VCC_GT Place on CPU (U22)
2 1 2 1 2 1
2
1
+
PC1128 PC1040 PC1133 PC1014
+VCC_SA
330U_D2_2.5VM_R9M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
+
PC1063 PC1041 PC1137 PC1015
330U_D3_2VM_R6M 1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
@
PC1042 PC1129 PC1016
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
@
2 1 2 1 PC1043 PC1132 PC1017
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
D
D
PC1153 PC1057 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
@
2 1 2 1 PC1044 PC1136 PC1018
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1147 PC1058 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 PC1045 PC1134 PC1019
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1148 PC1059 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
2 1 2 1 PC1046 PC1135 PC1020
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1149 PC1060 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
@
2 1 2 1 PC1047 PC1138 PC1021
DELL CONFIDENTIAL/PROPRIETARY
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
Date:
Size
Title
PC1150 PC1139 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
@
2 1 2 1 PC1048 PC1027 PC1022
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
Wednesday, December 20, 2017
Document Number
PC1151 PC1140 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
@
2 1 2 1 PC1049 PC1028 PC1023
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
Compal Electronics, Inc.
PC1152 PC1141 2 1 2 1 2 1
1U_0201_6.3V6M 22U_0603_6.3V6M
PROCESSOR DECOUPLING
2 1 PC1055 PC1130 PC1024
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
LA-F311P
PC1142 2 1 2 1 2 1
22U_0603_6.3V6M
2 1 PC1056 PC1029 PC1025
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1143 2 1 2 1 2 1
22U_0603_6.3V6M
for U42
2 1 PC1328 PC1131 PC1026
E
1U_0201_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
Sheet
PC1144 2 1
22U_0603_6.3V6M
2 1 PC1329
1U_0201_6.3V6M
PC1145
49
22U_0603_6.3V6M
2 1
of
PC1146
22U_0603_6.3V6M
58
R ev
2.0
1
A B C D
+PWR_SRC_AC
+SDC_IN +CHARGER_SRC
PR901
0.01_1206_1% EMC@ PL901
1UH +-20% 6.6A 5X5X3 MOLDING, A.3
1 4 2 1
2 3 +PWR_SRC
2200P_0402_50V7K
0.1U_0402_25V6
10U 25V K X6S 0805
10U 25V K X6S 0805
10U 25V K X6S 0805
10U 25V K X6S 0805
15U_B2_25VM_R100M
1
Vinafix.com
@EMC@ PC902
@EMC@ PC903
SMF4L22A SOD123FL-2
1
+
PC911
PC904
PC905
PC906
PC909
@ PJP901
1 2
2
2
PD906
1 PAD-OPEN 4x4m 1
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
15U_B2_25VM_R100M
1
1
+
PC913
PC914
PC915
PC916
PC921
@ E9 delete 15uF*2
2
2
10U_0805_25VAK
10U_0805_25VAK
PR909 PR910
1
PC952
PC951
2 +-1% 0603 2 +-1% 0603
2
CSIN_ISL9538
PC925
CSIP_ISL9538
4.7U 6.3V M X5R 0402
2200P_0402_50V7K
1 2
1U_0402_25V6K
1U_0402_25V6K
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_25V6
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
1U 25V K X5R 0402
1U 25V K X5R 0402
1
PC960
PC961
PC962
@EMC@ PC928
@EMC@ PC929
@EMC@ PC956
@EMC@ PC957
@EMC@PC958
@EMC@PC959
1
1
PC926
PC927
2
2
RF@
RF@
RF@
2
PC930
+PWR_SRC +SDC_IN
PR943
PD901 0.22U_0603_25V7K
1
2 1 1 2 ADP_ISL9538
RF reserved
SDMK0340L-7-F_SOD323-2~D
0_0603_5%
1
PD903
1
PR944
2 1 442K_0402_1% PR914
+VBUS_DC_SS 0_0603_5%
2 2
2
RB520SM-30T2R_EMD2-2
2
ACIN_ISL9538
CSIP_ISL9538
CSIN_ISL9538
BOOT1_ISL9538
UG1_ISL9538
LX1_ISL9538
LG1_ISL9538
PD904
1
2 1
+DC_IN_SS
1
PC955 PR945 PR915
UG1_ISL9538
SDMK0340L-7-F_SOD323-2~D 0.1U 25V K X5R 0402 4.7 +-5% 0603
UG2_ISL9538
100K_0402_5%
2
1 2 VDD_ISL9538
2
PR916
2
PU901
16
15
14
13
12
11
10
33
1_0805_5%~D
9
PC931 1U_0603_25V6 S IC ISL9538HRTZ-REV.C-T TQFN32P CHARGER
PQ905 PQ904
ADP
CSIP
ASGATE
CSIN
BOOT1
UGATE1
PHASE1
LGATE1
PAD
1
1 2 DCIN_ISL9538 PC932 AON6962 2N DFN5X6D-8 AON6962 2N DFN5X6D-8
@ PR960
1U_0402_6.3V6K +VCHGR PQ906
2
1 2 17 8 VDDP_ISL9538 2 1 PR917 EMZB08P03V 1P EDFN3X3-8
DCIN VDDP PL902 0.005_1206_1% 1 +PBATT
D1
G1
G1
D1
2 1 VDD_ISL9538 18 7 LG2_ISL9538 2.2UH_PCMB103T-2R2MS_13A_20% 2
0_0402_5% VDD LGATE2
2
1 4 3 5
PC933 PR918 @ PR919 ACIN_ISL9538 19 6 LX2_ISL9538 7 1 2 7
1U_0402_6.3V6K 0_0402_5% ACIN PHASE2 D2/S1 D2/S1 2 3
100K_0402_1%
1 2 OTGEN/CMIN 20 5 UG2_ISL9538
4
OTGEN/CMIN UGATE2 PC934 PR921
G2
G2
S2
S2
S2
S2
S2
S2
LX1_ISL9538
LX2_ISL9538
1
ACAV_IN1 @ 1
PR920 2 21 4 BOOT2_ISL9538 2 1 2 1
10U_0805_25V6K
10U_0805_25V6K
<32,41> PBAT_CHARGER_SMBDAT SDA BOOT2
1
4.7_1206_5%
4.7_1206_5%
3
3
1
@ 1PR922 2 0_0402_5% 22 3
@EMC@ PR923
@EMC@ PR924
PQ909 0.22U_0603_25V7K 2.2_0603_5%
4700P_0402_25V7K
<32,41> PBAT_CHARGER_SMBCLK SCL VSYS
1
1
D
PC935
PC936
DMN65D8LW-7_SOT323-3 PR925
OTGPG/CMOUT
2
2 1 PR926 2 PROCHOT#_ISL9538 23 2 CSOP_ISL9538
PC937
154K_0402_1%
LG1_ISL9538
LG2_ISL9538
<12,32,47> PROCHOT# 0_0402_5% PROCHOT# CSOP
AMON/BMON
<32> AC_DIS G @
1SNUB_CHG1 2
1SNUB_CHG2 2
2
1
CSON_ISL9538
BATGONE
S <51> PROCHOT#_ISL9538
24 1
3
1
0_0402_5% ACOK CSON @
BGATE_ISL9538
BGATE
PR929
CMOP
PROG
PSYS
VBAT
@ @
1 PR928 2 ACOK_ISL9538 1 2
680P_0603_50V7K
680P_0603_50V7K
PR927
2
1M_0402_1% @ PR930 PC938 +PWR_SRC
25
26
27
105K +-1% 0402 28
29
30
31
32
0_0402_5% 100K_0402_1% 0_0402_5%
@EMC@ PC940
@EMC@ PC941
10P_0402_50V8J
PR931 1 2 1 2 1 2
PR932 1
BGATE_ISL9538
<32,41> PBAT_PRES# 100K_0402_1%
2
3
1 2 @ PC939 0.1U_0402_25V6 3
PR933
VBAT1_ISL9538
100K_0402_1%
1 2
+3.3V_ALW
2
@ PR951
1 2
<51> CMOUT
0_0402_5% COMP_ISL9538
1 2
499 +-1% 0402
1
PR934
560P_0402_50V7K
@ PR947 @ PC942 1U 25V K X5R 0402
1
@
0.1U_0402_25V6
1
1 2
@ PC943
0_0402_5% PR936
12.7K +-1% 0402
1
PC947
@ PR948
0_0402_5%
2
PC945 PR937 1 +-1% 0603
2
PR948 @U42
0.01UF 25V K X7R 0402
2
1
1
PC944
1U 25V K X5R 0402 PR938 1 +-1% 0603
2
1 2
2
@ PR935 @ PR950 LM393_P
0_0402_5% 0_0402_5%
2
SD034118280 1 2 1 2
11.8K +-1% 0402 I_SYS <32,47>
I_BATT
PC946 0.22U 25V K X5R 0402
PD905
BAT54CW_SOT323-3 PC949
@ PR939
0.1U_0402_10V7K
1 2 3 1 2
I_ADP
<24,51> AC1_DISC#
PR948 @U22 MC74VHC1G08DFT2G SC70 5P AND
I_BATT <32> 0_0402_5% 1 PU903
5
I_ADP <32> +PBATT 1 2 2 1 @ PR946
P
<32,41,51> HW_ACAVIN_NB PR942 B <32> ACAV_IN
2 1 4 1 2
ACAV_IN1
1 2 2 Y
Close to EC ADP_I pin 0_0402_5% A
G
1
1
SD034127280 PR940
0_0402_5%
2
100_0402_1% @ PR941 @ PR953
4
12.7K +-1% 0402 4
3
@ PC950 0_0402_5%
100K_0402_1%
PR961
0.1U_0402_25V6
100K_0402_1%
1
Add PR953 for IT8010 voltage leakage issue
2
@ DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL P59 PWR-Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F311P
Date: Wednesday, December 20, 2017 Sheet 50 of 58
A B C D
5 4 3 2 1
PD1202
S SCH DIO 5A 100V 15UA 0.88V TO227-3
2
1
DCIN_AC_Detector 3
@ PC1201
0.01U_0402_25V7K~D
1 2
S4 S5
Vinafix.com
+3.3V_VDD_DCIN PD1801
+DC_IN +3.3V_VDD_DCIN 3 +3.3V_VDD_DCIN PQ1213 +VBUS_DC_SS PQ1202
EMZB08P03V 1P EDFN3X3-8 EMZB08P03V 1P EDFN3X3-8
1 LM393_P 1 1
+AC_IN 2 2
D 2 3 5 5 3
+SDC_IN D
+3.3V_VDD_PIC
1
1500P_0402_50V7K
0.47U 25V K X7R 0603
AO3409 P-CHANNEL SOT-23
AO3409 P-CHANNEL SOT-23
BAT54CW-7-F SOT-323 PR1251 PR1202
PQ1203
PR1203 300K +-5% 0402
499K +-1% 0402
300K +-5% 0402
1
1.8M_0402_1%
499K +-1% 0402
1
3
S S
PQ1215
1 2
PC1202
PR1205
PC1203
2PR1207
2
2
+3.3V_VDD_PIC
G G
PR1206 2 2
2
1K_0402_1%
2
1
+3.3V_VDD_PIC
LM393_P
240K_0402_1%
D D
1
1
1
PR1252
102K_0402_1%
2
PR1253 PR1209
PR1201
100K_0402_5%
PR1208
100K_0402_5% 100K_0402_5%
DMN65D8LDW-7_SOT363-6
6 2
PU1201A
1
49.9K +-1% 0402
2
2
8
LM393DGKR_VSSOP8 PR1214
PR1213
1
3
49.9K +-1% 0402
100K_0402_5%
+ P HW_ACAVIN_NB
3
PQ1214A
(>17.6V) 1
PR1212
2 O HW_ACAVIN_NB <32,41,50,51> EN_PD_HV_1# 2 @
DMN65D8LDW-7_SOT363-6
PR1218
3 2
2
-
G
PQ1204B
DMN65D8LDW-7_SOT363-6
3
5 1 2
1200P_0402_50V7K
23.2K +-1% 0402
100P_0402_50V8J~D
220P_0402_50V8J~D
2
1
@
84.5K_0402_1%
DMN65D8LDW-7_SOT363-6
<32,51> VBUS1_ECOK PR1220
1
PQ1214B
PQ1201B
PR1219
PC1205
PC1206
<24,51> EN_PD_HV_1
4
VBUS1_ECOK 0_0402_5%
6
5 1 2 5
PR1217
PC1207
DMN65D8LDW-7_SOT363-6
2
PQ1201A
DMN65D8LDW-7_SOT363-6
2
4
0_0402_5%
1
2
2
6
PC1204
1
0.1U_0402_10V7K PR1222 @
+3.3V_VDD_PIC 100K_0402_5% PR1223
PQ1204A
2 1
2
2 1 2 AC_DISC# <32,41,51>
PR1210 @ PR1254
1
1M_0402_5% 0_0402_5% @
1
2 1 1 2 PR1216 0_0402_5%
PU1200 0_0402_5%
PR1211
1
@ 0_0402_5% MC74VHC1G08DFT2G SC70 5P AND
1 2 1
P
<24,51> EN_PD_HV_1
2
B 4
1 2 2 O PR1262
(From TI GPIO1) A
G
100K_0402_1%
2
3
0_0402_5%
@ PR1215
C C
PQ1205
@ DMN65D8LW-7_SOT323-3
PR1221
D
<32> DCIN1_EN 1 2 3 1
0_0402_5%
G
2
1
100K_0402_5%
2
100K_0402_5%
1
@
PR1226
PR1225
PR1224
@ PJP1202 0_0402_5%
2
1 2
1
1 2
2
JUMP_43X118 +3.3V_ALW +3.3V_ALW
EMI Part
2
+TBTA_Vbus_1 PQ1206 S3
2
PL1201 EMC@
5A_Z120_25M_0805_2P EMZB08P03V 1P EDFN3X3-8 +3.3V_VDD_PIC @ PR1235
1 2 1 +3.3V_ALW @ 0_0402_5% 100K_0402_5% @ PR1233
2 100K_0402_5% +3.3V_ALW
PR1242
1
+TBTA_Vbus_1
+TBTA_VBUS 1 2 5 3
1
PL1202 <32,41> VBUS2_ECOK 1 2
5A_Z120_25M_0805_2P
100P_0402_50V8J
2
1 2
100K_0402_5%
EMC@ <32,51> VBUS1_ECOK
4
1
PR1231
1000P_0402_50V7K
1500P_0402_50V7K CMOUT <50>
1
1
@ PR1257
EMC@ PC1208
PR1227
EMC@ PC1216
499K +-1% 0402
2
0_0402_5% 100K_0402_5%
AC_DISC# <32,41,51>
DMN65D8LDW-7 2N SOT363-6
PC1210
PR1228
@ PR1245
2
3
+3.3V_ALW D
2
PQ1210B
1 2 5
2
1500P_0402_50V7K
0_0402_5%
1
6
+3.3V_ALW
PQ1211A
DMN65D8LDW-7 2N SOT363-6
DMN65D8LDW-7 2N SOT363-6
D D D S
4
1
2 5 2
PQ1211B
PR1234 G G G
PC1217
@ PR1255 100K_0402_5%
PC1209 can't over 1000P
2
2
150K_0402_1% S S S
2
PQ1210A
@
DMN65D8LDW-7 2N SOT363-6
PR1259 PROCHOT#_ISL9538 <50>
100K_0402_5% +3.3V_ALW
PQ1208A
DMN65D8LDW-7 2N SOT363-6
@ PR1260 D
1
0_0402_5% 2 D
B B
DMN65D8LW-7_SOT323-3
<24,51> EN_PD_HV_1 +3.3V_ALW
PQ1216
1 2 G 2
2
DMN65D8LDW-7 2N SOT363-6
G
PR1244
1
3
+TBTA_Vbus_1 +3.3V_VDD_PIC
PQ1208B
@ D S PR1230 S
3
2
1 2 5
S3 OVP <24,50> AC1_DISC#
G
100K_0402_5%
@ PD1205 PR1229 PR1232
1
SDMK0340L-7-F_SOD323-2 49.9K +-1% 0402 0_0402_5%
S 100K_0402_5%
2
4
1
1 2 +3.3V_VDD_PIC @ PR1261
100K_0402_1%
6
0_0402_5% D
@ PR1238
1 2 2 PQ1207A
@ PR1237
1 2 G DMN65D8LDW-7 2N SOT363-6
PR1241
2
3
@ D
2
PR1236 <32,41,50,51> HW_ACAVIN_NB 1 2 5 S
1
0_0402_5%
1
G PQ1207B
150K_0402_1%
100K_0402_5%
1
PR1240 DMN65D8LDW-7 2N SOT363-6
LM393_P 100K_0402_1% PQ1209A 0_0402_5%
PR1239
S
1
4
2 DMN65D8LDW-7_SOT363-6
2
PU1201B
3
1 2
2
1
8
@ LM393DGKR_VSSOP8 @
PR1243
5 @ PR1258
P
+ 7 1 2 5 PQ1209B 0_0402_5%
1200P_0402_50V7K
100P_0402_50V8J
6 O
0.01UF_0402_25V7K
-
G
1
DMN65D8LDW-7_SOT363-6
100K_0402_1%
100K +-1% 0402
100P_0402_50V8J
0_0402_5%
1
1
@ PC1211
@ PC1213
4
1
1
@ PR1246
PR1247
@ PC1212
@ PC1214
2
2
2
2
2
OVP set t i ng: 5. 5
V
DMN65D8LW-7_SOT323-3
@ PR1248 PT1
1
D 0_0402_5% PAD~D
LPS_PROTECT#
PQ1212
2 1 2
G
1
S
PR1250 (From EC)
3
PR1249 @
10K_0402_5% 1 2 EN_PD_HV_1 <24,51>
A A
2
0_0402_5%
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TypeC_PD
Size Document Number Re v
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-F311P
Date: Wednesday, December 20, 2017 Sheet 51 of 58
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )
Item Page# Title Date Request Issue Solution Rev.
Owner Description Description
2017
1 57 VCC_CORE 06/07 Compal Change DrMOS from TI to Fairlchild PU610/ PU612/ PU613 change to FDMF3035 (SA0000AHX00) X01
VCORE_VGT,VSA
50
51
52
Vinafix.com Add PC315, PC314,
PC142, PC143,
PC960, PC961, PC962, PC700, PC701,
2 +3.3V_ALW, +5V_ALW 2017 RF team request some item
D
53 VCC_CORE 06/12 Larry X01 D
56 VCORE_VGT,VSA Reserved PC316, PC12, PC702, PC141,PC695, PC696,PC224, PC703
57 Charger
59
+3.3V_ALW, +5V_ALW 2017 1. Depop PC133, PC134, PC135, PC136, PC137, PC138, PC139, PC140,
51 VCC_CORE 06/12 Albert EMI need to modify PC689, PC690, PC691, PC692, PC956, PC957, PC958, PC959. X01
3 57 VCORE_VGT,VSA
59 Charger 2. Pop PL901.
1. CPU input MLCC change to 0603 size and change to low noise
2017 MLCC (SE00000X210): PC608, PC612, PC656, PC657, PC658, PC664, PC665,
57 06/12 Compal Change component for acoustic solution X01
59 Charger PC672, PC673, PC674, PC675, PC682, PC683, PC684
4
2. Remove PC917~PC920(10U*4pcs) , add PC921(15U pos cap)
VCC_CORE 2017 Pop 2pcs 100uf (PC606,PC607)
5 57 VCORE_VGT 06/19 Compal Add one more bulk for acoustic solution X01
C C
12 Compal
13
Compal
14 Compal
15
Compal
16
Compal
B B
17 Compal
18 Compal
19
20
21
22
23
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
PWR P.I.R
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Re v
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 2.0
LA-F311P
Date: Wednesday, December 20, 2017 Sheet 52 of 58
5 4 3 2 1
5 4 3 2 1
+1.0V_PRIM
VCCPRIM_1P0 PCH SIO_PWRBTN# 8
Timing Diagram for S5 to S0 mode VCCPRIM_CORE
DCPDSW_1P0
VCCMPHYAON_1P0
VCCAPLL_1P0
PWRBTN#
RSMRST#
PCH_RSMRST#
7
VCCCLK1~6 SIO_SLP_SUS#
VCCMPHYGT_1P0
VCCSRAM_1P0
SLP_SUS# 5
SIO_SLP_S5#
+1.0V_MPHYGT VCCAMPHYPLL_1P0 SLP_S5#
VCCAPLLEBB
SIO_SLP_S4#
9
SLP_S4# 10
SIO_SLP_S3#
+3.3V_ALW +3.3V_ALW_DSW SLP_S3#
Vinafix.com
3
+3.3V_SPI 5 +3.3V_ALW_PCH
VCCDSW_3P3
SLP_A#
SIO_SLP_A#
D VCCST_PWRGD
CPU
+VCC_CORE VCCHDA SLP_LAN#
SIO_SLP_LAN#
11 D
VCCSPI
12 VCCST_PWRGD VCC VCCPRIM_3P3
VCCPGPPA~E
SLP_WLAN#/GPD9
SIO_SLP_WLAN#
+1.0VS_VCCIO VCCRTCPRIM RESET_OUT#
H_CPUPWRGD
VCCIO
6 +1.8V_PRIM SYS_PWROK
16
15 PROCPWRGD +VCC_GT VCCPGPPG
VCCATS PCH_PWROK
PCH_PWROK
PCH_PLTRST#
VCCGT
+RTC_CELL 14
+1.2V_MEM
17 PLTRST#
VDDQ
VCCRTC
VCCST_PWRGD
VCCST_PWRGD
12
0.6V_DDR_VTT_ON
VDDQC
VCCPLL_OC +1.0V_PRIM 6 +1.0V_PRIM_CORE
VCCPRIM_CORE
12 DDR_VTT_CNTL +1.0V_VCCST 11 SIO_SLP_S4# PROCPWRGD
H_CPUPWRGD
15
VCCST TPS22961 PCH_PLTRST#
VCCSTG
VCCPLL 17 PLTRST#
+VCC_SA
VCCSA
PCH_DPWROK
4 DSW_PWROK
+3.3V_ALW
ENVDD_PCH
+LCDVDD G524B1T11 EDP_VDDEN
+PWR_SRC
+1.0V_PRIM_CORE SIO_SLP_SUS# +3.3V_ALW
6 TPS62134
SIO_SLP_LAN#
+3.3V_ALW 11 +3.3V_LAN EM5209VF SLP_LAN#
6 +1.8V_PRIM
RT8097
+5V_RUN
@PCH_3.3V_TS_EN
C C
+5V_TSP LP2301ALT1G GPP_B21
+PWR_SRC
6 3.3V_TS_EN (EC)
+3.3V_RUN
+1.0V_PRIM SY8286
3.3V_CAM_EN#
+3.3V_CAM LP2301ALT1G GPD7
Power Button
EC 5105 1BAT 2AC
11 SIO_SLP_WLAN#
11 ADAPTER
+PWR_SRC
+5V_ALW ALWON
+5V_ALW2
RUN_ON
EC 5105 SYV828
+5V_ALW
+5V_RUN 1BAT
EM5209VF
+PWR_SRC
+3.3V_ALW +3.3V_RTC_LDO
BATTERY SY8288
+3.3V_ALW2 2AC
EM5209VF +3.3V_RUN +3.3V_HDD_M2 +3.3V_ALW
+1.8V_PRIM
SIO_SLP_WLAN#
EM5209VF +1.8V_RUN
PCH_RSMRST# 5
B
+PWR_SRC 7 SIO_SLP_SUS#
+3.3V_ALW
B
SLP_WLAN#_GATE
NMOS PCH_DPWROK
+3.3V_ALW TLV62130 +1.0VS_VCCIO 4 EM5209VF
@PCH_ALW_ON +3.3V_ALW_PCH 5
OR RESET_OUT#
11 +3.3V_WLAN EM5209VF Gate
AUX_EN_WOWL
16
Pop option
+3.3V_SPI
5 SIO_SLP_SUS#
10 SIO_SLP_S4#
SIO_SLP_S5#
9
SIO_SLP_LAN#
11 SIO_SLP_S3# +PWR_SRC
SIO_SLP_A# EN_INVPWR
AO6405 +BL_PWR_SRC 18
+PWR_SRC
12
+VCC_SA IMVP_VR_ON 10 +PWR_SRC
13 +VCC_CORE ISL95857 SIO_SLP_S4#
+VCC_GT +1.2V_MEM VDDQ
SY8210 VTT
DDR
+0.6V_DDR_VTT
PCH_PWROK
12
0.6V_DDR_VTT_ON
A
14 A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
Power Sequence
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Size Document Number Re v
2.0
LA-F311P
Date : Wednesday, December 20, 2017 Sheet 53 of 58
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) LA-F321P
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
Vinafix.com
D D
1 8 CPU (3/14) 2017/03/21 EE Winbond 16MB SPI ROM EOL (change to J-die) Change UC5, UC6 to SA00005VV20 0.1(X00)
2 8 CPU (3/14) 2017/03/21 ME JSPI1 connector change vendor Change JSPI1 to SP010022Q00 0.1(X00)
3 11 CPU (6/14) 2017/03/21 EE KBL-R U42 X'tal Add RC415~RC420,CC334,CC335,YC3 0.1(X00)
4 13 CPU (8/14) 2017/03/21 EE KBL-R CRB schematic Add RC436 0ohm to GND 0.1(X00)
5 14 CPU (9/14) 2017/03/21 ME JXDP1 connector change vendor Change JXDP1 to SP01001VB00 0.1(X00)
CPU (11/14)
Follow KBL-R_U42_Processor_Line_BGA1356_
6 16 2017/03/21 EE Ballout_Rev1p0 Reserve RC437, RC438 0.1(X00)
7 18 CPU (13/14) 2017/03/21 EE RTC Power Gate Circuit for +3.3V_DSW Add RC431~RC433, RC439, RC440, QC6, QC7 0.1(X00)
8 33 EC MEC5105 2017/03/21 EE RTC Power Gate Circuit for RTCRST Add QE14~QE17, RE540~RE546, RE551, CE63, RC441, RC442, DC1, DC2, RC445 0.1(X00)
C C
9 34 EC MEC5105 2017/03/21 EE Remove IO expander Remove UE2 relating circuit 0.1(X00)
Support
10 28 eDP CONN & 2017/03/21 ESD ESD request Remove DV7, DV8 0.1(X00)
Touch screen
11 35 USH & TPM 2017/03/21 EE TPM NPCT65X and NPCT75X schematic colay UZ12 relating circuit and change UZ12 to SA0000AQ200 0.1(X00)
12 31 NGFF Card 2017/03/21 RF RF request to align w/ BR MLK LI8, LI9 change to SM070003Z00, LI16, LI17 change to SM070003V00 0.1(X00)
13 33 EC MEC5105 2017/03/21 EE RTCRST_ON glitch Reserve CE64 0.1(X00)
14 All All 2017/03/21 EE Port map change JUSB1 change to USB30_port6 and USB20_port9 0.1(X00)
USB20_port1 BOM option to Type-C(PD UT5)
Delete PS8338 and WIGIG circuit and connect DDI2 to UT1
(Pop RT29 and change net name to CPU_DP2_HPD)
15 22 TBT-AR-SP(1/2) 2017/03/21 EE Reserve 0ohm for YT1 Add RT394 0.1(X00)
B DP, PCIE B
16 24 [Type C]PD 2017/03/28 EE Change PD to PD3.0 Change UT5 to SA0000AP500 0.1(X00)
Controller TI
17 9 CPU (4/14) 2017/03/28 EE JUART1 reverse JUART1 pin SWAP 0.1(X00)
EC MEC5105
RE300 change to 130K ohm for 12"
18 33 2017/03/28 EE Panel ID define change RE300 change to 62K ohm for 13" 0.1(X00)
Support
19 34 USH & TPM 2017/03/28 EE Prevent POA_WAKE# ESD Add RZ364 100 ohm to POA_WAKE# 0.1(X00)
20 34 USH & TPM 2017/03/28 EE Prevent Contactless_det# backdrive Add DZ8 0.1(X00)
[Type C]USB3.0
Change DT7, DT8, DT11, DT12 to DT39
21 26 2017/03/28 ESD ESD request Change DT15, DT16, DT19, DT20 to DT40 0.1(X00)
CONN
22 11 CPU (6/14) 2017/03/28 EE RTC Power Gate Circuit option Add RC441, RC442, DC1, DC2, RC445 0.1(X00)
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
EE P.I.R (1/5)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 2.0
LA-F311P
Date: Wednesday, December 20, 2017 Sheet 54 of 58
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) LA-F311P
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
Vinafix.com
D D
23 All All 2017/03/28 EE GPIO map change PCH_RSMRST#_GPIO204 -> USH_PWR_STATE# (delete RE363) 0.1(X00)
PORT80_DET# -> DCIN1_EN (delete RE512,RE513,RZ131)
SHD_IO3 -> VBUS1_ECOK
SHD_IO1 -> SATA_LED_EN
ENVDD_PCH -> DCIN2_EN
SIO_RCIN#_EC -> VBUS2_ECOK and delete RE339/RC13
USH_SMBCLK -> USH_EXPANDER_SMBCLK
USH_SMBDAT -> USH_EXPANDER_SMBCLK
Delete RTCRST_ON_GPIO141
PRIM_PWRGD_GPIO024 -> RESET_IN#
3.3V_TS_EN rename to PCH_3.3_TS_EN
SHD_IO0 change to 3.3V_TS_EN and delete RE366 and PU 100K RE547
Add RV323/RV324 for 3.3V_TS_EN/PCH_3.3V_TS_EN option
24 22 TBT-AR-SP(1/2) 2017/03/30 EE Intel review RT39 change to 4.75K_0402_0.5% 0.1(X00)
DP, PCIE
25 All All 2017/03/30 EE GPIO map change PANEL_ID -> SYSTEM_ID 0.1(X00)
SHD_IO1 -> SATA_LED_EN -> MASK_SATA_LED#
C EXPANDER_GPU_SMDAT -> VCCDSW_EN_GPIO and delete RE524 C
EXPANDER_GPU_SMCLK -> free and delete RE525
THERMATRIP1# -> THERMTRIP1#
THERMATRIP2# -> THERMTRIP2#
SIO_EXT_SCI#_EC -> free and delete RE341
FAN1_TACH -> TACH_FAN1
LCD_TST -> free
WWAN_RADIO_DIS# -> LCD_TST
EC GPIO123 (UE1.F12) -> WWAN_RADIO_DIS#
DCIN3_EN -> EC GPIO202 (UE1.J6) (SBMLK 12/13 only)
FAN1_PWM -> PWM_FAN1
PS_ID -> free
SHD_CLK -> PS_ID and delete RE374
AUD_NB_MUTE# -> NB_MUTE#
26 All All 2017/03/30 EE GPIO map change UE1.B1 -> add net name 3.3V_ALW2 and depop RE57 (Microchip suggest) 0.1(X00)
RESET_IN# -> Remove RE361 (Microchip suggest)
SLOT2_CONFIG_3 -> NGFF_CONFIG_3
ME_FWP -> ME_FWP_PCH
B ME_FW_EC -> ME_FWP B
HW_GPS_DISABLE# -> GPS_DISABLE#
VGA_ID -> BEEP
H_PROCHOT# -> PROCHOT#
USB_PWR_SHR_VBUS_EN -> USB_POWERSHARE_VBUS_EN
USB_PWR_SHR_LFT_EN# -> USB_POWERSHARE_EN#
SIO_EXT_SMI#_EC -> free and delete RE338
CLKRUN#_EC -> ENABLE_DS# and delete RE337 and add RE549, RE550
SHD_IO2 -> 1.8V_PRIM_PWRGD and delete RE360
BEEP -> VGA_IDENTIFY (rename from VGA_ID)
SHD_CS# -> PCH_RSMRST# and delete RE364
SLOT2_CONFIG_0 -> NGFF_CONFIG_0
SLOT2_CONFIG_1 -> NGFF_CONFIG_1
SLOT2_CONFIG_2 -> NGFF_CONFIG_2
ACAV_IN_NB -> HW_ACAVIN_NB
LID_CL#_NB -> LID_CL_SIO#
SYS_PWROK->reserved 0ohm RE548 and add netname to RESET_OUT
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
EE P.I.R (2/5)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 2.0
LA-F311P
Date: Wednesday, December 20, 2017 Sheet 55 of 58
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) LA-F311P
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
Vinafix.com
D
All
NGFF3 (SSD 4 Lane) add PCIE port 9 and port 10 D
27 All 2017/03/30 EE Port map change LOM change to PCIE port 4 0.1(X00)
11 CPU (6/14)
Add RC443, RC444 for SUSACK#, ME_SUS_PWR_ACK
28 32 2017/04/05 EE Intel PDG for DSx and NonDSx Add BOM structure DS3@ for RE349 and RE536 0.1(X00)
EC MEC5105
17 CPU (12/14)
29 40 2017/04/05 EE PCH_PRIM_EN net name change Change net name from SIO_SLP_SUS# to PCH_PRIM_EN 0.1(X00)
Power control
30 33 EC MEC5105 2017/04/05 EE Microchip suggest Change RE71 to 10 ohm 0.1(X00)
Support
Power control
+5V_RUN discharge circuit for
31 40 2017/04/05 EE S3 no power issue Add QZ4 and RZ370 0.1(X00)
PAD, LED
Add bracket CLIP1 CLIP_14P0X2P6
32 39 2017/04/05 ME Add bracket Add bracket CLIP2 CLIP_7P7X4P2 0.1(X00)
33 33 EC MEC5105 2017/04/11 EE +5V_RUN for FAN Change DE1 to SC400002J00 0.1(X00)
Support
Power control
EC request to reseve OR gate for
34 40 2017/04/14 EE WLAN power EN Reserve DZ9 0.1(X00)
C C
35 33 EC MEC5105 2017/04/14 EE EC request to reseve ESPI_RESET# for JESPI Reserve RE560 0.1(X00)
Support
36 32 EC MEC5105 2017/04/14 EE Schmatic align Add GPU_SMCLK/GPU_SMDAT PU to RPE12 0.1(X00)
37 11 CPU (6/14) 2017/04/14 EE WIGIG feature remove Add back RC50 and depop 0.1(X00)
38 31 CodeC ALC3246 2017/04/14 EE Realtek request CA54 change back to 10pf and depop 0.1(X00)
39 32 EC MEC5105 2017/04/14 EE RTC power Gate circuit rev.2 (0411) Delete RE540, RE542, RE544, RE545, QE14, QE16 0.1(X00)
11 CPU (6/14) Change RE543 to 1M ohm and RE546 to 10K ohm
Add DE2, CE65,
Reserve CE66 for VCCDSW_EN
40 11 CPU (6/14) 2017/04/14 EE RTC Power Gate Circuit option (0411) RC445 change to connect to VCCDSW_EN and pop 0.1(X00)
41 13 CPU (8/14) 2017/04/19 EE KBL-R CRB schematic Add BOM structure for RC436 U42@ 0.1(X00)
B B
42 All All 2017/04/19 EE GPIO map change RC443 BOM structure change to @ 0.1(X00)
GPIO126->GPU_PWR_LEVEL
Add RTCRST_ON_R net neme for QE17.2
Add SIO_SLP_SUS#_R net name and PU RE561
SYS_LED_MASK#->LED_MASK#
RC27.2->NC for CLKRUN#
HDD_DET#->SATAGP0
Add RV326 and depop RC282/RE547 for 3.3V_TS_EN/PCH_3.3V_TS_EN
43 34 USH & TPM 2017/04/19 EE TPM change to NPCT650x Change UZ12 to SA00008EL80 and related resistors 0.1(X00)
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
EE P.I.R (3/5)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 2.0
LA-F311P
Date: Wednesday, December 20, 2017 Sheet 56 of 58
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) LA-F311P
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
Vinafix.com
D D
44 32 EC MEC5105 2017/04/19 EE Dell request to add test point for Add test point T141 for UE1.D1->GPIO051 0.1(X00)
EC free pins Add test point T142 for UE1.L11->GPIO054
Add test point T264 for UE1.F13->VBUS3_ECOK
Add test point T143 for UE1.K7->GPIO011
Add test point T144 for UE1.M1->GPIO100
Add test point T262 for UE1.J6->DCIN3_EN
Add test point T147 for UE1.M4->GPIO013
45 All All 2017/04/20 EE GPIO map change GPIO013 net name change to DGPU_PWROK 0.1(X00)
UPD1_ALERT#->UPD1_SMBINT#
UPD1_SMBUS_ALERT#->UPD1_SMBINT#_R
46 11 CPU (6/14) 2017/04/20 EE Schematic align INTRUDER# PU change to +RTC_CELL_PCH 0.1(X00)
47 32 EC MEC5105 2017/04/26 EE GPIO map change UPD2_ALERT#->UPD2_SMBINT# 0.1(X00)
48 11 CPU (6/14) 2017/05/03 EE CLKREQ align Pop RC50 0.1(X00)
C C
Power control
EC request to reseve OR gate for Add QZ15 and RZ518
49 40 2017/06/02 EE WLAN power EN Add SLP_WLAN#_GATE net and RE552 to UE1.K10 0.2(X01)
50 24 [Type C]PD 2017/06/02 EE PD ROM main source change UT6 change to SA000095R10 (GD) 0.2(X01)
Controller TI
51 11 CPU (6/14) 2017/06/02 EE Schematic align Reserve RC551 for SUSACK#_R 0.2(X01)
USH & TPM
Nuvoton request to change TPM_PIRQ# power rail
TPM_PIRQ# power rail change to +3.3V_ALW_PCH
52 34 2017/06/02 EE TPM change to NPCT750 Change UZ12 to SA0000AQ200 and related resistors and CZ75 change to 10U 0.2(X01)
All
DI1,DI4,DT39,DT40 change to SC300001Y00
53 All 2017/06/02 ESD Main source change DI2,DI5 change to SCA00000T00 0.2(X01)
DA2 change to SCA00001A00
DT4 change to SCA00002Q00
All
DA8, DC1, DC2, DE2, DZ1, DZ2, DZ5-DZ8 footprint
54 All 2017/06/02 EE DFX request change to AZ5125-01HPR7G_SOD523-2 0.2(X01)
55 All All 2017/06/02 EE Dell request to change cap to L-end P/N L-end P/N for all cap 0.2(X01)
B B
56 31 CodeC ALC3246 2017/06/12 EE DFX request LA13 footprint change to TAI-T_HCB2012KF-121T50_2P 0.2(X01)
USH & TPM
Add CZ76/CZ77 (12pf/68pf) for +3.3V_RUN of UZ12
57 34 2017/06/12 RF RF request Add CZ78 (100pf) for +PWR_SRC of JUSH1 0.2(X01)
58 33 EC MEC5105 2017/06/12 EE Board ID Change RE79 to 130Kohm (rev. X01) 0.2(X01)
Support
CPU (4/14)
Add TypeC_CON_SEL1/TypeC_CON_SEL2 for UC1.W4/UC1.AB3
59 9 2017/06/14 EE GPIO map change Reserve RC553-RC556 for connector selection 0.2(X01)
Power control
EC request to reseve OR gate for
60 40 2017/06/14 EE WLAN power EN Change QZ15 to SB00000T000 0.2(X01)
61 39 PAD, LED 2017/06/14 EMI Crystal shielding can (YT1) Add CLIP3-CLIP5 0.2(X01)
62 31 CodeC ALC3246 2017/06/15 RF RF request Reserve CA78 for +5V_RUN_AUDIO 0.2(X01)
63 24 [Type C]PD 2017/06/21 EE PD change to rer.C UT5 change to SA0000AX700 0.2(X01)
Controller TI
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
EE P.I.R (4/5)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 2.0
LA-F311P
Date: Wednesday, December 20, 2017 Sheet 57 of 58
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )
LA-F311P Request
Item Page# Title Date Owner Issue Solution Rev.
Vinafix.com Description Description
D D
64 39 PAD, LED 2017/07/31 EMI Crystal shielding can (YT1) Add SHDCAN and remove CLIP13-CLIP15 0.3(X02)
27 eDP CONN Reserve RV400, CV635 for QV8
65 32 EC MEC5105 2017/08/04 EE Reserve soft start solution Reserve CZ200, RZ380 for QZ1 0.3(X02)
CPU (13/14)
18 Reserve CC340 for QC7
Reserve RE565 for QE15
66 31 CodeC ALC3246 2017/08/04 RF RF request to pop CA54 for 2MHz/4MHz noise Change CA54 to 82pf and pop 0.3(X02)
67 33 EC MEC5105 2017/08/07 EE Board ID Change RE79 to 62Kohm (rev. X02) 0.3(X02)
Support
68 9 CPU (4/14) 2017/08/09 EE TPM_PIRQ# GPIO map change Add RC560 and reserve RC561 to TPM_PIRQ# 0.3(X02)
69 33 EC MEC5105 2017/09/15 EE Board ID Change RE79 to 4.2Kohm (rev. A00) 1.0(A00)
Support
70 12 CPU (7/14) 2017/09/15 EE ME SW depop Depop RC222, SW1, RC221 change to 0 ohm short pad 1.0(A00)
C C
71 34 USH & TPM 2017/09/15 EE TPM change to MP version UZ12 change to SA0000AQ220 1.0(A00)
72 9 CPU (4/14) 2017/09/15 EE GPIO map change Depop RC330, RC331 1.0(A00)
73 8 CPU (3/14) 2017/09/15 EE Add solder mask Add UC6 -NPM 1.0(A00)
74 All All 2017/09/15 EE 0 ohm change to short pad 0 ohm change to short pad 1.0(A00)
75 All All 2017/09/15 EE Only support DS3 (0 ohm change to short pad) Only support DS3 (0 ohm change to short pad) 1.0(A00)
21 HDMI CONN
76 30 2017/09/18 EE DFX request Add LV3,LV6,LV9,LV12 RI27,RI28,RI29,RI30,RI47,RI48,RI49,RI50 -NPM 1.0(A00)
NGFF card
77 25 [Type C]PD Power 2017/10/03 EE X1 Code DT1,DT2,DT3 Change from SC1N4148180 to SC100005500 1.0(A00)
B 78 28 LAN Clarkvillie 2017/10/03 EE Not completely replaced with DAZ40 LL1 Change from SHI0000IY00 to SHI0000K000 1.0(A00) B
& RJ45
79 24 [Type C] 2017/11/10 EE Main vendor EOL CT74,CT83 Change from SE00000OU00 to SE00000QL10 1.0(A00)
PD Controller TI
80 24 [Type C] 2017/11/10 EE PD just change part number UT5 Change from SA0000AX700 to SA0000BIJ00 1.0(A00)
PD Controller TI
81 39 PAD, LED 2017/12/08 EE SW3 main source change SW3 main source change from SN111005800 to SN100005800 1.0(A00)
82 17 CPU (12/14) 2017/12/08 EE WHEA BSOD Intel request CC202 change to 22uf for 4+2 CPU, but keep 1uf for 2+2 CPU 1.0(A00)
83 17 CPU (12/14) 2017/12/20 EE WHEA BSOD Add CC341 22uf 0603,Depop CC202 22uf 0402 2.0(A01)
84 33 MEC5105 support 2017/12/29 EE Board ID Change RE79 to 2Kohm (rev. A01) 2.0(A01)
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
EE P.I.R (5/5)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 2.0
LA-F311P
Date: Friday, December 29, 2017 Sheet 58 of 58
5 4 3 2 1
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