UNIT 4 INTERFACING USING 8085 MICRO PROCESSOR

 INTERFACE is the path for communication between two components. Interfacing is of two
types, memory interfacing and I/O interfacing.

 MEMORY INTERFACING :

When we are executing any instruction, we need the microprocessor to access the memory for
reading instruction codes and the data stored in the memory. For this, both the memory and the
microprocessor requires some signals to read from and write to registers. The interfacing process
includes some key factors to match with the memory requirements and microprocessor signals.
The interfacing circuit therefore should be designed in such a way that it matches the memory
signal requirements with the signals of the microprocessor.

 I/O INTERFACING

There are various communication devices like the keyboard, mouse, printer, etc. So, we need to
interface the keyboard and other devices with the microprocessor by using latches and buffers.
This type of interfacing is known as I/O interfacing.

Block Diagram of Memory andI /O Interfacing

 8085 INTERFACING PINS

Following is the list of 8085 pins used for interfacing with other devices –
 A15 - A8 (Higher Address Bus)
 AD7 - AD0(Lower Address/Data Bus)
 ALE
 RD
 WR
 READY
(Note: Explanation of all the above pins are available in Unit-1 notes)

 WAYS OF COMMUNICATION− MICROPROCESSOR WITH THE OUTSIDE WORLD?

There are two ways of communication in which the microprocessor can connect with the outside
world.
 Serial Communication Interface

 Parallel Communication interface

 Serial Communication Interface − In this type of communication, the interface gets a

single byte of data from the microprocessor and sends it bit by bit to the other system
serially and vice-a-versa.

 Parallel Communication Interface − In this type of communication, the interface gets a

byte of data from the microprocessor and sends it bit by bit to the other systems in
simultaneous (or) parallel fashion and vice-a-versa.

 8257 DMA CONTROLLER

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest rate.
It allows the device to transfer the data directly to/from memory without any interference of the
CPU. Using a DMA controller, the device requests the CPU to hold its data, address and control
bus, so the device is free to transfer data directly to/from the memory. The DMA data transfer is
initiated only after receiving HLDA signal from the CPU.

 How DMA Operations are performed?

Following is the sequence of operations performed by a DMA −

 Initially, when any device has to send data between the device and the memory, thedevice
has to send DMA request (DRQ) to DMA controller.
  The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU toassert
the HLDA.
 Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU
leaves the control over bus and acknowledges the HOLD request through HLDA signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the operations over
buses between the CPU, memory, and I/O device

 Features of 8257

Here is a list of some of the features of 8257 −

 It has four channels which can be used over four I/O devices.
 Each channel has 16-bit address and 14-bit counter.
 Each channel can transfer data up to 64kb.
 Each channel can be programmed independently.
 Each channel can perform read transfer, write transfer and verify transfer operations.
 It generates MARK signal to the peripheral device that 128 bytes have been transferred.
 It requires a single phase clock.
 Its frequency ranges from 250Hz to 3MHz.
 It operates in 2 modes, i.e., Master mode and Slave mode.

 8255A - PROGRAMMABLE PERIPHERAL INTERFACE

The 8255A is a general purpose programmable I/O device designed to transfer the data from I/O to
interrupt I/O under certain conditions as required. It can be used with almost any microprocessor.
It consists of three 8-bit bidirectional I/O ports (24I/O lines) which can be configured as per the
requirement.
 Ports of 8255A

8255A has three ports, i.e., PORT A, PORT B, and PORT C.

 Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
 Port B is similar to PORT A.
 Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-
PC4) by the control word.
These three ports are further divided into two groups, i.e. Group A includes PORT A and upper
PORT C. Group B includes PORT B and lower PORT C. These two groups can be programmed
in three different modes, i.e. the first mode is named as mode 0, the second mode is named as
Mode 1 and the third mode is named as Mode 2.
 Operating Modes:

8255A has three different operating modes −

 Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as two 4- bit ports.
Each port can be programmed in either input mode or output mode where outputs are latched
and inputs are not latched. Ports do not have interrupt capability.
 Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be configured as
either input or output ports. Each port uses three lines from port C as handshake signals. Inputs
and outputs are latched.
 Mode 2 − In this mode, Port A can be configured as the bidirectional port and Port B either in
Mode 0 or Mode 1. Port A uses five signals from Port C as handshake signals for data transfer.
The remaining three signals from Port C can be used either as simple I/O or as handshake for
port B. Fig shows control word of 8255A.
 Features of 8255

The prominent features of 8255A are as follows −

 It consists of 3 8-bit IO ports i.e. PA, PB, and PC.
 Address/data bus must be externally demultiplexed.
 It is TTL compatible.
 It has improved DC driving capability.

 8255 Architecture:

The following figure shows the architecture of 8255A −

Now let us discuss the functional description of the pins in 8255A.
 Data Bus Buffer:

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data bus.
Data is transmitted or received by the buffer as per the instructions by the CPU. Control words and
status information is also transferred using this bus.
 Read/Write Control Logic:

This block is responsible for controlling the internal/external transfer of data/control/status word.
It accepts the input from the CPU address and control buses, and in turn issues command to both
the control groups.
 CS:

It stands for Chip Select. A LOW on this input selects the chip and enables the communication
between the 8255A and the CPU. It is connected to the decoded address, and A0 & A1 are
connected to the microprocessor address lines.
Their result depends on the following conditions –

CS A1 A0 Result

0 0 0 PORT A

0 0 1 PORT B

0 1 0 PORT C

0 1 1 Control Register

1 X X No Selection

 WR:

It stands for write. This control signal enables the write operation. When this signal goeslow, the
microprocessor writes into a selected I/O port or control register.
 RESET

This is an active high signal. It clears the control register and sets all ports in the input mode.
 RD

It stands for Read. This control signal enables the Read operation. When the signal is low,the
microprocessor reads the data from the selected I/O port of the 8255.
 A0 and A1

A1 A0 RD WR CS Result

Input Operation
0 0 0 1 0
PORT A → Data Bus

0 1 0 1 0 PORT B → Data Bus

1 0 0 1 0 PORT C → Data Bus

Output Operation
0 0 1 0 0
Data Bus → PORT A

0 1 1 0 0 Data Bus → PORT A

1 0 1 0 0 Data Bus → PORT B

1 1 1 0 0 Data Bus → PORT D

 These input signals work with RD, WR, and one of the control signals. Following is the table
showing their various signals with their result.

 Intel 8253/54 - Programmable Interval Timer

The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for microprocessors
to perform timing and counting functions using three 16-bit registers. Each counter has 2 input
pins, i.e. Clock & Gate, and 1 pin for “OUT” output. To operate a counter, a 16-bit count is loaded
in its register. On command, it begins to decrement the count until it reaches 0, then it generates a
pulse that can be used to interrupt the CPU.

Difference between 8253 and 8254

The following table differentiates the features of 8253 and 8254 −

8253 8254

Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 - 10 MHz

It uses N-MOS technology It uses H-MOS technology

Read-Back command is not available Read-Back command is available

Reads and writes of the same counter cannot Reads and writes of the same counter can
be interleaved. be interleaved.

Features of 8253 / 54

The most prominent features of 8253/54 are as follows −

 It has three independent 16-bit down counters.
 It can handle inputs from DC to 10MHz.
 These three counters can be programmed for either binary or BCD count.
 It is compatible with almost all microprocessors.

8254 has a powerful command called READ BACK command, which allows the user to check the
count value, the programmed mode, the current mode, and the status of the count
 INTEL 8259A Programmable Interrupt Controller

The 8259A is a programmable interrupt controller designed to work with Intelmicroprocessor 8080
A, 8085, 8086, 8088. The 8259 A interrupt controller can

 Handle eight interrupt inputs. This is equivalent to providing eight interruptpins on the
processor in place of one INTR/INT pin.
 Vector an interrupt request anywhere in the memory map. However, all theeight
interrupts are spaced at the interval of either four or eight location.
 This eliminates the major drawback, 8085 interrupts, in which all interrupts are vectored to
memory location on page 00H.
 Resolve eight levels of interrupt priorities in a variety of modes
 Mask each interrupt request individually.
 Read the status of pending interrupts, in service interrupts, and maskedinterrupts.
 Be set up to accept either the level triggered or edge triggered interruptrequest.
 Mine 8259 as can be cascade in a master slave configuration to handle 64interrupt
inputs.

The 8259 A is contained in a 28-element in line package that requires only acompatible with 8259. The
main difference between the two is that the 8259 A can be used with Intel 8086/8088 processor.