Contenu du Module:

 Intro + Periph Access/Masquage logique

 GPIO (STM32F4): Architecture et programmation par accès registre

 Programmation STM32F4 par utilisation de la couche HAL: GPIO, UART

 Les Interruptions: principe de fonctionnement et programmation

 ML on the Edge: Principe de fonctionnement (MLP, CNN) et Développement et

implémentation d’un modèle Deep Learning sur STM32F4.

 Les périphs : SPI et I2C

 Transfert DMA

 ADC

 Timer

DAMERGI Emir – INSAT 2021 1

Introduction

Emir DAMERGI
INSAT 2020/21
INTRODUCTION:

 Many terms related to embedded systems:

- GPP, DSP, ASIP, SPP, SOC, ASIC, FPGA, SISD, SIMD,
CISC, RISC, etc..

Many terms related to embedded systems:

- GPP, DSP, ASIP, ASIC, FPGA, SISD, SIMD, etc..

DAMERGI Emir – INSAT 2021 3

 INTRODUCTION

Problem Solution:
- Algorithms
(Scientific or Industrial) - Mathematical computing

Processing

Software approach Dedicated Hardware

(standard HW: Instruction Set Processor)

Design of a tailord HW
Processor GPP SPP « Single
DSP Purpose Processor »
ASIP
4
DAMERGI Emir – INSAT 2021
Dedicated Hardware (SPP)

Finite State Machines

Algorithm
Truth/Transition Tables

SPP: DataPath + control Program

(VHDL, Verilog)

SPP: Single Purpose Processor

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 Dedicated Hardware (SPP)

Memory
Data
Inputs Data
Outputs

Control DataPath
Predifiend
control Unit
sequence

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Software approach

Target Platform (Processor) Algorithm

chosen according to the
application constraints:
(GPP, DSP, ASIP)

GPP: General Purpose Processor

Program (C, C++, ASM, …)
memory
Processing
Unit
(Control
+ Binary File
DataPath)

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 Software approach: Processing Unit

Memory
Instructi Data
ons Inputs Data
Outputs

Control DataPath (ALU)

Control sequence
Unit
depends on
Instructions

Code and Data are placed generally in different memories:

• RAM: Data variables.
• Flash: Code and Data constants
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Software approach: Processing Unit
• When Instructions and Data are fetched through the same Bus (Data Bus)
 Von Neuman Architecture

Memory
Control DataPath (ALU)
Unit Code
(Instructions)

Address Bus

Data
C D
O A
D T
E A
Data Bus (Data + Code)

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Software approach: Processing Unit
• When Instructions and Data are fetched through 2 differents Buses:
 HARVARD Architecture

Memory Memory
Control DataPath (ALU)
Code Data
(Instructions) Unit

Address Address
Bus Bus

C D
O A
D T
E A
Code Data

DAMERGI Emir – INSAT 2021 9

Selection Criteria

Criteria 1: (FC = Final Cost per Product)

NRE NRE: Non Recurrent Engineering

FC   UC Cost
Q : Quantity
Q
UC: Unit Cost

Criteria 2 : Time To Market

On-Time Peak
Revenues (R)
Delayed Peak
R (P-D)/P

Product Release Temps

0 D P 2P
Delay
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Selection Criteria

Criteria 3 : Performance

• Number of executed Instructions (resp Floating Operations) per

time unit for 1Mhz Clock Frequency : MIPS/MHz (resp.
MFLOPS/MHz)
• Clock Frequency
 Absolute Performance = Clock Frequency * MIPS/Mhz
• Memory Access Bandwidth (Octets/sec)

ARM Cortex-M0 0.9 MIPS/MHz

ARM Cortex-M3/M4 1.25 MIPS/MHz
ARM Cortex-A5 1.57 MIPS/MHz
ARM Cortex-A7 1.9 MIPS/MHz

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Selection Criteria

Criteria 4 : Power (Energy Consumption)

• Power is expressed in Watt [W]

• Energy is expressed in Joule [J] = Power * Time

Consequences on:
• Battery Lifetime (Ah)  Autonomy
• Heat dissipation  System size and weight

Examples:
PCs: Tens of WATTs
SmartPhones: Watts
MCU: microWatts  MilliWatts

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Selection Criteria

Criteria 5 : Flexibility

How hard it is to make the system evolve or to change

completely his behavior?

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Example
The expression of the form

Is present in a large number of mathematical models

Convolution (Filter): y(k) =

Correlation: c(m)=

Matrix computation

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15
 Example : Execution on GPP
∑ 𝑎 ∗𝑥 = (𝑎 ∗ 𝑥 )+(𝑎 ∗ 𝑥 )+(𝑎 ∗ 𝑥 )+(𝑎 ∗ 𝑥 ) Memory
Ri a0
Rj  x3 𝟎 𝟎 𝟑
Control
Processing Acc = Rj* Ri
Unit
Unit Rk  Rres
Ri Rj Rk Ri a1
Rj  x2
𝟏 𝟏 𝟐
UAL Acc = Rj* Ri
(+,*,-,/, ..) Ri  Rres

Acc Acc = Rj + Rk 𝐪𝟎 + 𝐪𝟏
Rk  Rres
……
……. 𝟐 𝟐 𝟏
……
…… 𝐪𝟎 + 𝐪𝟏 + 𝐪𝟐
𝟑 𝟑 𝟎

𝐪𝟎 + 𝐪𝟏 + 𝐪𝟐 +
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 Example : Execution on GPP
instructions Memory
Ri  a 0
22 instructions:
Rj  x3 𝟎 𝟎 𝟑
4
Rres = Rj* Ri
- 22 instr. fetching from Memory
Rk  Rres
Ri  a 1 - 8 Mem to reg transfers
Rj  x2
4 𝟏 𝟏 𝟐
Rres = Rj* Ri - 7 Reg to Reg transfers
Ri  Rres
- 4 Multiplications
Rres = Rj + Rk 𝐪𝟎 + 𝐪𝟏
2
Rk  Rres - 4 additions
……
4 ……. 𝟐 𝟐 𝟏
……
2 …… 𝐪𝟎 + 𝐪𝟏 + 𝐪𝟐

4 𝟑 𝟑 𝟎

2 𝐪𝟎 + 𝐪𝟏 + 𝐪𝟐 + 𝐪𝟑
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Example : Execution on Dedicated Hardware
)+ )+ )+(

Memory (only data, No instruction) - 8 Mem to reg transfers

a0 , a1, a2, a3
(Parallel)
x0, x1, x2, x3
- 4 (2 Terms) Multiplication
Control
(executed in parallel)
Unit

- 1 (4 Terms) Addition

* * * *

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Example: Performance

GPP Dedicated Hardware

- 22 Instr. Fetch Cycles - 0

- 8 Mem to reg transfer Cycles - 1 Mem to reg transfer Cycle

- 7 Reg to Reg transfer Cycles - 0

- 4 Multiplication Cycles - 1 Multiplication Cycle

- 4 addition Cycles - 1 addition Cycle

--- +++

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Example: Energy

GPP Dedicated Hardware

- 22 Instr. Fetch - 0

- 8 Mem to reg transfers - 8 Mem to reg transfers

- 7 Reg to Reg Transfers - 0

- 4 Multiplications - 4 Multiplications

- 4 additions - 4 additions

--- +++
Furthermore, the GPP controller is more complex and consumes more energy

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Example: Flexibility/Time To market

change the processing to:

GPP Dedicated Hardware

- Very easy: Rewrite the software - Impossible: A new HW design

and compile must be realized

+++ ---

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Example: Criteria comparison
Best ( +++ ) Software Approach
Flexibility / Time To Market

GPP

Dedicated HW (SPP)

SPP

Performance / Power Best ( +++ )

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Example: Tradeoff GPP/SPP

A Trade off between Flexibility and Performance ?

Instructions Specialized
(Processor) Hardware

A Processor with and Specialized Datapath (ALU)

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Example: Tradeoff GPP/SPP

Memory
Instructi Data
ons Data
Inputs Outputs

A Instruction processor
Control Specialized DataPath (ALU)
Unit with support:
- Hardwired Application
Specific instructions
- Parallelization

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Example : tradeoff GPP/SPP

Multiple ALUs
Processing Unit
Parallel procesing
Ri Rj Rk Rl
With 2 ALUs:
Control Unit

ACC Ri * Rj + Rk * Rl
ALU ALU
SIMD: Single Instruction Multiple Data

ADD

ACC MAC : Multiply ACcumulate

ACC  ACC + (Ri * Rj + Rk * Rl)

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Example : tradeoff GPP/SPP
(𝑎 ∗ 𝑥 )+(𝑎 ∗ 𝑥 )+(𝑎 ∗ 𝑥 )+(𝑎 ∗ 𝑥 )
Memory
Ri  a 0
Processing Unit Rj  x3

Ri Rj Rk Rl Rk  a 1
Rl  x2
Control Unit

ACC+ a0 x3+ a1x2

ALU ALU Ri  a 2
Rj  x1
Rk  a 3
ADD
Rl  x0
ACCACC+ a0 x3+ a1x2
ACC ……
…….
……

DAMERGI Emir – INSAT 2021 26

Example : Tradeoff GPP/SPP
(𝑎 ∗ 𝑥 )+(𝑎 ∗ 𝑥 )+(𝑎 ∗ 𝑥 )+(𝑎 ∗ 𝑥 )

Memory
Ri a0 10 instructions:
Rj  x3
Rk a1
- 10 instr. fetching from Memory
Rl  x2
- 8 Mem to reg transfers
ACC a0 x3+ a1x2

Ri a2 - 4 Multiplications (2 Multiply cycles)

Rj  x1
- 2 additions (2 Addition cycles)
Rk a3
- 1 MAC operation
Rl  x0
ACCACC+ a0 x3+ a1x2
……
…….
……
DAMERGI Emir – INSAT 2021 27
 Example : Tradeoff GPP/SPP

Processing Unit The number of ALUs can be

Registers (Data) higher (4, 8, 16 , …)

Control Unit

All ALUs are controlled by

ALU ALU …… ALU the same ctrl signal
 All ALUs execute the
same Instruction

SIMD Architecture: Single Instruction Multiple Data

SIMD Architecture + MAC are found in DSP (Digital Signal Processors)

DAMERGI Emir – INSAT 2021 28

Example: Criteria comparison
Best ( +++ ) Software Approach

GPP
Flexibility / Time To Market

DSP

Dedicated HW (SPP)

SPP

Performance / Power Best ( +++ )

DAMERGI Emir – INSAT 2021 29

Flynn Taxonomy:

SISD Architecture: Single SIMD Architecture: Single

Instruction Single Data Instruction Multiple Data
(Cortex-M3) (Cortex-M4)

PU: Processing Unit (ALU)

DAMERGI Emir – INSAT 2021 30
Flynn Taxonomy:

MISD Architecture: Single MIMD Architecture: Single

Instruction Single Data Instruction Multiple Data

PU: Processing Unit

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What else

Memory • Deep Specialization of

Instruct Data
ions Inputs
Data the core (ALU)
Output
s
• Instruction set tailored
for a Specific Application
Control Application Specific
Unit DataPath (ALU)

ASIP
Application Specific
Instruction Processor

DAMERGI Emir – INSAT 2021 32

Example: Criteria comparison
Best ( +++ ) Software Approach

GPP
Flexibility / Time To Market

DSP

ASIP Dedicated HW (SPP)

SPP

Performance / Power Best ( +++ )

DAMERGI Emir – INSAT 2021 33

SPP: Implementation
SPP

on silicon: Transisitors on FPGA: Logic Blocks

Fixed Architecture (HW) Programmable Architecture (HW)

ASIC: Application Specific SPP on FPGA

Integrated Circuit

DAMERGI Emir – INSAT 2021 34

Example: Criteria comparison
Best ( +++ ) Software Approach

GPP
Flexibility / Time To Market

DSP

ASIP Dedicated HW (SPP)

SPP
on
FPGA
ASIC

Performance / Power Best ( +++ )

DAMERGI Emir – INSAT 2021 35

Choice dilemma: …?
Smart Phone Satellite Receiver
• Flexibility: Update The
GUI, applications…

• Performance: Decryption,
Sound & image decoding,
3G/4G Communications...

GPP, DSP, ASIP, ASIC, FPGA ?

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Choice dilemma : solution
Smart Phone Satellite Receiver
SPP
(HW )
GPP

SPP
(HW )

ASIP

FPGA

SOC: System On Chip

Choice of SOC components guided by the Application

 Single Purpose

DAMERGI Emir – INSAT 2021 37

SOCs: Set-top Box STi5518 OMEGA
ASIP, SPP, FPGA

Embedded processor (GPP)

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SOCs: 4G SOC « Snapdragon »

ASIP

DSP

SPP
(ASIC, FPGA)

Embedded processor (GPP)

DAMERGI Emir – INSAT 2021 39

 General Purpose SOCs: Microcontrollers (MCU)

Memory Program Memory

Applications: (RAM) (Flash, Eeprom)
• IoT
• Domotics Processor BUS
• Home
Entrées /Sorties
appliance Timer(s)
Parallèles
Advanced
• Automobile Convertisseur(s) Communication Peripherals
A/N & N/A série

Basic Peripherals
Tens of MCUnit references per Manufacturer:

CPU: 8 bits  32 bits , x MHz  100’s MHz

Memory: Kbytes  Mbytes
Peripherals: Basic (GPIO, Timers, USARTS)  Advanced (Ethernet, Crypto, ..)

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SoC vs MCU

A Sytem on a chip, also known as an SoC, is an integrated circuit that takes a

single platform and integrates an entire electronic or computer system onto it. It

is, exactly an entire system on a single chip. SoCs are generally designed for a

specific application (SoCs for Smartphones, for Digital Receivers, etc..)

A microcontroller (µc, or MCU for microcontroller unit) is a small computer on a integrated circuit (IC)

chip. It contains one or more CPUs (processor cores) along with memory and programmable

input/output peripherals.

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 SoC vs MCU
The two terms (MCU, SoC) are often used interchangeably. The main difference is that

• A SoC, in addition to standard peripherals embedded in a MCU (Serial, SPI, I2C, USB, Timers,

etc..), typically contains a greater number of onboard advanced peripherals that make it specific to a

given applications Field. And it can be used with minimal number of additional external circuits.

Bluetooth connectivity
embedded

UART
SPI
I2C Bluetooth
Module

STM32F4 MCU STM32WB55 SOC

Using ST MCU (STM32F4) for Using ST SOC (STM32WB55) with

Bluetooth connectivity Bluetooth connectivity (for IoT)

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