Engineering and Applied Science Research 2021;48(1):40-47 Research Article

Engineering and Applied Science Research

https://www.tci-thaijo.org/index.php/easr/index
Published by the Faculty of Engineering, Khon Kaen University, Thailand

Design of power efficient, high-speed 4-bit comparator in UMC 180 nm technology

Sudheer Raja Venishetty* and Anil Kumar Chidra

Department of Electronics and Communication Engineering, Vaagdevi College of Engineering, Warangal, India

Received 27 March 2020

Revised 2 June 2020
Accepted 23 June 2020

Abstract

Power, Area, and Delay are the three important performance metrics used for analyzing any digital circuit. This paper explores different
digital circuit design styles to achieve a better trade-off between the performance metrics. 4-bit Comparator based on 2’s complement
addition principle is designed and implemented using these different digital circuit principles. Full adder and the other components
required to implement 4-bit comparator are designed and implemented using Majority Gate Logic (MGL), Mirror Adder Logic (MAL),
Complementary Pass Transistor Logic (CPL), Transmission Gate Logic (TGL) and Gate Diffusion Input Logic (GDI) for studying
their performance under different stringent conditions of Temperature, Power supply, etc. The circuits are realized in the UMC 180 nm
process using the Cadence Spectre Simulator with a power supply of 1.8 V.

Keywords: Power, Comparator, Performance metrics, Gate diffusion input logic

1. Introduction very high speeds at the cost of low power. Digital comparator is
one such ALU block that has wide applications in the data
Recent advances in the field of electronics made an enormous processing, encryption applications and more specifically
increase in the usage of portable electronic systems. In such types decoding instructions given to a microprocessor-based system or
of portable applications, power dissipation has one of the most decision-based control system. Several architectures have
important design considerations making it to be vital for many derived in the works of literature for implementing a 2-bit or 4-
researchers in the field of integrated circuit design. The concern bit comparator. In [1], a 2-bit comparator is implemented using
about reducing the power dissipation has been increased with the all-n-transistor (ANT) dynamic CMOS logic based on the tree
scaling down of VLSI technologies. The number of transistors or structure. A comparator based on bit-wise competition logic is
gates per given chip area is increasing while the switching energy proposed in [2]. A low power-based style has been used to design
is not decreasing at the same speed and hence the power a comparator in [3]. [4] Proposes a 2-bit comparator based on
dissipation increases making the removal of accumulated heat reversible logic. In [5], 45 nm and 90 nm technologies are used
more difficult and expensive. To overcome this limitation various for designing a comparator in different logic styles. Various high-
design approaches at different levels of abstraction that include speed comparator architectures have been discussed in [6]. [7]
circuit, architectural, or system have been proposed in various Describes a comparator based on multiplexer architecture with a
existing works of literature. single clock operation. [8] and [9] describes various static circuit
Power dissipation in any digital circuit has three major design styles targeted to achieve low power digital circuits with
contributions Dynamic Power-Indicates loss of energy in countable speeds.
charging and discharging of output capacitance while switching This paper presents the performance of different static logic
the output states, Static Power- Usually termed as leakage power styles to achieve low power consumption and high packing
determined by the total leakage current of the circuit under density by designing a 4-bit comparator based on 2’s complement
steady-state conditions and Short Circuit power- Because of addition and the circuits are realized in UMC 180 nm process
current flowing through the input source to the ground during using the Cadence Spectre Simulator with a power supply of 1.8
short circuit conditions. Most of the design approaches are meant V.
for reducing the dynamic power dissipation as it contributes The proposed architecture of a 4-bit comparator based on 2’s
largely to the total power dissipation. In the existing literature, complement addition is discussed in section 2. While section 3
various digital logic techniques like Majority Gate Logic (MGL), describes the architecture of Full-Adder associated with the
Mirror Adder Logic (MAL), Complementary Pass Transistor proposed architecture using different logic styles. Simulation
Logic (CPL), Transmission Gate Logic (TGL) and Gate results and the conclusions are presented in section 4 and section
Diffusion Input Logic (GDI), etc are discussed to achieve the 5 respectively.
required performance.
In the present day high-performance systems like real-time 2. Architecture of 4-bit comparator
Digital signal processors, Microcontroller based systems consist
of high-speed circuits that include ADCs, Filters, etc which Various comparator architectures are discussed in the
require arithmetic and logic operations that should be executed at existing literature for different speeds, power, and circuit

*Corresponding author. Tel.: +9198 6612 3781

Email address: [email protected]
doi: 10.14456/easr.2021.5
Engineering and Applied Science Research 2021;48(1) 41

is applied with ‘1’ at Cin to convert input ‘A’ into twos

complement number. To study the performance metrics of
different digital design techniques, full adder of Figure 1 used in
developing the 4-bit comparator is designed using five design
styles namely Majority Gate Logic (MGL), Transmission Gate
Logic (TGL), Mirror Adder Logic (MAL), Complementary Pass
Transistor Logic (CPL), and Gate Diffusion Input Logic (GDI)
and is discussed.

3. Architectures of full adders (FAs)

The full adder plays a crucial role in designing the digital

circuits that perform various arithmetic operations like addition,
subtraction, multiplication, etc. It is so-called because it adds two
binary digits and a carry-in coming from the lower order stages
to produce Sum and Carry-out. Being the most critical part of
digital circuits involved with multiple operations, which
determines the comprehensive performance of the digital system.
Figure 1 Architecture of 4-Bit Magnitude Comparator Hence designing the FA with less power and the acceptable delay
has been the designer's challenge in the field of VLSI.
Full adder consists of three inputs- two inputs (Say, X, Y)
which are externally applied, and one carry-in (Say Cin) input
coming from the lower order stages producing two outputs- Sum
(Say SUM), representing the addition result of two bits and
Carry-Out (Say Cout), which acts as Cin for higher-order stages.
The operating principle of a full adder is defined by two Boolean
expressions representing each for two outputs and is expressed
as,

SUM = ∑ m(1, 2, 4 7) = A ⨁ B ⨁ Cin (1)

Cout = ∑ m(3, 5, 6, 7) = A ∙ B + Cin ∙ A + Cin ∙ B (2)

3.1 Full adder design using majority gate

From Eq. (1) and Eq. (2), the most straight forward approach
Figure 2 FA Architecture using Majority Gate Logic (MGL). for designing the adder is using logic gates like 3-input XOR gate
for sum (SUM) output and 3-2 input AND gates with 1-3 input
OR gate for Carry-out (Cout). From CMOS based circuit
complexity. The basic need of comparator is to find the
implementation of full adder modelled using Eq. (1) and Eq. (2),
arithmetic relation between two variables (say A, B) in terms of
it is found that it requires 40-Transistors for producing SUM and
either lesser than or greater than or equal to. The traditional
Cout outputs. The transistors required to construct the FA can be
method of comparison is the finding of relative magnitudes of the
reduced by modifying the SUM and Cout Boolean equations as
variables. One of the most common approaches to find arithmetic
follows,
relation is based on a bit-wise comparison for digital variables.
In which Most Significant Bits (MSB) are compared and if the ̅̅̅̅̅̅ = A
̅∙B
̅ ∙ ̅̅̅̅ ̅ ∙ B ∙ Cin + A ∙ B
̅ ∙ Cin + A ∙ B ∙ ̅̅̅̅
SUM Cin + A Cin (3)
relationship is found between these bits than that is the output of
comparator else if these two MSB bits found to be equal, then the
comparison result depends on lower-order bits. The bit-wise 𝐶𝑜𝑢𝑡 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅∙B
A ̅ + ̅̅̅̅
Cin ∙ (A̅+B ̅) = 𝑀𝐴𝐽𝑂𝑅𝐼𝑇𝑌 (A, B, Cin ) (4)
comparison continues until all the bits of two variables are
compared until a relation is found. Since the comparison is bit- From the Eq. (2), it can be observed that the output Cout
wise, it requires more logic gates in-turn transistors and hence exists, whenever the majority of inputs exist and the same is
results in larger power dissipation and longer delays. shown in Eq. (4), termed as called “Majority Gate Equation”, and
To overcome the circuit design complexity in terms of the hence the logic is called Majority Gate Logic (MGL). CMOS
number of transistors, the power consumed and smaller delays, a implementation of FA using Eq. (3) and Eq. (4) is illustrated in
new method of magnitude comparison is proposed. The basic Figure 2.
principle of proposed logic is based on 2’s complement addition. From Figure 2, it can be observed that MGL implementation
To find the arithmetic relation between two variables (say A, B), of FA requires a total of 32 Transistors out of which 6 for
bit-wise (B-A) subtraction is performed using 2’s complement inverters, 10 for the majority gate i.e. for Cout and 16 for SUM
logic. As per the 2’s complement addition, if the addition output. Hence this logic requires 20 % less area compared to
operation results in a carry than the relation is A ≤ B, if all the traditional CMOS implementation of FA based on Eq. (1) and
sum bits are Zero than the relation is A = B and while if carry (2).
don’t exist and if all the sum bits are not Zero than the relation is
A > B. The architecture based on this principle for the 3.2 Full adder design using mirror adder
comparison of two 4-bit inputs (Say, A [3:0] and B [3:0]) is
shown in Figure 1. The transistors count required for implementing FA based on
From the Figure 1, it can be observed that to perform (B-A), Eq. (1) and (2) can be further reduced by reusing Cout for
A is bit-wise complemented using Inverters and applied as the producing SUM. By applying Boolean algebraic rules, the SUM
second input to full adders (FAs), while the first stage full adder expression modelled using Eq. (1) can be factorized such that Cout
42 Engineering and Applied Science Research 2021;48(1)

Figure 3 Full Adder design using Mirror Adder Logic (MAL)

Figure 4 FA Architecture Using Complementary Pass Transistor Logic (CPL)

shown by Eq. (4) can be reused and thus the expression for SUM excellent method for utilizing the pass transistors which
output is, overcomes the disadvantages using static CMOS inverters and is
termed as “Complementary Pass transistor logic (CPL)”. In
SUM = A ∙ B ∙ Cin + (A + B + Cin) ∙ ̅̅̅̅̅̅
Cout (5) general, CPL consists of true and inverted variables; NMOS pass
transistors and level shifter using inverters.
Figure 3 illustrates the CMOS implementation of FA based The full adder modelled using Complementary Pass
on Eq. (5) and Eq. (6). It can be inferred from the circuit transistor logic (CPL) is shown in Figure 4. CPL tries to reduce
implementation that the PMOS and NMOS network are alike the number of transistors for implementing the FA logic by
rather than being the complement, unlike the traditional CMOS driving both gates together with source and drain terminals using
logic. This topology is termed as “Mirror Adder” and hence the the primary inputs unlike traditional CMOS logic [11]. It can be
logic is Mirror Adder Logic (MAL). The simplification involved observed from Figure 4, that FA designed using the CPL [12]
here has reduced the number of series transistors resulted in approach uses 30 Transistors in comparison to 40-Transistors
uniform Layout. 28 transistors are utilized to implement the FA based CMOS static logic [13].
which is 30 % less compared to traditional CMOS logic and
about 12.5 % less than MGL. 3.4 Transmission gate logic (TGL) based full adder design

3.3 FA Using complementary pass transistor logic (CPL) Unlike the digital gates, the Transmission Gate [14] is similar
to a switch that operates in both directions. It consists of an
In contrast to static CMOS logic, Pass transistor logic offers NMOS and PMOS transistors connected in parallel and whose
greater lead in terms of three parameters area, power, and speed. operation can be controlled by a control signal connected in
Even though it provides better performance, it has been avoided complement to their respective gates. The FA modelled by Eq.
in low power applications because of degraded logic voltage (1) and Eq. (2) implemented using these transmission gates is
levels which result in reduced noise Margins. [10] Proposed an illustrated in Figure 5. It can be noticed from Figure 5 that the
Engineering and Applied Science Research 2021;48(1) 43

Figure 5 Full Adder design Using Transmission Gate Logic (TGL)

Table 1 Input Combinations for various Logic operations using GDI logic.

Function G P N Output
OR A B ‘1’ A+B
AND A ‘0’ B A.B
MUX A B C A’.B+A.C
XOR A B B’ A’.B+A.B’
NOT A ‘1’ ‘0’ A’

̅∙P+G∙N
Q=G (6)

To highlight the advantages of the GDI technique, Table 1

also presents the comparison of GDI and traditional CMOS logic
implementation of various functions in terms of transistor count.
It is evident from Table 1, that GDI logic uses a reduced number
of transistors in contrast to the traditional CMOS circuit and
hence results in low power dissipation and larger speed. Full
adder (FA) using GDI has been implemented and illustrated in
Figure 7 and can be observed that FA design using GDI logic
requires a small transistor count in contrast to other logic styles
[17].
Figure 6 Basic GDI Logic Cell.
4. Simulation results
full adder implementation using transmission gate logic requires
only 20-Transistors in contrast to 40 and 30-transistors in Static
In this work, the 4-bit Magnitude Comparator (MC) has been
CMOS and CPL. Further, the use of transmission gates [15]
designed using five different design techniques that include
allows to gain high speed and low power consumption in contrast
Majority Gate Logic (MGL), Mirror Adder Logic (MAL),
to other logic styles and discussed in section 4.
Complementary Pass Transistor Logic (CPL), Transmission Gate
Logic (TGL) and Gate Diffusion Input Logic (GDI) [18]. The
3.5 Full adder design using gate diffusion input logic (GDI)
block diagram of a 4-bit magnitude comparator based on 2’s
Gate diffusion input (GDI) logic is a power-efficient design complement addition using various GDI logic blocks is
technique that overcomes the various problems associated with illustrated in Figure 8. The performance metrics of all the design
the other static CMOS design styles. Using GDI, a wide range of techniques discussed are studied by designing and implementing
logic circuits can be implemented by using only two transistors 4-Bit comparator in 180 nm CMOS Process Technology [19]
and suitable for fast and low power circuits with reduced using Cadence Spectre environment at a supply voltage of 1.8 V.
transistor count compared to other existing CMOS design styles For the ease of implementation and for achieving optimized pull-
in the literature. The basic logic cell used in the GDI technique up to pull- down ratios, the length and width of all the NMOS
opted from [16] is reproduced here in Figure 6 for the sake of transistors are fixed at 500 nm and 1 µm respectively and 500 nm
clarity. The logic cell resembles basic static CMOS inverter but and 2.5 µm for PMOS respectively [20, 21, 23]. Table 2 shows
with 4-terminals instead of two, 3-Inputs (Say G, P, and N) and the comparison of various logic techniques in terms of transistors
1-Output (Say Q) as shown in Figure 6. for implementing the basic component full adder required in
Different logic operations can be implemented with GDI designing the proposed comparison technique using 2’s
basic cell using various input combinations as presented in complement addition. It can be perceived from Table 2, that GDI
Table 1. The input combinations specified in Table 1 is based on logic requires a very less number of transistors compared to other
the output equation of GDI cell and is expressed as, techniques.
44 Engineering and Applied Science Research 2021;48(1)

Figure 7 FA design using Gate Diffusion Input logic (GDI)

VDD B
B
VDD
A A+B VDD
A A+B (A+B)’
Vin Vout
VDD (A+B+C+D)’
A+B+C+D
VDD Gnd
D
Gnd 2-Input GDI NOR
CMOS / GDI Inverter VDD Gnd
C C+D

Cout
A>B
B3 S3
+ VDD
A3 4 Input GDI NOR
A<B

C3
B2 S2
+
A2 A

C2 A=B
B1 S1 B
+ C SUM
A1

C1
B0 S0
+
A0
Cin

Architecture of 4 BIT Magnitude Comparator

Cout

10T GDI FA

Figure 8 Architecture of 4 Bit Magnitude Comparator using GDI logic Blocks.

Table 2 Transistor count for various FA designs.

Sr. No Design Style Number of Transistors

1 MGL [8] 32
2 MAL [8] 28
3 CPL [12] 32
4 TGL [14] 20
5 Hybrid [22] 18
6 GDI 10

Figure 9 depicts the power variation of the 4-bit comparator bar diagram, and the same is illustrated in Table 3. Figure 12
depicted in Figure 1 concerning temperature. Figure 10 shows the shows the simulation results of the 4-bit Comparator
power variations with respect to input voltages. It can be implemented using the GDI technique in the 180 nm process
observed from Figure 9, that the power dissipation increases with using the Cadence Spectre environment.
temperature, and this variation found to be very small in GDI
logic. From Figure 10, it can be inferred that the GDI exhibits 5. Conclusion
less power dissipation compared to other logic styles.
Figure 11 illustrates the performance analysis of the 4-bit The performance metrics power, delay, and area of 5
magnitude comparator designed using various design styles in different CMOS logic design styles are studied in this paper. 4-
terms of the number of transistors, power, and speed in terms of Bit comparator using 2’s complement addition technique has
Engineering and Applied Science Research 2021;48(1) 45

Figure 9 Variation of Power with Temperature of 4-bit MC

Figure 10 Variation of Power with Input Voltage of 4-bit MC

Figure 11 Performance Analysis of 4-Bit MC using various Logic Designs

Table 3 Performance Comparison of 4-bit MC using different digital logic styles.

Sr. No Design Style Number of Transistors Power (nW) Delay (ns)

1 MGL 154 3.027 1.269
2 MAL 138 2.750 1.062
3 CPL 154 1.327 1.608
4 TGL 126 1.267 1.688
5 GDI 62 1.173 0.932
46 Engineering and Applied Science Research 2021;48(1)

Figure 12 Simulation Results of 4-Bit Comparator using GDI logic obtained from Cadence spectre Environment

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