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DSP Unit-5 Solutions

The document discusses digital signal processors and their architectures. It covers topics like addressing modes, memory access schemes, convolution operations, pipeline architectures, and specific processors like TMS320C5X. Questions from past exams on understanding various concepts related to DSP processors are included.

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vasudevanandhasrividya16
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143 views

DSP Unit-5 Solutions

The document discusses digital signal processors and their architectures. It covers topics like addressing modes, memory access schemes, convolution operations, pipeline architectures, and specific processors like TMS320C5X. Questions from past exams on understanding various concepts related to DSP processors are included.

Uploaded by

vasudevanandhasrividya16
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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2.

Explain the short direct addressing and circular addressing modes


in programmable DSP’s. (SET-1 R19, June-2022, U-
Understand)

4. How convolution operation is performed using a single MAC unit?


Explain. (SET-2 R19, June-2022, U-Understand)
8. Explain the memory mapped addressing modes and bit reversed
addressing modes in programmable DSP’s. (SET-3 R19, June-2022, U-
Understand)
10 Explain the differences between Von Neumann and Harvard
architectures. Which architecture is preferred for DSP applications?
(SET-4 R19, June-2022, U-Understand)

12. Discuss the salient features and special addressing modes of Digital
signal processors. (SET-1 R20, July-2023, U-Understand)
13.Explain in brief memory access schemes in DSP processors. (SET-2 R20,
July-2023, U-Understand)
14.Draw the pipelined MAC configuration to perform convolution
operation and Explain with neat timing diagrams. (SET-2 R20, July-
2023,R-Remember)
It is the approach adopted for increasing the efficiency of the advanced
microprocessors as well as P-DSPs. An instruction cycle can be split into a number of
microinstructions. Execution of each of microinstructions is referred to as one phase
of an instruction. The four phases of an instruction cycle are as follows
1. Fetch phase in which the instruction is fetched from the program memory
2. Decode phase in which the instruction is decoded
3. Memory read phase in which the operand required for the execution of the
instruction may be read from the data memory
4. Execution phase in which execution as well as storage of results in either one of the
registers or memory is carried out.
Let us assume that each of the above four phases take equal time for completion.
If no pipelining in the processor, then only one instruction is processed at the CPU at
a time. That is only 25% of the time is utilized remaining time is wasted. The no. of
clock cycles required (time slots) to execute the three Instructions without pipelining
are as shown following table

So that 12 time slots are required to execute 3 instructions without pipelining. The
functional units can be kept busy almost all the time by processing a number of
instructions simultaneously in the CPU, which is called as “pipelining”. In pipelining
when instruction one is decoding the J2 is fetched simultaneously, and when I1 is
reading the I2 is decoded and I3 is fetched. The main advantage of the pipelining is
number of time slots required are reduced and the instruction execution speed is
increased. One of the problem in pipelining is extra time is required at the start of
algorithm execution, as the pipeline has to be filled before the result of I1 can start to
flow out. This initial delay in units of time is called a “pipeline latency”. It depends
on the number of units in the pipeline. The following table explains the pipeline
operation for 3 instructions
Here the number of time slots required are only 6. That means with pipelining the
number of time slots are reduced to 6 from 12. So, the speed increased with pipeline
operation. The pipeline latency for a four phase machine is 4T. With a non-pipelined
machine to execute N instructions time required is 4NT and with pipelining the time
required is (N+4) T.

15.What is meant by bit reversed addressing mode? What is the application


for which this addressing mode is preferred? (SET-2 R20, July-2023,U-
Understad)

Special data access capability is required to implement FFF using decimation in


time (DIT) algorithm. The naturally ordered data needs to be accessed as shown below
for 8 – point FFT.

Input Index Output index


(natural order) (b/t – reversed order)
000 = 0 000 = 0
001 = 1 100 = 4
010 = 2 010 = 2
011 = 3 110 = 6
100 = 4 001 = 1
101 = 5 101 = 5
110 = 6 011 = 3
111 = 7 111 = 7
The bit reversed indices are obtained as follows: start with index 0 obtain each current
index by adding half the size of the FFT to the corresponding previous index.
Current index=Previous index+(FFTsize/2)

The addition here is a reverse carry – add operation in which the carry must
Propagate from the most significant to the least significant bit.

16. Explain the special addressing modes of DSP with suitable examples.
(SET-3 R20, July-2023, U-Understand)
17.Explain the memory access schemes in P-DSP’s (SET-4 R20, July-2023,
U-Understand)

18.Explain the functioning of Multiplier and Multiplier Accumulator in DSP


processor (SET-4 R20, July-2023, U-Understand)

19.With neat block diagram, explain about the pipelining in DSP processors
(SET-1 R20, July-2023, U-Understand)

Refer Q.14

20. What is meant by instruction pipelining? Explain with an example (SET-


4 R19, June-2022,U-Understand)

Ans: Refer Q.14

21. Draw the block diagram of VLIW architecture and explain. (SET-3 R19,
June-2022,U-Understand)
22. Explain how the VLIW architecture is improving the performance of DSP
processor. (SET-2 R20, July-2023, U-Understand)

Ans: Refer Q.22

23. Write a short notes on the following: (i) Multiple access memory (ii)
Multiported memory. (SET-1 R19, June-2022,R-Remember)

Ans: Refer Q.17


24. List out the on-chip peripherals in programmable DSP’s and explain any
two of them in detail. (SET-2 R19, June-2022, R-Remember)

A TMS320C50 digital signal processor contains the following on-chip peripherals.


26.Explain briefly the following for TMS320C5X: i) Flags available in status
register ii) Parallel Logic Unit. (SET-1 R20, July-2023, U-Understand)

HM :
27. Explain in detail the architecture of TMS320C5X processor. (SET-1 R20,
July-2023, U-Understand)

Ans:Refer Page 12 to 21 from material

28. Write about the architectural features of TMS320C5X DSP processor.


(SET-3 R20, July-2023 R-Remember)

AnsL Refer 12 to 21 fro material

29. How much memory can be Interfaced to TMS320C5X? Explain in detail


its Memory mapping. (SET-3 R20, July-2023, U- Understand)

30.Explain the i) Bus Structure ii) On-chip peripherals in a TMS320C5X


DSP processor. (SET-3 R20, July-2023, U-Understand)
Ans:

For Interrupts refer Q.No.24

31. Discuss various interrupt types supported by TMS320C5X processor.


(SET-4 R20, July-2023, U-Understand)

Ans: Refer Q No.24

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