short-channel device:

• A MOSFET is considered to be short when the channel length is the same order of
magnitude as the depletion-layer widths (xdD, xdS)

Short Channel Effects:

• Five different physical phenonomena have to be considered in short-channel

devices:

• Drain induced barrier lowering and Punchthrough

• Surface scattering

• Velocity saturation

• Impact ionization

• Hot electrons

Drain-induced barrier lowering (DIBL):

• The electrons (carriers) in the channel face a potential barrier that blocks their flows

• The potential barrier, in small-geometry MOSFETs, is controlled by a two-dimensional

electric field vector (in other words by both VGS and VDS)

• If the drain voltage is increased the potential barrier in the channel decreases, leading to

Drain-Induced Barrier Lowering (DIBL)

 • Under DIBL condition electrons can flow between the source and drain even if V GS < VT

• The channel current that flows in this case is called subthreshold current

Surface scattering:

• For small-geometry MOSFETs, the electrons mobility in the channel depends on a two-
dimensional electric field ( x, y)

• The surface scattering occurs when electrons are accelerated toward the surface by the
vertical component of the electric field x

• The collision of the electrons causes a reduction in the mobility

• Electrons moves with great difficult parallel to the interface

• The average surface mobility is about half as much as that of the bulk mobility

Velocity saturation:

• For low y the electron drift velocity vde in the channel varies linearly with the electric
field intensity

• As y increases above 104 V/cm the drift velocity tends to approach a saturation value of
vde(sat)=107 cm/s around y =105 V/cm

• The velocity saturation reduces the transconductance of short-channel devices in the

saturation condition, as the following formula shows:
gm = W Cox vde(sat)

Impact ionization:

• The presence of high longitudinal fields can accelerate electrons that may be able of
ionizing Si atoms by impacting against them

• Normally most of the e- are attracted by the drain, so it is possible a higher concentration
of holes near the source

• If the holes concentration on the source is able to creates a voltage drop on the source-
substrate n-p junction of about 0.6V then

• e- may be injected from source to substrate

• e- travel toward the drain, increasing their energy and create new e-h pairs

• e- may escape the drain fields and afect other devices

Hot electrons:

• The channel Hot Electrons effect is caused by electrons flowing in the channel for
large VDS

• e- arriving at the Si-SiO2 interface with enough kinetic energy to surmount the surface
potential barrier are injected into the oxide

• This may degrade permanently the C-V characteristics of a MOSFETs

High k:

Intel made a significant breakthrough in the 45nm process by using a "high-k" (Hi-k) material
called hafnium dioxide to replace the transistor's silicon dioxide gate dielectric, and by using new
metals to replace the NMOS and PMOS polysilicon gate electrodes. These new materials
reduced the NMOS gate leakage by >25 Times and PMOS gate leakage by more than 1000
Times while simultaneously delivering improved drive current and improved circuit
performance.

Gate leakage in a modern transistor occurs through a process called "quantum mechanical
tunneling." Under normal circumstances, all the electrons are on the "upstream" side of the gate
(picture the gate as a dam, and electrons as water trapped behind the dam). Quantum mechanical
tunneling occurs when the gate dimension is so thin that the electrons (or holes) have a certain
statistical probability of being on the "downstream" side of the gate - without actually sloshing
over the gate. In modern transistors, the gate thickness is about five atomic layers. The thinner
the gate, the larger the tunneling current and the higher the leakage power.

The tunneling current can be reduced by thickening the gate. The problem here is that increasing
the physical gate thickness increases the electrical oxide thickness, and thus reduces the
transistor performance. The ideal solution would be to increase the physical thickness
WITHOUT increasing the electrical oxide thickness. Amazingly enough, this is possible by
increasing the "k" (or dielectric constant) of the material. A "higher-k" material can be physically
thicker without being electrically thicker.

"High-k" stands for high dielectric constant, a measure of how much charge a material can hold.
Air is the reference point for this constant and has a "k" of 1.0. Silicon dioxide (the "old-
fashioned" gate material) has a "k" of 3.9. "High-k" materials, such as hafnium dioxide (HfO2),
zirconium dioxide (ZrO2) and titanium dioxide (TiO2) have "k" values higher than 3.9.

FINFET:

FinFET is a type of multi gate (MOSFET). It was first developed at the University of Berkley,
California. It is named as FinFET because the 3D structure above the substrate looks like set of
fins. It is a 3D transistor and widely used in integration circuits recently instead of planar CMOS
FinFet. It is used more than other FETs because of its area of performance, lower leakage power,
low voltage operation, intra- die variability and lower retention voltages for SRAM.

Structure of FinFET
In planar FET the Gate is placed above the channel and there is leakage current flowing from
source to drain even when the gate is off. Like the normal FET , FinFET consists of a source,
drain and also a gate to control the current flow.In the FinFET the channel is thin vertical fin and
gate is wrapped around it. This helps in better controlling of the channel and thus the electrical
properties are better. FinFET can have two to four fins in the same structure.

Structure of FinFET

The manufacturing process of the FinFET includes the following steps.

Substrate: In the fabrication process first a lightly doped P type substrate is used and a hard mask
over it.

•Fin etch:Then by a highly anisotropic process fins are formed

•Oxide deposition: Over the fins oxide layers are formed to isolate the fins.

•Planarization: It is planarized by chemical mechanical polishing process.

•Recess etch: Excess oxide is etched

•Gate oxide: To isolate the channel from the gate by thermal oxidization process gate oxide is
deposited over the fins.

•Deposition of the gate: Finally gate layer is formed of highly doped N+ poly silicon layer and
deposited over the fins.

Advantages of FinFET over other FETs:

1) Lower power consumption

2) Operates at lower voltage

3) Operating speed is higher

4) Static leakage current is reduced upto 90%

5) More compact

Disadvantages of FinFET

1) For building the FinFET it involves many additional steps, so the fabrication cost is high

2) Controlling the Fin depth is difficult

Applications of FinFET

1) Used in the microprocessor

2) Used in smart phones

TFET :
The basic TFET structure differs from a MOSFET structure in selecting different source and
drain regions. Source is doped with p-type and drain is doped with n-type. The TFET device
structure consisting a P-I-N (p-type, Intrinsic, n-type) junction with the intrinsic area is covered
with oxide layer works on tunnelling between source and drain where the tunnelling potential is
controlled by a gate above the oxide layer. To understand the concept of tunnelling operation of
tunnel diode is being discussed here.

Figure 1. Basic TFET Structure

In simple terms, the TFET is a gated reverse-biased p-i-n structure. A simple implementation of
an n-type and a p-type TFET is shown in Figure 3.1. Structurally, the most distinguishing feature
of a TFET is the type of doping of the drain and the source. The doping of the drain and the
source are of opposite types in a TFET. In contrast, the drain and the source doping are of the
same type in a conventional MOSFET. For an n-type TFET, the drain is doped n+ while the
source is doped p+. For a p-type TFET, the drain is doped p+ while the source is doped n+. The
channel is an intrinsic or lowly doped p-type or n-type semiconductor. The channel is separated
from the gate electrode by a dielectric, similar to a conventional MOSFET.
The biasing schemes of an n-type TFET and a p-type TFET are shown in Figure 3.1. For an n-
type TFET, the source is grounded and a positive voltage is applied to the drain and the gate
electrodes. For a p-type TFET, the source is grounded and a negative voltage is applied to the
drain and the gate electrodes. A TFET is called an n-type TFET or a p-type TFET depending on
the dominant carrier in the channel formed under the gate when the TFET is turned on. When the
dominant carriers in the channel are electrons, the TFET is called an n-type TFET and when the
dominant carriers in the channel are holes, the TFET is called a p-type TFET. The terminals are
called source or drain depending on whether the dominant carriers enter or leave the channel
through that terminal. In an n-type TFET, the electrons enter the channel through the source and
leave the channel through the drain. In a p-type TFET, the holes enter the channel through the
source and leave the channel through the drain. The mechanism of the dominant carriers entering
the channel is band-to-band tunneling (BTBT).