Logic Analyzer

A Presentation By: Mohammad Umar Rehman Electrical Engg. Department A. M. U., Aligarh

Outline
Introduction Principle of Operation Block Diagram Oscilloscope v/s Logic Analyzer Application: Glitch Detection Final Remarks
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Introduction
The advent of digital circuits has dramatically changed the concerns of engineers and technicians working with electronic circuits. The digital systems, like microprocessors, motherboard circuits are the examples where the test instrument must be very fast and provide detailed analysis of the system under test (SUT). This necessitates the development of an instrument that extends the capabilities of the oscilloscope such that the user will be able to lock into the system and trace the flow of digital informationLogic Analyzer

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Thus, Logic Analyzer captures a set of digital inputs simultaneously, stores the binary values and displays this information in the form of a timing diagram, state machinetraces or assembly language Logic Analyzer is a versatile tool that can aid debugging of digital hardware (FPGA, ASIC), design verification and embedded software (Ps & Cs) Must placed instrument on a digital designers tabletop

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Principle of Operation
There are four operating steps: 1. Probe (connect to the system under testSUT) 2. Setup (clock mode and triggering) 3. Acquire 4. Analyze & Display

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Block Diagram
Probe Acquisition Buffer/ Memory Sampler Sample Trigger Clock Logic Memory 2 External ClockControl Clock Select Probes Internal Clock Umar_Logic Analyzer Generator 1 3 4 Analysis & Display

Input Probes

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Probes
Provide physical connection between the instrument and system under test Instead of using cable for each channel, 8 or more channels are grouped into pods (plug-on-devices) which then connects to the SUT as a single cable. Other important functions are:

To provide a high-quality signal path to the LA To minimize the electrical loading on the SUT To adapt to various types of connections on circuit boards & devices
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Logic analyzer probes provide a high-quality signal path to the instrument while maintaining a reliable physical connection
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Setup
1. Asynchronous Timing Mode: . An internal clock samples the input data, faster

sampling means better resolution.

. Timing analyzer works in the same manner as the

oscilloscope levels.

. Horizontal axis as time and vertical axis as logic . Suited for bus type architectures, many lines

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2. Synchronous State Mode used to acquire the state of the SUT. Triggered using external clock of SUT Data is sampled on the active edge and represents the condition of the SUT when the logic signals are stable Suited for both hardware and software debugging, and to catch data as the system sees it.

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Triggering
Unlike the limited triggering capability of oscilloscopes based on binary information a LA can be triggered based on a number of logic (Boolean) conditions. Triggering helps to select the data which is to be captured An oscilloscope starts the data acquisition after trigger signal while the LA stops at it Thus a LA can show information prior to the trigger point as well as after it Different types of triggering are: edge, pattern, glitch, counter, timer, word
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Acquisition
Real time acquisition memory is the heart of any LA which is the destination of all the sampled data from SUT. LAs have memory capable of storing data at instruments sample rate which can be viewed as a matrix with width & depth depending on no. of signals and acquisition time. The instrument accumulates a record of all signal activity until a triggered that results in an acquisition. Display is essentially a multi-channel waveform display that lets user view the interaction of all the acquired signals with a very high degree of timing precision

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Analysis & Display

Once the information is stored within the system, it can be viewed in formats ranging from timing waveforms to instruction mnemonics correlated to source code. Bench-top analyzers use dedicated LCD screens for display while PC based analyzers use the PC monitor Timing analyzer provides waveform display which is ideal for

diagnosing timing problems in SUT hardware Verifying correct hardware operation & timing related characterisitics

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The listing display provides state information in userselectable alphanumeric form. The data values in the listing are developed from samples captured from an entire bus and can be represented in hexadecimal or other formats.

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LA waveform display State acquisition captures a slice of data across a bus when the external Umar_Logic Analyzer 1717 clock signal enables an

Logic analyzers are supplied as PC-hosted or bench-top versions. Above shown is an Agilent Technologies 1680 Benchtop Protocol Analyzer
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A Real Logic Analyzer

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v/s

Oscilloscope v/s Logic Analyzer

S.No. 1. 2. Parameter Channels Display DSO LA 2-8 34-136 Actual Idealized timing Waveform, diagram, single repetitive signals event Stops Acquisition Multiple Moderate to High
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3. 4. 5.

Triggering Starts Acquisition Effect Trigger Mode Single Memory Moderate Requirements
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When to Use a...

Oscilloscope: (parametric info)

When it is required to observe small voltage excursions the signal. When high time-interval accuracy is required
Logic Analyzer: (timing relationship)

on

When many signals are to be observed simultaneously When it is necessary to look at signals in the same way the hardware does
as

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Application: Glitch Capture

A glitch is a signal that makes a transition through the threshold level twice (or even more) between successive clock samples The problem with the glitch is that it appears at very critical times (like data writing to latch) and can cause circuit malfunctioning. Moreover, it appears too infrequently, so a simple oscilloscope cant help. Timing analyzer then comes to rescue by keeping track of multiple transitions between the samples and trigger upon it
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Final Remarks
Logic analyzers is a basic tool used in the area of fault diagnosis of digital systems, hardware verification & software testing in embedded circuit design. The other area of application is in automated testing. However, the logic analyser is still far less frequently used than the oscilloscope, probably owing to cost and complexity Addition of more features like communication capabilities, self calibration, more user friendly interfaces might change this picture
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References
1. Anand, Manmohan Singh, Electronic Instruments & Instrumentation

Technology, PHI, New Delhi, 2008.

2. Tektronix, The XYZs of Logic AnalyzersPrimer 3. Kularatna, N., Digital & Analogue Instrumentationtesting and

measurement, IET, UK, 2008.

4. Kuan, Ai Lee, A How to tutorial on logic analyzer basics for digital

design, Agilent Technologies, [online] Available: http://www.eetindia.co.in/STATIC/PDF/200705/EEIOL_2007MAY02_POW_EM

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Thank You