CND 111

Design Project Project #1

Introduction to Digital Design

Title: Systolic Array for Matrix-Matrix Multiplication

Supervisor: Dr. Shady Agwa

Description:
Artificial Intelligence AI applications, and Deep Neural Networks DNNs at the core of them,
are currently dominating the technology landscape. Various application domains are utilizing
these AI models in Healthcare, Robotics, Automotive, Social media and other important daily-
life purposes. The main computational bottleneck of these AI models, from DNNs to
transformers, is the Matrix-Matrix Multiplications for large datasets. Systolic Arrays are
emerging specialized hardware accelerators that maximize the data utilization while efficiently
performing the matrix-matrix multiplication tasks. The project aims at building a small-scale
systolic array for matrix-matrix multiplication using the weight stationary dataflow
architecture.
Requirements:
• Search for a suitable architecture for the weight stationary systolic array.
• Develop a parametrized Processing Element PE with integer multiplication-
accumulation capability.
• Build a parameterized systolic-array of NxN PEs.
• Build a testbench with two matrices to test the systolic array.
• Characterize the performance, energy efficiency and area efficiency of the
implemented architecture.

Assessment Criteria:
— Circuit design, and implementation using Verilog --- 50%
— Simulation and testbench --- 30%
— Design metrics (resources usage, power, operating frequency) evaluation --- 20%
— Bonus:
o Advanced design considerations (low-power techniques, high speed, …) -- 15%
o Verify the implemented design on FPGA --- 15%

Best of Luck!

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 CND 111
Design Project Project #2
Introduction to Digital Design

Title: RTL Implementation of Differential Chaos Shift Keying (DCSK) Modulation and
Demodulation
Supervisor: Dr. Khaled Salah

Description:
Differential Chaos Shift Keying (DCSK) is a promising and innovative modulation technique
used in modern wireless communication systems. DCSK modulation offers advantages such
as robustness against channel impairments and low probability of interception, making it
suitable for secure and reliable wireless communications. This project aims to design,
implement, and validate the RTL (Register-Transfer Level) implementation of DCSK
modulation and demodulation algorithms.

Requirements:
• Propose an architecture
• Write a Verilog code to describe the architecture
• Write Verilog testbench to test it.
• Collect Synthesis results in terms of Area, Performance.
• Calculate power consumption

Assessment Criteria:
— Circuit design, and implementation using Verilog --- 50%
— Simulation and testbench --- 30%
— Design metrics (resources usage, power, operating frequency) evaluation --- 20%
— Bonus:
o Advanced design considerations (low-power techniques, high speed, …) -- 15%
o Verify the implemented design on FPGA --- 15%

Best of Luck!

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 CND 111
Design Project Project #3
Introduction to Digital Design

Title: RTL Implementation of SoC Bridge: AMBA AHB-APB bridge

Supervisor: Dr. Khaled Salah

Project 2 Description:
AHB-APB bridge is a crucial component in modern System-on-Chip designs, enabling
efficient communication between high-performance and peripheral components. This project
focuses on designing, implementing, and verifying the Register-Transfer Level (RTL)
representation of a System-on-Chip (SoC) bridge that serves as an interface between the
Advanced Microcontroller Bus Architecture (AMBA) Advanced High-Performance Bus
(AHB) and AMBA- Advanced Peripheral Bus (APB) protocols.

Project 2 Requirements:
• Propose an architecture
• Write a Verilog code to describe the architecture
• Write Verilog testbench to test it.
• Collect Synthesis results in terms of Area and performance.
• Calculate power consumption

Assessment Criteria:
— Circuit design, implementation using Verilog --- 50%
— Simulation and testbench --- 30%
— Design metrics (resources usage, power, operating frequency) evaluation --- 20%
— Bonus:
o Advanced design considerations (low-power techniques, high speed, …) -- 15%
o Verify the implemented design on FPGA --- 15%

Best of Luck!

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 CND 111
Design Project Project #4
Introduction to Digital Design

Title: RTL Implementation of a Programmable NoC

Supervisor: Dr. Khaled Mohamed

Description:
The Network-on-Chip (NoC) serves as a crucial interconnect infrastructure for complex
System-on-Chip (SoC) designs, offering flexibility, scalability, and efficient data
communication. This project is focused on the design, development, and verification of a highly
configurable and programmable Network-on-Chip (NoC) architecture at the Register-Transfer
Level (RTL).

Requirements:
• Propose an architecture
• Write a Verilog code to describe the architecture
• Write Verilog testbench to test it.
• Collect Synthesis results in terms of Area and performance.
• Calculate power consumption

Assessment Criteria:
— Circuit design, and implementation using Verilog --- 50%
— Simulation and testbench --- 30%
— Design metrics (resources usage, power, operating frequency) evaluation --- 20%
— Bonus:
o Advanced design considerations (low-power techniques, high speed, …) -- 15%
o Verify the implemented design on FPGA --- 15%

Best of Luck!

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 CND 111
Design Project Project #5
Introduction to Digital Design

Title: Approximate ALU

Supervisor: Dr. Omar Eldash

Description: Computing systems are becoming increasingly complex. To account for the
continuous trade-offs between performance, area and power we sometimes sacrifice accuracy.
This becomes more obvious in applications like machine learning and signal and image
processing where we can accommodate slight degradation without a significant loss in
application. The literature is already full of arithmetic blocks like adders and multipliers that
implement some sort of approximation. This project will implement an ALU that combines the
basic

Requirements: Implementation of an approximate ALU that has the following functions:

• Approximate 16-bit fixed point Add/Subtract with a minimum accuracy of 75% of the
cases.
• Approximate 4-bit Multiplier with a minimum accuracy of 60%
• Basic Logic operations

Assessment Criteria:
— Circuit design, and implementation using Verilog --- 50%
— Simulation and testbench --- 30%
— Design metrics (resources usage, power, operating frequency) evaluation --- 20%
— Bonus:
o Advanced design considerations (low-power techniques, high speed, …) -- 15%
o Verify the implemented design on FPGA --- 15%

Best of Luck!

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 CND 111
Design Project Project #6
Introduction to Digital Design

Title: Emulator for New Memory Technology

Supervisor: Dr. Omar Eldash

Description:
Electronic Design Automation is a big part of IC design process and a major player in speeding
it up. In many cases hardware emulation becomes a useful luxury to accelerate things further.
With many devices being utilized nowadays for non-volatile memory as a way to do in-memory
computing, programming them to an accurate level is a difficult task. This project will focus
on sampling a part of this domain by implementing a small array of resistive memories that are
organized in an architecture to perform matrix vector multiplication. The main idea is to use
approximate device models publicly available to estimate what should be the resistive memory
value set to for proper operation.

Requirements:
Implementing a behavioral emulator for A 4x4 Resistive RAM array that implements Matrix
Vector Multiplication. The deliverable will be expected in Verilog system that is running on
FPGA or in simulation.

Assessment Criteria:
— Circuit design, implementation using Verilog --- 50%
— Simulation and testbench --- 30%
— Design metrics (resources usage, power, operating frequency) evaluation --- 20%
— Bonus:
o Advanced design considerations (low-power techniques, high speed, …) -- 15%
o Verify the implemented design on FPGA --- 15%

Best of Luck!

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 CND 111
Design Project Project #7
Introduction to Digital Design

Title: 8-Bit ALU Core

Supervisor: Dr. Sameh Sherif

Introduction: What are the necessary steps and Verilog Script required to effectively
implement the architecture of an 8-bit ALU core, illustrated in Figure 1? Specifically, discuss
the integration of the three key units, namely Arithmetic, Logic, and Shifter units, alongside
the coordination provided by a control unit. Additionally, explore the optimal methods for
storing output data within the designated storage unit.

Functional Requirements:
The ALU's operations are governed by four function inputs (S3 to S0), which direct the 8-bit
2-to-1 multiplexers both internally and externally within the logic blocks. It is required to
implement the ALU both in behavioral and structure methods and compare the results of the
two designs. The operations performed by the ALU, based on the select inputs, are detailed in
Table 1.

Figure 1: Block Diagram

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Table 1: Operation Codes.

S0 S1 S2 S3 F Description

0 0 0 0 A+B Add

0 0 0 1 A-B Subtract

0 0 1 1 B’+1 2’s Complement

1 0 0 0 A AND B AND

1 0 0 1 A XOR B XOR

1 0 1 0 A OR B OR

1 0 1 1 B’ 1’s Complement

1 1 0 0 A→→ RIGHT ROTATE

1 1 0 1 ←←A LEFT ROTATE

1 1 1 0 A→ RIGHT SHIFT

1 1 1 1 ←A LEFT SHIFT

Assessment Criteria:
— Circuit design, and implementation using Verilog --- 50%
— Simulation and testbench --- 30%
— Design metrics (resources usage, power, operating frequency) evaluation --- 20%
— Bonus:
o Advanced design considerations (low-power techniques, high speed, …) -- 15%
o Verify the implemented design on FPGA --- 15%

Best of Luck!

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 CND 111
Design Project Project #8
Introduction to Digital Design

Title: Implementation of DSP Slice

Supervisor: Dr. Ahmed Saeed

FPGAs offer a high level of efficiency when it comes to digital signal processing (DSP)
applications due to their ability to execute customized algorithms in a fully parallel manner.
DSP applications heavily rely on binary multipliers and accumulators, which are ideally
implemented using dedicated DSP slices. In the case of Xilinx 7 series FPGAs, they are
equipped with numerous specialized, custom-designed, power-efficient DSP slices. The
basic functionality of the DSP48E1 slice is shown in Figure.

Figure 1: Basic DSP48E1 Slice Functionality [https://docs.xilinx.com/v/u/en-US/ug479_7Series_DSP48E1]

Requirements:
— Write a Verilog code to describe the architecture of the DSP48E1
— Capture the design as a schematic
— Create a symbol of your design and the testbench to simulate your design to verify
operation.
— Provide the RTL schematic and synthesis results.
— Explore the synthesis reports (Resource usage, power consumption, maximum clock)

Assessment Criteria:
— Circuit design, and implementation using Verilog --- 50%
— Simulation and testbench --- 30%
— Design metrics (resources usage, power, operating frequency) evaluation --- 20%
— Bonus:
o Advanced design considerations (low-power techniques, high speed, …) -- 15%
o Verify the implemented design on FPGA --- 15%
Best of Luck!
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 CND 111
Design Project Project #9
Introduction to Digital Design

Title: Microprocessor Design

Supervisor: Dr. Islam Yehia
Project Description:
Microprocessors stand as a pivotal component in digital systems, including Systems on Chip (SoCs),
making it an ideal case for grasping core principles and optimal approaches to digital design. Within this
project, students will embark on the creation of a 'Basic' microprocessor, with a primary emphasis on
crafting a thorough design and executing its implementation. This exercise encompasses the application of
various learned concepts and adherence to the best practices explored in digital design studies.

Project Requirements:
• Strict adherence to the established best practices (Lecture 4 + Ch4 + Ch13) is obligatory.
• Minimum specifications include an 8-bit microprocessor with 2 arithmetic operations, 2 logic
operations, and one branch operation. Groups with advanced skills may incorporate additional
functionalities, provided it doesn't compromise the quality of their design documentation.
• A comprehensive specification sheet is essential, encompassing specifications, I/O, block diagram,
timing diagram, testing plan, and programming guide (opcode, addressing mode, etc.).
• A detailed report on the design steps, with a specific focus on the control unit, outlining the various
blocks and the teamwork plan. The teamwork plan is a crucial component that must be clearly
articulated in your report.
• RTL implementation with accompanying simulation results.
• Keep in mind that the key Intended Learning Outcomes (ILOs) include:
o Applying best practices in design, distinguishing design from implementation, which
enhances your suitability for your dream job.
o Cultivating and showcasing effective team management skills.
o Establishing a strong connection between each studied concept and the relevant block in
the design.

Project Assessment Criteria:

• Adherence to studied best practices (Lecture 4 + Ch4 + Ch13) is 50% of the total evaluation.
• 20% teamwork plan.
• 20% RTL and simulation.
• 10% bonus on extra specs:
o Add more instructions (Call-Return, Mul, Div, And-Or-Invert, etc)
o Verify the implementation on FPGA

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