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LAB3 Full+Adder

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Dennis Ivan
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6 views

LAB3 Full+Adder

Uploaded by

Dennis Ivan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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LAB 3 | Full adder Using Three different modelling styles.

Objective
To write and simulate the HDL model for Full adder using three different modeling
styles

Resources
PC installed with Verilog tools

Theory

Full adder is the basic combinational arithmetic block used in digital design the purpose of
this model is to take three inputs (input A, input B and carry in) and provide the two outputs
(sum and carryout).sum will be the arithmetic addition of all the three inputs and the carryout
will be the overflow of value in the sum.

Block Diagram:

Logical Expressions:
sum = a_in xor b_in xor c_in;
carry= (a_in.b_in) + (b_in.c_in)+(a_in.b_in);

Truth Table:

Inputs Outputs
a_in b_in c_in sum carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Table 1: Truth Table for Full Adder
MODELLING STYLES
(1). Data Flow description
Verilog Code:
module fulladder(a_in, b_in, c_in, sum, carry);
input a_in, b_in,c_in;
output sum, carry;
assign sum = a_in^b_in^c_in;
assign carry = (a_in & b_in) | (b_in & c_in) | (a_in & c_in);
endmodule

(2). Behavioral description

Verilog Code:
module fulladder(abc, sum, carry);
input [2:0] abc;
output sum,carry;
reg sum,carry;
always@(abc)
begin
case (abc)
3’b000:begin sum=1’b0; carry=1’b0;end
3’b001:begin sum=1’b1; carry=1’b0;end
3’b010:begin sum=1’b1; carry=1’b0;end
3’b011:begin sum=1’b0; carry=1’b1;end
3’b100:begin sum=1’b1; carry=1’b0;end
3’b101:begin sum=1’b0; carry=1’b1;end
3’b110:begin sum=1’b0; carry=1’b1;end
3’b111:begin sum=1’b1; carry=1’b1;end
endcase
end
endmodule

(3). Structural Description

Block diagram : (gate level description)

2
COE180.1
Verilog Code:
module fa(a_in, b_in, c_in, sum, carry);
input a_in, b_in, c_in;
output sum, carry;
wire s1, s2, s3;

xor x1 (s1, a_in, b_in);


and a1 (s2, a_in, b_in);
xor x2 (sum, s1, c_in);
and a2 (s2, s1, c_in);
or o1 (carry, s2, s3);
endmodule

Procedure
1. Create a module with required number of variables and mention its input/output for a full adder
circuit.
2. Implement the full adder using the 3 modelling styles: data flow description, behavioral
description and Structural description.
3. Create another module referred as test bench to verify the functionality of the 3 modelling styles.
You can create one test bench for the 3 styles. Base your test bench inputs from the truth table.
4. Follow the steps required to simulate the design and compare the obtained output with the
corresponding truth table.

Deliverables
*Supply the simulation for the above codes and the test bench code.

3
COE180.1

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