LTC3717-1

Wide Operating Range,

No RSENSETM Step-Down Controller
for DDR/QDR Memory Termination
U
FEATURES DESCRIPTIO
■ VOUT = 1/2 VREF The LTC®3717-1 is a synchronous step-down switching
■ Adjustable and Symmetrical Sink/Source regulator controller for double data rate (DDR) and Quad
Current Limit up to 20A Data RateTM (QDRTM) memory termination. The controller
■ True Current Mode Control with Optional Use of uses a valley current control architecture to deliver very
Sense Resistor low duty cycles with or without a sense resistor. Operating
■ VON and ION Pins Allow Constant Frequency frequency is selected by an external resistor and is com-
Operation During Input and Output Voltage Changes pensated for variations in VIN and VOUT.
■ ±0.65% Output Voltage Accuracy
■ Up to 97% Efficiency Forced continuous operation reduces noise and RF inter-
■ Ultrafast Transient Response ference. Output voltage is internally set to half of VREF,
■ 2% to 90% Duty Cycle at 200kHz which is user programmable.
■ tON(MIN) ≤ 100ns Fault protection is provided by an output overvoltage
■ Stable with Ceramic COUT comparator and optional short-circuit shutdown timer.
■ Power Good Output Voltage Monitor Soft-start capability for supply sequencing is accom-
■ Wide VIN Range: 4V to 36V plished using an external timing capacitor. The regulator
■ Adjustable Switching Frequency up to 1.5MHz current limit level is symmetrical and user programmable.
■ Output Overvoltage Protection Wide supply range allows operation from 4V to 36V at the
■ Optional Short-Circuit Shutdown Timer VCC input.
■ Available in a 5mm × 5mm QFN Package , LTC and LT are registered trademarks of Linear Technology Corporation.
U No RSENSE is a trademark of Linear Technology Corporation.

APPLICATIO S QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, Hitachi, IDT, Micron Technology, Inc. and Samsung.

■ Bus Termination: DDR and QDR Memory, SSTL,

HSTL, ...
■ Notebook Computers, Desktop Servers
■ Tracking/Margining Power Supply

U
TYPICAL APPLICATIO
VCC
5V TO 28V
715k
Efficiency vs Load Current
1µF VCC VIN
ION
2.5V TO 5.5V 100
0.1µF VREF VDD = 2.5V + 150µF VOUT = 1.25V
6.3V 90
RUN/SS TG Si7840DP B320A ×2 80 VIN = 5V
LTC3717-1
470pF SW VOUT 70 VIN = 2.5V
SENSE +
EFFICIENCY (%)

20k 0.22µF 1.25V

0.68µH 60
ITH BOOST + 180µF ±10A
CMDSH-3 4V 50
DRVCC ×2
SGND INTVCC 40
VON BG Si7840DP B320A
+ 30
4.7µF 20
PGOOD PGND
10
SENSE –
VFB 37171 F01a
0
0 2 4 6 8 10 12 14
LOAD CURRENT (A)

Figure 1. High Efficiency DDR Memory Termination Supply 37171 F01b

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LTC3717-1
W W W U U W U
ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
(Note 1)
Boosted Topside Driver Supply Voltage TOP VIEW

(BOOST) ............................................... 42V to – 0.3V

RUN/SS

BOOST
VIN, ION, SW, SENSE+ Voltage .................. 36V to – 0.3V

NC

NC
NC

NC
NC
TG
EXTVCC, DRVCC, RUN/SS, PGOOD, 32 31 30 29 28 27 26 25
VON 1 24 SW
(BOOST – SW) Voltages ............................ 7V to – 0.3V
PGOOD 2 23 SENSE+
VON, VREF, VRNG Voltages .......(INTVCC + 0.3V) to – 0.3V
VRNG 3 22 NC
ITH, VFB Voltages...................................... 2.7V to – 0.3V ITH 4 21 SENSE–
TG, BG, INTVCC, EXTVCC, DRVCC Peak Currents ....... 2A SGND 5
33
20 PGND
TG, BG, INTVCC, EXTVCC, DRVCC RMS Currents .. 50mA ION 6 19 BG
Operating Ambient Temperature VFB 7 18 DRVCC

Range (Note 4) ................................... – 40°C to 85°C NC 8 17 INTVCC

Junction Temperature (Note 2) ............................ 125°C 9 10 11 12 13 14 15 16

NC
VREF
NC
NC
NC
NC
EXTVCC
VIN
Storage Temperature Range ................. – 65°C to 125°C
Reflow Peak Body Temperature ............................ 260°C UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/ W
EXPOSED PAD IS SGND (PIN 33) MUST BE SOLDERED TO PCB

ORDER PART NUMBER QFN PART MARKING

LTC3717EUH-1 37171
Consult LTC Marketing for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Buck Regulator
IQ(VIN) Input DC Supply Current (VIN)
Normal 1000 2000 µA
Shutdown Supply Current VRUN/SS = 0V 15 30 µA
VFB Feedback Voltage Accuracy ITH = 1.2V (Note 3), VREF = 2.4V ● – 0.65 0.1 0.65 %
∆VFB(LINE) Feedback Voltage Line Regulation VIN = 4V to 36V, ITH = 1.2V (Note 3) 0.002 %/V
∆VFB(LOAD) Feedback Voltage Load Regulation ITH = 0.5V to 1.9V (Note 3) ● – 0.05 – 0.3 %
gm(EA) Error Amplifier Transconductance ITH = 1.2V (Note 3) 0.93 1.13 1.33 mS
tON On-Time ION = 30µA, VON = 0V 186 233 280 ns
ION = 60µA, VON = 0V 95 115 135 ns
tON(MIN) Minimum On-Time ION = 180µA 50 100 ns
tOFF(MIN) Minimum Off-Time 300 400 ns
VSENSE(MAX) Maximum Current Sense Threshold VRNG = 1V, VFB = VREF/2 – 50mV ● 108 135 162 mV
VPGND – VSW (Source) VRNG = 0V, VFB = VREF/2 – 50mV ● 76 95 114 mV
VRNG = INTVCC, VFB = VREF/2 – 50mV ● 148 185 222 mV
VSENSE(MIN) Minimum Current Sense Threshold VRNG = 1V, VFB = VREF/2 + 50mV ● –140 –165 –190 mV
VPGND – VSW (Sink) VRNG = 0V, VFB = VREF/2 + 50mV ● –97 –115 –133 mV
VRNG = INTVCC, VFB = VREF/2 + 50mV ● – 200 – 235 – 270 mV

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 LTC3717-1
ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN = 15V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
∆VFB(OV) Output Overvoltage Fault Threshold 8 10 12 %
VFB(UV) Output Undervoltage Threshold – 25 %
VRUN/SS(ON) RUN Pin Start Threshold ● 0.8 1.5 2 V
VRUN/SS(LE) RUN Pin Latchoff Enable RUN/SS Pin Rising 4 4.5 V
VRUN/SS(LT) RUN Pin Latchoff Threshold RUN/SS Pin Falling 3.5 4.2 V
IRUN/SS(C) Soft-Start Charge Current VRUN/SS = 0V – 0.5 –1.2 –3 µA
IRUN/SS(D) Soft-Start Discharge Current VRUN/SS = 4.5V, VFB = 0V 0.8 1.8 3 µA
VIN(UVLO) VIN Undervoltage Lockout VIN Falling ● 3.4 3.9 V
VIN Rising ● 3.5 4.0 V
TG RUP TG Driver Pull-Up On Resistance TG High (Note 5) 2 Ω
TG RDOWN TG Driver Pull-Down On Resistance TG Low (Note 5) 2 Ω
BG RUP BG Driver Pull-Up On Resistance BG High (Note 5) 3 Ω
BG RDOWN BG Driver Pull-Down On Resistance BG Low (Note 5) 1 Ω
TG tr TG Rise Time CLOAD = 3300pF 20 ns
TG tf TG Fall Time CLOAD = 3300pF 20 ns
BG tr BG Rise Time CLOAD = 3300pF 20 ns
BG tf BG Fall Time CLOAD = 3300pF 20 ns
Internal VCC Regulator
VINTVCC Internal VCC Voltage 6V < VCC < 30V, VEXTVCC = 4V ● 4.7 5 5.3 V
∆VLDO(LOADREG) Internal VCC Load Regulation ICC = 0mA to 20mA, VEXTVCC = 4V – 0.1 ±2 %
VEXTVCC EXTVCC Switchover Voltage ICC = 20mA, VEXTVCC Rising ● 4.5 4.7 V
∆VEXTVCC EXTVCC Switch Drop Voltage ICC = 20mA, VEXTVCC = 5V 150 300 mV
∆VEXTVCC(HYS) EXTVCC Switchover Hysteresis 200 mV
PGOOD Output
∆VFBH PGOOD Upper Threshold VFB Rising (0% = 1/3 VREF) 8 10 12 %
∆VFBL PGOOD Lower Threshold VFB Falling (0% = 1/3 VREF) –8 – 10 – 12 %
∆VFB(HYS) PGOOD Hysteresis VFB Returning (0% = 1/3 VREF) 1 2 %
VPGL PGOOD Low Voltage IPGOOD = 5mA 0.15 0.4 V

Note 1: Absolute Maximum Ratings are those values beyond which the life Note 4: The LTC3717EUH-1 is guaranteed to meet performance
of a device may be impaired. specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
Note 2: TJ is calculated from the ambient temperature TA and power operating temperature range are assured by design, characterization and
dissipation PD as follows: correlation with statistical process controls.
LTC3717EUH-1: TJ = TA + (PD • 34°C/W) Note 5: RDS(ON) limit guaranteed by design and/or correlation to static
Note 3: The LTC3717EUH-1 is tested in a feedback loop that adjusts VFB to test.
achieve a specified error amplifier output voltage (ITH).

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 LTC3717-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
VOUT/VIN Tracking Ratio
Efficiency vs Load Current vs Input Voltage Frequency vs Input Voltage
100 50.00 450
90 VIN = 2.5V
VOUT = 1.25V LOAD = 0A 400
49.95 LOAD = 10A
80
350
70 49.90

FREQUENCY (kHz)
300
EFFICIENCY (%)

LOAD = 1A

VOUT/VIN (%)
60
49.85 250
50 LOAD = 0A
LOAD = 10A
49.80 200
40
30 150
49.75
20 100
49.70 VOUT = 1.25V
10 FIGURE 1 CIRCUIT 50
FIGURE 1 CIRCUIT FIGURE 1 CIRCUIT
0 49.65 0
0.01 0.1 1 10 100 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
LOAD CURRENT (A) INPUT VOLTAGE (V) INPUT VOLTAGE (V)
37171 G01
37171 G02 37171 G03

Load-Step Transient Start-Up Response

VOUT
200mV/DIV VOUT
1V/DIV

IL IL
5A/DIV 2A/DIV

VIN = 2.5V 20µs/DIV 37171 G05 VIN = 2.5V 4ms/DIV 37171 G06

VOUT = 1.25V VOUT = 1.25V

LOAD = 500mA TO 10A STEP LOAD = 0.2Ω
FIGURE 1 CIRCUIT FIGURE 1 CIRCUIT

Load Regulation On-Time vs VON Voltage On-Time vs Temperature

0 1000 300
VIN = 2.5V IION = 30µA IION = 30µA
VOUT = 1.25V
–0.1 250
800

–0.2 200
∆VOUT/VOUT (%)

ON-TIME (ns)

ON-TIME (ns)

600
–0.3 150
400
–0.4 100

200
–0.5 50
FIGURE 1 CIRCUIT
–0.6 0 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 –50 –25 0 25 50 75 100 125
LOAD CURRENT (A) VON VOLTAGE (V) TEMPERATURE (°C)
37171 G04 37171 G07 37171 G08

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 LTC3717-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS
RUN/SS Latchoff Thresholds
On-Time vs ION Current INTVCC Load Regulation vs Temperature
10k 0 3
VVON = 0V

–0.1 2

FCB PIN CURRENT (µA)

1k PULL-DOWN CURRENT
ON-TIME (ns)

∆INTVCC (%)
–0.2 1

–0.3 0
100
PULL-UP CURRENT
–0.4 –1

10 –0.5 –2
1 10 100 0 10 20 30 40 50 –50 –25 0 25 50 75 100 125
ION CURRENT (µA) INTVCC LOAD CURRENT (mA) TEMPERATURE (°C)
37171 G09
37171 G10 37171 G11

RUN/SS Latchoff Thresholds Undervoltage Lockout Threshold Maximum Current Sense Threshold
vs Temperature vs Temperature vs VRNG Voltage
300

MAXIMUM CURRENT SENSE THRESHOLD (mV)

5.0 4.0
UNDERVOLTAGE LOCKOUT THRESHOLD (V)

250
4.5 3.5
RUN/SS THRESHOLD (V)

200
LATCHOFF ENABLE

4.0 3.0 150

100
3.5 2.5
LATCHOFF THRESHOLD 50

3.0 2.0 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 0.50 0.75 1.00 1.25 1.50 1.75 2.00
TEMPERATURE (°C) TEMPERATURE (C) VRNG (V)
37171 G12 37171 G13 37171 G14

Maximum Current Sense Threshold Maximum Current Sense Threshold Error Amplifier gm
vs RUN/SS Voltage, VRNG = 1V vs Temperature, VRNG = 1V vs Temperature
180
MAXIMUM CURRENT SENSE THRESHOLD (mV)

160 1.50
MAXIMUM CURRENT SENSE THRESHOLD (mV)

140 160 1.40

140
120 1.30
120
100 1.20
gm (mS)

100
80 1.10
80
60 1.00
60
40 0.90
40
20 20 0.80

0 0 0.70
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 –50 –30 –10 10 30 50 70 90 110 130 –50 –30 –10 10 30 50 70 90 110 130
RUN/SS (V) TEMPERATURE (°C) TEMPERATURE (°C)
37171 G15 37171 G16 37171 G17

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LTC3717-1
U U U
PI FU CTIO S
VON (Pin 1): On-Time Voltage Input. Voltage trip point for good threshold, and short-circuit shutdown threshold. Do
the on-time comparator. Tying this pin to the output not apply more than 3V on VREF. If higher voltages are
voltage makes the on-time proportional to VOUT. The used, connect an external resistor (R1 ≥ 160k) from
comparator input defaults to 0.7V when the pin is grounded, voltage reference to VREF.
2.4V when the pin is tied to INTVCC. EXTVCC (Pin 15): External VCC Input. When EXTVCC
PGOOD (Pin 2): Power Good Output. Open-drain logic exceeds 4.7V, an internal switch connects this pin to
output that is pulled to ground when the output voltage is INTVCC and shuts down the internal regulator so that
not within ±10% of the regulation point. controller and gate drive power is drawn from EXTVCC. Do
not exceed 7V at this pin and ensure that EXTVCC < VIN.
VRNG (Pin 3): Sense Voltage Range Input. The voltage at
this pin is ten times the nominal sense voltage at maxi- VIN (Pin 16): Main Input Supply. Decouple this pin to
mum output current and can be set from 0.5V to 2V by a PGND with an RC filter (1Ω, 0.1µF).
resistive divider from INTVCC. The nominal sense voltage
INTVCC (Pin 17): Internal Regulator Output. The control
defaults to 70mV when this pin is tied to ground, 140mV circuits are powered from this voltage when VIN is greater
when tied to INTVCC. than 5V. Decouple this pin to power ground with a mini-
ITH (Pin 4): Current Control Threshold and Error Amplifier mum of 4.7µF low ESR tantalum or ceramic capacitor.
Compensation Point. The current comparator threshold DRVCC (Pin 18): Voltage Supply to Bottom Gate Driver.
increases with this control voltage. The voltage ranges Normally connected to the INTVCC pin through a decoup-
from 0V to 2.4V with 0.8V corresponding to zero sense ling RC filter (1Ω/0.1µF). Decouple this pin to power ground
voltage (zero current). with a minimum of 4.7µF low ESR tantalum or ceramic
SGND (Pin 5)/Exposed Pad (Pin 33): Signal Ground. All capacitor. Do not exceed 7V at this pin.
small-signal components and compensation components BG (Pin 19): Bottom Gate Drive. Drives the gate of the
should connect to this ground, which in turn connects to bottom N-channel MOSFET between ground and DRVCC.
PGND at one point. Pin 5 is electrically connected to the
exposed pad. Exposed pad must be soldered to PCB. PGND (Pin 20): Power Ground. Connect these pins closely
to the source of the bottom N-channel MOSFET, the (–)
ION (Pin 6): On-Time Current Input. Tie a resistor from VIN terminal of CVCC and the (–) terminal of CIN.
to this pin to set the one-shot timer current and thereby set
the switching frequency. SENSE – (Pin 21): Negative Current Sense Comparator
Input. The (–) input to the current comparator is normally
VFB (Pin 7): Error Amplifier Feedback Input. This pin
connected to power ground unless using a resistive di-
connects to VOUT and divides its voltage to 2/3 • VFB vider from INTVCC (see Applications Information).
through precision internal resistors before it is applied to
the input of the error amplifier. Do not apply more than SENSE + (Pin 23): Positive Current Sense Comparator
1.5V on VFB. For higher output voltages, attach an external Input. The (+) input to the current comparator is normally
resistor R2 (1/2 • R1 at VREF) from VOUT to VFB. connected to the SW node unless using a sense resistor
(see Applications Information).
NC (Pins 8, 9, 11, 12, 13, 14, 22, 25, 26, 29, 30, 32): Do
Not Connect. SW (Pin 24): Switch Node. The (–) terminal of the boot-
strap capacitor CB connects here. This pin swings from a
VREF (Pin 10): Positive Input of Internal Error Amplifier. diode voltage drop below ground up to VIN.
This pin connects to an external reference and divides its
voltage to 1/3 VREF through precision internal resisters TG (Pin 27): Top Gate Drive. Drives the top N-channel
before it is applied to the positive input of the error MOSFET with a voltage swing equal to INTVCC superim-
amplifier. Reference voltage for output voltage, power posed on the switch node voltage SW.

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 LTC3717-1
U U U
PI FU CTIO S
BOOST (Pin 28): Boosted Floating Driver Supply. The (+) RUN/SS (Pin 31): Run Control and Soft-Start Input. A
terminal of the bootstrap capacitor CB connects here. This capacitor to ground at this pin sets the ramp time to full
pin swings from a diode voltage drop below INTVCC up to output current (approximately 3s/µF) and the time delay
VIN + INTVCC. for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.

U U W
FU CTIO AL DIAGRA
RON
VON VIN
+
1 6 ION 15 EXTVCC 16 VIN CIN
4.7V

+ – 0.8V
0.7V 2.4V REF

5V
REG

BOOST
28
TG CB
VVON
tON = (10pF) R 27 M1
IION
S Q SW
24
ON SENSE+ L1
20k
+ + 23 DB VOUT

ICMP IREV SWITCH INTVCC

LOGIC
– – 17
CVCC
DRVCC
SHDN 18 +
1.4V BG COUT
OV
19 M2
VRNG
PGND
3
× 20
SENSE –
21
0.7V
PGOOD
2
5.7µA

1
240k + 3/10VREF
Q2 UV
– R3
ITHB VFB
20k
7
R4
Q1 40k
+
Q5 SGND
OV 5
– 11/30VREF

SS RUN
– + SHDN
1.2µA
EA
+
–

+ –
0.6V 6V
R2 37171 FD01

80k
VREF 10 4 ITH CC1 31 RUN/SS CSS
RC 0.6V
R1
40k

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LTC3717-1
U
OPERATIO
Main Control Loop Furthermore, in an overvoltage condition, M1 is turned off
and M2 is turned on and held on until the overvoltage
The LTC3717-1 is a current mode controller for DC/DC
condition clears.
step-down converters. In normal operation, the top
MOSFET is turned on for a fixed interval determined by a Pulling the RUN/SS pin low forces the controller into its
one-shot timer OST. When the top MOSFET is turned off, shutdown state, turning off both M1 and M2. Releasing
the bottom MOSFET is turned on until the current com- the pin allows an internal 1.2µA current source to charge
parator ICMP trips, restarting the one-shot timer and initi- up an external soft-start capacitor CSS. When this voltage
ating the next cycle. Inductor current is determined by reaches 1.5V, the controller turns on and begins switch-
sensing the voltage between the SENSE+ and SENSE– pins ing, but with the ITH voltage clamped at approximately
using the bottom MOSFET on-resistance . The voltage on 0.6V below the RUN/SS voltage. As CSS continues to
the ITH pin sets the comparator threshold corresponding charge, the soft-start current limit is removed.
to inductor valley current. The error amplifier EA adjusts
INTVCC/EXTVCC Power
this ITH voltage by comparing 2/3 of the feedback signal
VFB from the output voltage with a reference equal to 1/3 Power for the top and bottom MOSFET drivers and most
of the VREF voltage. If the load current increases, it causes of the internal controller circuitry is derived from the
a drop in the feedback voltage relative to the reference. The INTVCC pin. The top MOSFET driver is powered from a
ITH voltage then rises until the average inductor current floating bootstrap capacitor CB. This capacitor is re-
again matches the load current. As a result in normal DDR charged from INTVCC through an external Schottky diode
operation VOUT is equal to 1/2 of the VREF voltage. DB when the top MOSFET is turned off. When the EXTVCC
pin is grounded, an internal 5V low dropout regulator
The operating frequency is determined implicitly by the
supplies the INTVCC power from VCC. If EXTVCC rises
top MOSFET on-time and the duty cycle required to
above 4.7V, the internal regulator is turned off, and an
maintain regulation. The one-shot timer generates an on-
time that is proportional to the ideal duty cycle, thus internal switch connects EXTVCC to INTVCC. This allows
holding frequency approximately constant with changes a high efficiency source connected to EXTVCC, such as an
in VIN. The nominal frequency can be adjusted with an external 5V supply or a secondary output from the
external resistor RON. converter, to provide the INTVCC power. Voltages up to
7V can be applied to EXTVCC for additional gate drive. If
Overvoltage and undervoltage comparators OV and UV the VCC voltage is low and INTVCC drops below 3.4V,
pull the PGOOD output low if the output feedback voltage undervoltage lockout circuitry prevents the power
exits a ±10% window around the regulation point. switches from turning on.

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 LTC3717-1
U U W U
APPLICATIO S I FOR ATIO
A typical LTC3717-1 application circuit is shown in the source of the bottom MOSFET M2 and ground. Con-
Figure 1. External component selection is primarily de- nect the SENSE + and SENSE – pins as a Kelvin connection
termined by the maximum load current and begins with to the sense resistor with SENSE + at the source of the
the selection of the sense resistance and power MOSFET bottom MOSFET and the SENSE – pin to PGND. Using a
switches. The LTC3717-1 uses the on-resistance of the sense resistor provides a well defined current limit, but
synchronous power MOSFET for determining the induc- adds cost and reduces efficiency. Alternatively, one can
tor current. The desired amount of ripple current and eliminate the sense resistor and use the bottom MOSFET
operating frequency largely determines the inductor value. as the current sense element by simply connecting the
Finally, CIN is selected for its ability to handle the large SENSE + pin to the drain and the SENSE – pin to the source
RMS current into the converter and COUT is chosen with of the bottom MOSFET. This improves efficiency, but one
low enough ESR to meet the output voltage ripple and must carefully choose the MOSFET on-resistance as dis-
transient specification. cussed in a later section.
Maximum Sense Voltage and VRNG Pin Power MOSFET Selection
Inductor current is determined by measuring the voltage The LTC3717-1 requires two external N-channel power
across a sense resistance that appears between the MOSFETs, one for the top (main) switch and one for the
SENSE + and SENSE – pins. The maximum sense voltage bottom (synchronous) switch. Important parameters for
is set by the voltage applied to the VRNG pin and is equal the power MOSFETs are the breakdown voltage V(BR)DSS,
to approximately (0.13)VRNG for sourcing current and threshold voltage V(GS)TH, on-resistance RDS(ON), reverse
(0.17)VRNG for sinking current. The current mode control transfer capacitance CRSS and maximum current IDS(MAX).
loop will not allow the inductor current valleys to exceed
The gate drive voltage is set by the 5V INTVCC supply.
(0.13)VRNG/RSENSE for sourcing current and (0.17)VRNG
Consequently, logic-level threshold MOSFETs must be
for sinking current. In practice, one should allow some
used in LTC3717-1 applications.
margin for variations in the LTC3717-1 and external
component values and a good guide for selecting the When the bottom MOSFET is used as the current sense
sense resistance is: element, particular attention must be paid to its
VRNG on-resistance. MOSFET on-resistance is typically speci-
RSENSE = fied with a maximum value RDS(ON)(MAX) at 25°C. In this
10 • IOUT (MAX) case, additional margin is required to accommodate the
when VRNG = 0.5 – 2V. rise in MOSFET on-resistance with temperature:
An external resistive divider from INTVCC can be used to RSENSE
set the voltage of the VRNG pin between 0.5V and 2V RDS(ON)(MAX) =
ρT
resulting in nominal sense voltages of 50mV to 200mV.
Additionally, the VRNG pin can be tied to SGND or INTVCC The ρT term is a normalization factor (unity at 25°C)
in which case the nominal sense voltage defaults to 70mV accounting for the significant variation in on-resistance
or 140mV, respectively. The maximum allowed sense with temperature, typically about 0.4%/°C as shown in
voltage is about 1.3 times this nominal value for positive Figure 2. For a maximum junction temperature of 100°C,
output current and 1.7 times the nominal value for nega- using a value ρT = 1.3 is reasonable.
tive output current.
The power dissipated by the top and bottom MOSFETs
Connecting the SENSE + and SENSE – Pins strongly depends upon their respective duty cycles and
the load current. During normal operation, the duty cycles
The LTC3717-1 can be used with or without a sense for the MOSFETs are:
resistor. When using a sense resistor, it is placed between

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LTC3717-1
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APPLICATIO S I FOR ATIO
2.0
set by the current into the ION pin and the voltage at the VON
pin according to:
ρT NORMALIZED ON-RESISTANCE

1.5
VVON
tON = (10pF )
1.0
IION
Tying a resistor RON from VIN to the ION pin yields an on-
0.5 time inversely proportional to VIN. For a step-down
converter, this results in approximately constant fre-
quency operation as the input supply varies:
0
– 50 0 50 100 150

[Hz]
JUNCTION TEMPERATURE (°C) VOUT
37171 F02
f=
VVONRON (10pF )
Figure 2. RDS(ON) vs. Temperature
To hold frequency constant during output voltage changes,
tie the VON pin to VOUT. The VON pin has internal clamps
VOUT that limit its input to the one-shot timer. If the pin is tied
D TOP = below 0.7V, the input to the one-shot is clamped at 0.7V.
VIN
Similarly, if the pin is tied above 2.4V, the input is clamped
V –V
DBOT = IN OUT at 2.4V.
VIN
Because the voltage at the ION pin is about 0.7V, the
The resulting power dissipation in the MOSFETs at maxi- current into this pin is not exactly inversely proportional to
mum output current are: VIN, especially in applications with lower input voltages.
PTOP = DTOP IOUT(MAX)2 ρT(TOP) RDS(ON)(MAX) To account for the 0.7V drop on the ION pin, the following
equation can be used to calculate frequency:
+ k VIN2 IOUT(MAX) CRSS f
PBOT = DBOT IOUT(MAX)2 ρT(BOT) RDS(ON)(MAX)
f=
(VIN − 0.7V) • VOUT
Both MOSFETs have I2R losses and the top MOSFET VVON • VIN • RON (10pF )
includes an additional term for transition losses, which are To correct for this error, an additional resistor RON2
largest at high input voltages. The constant k = 1.7A–1 can connected from the ION pin to the 5V INTVCC supply will
be used to estimate the amount of transition loss. The further stabilize the frequency.
bottom MOSFET losses are greatest when the bottom duty
cycle is near 100%, during a short-circuit or at high input 5V
voltage. RON2 = RON
0.7V
Operating Frequency Changes in the load current magnitude will also cause
frequency shift. Parasitic resistance in the MOSFET
The choice of operating frequency is a tradeoff between
switches and inductor reduce the effective voltage across
efficiency and component size. Low frequency operation
the inductance, resulting in increased duty cycle as the
improves efficiency by reducing MOSFET switching losses
load current increases. By lengthening the on-time slightly
but requires larger inductance and/or capacitance in order
as current increases, constant frequency operation can be
to maintain low output ripple voltage.
maintained. This is accomplished with a resistive divider
The operating frequency of LTC3717-1 applications is from the ITH pin to the VON pin and VOUT. The values
determined implicitly by the one-shot timer that controls required will depend on the parasitic resistances in the
the on-time tON of the top MOSFET switch. The on-time is specific application. A good starting point is to feed about
sn37171 37171fs

10
 LTC3717-1
U U W U
APPLICATIO S I FOR ATIO
RVON1 RVON1
30k 3k
VOUT VON VOUT VON
CVON RVON2 CVON
RVON2 0.01µF 10k 10k 0.01µF
100k LTC3717-1 LTC3717-1
INTVCC
RC RC
ITH Q1 ITH
2N5087
CC CC
37171 F03

(3a) (3b)

Figure 3. Adjusting Frequency Shift with Load Current Changes

25% of the voltage change at the ITH pin to the VON pin as or Kool Mµ® cores. A variety of inductors designed for high
shown in Figure 3a. Place capacitance on the VON pin to current, low voltage applications are available from manu-
filter out the ITH variations at the switching frequency. The facturers such as Sumida, Panasonic, Coiltronics, Coil-
resistor load on ITH reduces the DC gain of the error amp craft and Toko.
and degrades load regulation, which can be avoided by
using the PNP emitter follower of Figure 3b. Schottky Diode D1, D2 Selection
The Schottky diodes, D1 and D2, shown in Figure 1
Inductor L1 Selection
conduct during the dead time between the conduction of
Given the desired input and output voltages, the inductor the power MOSFET switches. It is intended to prevent the
value and operating frequency determine the ripple body diodes of the top and bottom MOSFETs from turning
current: on and storing charge during the dead time, which can
cause a modest (about 1%) efficiency loss. The diodes can
 V  V 
∆IL =  OUT   1 − OUT  be rated for about one half to one fifth of the full load current
 fL   VIN  since they are on for only a fraction of the duty cycle. In
order for the diode to be effective, the inductance between
Lower ripple current reduces cores losses in the inductor,
it and the bottom MOSFET must be as small as possible,
ESR losses in the output capacitors and output voltage
mandating that these components be placed adjacently.
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving The diodes can be omitted if the efficiency loss is tolerable.
this requires a large inductor. There is a tradeoff between CIN and COUT Selection
component size, efficiency and operating frequency.
The input capacitance CIN is required to filter the square
A reasonable starting point is to choose a ripple current wave current at the drain of the top MOSFET. Use a low
that is about 40% of IOUT(MAX). The largest ripple current ESR capacitor sized to handle the maximum RMS current.
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance VOUT VIN
should be chosen according to: IRMS ≅ IOUT (MAX) –1
VIN VOUT
 VOUT   VOUT 
L= 1 − This formula has a maximum at VIN = 2VOUT, where
 
 f ∆IL(MAX)   VIN(MAX)  IRMS = IOUT(MAX) / 2. This simple worst-case condition is
commonly used for design because even significant
Once the value for L is known, the type of inductor must be deviations do not offer much relief. Note that ripple
selected. High efficiency converters generally cannot af- current ratings from capacitor manufacturers are often
ford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy Kool Mµ is a registered trademark of Magnetics, Inc.
sn37171 37171fs

11
LTC3717-1
U U W U
APPLICATIO S I FOR ATIO
based on only 2000 hours of life which makes it advisable on, the switch node rises to VIN and the BOOST pin rises
to derate the capacitor. to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step top MOSFET. In most applications a 0.1µF to 0.47µF X5R
or X7R dielectric capacitor is adequate.
transients. The output ripple ∆VOUT is approximately
bounded by: Fault Condition: Current Limit
 1  The maximum inductor current is inherently limited in a
∆VOUT ≤ ∆IL  ESR + 
 8fC OUT  current mode controller by the maximum sense voltage. In
the LTC3717-1, the maximum sense voltage is controlled
Since ∆IL increases with input voltage, the output ripple is by the voltage on the VRNG pin. With valley current control,
highest at maximum input voltage. Typically, once the ESR the maximum sense voltage and the sense resistance
requirement is satisfied, the capacitance is adequate for determine the maximum allowed inductor valley current.
filtering and has the necessary RMS current rating. The corresponding output current limit is:
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements. VSNS(MAX) 1
ILIMITPOSITIVE = + ∆IL
Dry tantalum, special polymer, aluminum electrolytic and RDS(ON)ρT 2
ceramic capacitors are all available in surface mount VSNS(MIN) 1
packages. Special polymer capacitors offer very low ESR ILIMITNEGATIVE = − ∆IL
RDS(ON)ρT 2
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
The current limit value should be checked to ensure that
but it is important to only use types that have been surge
ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit
tested for use in switching power supplies. Aluminum
generally occurs with the largest VIN at the highest ambi-
electrolytic capacitors have significantly higher ESR, but
ent temperature, conditions that cause the largest power
can be used in cost-sensitive applications providing that
loss in the converter. Note that it is important to check for
consideration is given to ripple current ratings and long
self-consistency between the assumed MOSFET junction
term reliability. Ceramic capacitors have excellent low
temperature and the resulting value of ILIMIT which heats
ESR characteristics but can have a high voltage coeffi-
the MOSFET switches.
cient and audible piezoelectric effects. The high Q of
ceramic capacitors with trace inductance can also lead to Caution should be used when setting the current limit
significant ringing. When used as input capacitors, care based upon the RDS(ON) of the MOSFETs. The maximum
must be taken to ensure that ringing from inrush currents current limit is determined by the minimum MOSFET on-
and switching does not pose an overvoltage hazard to the resistance. Data sheets typically specify nominal and
power switches and controller. To dampen input voltage maximum values for RDS(ON), but not a minimum. A
transients, add a small 5µF to 50µF aluminum electrolytic reasonable assumption is that the minimum RDS(ON) lies
capacitor with an ESR in the range of 0.5Ω to 2Ω. High the same amount below the typical value as the maximum
performance through-hole capacitors may also be used, lies above it. Consult the MOSFET manufacturer for further
but an additional ceramic capacitor in parallel is recom- guidelines.
mended to reduce the effect of their lead inductance.
Minimum Off-time and Dropout Operation
Top MOSFET Driver Supply (CB, DB)
The minimum off-time tOFF(MIN) is the smallest amount of
An external bootstrap capacitor CB connected to the BOOST time that the LTC3717-1 is capable of turning on the
pin supplies the gate drive voltage for the topside MOSFET. bottom MOSFET, tripping the current comparator and
This capacitor is charged through diode DB from INTVCC turning the MOSFET back off. This time is generally about
when the switch node is low. When the top MOSFET turns sn37171 37171fs

12
 LTC3717-1
U U W U
APPLICATIO S I FOR ATIO
250ns. The minimum off-time limit imposes a maximum BOOST DRVCC

duty cycle of tON/(tON + tOFF(MIN)). If the maximum duty Q1 Q3

FMMT619 FMMT619
cycle is reached, due to a dropping input voltage for 10Ω 10Ω
GATE GATE
example, then the output will drop out of regulation. The TG
OF M1
BG
OF M2
Q2 Q4
minimum input voltage to avoid dropout is: FMMT720 FMMT720

tON + tOFF(MIN) SW PGND

VIN(MIN) = VOUT
37171 F05

tON
Figure 5. Optional External Gate Driver
Output Voltage Programming
Soft-Start and Latchoff with the RUN/SS Pin
When VFB is connected to VOUT, the output voltage is
regulated to one half of the voltage at the VREF pin. A The RUN/SS pin provides a means to shut down the
resistor connected between VFB and VOUT can be used to LTC3717-1 as well as a timer for soft-start and overcur-
further adjust the output voltage according to the follow- rent latchoff. Pulling the RUN/SS pin below 0.8V puts the
ing equation: LTC3717-1 into a low quiescent current shutdown
(IQ < 30µA). Releasing the pin allows an internal 1.2µA
 60k + RFB  current source to charge up the external timing capacitor
VOUT = VREF   CSS. If RUN/SS has been pulled all the way to ground,
 120k 
there is a delay before starting of about:
If VREF exceeds 3V, resistors should be placed in series
with the VREF pin and the VFB pin to avoid exceeding the tDELAY =
1.5V
1.2µA
(
C SS = 1.3s/µF C SS )
input common mode range of the internal error amplifier.
To maintain the VOUT = VREF/2 relationship, the resistor in When the voltage on RUN/SS reaches 1.5V, the LTC3717-
series with the VREF pin should be made twice as large as 1 begins operating with a clamp on ITH of approximately
the resistor in series with the VFB pin. 0.9V. As the RUN/SS voltage rises to 3V, the clamp on ITH
is raised until its full 2.4V range is available. This takes an
RFB
249k additional 1.3s/µF, during which the load current is folded
VOUT VFB
back. During start-up, the maximum load current is re-
RFB LTC3717-1 duced until either the RUN/SS pin rises to 3V or the output
VREF
499k
VREF
reaches 75% of its final value. The pin can be driven from
37171 F04 logic as shown in Figure 6. Diode D1 reduces the start
delay while allowing CSS to charge up slowly for the soft-
Figure 4 start function.
INTVCC

External Gate Drive Buffers VIN

RSS*

3.3V OR 5V RUN/SS RUN/SS

The LTC3717-1 drivers are adequate for driving up to RSS*
D2*

about 30nC into MOSFET switches with RMS currents of D1

50mA. Applications with larger MOSFET switches or oper- CSS

CSS

ating at frequencies requiring greater RMS currents will 37171 F06

benefit from using external gate drive buffers such as the *OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF
LTC1693. Alternately, the external buffer circuit shown in
Figure 5 can be used. Note that the bipolar devices reduce (6a) (6b)
the signal swing at the MOSFET gate. Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated
sn37171 37171fs

13
LTC3717-1
U U W U
APPLICATIO S I FOR ATIO
After the controller has been started and given adequate high frequency of operation may cause the LTC3717-1 to
time to charge up the output capacitor, CSS is used as a exceed its maximum junction temperature rating or RMS
short-circuit timer. After the RUN/SS pin charges above current rating. Most of the supply current drives the
4V, if the output voltage falls below 75% of its regulated MOSFET gates unless an external EXTVCC source is used.
value, then a short-circuit fault is assumed. A 1.8µA cur- In continuous mode operation, this current is IGATECHG =
rent then begins discharging CSS. If the fault condition f(Qg(TOP) + Qg(BOT)). The junction temperature can be
persists until the RUN/SS pin drops to 3.5V, then the con- estimated from the equations given in Note 2 of the
troller turns off both power MOSFETs, shutting down the Electrical Characteristics. For example, the LTC3717EUH-1
converter permanently. The RUN/SS pin must be actively is limited to less than 14mA from a 30V supply:
pulled down to ground in order to restart operation. TJ = 70°C + (14mA)(30V)(34°C/W) = 84.3°C
The overcurrent protection timer requires that the soft- For larger currents, consider using an external supply with
start timing capacitor CSS be made large enough to guar- the EXTVCC pin.
antee that the output is in regulation by the time CSS has
reached the 4V threshold. In general, this will depend upon EXTVCC Connection
the size of the output capacitance, output voltage and load
current characteristic. A minimum soft-start capacitor can The EXTVCC pin can be used to provide MOSFET gate drive
be estimated from: and control power from the output or another external
source during normal operation. Whenever the EXTVCC
CSS > COUT VOUT RSENSE (10 – 4 [F/V s]) pin is above 4.7V the internal 5V regulator is shut off and
Generally 0.1µF is more than sufficient. an internal 50mA P-channel switch connects the EXTVCC
pin to INTVCC. INTVCC power is supplied from EXTVCC until
Overcurrent latchoff operation is not always needed or this pin drops below 4.5V. Do not apply more than 7V to
desired. The feature can be overridden by adding a pull- the EXTVCC pin and ensure that EXTVCC ≤ VCC. The follow-
up current greater than 5µA to the RUN/SS pin. The ing list summarizes the possible connections for EXTVCC:
additional current prevents the discharge of C SS during a
fault and also shortens the soft-start period. Using a 1. EXTVCC grounded. INTVCC is always powered from the
resistor to VIN as shown in Figure 6a is simple, but slightly internal 5V regulator.
increases shutdown current. Connecting a resistor to 2. EXTVCC connected to an external supply. A high effi-
INTVCC as shown in Figure 6b eliminates the additional ciency supply compatible with the MOSFET gate drive
shutdown current, but requires a diode to isolate CSS. Any requirements (typically 5V) can improve overall
pull-up network must be able to pull RUN/SS above the efficiency.
4.2V maximum threshold of the latchoff circuit and over-
come the 4µA maximum discharge current. 3. EXTVCC connected to an output derived boost network.
The low voltage output can be boosted using a charge
INTVCC Regulator pump or flyback winding to greater than 4.7V. The system
will start-up using the internal linear regulator until the
An internal P-channel low dropout regulator produces the boosted output supply is available.
5V supply that powers the drivers and internal circuitry
within the LTC3717-1. The INTVCC pin can supply up to Efficiency Considerations
50mA RMS and must be bypassed to ground with a
minimum of 4.7µF tantalum or other low ESR capacitor. The percent efficiency of a switching regulator is equal to
Good bypassing is necessary to supply the high transient the output power divided by the input power times 100%.
currents required by the MOSFET gate drivers. Applica- It is often useful to analyze individual losses to determine
tions using large MOSFETs with a high input voltage and

sn37171 37171fs

14
 LTC3717-1
U U W U
APPLICATIO S I FOR ATIO
what is limiting the efficiency and which change would Checking Transient Response
produce the most improvement. Although all dissipative The regulator loop response can be checked by looking
elements in the circuit produce losses, four main sources at the load transient response. Switching regulators take
account for most of the losses in LTC3717-1 circuits: several cycles to respond to a step in load current. When
1. DC I2R losses. These arise from the resistances of the a load step occurs, VOUT immediately shifts by an amount
MOSFETs, inductor and PC board traces and cause the equal to ∆ILOAD (ESR), where ESR is the effective series
efficiency to drop at high output currents. In continuous resistance of COUT. ∆ILOAD also begins to charge or
mode the average output current flows through L, but is discharge COUT generating a feedback error signal used
chopped between the top and bottom MOSFETs. If the two by the regulator to return VOUT to its steady-state value.
MOSFETs have approximately the same RDS(ON), then the During this recovery time, VOUT can be monitored for
resistance of one MOSFET can simply be summed with the overshoot or ringing that would indicate a stability
resistances of L and the board traces to obtain the DC I2R problem. The ITH pin external components shown in
loss. For example, if RDS(ON) = 0.01Ω and RL = 0.005Ω, the Figure 1 will provide adequate compensation for most
loss will range from 1% up to 10% as the output current applications. For a detailed explanation of switching
varies from 1A to 10A for a 1.5V output. control loop theory see Application Note 76.
2. Transition loss. This loss arises from the brief amount Design Example
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input As a design example, take a supply with the following
voltage, load current, driver strength and MOSFET capaci- specifications: VIN = VREF = 2.5V, VEXTVCC = 5V, VOUT =
tance, among other factors. The loss is significant at input 1.25V ±5%, IOUT(MAX) = 10A, f = 250kHz. First, calculate
voltages above 20V and can be estimated from: the timing resistor with VON = VOUT:
Transition Loss ≅ (1.7A–1) VIN2 IOUT CRSS f 1.25V(2.5V – 0.7V)
RON = = 514kΩ
3. INTVCC current. This is the sum of the MOSFET driver (0.7V)(250kHz)(10pF )2.5V
and control currents.
and choose the inductor for about 40% ripple current at
4. CIN loss. The input capacitor has the difficult job of the maximum VIN:
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and 1.25V  1.25V 
sufficient capacitance to prevent the RMS current from L=  1−  = 0.63µH
(250kHz)(0.4)(10A)  2.5V 
causing additional upstream losses in fuses or batteries.
Other losses, including COUT ESR loss, Schottky diode D1 Selecting a standard value of 0.68µH results in a maximum
conduction loss during dead time and inductor core loss ripple current of:
generally account for less than 2% additional loss.
1.25V  1.25V 
When making adjustments to improve efficiency, the input ∆IL = 1–  = 3.7A
current is the best indicator of changes in efficiency. If you (250kHz)(0.68µH)  2.5V 
make a change and the input current decreases, then the
Next, choose the synchronous MOSFET switch. Choosing
efficiency has increased. If there is no change in input
a Si4874 (RDS(ON) = 0.0083Ω (NOM) 0.010Ω (MAX),
current, then there is no change in efficiency.
θJA = 40°C/W) yields a nominal sense voltage of:
VSNS(NOM) = (10A)(1.3)(0.0083Ω) = 108mV

sn37171 37171fs

15
LTC3717-1
U U W U
APPLICATIO S I FOR ATIO
Tying VRNG to 1.1V will set the current sense voltage range 0.013Ω to minimize output voltage changes due to induc-
for a nominal value of 110mV with current limit occurring tor ripple current and load steps. For current sinking
at 143mV. To check if the current limit is acceptable, applications where current flows back to the input through
assume a junction temperature of about 40°C above a the top transistor, output capacitors with a similar amount
70°C ambient with ρ110°C = 1.4: of bulk C and ESR should be placed on the input as well.
(This is typically the case, since VIN is derived from
143mV 1 another DC/DC converter.) The ripple voltage will be only:
ILIMIT ≥ + (3.7A) = 12.1A
(1.4)(0.010Ω) 2 ∆VOUT(RIPPLE) = ∆IL(MAX) (ESR)
= (4A) (0.013Ω) = 52mV
and double check the assumed TJ in the MOSFET:
However, a 0A to 10A load step will cause an output
2.5V – 1.25V change of up to:
PBOT = (12.1A)2 (1.4)(0.010Ω) = 1.02 W
2.5V
∆VOUT(STEP) = ∆ILOAD (ESR) = (10A) (0.013Ω) = 130mV
TJ = 70°C + (1.02W)(40°C/W) = 111°C
An optional 22µF ceramic output capacitor is included to
Because the top MOSFET is on roughly the same amount minimize the effect of ESL in the output ripple. The
of time as the bottom MOSFET, the same Si4874 can be complete circuit is shown in Figure 7.
used as the synchronous MOSFET.
PC Board Layout Checklist
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful When laying out a PC board follow one of the two sug-
attention to heat sinking will be necessary in this circuit. gested approaches. The simple PC board layout requires
a dedicated ground plane layer. Also, for higher currents,
CIN is chosen for an RMS current rating of about 5A at it is recommended to use a multilayer board to help with
85°C. The output capacitors are chosen for a low ESR of heat sinking power components.

CSS DB
0.1µF CMDSH-3
RUN/SS BOOST VIN = 2.5V
R3 R4 RPG CB D2
CIN + CIN
11k 39k 100k 0.22µF 22µF 180µF
M1 B320A 6.3V 4V
PGOOD TG
Si4874 X7R ×2 VOUT
LTC3717-1 1.25V
CC1 VRNG SW L1 ±10A
RC 0.68µH + COUT1-2 COUT3
470pF SENSE +
20k 270µF 22µF
ITH PGND M2 D1 2V 6.3V
CC2 Si4874 B320A ×2 X7R
SENSE –
100pF
SGND BG
CON 0.01µF VON CVCC
+ 4.7µF
ION INTVCC
DRVCC RF
1Ω
VFB VCC VEXT 5V
CF
0.1µF
VREF EXTVCC
RON (OPT)
511k 0.1µF
10Ω

37171 F07

CIN, COUT1-2: CORNELL DUBILIER ESRE181E04B

L1: SUMIDA CEP125-0R68MC-H

Figure 7. Design Example: 1.25V/±10A at 250kHz

sn37171 37171fs

16
 LTC3717-1
U U W U
APPLICATIO S I FOR ATIO
• The ground plane layer should not have any traces and When laying out a printed circuit board, without a ground
it should be as close as possible to the layer with power plane, use the following checklist to ensure proper opera-
MOSFETs. tion of the controller. These items are also illustrated in
• Place CIN, COUT, MOSFETs, D1 and inductor all in one Figure 8.
compact area. It may help to have some components on • Segregate the signal and power grounds. All small
the bottom side of the board. signal components should return to the SGND pin at
• Place LTC3717-1 chip with Pins 15 to 28 facing the one point which is then tied to the PGND pin close to the
power components. Keep the components connected source of M2.
to Pins 1 to 10 close to LTC3717-1 (noise sensitive • Place M2 as close to the controller as possible, keeping
components). the PGND, BG and SW traces short.
• Use an immediate via to connect the components to • Connect the input capacitor(s) CIN close to the power
ground plane including SGND and PGND of LTC3717-1. MOSFETs. This capacitor carries the MOSFET AC cur-
Use several bigger vias for power components. rent.
• Use compact plane for switch node (SW) to improve • Keep the high dV/dT SW, BOOST and TG nodes away
cooling of the MOSFETs and to keep EMI down. from sensitive small-signal nodes.
• Use planes for VIN and VOUT to maintain good voltage • Connect the INTVCC and DRVCC decoupling capacitor
filtering and to keep power losses low. CVCC closely to the INTVCC, DRVCC and PGND pins.
• Flood all unused areas on all layers with copper. Flood- • Connect the top driver boost capacitor CB closely to the
ing with copper will reduce the temperature rise of BOOST and SW pins.
power component. You can connect the copper areas to • Connect the VCC pin decoupling capacitor CF closely to
any DC net (VIN, VOUT, GND or to any other DC rail in
the VCC and PGND pins.
your system).

CSS CB
L
RUN/SS BOOST

PGOOD TG
LTC3717-1 DB
VRNG SW +
CC1 M1
RC SENSE +
ITH PGND
CC2 SENSE – D2 VIN
SGND BG M2 D1 CIN
CION CVCC
VON –
ION INTVCC
+

CFB DRVCC –
VFB VCC CF COUT VOUT
+
RF
VREF EXTVCC

RON

37171 F08
BOLD LINES INDICATE HIGH CURRENT PATHS

Figure 8. LTC3717-1 Layout Diagram

sn37171 37171fs

17
LTC3717-1
U
TYPICAL APPLICATIO S
1.5V/±10A at 300kHz from 5V to 28V Input

CSS DB
0.1µF CMDSH-3
VIN
RUN/SS BOOST
RR1 RR2 RPG CB CIN 5V TO 28V
11k 39k 100k 0.22µF B320A 10µF
M1
PGOOD TG 35V
IRF7811W
×3 VOUT
LTC3717-1
1.5V
L1
CC1 VRNG SW ±10A
1.2µH COUT
680pF RC
SENSE + + 270µF
20k M2
ITH PGND D1 2V
IRF7822 B320A ×2
CC2 SENSE –
100pF
SGND BG
CON 0.01µF VON CVCC
4.7µF
ION INTVCC
DRVCC
VFB VCC

VREF 3V VREF EXTVCC

10µF RON
6.3V 510k
X7R

37171 TA01
COUT: CORNELL DUBILIER ESRE271M02B

High Voltage Half (VIN) Power Supply

CSS DB
0.1µF CMDSH-3
VIN
RUN/SS BOOST
RPG CIN 5V TO 25V
CB
100k 0.22µF 10µF
M1
PGOOD TG 25V
FDS6680S
×2 VOUT
LTC3717-1 VIN/2
VRNG SW L1 ±6A
CC1
1.8µH
470pF RC SENSE + + COUT1 COUT2
20k M2 270µF 10µF
ITH PGND
FDS6680S 16V 15V
CC2 SENSE –
100pF
SGND BG
CON 0.01µF VON CVCC
4.7µF
ION INTVCC
DRVCC RF
1Ω
VFB VCC
CF
0.1µF
VREF EXTVCC
RON
510k
R2 R1 2M
1M
C2
2200pF
37171 TA02
CIN: TAIYO YUDEN TMK432BJ106MM
COUT1: SANYO, OS-CON 16SP270
COUT2: TAIYO YUDEN JMK316BJ106ML
L1: TOKO 919AS-1R8N

sn37171 37171fs

18
 LTC3717-1
U
PACKAGE DESCRIPTIO
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)

0.57 ±0.05

5.35 ±0.05
4.20 ±0.05
3.45 ±0.05
(4 SIDES)

PACKAGE OUTLINE

0.23 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT BOTTOM VIEW—EXPOSED PAD

0.75 ± 0.05 R = 0.115 0.40 ± 0.10

5.00 ± 0.10
TYP
(4 SIDES) 31 32
0.00 – 0.05

PIN 1
TOP MARK
1
2

3.45 ± 0.10
(4-SIDES)

(UH) QFN 0102

0.200 REF 0.23 ± 0.05

0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED

sn37171 37171fs

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19
LTC3717-1
U
TYPICAL APPLICATIO
Typical Application 1.25V/±3A at 1.4MHz

CSS DB
0.1µF CMDSH-3
VIN
RUN/SS BOOST
RPG CB + CIN
2.5V
100k 0.22µF M1 120µF
PGOOD TG L1
1/2 Si9802 0.7µH 4V
VOUT
LTC3717-1
1.25V
CC1 VRNG SW ±3A
470pF RC SENSE + + COUT
33k M2 120µF
ITH PGND
1/2 Si9802 4V
CC2 SENSE –
100pF
SGND BG
CON, 0.01µF CVCC
VON
4.7µF
ION INTVCC
DRVCC
VFB VCC 5V

VREF EXTVCC
RON 1µF
92k

3717 TA03

CIN, COUT: CORNELL DUBILIER ESRD121M04B

L1: TOKO A921CY-0R7M

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Burst Mode is a registered trademark of Linear Technology Corporation.
sn37171 37171fs

LT/TP 0603 1K • PRINTED IN USA

20 Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417
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