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2-3 Intro To Protected Mode Memory Addressing: Descriptor From A Descriptor Table

The document discusses memory addressing in protected mode and paging. Protected mode allows access to memory above 1MB using segment selectors and descriptors from descriptor tables. Memory paging maps linear addresses to physical addresses using page directories and page tables. It also describes calculating linear addresses and the translation lookaside buffer cache.

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8 views

2-3 Intro To Protected Mode Memory Addressing: Descriptor From A Descriptor Table

The document discusses memory addressing in protected mode and paging. Protected mode allows access to memory above 1MB using segment selectors and descriptors from descriptor tables. Memory paging maps linear addresses to physical addresses using page directories and page tables. It also describes calculating linear addresses and the translation lookaside buffer cache.

Uploaded by

joselazaro.2037
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Chapter

Chapter2:2: The
TheMicroprocessor
Microprocessorand
andits
itsArchitecture
Architecture

2–3 INTRO TO PROTECTED MODE


MEMORY ADDRESSING
• Allows access to data and programs located
within & above the first 1M byte of memory.
• Protected mode is where Windows operates.
• In place of a segment address, the segment
register contains a selector that selects a
descriptor from a descriptor table.

١
Selectors and Descriptors
• The descriptor is located in the segment
register & describes the location, length, and
access rights of the segment of memory.
– it selects one of 8192 descriptors from one
of two tables of descriptors
• In protected mode, this segment number can
address any memory location in the system
for the code segment.
• Indirectly, the register still selects a memory
segment, but not directly as in real mode.

• Global descriptors contain segment


definitions that apply to all programs.
• Local descriptors are usually unique to an
application.
– a global descriptor might be called a system
descriptor, and local descriptor an application
descriptor
• Figure 2–6 shows the format of a descriptor
for the 80286 through the Core2.
– each descriptor is 8 bytes in length
– global and local descriptor tables are a
maximum of 64K bytes in length

٢
Figure 2–6 The 80286 through Core2 64-bit descriptors.

• The base address of the descriptor indicates


the starting location of the memory segment.
– the paragraph boundary limitation is removed in
protected mode
– segments may begin at any address
• The G, or granularity bit allows a segment
length of 4K to 4G bytes in steps of 4K bytes.

• Descriptors are chosen from the descriptor


table by the segment register.

٣
Figure 2–8 The contents of a segment register during protected mode
operation of the 80286 through Core2 microprocessors.

• The TI bit selects either the global or the local


descriptor table.
• Requested Privilege Level (RPL) requests
the access privilege level of a memory
segment.
– If the requested privilege level matches or is
higher in priority than the privilege level set by the
access rights byte, access is granted.

٤
Figure 2–9 Using the DS register to select a description from the global
descriptor table. In this example, the DS register accesses memory locations
00100000H–001000FFH as a data segment.

٥
• DS contains 0008H, which accesses the
descriptor number 1 from the global
descriptor table using a requested
privilege level of 00.
• Descriptor number 1 contains a descriptor
that defines the base address as
00100000H with a segment limit of
000FFH.
• This means that a value of 0008H loaded
into DS causes the microprocessor to use
memory locations 00100000H–
001000FFH

2–4 MEMORY PAGING

• The memory paging mechanism allows any


physical memory location to be assigned to
any linear address.
• Iinear address is defined as the address
generated by a program.
• Physical address is the actual memory
location accessed by a program.
• With memory paging, the linear address is
invisibly translated to any physical address.

٦
• The linear address, as generated by software,
is broken into three sections that are used to
access the page directory entry, page table
entry, and memory page offset address.

• Figure 2–12 shows the linear address and its


makeup for paging.

Figure 2–12 The format for the linear address (a) and a
page directory or page table entry (b).

٧
Calculating Linear Addresses
• Given a segment address, multiply it by 16
(10H) (add a hexadecimal zero to the
right), and add it to the offset.
• Example: convert 08F1:0100 to a linear
address
- Adjusted Segment value: 0 8 F 1 0
- Add the offset: 0 1 0 0
- Linear address: 0 9 0 1 0

The Page Directory and Page


Table
• Only one page directory in the system.
• Page directory and each page table are 4K
bytes in length.
• Figure 2–13 shows the page directory, a few
page tables, and some memory pages.

٨
Figure 2–13 The paging mechanism in the 80386 through
Core2 microprocessors.

• Intel has incorporated a special type of cache


called TLB (translation look-aside buffer).

• The 80486 cache holds the 32 most recent


page translation addresses.
– if the same area of memory is accessed, the
address is already present in the TLB
– This speeds program execution

٩
١٠

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