University of Tripoli

Faculty of Engineering
Electrical and Electronic Engineering Department

EE331N – Digital Laboratory

Fall 2022 |2023

Report of the Experiment #7

D and J-K Flip-Flops
With Pre-Lab (Questions)

‫ محمد مصطفى كميل‬: ‫اإلسم‬

0652022212 : ‫رقم القيد‬
)3( : ‫المجموعة‬
‫ أحمد الدويب‬.‫ د‬: ‫تحت اشراف‬
Pg. 01 Introduction

Introduction
Sequential circuit is consists of a combinational circuit to which memory elements are connected to
form a feedback path. The memory elements used in clocked sequential circuits are called flip-
flops.

A flip-flop is a binary storage device capable of storing one bit of information. In a stable state, the
output of a flip-flop is either 0 or 1. A sequential circuit may use many flip-flops to store as many
bits as necessary.

Figure 1. Block diagram of sequential circuit

The output of a combinational circuit depends on only the inputs to the circuit; the output of a
sequential circuit depends on the inputs to the circuit and the present state of the storage
elements.

D Flip-Flop
The D flip-flop holds the value given as its input until the input changes. It thus stores data. Since it
is activated by the clock pulse, it samples the input data only when the positive edge of the clock
pulse occurs.

Figure 2. D Flip-Flop symbol

Pg. 02 Introduction

D CLK Q(t+1)
0 1 0 Set
1 1 1 Reset

Table 1. Truth table of D Flip-Flop

There is another version of the D flip-flop, known as the D latch. The primary difference between
the two is the "edge triggering" feature of the D flip-flop, absent in the D Latch.

J-K Flip-Flop
The J-K flip-flop using a clock pulse to control the change of state of the flip-flop synchronizes its
operation with the rest of the circuit. This avoids the "race condition" that can occur with the RS
flip-flop. The device is triggered by the negative edge of the clock pulse.

Figure 3. J-K Flip-Flop symbol

J K CLK Q(t+1)
0 0 1 No change
0 1 1 0 Reset
1 0 1 1 Set
1 1 1 toggle

Table 2. Truth table of J-K Flip-Flop

Pg. 03 D and J-K Flip-Flops Lab

D and J-K Flip-Flops Lab

Objectives
• The purpose of this experiment is to examine the operation two types of Flip-flops (D and
J-K Flip-Flops).

Equipment List
 Digital breadboard
 1 Chip – IC 7404 (Inverter)
 1 Chip – IC 7474 (Dual D Flip-Flop)
 1 Chip – IC 7476 (Dual J-K Flip-Flop)
 Power supply 5V
 Wires

Procedure

1) We construct the D flip-flop by using the IC 7474 and realized the truth table in Table (1).

Figure 4. D flip-flop by using the IC 7474 (using MULTISIM)

Pg. 04 D and J-K Flip-Flops Lab

2) Then we examine the effect of CLR and PRE control signals for the step (1).

Figure 5.a. When PRE = 0 & CLR = 1, the Q lamp is ON (using MULTISIM)

Figure 5.b. When PRE = 1 & CLR = 0, the Q lamp is OFF (using MULTISIM)

3) We construct the J-K flip-flop by using the IC 7476 and realized the truth table in Table (2).

Figure 6. J-K flip-flop by using the IC 7476 (using MULTISIM)

Pg. 05 D and J-K Flip-Flops Lab

4) For convert J-K to D Flip-Flop, we connect the inverter IC 7404 between J and K.

Figure 7. Conversion from J-K flip-flop to D flip-flop (using MULTISIM)

Result
 The realization of the design is true for D and J-K Flip-Flops.
 When switch CLR is 0 (in our case, CLR is active low) the data the outputs of the flip-flop are
always zero. When switch PRE is 0 (in our case, PRE is low active) the data the outputs of the
flip-flop are always one.

Conclusion
 Flip-Flops is a circuit that maintains a state until directed by input to change the state. The Flip-
Flops is a fundamental components of sequential circuits in digital systems.
 CLR and PRE signals are Active low, i.e. they triggered on a negative going pulse edge.
 In D flip-flop, the output Q can only be changed at the clock edge, and if the input changes at
other pulses (times), the output Q will be unaffected.
 In J-K flip-flop, if J and K are different, then the output Q takes the value of J at the next clock
edge. If J and K are both low, then no change occurs. If J and K are both high at the clock edge,
then the output will toggle from one state to the other.
 The D flip-flop is widely used an electronic temporary memory component.
 J-K Flip-Flops makes the circuit toggle between two states and is widely used is shift registers,
counters and more computer applications.
Pg. 06 Pre – Lab (Questions)

Pre – Lab (Questions)

Question 1:

Flip-Flop is a binary storage device capable of storing one bit of information. In a

stable state, the output of a flip-flop is either 0 or 1.

Question 2:

D CLK Q(t+1)
0 1 0 Set
1 1 1 Reset

Table 1. Truth table of D Flip-Flop

J K CLK Q(t+1)
0 0 1 No change
0 1 1 0 Reset
1 0 1 1 Set
1 1 1 toggle

Table 2. Truth table of J-K Flip-Flop

Question 3:

- The D Flip-Flops are widely used an electronic temporary memory component.

- J-K Flip-Flops makes the circuit toggle between two states and is widely used is
shift registers, counters and more computer applications.
Pg. 07 Pre – Lab (Questions)

Question 4:

CLR (Clear): drives the Flip-Flop output Q to a set state.

PRE (Preset): drives the Flip-Flop output Q to a reset state.

Question 5:

J K Q(t) Q(t+1) D
0 X 0 0 0
X 1 1 0 0
1 X 0 1 1
X 0 1 1 1

0 1 Using K-map:

0 X 𝐽=𝐷

1 1 X 𝐾 = 𝐷’

0 1

0 X 1

1 X
Pg. 08 Pre – Lab (Questions)

Question 6:

The data inputs to Flip-Flops (D or J, K) are referred to as synchronous inputs because

they have an effect on the output Q only in sync, with the clock signal.

Asynchronous inputs have control over the output Q regardless of clock input status.
These inputs are called the preset (PRE) and the clear (CLR).