Lab 6: SystemVerilog Assertions

Table of Contents
1. The Concept of Assertions..........................................................................................................................................1
2. Types of Assertions......................................................................................................................................................2
3. Concurrent Assertions................................................................................................................................................3
3.1 Concurrent Assertions Layers..................................................................................................................................3
3.1.1 Concurrent Assertions Example........................................................................................................................4
3.2 Implication...........................................................................................................................................................5
3.3 Sequence cycle delay operator............................................................................................................................5
3.4 Combing Sequences.............................................................................................................................................6
3.5 Assertion System Functions................................................................................................................................7
3.5.1 Assertion System Functions Example...............................................................................................................8
3.6 Assertion Directives.............................................................................................................................................9
3.7 Local variables in A sequence...........................................................................................................................10
4 Assignment.................................................................................................................................................................10
 1. The Concept of Assertions
An assertion is a statement or property that describes the expected behavior of a system or design. It is used to validate
whether the system behaves correctly according to its specification. When an assertion is checked during simulation, if the
property being checked does not hold true, the assertion fails. Assertions can also be used to flag unexpected or forbidden
behavior in the design.

Using assertions in verification provides several benefits:

 Improved error detection: Assertions help in catching simulation errors as soon as a design specification is
violated. By specifying properties that the design should satisfy, any deviations or violations can be quickly
identified, leading to faster bug detection.
 Enhanced debug capabilities: Assertions provide better observability into the design. When a test failure occurs,
assertions can pinpoint specific properties that are not being met, making it easier to identify the root cause of the
failure and debug the issue.
 Dynamic and formal verification: Assertions can be checked dynamically during simulation, where they are
evaluated at run-time. They can also be used in formal verification, where formal tools analyze the design and
check whether the specified properties hold for all possible input scenarios. This allows for comprehensive
verification coverage.
 Functional coverage: Assertions can be used to ensure that specific design properties are exercised during
simulation. By defining assertions on input stimulus, coverage metrics can be collected to determine how well the
design has been tested. This helps in ensuring that the design is thoroughly exercised and provides confidence in
its functionality.

2. Types of Assertions
In SystemVerilog, there are two types of assertions: immediate assertions and concurrent assertions. Let's explore the
differences between these two types with examples:

1. Immediate Assertion:

An immediate assertion is evaluated at a specific point in time during simulation. It is typically used to check properties at
a specific event or condition. Immediate assertions are defined using the assert keyword within an initial or always
block.

Example:

Consider a scenario where we want to verify that a counter increments by exactly one whenever an enable signal is
asserted. We can express this property using an immediate assertion as follows:
In this example, the immediate assertion (counter == $past(counter) + 1) is placed inside the always block that increments
the counter. The assertion checks that the counter increments by exactly one for every rising edge of the clock when the
enable signal is asserted.

The immediate assertion is evaluated at the specific point in time when it is encountered during simulation. If the property
being checked is false, an error is reported.

2. Concurrent Assertion:

A concurrent assertion is evaluated continuously throughout the simulation, checking the specified property
concurrently with the simulation activities. It is typically used to check properties over time or across multiple signals or
events. Concurrent assertions are defined using the assert keyword. They usually appear outside any initial or always
blocks in modules.

Example:

Suppose we have a design with two input signals, A and B, and we want to ensure that whenever A is high, B should also
be high after two clock cycles. We can express this property using a concurrent assertion as follows:

In this example, the concurrent assertion A |-> ##2 B specifies that if A is high (A |->), then B should be high after two
clock cycles (##2 B). The assertion is evaluated continuously during simulation, and if it fails, an error is reported.

3. Concurrent Assertions

3.1 Concurrent Assertions Layers

 Assertion
Directives

Property Declaration

Sequential Regular
Expression

Boolean Expression

3.1.1 Concurrent Assertions Example

If I have this Assertion that runs for entire duration of simulation that ensure that both a & b signal is high together at
posedge clk

If we randomize signals A and B in our simulation, there is a possibility that the assertion will fail at certain edges. Let's
analyze the waveform and determine where the assertion would fail.
3.2 Implication
The implication construct (|->) allows a user to monitor sequences based on satisfying a precondition to a sequence and
evaluate the sequence only if the condition is successful.

The left-hand side operand of the implication is called the antecedent sequence expression, while the right-hand side is
called the consequent sequence expression.

If there is no match of the antecedent sequence expression, implication succeeds vacuously by returning true.

If there is a match, for each successful match of the antecedent sequence expression, the consequent sequence, expression
is separately evaluated, beginning at the end point of the match.

Here’s an example for the difference between them.

3.3 Sequence cycle delay operator

Cycle Delay Syntax Explanation

Simple Delay S1 ##n S2 s2 begins on n clock cycles after s1 ends

Delay Range s1 ##[n:m] s2 s2 begins at minimum n clock cycles and at maximum m

clock cycles after s1 ends

Open-ended s1 ##[n:$] s2 s2 begins at minimum n clock cycles and no maximum

clock cycles after s1 ends

One or more s1 ##[+] s2 used as an equivalent representation of s1##[1:$] s2

Zero or more s1 ##[*] s2 used as an equivalent representation of s1##[0:$] s2

Repetition Range S1 [*1:n] Equivalent to (S1) or (S1 ##1 S1) or (S1 ##S1 ##1 S1)

1. The $ operator can be used to extend a time window to a finite, but unbounded range.

2. The [-> or Goto repetition operator specifies a non-consecutive sequence. This means S1 is followed by any
number of clocks where S3 is false, and S2 is true between 1 and three times, the last time being the clock before
S3 is true.

3. The [= or non-consecutive repetition operator is similar to Goto repetition, but the expression (S2 in this
example) need not be true in the clock cycle before S3 is true.

3.4 Combing Sequences

1. The "and" operator is used when both operand sequences are expected to succeed. The end time of the combined
sequence is determined by the sequence that terminates last.

Example: S1 and s2

This operator succeeds if both s1 and s2 succeed. The end time of the combined sequence is the end time of the
sequence that terminates last

2. The "intersect" operator is used when both operand sequences are expected to succeed and their end times must
be the same.
Example: S1 intersect S2
This operator succeeds if both s1 and s2 succeed, and their end times are the same.
3. The "or" operator is used when at least one of the two operand sequences is expected to match. The resulting
sequence matches whenever at least one of the operands is evaluated to true.
Example: S1 or S2
 This operator succeeds whenever at least one of the sequences s1 or s2 is evaluated to true.

4. The "first_match" operator matches only the first match of possibly multiple matches for an evaluation attempt
of a sequence expression. This allows subsequent matches to be discarded.

Example: sequence fms;

first_match(s1 ##[1:2] s2);

endsequence
The result of sequence fms is whichever of (s1 ##1 s2) and (s1 ##2 s2) matches first.

5. The "throughout" construct specifies that an expression must evaluate true at every clock tick during the
evaluation of a sequence.

Example: Sig1 throughout s1

The signal sig1 should be high for the duration of the sequence s1.

6. The "within" construct specifies that one sequence must occur entirely within another sequence.

Example: SequenceExpr1 within SequenceExpr2

This construct requires that SequenceExpr1 occurs at least once entirely within SequenceExpr2, with both the
start and end points of SequenceExpr1 being between the start and end points of SequenceExpr2.

3.5 Assertion System Functions

1. $rose(signal):

The $rose function is used to detect the rising edge of a signal. It evaluates to true if the given signal transitions
from low to high at the current clock tick.

2. $fell(signal):

The $fell function is the opposite of $rose. It detects the falling edge of a signal. It evaluates to true if the given
signal transitions from high to low at the current clock tick.

3. $stable(signal):

The $stable function checks if a signal has remained stable (unchanged) for at least one clock cycle. It evaluates
to true if the given signal has the same value in the current and previous clock ticks.

4. $changed(signal):
 The $changed function is the opposite of $stable. It checks if a signal has changed its value between the current
and previous clock ticks. It evaluates to true if the given signal has a different value in the current and previous
clock ticks.

5. $past(expression):

The $past function is used to access the value of an expression in the previous clock tick. It allows referencing
past values of signals or variables within assertions.

3.5.1 Assertion System Functions Example

If we randomize a, Let's analyze the waveform and determine where the assertion would fail.

The

disable iff construct is typically used in conjunction with an assertion or property to selectively disable its evaluation
based on a condition. The condition is specified within parentheses following the disable iff keywords.

Example:

Let's consider a simple property that verifies that a signal data_valid is true whenever a signal data is valid and not during
a reset phase:

In this example, the

property p states that whenever there is a positive clock edge, if the reset signal is false, then data_valid must be true
whenever data is valid.
3.6 Assertion Directives
Assertion directives in SystemVerilog provide additional control and guidance to the assertion checker, influencing the
checking process and reporting behavior. Here's an explanation of commonly used assertion directives along with
examples:

1. Assert Directive:

The assert directive is used to specify assertions that must always hold true during the verification process. When
an assertion fails, it indicates a violation of the expected behavior.

In this example, the assert directive ensures that whenever signal a becomes true, signal b must
become false. If this assertion fails during simulation or formal verification, it indicates a violation of the
specified property.

2. Assume Directive:

The assume directive is used to provide additional assumptions about the system behavior. These assumptions
help guide the verification process and may influence the coverage analysis.

Example:

In this example, the assume directive specifies that signal x must be true and signal y must be false in every clock
cycle. This assumption guides the verification process by considering these conditions during analysis and
coverage assessment.

3. Cover Directive:

The cover directive is used to define coverage points that track the occurrence of specific events or conditions
during the verification process. It helps measure how well certain properties or behaviors are exercised.

Example:

4.
Restrict Directive
 To specify the property as a constraint on formal verification computations and is ignored by simulators

3.7 Local variables in A sequence

One of the powerful features of SVA. It enables information to be stored within the thread of a sequence and then
tested at later cycles within this sequence. Variables can be used in sequence and property where it’s declared.

4 Lab
Task
Use your
lab 5 files
“arbiter .v”,
“arbiter_io.sv”, “test.v”, and “arbiter_test_top.sv”

1) In the testbench (test.v), consider you want to check the grant signal is correct when a certain request is sent
like shown in the example below.

Replace the if statement above with an immediate assertion and run your code.

2) Add a concurrent assertion in your interface (arbiter_io.sv) that checks that the arbiter request signal does not
have X or Z values except during reset.

5 Assignment
1. Write a SystemVerilog assertion to check if a signal valid is high whenever a signal ready is high
2. Write a SystemVerilog assertion to check if a sequence of events a, b, and c occurs in the given order with a one-
cycle gap between each event. Ensure that the sequence does not trigger if the reset signal is active.
3. Write a SystemVerilog cover directive to measure the coverage of a signal data being greater than zero.
4. Write a SystemVerilog sequence that checks if a signal a is high for at least two clock cycles, followed by a
sequence of events b and c, and assert it.
5. Write a SystemVerilog sequence, s1, that checks for the following pattern in a signal sequence:
 The sequence should start with a rising edge of a signal called data_valid.
 The sequence should then wait for a delay of 7 clock cycles.
 After the delay, the signal data_out should be equal to the value stored in data_in before the delay.
6. Consider the following SystemVerilog sequence: S1 ##2 S2[=1:2] ##1 S3 ##1 S4[->1:3] ##1 S5.

Your task is to analyze the given sequence and identify the conditions that will result in the sequence succeeding
or failing.

Write a comprehensive explanation that includes:

 The conditions under which the sequence will succeed.

 The conditions that will cause the sequence to fail.
 Provide specific examples for both success and failure cases to demonstrate your understanding.