VERILOG MINI PROJECT

DIGITAL ALARM CLOCK

Shaik Shabana

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 Table of Contents

1. Abstract 3

2. Introduction 4

3. Methodology 5

3.1 compilation 6

3.2 block diagram 6

4. Implementation 7

5. Verilog hdl codes 9

6. Results 17

7. Conclusion 18
 2
1. Abstract

This project presents the design and implementation of a digital alarm clock using Verilog
hardware description language(HDL). The system integrates key functionalities such as
real-time clock (RTC), alarm setting and display control on a field-programmable gate
array (FPGA) platform. The Verilog code utilizes sequential and combinational logic to
achieve accurate timekeeping and reliable alarm triggering.

Additionally, the project incorporates a user-friendly interface for setting the alarm time
and provides a clear display of the current time. The implementation demonstrates the
effectiveness of Verilog in creating a robust and versatile digital alarm clock system
suitable for various application.
 3

2. Introduction

Designing an alarm clock in VLSI (Very Large Scale Integration) involves creating a digital circuit at
a lower level of abstraction compared to Verilog. In VLSI design, you would typically use a hardware
description language (HDL) like Verilog or VHDL to describe the functionality of the alarm clock, but
then you would synthesize it into a gate-level netlist, perform place and route, and finally, the design
would be fabricated into silicon.
 Here's a simplified overview of the steps involved in designing an alarm clock in VLSI :

 Specification and Architecture: Define the requirements and architecture of the alarm clock,
including features like setting the time, setting the alarm, turning off the alarm, etc.
 RTL Design: Write the RTL (Register Transfer Level) description of the alarm clock functionality
using a hardware description language like Verilog or VHDL. This involves describing the behavior
of the alarm clock in terms of registers, combinational logic, and clocked processes.
 Simulation: Verify the functionality of the RTL design using simulation tools to ensure that it
meets the specified requirements.
 Synthesis: Use synthesis tools to convert the RTL description into a gate-level netlist consisting of
logic gates and flip-flops. This netlist represents the logical implementation of the alarm clock.
 Place and Route: Place the synthesized gates onto the physical layout of the chip and route
interconnections between them while considering factors like timing, area, and power.
 Physical Design Verification: Perform various checks (such as DRC, LVS, and ERC) to ensure
that the physical layout adheres to design rules and is free from errors.
 Timing Analysis and Optimization: Analyze the timing of the design to ensure that all timing
constraints are met, and perform optimizations if necessary to improve timing performance.
 Fabrication: Once the design is verified and meets all requirements, it sent for fabrication, where
the chip is manufactured usingsemiconductor fabrication processes.
 Testing: After fabrication, the chips are tested to ensure that they function correctly according to
the design specifications. This may involve functional testing, parametric testing, and other tests
to ensure reliability and quality.
 Integration: The fabricated chips can then be integrated into larger systems or devices, such as
alarm clocks, where they provide the desired functionality.
Each of these steps involves various tools, methodologies, and expertise in VLSI design and semiconductor
manufacturing. The process is complex and requires careful attention to detail at each stage to ensure a
successful outcome.

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 3. Methodology

1. Block Diagram: Create a block diagram outlining the system's main components:Real-Time Clock
(RTC) block - Generates timing signals (seconds, minutes, hours).

Time Setting block - Allows users to set the current time and alarm time.

Alarm block - Compares the current time with the alarm time and triggers an alarm if they match.

LCD Controller block - Drives the LCD to display the time and alarm status.

User Interface block - Provides buttons or switches for user interaction (setting time and alarm).

2. Component Design: Develop VHDL code for each block:

RTC block - Uses a counter that increments based on a clock signal to keep track of time.

Time Setting block - Captures user input (e.g., button presses) to set the current time and alarm time.

Alarm block - Continuously compares the current time from the RTC block with the alarm time.

When they match, it generates an alarm signal.

LCD Controller block - Takes time data from the RTC block and alarm signal from the Alarm block

and converts them into a format suitable for the LCD. It then sends control signals to the LCD to

update the display.

User Interface block - Detects user input (e.g., button presses) and sends signals to other blocks like

the Time Setting block.

3. Integration: Integrate all the blocks by connecting their input and output signals.

4. Simulation and Testing: Simulate the VHDL code to verify its functionality. Test the design with
various scenarios (different times, setting alarms, triggering alarms).

5. Synthesis and Implementation: Synthesize the VHDL code into a hardware description suitable
for your target FPGA platform. Implement the design on the FPGA board.

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 3.1 Compilation

Compiling the VHDL code for your digital alarm clock involves first defining the top entity with its
input and output ports for clock signal, reset, user interface buttons, and LCD control signals. Then, the
architecture describes functionalities in separate processes. One process updates the timekeeping based
on the clock signal, while others handle user input for setting time and alarm, compare time for alarms,
and control the LCD display. Finally, depending on your chosen FPGA platform, you'll use vendor-
specific tools to translate the VHDL code into hardware for implementation on the FPGA. Remember,
this is a general outline, and specific details will depend on your chosen LCD interface, user controls,
and desired features.

3.2 Block Diagram

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 4. Implementation

Implementation for the digital alarm clock with LCD in VHDL

1. User Interface:
Design a user interface with buttons or switches for setting the current time, alarm time, and
potentially other functions. In your VHDL code, define input ports for these buttons and interpret
their presses in dedicated processes.

2. LCD Interface:
Choose a suitable LCD for your project and determine its communication protocol (e.g., SPI, I2C).
Find existing VHDL libraries or code examples for your chosen LCD interface. These will
provide components for sending data and control signals to the LCD.
In your architecture, instantiate the LCD controller component and connect its signals according to
the library documentation.

3. Real-Time Clock (RTC):

There are two approaches:Implement a counter that increments based on the clock signal to keep
track of time. This requires handling overflows for seconds, minutes, and hours.
Utilize an external RTC module (integrated circuit) for more accurate timekeeping. You'll need to
find a VHDL component for your chosen RTC module and integrate it into your design.

4. Timekeeping and Alarm Logic:

Implement a process that increments the timekeeping signals (seconds, minutes, hours) based on
the clock signal. Handle overflows for each unit (seconds to minutes, minutes to hours).
Create a separate process for handling alarms. Continuously compare the current time with the
stored alarm time (set by the user). When they match, generate an alarm signal which can be
used to drive an alarm sound or visual indicator (LCD message).

5. Synthesis and Implementation:

Use your chosen FPGA vendor's software tools to synthesize the VHDL code. This translates the
code into a hardware description suitable for your target FPGA.
Implement the design on the FPGA board by following the vendor's instructions. This typically
involves downloading the synthesized design file to the FPGA.

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Alarm Controller – FSM

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 5. Verilog HDL Codes

module aclock (
input reset, /* Active high reset pulse, to set the time to the input hour and minute
(as defined by the H_in1, H_in0, M_in1, and M_in0 inputs) and the second to 00. It
should also set the alarm value to 0.00.00, and to set the Alarm (output) low.For
normal operation, this input pin should be 0*/
input clk, /* A 10Hz input clock. This should be used to generate each real-time
second*/
input [1:0] H_in1, /*A 2-bit input used to set the most significant hour digit of the clock
(if LD_time=1),or the most significant hour digit of the alarm (if LD_alarm=1). Valid
values are 0 to 2. */
input [3:0] H_in0, /* A 4-bit input used to set the least significant hour digit of the
clock (if LD_time=1),or the least significant hour digit of the alarm (if LD_alarm=1).
Valid values are 0 to 9.*/
input [3:0] M_in1, /*A 4-bit input used to set the most significant minute digit of the
clock (if LD_time=1),or the most significant minute digit of the alarm (if LD_alarm=1).
Valid values are 0 to 5.*/
input [3:0] M_in0, /*A 4-bit input used to set the least significant minute digit of the
clock (if LD_time=1),or the least significant minute digit of the alarm (if LD_alarm=1).
Valid values are 0 to 9. */
input LD_time, /* If LD_time=1, the time should be set to the values on the inputs
H_in1, H_in0, M_in1, and M_in0. The second time should be set to 0.If LD_time=0,
the clock should act normally (i.e. second should be incremented every 10 clock
cycles).*/
input LD_alarm, /* If LD_alarm=1, the alarm time should be set to the values on the
inputs H_in1, H_in0, M_in1, and M_in0.If LD_alarm=0, the clock should act
normally.*/
input STOP_al, /* If the Alarm (output) is high, then STOP_al=1 will bring the
output back low. */
input AL_ON, /* If high, the alarm is ON (and Alarm will go high if the alarm time
equals the real time). If low the the alarm function is OFF. */
output reg Alarm, /* This will go high if the alarm time equals the current time, and
AL_ON is high. This will remain high, until STOP_al goes high, which will bring Alarm
back low.*/
output [1:0] H_out1,
/* The most significant digit of the hour. Valid values are 0 to 2. */
output [3:0] H_out0,
/* The least significant digit of the hour. Valid values are 0 to 9. */
output [3:0] M_out1,
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/* The most significant digit of the minute. Valid values are 0 to 5.*/
output [3:0] M_out0, /* The least significant digit of the minute. Valid values are 0 to
9. */
output [3:0] S_out1, /* The most significant digit of the minute. Valid values are 0 to
5. */
output [3:0] S_out0 /* The least significant digit of the minute. Valid values are 0 to
9. */
);
// fpga4student.com FPGA projects, VHDL projects, Verilog project
// internal signal
reg clk_1s; // 1-s clock
reg [3:0] tmp_1s; // count for creating 1-s clock
reg [5:0] tmp_hour, tmp_minute, tmp_second;
// counter for clock hour, minute and second
reg [1:0] c_hour1,a_hour1;
/* The most significant hour digit of the temp clock and alarm. */
reg [3:0] c_hour0,a_hour0;
/* The least significant hour digit of the temp clock and alarm. */
reg [3:0] c_min1,a_min1;
/* The most significant minute digit of the temp clock and alarm.*/
reg [3:0] c_min0,a_min0;
/* The least significant minute digit of the temp clock and alarm.*/
reg [3:0] c_sec1,a_sec1;
/* The most significant second digit of the temp clock and alarm.*/
reg [3:0] c_sec0,a_sec0;
/* The least significant minute digit of the temp clock and alarm.*/

/************************************************/
/*****************function mod10******************/
/*************************************************/
function [3:0] mod_10;
input [5:0] number;
begin
mod_10 = (number >=50) ? 5 : ((number >= 40)? 4 :((number >= 30)? 3 :((number
>= 20)? 2 :((number >= 10)? 1 :0))));
end
endfunction

/*************************************************/
/************* Clock operation**************/
/*************************************************/
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// fpga4student.com FPGA projects, VHDL projects, Verilog project
always @(posedge clk_1s or posedge reset )
begin
if(reset) begin // reset high => alarm time to 00.00.00, alarm to low, clock to H_in and
M_in and S to 00
a_hour1 <= 2'b00;
a_hour0 <= 4'b0000;
a_min1 <= 4'b0000;
a_min0 <= 4'b0000;
a_sec1 <= 4'b0000;
a_sec0 <= 4'b0000;
tmp_hour <= H_in1*10 + H_in0;
tmp_minute <= M_in1*10 + M_in0;
tmp_second <= 0;
end
else begin
if(LD_alarm) begin // LD_alarm =1 => set alarm clock to H_in, M_in
a_hour1 <= H_in1;
a_hour0 <= H_in0;
a_min1 <= M_in1;
a_min0 <= M_in0;
a_sec1 <= 4'b0000;
a_sec0 <= 4'b0000;
end
if(LD_time) begin // LD_time =1 => set time to H_in, M_in
tmp_hour <= H_in1*10 + H_in0;
tmp_minute <= M_in1*10 + M_in0;
tmp_second <= 0;
end
else begin // LD_time =0 , clock operates normally
tmp_second <= tmp_second + 1;
if(tmp_second >=59) begin // second > 59 then minute increases
tmp_minute <= tmp_minute + 1;
tmp_second <= 0;
if(tmp_minute >=59) begin // minute > 59 then hour increases
tmp_minute <= 0;
tmp_hour <= tmp_hour + 1;
if(tmp_hour >= 24) begin // hour > 24 then set hour to 0
tmp_hour <= 0;
end
end
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end

end
end
end
 /*************************************************/
/******** Create 1-second clock****************/
/*************************************************/
// fpga4student.com FPGA projects, VHDL projects, Verilog project
always @(posedge clk or posedge reset)
begin
if(reset)
begin
tmp_1s <= 0;
clk_1s <= 0;
end
else begin
tmp_1s <= tmp_1s + 1;
if(tmp_1s <= 5)
clk_1s <= 0;
else if (tmp_1s >= 10) begin
clk_1s <= 1;
tmp_1s <= 1;
end
else
clk_1s <= 1;
end
end

/*************************************************/
/***OUTPUT OF THE CLOCK**********************/
/*************************************************/
always @(*) begin

if(tmp_hour>=20) begin
c_hour1 = 2;
end
else begin
if(tmp_hour >=10)

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c_hour1 = 1;
else
c_hour1 = 0;
end
c_hour0 = tmp_hour - c_hour1*10;
c_min1 = mod_10(tmp_minute);
c_min0 = tmp_minute - c_min1*10;
c_sec1 = mod_10(tmp_second);
c_sec0 = tmp_second - c_sec1*10;
end
// fpga4student.com FPGA projects, VHDL projects, Verilog project
assign H_out1 = c_hour1; // the most significant hour digit of the clock
assign H_out0 = c_hour0; // the least significant hour digit of the clock
assign M_out1 = c_min1; // the most significant minute digit of the clock
assign M_out0 = c_min0; // the least significant minute digit of the clock
assign S_out1 = c_sec1; // the most significant second digit of the clock
assign S_out0 = c_sec0; // the least significant second digit of the clock

/*************************************************/
/******** Alarm function******************/
/*************************************************/
// fpga4student.com FPGA projects, VHDL projects, Verilog project
always @(posedge clk_1s or posedge reset) begin
if(reset)
Alarm <=0;
else begin
if({a_hour1,a_hour0,a_min1,a_min0,a_sec1,a_sec0}=={c_hour1,c_hour0,c_min1,c_
min0,c_sec1,c_sec0})
begin // if alarm time equals clock time, it will pulse high the Alarm signal with
AL_ON=1
if(AL_ON) Alarm <= 1;
end
if(STOP_al) Alarm <=0; // when STOP_al = 1, push low the Alarm signal
end
end

endmodule
Testbench Verilog code for alarm clock:
module test;
// fpga4student.com FPGA projects, VHDL projects, Verilog project
// Inputs
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reg reset;
reg clk;
reg [1:0] H_in1;
reg [3:0] H_in0;
reg [3:0] M_in1;
reg [3:0] M_in0;
reg LD_time;
reg LD_alarm;
reg STOP_al;
reg AL_ON;

// Outputs
 wire Alarm;
wire [1:0] H_out1;
wire [3:0] H_out0;
wire [3:0] M_out1;
wire [3:0] M_out0;
wire [3:0] S_out1;
wire [3:0] S_out0;
// fpga4student.com FPGA projects, VHDL projects, Verilog project
// Instantiate the Unit Under Test (UUT)
aclock uut (
.reset(reset),
.clk(clk),
.H_in1(H_in1),
.H_in0(H_in0),
.M_in1(M_in1),
.M_in0(M_in0),
.LD_time(LD_time),
.LD_alarm(LD_alarm),
.STOP_al(STOP_al),
.AL_ON(AL_ON),
.Alarm(Alarm),
.H_out1(H_out1),
.H_out0(H_out0),
.M_out1(M_out1),
.M_out0(M_out0),
.S_out1(S_out1),
.S_out0(S_out0)
);
// clock 10Hz
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initial begin
clk = 0;
forever #50 clk = ~clk;
end
initial begin
// Initialize Inputs
reset = 1;
H_in1 = 1;
H_in0 = 0;
M_in1 = 1;
M_in0 = 4;
LD_time = 0;
LD_alarm = 0;
STOP_al = 0;
AL_ON = 0; // set clock time to 11h26, alarm time to 00h00 when reset
// Wait 100 ns for global reset to finish
#1000;
reset = 0;
H_in1 = 1;
H_in0 = 0;
M_in1 = 2;
M_in0 = 0;
LD_time = 0;
LD_alarm = 1;
STOP_al = 0;
AL_ON = 1; // turn on Alarm and set the alarm time to 11h30
#1000;
reset = 0;
H_in1 = 1;
H_in0 = 0;
M_in1 = 2;
M_in0 = 0;
LD_time = 0;
LD_alarm = 0;
STOP_al = 0;
AL_ON = 1;
wait(Alarm); // wait until Alarm signal is high when the alarm time equals clock time
#1000
STOP_al = 1; // pulse high the STOP_al to push low the Alarm signal
#1000
STOP_al = 0;
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H_in1 = 0;
H_in0 = 4;
M_in1 = 4;
M_in0 = 5;
LD_time = 1; // set clock time to 11h25
LD_alarm = 0;
#1000
STOP_al = 0;
H_in1 = 0;
H_in0 = 4;
M_in1 = 5;
M_in0 = 5;
LD_alarm = 1; // set alarm time to 11h35
LD_time = 0;
wait(Alarm); // wait until Alarm signal is high when the alarm time equals clock time
#1000
STOP_al = 1;// pulse high the STOP_al to push low the Alarm signal
// fpga4student.com FPGA projects, VHDL projects, Verilog project
end

endmodule

Flowchart

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6. Results
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7. Conclusion
In conclusion, designing an alarm clock in VLSI involves a series of steps from specification to
fabrication, leveraging hardware description languages, synthesis tools, physical design tools, and
semiconductor manufacturing processes. The process requires careful consideration of requirements,
architectural decisions, RTL design, simulation, synthesis, place and route, physical design
verification, timing analysis, fabrication, testing, and integration.

Despite its complexity, the design of an alarm clock in VLSI offers the opportunity to apply
principles of digital design, logic optimization, timing analysis, and physical layout to create a
compact and efficient digital circuit that meets the specified requirements. The successful completion
of this process results in a chip capable of performing the desired alarm clock functionality, which
can then be integrated into larger systems or devices, contributing to the advancement of technology
in various applications.

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