ELECTRONICS & COMMUNICATION ENGINEERING

CATEGORY L T P CREDIT
ECT304 VLSI CIRCUIT DESIGN
PCC 3 1 0 4

Preamble: This course aims to impart the knowledge of VLSI design methodologies and Digital
VLSI circuit design.

Prerequisite:
1. ECT201 Solid State Devices
2. ECT202 Analog Circuits
3. ECT 203 Logic Circuit Design.

COURSE OUTCOMES.
After the completion of the course the student will be able to:
CO1 Explain the various methodologies in ASIC and FPGA design.
CO2 Design VLSI Logic circuits with various MOSFET logic families.
CO3 Compare different types of memory elements.
CO4 Design and analyse data path elements such as Adders and multipliers.
CO5 Explain MOSFET fabrication techniques and layout design rules.

Mapping of course outcomes with program outcomes:

PO1 PO1 PO1
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9
0 1 2
CO1 3 3 2
CO2 3 2 3 2
CO3 3 2 3 2
CO4 3 2 3 2
CO5 3 2 2

Assessment Pattern:
End Semester
Continuous Assessment Tests
Bloom’s Category Examination
1 2
Remember
10 10 20
Understand
20 20 40
Apply
20 20 40
Analyze

Evaluate

Create

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Mark distribution:

Total Marks CIE ESE Duration

150 50 100 3Hrs

Continuous Internal Evaluation Pattern:

Attendance : 10 marks
Continuous Assessment Test (2 numbers) : 25 marks
Assignments : 15 marks.

End Semester Examination Pattern

Maximum Marks : 100 Time : 3 hours

End Semester Examination Pattern: There will be two parts; Part A and Part B. Part A contain
10 questions with 2 questions from each module, having 3 marks for each question. Students
should answer all questions. Part B contains 2 questions from each module of which student
should answer any one. Each question can have maximum 2 sub-divisions and carry 14 marks.
Mark patterns are as per the syllabus with 75% for theory and 25% for logical/numerical
problems.

Course Level Assessment Questions.

CO1:
1. Differentiate between full custom and semi-custom ASIC.
2. With a neat flow chart, explain ASIC design flow.
3. Describe Gate array based ASIC with neat diagram.
4. What are the processes involved in Soc design.

CO2:
1. With a neat diagram explain static and transient analysis of CMOS inverter
2. Realize the given logic function using static CMOS logic and transmission gate logic.
3. Compare the advantages and disadvantages of static and dynamic circuits.

CO3:
1. Compare different ROM structures.
2. Compare static and dynamic RAM structures.
3.Compare the advantages of three transistor and one transistor DRAM cell.

CO4:
1. Design a full adder with static CMOS logic
2. Compare the delay of Carry-Bypass adder, Linear Carry- Select adder, Square- root carry-
select adder.

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CO5:
1. Explain how electronic grade silicon (EGS) is developed .
2. Explain the necessity of single crystalline silicon in VLSI fabrication and how single crystal
silicon is made.
3. Explain diffusion and ion implantation techniques.
4. Explain the advantages of SiO2 and the oxidation techniques.

Syllabus

Module 1: VLSI Design Methodologies.

Introduction: Moore’s law .ASIC design, Full custom ASICs, Standard cell based ASICs, Gate
array based ASICs, SoCs, FPGA devices, ASIC and FPGA Design flows, Top-Down and
Bottom-Up design methodologies. Logical and Physical design. Speed power and area
considerations in VLSI design

Module 2: Static CMOS Logic Design

MOSFET Logic Design - NMOS Inverter (Static analysis only), basic logic gates,
CMOS logic, Static and transient analysis of CMOS inverter, Switching power dissipation and
delays. Realization of logic functions with static CMOS logic, Pass transistor logic, and
transmission gate logic

Module 3: Dynamic logic Design and Storage Cells

Dynamic Logic Design-Pre charge- Evaluate logic, Domino Logic, NP domino logic.
Read Only Memory-4x4 MOS ROM Cell Arrays(OR,NOR,NAND)
Random Access Memory –SRAM-Six transistor CMOS SRAM cell, DRAM –Three transistor
and One transistor Dynamic Memory Cell.

Module 4: Arithmetic circuits

Adders: Static adder, Carry-Bypass adder, Linear Carry- Select adder, Square- root carry- select
adder. Multipliers: Array multiplier.

Module 5: Fabrication techniques and MOSFET physical Design

Material Preparation
Purification and Crystal growth (CZ process), wafer preparation
Thermal Oxidation- Growth mechanisms, Dry and Wet oxidation.
Diffusion and ion implantation techniques.
Epitaxy : molecular beam epitaxy.
Lithography- Photo lithographic sequence, Electron Beam Lithography, Etching and metal
deposition techniques.
MOSFET Fabrication techniques
Twin-Tub fabrication sequence, Fabrication process flow.
Layout Design and Design rules, Stick Diagram and Design rules-micron rules and Lambda
rules. (definitions only).layout of CMOS Inverter, two input NAND and NOR gates.

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Text Books:
1. Sung –Mo Kang & Yusuf Leblebici, CMOS Digital Integrated Circuits- Analysis & Design,
McGraw-Hill, Third Ed., 2003
2. S.M. SZE, VLSI Technology, 2/e, Indian Edition, McGraw-Hill,2003
3. Wayne Wolf ,Modern VLSI design, Third Edition, Pearson Education,2002.

References:
1. Michael John Sebastian Smith, Application Specific Integrated Circuits, Pearson
Education,2001.
2. Neil H.E. Weste, Kamran Eshraghian, Principles of CMOS VLSI Design- A Systems
Perspective, Second Edition. Pearson Publication, 2005.
3. Jan M. Rabaey, Digital Integrated Circuits- A Design Perspective, Prentice Hall, Second
Edition, 2005.
4. Razavi - Design of Analog CMOS Integrated Circuits,1e, McGraw Hill Education India
Education, New Delhi, 2003.
5.
Course Contents and Lecture Schedule.

No. of.
No Topic
Lectures
Module 1: VLSI Design Methodologies. (11 Hrs)

Introduction: Moore slaw .ASIC design, Full custom ASICs,

1.1 3
Standard cell based ASICs, Gate array based ASICs,
SoCs, FPGA devices
1.2 2
ASIC and FPGA Design flows Top-Down and Bottom-Up design
1.3 3
methodologies.
Logical and Physical design. Speed power and area considerations
1.4 3
in VLSI design
Module 2:Static CMOS Logic Design (9 Hrs)

MOSFET Logic Design - NMOS logic (Static analysis of Basic

2.1 gates only) 3

CMOS logic, Static and transient analysis of CMOS inverter

2.2 3
Switching power dissipation and delays
Realization logic functions in static CMOS logic, Pass transistor
2.3 logic, and transmission gate logic (Static analysis only) 3

Module 3: Dynamic logic Design and Storage Cells (8 Hrs)

Dynamic Logic Design-Pre charge- Evaluate logic, Domino Logic,

3.1 NP domino logic. 3

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Read Only Memory-4x4 MOS ROM Cell

3.2 Arrays(OR,NOR,NAND) 2

Random Access Memory –SRAM-Six transistor CMOS SRAM

3.3 cell, DRAM –Three transistor and One transistor Dynamic Memory 3
Cell.

Module 4: Arithmetic circuits (5 Hrs)

4.1 Adders- Static adder, Carry-Bypass adder, Linear Carry- Select 3

adder, Square- root carry- select adder.

4.2 Multipliers-Array multiplier. 2

Module 5: MOSFET physical Design and Fabrication techniques (13 Hrs)

5.1 Material Preparation (qualitative analysis only) 2

Purification and Crystal growth (CZ process), wafer preparation.
Thermal Oxidation- Growth mechanisms, Dry and Wet oxidation.
5.2 3
Diffusion and ion implantation techniques.
Epitaxy : Molecular beam epitaxy.
5.3 Lithography- Photo lithographic sequence, Electron Beam 3
Lithography, Etching and metal deposition techniques
MOSFET Fabrication techniques(qualitative analysis only)
5.4 2
Twin-Tub fabrication sequence, Fabrication process flow.
Layout Design and Design rules, Stick Diagram and Design rules-
5.5 micron rules and Lambda rules. Layout of CMOS Inverter, two 3
input NAND and NOR gates,

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Model Question Paper

A P J Abdul Kalam Technological University

Sixth Semester B Tech Degree Examination
Branch: Electronics and Communication Course:
Time: 3 Hrs Max. ECT 304 VLSI CIRCUIT DESIGN
Marks: 100
PART A
(Answer All Questions)

1 What is Moore's law in VLSI design? (3)

2 Differentiate between ASIC and FPGA. (3)
3 Switching threshold voltage equation of CMOS inverter and explain each (3)
parameter
4 List the advantage of CMOS logic. (3)
5 List the advantages of dynamic logic over static logic circuits. (3)
6 Differentiate between volatile and non volatile memories. (3)
7 Explain propagate delete and generate signals. (3)
8 What are the different types of power dissipation in a CMOS inverter? (3)
9 List the advantages of SiO2 (3)
10 Define lambda rules and micron rules. (3)

PART B
(Answer one question from each module. Each question carries 14 mark.)

11(A) What is FPGA? What are its applications? With block diagram explain its (6)
internal architecture?
11(B) Explain ASIC design flow. (8)
OR
12(A) Compare different ASIC design methodologies. (8)
12(A) List the advantages of SOC (6)

13(A) Derive expression for the switching threshold of a CMOS inverter. (7)
13(B) What is meant by pass transistor logic? What are the differences in (7)
transmission characteristics of N MOS and P MOS transistors?
OR
14(A) What are the different types of power dissipation in a CMOS inverter? (8)
Derive expression for the total power dissipation.
14(B) Why PMOS transistor can pass only strong ones and NMOS can pass (6)
strong zeros.

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15(A) Draw the circuit diagram and explain the principle of operation of a (7)
CMOS based static RAM cell. Explain the read and write operations.
What are the constraints on the sizes of transistors?
15(B) Draw the circuit diagram and explain the principle of operation of a one (7)
transistor dynamic RAM cell. Explain the read, write and refresh
operations
OR
16(A) Explain the read and write operation of a three-transistor DRAM cell (7)
16(B) Explain the read and write operation of a six transistor CMOS SRAM cell. (7)
OR
17(A) With diagram illustrate the principle of operation of an array multiplier. (8)
Show the critical path. Estimate the delay of the multiplier.
17(B) With block diagram illustrate the principle of operation of a square root (6)
carry select adder. Estimate the delay of an n bit adder
OR
18(A) Draw circuit diagram of a full adder with not more than 28 transistors in (8)
standard CMOS logic
18(B) Explain the working a 16-bit carry-by pass adder and write down the (6)
expression for worst-case delay.

19(A) Illustrate with diagram the principle of crystal growth by Czochralzki (7)
method.
19(B) What is photolithography? With diagram illustrate the steps involved in (7)
photolithography process.
OR
20(A) Explain the principle of molecular beam epitaxy, with schematic diagram (8)
of an MBE system. What are its advantages and disadvantages?
20(B) With schematic diagram and chemical reactions involved, illustrate wet (6)
and dry oxidation processes

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MODEL ASSIGNMENT QUESTIONS

Module 1
1. How to choose between FPGA and ASIC ?
2. Describe ASIC in terms of Size, power and performance, IP protection and competitive
Edge
3. Compare Gate-array design and Full-custom design?
4. What are the differences between CPLDs and CLBs
5 List some of the commonly used FPGA development board ?
6. Discuss the architecture of any one of the leading FPGA in industry ?

Module 2
1. Power and interconnect delay analysis of CMOS inverter?
2. Implement XOR function using pass transistor logic?
3. Derive V IL, V IH,V OH , and V OL of depletion load inverter?
4. Design 8:1 MUX using transmission gate logic?
5. What are the advantages of NMOS over CMOS ?

Module 3
1. Explain the working of sense amplifiers in memory structures?
2. Design a voltage comparator in precharge-evaluate logic .
3. Discuss the cascading problem of P-E logic
4. Discuss the architecture of FLASH EPROM
5. Explain the working of FGMOS

Module 4
1. With diagram illustrate the principle of operation of an array multiplier. Show the critical
path. Estimate the delay of the multiplier
2. Implement a 3x3 array multiplier?

Module 5
1. What is photolithography? With diagram illustrate the steps involved in photolithography
process?
2. What is Deal Grove model of oxidation? What are linear and parabolic rate coefficients
with reference to oxidation process?
3. Illustrate with diagram the principle of crystal growth by Czochralzki method
4. Explain DEAL-GROVE model of oxidation?
5. What are the requirements of a "clean-room" in VLSI fabrication

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