500 Counters

9–2 Asynchronous Counters

The term asynchronous refers to events that do not have a fixed time relationship with
each other and, generally, do not occur at the same time. An asynchronous counter is one
in which the flip-flops (FF) within the counter do not change states at exactly the same time
because they do not have a common clock pulse.
After completing this section, you should be able to
u Describe the operation of a 2-bit asynchronous binary counter
u Describe the operation of a 3-bit asynchronous binary counter
u Define ripple in relation to counters
u Describe the operation of an asynchronous decade counter
u Develop counter timing diagrams
u Discuss the implementation of a 4-bit asynchronous binary counter

A 2-Bit Asynchronous Binary Counter

The clock input of an asynchronous Figure 9–4 shows a 2-bit counter connected for asynchronous operation. Notice that the clock
counter is always connected only to (CLK) is applied to the clock input (C) of only the first flip-flop, FF0, which is always the
the LSB flip-flop. least significant bit (LSB). The second flip-flop, FF1, is triggered by the Q 0 output of FF0.
FF0 changes state at the positive-going edge of each clock pulse, but FF1 changes only when
triggered by a positive-going transition of the Q 0 output of FF0. Because of the inherent
propagation delay time through a flip-flop, a transition of the input clock pulse (CLK) and a
transition of the Q 0 output of FF0 can never occur at exactly the same time. Therefore, the
two flip-flops are never simultaneously triggered, so the counter operation is asynchronous.

FF0 FF1

D0 Q0 D1 Q1
CLK
C C
Q0
Q1

FIGURE 9–4 A 2-bit asynchronous binary counter. Open file F09-04 to verify operation. A
Multisim tutorial is available on the website.

The Timing Diagram

Let’s examine the basic operation of the asynchronous counter of Figure 9–4 by applying four
clock pulses to FF0 and observing the Q output of each flip-flop. Figure 9–5 illustrates the
changes in the state of the flip-flop outputs in response to the clock pulses. Both flip-flops are
connected for toggle operation (D = Q) and are assumed to be initially RESET (Q LOW).
Asynchronous counters are also The positive-going edge of CLK1 (clock pulse 1) causes the Q0 output of FF0 to go
known as ripple counters. HIGH, as shown in Figure 9–5. At the same time the Q 0 output goes LOW, but it has no
effect on FF1 because a positive-going transition must occur to trigger the flip-flop. After
the leading edge of CLK1, Q 0 = 1 and Q 1 = 0. The positive-going edge of CLK2 causes
Q0 to go LOW. Output Q 0 goes HIGH and triggers FF1, causing Q1 to go HIGH. After the
leading edge of CLK2, Q 0 = 0 and Q 1 = 1. The positive-going edge of CLK3 causes Q0
to go HIGH again. Output Q 0 goes LOW and has no effect on FF1. Thus, after the leading
edge of CLK3, Q 0 = 1 and Q 1 = 1. The positive-going edge of CLK4 causes Q0 to go
LOW, while Q 0 goes HIGH and triggers FF1, causing Q1 to go LOW. After the leading
 Asynchronous Counters 501

CLK 1 2 3 4

Q0

Outputs Q0 (LSB)

Q1 (MSB)

FIGURE 9–5 Timing diagram for the counter of Figure 9–4. As in previous chapters,
output waveforms are shown in green.

edge of CLK4, Q 0 = 0 and Q 1 = 0. The counter has now recycled to its original state
(both flip-flops are RESET).
In the timing diagram, the waveforms of the Q0 and Q1 outputs are shown relative to the
clock pulses as illustrated in Figure 9–5. For simplicity, the transitions of Q0, Q1, and the
clock pulses are shown as simultaneous even though this is an asynchronous counter. There
is, of course, some small delay between the CLK and the Q0 transition and between the Q 0
transition and the Q1 transition.
Note in Figure 9–5 that the 2-bit counter exhibits four different states, as you would In digital logic, Q0 is always the LSB
expect with two flip-flops (22 = 4). Also, notice that if Q0 represents the least significant unless otherwise specified.
bit (LSB) and Q1 represents the most significant bit (MSB), the sequence of counter states
represents a sequence of binary numbers as listed in Table 9–1.

TABLE 9–1
Binary state sequence for the counter in Figure 9–4.
Clock Pulse Q1 Q0
Initially 0 0
1 0 1
2 1 0
3 1 1
4 (recycles) 0 0

Since it goes through a binary sequence, the counter in Figure 9–4 is a binary counter. It
actually counts the number of clock pulses up to three, and on the fourth pulse it recycles
to its original state (Q 0 = 0, Q 1 = 0). The term recycle is commonly applied to counter
operation; it refers to the transition of the counter from its final state back to its original state.

A 3-Bit Asynchronous Binary Counter

The state sequence for a 3-bit binary counter is listed in Table 9–2, and a 3-bit asynchronous
binary counter is shown in Figure 9–6(a). The basic operation is the same as that of the 2-bit

TABLE 9–2
State sequence for a 3-bit binary counter.
Clock Pulse Q2 Q1 Q0
Initially 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 (recycles) 0 0 0
502 Counters

FF0 FF1 FF2

D0 Q0 D1 Q1 D2 Q2

CLK C C C
Q0 Q1 Q2

(a)

CLK 1 2 3 4 5 6 7 8

Q0 (LSB) 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 (MSB) 0 0 0 0 1 1 1 1 0

(b) Recycles back to 0

FIGURE 9–6 Three-bit asynchronous binary counter and its timing diagram for one cycle.
Open file F09-06 to verify operation.

counter except that the 3-bit counter has eight states, due to its three flip-flops. A timing
diagram is shown in Figure 9–6(b) for eight clock pulses. Notice that the counter progresses
through a binary count of zero through seven and then recycles to the zero state. This counter
can be easily expanded for higher count, by connecting additional toggle flip-flops.

Propagation Delay
Asynchronous counters are commonly referred to as ripple counters for the following
reason: The effect of the input clock pulse is first “felt” by FF0. This effect cannot get to
FF1 immediately because of the propagation delay through FF0. Then there is the propa-
gation delay through FF1 before FF2 can be triggered. Thus, the effect of an input clock
pulse “ripples” through the counter, taking some time, due to propagation delays, to reach
the last flip-flop.
To illustrate, notice that all three flip-flops in the counter of Figure 9–6 change state on
the leading edge of CLK4. This ripple clocking effect is shown in Figure 9–7 for the first
four clock pulses, with the propagation delays indicated. The LOW-to-HIGH transition of

CLK 1 2 3 4

Q0

Q1

Q2

tPHL (CLK to Q0 ) tPHL (CLK to Q0)

tPLH tPLH (Q0 to Q1) tPHL (Q0 to Q1)
tPLH (Q1 to Q2)
(CLK to Q0 )

FIGURE 9–7 Propagation delays in a 3-bit asynchronous (ripple-clocked) binary counter.

 Asynchronous Counters 503

Q0 occurs one delay time (tPLH) after the positive-going transition of the clock pulse. The
LOW-to-HIGH transition of Q1 occurs one delay time (tPLH) after the positive-going tran-
sition of Q 0. The LOW-to-HIGH transition of Q2 occurs one delay time (tPLH) after the
positive-going transition of Q 1. As you can see, FF2 is not triggered until two delay times
after the positive-going edge of the clock pulse, CLK4. Thus, it takes three propagation
delay times for the effect of the clock pulse, CLK4, to ripple through the counter and change
Q2 from LOW to HIGH.
This cumulative delay of an asynchronous counter is a major disadvantage in many
applications because it limits the rate at which the counter can be clocked and creates
decoding problems. The maximum cumulative delay in a counter must be less than the
period of the clock waveform.

EXAMPLE 9–1

A 4-bit asynchronous binary counter is shown in Figure 9–8(a). Each D flip-flop is

negative edge-triggered and has a propagation delay for 10 nanoseconds (ns). Develop
a timing diagram showing the Q output of each flip-flop, and determine the total propa-
gation delay time from the triggering edge of a clock pulse until a corresponding change
can occur in the state of Q3. Also determine the maximum clock frequency at which the
counter can be operated.

FF0 FF1 FF2 FF3

Q0 Q1 Q2 Q3
D0 D1 D2 D3

CLK C C C C

Q0 Q1 Q2 Q3

(a)

CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Q0

Q1

Q2

Q3

(b)

FIGURE 9–8 Four-bit asynchronous binary counter and its timing diagram. Open file
F09-08 and verify the operation.

Solution
The timing diagram with delays omitted is as shown in Figure 9–8(b). For the total
delay time, the effect of CLK8 or CLK16 must propagate through four flip-flops before
Q3 changes, so
tp(tot) = 4 * 10 ns = 40 ns
504 Counters

The maximum clock frequency is

1 1
fmax = = = 25 MHz
tp(tot) 40 ns
The counter should be operated below this frequency to avoid problems due to the
propagation delay.

Related Problem*
Show the timing diagram if all of the flip-flops in Figure 9–8(a) are positive edge-
triggered.

*Answers are at the end of the chapter.

Asynchronous Decade Counters

n
A counter can have 2 states, where The modulus of a counter is the number of unique states through which the counter will
n is the number of flip-flops. sequence. The maximum possible number of states (maximum modulus) of a counter is 2n,
where n is the number of flip-flops in the counter. Counters can be designed to have a num-
ber of states in their sequence that is less than the maximum of 2n. This type of sequence
is called a truncated sequence.
One common modulus for counters with truncated sequences is ten (called MOD10).
Counters with ten states in their sequence are called decade counters. A decade counter
with a count sequence of zero (0000) through nine (1001) is a BCD decade counter because
its ten-state sequence produces the BCD code. This type of counter is useful in display
applications in which BCD is required for conversion to a decimal readout.
To obtain a truncated sequence, it is necessary to force the counter to recycle before
going through all of its possible states. For example, the BCD decade counter must recycle
back to the 0000 state after the 1001 state. A decade counter requires four flip-flops (three
flip-flops are insufficient because 23 = 8).
Let’s use a 4-bit asynchronous counter such as the one in Example 9–1 and modify its
sequence to illustrate the principle of truncated counters. One way to make the counter
recycle after the count of nine (1001) is to decode count ten (1010) with a NAND gate and
connect the output of the NAND gate to the clear (CLR) inputs of the flip-flops, as shown
in Figure 9–9(a).

Partial Decoding
Notice in Figure 9–9(a) that only Q1 and Q3 are connected to the NAND gate inputs. This
arrangement is an example of partial decoding, in which the two unique states (Q 1 = 1
and Q 3 = 1) are sufficient to decode the count of ten because none of the other states (zero
through nine) have both Q1 and Q3 HIGH at the same time. When the counter goes into
count ten (1010), the decoding gate output goes LOW and asynchronously resets all the
flip-flops.
The resulting timing diagram is shown in Figure 9–9(b). Notice that there is a glitch
on the Q1 waveform. The reason for this glitch is that Q1 must first go HIGH before
the count of ten can be decoded. Not until several nanoseconds after the counter goes
to the count of ten does the output of the decoding gate go LOW (both inputs are
HIGH). Thus, the counter is in the 1010 state for a short time before it is reset to 0000,
thus producing the glitch on Q1 and the resulting glitch on the CLR line that resets the
counter.
Other truncated sequences can be implemented in a similar way, as Example 9–2
shows.
 Asynchronous Counters 505

10 decoder
CLR

FF0 FF1 FF2 FF3

Q0 Q1 Q2 Q3
D0 D1 D2 D3

CLK C C C C
Q0 Q1 Q2 Q3

CLR CLR CLR CLR

(a)

CLK 1 2 3 4 5 6 7 8 9 10

Q0

Glitch
Q1

Q2

Q3

CLR
Glitch
(b)

FIGURE 9–9 An asynchronously clocked decade counter with asynchronous recycling.

EXAMPLE 9–2

Show how an asynchronous counter with J-K flip-flops can be implemented having a modulus of twelve with a straight
binary sequence from 0000 through 1011.

Solution
Since three flip-flops can produce a maximum of eight states, four flip-flops are required to produce any modulus greater
than eight but less than or equal to sixteen.
When the counter gets to its last state, 1011, it must recycle back to 0000 rather than going to its normal next state of
1100, as illustrated in the following sequence chart:
Q3 Q2 Q1 Q0
0 0 0 0
# # # #
# # # # Recycles
# # # #
1 0 1 1
1 1 0 0 Normal next state
Observe that Q0 and Q1 both go to 0 anyway, but Q2 and Q3 must be forced to 0 on the twelfth clock pulse. Figure 9–10(a)
shows the modulus-12 counter. The NAND gate partially decodes count twelve (1100) and resets flip-flop 2 and flip-flop 3.
506 Counters

Thus, on the twelfth clock pulse, the counter is forced to recycle from count eleven to count zero, as shown in the timing
diagram of Figure 9–10(b). (It is in count twelve for only a few nanoseconds before it is reset by the glitch on CLR.)

12 decoder

HIGH
FF0 FF1 FF2 FF3
Q0 Q1 Q2 Q3
J0 J1 J2 J3

CLK C C C C

K0 K1 K2 K3
CLR CLR CLR CLR
CLR

(a)

CLK 1 2 3 4 5 6 7 8 9 10 11 12

Q0

Q1
Glitch
Q2

Q3

Decoder
output
(CLR) Glitch
(b)

FIGURE 9–10 Asynchronously clocked modulus-12 counter with asynchronous recycling.

Related Problem
How can the counter in Figure 9–10(a) be modified to make it a modulus-13 counter?

IMPLEMENTATION: 4-BIT ASYNCHRONOUS BINARY COUNTER

Fixed-Function Device The 74HC93 is an example of a specific integrated circuit asyn-
chronous counter. This device actually consists of a single flip-flop (CLK A) and a 3-bit asyn-
chronous counter (CLK B). This arrangement is for flexibility. It can be used as a divide-by-2
device if only the single flip-flop is used, or it can be used as a modulus-8 counter if only the
3-bit counter portion is used. This device also provides gated reset inputs, RO(1) and RO(2).
When both of these inputs are HIGH, the counter is reset to the 0000 state CLR.
Additionally, the 74HC93 can be used as a 4-bit modulus-16 counter (counts 0 through
15) by connecting the Q0 output to the CLK B input as shown by the logic symbol in
Figure 9–11(a). It can also be configured as a decade counter (counts 0 through 9) with
asynchronous recycling by using the gated reset inputs for partial decoding of count ten, as
shown by the logic symbol in Figure 9–11(b).
 Synchronous Counters 507

CLK A C CTR DIV 16 CLK A C CTR DIV 10

CLK B C CLK B C
RO(1) RO(1)
RO(2) RO(2)

Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3

(a) 74HC93 connected as a modulus-16 counter (b) 74HC93 connected as a decade counter

FIGURE 9–11 Two configurations of the 74HC93 asynchronous counter. (The qualifying
label, CTR DIV n, indicates a counter with n states.)

Programmable Logic Device (PLD) The VHDL code for a generic 4-bit asynchronous
binary counter using J-K flip flops with preset (PRN) and clear (CLRN) inputs is as
follows:
library ieee;
use ieee.std_logic_1164.all;
entity AsyncFourBitBinCntr is
port (Clock, Clr: in std_logic; Q0, Q1, Q2, Q3: inout std_logic); Inputs and outputs declared
end entity AsyncFourBitBinCntr;
architecture LogicOperation of AsyncFourBitBinCntr is
component jkff is
port (J, K, Clk, PRN, CLRN: in std_logic; Q: out std_logic); s J-K flip-flop component
end component jkff; declaration

begin
FF0: jkff port map(J=7‘1’, K=7‘1’, Clk=7Clock, CLRN=7Clr, PRN=7‘1’, Q=7Q0);
FF1: jkff port map(J=7‘1’, K=7‘1’, Clk=7not Q0, CLRN=7Clr, PRN=7‘1’, Q=7Q1); Instantiations define
FF2: jkff port map(J=7‘1’, K=7‘1’, Clk=7not Q1, CLRN=7Clr, PRN=7‘1’, Q=7Q2); t how each flip-flop is
FF3: jkff port map(J=7‘1’, K=7‘1’, Clk=7not Q2, CLRN=7Clr, PRN=7‘1’, Q=7Q3); connected.
end architecture LogicOperation;

SECTION 9–2 CHECKUP

1. What does the term asynchronous mean in relation to counters?

2. How many states does a modulus-14 counter have? What is the minimum number of
flip-flops required?

9–3 Synchronous Counters

The term synchronous refers to events that have a fixed time relationship with each other.
A synchronous counter is one in which all the flip-flops in the counter are clocked at the
same time by a common clock pulse. J-K flip-flops are used to illustrate most synchronous
counters. D flip-flops can also be used but generally require more logic because of having
no direct toggle or no-change states.
508 Counters

After completing this section, you should be able to

u Describe the operation of a 2-bit synchronous binary counter
u Describe the operation of a 3-bit synchronous binary counter
u Describe the operation of a 4-bit synchronous binary counter
u Describe the operation of a synchronous decade counter
u Develop counter timing diagrams

A 2-Bit Synchronous Binary Counter

Figure 9–12 shows a 2-bit synchronous binary counter. Notice that an arrangement differ-
ent from that for the asynchronous counter must be used for the J1 and K1 inputs of FF1
in order to achieve a binary sequence. A D flip-flop implementation is shown in part (b).

HIGH
FF0 FF1
Q0 Q0
D1
J0 J1 Q1 D0 Q1

C C C C

K0 K1 Q1

CLK CLK
(a) J-K flip-flop (b) D flip-flop

FIGURE 9–12 2-bit synchronous binary counters.

The clock input goes to each flip-flop The operation of a J-K flip-flop synchronous counter is as follows: First, assume that the
in a synchronous counter. counter is initially in the binary 0 state; that is, both flip-flops are RESET. When the positive
edge of the first clock pulse is applied, FF0 will toggle and Q0 will therefore go HIGH. What
happens to FF1 at the positive-going edge of CLK1? To find out, let’s look at the input con-
ditions of FF1. Inputs J1 and K1 are both LOW because Q0, to which they are connected, has
not yet gone HIGH. Remember, there is a propagation delay from the triggering edge of the
clock pulse until the Q output actually makes a transition. So, J = 0 and K = 0 when the
leading edge of the first clock pulse is applied. This is a no-change condition, and therefore
FF1 does not change state. A timing detail of this portion of the counter operation is shown
in Figure 9–13(a).

CLK1 CLK2

1 1
Q0 Propagation delay through FF0 Q0 Propagation delay through FF0
0 0

Q1 Q1 1 Propagation delay through FF1

0 0
(a) (b)

CLK3 CLK4

Q0 1 Propagation delay through FF0 Q0 1 Propagation delay through FF0

0 0
1 1
Q 1 Q1 Propagation delay through FF1
0
(c) (d)

FIGURE 9–13 Timing details for the 2-bit synchronous counter operation (the
propagation delays of both flip-flops are assumed to be equal).
 Synchronous Counters 509

After CLK1, Q 0 = 1 and Q 1 = 0 (which is the binary 1 state). When the leading edge
of CLK2 occurs, FF0 will toggle and Q0 will go LOW. Since FF1 has a HIGH (Q 0 = 1) on
its J1 and K1 inputs at the triggering edge of this clock pulse, the flip-flop toggles and Q1
goes HIGH. Thus, after CLK2, Q 0 = 0 and Q 1 = 1 (which is a binary 2 state). The timing
detail for this condition is shown in Figure 9–13(b).
When the leading edge of CLK3 occurs, FF0 again toggles to the SET state (Q 0 = 1),
and FF1 remains SET (Q 1 = 1) because its J1 and K1 inputs are both LOW (Q 0 = 0). After
this triggering edge, Q 0 = 1 and Q 1 = 1 (which is a binary 3 state). The timing detail is
shown in Figure 9–13(c).
Finally, at the leading edge of CLK4, Q0 and Q1 go LOW because they both have a toggle
condition on their J and K inputs. The timing detail is shown in Figure 9–13(d). The counter
has now recycled to its original state, binary 0. Examination of the D flip-flop counter in
Figure 9–12(b) will show the timing diagram is the same as for the J-K flip-flop counter.
The complete timing diagram for the counters in Figure 9–12 is shown in Figure 9–14.
Notice that all the waveform transitions appear coincident; that is, the propagation delays are
not indicated. Although the delays are an important factor in the synchronous counter opera-
tion, in an overall timing diagram they are normally omitted for simplicity. Major waveform
relationships resulting from the normal operation of a circuit can be conveyed completely
without showing small delay and timing differences. However, in high-speed digital circuits,
these small delays are an important consideration in design and troubleshooting.

FIGURE 9–14 Timing diagram

CLK 1 2 3 4
for the counters of Figure 9–12.

Q0

Q1

A 3-Bit Synchronous Binary Counter

A 3-bit synchronous binary counter is shown in Figure 9–15, and its timing diagram is
shown in Figure 9–16. You can understand this counter operation by examining its sequence
of states as shown in Table 9–3.
HIGH
FF0 FF1 Q0 Q1 FF2
Q0 Q1
J0 J1 J2 Q2

C C C

K0 K1 K2

CLK
FIGURE 9–15 A 3-bit synchronous binary counter. Open file F09-15 to verify the operation.

CLK 1 2 3 4 5 6 7 8

Q0

Q1

Q2

FIGURE 9–16 Timing diagram for the counter of Figure 9–15.

510 Counters

TABLE 9–3
State sequence for a 3-bit binary counter.
Clock Pulse Q2 Q1 Q0
Initially 0 0 0
1 0 0 1
InfoNote 2 0 1 0
3 0 1 1
The TSC or time stamp counter in 4 1 0 0
some microprocessors is used for 5 1 0 1
performance monitoring, which 6 1 1 0
enables a number of parameters 7 1 1 1
important to the overall perform- 8 (recycles) 0 0 0
ance of a system to be determined
exactly. By reading the TSC before
First, let’s look at Q0. Notice that Q0 changes on each clock pulse as the counter pro-
and after the execution of a proce-
gresses from its original state to its final state and then back to its original state. To produce
dure, the precise time required for
this operation, FF0 must be held in the toggle mode by constant HIGHs on its J0 and K0
the procedure can be determined
inputs. Notice that Q1 goes to the opposite state following each time Q0 is a 1. This change
based on the processor cycle time.
occurs at CLK2, CLK4, CLK6, and CLK8. The CLK8 pulse causes the counter to recycle.
In this way, the TSC forms the
To produce this operation, Q0 is connected to the J1 and K1 inputs of FF1. When Q0 is a 1
basis for all time evaluations in
and a clock pulse occurs, FF1 is in the toggle mode and therefore changes state. The other
connection with optimizing system
times, when Q0 is a 0, FF1 is in the no-change mode and remains in its present state.
operation. For example, it can
Next, let’s see how FF2 is made to change at the proper times according to the binary
be accurately determined which
sequence. Notice that both times Q2 changes state, it is preceded by the unique condi-
of two or more programming
tion in which both Q0 and Q1 are HIGH. This condition is detected by the AND gate and
sequences is more efficient. This
applied to the J2 and K2 inputs of FF2. Whenever both Q0 and Q1 are HIGH, the output of
is a very useful tool for compiler
the AND gate makes the J2 and K2 inputs of FF2 HIGH, and FF2 toggles on the following
developers and system program-
clock pulse. At all other times, the J2 and K2 inputs of FF2 are held LOW by the AND gate
mers in producing the most effec-
output, and FF2 does not change state.
tive code.
The analysis of the counter in Figure 9–15 is summarized in Table 9–4.

TABLE 9–4
Summary of the analysis of the counter in Figure 9–15.
Outputs J-K Inputs At the Next Clock Pulse
Clock Pulse Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 FF2 FF1 FF0
Initially 0 0 0 0 0 0 0 1 1 NC* NC Toggle
1 0 0 1 0 0 1 1 1 1 NC Toggle Toggle
2 0 1 0 0 0 0 0 1 1 NC NC Toggle
3 0 1 1 1 1 1 1 1 1 Toggle Toggle Toggle
4 1 0 0 0 0 0 0 1 1 NC NC Toggle
5 1 0 1 0 0 1 1 1 1 NC Toggle Toggle
6 1 1 0 0 0 0 0 1 1 NC NC Toggle
7 1 1 1 1 1 1 1 1 1 Toggle Toggle Toggle
Counter recycles back to 000.
*
NC indicates No Change.

A 4-Bit Synchronous Binary Counter

Figure 9–17(a) shows a 4-bit synchronous binary counter, and Figure 9–17(b) shows its
timing diagram. This particular counter is implemented with negative edge-triggered flip-
flops. The reasoning behind the J and K input control for the first three flip-flops is the
same as previously discussed for the 3-bit counter. The fourth stage, FF3, changes only
twice in the sequence. Notice that both of these transitions occur following the times that
Q0, Q1, and Q2 are all HIGH. This condition is decoded by AND gate G2 so that when a
 Synchronous Counters 511

HIGH

FF0 FF1 Q0 Q1 FF2 Q0 Q1 Q2 FF3

Q0 Q1 G1 G2
J0 J1 J2 J3 Q3
Q2

C C C C

K0 K1 K2 K3

CLK
(a)

Q0 Q1 Q 0 Q 1 Q2 Q0 Q1 Q0 Q1 Q2

CLK

Q0

Q1

Q2

Q3

(b)

FIGURE 9–17 A 4-bit synchronous binary counter and timing diagram. Times where the
AND gate outputs are HIGH are indicated by the shaded areas.

clock pulse occurs, FF3 will change state. For all other times the J3 and K3 inputs of FF3
are LOW, and it is in a no-change condition.

A 4-Bit Synchronous Decade Counter

As you know, a BCD decade counter exhibits a truncated binary sequence and goes from A decade counter has ten states.
0000 through the 1001 state. Rather than going from the 1001 state to the 1010 state, it
recycles to the 0000 state. A synchronous BCD decade counter is shown in Figure 9–18.
The timing diagram for the decade counter is shown in Figure 9–19.

HIGH

FF0 Q0 FF1 FF2 FF3

J0 J1 J2 J3
Q1 Q2 Q3

C C C C

Q3
K0 K1 K2 K3

CLK

FIGURE 9–18 A synchronous BCD decade counter. Open file F09-18 to verify operation.
512 Counters

CLK 1 2 3 4 5 6 7 8 9 10

Q0 0 1 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0 0 0

Q2 0 0 0 0 1 1 1 1 0 0 0

Q3 0 0 0 0 0 0 0 0 1 1 0

FIGURE 9–19 Timing diagram for the BCD decade counter (Q0 is the LSB).

The counter operation is shown by the sequence of states in Table 9–5. First, notice that
FF0 (Q0) toggles on each clock pulse, so the logic equation for its J0 and K0 inputs is
J0 = K0 = 1
This equation is implemented by connecting J0 and K0 to a constant HIGH level.

TABLE 9–5
States of a BCD decade counter.
Clock Pulse Q3 Q2 Q1 Q0
Initially 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 (recycles) 0 0 0 0

Next, notice in Table 9–5 that FF1 (Q1) changes on the next clock pulse each time
Q 0 = 1 and Q 3 = 0, so the logic equation for the J1 and K1 inputs is
J1 = K1 = Q 0Q 3
This equation is implemented by ANDing Q0 and Q 3 and connecting the gate output to the
J1 and K1 inputs of FF1.
Flip-flop 2 (Q2) changes on the next clock pulse each time both Q 0 = 1 and Q 1 = 1.
This requires an input logic equation as follows:
J2 = K2 = Q 0Q 1
This equation is implemented by ANDing Q0 and Q1 and connecting the gate output to the
J2 and K2 inputs of FF2.
Finally, FF3 (Q3) changes to the opposite state on the next clock pulse each time Q 0 = 1,
Q 1 = 1, and Q 2 = 1 (state 7), or when Q 0 = 1 and Q 3 = 1 (state 9). The equation for
this is as follows:
J3 = K3 = Q 0Q 1Q 2 + Q 0Q 3
This function is implemented with the AND/OR logic connected to the J3 and K3 inputs of
FF3 as shown in the logic diagram in Figure 9–18. Notice that the differences between this
 Synchronous Counters 513

decade counter and the modulus-16 binary counter in Figure 9–17(a) are the Q 0Q 3 AND
gate, the Q0Q3 AND gate, and the OR gate; this arrangement detects the occurrence of the
1001 state and causes the counter to recycle properly on the next clock pulse.

IMPLEMENTATION: 4-BIT SYNCHRONOUS BINARY COUNTER

Fixed-Function Device The 74HC163 is an example of an integrated circuit 4-bit syn-
chronous binary counter. A logic symbol is shown in Figure 9–20 with pin numbers in
parentheses. This counter has several features in addition to the basic functions previously
discussed for the general synchronous binary counter.

Data inputs

D0 D1 D2 D3

(3) (4) (5) (6)

(1)
CLR CTR DIV 16
(9)
LOAD
(10) (15)
ENT TC = 15 RCO
(7)
ENP
(2)
CLK C

(14) (13) (12) (11)

Q0 Q1 Q2 Q3

Data outputs

FIGURE 9–20 The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR
DIV 16 indicates a counter with sixteen states.)

First, the counter can be synchronously preset to any 4-bit binary number by applying
the proper levels to the parallel data inputs. When a LOW is applied to the LOAD input,
the counter will assume the state of the data inputs on the next clock pulse. Thus, the coun-
ter sequence can be started with any 4-bit binary number.
Also, there is an active-LOW clear input (CLR), which synchronously resets all four
flip-flops in the counter. There are two enable inputs, ENP and ENT. These inputs must
both be HIGH for the counter to sequence through its binary states. When at least one
input is LOW, the counter is disabled. The ripple clock output (RCO) goes HIGH when
the counter reaches the last state in its sequence of fifteen, called the terminal count
(TC = 15). This output, in conjunction with the enable inputs, allows these counters to be
cascaded for higher count sequences.
Figure 9–21 shows a timing diagram of this counter being preset to twelve (1100) and
then counting up to its terminal count, fifteen (1111). Input D0 is the least significant input
bit, and Q0 is the least significant output bit.
Let’s examine this timing diagram in detail. This will aid you in interpreting timing
diagrams in this chapter or on manufacturers’ data sheets. To begin, the LOW level pulse
on the CLR input causes all the outputs (Q0, Q1, Q2, and Q3) to go LOW.
Next, the LOW level pulse on the LOAD input synchronously enters the data on the
data inputs (D0, D1, D2, and D3) into the counter. These data appear on the Q outputs at the
time of the first positive-going clock edge after LOAD goes LOW. This is the preset opera-
tion. In this particular example, Q0 is LOW, Q1 is LOW, Q2 is HIGH, and Q3 is HIGH.
This, of course, is a binary 12 (Q0 is the LSB).
The counter now advances through states 13, 14, and 15 on the next three positive-
going clock edges. It then recycles to 0, 1, 2 on the following clock pulses. Notice that
514 Counters

CLR
LOAD

D0

D1
Data
inputs D2

D3

CLK

ENP

ENT
Q0

Q1
Outputs
Q2

Q3

RCO
12 13 14 15 0 1 2

Count Inhibit
Clear Preset

FIGURE 9–21 Timing example for a 74HC163.

both ENP and ENT inputs are HIGH during the state sequence. When ENP goes LOW, the
counter is inhibited and remains in the binary 2 state.
Programmable Logic Device (PLD) The VHDL code for a 4-bit synchronous decade
counter using J-K flip flops is as follows:
library ieee;
use ieee.std_logic_1164.all;
entity FourBitSynchDecadeCounter is
port (Clk: in std_logic; Q0, Q1, Q2, Q3: inout std_logic); Input and outputs
end entity FourBitSynchDecadeCounter; declared

architecture LogicOperation of FourBitSynchDecadeCounter is

component jkff is
port (J, K, Clk: in std_logic; Q: out std_logic); s Component declaration for
end component jkff; the J-K flip-flop

signal J1, J2, J3: std_logic;

begin
J1 6= Q0 and not Q3; Boolean expressions for J input
J2 6= Q1 and Q0; t
of each flip-flop (J = K)
J3 6= (Q2 and J2) or (Q0 and Q3);
FF0: jkff port map (J =7 ‘1’, K =7 ‘1’, Clk =7 Clk, Q =7 Q0);
FF1: jkff port map (J =7 J1, K =7 J1, Clk =7 Clk, Q =7 Q1); Instantiations define
t connections for each
FF2: jkff port map (J =7 J2, K =7 J2, Clk =7 Clk, Q =7 Q2);
FF3: jkff port map (J =7 J3, K =7 J3, Clk =7 Clk, Q =7 Q3); flip-flop.
end architecture LogicOperation;
 Up/Down Synchronous Counters 515

SECTION 9–3 CHECKUP

1. How does a synchronous counter differ from an asynchronous counter?

2. Explain the function of the preset feature of counters such as the 74HC163.
3. Describe the purpose of the ENP and ENT inputs and the RCO output for the
74HC163 counter.

9–4 Up/Down Synchronous Counters

An up/down counter is one that is capable of progressing in either direction through a
certain sequence. An up/down counter, sometimes called a bidirectional counter, can have
any specified sequence of states. A 3-bit binary counter that advances upward through
its sequence (0, 1, 2, 3, 4, 5, 6, 7) and then can be reversed so that it goes through the
sequence in the opposite direction (7, 6, 5, 4, 3, 2, 1, 0) is an illustration of up/down
sequential operation.
After completing this section, you should be able to
u Explain the basic operation of an up/down counter
u Discuss the 74HC190 up/down decade counter

In general, most up/down counters can be reversed at any point in their sequence. For
instance, the 3-bit binary counter can be made to go through the following sequence:
UP UP
¸˚˚˝˚˚˛ ¸˚˝˚˛
0, 1, 2, 3, 4, 5, ¸˝˛
4, 3, 2, 3, 4, 5, 6, 7, ¸˝˛
6, 5, etc.
DOWN DOWN
Table 9–6 shows the complete up/down sequence for a 3-bit binary counter. The arrows
indicate the state-to-state movement of the counter for both its UP and its DOWN modes
of operation. An examination of Q0 for both the up and down sequences shows that FF0
toggles on each clock pulse. Thus, the J0 and K0 inputs of FF0 are
J0 = K0 = 1

TABLE 9–6
Up/Down sequence for a 3-bit binary counter.
Clock Pulse Up Q2 Q1 Q0 Down
[ [ [ [ [ [ [ [

[ [ [ [ [ [ [ [

0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

For the up sequence, Q1 changes state on the next clock pulse when Q 0 = 1. For the down
sequence, Q1 changes on the next clock pulse when Q 0 = 0. Thus, the J1 and K1 inputs of
FF1 must equal 1 under the conditions expressed by the following equation:
J1 = K1 = (Q 0 # UP) + (Q 0 # DOWN)
516 Counters

For the up sequence, Q2 changes state on the next clock pulse when Q0 = Q 1 = 1. For
the down sequence, Q2 changes on the next clock pulse when Q0 = Q 1 = 0. Thus, the
J2 and K2 inputs of FF2 must equal 1 under the conditions expressed by the following
equation:
J2 = K2 = (Q0 # Q1 # UP) + (Q0 # Q1 # DOWN)
Each of the conditions for the J and K inputs of each flip-flop produces a toggle at the
appropriate point in the counter sequence.
Figure 9–22 shows a basic implementation of a 3-bit up/down binary counter using
the logic equations just developed for the J and K inputs of each flip-flop. Notice that the
UP/DOWN control input is HIGH for UP and LOW for DOWN.

UP
Q0 • UP

HIGH FF0 FF1 FF2

Q2
J0 J1 J2
Q0 Q1
UP/DOWN
C C C
Q0 Q1 Q2
K0 K1 K2

DOWN
Q0 • DOWN
CLK

FIGURE 9–22 A basic 3-bit up/down synchronous counter. Open file F09-22 to verify
operation.

EXAMPLE 9–3

Show the timing diagram and determine the sequence of a 4-bit synchronous binary
up/down counter if the clock and UP/DOWN control inputs have waveforms as shown
in Figure 9–23(a). The counter starts in the all-0s state and is positive edge-triggered.

UP/ DOWN
Up Down Up Down

CLK
(a)

Q0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 1 1 0 0 1 0 0 1 0 0

Q2 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0

Q3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
(b)

FIGURE 9–23
 Up/Down Synchronous Counters 517

Solution
The timing diagram showing the Q outputs is shown in Figure 9–23(b). From these
waveforms, the counter sequence is as shown in Table 9–7.

TABLE 9–7
Q3 Q2 Q1 Q0
0 0 0 0

˛˚˝˚¸ ˛˚˝˚¸ ˛˝¸

0 0 0 1
0 0 1 0 UP
0 0 1 1
0 1 0 0
0 0 1 1
0 0 1 0
0 0 0 1 DOWN
0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 1 UP
0 0 1 0
˛˝¸
0 0 0 1
DOWN
0 0 0 0

Related Problem
Show the timing diagram if the UP/DOWN control waveform in Figure 9–23(a) is
inverted.

IMPLEMENTATION: UP/DOWN DECADE COUNTER

Fixed-Function Device Figure 9–24 shows a logic diagram for the 74HC190, an example
of an integrated circuit up/down synchronous decade counter. The direction of the count is
determined by the level of the up/down input (D/U). When this input is HIGH, the counter
counts down; when it is LOW, the counter counts up. Also, this device can be preset to any
desired BCD digit as determined by the states of the data inputs when the LOAD input
is LOW.

D0 D1 D2 D3

(15) (1) (10) (9)

(4) (12)
CTEN MAX/MIN
(5)
D/U
(11) CTR DIV 10
LOAD
(14) (13)
CLK C RCO

(3) (2) (6) (7)

Q0 Q1 Q2 Q3

FIGURE 9–24 The 74HC190 up/down synchronous decade counter.

518 Counters

The MAX/MIN output produces a HIGH pulse when the terminal count nine (1001)
is reached in the UP mode or when the terminal count zero (0000) is reached in the
DOWN mode. The MAX/MIN output, the ripple clock output (RCO), and the count enable
input (CTEN) are used when cascading counters. (Cascaded counters are discussed in
Section 9–6.)
Figure 9–25 is a timing diagram that shows the 74HC190 counter preset to seven
(0111) and then going through a count-up sequence followed by a count-down sequence.
The MAX/MIN output is HIGH when the counter is in either the all-0s state (MIN) or the
1001 state (MAX).

LOAD
D0

D1
Data
inputs D2

D3

CLK
D/U
CTEN

Q0

Data Q1
outputs
Q2

Q3

MAX/MIN

RCO
7 8 9 0 1 2 2 2 1 0 9 8 7

Count up Inhibit Count down

Load

FIGURE 9–25 Timing example for a 74HC190.

Programmable Logic Device (PLD) A VHDL code for an up/down decade counter using
J-K flip-flops is as follows:

library ieee;
use ieee.std_logic_1164.all;

entity UpDnDecadeCntr is UPDN: Counter direction

port (UPDN, Clk: in std_logic; Q0, Q1, Q2, Q3: buffer std_logic); Clk: System clock
end entity UpDnDecadeCntr; Q0-Q3: Counter output

architecture LogicOperation of UpDnDecadeCntr is

component jkff is
port (J, K, Clk: in std_logic; Q: buffer std_logic); s J-K flip flop component
end component jkff;
 Design of Synchronous Counters 519

function UpDown(A, B, C, D: in std_logic)

return std_logic is Function UpDown is a helper function performing the common
begin u logic between stages performed by the two AND gates applied
return((A and B) or (C and D)); to the OR gate supplying the J K inputs of the next stage. See
end function UpDown; Figure 9–22.
J1Up: Initial Up logic for FF1.
signal J1Up, J1Dn, J1, J2, J3: std_logic; J1Dn: Initial Down logic for FF1.
J1-J3: Variable for combined UpDown applied to FF1-FF3.
begin
J1Up 6= UPDN and Q0; J1Dn <= not UPDN and not Q0; Identifiers J1, J2, and J3 complete the
UpDn1: J1 6= UpDown(UPDN, Q0, not UPDN, not Q0); up/down logic applied to the J and K
UpDn2: J2 6= UpDown(J1Up, Q1, J1Dn, not Q1); t inputs of flip-flop stages FF0-FF1.
UpDn3: J3 6= UpDown(J1Up and Q1, Q2, J1Dn and not Q1, not Q2); Using a function to perform operations
common to multiple tasks simplifies the
FF0: jkff port map (J =7‘1’, K =7‘1’, Clk =7 Clk, Q =7 Q0); overall code design and implementation.
FF1: jkff port map (J =7 J1, K =7 J1, Clk =7 Clk, Q =7 Q1); Flip-flop stages FF0-FF3 complete the
FF2: jkff port map (J =7 J2, K =7 J2, Clk =7 Clk, Q =7 Q2); t Up/Down counter.
FF3: jkff port map (J =7 J3, K =7 J3, Clk =7 Clk, Q =7 Q3);
end architecture LogicOperation;

SECTION 9–4 CHECKUP

1. A 4-bit up/down binary counter is in the DOWN mode and in the 1010 state. On the
next clock pulse, to what state does the counter go?
2. What is the terminal count of a 4-bit binary counter in the UP mode? In the DOWN
mode? What is the next state after the terminal count in the DOWN mode?

9–5 Design of Synchronous Counters

In this section, you will learn the six steps to design a counter (state machine). As you
learned in Section 9–1, sequential circuits can be classified into two types: (1) those in
which the output or outputs depend only on the present internal state (Moore state machines)
and (2) those in which the output or outputs depend on both the present state and the input
or inputs (Mealy state machines). This section is recommended for those who want an
introduction to counter design or to state machine design in general. It is not a prerequisite
for any other material.
After completing this section, you should be able to
u Develop a state diagram for a given sequence
u Develop a next-state table for a specified counter sequence
u Create a flip-flop transition table
u Use the Karnaugh map method to derive the logic requirements for a synchronous
counter
u Implement a counter to produce a specified sequence of states

Step 1: State Diagram

The first step in the design of a state machine (counter) is to create a state diagram. A state
diagram shows the progression of states through which the counter advances when it is
520 Counters

clocked. As an example, Figure 9–26 is a state diagram for a basic 3-bit Gray code counter.
This particular circuit has no inputs other than the clock and no outputs other than the
outputs taken off each flip-flop in the counter. You may wish to review the coverage of the
Gray code in Chapter 2 at this time.

000
100 001

101 011

111 010
110

FIGURE 9–26 State diagram for a 3-bit Gray code counter.

Step 2: Next-State Table

Once the sequential circuit is defined by a state diagram, the second step is to derive a
next-state table, which lists each state of the counter (present state) along with the cor-
responding next state. The next state is the state that the counter goes to from its present
state upon application of a clock pulse. The next-state table is derived from the state
diagram and is shown in Table 9–8 for the 3-bit Gray code counter. Q0 is the least sig-
nificant bit.

TABLE 9–8 TABLE 9–9

Next-state table for 3-bit Gray code counter. Transition table for a J-K flip-flop.
Present State Next State Output Transitions Flip-Flop Inputs
Q2 Q1 Q0 Q2 Q1 Q0 QN QN 1 1 J K
0 0 0 0 0 1 0 ¡ 0 0 X
0 0 1 0 1 1 0 ¡ 1 1 X
0 1 1 0 1 0 1 ¡ 0 X 1
0 1 0 1 1 0 1 ¡ 1 X 0
1 1 0 1 1 1
QN: present state
1 1 1 1 0 1
QN + 1: next state
1 0 1 1 0 0
X: “don’t care”
1 0 0 0 0 0

Step 3: Flip-Flop Transition Table

Table 9–9 is a transition table for the J-K flip-flop. All possible output transitions are
listed by showing the Q output of the flip-flop going from present states to next states.
QN is the present state of the flip-flop (before a clock pulse) and QN + 1 is the next state
(after a clock pulse). For each output transition, the J and K inputs that will cause the
transition to occur are listed. An X indicates a “don’t care” (the input can be either a 1
or a 0).
To design the counter, the transition table is applied to each of the flip-flops in the
counter, based on the next-state table (Table 9–8). For example, for the present state 000,
 Design of Synchronous Counters 521

Q0 goes from a present state of 0 to a next state of 1. To make this happen, J0 must be a
1 and you don’t care what K0 is (J0 = 1, K0 = X), as you can see in the transition table
(Table 9–9). Next, Q1 is 0 in the present state and remains a 0 in the next state. For this
transition, J1 = 0 and K1 = X. Finally, Q2 is 0 in the present state and remains a 0 in the
next state. Therefore, J2 = 0 and K2 = X. This analysis is repeated for each present state
in Table 9–8.

Step 4: Karnaugh Maps

Karnaugh maps can be used to determine the logic required for the J and K inputs of each
flip-flop in the counter. There is a Karnaugh map for the J input and a Karnaugh map for
the K input of each flip-flop. In this design procedure, each cell in a Karnaugh map repre-
sents one of the present states in the counter sequence listed in Table 9–8.
From the J and K states in the transition table (Table 9–9) a 1, 0, or X is entered into each
present-state cell on the maps depending on the transition of the Q output for a particular
flip-flop. To illustrate this procedure, two sample entries are shown for the J0 and the K0
inputs to the least significant flip-flop (Q0) in Figure 9–27.

J0 map K0 map
Q0 Q0
Q2Q1 0 1 Q2Q1 0 1

The values of J0 and K0 required 00 1 00 X

to produce the transition are
placed on each map in the
present-state cell. 01 01

11 11

10 X 10 1
The values of J0 and K0 required
to produce the transition are
placed on each map in the
present-state cell.

Output Flip-Flop Present State Next State For the present state 000, Q0
makes a transition from 0 to 1
Transitions Inputs Q2 Q1 Q0 Q2 Q1 Q0 to the next state.
QN QN+1 J K
0 0 0 0 0 1
0 0 0 X 0 0 1 0 1 1
0 1 1 X 0 1 1 0 1 0 For the present state 101, Q0
1 0 X 1 0 1 0 1 1 0 makes a transition from 1 to 0
1 1 X 0 1 1 0 1 1 1 to the next state.
1 1 1 1 0 1
Flip-flop transition table 1 0 1 1 0 0
1 0 0 0 0 0

Next-state table

FIGURE 9–27 Examples of the mapping procedure for the counter sequence
represented in Table 9–8 and Table 9–9.

The completed Karnaugh maps for all three flip-flops in the counter are shown in
Figure 9–28. The cells are grouped as indicated and the corresponding Boolean expres-
sions for each group are derived.
522 Counters

Q0 Q0 Q0
Q2Q1 0 1 Q2Q1 0 1 Q2Q1 0 1

00 0 0 00 0 1 Q2Q0 00 1 X Q2Q1

01 1 0 01 X X 01 0 X
Q1Q0 X X X X X
11 11 11 1 Q2Q1

10 X X 10 0 0 10 0 X

J2 map J1 map J0 map

Q0 Q0 Q0
Q2Q1 0 1 Q2Q1 0 1 Q2Q1 0 1

00 X X 00 X X 00 X 0

01 X X 01 0 0 01 X 1 Q2Q1

11 0 0 11 0 1 Q2Q0 0 11 X

10 1 0 10 X X 10 X 1 Q2Q1

Q1Q0 K2 map K1 map K0 map

FIGURE 9–28 Karnaugh maps for present-state J and K inputs.

Step 5: Logic Expressions for Flip-Flop Inputs

From the Karnaugh maps of Figure 9–28 you obtain the following expressions for the J and
K inputs of each flip-flop:
J0 = Q 2Q 1 + Q 2Q 1 = Q 2  Q 1
K0 = Q 2Q 1 + Q 2Q 1 = Q 2  Q 1
J1 = Q 2Q 0
K1 = Q 2Q 0
J2 = Q 1Q 0
K2 = Q 1Q 0

Step 6: Counter Implementation

The final step is to implement the combinational logic from the expressions for the J and
K inputs and connect the flip-flops to form the complete 3-bit Gray code counter as shown
in Figure 9–29.

FF0 FF1 FF2

Q0 Q2
J0 J1 J2
Q1
C C C
Q0 Q1 Q2
K0 K1 K2

CLK

FIGURE 9–29 Three-bit Gray code counter. Open file F09-29 to verify operation.
 Design of Synchronous Counters 523

A summary of steps used in the design of the 3-bit Gray code counter follows. In gen-
eral, these steps can be applied to any state machine.
1. Specify the counter sequence and draw a state diagram.
2. Derive a next-state table from the state diagram.
3. Develop a transition table showing the flip-flop inputs required for each transition.
The transition table is always the same for a given type of flip-flop.
4. Transfer the J and K states from the transition table to Karnaugh maps. There is a
Karnaugh map for each input of each flip-flop.
5. Group the Karnaugh map cells to generate and derive the logic expression for each
flip-flop input.
6. Implement the expressions with combinational logic, and combine with the flip-flops
to create the counter.
This procedure is now applied to the design of other synchronous counters in Examples
9–4 and 9–5.

EXAMPLE 9–4

Design a counter with the irregular binary count sequence shown in the state diagram of
Figure 9–30. Use D flip-flops.

001
(1)

111 010
(7) (2)

101
(5)

FIGURE 9–30

Solution
Step 1: The state diagram is as shown. Although there are only four states, a 3-bit
counter is required to implement this sequence because the maximum binary
count is seven. Since the required sequence does not include all the possible
binary states, the invalid states (0, 3, 4, and 6) can be treated as “don’t cares”
in the design. However, if the counter should erroneously get into an invalid
state, you must make sure that it goes back to a valid state.
Step 2: The next-state table is developed from the state diagram and is given in
Table 9–10.

TABLE 9–10
Next-state table.
Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0

0 0 1 0 1 0
0 1 0 1 0 1
1 0 1 1 1 1
1 1 1 0 0 1
524 Counters

Step 3: The transition table for the D flip-flop is shown in Table 9–11.

TABLE 9–11
Transition table for a D flip-flop.
Output Transitions Flip-Flop Input
QN QN 1 1 D

0 ¡ 0 0
0 ¡ 1 1
1 ¡ 0 0
1 ¡ 1 1

Step 4: The D inputs are plotted on the present-state Karnaugh maps in Figure 9–31.
Also “don’t cares” can be placed in the cells corresponding to the invalid
states of 000, 011, 100, and 110, as indicated by the red Xs.

Q0 Q0 Q0
Q2Q1 0 1 Q2Q1 0 1 Q2Q1 0 1

00 X 0 00 X 1 00 X 0

01 1 X 01 0 X 01 1 X

11 X 0 11 X 0 Q0 11 X 1
Q0 X 1 X 1 X 1
10 10 10
Q2Q1 Q1 Q2
D2 map D1 map D0 map

FIGURE 9–31

Step 5: Group the 1s, taking advantage of as many of the “don’t care” states as pos-
sible for maximum simplification, as shown in Figure 9–31. The expression
for each D input taken from the maps is as follows:
D0 = Q 0 + Q 2
D1 = Q 1
D2 = Q 0 + Q 2 Q 1
Step 6: The implementation of the counter is shown in Figure 9–32.

Q0 Q1

Q2
D0 D1 D2

C C C
Q0 Q1

CLK
FIGURE 9–32
 Design of Synchronous Counters 525

An analysis shows that if the counter, by accident, gets into one of the invalid states
(0, 3, 4, 6), it will always return to a valid state according to the following sequences:
0 S 3 S 4 S 7, and 6 S 1.

Related Problem
Verify the analysis that proves the counter will always return (eventually) to a valid
state from an invalid state.

EXAMPLE 9–5

Develop a synchronous 3-bit up/down counter with a Gray code sequence using J-K flip-flops. The counter should count up
when an UP/DOWN control input is 1 and count down when the control input is 0.

Solution
Step 1: The state diagram is shown in Figure 9–33. The 1 or 0 beside each arrow indicates the state of the UP/DOWN
control input, Y.

1 000 Y=1

100 0 001
Y=0
1
1
0 0

101 011

0 0
1
1
111 0 0 010

1 110 1

FIGURE 9–33 State diagram for a 3-bit up/down Gray code counter.

Step 2: The next-state table is derived from the state diagram and is shown in Table 9–12. Notice that for each present state
there are two possible next states, depending on the UP/DOWN control variable, Y.

TABLE 9–12
Next-state table for 3-bit up/down Gray code counter.
Next State
Present State Y  0 (DOWN) Y  1 (UP)
Q2 Q1 Q0 Q2 Q1 Q0 Q2 Q1 Q0

0 0 0 1 0 0 0 0 1
0 0 1 0 0 0 0 1 1
0 1 1 0 0 1 0 1 0
0 1 0 0 1 1 1 1 0
1 1 0 0 1 0 1 1 1
1 1 1 1 1 0 1 0 1
1 0 1 1 1 1 1 0 0
1 0 0 1 0 1 0 0 0
Y = UP/ DOWN control input.
526 Counters

Step 3: The transition table for the J-K flip-flops is repeated in Table 9–13.

TABLE 9–13
Transition table for a J-K flip-flop.
Output Transitions Flip-Flop Inputs
QN QN 1 1 J K

0 ¡ 0 0 X
0 ¡ 1 1 X
1 ¡ 0 X 1
1 ¡ 1 X 0

Step 4: The Karnaugh maps for the J and K inputs of the flip-flops are shown in Figure 9–34. The UP/DOWN control
input, Y, is considered one of the state variables along with Q0, Q1, and Q2. Using the next-state table, the informa-
tion in the “Flip-Flop Inputs” column of Table 9–13 is transferred onto the maps as indicated for each present state
of the counter.

Q2Q0Y Q2Q1Y
Q0Y Q0Y Q0Y
Q2Q1 00 01 11 10 Q2Q1 00 01 11 10 Q2Q1 00 01 11 10
Q2Q1Y
00 1 0 0 0 00 0 0 1 0 00 0 1 X X

01 0 1 0 0 01 X X X X 01 1 0 X X
Q1Q0Y Q2Q1Y
11 X X X X 11 X X X X 11 0 1 X X

10 X X X X 10 0 0 0 1 10 1 0 X X

Q1Q0Y J2 map J1 map J0 map

Q2Q0Y Q2Q1Y

Q2Q0Y
Q0Y Q0Y Q0Y Q2Q1Y
Q2Q1 00 01 11 10 Q2Q1 00 01 11 10 Q2Q1 00 01 11 10

00 X X X X 00 X X X X 00 X X 0 1
Q2Q1Y
01 X X X X 01 0 0 0 1 01 X X 1 0
Q1Q0Y
11 1 0 0 0 11 0 0 1 0 11 X X 0 1

10 0 1 0 0 10 X X X X 10 X X 1 0 Q2Q1Y

K2 map K1 map K0 map

Q1Q0Y Q2Q0Y Q2Q1Y

FIGURE 9–34 J and K maps for Table 9–12. The UP/DOWN control input, Y, is treated
as a fourth variable.

Step 5: The 1s are combined in the largest possible groupings, with “don’t cares” (Xs) used where possible. The groups
are factored, and the expressions for the J and K inputs are as follows:
J0 = Q 2Q 1Y + Q 2Q 1Y + Q 2Q 1Y + Q 2Q 1Y K 0 = Q 2Q 1Y + Q 2Q 1Y + Q 2Q 1Y + Q 2Q 1Y
J1 = Q 2Q 0Y + Q 2Q 0Y K 1 = Q 2Q 0Y + Q 2Q 0Y
J2 = Q 1Q 0Y + Q 1Q 0Y K 2 = Q 1Q 0Y + Q 1Q 0Y
Step 6: The J and K equations are implemented with combinational logic. This step is the Related Problem.

Related Problem
Specify the number of flip-flops, gates, and inverters that are required to implement the logic described in Step 5.
 Cascaded Counters 527

SECTION 9–5 CHECKUP

1. A flip-flop is presently in the RESET state and must go to the SET state on the next
clock pulse. What must J and K be?
2. A flip-flop is presently in the SET state and must remain SET on the next clock pulse.
What must J and K be?
3. A binary counter is in the Q 3Q 2Q 1Q 0 = 1010 state.
(a) What is its next state?
(b) What condition must exist on each flip-flop input to ensure that it goes to the
proper next state on the clock pulse?

9–6 Cascaded Counters

Counters can be connected in cascade to achieve higher-modulus operation. In essence,
cascading means that the last-stage output of one counter drives the input of the next counter.
After completing this section, you should be able to
u Determine the overall modulus of cascaded counters
u Analyze the timing diagram of a cascaded counter configuration
u Use cascaded counters as a frequency divider
u Use cascaded counters to achieve specified truncated sequences

Asynchronous Cascading
An example of two asynchronous counters connected in cascade is shown in Figure 9–35
for a 2-bit and a 3-bit ripple counter. The timing diagram is shown in Figure 9–36. Notice

HIGH HIGH

J0 J1 J2 J3 J4
Q4

CLK C C C C C

K0 K1 K2 K3 K4
Q0 Q1 Q2 Q3

Modulus-4 counter Modulus-8 counter

FIGURE 9–35 Two cascaded asynchronous counters (all J and K inputs are HIGH).

CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Q0

Q1

Q2

Q3

Q4

FIGURE 9–36 Timing diagram for the cascaded counter configuration of Figure 9–35.
528 Counters

The overall modulus of cascaded that the final output of the modulus-8 counter, Q4, occurs once for every 32 input clock
counters is equal to the product of pulses. The overall modulus of the two cascaded counters is 4 * 8 = 32; that is, they act
the individual moduli. as a divide-by-32 counter.

Synchronous Cascading
When operating synchronous counters in a cascaded configuration, it is necessary to use
InfoNote the count enable and the terminal count functions to achieve higher-modulus operation.
On some devices the count enable is labeled simply CTEN (or some other designation
The time stamp counter (TSC),
such as G), and terminal count (TC) is analogous to ripple clock output (RCO) on some IC
mentioned in the last InfoNote, is
counters.
a 64-bit counter. It is interesting
Figure 9–37 shows two decade counters connected in cascade. The terminal count (TC)
to observe that if this counter (or
output of counter 1 is connected to the count enable (CTEN) input of counter 2. Counter 2
any full-modulus 64-bit counter)
is inhibited by the LOW on its CTEN input until counter 1 reaches its last, or terminal, state
is clocked at a frequency of 1 GHz,
and its terminal count output goes HIGH. This HIGH now enables counter 2, so that when
it will take 583 years for it to go
the first clock pulse after counter 1 reaches its terminal count (CLK10), counter 2 goes
through all of its states and reach
from its initial state to its second state. Upon completion of the entire second cycle of coun-
its terminal count. In contrast,
ter 1 (when counter 1 reaches terminal count the second time), counter 2 is again enabled
a 32-bit full-modulus counter
and advances to its next state. This sequence continues. Since these are decade counters,
will exhaust all of its states in
counter 1 must go through ten complete cycles before counter 2 completes its first cycle.
approximately 4.3 seconds when
In other words, for every ten cycles of counter 1, counter 2 goes through one cycle. Thus,
clocked at 1 GHz. The difference is
counter 2 will complete one cycle after one hundred clock pulses. The overall modulus of
astounding.
these two cascaded counters is 10 * 10 = 100.

HIGH
Counter 1 ƒin Counter 2
10 ƒin
CTEN CTEN TC
100
CTR DIV 10 TC CTR DIV 10
CLK C Q0 Q1 Q2 Q3 C Q0 Q1 Q2 Q3
ƒin

FIGURE 9–37 A modulus-100 counter using two cascaded decade counters.

When viewed as a frequency divider, the circuit of Figure 9–37 divides the input clock
frequency by 100. Cascaded counters are often used to divide a high-frequency clock sig-
nal to obtain highly accurate pulse frequencies. Cascaded counter configurations used for
such purposes are sometimes called countdown chains. For example, suppose that you have
a basic clock frequency of 1 MHz and you wish to obtain 100 kHz, 10 kHz, and 1 kHz;
a series of cascaded decade counters can be used. If the 1 MHz signal is divided by 10,
the output is 100 kHz. Then if the 100 kHz signal is divided by 10, the output is 10 kHz.
Another division by 10 produces the 1 kHz frequency. The general implementation of this
countdown chain is shown in Figure 9–38.

HIGH 100 kHz 10 kHz 1 kHz

CTEN TC CTEN TC CTEN TC

CTR DIV 10 CTR DIV 10 CTR DIV 10
1 MHz C C C

FIGURE 9–38 Three cascaded decade counters forming a divide-by-1000 frequency

divider with intermediate divide-by-10 and divide-by-100 outputs.
 Cascaded Counters 529

EXAMPLE 9–6

Determine the overall modulus of the two cascaded counter configurations in Figure 9–39.

Input CTR DIV 8 CTR DIV 12 CTR DIV 16 Output

(a)

Input CTR DIV 10 CTR DIV 4 CTR DIV 7 CTR DIV 5 Output

(b)

FIGURE 9–39

Solution
In Figure 9–39(a), the overall modulus for the 3-counter configuration is
8 * 12 * 16 = 1536
In Figure 9–39(b), the overall modulus for the 4-counter configuration is
10 * 4 * 7 * 5 = 1400

Related Problem
How many cascaded decade counters are required to divide a clock frequency by 100,000?

EXAMPLE 9–7

Use 74HC190 up/down decade counters connected in the UP mode to obtain a 10 kHz waveform from a 1 MHz clock.
Show the logic diagram.

Solution
To obtain 10 kHz from a 1 MHz clock requires a division factor of 100. Two 74HC190 counters must be cascaded as shown
in Figure 9–40. The left counter produces a terminal count (MAX/MIN) pulse for every 10 clock pulses. The right counter
produces a terminal count (MAX/MIN) pulse for every 100 clock pulses.

LOAD D0 D1 D2 D3 LOAD D0 D1 D2 D3

(15) (1) (10) (9) (15) (1) (10) (9)

CTR DIV 10 CTR DIV 10
(11) (11)
LOAD LOAD
(4) (12) (4) (12)
CTEN MAX/MIN CTEN MAX/MIN 10 kHz
(5) (5)
D/U D/U
(14) (14)
C C
(3) (2) (6) (7) (3) (2) (6) (7)
CLK
1 MHz
Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3

FIGURE 9–40 A divide-by-100 counter using two 74HC190 up/down decade counters
connected for the up sequence.

Related Problem
Determine the frequency of the waveform at the Q0 output of the second counter (the one on the right) in Figure 9–40.
530 Counters

Cascaded Counters with Truncated Sequences

The preceding discussion has shown how to achieve an overall modulus (divide-by-factor)
that is the product of the individual moduli of all the cascaded counters. This can be con-
sidered full-modulus cascading.
Often an application requires an overall modulus that is less than that achieved by full-
modulus cascading. That is, a truncated sequence must be implemented with cascaded
counters. To illustrate this method, we will use the cascaded counter configuration in
Figure 9–41. This particular circuit uses four 74HC161 4-bit synchronous binary coun-
ters. If these four counters (sixteen bits total) were cascaded in a full-modulus arrange-
ment, the modulus would be
216 = 65,536

LOAD
LSD 016 C16 316 616 MSD

0 0 0 0 1 1 0 0 0 0 1 1 0 1 1 0
HIGH

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
ENP ENP ENP ENP
ENT RCO ENT RCO ENT RCO ENT RCO
C C C C
CTR DIV 16 CTR DIV 16 CTR DIV 16 CTR DIV 16

Output

CLK
FIGURE 9–41 A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note
that each of the parallel data inputs is shown in binary order (the right-most bit D0 is the
LSB in each counter).

Let’s assume that a certain application requires a divide-by-40,000 counter (modulus

40,000). The difference between 65,536 and 40,000 is 25,536, which is the number of
states that must be deleted from the full-modulus sequence. The technique used in the cir-
cuit of Figure 9–41 is to preset the cascaded counter to 25,536 (63C0 in hexadecimal) each
time it recycles, so that it will count from 25,536 up to 65,535 on each full cycle. Therefore,
each full cycle of the counter consists of 40,000 states.
Notice in Figure 9–41 that the RCO output of the right-most counter is inverted and
applied to the LOAD input of each 4-bit counter. Each time the count reaches its terminal
value of 65,535, which is 11111111111111112, RCO goes HIGH and causes the number
on the parallel data inputs (63C016) to be synchronously loaded into the counter with the
clock pulse. Thus, there is one RCO pulse from the right-most 4-bit counter for every
40,000 clock pulses.
With this technique any modulus can be achieved by synchronous loading of the counter
to the appropriate initial state on each cycle.

SECTION 9–6 CHECKUP

1. How many decade counters are necessary to implement a divide-by-1000 (modulus-

1000) counter? A divide-by-10,000?
2. Show with general block diagrams how to achieve each of the following, using a flip-
flop, a decade counter, and a 4-bit binary counter, or any combination of these:
(a) Divide-by-20 counter (b) Divide-by-32 counter
(c) Divide-by-160 counter (d) Divide-by-320 counter
 Counter Decoding 531

9–7 Counter Decoding

In many applications, it is necessary that some or all of the counter states be decoded.
The decoding of a counter involves using decoders or logic gates to determine when
the counter is in a certain binary state in its sequence. For instance, the terminal count
function previously discussed is a single decoded state (the last state) in the counter
sequence.
After completing this section, you should be able to
u Implement the decoding logic for any given state in a counter sequence
u Explain why glitches occur in counter decoding logic
u Use the method of strobing to eliminate decoding glitches

Suppose that you wish to decode binary state 6 (110) of a 3-bit binary counter. When
Q 2 = 1, Q 1 = 1, and Q 0 = 0, a HIGH appears on the output of the decoding gate, indi-
cating that the counter is at state 6. This can be done as shown in Figure 9–42. This is called
active-HIGH decoding. Replacing the AND gate with a NAND gate provides active-LOW
decoding.

HIGH

Q0 Q1 Q2
J0 J1 J2

C C C
Q0 Q1 Q2
K0 K1 K2

CLK
1 1 1
LSB MSB

Decoded 6
Q 2Q 1Q 0

FIGURE 9–42 Decoding of state 6 (110). Open file F09-42 to verify operation.

EXAMPLE 9–8

Implement the decoding of binary state 2 and binary state 7 of a 3-bit synchronous
counter. Show the entire counter timing diagram and the output waveforms of the
decoding gates. Binary 2 = Q 2Q 1Q 0 and binary 7 = Q2Q1Q0.

Solution
See Figure 9–43. The 3-bit counter was originally discussed in Section 9–3 (Figure 9–15).
532 Counters

HIGH

FF0 FF1 FF2

LSB MSB
Q1
J0 J1 J2 Q2
Q0

C C C
Q0 Q2
K0 K1 K2

CLK

7
2

CLK 1 2 3 4 5 6 7 8

Q0

Q1

Q2

2
Decoded
outputs
7

FIGURE 9–43 A 3-bit counter with active-HIGH decoding of count 2 and count 7.
Open file F09-43 to verify operation.

Related Problem
Show the logic for decoding state 5 in the 3-bit counter.

Decoding Glitches
A glitch is an unwanted spike of The problem of glitches produced by the decoding process was discussed in Chapter 6. As
voltage. you have learned, the propagation delays due to the ripple effect in asynchronous coun-
ters create transitional states in which the counter outputs are changing at slightly dif-
ferent times. These transitional states produce undesired voltage spikes of short duration
(glitches) on the outputs of a decoder connected to the counter. The glitch problem can also
occur to some degree with synchronous counters because the propagation delays from the
clock to the Q outputs of each flip-flop in a counter can vary slightly.
Figure 9–44 shows a basic asynchronous BCD decade counter connected to a BCD-to-
decimal decoder. To see what happens in this case, let’s look at a timing diagram in which the
propagation delays are taken into account, as shown in Figure 9–45. Notice that these delays
cause false states of short duration. The value of the false binary state at each critical transi-
tion is indicated on the diagram. The resulting glitches can be seen on the decoder outputs.
 Counter Decoding 533

CTR DIV 10 BCD/DEC

0
1
Q0 2
1
Q1 3
2 4
Q2
4 5
Q3
6
8
7
8
CLK C
EN 9

FIGURE 9–44 A basic decade (BCD) counter and decoder.

CLK 1 2 3 4 5 6 7 8 9 10

Q0

Q1
Counter
outputs Q2

Q3
0100 0100
0000 0010 0110 0000 1000
0000
0

Decoder 4
outputs
5

FIGURE 9–45 Outputs with glitches from the decoder in Figure 9–44. Glitch widths are
exaggerated for illustration and are usually only a few nanoseconds wide.

One way to eliminate the glitches is to enable the decoded outputs at a time after the
glitches have had time to disappear. This method is known as strobing and can be accom-
plished in the case of an active-HIGH clock by using the LOW level of the clock to enable
the decoder, as shown in Figure 9–46. The resulting improved timing diagram is shown in
Figure 9–47.
534 Counters

CTR DIV 10 BCD/DEC

0
1
Q0 2
1
Q1 3
2 4
Q2
4 5
Q3
6
8
7
8
C EN 9

CLK/STROBE
FIGURE 9–46 The basic decade counter and decoder with strobing to eliminate glitches.

CLK/STROBE 1 2 3 4 5 6 7 8 9 10

4
Decoder
outputs 5

FIGURE 9–47 Strobed decoder outputs for the circuit of Figure 9–46.

SECTION 9–7 CHECKUP

1. What transitional states are possible when a 4-bit asynchronous binary counter
changes from
(a) count 2 to count 3 (b) count 3 to count 4
(c) count 1010 to count 1110 (d) count 15 to count 0

9–8 Counter Applications

The digital counter is a useful and versatile device that is found in many applications. In
this section, some representative counter applications are presented.
After completing this section, you should be able to
u Describe how counters are used in a basic digital clock system
u Explain how a divide-by-60 counter is implemented and how it is used in a digital
clock
 Counter Applications 535

u Explain how the hours counter is implemented

u Discuss the application of a counter in an automobile parking control system
u Describe how a counter is used in the process of parallel-to-serial data conversion

A Digital Clock
A common example of a counter application is in timekeeping systems. Figure 9–48 is a
simplified logic diagram of a digital clock that displays seconds, minutes, and hours. First,
a 60 Hz sinusoidal ac voltage is converted to a 60 Hz pulse waveform and divided down to
a 1 Hz pulse waveform by a divide-by-60 counter formed by a divide-by-10 counter fol-
lowed by a divide-by-6 counter. Both the seconds and minutes counts are also produced by
divide-by-60 counters, the details of which are shown in Figure 9–49. These counters count
from 0 to 59 and then recycle to 0; synchronous decade counters are used in this particular
implementation. Notice that the divide-by-6 portion is formed with a decade counter with
a truncated sequence achieved by using the decoder count 6 to asynchronously clear the
counter. The terminal count, 59, is also decoded to enable the next counter in the chain.

Divide-by-60
60 Hz ac 60 Hz 1 Hz
Wave- CTR DIV 10 CTR DIV 6
shaping C EN
circuit C

FF Hours counter Minutes counter (divide-by-60) Seconds counter (divide-by-60)

Q CTR DIV 10 CTR DIV 6 CTR DIV 10 CTR DIV 6 CTR DIV 10 EN
C EN EN EN EN
C C C C C

BCD/7-seg BCD/7-seg BCD/7-seg BCD/7-seg BCD/7-seg BCD/7-seg

(0–1) (0–9) (0–5) (0–9) (0–5) (0–9)

Hours Minutes Seconds

FIGURE 9–48 Simplified logic diagram for a 12-hour digital clock. Logic details using
specific devices are shown in Figures 9–49 and 9–50.

The hours counter is implemented with a decade counter and a flip-flop as shown in Figure
9–50. Consider that initially both the decade counter and the flip-flop are RESET, and the
decode-12 gate and decode-9 gate outputs are HIGH. The decade counter advances through all
of its states from zero to nine, and on the clock pulse that recycles it from nine back to zero, the
flip-flop goes to the SET state (J = 1, K = 0). This illuminates a 1 on the tens-of-hours dis-
play. The total count is now ten (the decade counter is in the zero state and the flip-flop is SET).
536 Counters

CLR CTR DIV 10 CLR CLR CTR DIV 6

HIGH CTEN
TC = 9 CTEN
C
C
To next
CLK counter
Decode 6

TC = 59
To ENABLE
Decode 59
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 of next CTR

units tens
FIGURE 9–49 Logic diagram of typical divide-by-60 counter using synchronous decade
counters. Note that the outputs are in binary order (the right-most bit is the LSB).

0 0 0 1
D3 D2 D1 D0

LOAD J
Q
CTR DIV 10
CLK
K

Q 3 Q2 Q 1 Q0

G1
Decode 9 G2
Decode
12
8 4 2 1 8 4 2 1

BCD/7-seg BCD/7-seg

g f e d c b a g f e d c b a

To units-of-hours To tens-of-hours
display display

FIGURE 9–50 Logic diagram for hours counter and decoders. Note that on the counter
inputs and outputs, the right-most bit is the LSB.

Next, the total count advances to eleven and then to twelve. In state 12 the Q2 output of
the decade counter is HIGH, the flip-flop is still SET, and thus the decode-12 gate output
is LOW. This activates the LOAD input of the decade counter. On the next clock pulse, the
decade counter is preset to 0001 from the data inputs, and the flip-flop is RESET (J = 0,
K = 1). As you can see, this logic always causes the counter to recycle from twelve back
to one rather than back to zero.

Automobile Parking Control

This counter example illustrates the use of an up/down counter to solve an everyday prob-
lem. The problem is to devise a means of monitoring available spaces in a one-hundred-
space parking garage and provide for an indication of a full condition by illuminating a
display sign and lowering a gate bar at the entrance.
 Counter Applications 537

A system that solves this problem consists of optoelectronic sensors at the entrance and
exit of the garage, an up/down counter and associated circuitry, and an interface circuit that
uses the counter output to turn the FULL sign on or off as required and lower or raise the
gate bar at the entrance. A general block diagram of this system is shown in Figure 9–51.

Full
Entrance indication
sensor
On/Off
UP
Terminal
CTR DIV 100 Interface
count Lower/Raise
DOWN

Exit
sensor Gate
activation

FIGURE 9–51 Functional block diagram for parking garage control.

A logic diagram of the up/down counter is shown in Figure 9–52. It consists of two cas-
caded up/down decade counters. The operation is described in the following paragraphs.

From
entrance S
sensor D/U CTR DIV 10 D/U CTR DIV 10
CTEN RCO CTEN MAX/MIN
From C C (to interface)
exit R HIGH activates
Q
sensor FULL sign and
lowers gate.

FIGURE 9–52 Logic diagram for modulus-100 up/down counter for automobile parking
control.

The counter is initially preset to 0 using the parallel data inputs, which are not shown.
Each automobile entering the garage breaks a light beam, activating a sensor that produces
an electrical pulse. This positive pulse sets the S-R latch on its leading edge. The LOW on the
Q output of the latch puts the counter in the UP mode. Also, the sensor pulse goes through
the NOR gate and clocks the counter on the LOW-to-HIGH transition of its trailing edge.
Each time an automobile enters the garage, the counter is advanced by one (incremented). Incrementing a counter increases its
When the one-hundredth automobile enters, the counter goes to its last state (10010). The count by one.
MAX/MIN output goes HIGH and activates the interface circuit (no detail), which lights the
FULL sign and lowers the gate bar to prevent further entry.
When an automobile exits, an optoelectronic sensor produces a positive pulse, which
resets the S-R latch and puts the counter in the DOWN mode. The trailing edge of the clock
decreases the count by one (decremented). If the garage is full and an automobile leaves, the Decrementing a counter decreases its
MAX/MIN output of the counter goes LOW, turning off the FULL sign and raising the gate. count by one.

Parallel-to-Serial Data Conversion (Multiplexing)

A simplified example of data transmission using multiplexing and demultiplexing tech-
niques was introduced in Chapter 6. Essentially, the parallel data bits on the multiplexer
inputs are converted to serial data bits on the single transmission line. A group of bits
appearing simultaneously on parallel lines is called parallel data. A group of bits appearing
on a single line in a time sequence is called serial data.
Parallel-to-serial conversion is normally accomplished by the use of a counter to provide
a binary sequence for the data-select inputs of a data selector/multiplexer, as illustrated in
Figure 9–53. The Q outputs of the modulus-8 counter are connected to the data-select
inputs of an 8-bit multiplexer.
538 Counters

CTR DIV 8 MUX

Q0
Q1 0
Data
Q2 Select
2
CLK C

D0 0 Serial
D1 1 data out
D2 2
Parallel D3 3
data in D4 4
D5 5
D6 6
D7 7

FIGURE 9–53 Parallel-to-serial data conversion logic.

Figure 9–54 is a timing diagram illustrating the operation of this circuit. The first byte
(eight-bit group) of parallel data is applied to the multiplexer inputs. As the counter goes
through a binary sequence from zero to seven, each bit, beginning with D0, is sequentially

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
CLK

Q0

Data Q1
select

Q2

D0 1 0

D1 0 0

D2 0 1
InfoNote
Computers contain an internal D3 1 0
Data
counter that can be programmed in
for various frequencies and tone D4 1 1
durations, thus producing “music.”
To select a particular tone, the
programmed instruction selects a D5 1 0
divisor that is sent to the counter.
The divisor sets the counter up to D6 0 1
divide the basic peripheral clock
frequency to produce an audio
tone. The duration of a tone can D7 1 0
also be set by a programmed
instruction; thus, a basic counter
Data 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0
is used to produce melodies by out
controlling the frequency and dura- 1st byte 2nd byte
tion of tones.
FIGURE 9–54 Example of parallel-to-serial conversion timing for the circuit in Figure 9–53.
 Logic Symbols with Dependency Notation 539

selected and passed through the multiplexer to the output line. After eight clock pulses the
data byte has been converted to a serial format and sent out on the transmission line. When
the counter recycles back to 0, the next byte is applied to the data inputs and is sequentially
converted to serial form as the counter cycles through its eight states. This process contin-
ues repeatedly as each parallel byte is converted to a serial byte.

SECTION 9–8 CHECKUP

1. Explain the purpose of each NAND gate in Figure 9–50.

2. Identify the two recycle conditions for the hours counter in Figure 9–48, and explain
the reason for each.

9–9 Logic Symbols with Dependency Notation

Up to this point, the logic symbols with dependency notation specified in ANSI/IEEE Stan-
dard 91-1984 have been introduced on a limited basis. In many cases, the symbols do not
deviate greatly from the traditional symbols. A significant departure does occur, however, for
some devices, including counters and other more complex devices. Although we will continue
to use primarily the more traditional symbols throughout this book, a brief coverage of logic
symbols with dependency notation is provided. A specific IC counter is used as an example.
After completing this section, you should be able to
u Interpret logic symbols that include dependency notation
u Identify the common block and the individual elements of a counter symbol
u Interpret the qualifying symbol
u Discuss control dependency
u Discuss mode dependency
u Discuss AND dependency

Dependency notation is fundamental to the ANSI/IEEE standard. Dependency notation

is used in conjunction with the logic symbols to specify the relationships of inputs and
outputs so that the logical operation of a given device can be determined entirely from its
logic symbol without a prior knowledge of the details of its internal structure and without a
detailed logic diagram for reference. This coverage of a specific logic symbol with depen-
dency notation is intended to aid in the interpretation of other such symbols that you may
encounter in the future.
The 74HC163 4-bit synchronous binary counter is used for illustration. For comparison,
Figure 9–55 shows a traditional block symbol and the ANSI/IEEE symbol with depen-
dency notation. Basic descriptions of the symbol and the dependency notation follow.

Common Control Block

The upper block with notched corners in Figure 9–55(b) has inputs and an output that are
considered common to all elements in the device and not unique to any one of the elements.

Individual Elements
The lower block in Figure 9–55(b), which is partitioned into four abutted sections, repre-
sents the four storage elements (D flip-flops) in the counter, with inputs D0, D1, D2, and D3
and outputs Q0, Q1, Q2, and Q3.

Qualifying Symbol
The label “CTR DIV 16” in Figure 9–55(b) identifies the device as a counter (CTR) with
sixteen states (DIV 16).
540 Counters

Common
CTR DIV 16 control
(1) block
CLR 5CT = 0
(9)
D0 D1 D2 D3 LOAD M1
(15)
M2 3CT = 15 RCO
(3) (4) (5) (6) (10)
ENT G3
(7)
(1) ENP G4
CLR (2)
(9) CLK C5/2,3,4+
LOAD
(10) (15)
ENT CTR DIV 16 RCO
(7) (3) (14)
ENP D0 1, 5 D [1] Q0
(2) (4) (13)
CLK C [2] Q1
D1
(5) (12)
(14) (13) (12) (11) D2 [4] Q2
(6) (11)
D3 [8] Q3
Q0 Q1 Q2 Q3
(a) Traditional block symbol (b) ANSI/IEEE Std. 91-1984 logic symbol

FIGURE 9–55 The 74HC163 4-bit synchronous counter.

Control Dependency (C)

As shown in Figure 9–55(b), the letter C denotes control dependency. Control inputs usu-
ally enable or disable the data inputs (D, J, K, S, and R) of a storage element. The C input
is usually the clock input. In this case the digit 5 following C (C5/2,3,4+) indicates that the
inputs labeled with a 5 prefix are dependent on the clock (synchronous with the clock). For
example, 5CT = 0 on the CLR input indicates that the clear function is dependent on the
clock; that is, it is a synchronous clear. When the CLR input is LOW (0), the counter is reset
to zero (CT = 0) on the triggering edge of the clock pulse. Also, the 5 D label at the input
of storage element [1] indicates that the data storage is dependent on (synchronous with)
the clock. All labels in the [1] storage element apply to the [2], [4], and [8] elements below
it since they are not labeled differently.

Mode Dependency (M)

As shown in Figure 9–55(b), the letter M denotes mode dependency. This label is used to
indicate how the functions of various inputs or outputs depend on the mode in which the
device is operating. In this case the device has two modes of operation. When the LOAD
input is LOW (0), as indicated by the triangle input, the counter is in a preset mode (M1) in
which the input data (D0, D1, D2, and D3) are synchronously loaded into the four flip-flops.
The digit 1 following M in M1 and the 1 in the label 1, 5 D show a dependency relationship
and indicate that input data are stored only when the device is in the preset mode (M1), in
which LOAD = 0. When the LOAD input is HIGH (1), the counter advances through its
normal binary sequence, as indicated by M2 and the 2 in C5/2,3,4+.

AND Dependency (G)

As shown in Figure 9–55(b), the letter G denotes AND dependency, indicating that an input
designated with G followed by a digit is ANDed with any other input or output having the
same digit as a prefix in its label. In this particular example, the G3 at the ENT input and
the 3CT = 15 at the RCO output are related, as indicated by the 3, and that relationship is
an AND dependency, indicated by the G. This tells us that ENT must be HIGH (no triangle
on the input) and the count must be fifteen (CT = 15) for the RCO output to be HIGH.
Also, the digits 2, 3, and 4 in the label C5/2,3,4+ indicate that the counter advances
through its states when LOAD = 1, as indicated by the mode dependency label M2, and
when ENT = 1 and ENP = 1, as indicated by the AND dependency labels G3 and G4.
The + indicates that the counter advances by one count when these conditions exist.
 Troubleshooting 541

SECTION 9–9 CHECKUP

1. In dependency notation, what do the letters C, M, and G stand for?

2. By what letter is data storage denoted?

9–10 Troubleshooting
The troubleshooting of counters can be simple or quite involved, depending on the type of
counter and the type of fault. This section will give you some insight into how to approach
the troubleshooting of sequential circuits.
After completing this section, you should be able to
u Detect a faulty counter
u Isolate faults in maximum-modulus cascaded counters
u Isolate faults in cascaded counters with truncated sequences
u Determine faults in counters implemented with individual flip-flops

Counters
The symptom for a faulty counter is usually that it does not advance its count. If this is the
case, then check power and ground on the chip. Look at these lines with a scope to make sure
there is no noise present (a noisy ground may actually be open). Check that there are clock
pulses and that they have the correct amplitude and rise time and that there is not extrane-
ous noise on the line. (Sometimes clock pulses can be loaded down by other ICs, making it
appear that the counter is faulty when it is not). If power, ground, and the clock pulses are
okay, check all inputs (including enable, load, and clear inputs), to see that they are connected
correctly and that the logic is correct. An open input can cause a counter to work correctly
some of the time—inputs should never be left open, even if they are not used. (An unused
input should be connected to an inactive level). If the counter is stuck in a state and the clock
is present, determine what input should be present to advance the counter. This may point to
a faulty input (including clear or load inputs), which can be caused by logic elsewhere in the
circuit. If inputs are all checked okay, an output may be pulled LOW or HIGH by an external
short or open (or another faulty IC), keeping the output from advancing.

Cascaded Counters with Maximum Modulus

A failure in one of the counters in a chain of cascaded counters can affect all the counters
that follow it. For example, if a count enable input opens, it effectively acts as a HIGH (for
TTL logic), and the counter is always enabled. This type of failure in one of the counters
will cause that counter to run at the full clock rate and will also cause all the succeeding
counters to run at higher than normal rates. This is illustrated in Figure 9–56 for a divide-
by-1000 cascaded counter arrangement where an open enable (CTEN) input acts as a TTL
HIGH and continuously enables the second counter. Other faults that can affect “down-
stream” counter stages are open or shorted clock inputs or terminal count outputs. In some
of these situations, pulse activity can be observed, but it may be at the wrong frequency.
Exact frequency or frequency ratio measurements must be made.

Cascaded Counters with Truncated Sequences

The count sequence of a cascaded counter with a truncated sequence, such as that in Figure
9–57, can be affected by other types of faults in addition to those mentioned for maximum-
modulus cascaded counters. For example, a failure in one of the parallel data inputs, the LOAD
input, or the inverter can alter the preset count and thus change the modulus of the counter.
542 Counters

100 kHz 10 kHz 1 kHz

HIGH CTEN TC CTEN TC CTEN TC

CTR DIV 10 CTR DIV 10 CTR DIV 10
C C C

1 MHz
(a) Normal operation

100 kHz 100 kHz 10 kHz

OPEN (acts as a HIGH)

HIGH CTEN TC CTEN TC CTEN TC

CTR DIV 10 CTR DIV 10 CTR DIV 10
C C C

1 MHz
(b) Count Enable (CTEN) input of second counter open

FIGURE 9–56 Example of a failure that affects following counters in a cascaded arrangement.

OPEN
LOAD
016 C16 316 616
0 0 0 0 1 1 0 0 0 0 1 1 0 1 1 0

HIGH
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
CTEN TC CTEN TC CTEN TC CTEN TC
CTR DIV 16 CTR DIV 16 CTR DIV 16 CTR DIV 16
C C C C

1 MHz
Least significant Most significant

138 Hz
FIGURE 9–57 Example of a failure in a cascaded counter with a truncated sequence.

For example, suppose the D3 input of the most significant counter in Figure 9–57 is
open and acts as a HIGH. Instead of 616 (0110) being preset into the counter, E16 (1110) is
preset in. So, instead of beginning with 63C016 (25,53610) each time the counter recycles,
the sequence will begin with E3C016 (58,30410). This changes the modulus of the counter
from 40,000 to 65,536 - 58,304 = 7232.
To check this counter, apply a known clock frequency, for example 1 MHz, and mea-
sure the output frequency at the final terminal count output. If the counter is operating
properly, the output frequency is
fin 1 MHz
fout = = = 25 Hz
modulus 40,000
In this case, the specific failure described in the preceding paragraph will cause the output
frequency to be
fin 1 MHz
fout = = _ 138 Hz
modulus 7232

EXAMPLE 9–9

Frequency measurements are made on the truncated counter in Figure 9–58 as indicated. Determine if the counter is work-
ing properly, and if not, isolate the fault.
 Troubleshooting 543

LOAD
016 C16 216 816

0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 0

D 3 D 2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
HIGH CTEN TC CTEN TC CTEN TC CTEN TC
CTR DIV 16 CTR DIV 16 CTR DIV 16 CTR DIV 16
C C C C

CTR1 CTR2 CTR3 CTR4

TC 4

MHz Hz
FIGURE 9–58

Solution
Check to see if the frequency measured at TC 4 is correct. If it is, the counter is working properly.
truncated modulus = full modulus - preset count
= 164 - 82C016
= 65,536 - 33,472 = 32,064
The correct frequency at TC 4 is
10 MHz
f4 = _ 312 Hz
32,064
There is a problem. The measured frequency of 637.8 Hz does not agree with the correct calculated frequency of 312 Hz.
To find the faulty counter, determine the actual truncated modulus as follows:
fin 10 MHz
modulus = = = 15,679
fout 637.8 Hz
Because the truncated modulus should be 32,064, most likely the counter is being preset to the wrong count when it recy-
cles. The actual preset count is determined as follows:
truncated modulus = full modulus - preset count
preset count = full modulus - truncated modulus
= 65,536 - 15,679
= 49,857
= C2C016
This shows that the counter is being preset to C2C016 instead of 82C016 each time it recycles.
Counters 1, 2, and 3 are being preset properly but counter 4 is not. Since C16 = 11002, the D2 input to counter 4 is HIGH
when it should be LOW. This is most likely caused by an open input. Check for an external open caused by a bad solder con-
nection, a broken conductor, or a bent pin on the IC. If none can be found, replace the IC and the counter should work properly.

Related Problem
Determine what the output frequency at TC 4 would be if the D3 input of counter 3 were open.

Counters Implemented with Individual Flip-Flops

Counters implemented with individual flip-flop and gate ICs are sometimes more difficult
to troubleshoot because there are many more inputs and outputs with external connections
than there are in an IC counter. The sequence of a counter can be altered by a single open
or short on an input or output, as Example 9–10 illustrates.
544 Counters

EXAMPLE 9–10

Suppose that you observe the output waveforms (green) that are indicated for the coun-
ter in Figure 9–59. Determine if there is a problem with the counter.

HIGH
FF0 FF1 FF2
Q0 Q2
J0 J1 J2
Q1
C C C

K0 K1 K2

CLK

CLK

Q0

Q1

Q2

FIGURE 9–59

Solution
The Q2 waveform is incorrect. The correct waveform is shown as a red dashed line.
You can see that the Q2 waveform looks exactly like the Q1 waveform, so whatever is
causing FF1 to toggle appears to also be controlling FF2.
Checking the J and K inputs to FF2, you find a waveform that looks like Q0. This result
indicates that Q0 is somehow getting through the AND gate. The only way this can happen is
if the Q1 input to the AND gate is always HIGH. However, you have seen that Q1 has a cor-
rect waveform. This observation leads to the conclusion that the lower input to the AND gate
must be internally open and acting as a HIGH. Replace the AND gate and retest the circuit.

Related Problem
Describe the Q2 output of the counter in Figure 9–59 if the Q1 output of FF1 is open.

To observe the time relationship between two digital signals with a dual-trace analog oscilloscope,
the proper way to trigger the scope is with the slower of the two signals. The reason for this is that the
slower signal has fewer possible trigger points than the faster signal and there will be no ambiguity
for starting the sweep. Vertical mode triggering uses a composite of both channels and should never
be used for determining absolute time information. Since clock signals are usually the fastest signal
in a digital system, they should not be used for triggering.

SECTION 9–10 CHECKUP

1. What failures can cause the counter in Figure 9–56 to have no pulse activity on any
of the TC outputs?
2. What happens if the inverter in Figure 9–58 develops an open output?