Memory Transistors

Nonvolatile Analog Memory Transistor Based on Carbon

Nanotubes and C60 Molecules
Byungjin Cho, Kyunghyun Kim, Chia-Ling Chen, Alex Ming Shen, Quyen Truong,
and Yong Chen*

A nonvolatile analog memory transistor is demonstrated by integrating C60 molecules

as charge storage molecules in the transistor gate, and carbon nanotubes (CNTs) in the
transistor channel. The currents through the CNT channel can be tuned quantitatively
and reversibly to analog values by controlling the number of electrons trapped in the
C60 molecules. After tuning, the electrons trapped in the C60 molecules in the gate,
and the current through the CNT channel, can be preserved in a nonvolatile manner,
indicating the characteristics of the nonvolatile analog memory.

1. Introduction molecule has strong electron affinity, and electrons injected

into the C60 molecule can be stored stably.[10,11,15] However,
Carbon nanotubes (CNTs) and C60 molecules have been it is still a challenge to integrate those devices in a large-scale
considered as promising building blocks for nanoscale tran- circuit for practical applications, as a result of the large vari-
sistors, owing to their unique physical, chemical, and mechan- ations of the device properties, induced by the intrinsic vari-
ical properties. Memory devices based on CNTs have been ations of the CNT structures, electronic properties, locations,
demonstrated by modifying CNT conductivity using electro- densities, and defects. The bottleneck problem can be solved
chemical reactions,[1,2] electromechanical force,[3] and charges by developing devices with analog configurability, and tuning
stored in a floating gate,[4,5] defects in a dielectric layer,[6] a the devices toward their desirable properties in a program-
ferroelectric layer,[7,8] and nanocrystals.[9] Owing to the nano- mable circuit.[16,17] The device with analog configurability and
scale diameter and large carrier mobility in CNT, the CNT- memory can also increase its memory capacity significantly.
based memory devices have achieved nanoscale size, high Although devices with analog configurability and memory
switching ratio, fast switching speed, low power consump- have been demonstrated previously in Si transistors,[18,19]
tion, and nonvolatile memory.[4–9] It is also well known that organic transistors,[20] and memristors,[21–23] the devices still
the electronic carrier concentration in CNT can be modified suffered from high power consumption during the device
sensitively by the surrounding electronic charge.[10,11] On configuration, stability of the analog memory states, and con-
the other hand, C60 molecule has been utilized for single figurable ranges of the device states.
electron transistors for memory owing to its small size and Here we report an analog memory transistor based on
the rehybridization of its molecular orbitals.[12–14] The C60 CNT and C60 molecules with analog configurability, low
power consumption, large configurable range, and nonvola-
tile memory. The transistor structure is shown schematically
Dr. B. Cho, K. Kim, Dr. C.-L. Chen, A. M. Shen,
Q. Truong, Prof. Y. Chen
in Figure 1a. The transistor channel is made from a random
Department of Mechanical CNT network composed of 98% semiconducting single-
and Aerospace Engineering wall CNTs (Figure 1b), which is connected by a source and
University of California drain electrodes with a 5 nm thick Ti layer and 45 nm thick
Los Angeles, California 90095, USA Au layer. The transistor gate is composed of a 30 nm thick
E-mail: [email protected] polyimide (PI) barrier layer, a 30 nm thick charge storage
Prof. Y. Chen layer with C60 derivative, 6,6-phenyl-C61 butyric acid
California NanoSystems Institute
methyl ester (PCBM) molecules embedded in a PI layer, a
University of California
Los Angeles,California 90095, USA
30 nm thick Al2O3 barrier layer, and a gate electrode with a
15 nm thick Ti layer and a 100 nm thick Al layer. Owing to its
DOI: 10.1002/smll.201202593 unique structure and rehybridization of its molecular orbitals,

small 2013, © 2013 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim wileyonlinelibrary.com 1
DOI: 10.1002/smll.201202593
 full papers B. Cho et al.

shown in Figure 2a. When Vg swept from

6 V to –6 V, Id was turned on, indicating
that the device was a p-type transistor
with holes as the major carriers. A sub-
threshold swing was ∼460 mV/dec, which
was derived from the Id–Vg curve in
Figure 2a. The leakage current through the
transistor gate was <20 pA. The memory
effect of the transistor was featured by a
counterclockwise hysteresis loop in the
Id–Vg curve: when Vg swept from 6 V to 0
V, the gate threshold Vth to turn on Id was
derived as ∼3.1 V; when Vg swept from -6
V to 0 V, Vth was shifted approximately to
–1.3 V. As measured at Vg = 0 V and Vd =
0.5 V from the hysteresis loop, the Id ratio
at its on/off states was ∼104. Statistically,
among 72 tested devices, the Id–Vg hyster-
esis loops and analog configurable memory
were observed in the 65 devices, and zero
Id was observed in the rest 7 devices, which
is probably due to the disconnected CNT
networks in the transistor channel.
Figure 1. a) A scheme showing the structure of a nonvolatile analog memory CNT transistor,
with a CNT network in the transistor channel, and C60 molecules in a PI barrier layer in the The transistor memory could be attrib-
gate. b) An atomic force microscope (AFM) image showing a CNT network in the transistor uted to the modification of charge elec-
channel. c) Energy diagrams of the transistor gate under different gate voltage biases (Vg = 0 trons stored in the C60 molecules in the
V, Vg > 1 V, and Vg < –3 V). C60:PI layer, and their attraction to the
holes in the CNT channel: When a positive
the C60 molecule has strong electron affinity (Figure 1c). Vg is applied, the electrons are injected into the C60 mole-
The electrons are injected into the C60 molecules in the PI cules through the PI polymer layer, resulting in the increase
polymer barrier layer in the transistor gate, which, in turn, of hole concentration in the CNT channel and Id. When a
modify the carrier concentration and current through the negative Vg is applied, the electrons are depleted from the
CNT channel of the transistor. The current can be tuned to C60 molecules, resulting in the decrease of hole concentra-
analog values quantitatively and reversibly by controlling tion in the CNT channel and Id.The modification of the gate
the number of electrons injected into the C60 molecules. The threshold Vth was observed as a function of the Vg sweeping
electrons can be trapped stably and preserved inside the C60 range. The Vth values were derived from the linear extrapo-
molecules, even after the gate voltages are removed, resulting lation of Id–Vg curves (Figure S1, Supporting Information).
in nonvolatile memory. The device could potentially be used As shown in Figure 2b, when Vg swept from –1 V → 1 V,
for nonvolatile analog memory, programmable analog logic, Vth = –0.1 V. When Vg swept from 1 V → –1 V, Vth = -0.1 V,
defect-tolerant, and neuromorphic circuits. no obvious change of Vth was observed, which indicates that
the electrons in the C60 molecules could hardly be modified

2. Results and Discussion

Figure 1b shows an atomic force micro-
scope (AFM) image of the CNT network
in the transistor channel. It was measured
from the AFM images that the CNT net-
work is composed of single-wall CNTs
with an average diameter of 1.5 nm and
an average length of 0.5 µm, and bun-
dles of CNTs with an average height of
4 nm and an average length of 2 µm. The
average density of the single-wall CNTs is
∼13 µm−2, and the average density of the
CNT bundles is 1 µm−2. Figure 2. a) A hysteresis curve of a source–drain current Id versus a gate voltage Vg when Vg
A typical source–drain current sweeps from –6 V → 6 V → -6 V. The arrows indicate the Vg sweep directions. b) The gate
(Id) versus a gate voltage (Vg), meas- threshold Vth, measured when Vg sweeps from –Vgm → Vgm (square) and from Vgm → –Vgm
ured from the transistor at Vd = 0.5 V, is (circle), is shown as a function of Vg sweeping amplitude, Vgm.

2 www.small-journal.com © 2013 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim small 2013,
DOI: 10.1002/smll.201202593
Nonvolatile Analogue Memory Transistor

Vg = 6 V and a duration of 1 ms, and then a

series of negative Vg pulses with an ampli-
tude Vg = –2 V and a duration of 1 ms was
applied at the frequency of 0.5 kHz, and Id
was measured under the same condition as
described above. As shown in Figure 3b, Id
was approximately and linearly decreased
versus the number of the negative Vg
pulses. The results indicate that the charge
inside the C60 molecules can be modified
quantitatively and controlled by applying
Vg pulses, and the transistor can be tuned
Figure 3. a) The change of the source–drain current, ΔId, is plotted as a function of the gradually by the Vg pulses with an ampli-
number of positive gate voltage pulses with fixed amplitudes Vg = 2 V (square), 4 V (circle), 6 V
tude of 2 V that is compatible with Si
(triangle), and 8 V (reversed triangle). b) ΔId is plotted as a function of the number of negative
gate voltage pulses with fixed amplitudes Vg = -2 V (square), -4 V (circle), -6 V (triangle), and CMOS circuits.
-8 V (reversed triangle). The configuration rate of the tran-
sistor can be modified by the amplitude
of the Vg pulses. To study this effect, Id
by Vg with |Vg| ≤ 1 V. When Vg swept from 2 V → –2 V, Vth was increased sequentially by a series of Vg pulses with fixed
was changed to 0.5 V, which indicates that the electrons were amplitudes of 2, 4, 6, and 8 V, respectively, by following the
injected into the C60 molecules by a positive Vg with Vg > same protocol described above. The change of Id is shown in
1 V. Vth increased gradually from -0.1 V to 3.7 V when the Figure 3a as a function of the pulse number, Np. The configu-
Vg sweeping range, Vgm, increased from 1 V to 8 V. On the ration rate, dId/dNp, increased significantly when the ampli-
other hand, Vth had no obvious change when Vgm decreased tude of Vg pulses increased from 2 V to 8 V. ΔId was saturated
from –1 V to -3 V; Vth decreased from 0 V to –1.8 V when after applying limited numbers of the pulses with Vg > 4 V. By
Vgm decreased from –3 V to –8 V. The change of the gate following the same protocol, Id was decreased sequentially by
threshold voltage can be understood by analyzing the elec- a series of Vg pulses with fixed amplitudes of –2, –4, –6, and
tronic energy structure of the transistor gate under different –8 V, respectively. The change of the Id is shown in Figure 3b
gate voltages (Figure 1c). When Vg increases (Vg > 1 V), the as a function of the pulse number, Np. The configuration rate,
lowest unoccupied molecular orbital (LUMO) energy level |dId/dNp|, increased significantly when the amplitude of Vg
of the C60 molecule is reduced below the CNT Fermi level, pulses decreased from -2 V to -8 V. |ΔId| was also saturated
and electrons are injected from the CNT into the C60 mol- after applying limited numbers of the pulses with Vg < –4 V.
ecules by hopping through the PI polymer,[24,25] resulting in The electrons could be transferred through the PI polymer
the increase of the hole concentration in the CNT and Vth. layer by hopping conduction mechanism,[24,25] which ena-
It has been reported that electrons can hop through the PI bles the amount of the charge in the C60 molecules and the
polymer via the localized electronic states associated with Id to be modified quantitatively to analogue values, by
phenyl and imide rings in the polymer chain.[25] When Vg applying the gate voltage with different amplitudes and polar-
< –3 V, the highest occupied molecular orbital (HOMO) ities. Based on the hopping model, the electron hopping rate
energy level of the C60 molecules increases above the CNT is exponentially proportional to the Vg amplitude, which may
Fermi level, and electrons are driven from the C60 molecules explain the Id configuration rate, |dId/dNp|, which increased
toward the CNT, resulting in the positive charge in the C60 significantly with increasing |Vg|. Under small Vg amplitudes
molecules and the negative shift of the Vth. The change of the (i.e. |Vg| = 2 V), the electron hopping rate and |dId/dNp| are
gate threshold voltage, ΔVth, is approximately proportional to almost constant, which enables the charge density inside the
the density of the charge in the C60 molecules, and the abso- C60 molecules and Id to be modified quantitatively and con-
lute value of the charge density increases with increasing Vgm, trolled by the pulse number.
as observed experimentally and shown in Figure 2b. After Id was configured to different analog values, the
The transistor can be configured to analogue states quan- nonvolatility of the CNT transistor was examined by moni-
titatively and reversibly, by applying a series of Vg pulses with toring the Id versus time for a week at Vd = 0.5 V, Vg = 0 V,
different amplitude and polarity. For example, Id was first and room temperature. As shown in Figure 4, Id was config-
configured to its minimum value by applying five pulses with ured to different analog values ranging from 10−12 – 10−7 A,
an amplitude Vg = –6 V and a duration of 1 ms, and then a and the different Id values could be distinguished and pre-
series of positive Vg pulses with a fixed amplitude Vg = 2 V served during the test period. Based on the extrapolations of
and a duration of 1 ms was applied to the transistor gate at the experimental data (Figure 4), the analog Id values could
the frequency of 0.5 kHz. After every five pulses, the tran- be distinguished and preserved for more than ten years,
sistor was stabilized at Vg = 0 V for 1 s, and then Id was meas- indicating the long-term nonvolatile analog memory of the
ured at Vg = 0 V and Vd = -0.5 V. As shown in Figure 3a, Id CNT transistor. The long retention time could be attributed
was approximately and linearly increased versus the number to the large electron affinity of the C60 molecules and the
of the positive Vg pulses. In contrast, Id was first configured to polarons formed at the interface between the C60 molecules
its maximum value by applying five pulses with an amplitude and polymer,[26,27] which trap and preserve the charge inside

small 2013, © 2013 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim www.small-journal.com 3
DOI: 10.1002/smll.201202593
 full papers B. Cho et al.

decreasing the hole concentration in the CNT and Id. The

electrons are transferred by hopping through the polymer
layer, which enables the amount of the charge in the C60 mol-
ecules and Id to be modified quantitatively and reversely, and
controlled to analog values by the number of the gate voltage
pulses. The charges can be trapped and preserved in the C60
molecules owing to a strong electron affinity of the C60 mol-
ecule, resulting in the long-term nonvolatile memory of the
transistor. The nonvolatile analog transistor could, potentially,
be applied to nonvolatile analog memory, programmable
analog logic, defect-tolerant and neuromorphic circuits.

4. Experimental Section
Fabrication of CNT Transistor: A randomly aligned CNT network
Figure 4. A source–drain current Id is plotted as a function of time after
composed of 98% semiconducting single-wall CNTs (IsoNanotubes-
Id was configured to different analog values. The experimental data
S) was spin-coated onto a SiO2 surface on a Si substrate. Source
(dots) are fitted and extrapolated (solid lines).
and drain electrodes with a 5 nm thick Ti layer and 45 nm thick Au
layer were deposited onto the CNT network by e-beam evaporation,
and patterned by photolithography. The CNT channel with a length
the molecules for a long time. It is also noted that Id at a large
of 30 µm and a width of 8 µm was then defined by photolithog-
value (e.g., ∼6.8 × 10−8 A) decreased slowly versus time, and
raphy. The PI barrier layer was spin-coated onto the CNT channel.
Id at a small value (e.g., ∼4.8 × 10−9 A) increased slowly versus
A C60 derivative, 6,6-phenyl-C61 butyric acid methyl ester (PCBM)
time, which could be caused by the leakage of the electrons
and PI were dissolved in a 1-vinyl-2-pyrrolidinone solvent with a
and holes in the C60 molecules, through the PI polymer layer.
PCBM:PI weight ratio of 1:22, and the C60/PI charge-storage layer
The leakage could potentially be reduced further by replacing
was deposited onto the PI barrier layer by spin-coating the C60:PI
the PI polymer in the gate with a material with lower leakage
solution. The Al2O3 barrier layer was deposited onto the C60:PI
current.
charge-storage layer by e-beam evaporation. Finally, the top gate
To understand the memory mechanism of the device, two
electrode with a 15 nm thick Ti layer and a 100 nm thick Al layer
different control devices were fabricated and tested. In the
was deposited onto the top of the Al2O3 barrier layer by e-beam
first control device, the C60:PI layer in the transistor was
evaporation, and patterned by photolithography.
replaced by a SU8 epoxy layer. No obvious hysteresis loop
Characterization: The structures of the CNT network were char-
was observed in the Id–Vg curve (Figure S2, Supporting Infor-
acterized by an AFM (Digital Instruments Veeco Metrology Group).
mation), indicating that the control device has no memory
The electric properties of the transistors were characterized in an
effect without the C60:PI layer. In the second control device,
ambient environment using a HP4156B and a Keithley 4200 SCS
the C60 molecule was removed from the PI layer in the tran-
semiconductor parameter analyzers. The potential pulse tests were
sistor. A counterclockwise hysteresis loop was still observed
carried out by a customized electrical circuit.
in the Id–Vg curve, but the Id ratio at its on/off states meas-
ured at Vg = 0 V and Vd = 0.5 V from the hysteresis loop was
∼3 (Figure S3, Supporting Information), and contrarily the
Id on/off ratio measured under the same condition from the
devices with C60 molecules is ∼104. The hysteresis loop in Supporting Information
the control device might be induced by the electronic charge
stored in the PI layer, but the amount of the charge stored in Supporting Information is available from the Wiley Online Library
the PI layer might be decreased significantly without the C60 or from the author.
molecules.

Acknowledgements
3. Conclusion
The authors acknowledge the supports of this work by the Air
We demonstrated an analog memory transistor based on
Force Office of Scientific Research (AFOSR) under the program ‘Bio-
CNT and C60 molecules. In the transistor, the source-drain
inspired intelligent sensing materials for Fly-by-Feel autonomous
current through the CNT channel, Id, was modified with a
large Id on/off ratio up to ∼104 by the charge in the C60 mol- vehicle’ (contract number: FA9550-09-1-0677).
ecules in the polymer layer in the gate. When a positive gate
voltage is applied to the gate, electrons are injected from the
[1] Y. S. Ahn, K. Kim, H. K. Park, H. T. Hahn, Y. Chen, Adv. Mater.
CNTs to the C60 molecules, increasing the hole concentration 2011, 23, 3075–3079.
in the CNT and Id. When a negative gate voltage is applied [2] S. Rosenblatt, Y. Yaish, J. Park, J. Gore, V. Sazonova, P. L. McEuen,
to the gate, electrons are depleted from the C60 molecules, Nano Lett. 2002, 2, 869–872.

4 www.small-journal.com © 2013 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim small 2013,
DOI: 10.1002/smll.201202593
Nonvolatile Analogue Memory Transistor

[3] A. B. Kaul, E. W. Wong, L. Epp, B. D. Hunt, Nano Lett. 2006, 6, [17] G. Agnus, W. Zhao, V. Derycke, A. Filoramo, Y. Lhuillier, S. Lenfant,
942–947. D. Vuillaume, C. Gamrat, J.-P. Bourgoin, Adv. Mater. 2010, 22,
[4] W. J. Yu, S. H. Chae, S. Y. Lee, D. L. Duong, Y. H. Lee, Adv. Mater. 702–706.
2011, 23, 1889–1893. [18] Q. Lai, L. Zhang, Z. Li, W. F. Stickle, R. S. Williams, Y. Chen, Adv.
[5] W. J. Yu, B. R. Kang, I. H. Lee, Y.-S. Min, Y. H. Lee, Adv. Mater. Mater. 2010, 22, 2448–2453.
2009, 21, 4821–4824. [19] Q. Lai, Z. Li, L. Zhang, X. Li, W. F. Stickle, Z. Zhu, Z. Gu, T. I. Kamins,
[6] M. Rinkiö, A. Johansson, G. S. Paraoanu, P. Törmä, Nano Lett. R. S. Williams, Y. Chen, Nano Lett. 2008, 8, 876–880.
2009, 9, 643–647. [20] F. Alibart, S. Pleutin, D. Guérin, C. Novembre, S. Lenfant,
[7] W. Fu, Z. Xu, X. Bai, C. Gu, E. Wang, Nano Lett. 2009, 9, 921–925. K. Lmimouni, C. Gamrat, D. Vuillaume, Adv. Funct. Mater. 2010,
[8] W. Y. Fu, Z. Xu, L. Liu, X. D. Bai, E. G. Wang, Nanotechnology 2009, 20, 330–337.
20, 475305. [21] V. Erokhin, T. Berzina, P. Camorani, A. Smerieri, D. Vavoulis,
[9] M. Olmedo, C. Wang, K. Ryu, H. Zhou, J. Ren, N. Zhan, C. Zhou, J. Feng, M. P. Fontana, BioNanoSci. 2011, 1, 24–30.
J. Liu, ACS Nano 2011, 5, 7972–7977. [22] S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, W. Lu,
[10] T. B. Singh, N. Marjanovic´, G. J. Matt, N. S. Sariciftci, R. Schwödiauer, Nano Lett. 2010, 10, 1297–1301.
S. Bauer, Appl. Phys. Lett. 2004, 85, 5409–5411. [23] Y. Shimeng, W. Yi, R. Jeyasingh, D. Kuzum, H. P. Wong, IEEE Trans.
[11] B. Park, S. Choi, S. Graham, E. Reichmanis, J. Phys. Chem. C 2012, Electron Devices 2011, 58, 2729–2737.
116, 9390–9397. [24] A. A. Alagiriswamy, K. S. Narayan, R. Govinda, J. Phys. D: Appl.
[12] L. H. Yu, D. Natelson, Nano Lett. 2003, 4, 79–83. Phys. 2002, 35, 2850.
[13] H. Park, J. Park, A. K. L. Lim, E. H. Anderson, A. P. Alivisatos, [25] R. M. S. Gaur, R. K. Tiwari, J. Plast. Film Sheeting 2009, 25,
P. L. McEuen, Nature 2000, 407, 57–60. 271–283.
[14] E. D. Mentovich, B. Belgorodsky, I. Kalifa, S. Richter, Adv. Mater. [26] D. Dick, X. Wei, S. Jeglinski, R. E. Benner, Z. V. Vardeny, D. Moses,
2010, 22, 2182–2186. V. I. Srdanov, F. Wudl, Phys. Rev. Lett. 1994, 73, 2760–2763.
[15] R. C. Haddon, R. E. Palmer, H. W. Kroto, P. A. Sermon, Phil. Trans. [27] W. Osikowicz, M. P. de Jong, W. R. Salaneck, Adv. Mater. 2007,
R. Soc. Lond. A 1993, 343, 53–62. 19, 4213–4217.
[16] J. Borghetti, V. Derycke, S. Lenfant, P. Chenevier, A. Filoramo, Received: October 20, 2012
M. Goffman, D. Vuillaume, J.-P. Bourgoin, Adv. Mater. 2006, 18, Revised: November 28, 2012
2535–2540. Published online:

small 2013, © 2013 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim www.small-journal.com 5
DOI: 10.1002/smll.201202593