Scribd
Upload
20 views

2020 Ques Mid Advd

Uploaded by

SABUJ CHAKI
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
20 views

2020 Ques Mid Advd

Uploaded by

SABUJ CHAKI
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

Mid Semester Advanced VLSI Design 11:00 - 12:30 Tue 03 Mar 2020

Write your name and ID# legibly on the top margin of this question paper and attach this as the front cover of your answer
booklet before submission. All symbols have their usual significance. This is a closed book evaluation, however, you may
refer to only one A4 sheet of hand-written formulas during the examination. ox = 3.90 , q = 1.6 × 10−19 C, kB T /q = 26
mV, ni = 1.45 × 1010 /cm3 , si = 11.70 , 0 = 8.85 × 10−14 F/cm.

1. Design the (W/L)p and (W/L)n for a static CMOS inverter such that tP LH = tP HL = 100 ps while the circuit drives
a load capacitance of 50 fF. VDD = 1.8 V, µn Cox = 100 µA/V2 , µp Cox = 50 µA/V2 , VT n = 0.4 V, VT p = −0.5 V,
λn = λp = 0.
(W/L)n = [5]
(W/L)p = [5]
2. Assuming rail-to-rail operation, calculate the noise margins for a CMOS inverter. (W/L)n = 5/0.18, (W/L)p =
11/0.18, VDD = 1.8 V, µn Cox = 100 µA/V2 , µp Cox = 50 µA/V2 , VT n = 0.4 V, VT p = −0.5 V, λn = λp = 0.
N ML = [5]
N MH = [5]

3. (a) Compute the optimal inverter fanout ratio f for a 3-stage inverter chain with CL = 200 fF and Cin = 1 fF.
f= [3]
(b) Recompute the value of f if the optimal no. of stages is used.
f= [3]
(c) Compute the delay through the chain of inverter in both the above cases assuming τinv = 7.5 ps and parasitic
delay of 0.5τinv .
Absolute delay in (a)= Absolute delay in (b)= [2+2]

4. A transistor was fabricated on an n-type substrate with a bulk doping density of ND = 1016 /cm3 , n+ polysilicon
gate doping density of ND = 1020 /cm3 , Qox = 4 × 1010 q /cm2 and gate oxide thickness tox = 0.1 µm. Calculate
the nominal threshold voltage at room temperature.
VT 0 = [5]
5. As an IC designer you are required to use a typical nMOSFET with n+ polysilicon gate for designing some digital
circuitry for missiles. What is the maximum tolerable temperature (in√°C) beyond which your circuit will fail?
VT 0 = 0.5 V, dEg /dT ≈ −0.27 meV/K, Nsub ∼ 1018 /cm3 , m ≈ 1.3, and Nc Nv ≈ 3 × 1019 /cm3 .
T = [5]

40 Marks MEL G623 Page 1 of 1

You might also like