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UMBB, IGEE, EE323 Microprocessor Systems Design (L05), March 29, 2021
Final Exam (2020-2021) Duration: 1h30

Questions:

- What is the function of M1- signal?

0,5 1- This signal differentiates the Opcode fetch cycle from other operations
0,5 2- It is used to generate the interrupt Acknowledge signal.

- What is the difference between LD HL and LD (HL)

0,5
LD HL: Load 16 bit into register pair HL.
0,5 LD (HL): Load 8 bit to the address specified by 16 bit contents of HL.

- Is the number of T-states required for a given machine cycle constant? Explain.

No, the number of T-states is not constant. Memory read/write and I/O read/write machine cycles,
1,0
generally, take three of four T-states, however there are some exceptions.

Exercise N° 1:
The following program is a continuous Hex counter with an appropriate delay between two
counts.
2000H LD SP, 20FAH
2003H LD HL, 2065H
2006H LD BC, 0010H
2009H LD A, 00H
200BH OUT (port1), A
200DH CALL 2065H
2010H INC A
2011H JP 200BH
|
2065H PUSH HL
2066H PUSH BC
2067H LD HL, 10FFH
206AH DEC HL
|
2070H POP BC
2071H RET
1- List the used stack locations and their contents after the execution of the instruction
PUSH BC.
10 20F4
PUSH BC
00 20F5

65 20F6
PUSH HL 1,5
20 20F7

10 20F8
CALL
20 20F9
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2- Where does the program return after the execution of the RET instruction and what is
the content of the stack pointer.

0,5 PC=2065 , 0,5 SP=20F8

3- What is being displayed at port1? Explain your answer.

0,5 00H

Exercise N° 2:

Identify the machine cycles in the following instructions.

LD A, (2100H): (3 bytes) Opcode fetch, memory read, memory read, memory read 0,5

ADD C: (1byte) Opcode fetch 0,5

POP BC: (1byte) Opcode fetch, memory read, memory read 0,5

SUB 55H: (2bytes) Opcode fetch, memory read 0,5

DEC (HL): (1byte) Opcode fetch, memory read, memory write 0,5

ADD A, (HL): (1byte) Opcode fetch, memory read 0,5

Exercise N°3:

-1- Data cannot be loaded directly into the flag register, program counter PC and alternate registers;
the immediate addressing mode is not available for these registers.

Write an assembly program to load an 8-bit value into the flag register.
(example : 0 to sign flag , 0 to Z flag, 1 to Half carry, 0 to P/V flag , 0 to N flag and 1 to C flag)

LD SP 3FB0 ;
S Z D5 H D3 P/V N C
LD BC 0039 ; or LD BC 0011
1,5 0 0 X 1 X 0 0 1
LD BC 0019
LD BC 0031.
PUSH BC
POP AF
HALT

-2- Specify the registers contents and the flag status after the execution of the following instructions.

Program Registers Contents Flag

A B C S Z CY
SUB B FF 80 89 1 0 1
LD B, A FF FF 89 1 0 1 0,5
ADD A, A9H A8 FF 89 1 0 1 0,5
LD C, 57H A8 FF 57 1 0 1 0,5
ADD A, C FF FF 57 1 0 0 0,5

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DEC A FE FF 57 1 0 0 0,5
OUT (OUTPRT), A FE FF 57 1 0 0 0,5
HALT FE FF 57 1 0 0 0,5

Exercise 4:

Using the following components:

- 2 decoder 74LS138 (3 to 8 decoder ) with ̅̅̅ , ̅̅̅ and enables

- 1 ROM (8K* 8-bit) with onechip select ̅̅̅̅ and output enable ̅̅̅̅
- 1 R/W Memory (8K*8-bit) with one chip select ̅̅̅̅ , output enable ̅̅̅̅ and Write enable
̅̅̅̅̅
- 1 R/W Memory (1K*8-bit) with onechip select ̅̅̅̅ , output enable ̅̅̅̅ and Write enable ̅̅̅̅̅

design an interfacing circuit to meet the following specification:

Specification: ROM with starting address 0000H, R/W Memory of 8k*8-bit with starting address
2000H, and R/W Memory (1K*8bit) with starting address 6000H.

̅̅̅̅̅̅̅̅
MREQ Give the schematic of the interfacing circuit.
VCC

A15 E1 E2 E3 O3 (3)
A14 3-to-8 O1
Decoder O0 ̅̅̅̅
RD ̅̅̅̅
RD ̅̅̅̅̅
WD ̅̅̅̅ ̅̅̅̅̅
RD WD
A13
A12 ̅̅̅̅
CE ̅̅̅̅
OE A12 ̅̅̅̅ OE
CE ̅̅̅̅ ̅̅̅̅̅
WE A9 ̅̅̅
CE̅ ̅̅̅̅
OE ̅̅̅̅̅
WE
VCC ROM
8k x 8 1k x 8
A12 E1 E2 E3 8k x 8
A0 A0 A0
3-to-8
A11
Decoder O0
A10

Give the address range of the 3 memories.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0,5
1FFF 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
2000 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0,5 3FFF 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
6000 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0,5
63FF 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1

Give the memory map of the system. 0000

ROM
1FFF
2000
R/W(1)
3FFF 1,5
4000
unused
5FFF
6000
R/W(1)
63FF
3/3 6400 D.BELAIDI
unused
FFFF