WIDE-BANDWIDTH HIGH DYNAMIC RANGE D/A CONVERTERS

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WIDE-BANDWIDTH HIGH
DYNAMIC RANGE D/A
CONVERTERS

by

Konstantinos Doris
Philips Research Laboratories,
Eindhoven, The Netherlands

Arthur van Roermund

Eindhoven University of Technology,
Eindhoven, The Netherlands

and

Domine Leenaerts
Philips Research Laboratories,
Eindhoven, The Netherlands
A C.I.P. Catalogue record for this book is available from the Library of Congress.

ISBN-10 0-387-30415-0 (HB)

ISBN-13 978-0-387-30415-1 (HB)
ISBN-10 0-387-30416-9 (e-book)
ISBN-13 978-0-387-30416-8 (e-book)

Published by Springer,
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Printed in the Netherlands.

 Contents

Glossary ix

Abbreviations xiii

Preface xv

1 Digital to Analog conversion concepts 1

1.1 Functional aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Definition of the D/A function . . . . . . . . . . . . . . . . . . . 1
1.1.2 Functional specifications . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Algorithmic aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 Signal processing aspects . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.1 Waveforms and Line coding . . . . . . . . . . . . . . . . . . . . 11
1.3.2 Signal Modulation concepts . . . . . . . . . . . . . . . . . . . . 13
1.4 Circuit aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4.1 Architecture terminology . . . . . . . . . . . . . . . . . . . . . . 14
1.4.2 Resistive voltage division architectures . . . . . . . . . . . . . . 15
1.4.3 Capacitive voltage and charge division architectures . . . . . . . 16
1.4.4 Current division based architectures . . . . . . . . . . . . . . . . 18
1.5 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2 Framework for Analysis and Synthesis of DACs 19

2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 Framework description . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.1 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.2 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
vi Contents

3 Current Steering DACs 25

3.1 Basic circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1 Partitioning and segmentation . . . . . . . . . . . . . . . . . . . 26
3.1.2 Current switching network and current sources . . . . . . . . . . 29
3.1.3 Clock-data synchronization circuit . . . . . . . . . . . . . . . . . 29
3.1.4 Auxiliary circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 Implementations and technology impact . . . . . . . . . . . . . . . . . . 30

4 Dynamic limitations of Current Steering DACs 35

4.1 State of the art in dynamic linearity . . . . . . . . . . . . . . . . . . . . . 35
4.2 Dynamic limitations of current steering DACs . . . . . . . . . . . . . . . 40
4.2.1 Matching and relative amplitude precision . . . . . . . . . . . . . 41
4.2.2 Matching and relative timing precision . . . . . . . . . . . . . . 42
4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5 Current Steering DAC circuit error analysis 45

5.1 Amplitude domain errors . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.1.1 Relative amplitude inaccuracies . . . . . . . . . . . . . . . . . . 45
5.1.2 Output resistance modulation . . . . . . . . . . . . . . . . . . . 47
5.2 Time domain errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.2.1 Nonlinear settling and output impedance modulation . . . . . . . 48
5.2.2 Asymmetrical switching . . . . . . . . . . . . . . . . . . . . . . 51
5.2.3 Modulation of switching behavior . . . . . . . . . . . . . . . . . 53
5.2.4 Charge feedthrough and injection . . . . . . . . . . . . . . . . . 54
5.2.5 Relative timing inaccuracies . . . . . . . . . . . . . . . . . . . . 56
5.2.6 Power supply bounce and substrate noise . . . . . . . . . . . . . 59
5.2.7 Clock (timing) jitter . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6 High-level modeling of Current Steering DACs 67

6.1 System modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.1.1 System layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.1.2 System excitations and responses . . . . . . . . . . . . . . . . . 69
6.1.3 System parameters . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1.4 Subsystem interaction . . . . . . . . . . . . . . . . . . . . . . . 71
6.1.5 System modulation . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.2 Error properties and classification . . . . . . . . . . . . . . . . . . . . . 72
6.2.1 Error properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.2.2 Error classification . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3 Functional error generation mechanisms . . . . . . . . . . . . . . . . . . 79
6.3.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.2 Algorithmic modeling . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.3 Functional modeling . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.4 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Contents vii

6.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

7 Functional modeling of timing errors 89

7.1 Non-uniform timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7.1.1 The Equivalent Timing error of a transition . . . . . . . . . . . . 89
7.1.2 Non-uniform timing in the process of signal sampling . . . . . . 91
7.1.3 Non-uniform timing in the process of signal creation . . . . . . . 92
7.2 Stochastic non-uniform timing analysis . . . . . . . . . . . . . . . . . . 95
7.2.1 Correlated non-uniform timing . . . . . . . . . . . . . . . . . . . 95
7.2.2 White non-uniform timing . . . . . . . . . . . . . . . . . . . . . 97
7.2.3 RZ and NRZ waveforms . . . . . . . . . . . . . . . . . . . . . . 100
7.3 Deterministic non-uniform timing . . . . . . . . . . . . . . . . . . . . . 103
7.3.1 Non-linear mapping of time domains . . . . . . . . . . . . . . . 103
7.3.2 Non-uniform timing in signal creation . . . . . . . . . . . . . . . 105
7.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

8 Functional analysis of local timing errors 109

8.1 Local timing error analysis . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.1.1 Equivalent timing error calculation . . . . . . . . . . . . . . . . . 109
8.1.2 Signal error calculation . . . . . . . . . . . . . . . . . . . . . . . 113
8.2 High level architectural parameter tradeoffs: segmentation . . . . . . . . 116
8.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

9 Circuit analysis of local timing errors 119

9.1 Circuit analysis with linear models . . . . . . . . . . . . . . . . . . . . . 119
9.1.1 Circuit behavioral-level analysis of timing errors in a chain . . . . 120
9.1.2 Transistor level analysis . . . . . . . . . . . . . . . . . . . . . . 126
9.2 Local timing error tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.2.1 Switch timing errors . . . . . . . . . . . . . . . . . . . . . . . . 135
9.2.2 Latch timing errors . . . . . . . . . . . . . . . . . . . . . . . . . 137
9.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

10 Synthesis concepts for CS DACs 139

10.1 Information management in the CS DAC . . . . . . . . . . . . . . . . . . 139
10.1.1 The basic current steering DAC hardware . . . . . . . . . . . . . 141
10.1.2 Information sources . . . . . . . . . . . . . . . . . . . . . . . . 141
10.1.3 Optional hardware: detection and control operations . . . . . . . 142
10.1.4 Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
10.1.5 Space/Time error mapping and processing . . . . . . . . . . . . . 145
10.2 Synthesis Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
10.3 A-posteriori error correction methods . . . . . . . . . . . . . . . . . . . 148
10.3.1 Calibration in amplitude and time domain . . . . . . . . . . . . . 148
10.3.2 Generalized mapping . . . . . . . . . . . . . . . . . . . . . . . . 151
10.3.3 Applications of generalized mapping . . . . . . . . . . . . . . . 155
viii Contents

10.3.4 Realization issues of the generalized mapping concept . . . . . . 156

10.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

11 Design of a 12 bit 500 Msample/s DAC 159

11.1 Design approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.2.1 Signaling and circuit logic . . . . . . . . . . . . . . . . . . . . . 160
11.2.2 Power supply and biasing . . . . . . . . . . . . . . . . . . . . . 161
11.2.3 Thermometer/binary bits partitioning . . . . . . . . . . . . . . . 162
11.3 Switched-Current cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
11.3.1 Current source . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
11.3.2 Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
11.4 Decoder, data synchronization and conditioning . . . . . . . . . . . . . . 174
11.4.1 Binary-to-Thermometer decoder . . . . . . . . . . . . . . . . . . 174
11.4.2 Delay equalization . . . . . . . . . . . . . . . . . . . . . . . . . 175
11.4.3 Master-slave latches and drivers . . . . . . . . . . . . . . . . . . 175
11.4.4 Clock buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.5 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
11.6 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
11.6.1 DC linearity measurements . . . . . . . . . . . . . . . . . . . . . 180
11.6.2 AC linearity measurements . . . . . . . . . . . . . . . . . . . . . 181
11.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

References 185

A Output spectrum for timing errors 199

A.1 Power spectrum of y(t) for random timing errors . . . . . . . . . . . . . 199
A.2 Spectrum of y(t) for deterministic timing errors . . . . . . . . . . . . . . 202

B Literature data 203

 Glossary

Symbol Description Unit

Aβ current factor mismatch process parameter

AD gain of a driver
AVth threshold mismatch process parameter mV µ m
B1 lower frequency limit of a bandpass signal Hz
B2 higher frequency limit of a bandpass signal Hz
cn−m (tn ,tm ) joint probability density function of timing errors
Ck−l ( fk , fl ) characteristic function for timing errors µm
Cq ( f , − f ) characteristic function for correlated stationary timing errors
|C( f )|2 characteristics function for uncorrelated stationary timing errors
Cu capacitance difference between switched on and off phases of a F
switched current source
Con output capacitance of a switched-on current source F
Co f f output capacitance of a switched-off current source F
CC total clock node capacitance F
CCD output capacitance of the clock driver F
CD self output load capacitance of the driver F
Cgd MOS gate drain capacitance F
CG gate capacitance of the current switches F
Cint interconnect capacitance between driver and current switches F
CInt clock interconnect network capacitance F
Cov MOS overlap capacitance per unit width F m−1
Cox oxide capacitance per unit area F m−2
δ (t) delta pulse
∆Ik unit error of the k-th current source A
∆t timing error created by a circuit (accompanied by a subscript) sec
di (m) thermometer bit i as a function of discrete time index m
D(m) DAC binary input word at time index m
x Glossary

E{} expectation with respect to the probability density function

(PDF) of the function under consideration
f frequency Hz
f1 lower band frequency limit Hz
f2 higher band frequency limit Hz
fN Nyquist frequency Hz
h(t) arbitrary interpolation pulse
|H( f )|2 energy spectral density of an arbitrary pulse h(t) Hz−2
I reference (LSB) current of the DAC A
Inorm (w) normalized current amplitude as a function of w A
Iu current generated by a switched current cell A
IFS full scale current of the DAC A
J p (x) Bessel function of the first kind
K number of bands
λ frequency normalized over fs
L MOS transistor length m
m discrete time index
µi local timing error of each circuit element i sec
µm timing errors as a function of the time index m sec
N number of bits
NB bits remaining in binary code
NT bits decoded in thermometer code
pr (t) rectangular pulse
p(t) sinc interpolation pulse
P total signal power including signal and noise W
PB power of a signal in a band W
Pk power of the k-th harmonic of a signal W
Pmax power of the largest spurious component in the band of interest W
PN noise power W
|Pr ( f )|2 energy spectral density of a rectangular pulse pr (t) Hz−2
PS signal power W
rµ (m, q) correlation function of the timing error series {µm } sec2
Ry (t,t + τ ) probabilistic autocorrelation of the CT process y(t) V 2 or A2
R̂y (τ ) empirical autocorrelation of the CT process y(t) V 2 or A2
Rz (m, m + q) probabilistic autocorrelation of the DT process z(m) V 2 or A2
R̂z (m, m + q) empirical autocorrelation of the DT process z(m) V 2 or A2

Ry (τ ) averaged probabilistic autocorrelation V 2 or A2
E{R̂y (τ )} mean of the empirical autocorrelation V 2 or A2
Sy ( f ) probabilistic power spectrum of the CT process y(t) W Hz−1
Ŝy ( f ) empirical power spectrum of the CT process y(t) W Hz−1

Sy ( f ) averaged probabilistic power spectrum of the CT process y(t) W Hz−1
E{Ŝy ( f )} mean of the empirical power spectrum of the CT process y(t) W Hz−1
Rz (0) power of z(m) W
RL output DAC resistive load Ω
σ spread of timing errors sec
s(t) output signal of the DAC V or A
Glossary xi

S0 amplitude of the power spectral density W

SzDT (λ ) power spectral density of z(m) W normalized Hz
Sz ( f ) power spectral density of z(t) W sec
Sz (t) first derivative of z(t)(instantaneous slope) V sec−1
τ time constant (accompanied with subscripts) sec
τ (w) DAC output node time constant as a function of w sec
τu DAC output node time constant increment per each step of w sec
t time variable sec
tox oxide thickness m
T0 width of a return to zero pulse sec
TE (w1 , w2 ) equivalent timing error for the transistion w1 → w2 sec
tm non-uniform timing moments sec
Tr(m − 1, m) normalized transition from sample to sample V or A
Ts Sampling period sec
û(t, w) normalized pulse for local timing errors µi
u(t) unit step
|U( f )|2 energy spectral density of a step pulse u(t) Hz−2
v̂(t, w) general description of the normalized pulse V or A
Vdd positive power supply V
VD voltage swing of a driver V
VL voltage swing of a latch V
Vre f reference voltage V
Vss negative power supply V
Vswi voltage swing
Vth Threshold voltage V
w(m) integer value of D(m)
W MOS transistor width m
|Y ( f )| magnitude spectrum of y(t) V or A
z(m) generic discrete time signal V or A
Zu ( f ) output impedance of a switched current cell vs. frequency Ω
 Abbreviations

AC Alternating Current
ADC Analog-to-Digital Converter
AM Amplitude Modulation
BER Bit Error Rate
BJT Bipolar Junction Transinstor
CAD Computer Aided Design
CML Current Mode Logic
CMOS Complementary Metal Oxide Semiconductor
CS Current Steering
CT Continous Time
DAC Digital-to-Analog Converter
DC Direct Current
DEM Dynamic Element Matching
DNL Differential Non Linearity
DT Discrete Time
DT/CT Discrete Time to Continous Time conversion
ECL Emitter Coupled Logic
ESD Energy Spectral Density
FM Frequency Modulation
HD2,HD3 Second and third order harmonic distortion
HW Hardware
INL Integral Non Linearity
LSB Least Significant Bit
MSB Most Singificant Bit
NRZ Non Return to Zero
PPM Pulse Position Modulation
PSD Power Spectral Density
PWL Piece-wise Linear
PWM Pulse Width Modulation
PDM Pulse Duration Modulation
RZ Return to Zero
xiv Abbre viations

SC Switched Capacitor
SI Switched Current
SDR Signal to Distortion Ratio
SFDR Spurious Free Dynamic Range
SNDR Signal to Noise and Distortio Ratio
SNR Signal to Noise Ratio
T/H Track and Hold
THD Total Harmonic Distortion
WSS Wide Sense Stationary
 Preface

H IGH-SPEED Digital to Analog (D/A) converters are essential components in digi-

tal communication systems providing the necessary conversion of signals encoding
information in bits to signals encoding information in their amplitude vs. time domain
characteristics. In general, they are parts of a larger system, the interface, which con-
sists of several signal conditioning circuits. Dependent on where the converter is located
within the chain of circuits in the interface, signal processing operations are partitioned in
those realized with digital techniques, and those with analog.
The rapid evolution of CMOS technology has established implicit and explicite trends
related to the interface, and in particular to the D/A converter. The implicit relationship
comes via the growth of digital systems. First, it is a global trend with respect to all
interface circuits that increasing operating frequencies of digital systems place a similar
demand for the interface circuits. The second trend takes place locally within the inter-
face. Initially, the D/A converter was placed at the beginning of the interface chain, and all
signal conditioning was implemented in the analog domain after the D/A conversion. The
increasing flexibility and robustness of digital signal processing shifted the D/A converter
closer to the end point of the chain where the demands for high quality high frequency
operation are very high. Third, there is a gradual change in the signal properties and spec-
ifications, which reflect to the rapid widening of application range, to user requirements,
and of course to environmental constraints relevant to the application. Explicit trends are
established by the direct impact of physical constrains of the technology on converters.
One of them concerns how information is distributed in the amplitude and time domains.
Modern CMOS technologies allow less and less room to use the amplitude domain due to
decreasing power supply levels but not decreasing noise and interference levels. Instead,
they offer plenty of room in the time domain.
Wideband high dynamic range D/A converters are carriers of these trends and enablers
of modern multi-carrier communication applications. These converters are required to
process multiple signals over large frequency ranges of hundreds of mega hertz with high
xvi Preface

linearity and low noise levels. To further simplify the subsequent lowpass filtering and to
allow efficient implementation of pre-distortion techniques for high data rate communi-
cations sampling rates multiple times higher than the actual transmitted signal bandwidth
are required. However, the demands placed by these trends can not be straightforwardly
mapped to physical realization despite the potential offerings of modern technologies. As
a result the D/A converter becomes one of the bottlenecks in system performance.
The Current Steering Digital to Analog Converter (CS DAC) offers the possibility for
such wideband high dynamic range signal conversion. However, its potential to achieve
high speed is limited by the fact that it exhibits strong nonlinear behavior at high fre-
quencies, which is unwanted. This nonlinear behavior, especially at high frequencies, is
dominated by mechanisms that can not be described as amplitude domain transfer func-
tions between input and output signals, like for example the case of the nonlinear behavior
of an operational amplifier. This nonlinear behavior is neither easy to understood, nor to
cope with. It stems mainly from the way circuit imperfections affect the inherently nonlin-
ear transient behavior of the signals the D/A converter generates. The appearance of such
behavior reveals that there is limited knowledge about the CS DAC nonlinear behavior at
high frequencies. As a result, there is a corresponding difficulty to bring a relationship
between signals, user information, application aspects, internal aspects of the converter,
environmental aspects, etc. in a generic form that would allow maximum exploitation of
what modern technologies offer. The lack of knowledge brings up an ambiguity element
in the CS DAC design phase that impedes performance progress.
This book provides a structured and comprehensive description of the nonlinear be-
havior of the CS DAC and of ways to deal with it. In order to achieve this an analysis
and synthesis framework of concepts will be built with a generic scope beyond this par-
ticular architecture, and then the proposed concepts will be applied in practice with an IC
implementation. The book consists of an introductory part about DACs (Chapters 1-2),
a modeling and analysis part for Current Steering Digital to Analog Converters (chapters
3-9) and a synthesis part (Chapters 10 and 11). Chapters 1 and 2 deal with the general
aspects of D/A converters, and those of the framework of analysis and synthesis that will
be developed.
Chapters 3-6 concern CS DACs. In Chapter 3 architectural and circuit aspects of CS
DACs are discussed. In Chapter 4, the current state of the art is examined which helps to
formulate the characteristics of knowledge that needs to be developed about the behavior
of this circuit. In Chapter 5 circuit error mechanisms due to hardware imperfections are
analyzed, emphasizing those that limit high frequency performance. This chapter reviews
and extends further existing knowledge about these error mechanisms. Chapter 6 deals
with high level DAC modeling. The signal errors are mapped to principle causes within
the physical hierarchy of the DAC and they are categorized to classes according to their
principle characteristics with amplitude, time, spatial domains, and other properties.
Chapters 7-9 deal specifically with the class of timing errors which is the most signif-
icant one for high frequencies. Chapter 7 addresses functional modeling issues of timing
errors, and shows that they can be described with Pulse Position and Pulse Width Modu-
lation in the DAC signal creation process. This unifies all the errors of this class under one
Pref ace xvii

common modulation mechanism, each error being a specific subcase of this mechanism
that is determined by its other error properties. In chapter 8 the developed models are ap-
plied to spatially local timing errors (timing skew between individual current transients)
which is one of the most important but least understood high frequency error mechanisms.
In chapter 9 these errors are analyzed in circuit details, moving from the functional as-
pects to circuit and transistor level ones. All analysis results are then combined to reveal
interesting design tradeoffs.
Chapters 10 and 11 deal with DAC synthesis. A generic view of DAC synthesis is pre-
sented in chapter 10. The information available about a CS DAC is classified according to
its type (e.g. information about signals, errors, application, user, etc.) and properties. Of
particular importance is the definition of a-priori information, which is information about
the DAC known at the design phase, and a-posteriori information obtained only after chip
implementation. It is explained that current DACs use only a-priori information to deal
with the dominant high-frequency error mechanisms. The use of a-posteriori information
can provide a next step in DAC performance and efficiency. Two methods that can deal
with local timing errors are discussed.
Chapter 11 presents the design of a concept driven 12 bit 500 Msample/s DAC IC
in a CMOS 0.18 µ m process that achieves exceptionally high performance at low power
consumption and occupying small area. The DAC is optimized using only a-priori infor-
mation about error generation mechanisms to investigate the limits of this approach.
 1

Digital to Analog conversion concepts

F UNCTIONAL , algorithmic, signal processing, and circuit aspects of a Digital to

Analog (D/A) converter will be briefly reviewed in this chapter. Definitions with
respect to these aspects and D/A converters architectures will be given.

1.1 Functional aspects

1.1.1 Definition of the D/A function
The term Digital to Analog (D/A) conversion describes the conversion of a signal that
represents data in Digital format to a signal that represents data in Analog format. This
description excludes the electrical nature of conversion, and refers basically to how infor-
mation is represented, i.e. in digital or in analog form. When one speaks of an electronic
Digital to Analog converter there are additional conversions that take place.
An electronic linear D/A converter is an electronic circuit that accepts at its input a
set of electrical signals, that represent a digital numeric code, and yields at its output an
analog electrical signal, i.e. in proportion to a reference electrical quantity as the input
numeric code is to the full range of possible codes. A full list of the electronic character-
istics that the ideal electronic D/A converter must satisfy are described in [1]. It is indeed
tempting to reduce the definition of the D/A converter to a statement similar to “the con-
version of an input code word to an output electric quantity”, neglecting completely the
electrical waveform characteristics of the input signal. Because information in the input
electrical signal is defined very accurately with the use of only two digits, the input elec-
trical signals can be abstracted to generic signals described by a sequence of values; it
becomes identical to speak of abstract signals with zero’s and one’s or of continuous time

1
2 Chapter 1 Digital to Analog conversion concepts

(CT) electrical signals that use specific voltage levels to represent logic levels. Since the
electrical nature of the input signal can be neglected the only relevant “time” issue is the
sequence of the input samples.
On the basis of this reduction an N bit linear D/A converter is the electronic system
that represents an N bit binary word D = D1 D2 ...DN at its input with an electrical quantity
at its output (usually voltage or current) that has amplitude or time domain characteristics
that are modulated in proportion to the value of the code word and to a reference quantity.

Code conversion Electrical signal creation Waveform shaping

amplitude and time references
C Ts

D(m) binary w(m) DT Pulse s(t)

to integer h(t)
CT

Figure 1.1 D/A conversion in the amplitude domain.

A functional diagram of the D/A conversion when the information is placed in the
amplitude domain is given in fig. 1.1. The generic input signal is represented by the
sequence of code words D(m). In the first stage of the diagram, the words D(m) are
converted into the integer values w(m). The second stage represents the creation of the
electrical signal that possesses physical dimensions. This is realized using amplitude
and time references. A multiplication assigns the amplitude dimensions to the abstract
signal. The Discrete-to-Continuous time conversion (DT/CT) assigns the time domain
properties to the signal. The last sub-function of the D/A function is the shaping (filtering)
of the generated electrical signal to obtain the predetermined shape (e.g. interpolation).
The result of the three sub-functions is an electrical signal consisting of pulses that are
amplitude modulated by the integer equivalent w(m) of the binary words D(m).
Where exactly the time domain conversion takes place does not imply any physical
necessity, rather it represents the subjectiveness of the model. Physically, time domain
exists in D(m) and can not be separated from it. From a modeling perspective, such a dis-
tinction defines at which point time domain issues are important at the realized hardware
and can not be neglected any more. For example, if a Track and Hold (T/H) circuit is used
at the output to re-sample the signal and clean it from artifacts that appear at the switching
transients, the time domain assignment takes place there. It should be mentioned that the
term DT is misleading, because it implies that time is involved in the signal D(m); this is
not true since the only relevant issue in D(m) is the sequence (the order) of the values.
The D/A conversion function with information encapsulated in the time domain of an
electrical signal is given in fig. 1.2 and can be explained in a similar manner. In summary,
the function of an ideal electronic D/A converter consists of:
1.1 Functional aspects 3

code conversion in the abstract amplitude domain.

conversion from the abstract to the electrical signal domain. It consists of amplitude
and time domain signal creation with the use of references (e,g, voltage, current).

Electrical signal shaping (filtering) in which the electrical signal takes a predeter-
mined pulse shape modulated by the integer value w.

Code conversion Electrical signal creation

time and amplitude references
Ts C

D(m) binary w(m) s(t)

to integer PWM

Figure 1.2 D/A conversion in the time domain.

In this description of a D/A converter with figures 1.1 and 1.2 there is no coupling of
the types of sub-operations and no transparency on the way of implementing each of
them. In practice, all three sub-functions come together every time a specific algorithm is
instantiated to realize the D/A function. The D/A converter that performs the 1-1 mapping
of an input code to an output electrical signal as defined by the previously mentioned
operations will be referred to as a D/A converter core, or simply a DAC core.

1.1.2 Functional specifications

A real D/A converter is subject to many physical imperfections that introduce limitations
to its functionality. The DAC is designed such that it complies with a set of functional
specifications, which can be embraced under the term “signal quality” within a well de-
fined area of electrical and environmental conditions. Specifications include

Functional specifications that express whether the signal quality offered by the
hardware complies to a prespecified range. Resolution, absolute accuracy, con-
version rate, dynamic range are typical examples.

Physical specifications that describe the physical resources required (area, power
etc) for the hardware to deliver a prespecified signal quality.

Environmental specifications that describe the conditions under which the hardware
can operate with a predetermined signal quality. Temperature is a typical example.
Hardware quality depends on the factors considered relevant for a given application. Of-
ten, figures of merit are defined to capture a combination of functional and physical spec-
ifications (e.g. energy per conversion per frequency for a specific accuracy). Functional
specifications for DAC’s are described in more detail in the following.
4 Chapter 1 Digital to Analog conversion concepts

Signal quality receives proper meaning by defining how information is embodied in

the characteristics of the electrical signal, and how these are affected by physical imper-
fections. In an ADC (see fig. 1.3) all errors due to physical imperfections are embodied

Input Output Input Output

ADC 00111 DAC

All problems are embodied Problems are distributed in

in the amplitude domain (codewords) the amplitude and time domains

Figure 1.3 Dynamic problems affecting amplitude and time domains of

DAC/ADC output signals.

in the amplitude domain of the output signal (the codewords). In a DAC the output sig-
nal consists of a series of pulses. Therefore, errors related to limitations in the dynamic
response of the DAC are embodied in the characteristics of pulse to pulse transitions (fig.
1.3). These dynamic phenomena decay substantially at the end of the sampling period
and the settled (DC) value of the converter can be determined. Therefore, the impact of
physical problems in the functional behavior of the DAC is distributed in both amplitude
and time domains at the output signal and each problem can be mapped to a specific de-
formation of the ideally expected waveform (overshoot, delay, settling, etc.); in contrast,
in an ADC everything ends to amplitude domain errors. Consequently, the revelant issue
for DAC’s is which output waveform characteristics are relevant for a given application.
A major distinction is between static and dynamic performance evaluation. This refers
to the use of time invariant, or variant input signals (e.g. sinusoids), respectively. The lat-
ter result in dynamics of transients that dominate the performance. One way of assessing
dynamic performance is based on the time domain response of the DAC for a full scale
pulse as input (fig. 1.4). This method relies on evaluation of waveform characteristics
such as the time it takes for the output signal to settle within a specified value (e.g. LSB).
Other criteria include the rise/fall times, or the glitch magnitude compared to an LSB
value. Evaluating time domain electrical characteristics was exercised until the beginning
of the 90’s.1 The shift of interest to the spectral properties of signals was essentially a shift
from characterizing hardware at a higher layer, following the trends of digital processing
systems evolution toward larger signal processing systems.
Sinusoidal signals are the most widely adopted type of signals used for performance
evaluation. When processing sinusoids, any waveform deformation that generates (non)
harmonic distortion is relevant to performance. Before giving the figures of merit that
describe linearity it is insightful to give a brief description of the concept of linearity.
1 Static and dynamic performance terminology for ADCs and DACs is given in [2], expressing the methods

to characterize functional performance (see also [3] for static and dynamic test methods of these times).
1.1 Functional aspects 5

overshoot and glitches < LSB

LSB LSB

settles to 1 LSB error

LSB
Settling time

Figure 1.4 Full scale transition: (a) settling time and (b) amplitude based eval-
uation of dynamic performance.

Nonlinear distortion is the distortion caused by a deviation from a linear relationship

between specified input and output parameters of a system or component. For the DAC,
nonlinear distortion refers to its input-output functional relationship. Yet, further specifi-
cation is required to define which particular aspects of this relationship are relevant.
The DAC realizes a transfer function between its input and output signal amplitudes.
For an ideal DAC this linear function can be described as s = α · w, where α is a gain
factor while s and w have their usual meaning. Time domain effects are not included here;
it simply defines the output settled, or DC, signal value that corresponds to an input value.
In practice, the transfer function is not linear and shows deviations. It can be modeled as
a ν -th order polynomial s = α1 w + α2 w2 + α3 w3 + ...αν wν . The degree of deviation from
the ideal transfer function determines the accuracy of the converter. Because only static
signals are assumed, it can be called static nonlinearity. Neglecting the inherent dynamics
of the DAC but using a time-variant signal, a nonlinear error is generated at the output
that changes over time. The only dynamic phenomenon here relates to the signal.
In reality time-variant signals are processed by a DAC that in addition involves certain
dynamic behavior. For a input sample to sample transition, an output signal transient is
composed. The nonlinear errors in these case extend to the nonlinear relationship between
the output signal transients, which are different for different input sample transitions.
Errors generated in this way are also dynamic nonlinear errors, but dynamic applies now
both to the signal and the inherent dynamics of the DAC. In practice, the DAC dynamics
are dominant as frequencies increase beyond a few MHz.

Number of bits

The number of bits N of the DAC represents the relative accuracy with which a full scale
electrical signal range can be represented in discrete steps. Observe that in a DAC quan-
tization noise or distortion is not a relevant issue since by nature of the DAC function it
does not introduce quantization.
6 Chapter 1 Digital to Analog conversion concepts

Differential and Integral Non-Linearity

For static performance characterization, Integral-Non-Linearity (INL) and the Differential-
Non-Linearity (DNL) figures are used. DNL expresses the output difference between two
adjacent codes compared to the LSB step ∆. The INL expresses output amplitude devi-
ations from ideal values for a selected input codeword. The ideal output values fall in a
line that is corrected for gain and offset errors. The DNL and INL at an input step k are
defined in [4] by
Ak −Ak−1 Ak
DNLk = a·∆
INLk = a·∆
(1.1)
where ∆ is the LSB step and a is the input value corrected for offset and gain error.
The worst case DNL and INL are given by
DNL = maxk∈1...N {|DNLk |}, INL = maxk∈1...N {|INLk |}, (1.2)

Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the power of the fundamental and the
total noise power within a certain frequency band excluding harmonic components:
PS
SNR = 10 · log10 , (1.3)
PN
where PS is the signal power and PN is the noise power in the band of interest.
The SNR is not a linearity figure in the strict sense. Whether or not it may be used in a
linearity context is a modeling issue. For example, amplitude quantization is a non-linear
effect that is expressed as a transfer function [5] and for sinusoidal signals it generates
harmonic distortion that can be calculated. However, it is often approximated as noise
(see [6] for an overview of the conditions). Other effects can be considered noisy as well.

Dynamic range
In a system or device dynamic range is the ratio of a specified maximum level of a pa-
rameter, such as power, current, voltage, or frequency to the minimum detectable value of
that parameter. The dynamic range is usually expressed in dB. In a transmission system,
dynamic range is the ratio of the overload level, i.e., the maximum signal power that the
system can tolerate without distortion of the signal, to the noise level of the system. Used
in the context of digital systems, it defines the ratio of maximum and minimum signal
levels required to maintain a specified bit error ratio.

Total Harmonic Distortion and Signal to Distortion ratio

The total harmonic distortion (THD) is the ratio of the total harmonic distortion power
and the power of the fundamental in a certain frequency band, i.e.
∞
∑k=2 Pk
T HD = 10 · log10 , (1.4)
PS
1.1 Functional aspects 7

where Pk is the power of the k-th harmonic, and PS is the power of the signal. The inverse
of the THD can be defined as the Signal to Distortion ratio (SDR).

Power (dB)
SFDR

f 2f 3f 4f
fundamental frequency (Hz)

Figure 1.5 Spurious Free Dynamic Range (SFDR).

Signal-to-Noise and Distortion Ratio

The signal-to-noise-and-distortion ratio (SNDR) is the ratio between the power of the
fundamental and the total noise and distortion power in a certain frequency band
PS
SNDR = 10 · log10 , (1.5)
PN + ∑∞k=2 Pk

where Pk is the power of the k-th harmonic.

Spurious Free Dynamic Range

The spurious-free dynamic range (SFDR) is the ratio between the power of the signal
and the power of the largest spurious (unwanted) tone within a certain frequency band, as
shown in figure 1.5. SFDR is usually expressed in dB as
PS
SFDR = 10 · log10 , (1.6)
Pmax
where PS is the signal power and Pmax is the power of the largest spurious component in the
band of interest. The SFDR is the same when one distortion component is very dominant
with respect to the other, and when all components are equal. In the former case the SFDR
approximates the SDR, but in the latter SFDR and SDR are widely different.

Bandwidth and conversion rate

All the previously given measures of linearity need always to be associated with a band-
width in which they are evaluated, and a conversion rate. The bandwidth of the DAC
8 Chapter 1 Digital to Analog conversion concepts

defines the frequency range in which the figures of merit are evaluated. The maximum
conversion rate of DAC defines the maximum rate of conversion of samples at which the
functional specifications are within their specified range. In literature, it is most often
used to describe the maximum conversion rate at which the DAC still operates, meaning
that it still captures properly the digital input data. This definition, however, does only
characterise the digital parts of the DAC and the limits of the technology used.

Functional specifications for this book

The range of functional specifications that are relevant for this thesis are

Resolution and accuracy 10 − 16 bits.

Conversion rates 100 − 1000+ MHz.

SFDR over 60 dB for signals up to the Nyquist frequency.

1.2 Algorithmic aspects

The definition of an algorithm is always given with respect to a particular problem that
needs to be solved. An algorithm defines a step-by-step problem solving procedure for
solving a problem in a finite number of steps. An algorithm has a ubiquitous scope and
applies in every step of the design hierarchy. The function defined by a DAC core can
be realized with a wide variety of algorithms. Each D/A conversion algorithm represents
a mapping of the D/A function to a specific combination of functional components and
operations that can realize the function. The main components of a D/A algorithm are

1. Coding. Coding describes all aspects related to how the assumed binary input sym-
bols will be converted in the end to integer symbols at the output. The weighting
can be binary, thermometer or any other code form which can be easily convertible
to an integer value.

2. The reference quantity. The (electric) reference of the signals being processed to
make the conversion.

3. The electrical generation mechanism. The electrical generation mechanism de-

scribes the physical mechanism that creates the signal. It is distinguished in

(a) the Amplitude domain, where for example amplitude modulation (eg. PAM)
describes the mechanism of signal shaping of the amplitude in proportion to
the input code,
(b) and in the Time domain, where PWM, PPM, etc. modulation concepts de-
scribe the signal shaping of the time domain characteristic (duration, position
etc) in proportion to the input code.
1.2 Algorithmic aspects 9

The combination of the algorithmic concepts is described with an algorithmic architecture

that binds together the exact functions between signals, signal components, the time steps
of execution, the amplitude conversion steps, and the reference division. The mapping, or
translation of the D/A algorithm to hardware includes always the following two steps

1. Partitioning: it defines how certain operations will be divided in sub-parts, each part
realized with different algorithmic concepts. It also defines the number of steps and
the order with which the algorithmic concepts instantiated occur.

2. Time Scheduling: it assigns relative time to the operations, ie. the order in which
the operations are performed.

Partitioning is a concept that can be applied hierarchically and recursively in a DAC. More
details about it will be given in another chapter.
Next, a specific form of partitioning used very often in the coding of the DAC will be
describe in more details: segmentation. The binary to decimal conversion is written as

N
w = ∑ Di 2i (1.7)
i=1

for an input binary code D = D1 D2 ...DN and an output decimal value w, which de-
scribes that for an N bit converter a word consisting of N digits are multiplied with binary
weighted units and then summed. Let us consider the following modification of eq. (1.7):

NF NC
w = ∑ Di 2i−1 + ∑ Dk+NF 2k−1 2NF (1.8)
i=1 k=1

with NC + NF = N. This equation says that the output code is generated by the summation
of two terms, each one defined with different weighting factors and different bits of the
input code word. The separation of the overall code conversion in two or more parts is
a partitioning of the code. The part with the NC Most Significant Bits (MSB’s) is called
the coarse part, and the part with the NF Least Significant Bits (LSB’s) fine part. Code
conversion in a segment requires a dedicated code conversion digital circuitry.
In DAC terminology, segmentation is explicitly meant as partitioning of the binary
code in one part that remains binary coded, and another one that is decoded to a ther-
mometer code [7], which is only one of the possibilities available. If all binary words are
translated to thermometer code then it is said that the converter is called fully segmented;
and when only some bits become thermometer encoded, then the larger the number of the
thermometer bits is, the larger the segmentation that the converter uses. For example, for
a 10 bit DAC in [8] 80% segmentation means 8 thermometer and 2 binary bits. This ter-
minology will not be used here. Segmentation is a form of partitioning, consequently the
larger the segmentation should be interpreted as “the more the binary code is partitioned
to more parts, or segments”, and not that number of bits per partition is increased.
10 Chapter 1 Digital to Analog conversion concepts

N
2 −1
C
N
2 −2
N−1 N−2 N−3 0
2 2 2 2

DN DN−1 DN−2 D1
2N−3 Cw
C

Cw

D encoder

(a) (b)

Figure 1.6 Parallel-bit algorithms: (a) combination of weighted units, (b) se-
lection of the correct value among all possible ones.

Examples of algorithms

In fig. 1.6(a) binary weighted (coding) summation is portrayed. Unit replicas of the
reference electrical quantity are provided by reference replication and scaling mecha-
nisms. Other types of algorithms which are not based on summation and combination of
weighted units exist as well. In fig. 1.6(b) another algorithm is shown, named parallel-
select algorithm [1]. The algorithm selects the proper output value among all 2N − 1
possible output values. This means that all possible values must be available (task to
be accomplished by reference replication and scaling). A selection mechanism picks the
right output value with the aid of an encoding mechanism.

D= D D... D i=1,2,..,N
1 2 N
C C

D0
D (−1) D 0 is the sign−bit for D i
N+1−i

wi w(m)
−1 −1 Di z−1/2
z−1/2 2 2

z−1/2 z−1 z−1/2

(a) (b)
Figure 1.7 Serial-bit algorithms: (a) conversion starts with LSB DN , (b) con-
version starts with MSB D1.
1.3 Signal processing aspects 11

Because in fig. 1.6(a) the composition of the output word is made in parallel for all
weighted units the algorithm is called parallel-bit. The same applies for the algorithm
depicted in fig. 1.6(b). Parallel-bit algorithms offer intrinsic advantages for high speed
operation because all sub-operations can be performed synchronously to each other.
Another main category of algorithms are the serial-bit algorithms [1]. The main char-
acteristic of serial-bit converters is that they require a sequence of steps before they gener-
ate the correct output value. In each step a bit is resolved and the equivalent analog value
of this bit is added in the output. After all bits are resolved the final value is available
for use. The type of coding used determines the number of steps. For binary weighting
codes N steps are needed, whereas for a thermometer code the steps vary between zero
and 2N − 1. A binary weighted serial-bit algorithm is described by the iterative procedure:

w(m, i) = w(m, i − 1) + Di (m)2i (1.9)

where m is the sample index, and i iterates from bit to bit. A specific version of a serial
bit algorithm is the cyclic algorithm, which uses the same hardware iteratively for all
steps of the conversion. Two examples of serial-bit algorithms are shown in fig. 1.7. In
literature, the term “algorithmic” converter is misleading because it is meant only for a
specific type of cyclic converters neglecting the fact that all converters are algorithmic by
nature! For both algorithmic-architectures shown in fig. 1.7 the code conversion is based
on summation of binary weighted units, hence it is finalized after N steps. Therefore,
although both are serial, there are differences on how they are realized.
Most of the concepts mentioned can be instantiated recursively. An example can
be found in [9], where the partitioning concepts are applied in the amplitude and time
domains, in the coding, in a serial-bit formation. In particular, an amplitude domain D/A
converter of 15 bits is partitioned in three parts (5 − 5 − 5, i.e. coarse, fine, finest). The
three partitions are cascaded in series, which means that the conversion is divided in three
sequential steps. Each part is individually realized using thermometer coding and realized
again in a serial-bit manner. Several other algorithmic concepts may be added next to the
parallel and serial concepts: for example, converters based on counters, on duty cycles,
interpolation between previous and next values, etc.

1.3 Signal processing aspects

Sampling and interpolation theory is the theoretical framework under which A/D and
D/A conversion is placed when it comes to input-output signal relationships. The D/A
function represents the reconstruction process of a sampled signal, however, if seen in
view of generic discrete time signals it can be defined as a signal generation process. Two
signal processing aspects of this process are discussed in this section.

1.3.1 Waveforms and Line coding

In communication terminology Binary Line Coding [10] represents how a series of bit
data are formatted physically in an electrical signal which is passed on to a physical
12 Chapter 1 Digital to Analog conversion concepts

s(t)

mTs (m+1)Ts (m+2)Ts t (sec)

Figure 1.8 DT/CT conversion and RZ interpolation of samples in a DAC.

channel. These formats are called line codes. Line codes are distinguished in two major
categories: Return-to-Zero (RZ) and Non-Return-to-Zero (NRZ). Given a bit interval Ts ,
a RZ waveform returns to zero volts (for a voltage waveform) for a portion of the bit
interval, whereas the NRZ stays constant. Line codes may be further classified according
to the voltage levels that represent the binary data. Examples include Unipolar signaling,
Polar signaling, Bipolar (Pseudoternary) signaling [10], etc.

s(t)

mTs (m+1)Ts (m+2)Ts t (sec)

Figure 1.9 Interpolation of samples in D/A converter using NRZ pulses.

The D/A converter output can show similar shape, and this is why the terms RZ and
NRZ are used. In the D/A output, the signal represents CT information, and the pulse
shape determines the interpolation of the signal value between the sample moments.
DT/CT conversion and RZ Interpolation of D/A input data w(m) is shown in fig. 1.8.
If T0 is the duration of each pulse, then the RZ pulses are described by
∞
s(t) = u(t) ⊗ ∑ w(m) (δ (t − mTs ) − δ (t − T0 − mTs )) (1.10)
m=−∞

where u(t) is the unit step function. With NRZ pulses the signal is described in a Σ∆ form
∞
s(t) = u(t) ⊗ ∑ ∆w(m)δ (t − mTs ) (1.11)
m=−∞

with zero initial conditions. A graphical representation of this signal is given in fig. 1.9.
1.4 Circuit aspects 13

The above descriptions can now be defined in a more generic way. Let us consider
only the signal creation process of a real signal from an arbitrary sequence of samples
z(m) assuming an arbitrary interpolating pulse h(t). Then the generated signal is given by
∞ ∞
s(t) = ∑ z(m)h(t − mTs ) = h(t) ⊗ ∑ z(m)δ (t − mTs ) (1.12)
m=−∞ m=−∞

The signal generation process consists of the creation of an amplitude modulated delta
pulse train, and the interpolation (or signal shaping, filtering, etc.), which assigns the
wanted shape to the signal. The creation of the delta train is called DT/CT conversion,
despite that the sequence of samples z(m) does not constitute any time varying signal as
the term DT implies. Notice now how both NRZ and RZ waveforms from eq. (1.10)
and (1.10), respectively, can be mapped to the general description of eq. (1.12). For
the RZ waveform, we let the interpolating pulse be h(t) = u(t) and the samples z(m) to
represent the specific samples w(m) of the D/A input. For the NRZ waveform, we assume
that the signal w(m) is passed through a differentiator before it is interpolated, such that
z(m) = ∆w(m) = w(m) − w(m − 1). Alternatively, one may consider z(m) = w(m) and
replace h(t) by p(t), where p(t) is a pulse with a fixed duration of one sample period Ts .
Moving back to the digital bitstream, to create such a waveform a series of finite en-
ergy pulses h(t − mTs ) is amplitude modulated by the binary data z(m), which are either
logic one, or logic zero. For the spectral content of such a pulse train as a function of
the pulse type, the encoding of bit values, etc. there is a plethora of results in telecom-
munication theory textbooks that describe it when assumptions are made for the type and
content of signals z(m) (stochastic, deterministic, signals that represent specific digital
modulation schemes, etc.) and for the specific line coding [10]. These results are placed
in the heart of the D/A area on the basis of the previously mentioned similarities, if one
modifies the meaning and properties of z(m) to the D/A input signal, and then links the
D/A output signal to the particular physical problems that appear in a physical realization.

1.3.2 Signal Modulation concepts

The D/A conversion algorithms that described so far refer to algorithms that implement
the DAC core function. DAC cores can be used as well as parts of larger D/A converters
that use signal modulation in the whole stream of data that carries information, instead of
using the one to one mapping between an input and an output value.
These D/A converters seize specific modulation concepts that convert information
from a given combination of amplitude and time domains to another combination, thereby
operating in both domains of a real signal simultaneously. Σ∆ modulation is maybe the
most popular modulation concepts that belongs in this category.

1.4 Circuit aspects

The architecture of the circuit hardware is the result of a one-to-many translation of an
algorithm to hardware. In this section we review some basic architectures that realize
14 Chapter 1 Digital to Analog conversion concepts

DACs. First architecture terminology is given, and then resistive voltage, capacitive volt-
age and charge, and current division architectures are briefly described.

1.4.1 Architecture terminology

Architectures are distinguished in literature via combinations of circuit and algorithmic
concepts, or via distinguishing features, e.g. Σ∆, Flash, cyclic, interpolative converters
for DACs in general, or current-steering, R-2R ladder, binary weighted, resistor string,
charge re-distribution, segmented, etc. for DAC cores in particular. Here, the focus is
at high speed operation, therefore only parallel amplitude-domain DAC’s are considered.
An architecture can be further distinguished in three main circuit parts: (1) reference
scaling and replication network; (2) code conversion network; (3) output network.

Reference network

To realize waveforms that have characteristics proportional to the applied input codes, the
amplitude range of the converter (amplitude and time references) should be discretized
such that all resolution defined values can be recovered either via reference division, or
via replications of the reference into scaled units and combinations of them according
to a code. For an N bit linear converter with all information in the amplitude domain,
the reference scaling and replication circuit should provide 2N − 1 discrete unit levels.
Reference scaling in general (division or multiplication) is realized with a few basic circuit
networks consisting of resistors, capacitors, voltage and current sources. Most amplitude
domain scaling concepts exploit the charge conservation law.

Code conversion

The code conversion domain is where the binary to integer conversion is realized. The
two main implementations are (a) a selection network that selects the correct value that
corresponds to the input binary code, among all possible codes that are available for se-
lection, (b) a combinatorial network, which combines weighted quantities according to
a code or code combinations and generates the proper output value dependent on the in-
put code. The code conversion domain can be realized in the voltage, current, or charge
domain and usually grands the name of the converter.

Output network

It is the role of the output network to make the necessary conversions and impedance
adaptations such that the DAC can drive efficiently external loads. The most common
blocks required are voltage to voltage buffers for impedance adaptation, resistors, or in-
tegrating amplifiers to convert charge packets or currents into voltage. In practice, these
circuits influence significantly the high speed potential of an architecture.
1.4 Circuit aspects 15

1.4.2 Resistive voltage division architectures

A parallel resistive voltage division DAC is shown in fig 1.10 [1]. It consists of three
stages: the first is a resistive divider, the second is a network of switches, and the third is an
impedance adaptation buffer. The reference voltage Vre f of the voltage divider is divided

Vref
RM D1
D2
V M−1
R M−1
V M−2 R

D1 DN
R V0
−
+
D1
V2

V1
R1 D2
D1
Volt Volt

Voltage division Voltage level selection Impedance adaptation

Figure 1.10 Resistor string DAC core circuit.

in M = 2N steps using a network of identical resistors. Because the number of resistors

scales with a power of N, for high resolution this architecture becomes impractical.
The main consideration for the ladder is to meet the requirements for INL and DNL,
which are limited by process mismatch between resistors. The ladder’s resistors are made
of polysilicon or of diffusion layers. The physical reasons causing the values of identically
designed resistors to vary are geometrical variations, doping level variations, variations in
contact resistances, etc. The layout of the resistor ladderon silicon has a significant impact
on the magnitude of these problems. The DC signal error for an input code is determined
by the accumulation of the individual resistor errors that contribute to the output value.
When the individual errors are random, the law of the large numbers applies.
The resistor value seen at each tap is important for the capability of the ladder to
discharge large capacitive load at each tap. Because the resistance varies from tap to
tap the speed of charging a capacitive load varies as well. The transition time from a
signal value to another is modulated by the input codeword value because this determines
which tap is selected. This result in significant signal distortion. If the ladders are made
of diffused resistors, then the dependence of the resistance value on the thickness of the
depletion layer beneath the device which is a function of the voltage is important, because
this voltage is a function of the rank of the resistor in the ladder, and varies from the
reference voltage to the ground. Also, the depletion layer capacitance across the ladder to
16 Chapter 1 Digital to Analog conversion concepts

the substrate can also impact the charging and discharging time constants of each tap.
The network of switches is controlled via a decoder by the input bits. For an input
codeword the network selects one of the binary taps and provides resistive path from
that tap to the output node. For an N bit DAC N switches appear in series between the
tap and the output nodes. Consequently, a very large number of switches is required for
high resolution. Moreover, the switch devices introduce additional input signal dependent
impedance modulation [11]. Finally, an output buffer is required by this DAC to drive
properly an output load. This buffer is a major bottleneck in high speed.
In literature several architectural modifications have been considered [4,7,11]. In [12]
a modification called switched subdivider has been introduced, which reduces the number
of required devices to approximately 2N/2 instead of 2N . This technique is based on par-
titioning the ladder in a coarse-fine configuration. Drawbacks of the switched subdivider
architecture have been alleviated with the double resistor string ladder (intermeshed lad-
der) architecture [13]. In [11] the combination of an intermeshed ladder [13] in a matrix
arrangement [14] proved the feasibility of 10 bits of resolution with 50 MHz conversion
rate, which is basically the highest reported for these type of converter. In summary, the
main limitations of this circuit architecture are: the accuracy of matching (random and
deterministic) between the resistors; the output buffer, which dominates the performance
at higher frequencies; the code-dependent output impedance; the switch network.
Resistor string DACs proved capable and versatile for medium-high resolution and
low to moderate speed applications due to several inherent advantages (monotonicity,
versatility, compactness of integration etc), but not equally succesful for high speeds.

1.4.3 Capacitive voltage and charge division architectures

Capacitive voltage and charge division based DAC cores are realized with networks of
switched capacitors based on charge re-distribution. This concept has been adopted in
[15] to create a voltage-division binary-weighted parallel-bit A/D converter, whereas in
[16] it was used to construct a voltage-division cyclic DAC. The binary-weighted DAC
from [15] is portrayed in fig. 1.11(a).
The SC network consists of weighted capacitors. An additional capacitor C is added
such that for an N bit converter a total of 2N C capacitance is present at the common ca-
pacitor terminal. The capacitor array is discharged before each conversion via the switch
Sd . Then all capacitors except the additional resume the reference voltage at their individ-
ual terminals and precharge to Vre f . The additional capacitor C is held grounded. A total
charge Q = Vre f C2N is deposited on the top plates. When the conversion starts all capac-
itors resume ground, or Vre f , dependent on their bits, while the additional capacitor is let
free. The charge conservation law makes the stored charge in the top plate to re-distribute
forcing a voltage voltage at the top plate which is a fraction of Vre f according to the code.
The accuracy of SC DACs is limited by capacitor matching [17,18] and shares similar-
ities with that of resistors: for a fixed relative capacitance spread, the averaging principle
determines the impact on INL as a function of the number of elements of the converter. In-
herent matching of capacitors is practically limited around the level of 10 bits of accuracy.
Additional non-linearity problems rise from the voltage and temperature dependency of
1.4 Circuit aspects 17

SI

CI

Sd Sd
VC VC
− Vout Vout
−
C 20 C 21 C 2N−1 C C 20 C 21 C 2N−1 C
+ +

S1 S2 SN S1 S2 SN

V ref V ref

(a) (b)

Figure 1.11 (a) SC DAC core circuit, (b)SC DAC using an integrating amplifier.

MOS integrated capacitors [17, 18]. The dynamic performance of SC DACs based on
parallel capacitor arrays is highly affected by the large capacitance connected in parallel
in the common node, and by the thermal noise considerations that dictate large capacitors.
Notice that for all SC DACs a voltage buffer is required as well. For charge division, this
buffer is replaced by an integrator to convert the current delivering the charge packets into
voltage transients. To drive resistive loads an additional Gm stage may be necessary. The
requirements for such blocks limits substantially the maximum speed of operation for SC
DACs. SC DACs are realized today with differential circuit topologies.
The architecture shown in fig. 1.11(a) has received several modifications [4, 7, 9,
19–23]. In [24, 25] the binary capacitor array was partitioned in coarse-fine segments
connected by a capacitive divider (two-stage binary-weighted architecture [19, 26]). In
this way, the LSB to MSB capacitor ratio’s was reduced significantly. A combination of
circuit and code level partitioning was applied in [27] using a coarse thermometer resistor
part and a fine binary capacitor part. The transition from the voltage division to the charge
division using the same capacitor array from fig. 1.11(a) has been introduced in [19] (see
fig. 1.11(b)). A circuit modification called the Direct-Charge-Transfer (DCT) technique
is described in [22]. Sequential bisection of charge has been initially applied in [20]
and recently in [28] and [29] with 10 bits in a differential version reaching a sampling
rate of 400 Msample/s [29], and good dynamic performance for 300 Msample/s. In
summary, SC DAC’s are limited by: matching accuracy of the capacitors; speed and
linearity limitations of the voltage buffer; large capacitance present in the node of the top
plates of the capacitors; non-linear relation between a capacitor’s value and the voltage;
on-linear behavior of the junction capacitance in MOS switches; thermal noise.
SC DAC cores have been used successfully as parts of other architectures such as
“algorithmic” ADCs [30], pipeline [31], and Σ∆ ADCs and DACs [22, 32]. A wide ap-
plication range is covered with this technique, from low data rate very high-resolution
audio DACs [22, 23, 33] to high-resolution medium-frequencies [32] for communication
applications (e.g. ADSL), SC DACs have been proven most suitable for high accuracy
applications (12 − 16+ bits) and low to medium frequencies (1 kHz − 1 MHz).
18 Chapter 1 Digital to Analog conversion concepts

1.4.4 Current division based architectures

A parallel DAC based on current division is shown in fig. 1.12 known as the current
steering (CS) DAC. It consists of a reference current replication network, a network that
combines binary weighted currents to generate the output value and a current to voltage
converter. The original version of this architecture was filed as a patent in 1955 [1] and
granted in 1963. This architecture has proven well its potential for high speeds because
the current steering nature of the circuitry is inherently fast, and because the demanding
output buffer can be replaced with a simple resistor.

V out

I/V buffer

MSB LSB

I N−1 I1

Current division network

Figure 1.12 Conceptual diagram of the binary CS DAC architecture.

CS DAC’s are used for high speed and high resolution applications such as Direct
Digital Synthesis, video applications, upstream cable transmission channels, etc. DACs
with conversion rates in the range of hundreds of MHz have been available in non CMOS
processes for a long time already [34–38]. Recently they appear in CMOS as well [8, 39,
40] whereas resolution and accuracy of 10 − 16 bits are mainstream features of todays
DACs [41–43]. The dynamic range offered by today’s realizations vary roughly between
50 − 90 dB dependent mainly on frequency ranges and conversion rates and not so much
on the resolution. This architecture will be the main focus for the remaining of this book.

1.5 Conclusions
The chapter presented an overview of the functional, algorithmic, and circuit aspects of
Digital to Analog converters. The D/A conversion function was defined as a signal cre-
ation process that realizes a code conversion in the abstract amplitude domain, a conver-
sion from the abstract to the electrical signal domain, and a process of electrical signal
shaping. The algorithmic aspects of the DAC were discussed, and the concepts of parti-
tioning and scheduling were introduced. Waveform Line coding in the DAC output pulses
was defined based on its similarities with digital pulse methods. Finally, circuit architec-
ture terminology and an overview of the main DAC architectures were given.
 2

Framework for Analysis and Synthesis of DACs

T HE qualitative lines of the proposed framework of analysis and synthesis for DACs
will be described in this chapter.

2.1 Overview
The main lines of an analysis and synthesis framework are explained with the aid of fig.
2.1. The system, e.g. a DAC, realizes a function between input and output signals. It
can be described in various hierarchical layers with subfunctions, circuits, etc. Actual
input signals are applied to it via its functional, electrical, and physical environment.
The functional inputs are constitutional parts of its functional relationship, whereas all
other inputs are parameters of its behavior. The outputs responses of the system and its
physical characteristics are described by properties, such as signal quality, silicon area,
power consumption, etc. Several signals constitute its hidden excitations and responses
that are visible only within its hierarchy.
An analysis framework reveals the links between the system responses and proper-
ties and the input excitations applied to it, and shows the physical, circuit, and functional
mechanisms and principles that govern its operation. Synthesis is the inverse of analysis.
It starts with a predetermined aim of a system that is to be built and problems to address,
although specific properties are still left open. A synthesis combines analysis with prin-
ciple design techniques throughout the complete hierarchy of the system, from physics to
signals. Therefore, synthesis requires the knowledge of design techniques to exploit the
knowledge offered by the analysis in view of a coarsely defined system. A specific design
example is the result of the combination of a specific set of required system properties
-the specifications-, and the general synthesis procedures.

19
 20
Figure 2.1 Framework for analysis and synthesis.
DAC synthesis specific design example

actual system responses

DAC analysis
all system
SYSTEM
excitations
physical & signal
specifications
properties

Chapter 2 Frame work for Analysis and Synthesis of DACs

hidden signal/system signal & physical
responses&properties (e.g. resources,
environmental)

Design procedure

Available IC
design technology Instatiation&combinations
of techniques

principal techniques
algorithm
function

physics
device
circuit
2.2 Frame work description 21

2.2 Framework description

In this section the main aspects of the framework for analysis and synthesis that will
be build will be described. For a DAC, the limit to achieve low signal errors and high
quality figures of performance (functional, physical, etc.) is determined by two factors:
(a) the potential offered by the used technology that realizes the converter, (b) the level of
exploitation of this potential, which is determined by the knowledge available about the
way errors are generated, and the use of proper techniques to exploit this potential.

2.2.1 Analysis
The CS DAC represents the system shown in fig. 2.1. Of primary role in the developed
concepts is the meaning of errors in the actual DAC response -the output signal-, and the
way it can be grasped functionally, given that only in the functional level they can be
evaluated. The meaning of errors in the signal can be understood introducing the concept
of the normalized pulses at the DAC output. In the top left side of fig. 2.2 an ideal
DAC output signal is shown. Below the actual signal we see the normalized pulses that
result by dividing each pulse with the corresponding number of discrete steps it includes.
In this ideal situation all normalized pulses are identical; they start at the same moment
every other Ts and they have the same shape during the transition from the old value to
the new value. The problem is that for a wide variety of reasons, the actual DAC signal
pulses are corrupted, consequently their normalized counterparts look different from each
other. This can be seen at the right side of fig. 2.2. The normalized deformations is
an indication of signal errors. If the normalized pulses are different for each sample in

Ideal signal Actual signal

output signal
normalized transitions

mTs (m+1)Ts mTs (m+1)Ts

time time

Figure 2.2 The concept of normalized pulses.

22 Chapter 2 Frame work for Analysis and Synthesis of DACs

a data-dependent way, then for a sinusoidal signal the errors are harmonically related
to it, whereas if the deformations are random, then the results are noise and distortion
dependent on the correlation with the input signal.
From chapter 1, in eq. (1.12) we see that the signal creation mechanism is based on
mapping a sequence of samples to a sequence of pulses according to

z(m) → z(m) · h(t) ⊗ δ (t − mTs ) (2.1)



 
amplitude shape timing

which says that

1. the amplitude of the signal is determined by z(m),
2. the time difference between successive sample transitions equals Ts ,
3. the shape of the pulse h(t) is identical for every code to code transition.
Therefore, when modeling the actual signal with the former equation, the timing of a pulse
can be distinguished from its shape, both of which together form the actual signal pulse,
or the actual code to code signal transition. In the following the use of the word actual
is meant for this distinction. If each transition from an input value to another resulted
in identical normalized pulse shape and ideally accurate timing, then the ideal amplitude
modulated pulse train given in eq. (2.1) would be obtained. The quality degradation of
a DACs actual output signal can be related to the deformations of its normalized pulse
shape and timing in random or deterministic ways, correlated or not to the input signal
(for example, clock jitter). In other words, the signal’s quality is a function of the the
non-linear transfer functions pulse-shape vs. signal, and timing vs. signal.

Horizontal modulation in the signal flow

DAC function

signal in signal out

z(m) subfunction 1 subfunction 2 subfunction 3 s(t)
(decoding) (re−timing) (V/I conversion)

Figure 2.3 Signal flow in the functional description of the DAC.

Another aspect in the framework is the association between output signal errors and
the input signal in view of system parameters and properties of lower hierarchy: that is,
how do the normalized pulses depend on the signal; what do exactly these dependencies
cause; what is their dependence with system properties and parameters.
2.2 Frame work description 23

To understand these aspects the so called error generation mechanism of each error
need to be found. These are the mixing of vertical and horizontal modulation mecha-
nisms. The DAC function can be partitioned in main subfunctions realized by functional
circuits, which are further realized by circuit components. In each hierarchy layer there
are horizontal modulation mechanisms in the input-output signal flow. Horizontal means
that the modulations take place at the same physical abstraction layer. For example, the
principles of modulation theory apply to describe how the signal is generated from its
primitive signal components in the functional layer: this defines the functional signal
generation mechanisms of the DAC. A description of this functional mechanism is given
in fig. 2.3 for the CS DAC, without loss of generality. Circuit imperfections are usu-
ally introduced at specific locations at the bottom layers of the DAC description, however
they can be abstracted at the functional level. How they are introduced at these locations
is determined by the vertical modulation mechanisms which translate physical imperfec-
tions to error signals at the subfunctions. The way errors are generated in each sublayer
can be described with the corresponding error mechanisms (e.g. circuit mechanisms).
Consequently, the mixture of horizontal and vertical modulation mechanisms results in
the creation of signal errors in the output signal (see the schematic in fig. 2.4), and it
describes the error generation, or error creation mechanism.

Horizontal modulation in the signal flow

Vertical modulation from physics to signal

DAC functional description

signal in
subfunction 1 subfunction 2 subfunction 3 signal out
z(m)
s(t)

circuit network circuit network circuit network

circuit transistor circuit transistor circuit transistor

physical physical physical

Environment

Figure 2.4 Vertical and horizontal error generation mechanisms.

The pattern that will be followed is the following

1. Vertical error mechanisms are analyzed (i.e. the imperfections in the realization of
each DAC subfunction) in electronic circuit details;

2. The results of the analysis will be translated to abstract errors in the subfunctions
such subsignals embody important properties of the lower hierarchical levels. This
will be made by grouping errors that share similar properties. Therefore, error
properties will be defined, and the errors will be classified.
24 Chapter 2 Frame work for Analysis and Synthesis of DACs

3. The expanded signal flow such as the one given in fig. 2.4 will be reduced to a
simple functional description similar to eq. (1.12). This will be studied to reveal
the signal errors as a function of generic input signals with lower hierarchical layer
properties as parameters.

4. The generic results will then be applied to specific cases of error mechanisms with
specific setting of DAC input signals and system parameters.

2.2.2 Synthesis
The exploitation of knowledge over the error generation mechanisms in the DAC consists
of two components: first, use of the analysis to rationalize and improve the way DACs are
designed with established designed techniques, subsequently improving the state of the
art performance envelope, and second, to pave the way for new design techniques that can
push the DAC performance envelope even further. How this will be achieved is further
described in the following paragraphs.
The analysis framework approach described previously, summarizes the error knowl-
edge by classifying errors according to their principle properties. Furthermore, via the
identification of the vertical and horizontal error components it shows how errors are in-
fluenced by parameters, actual and hidden signals, etc. that span through the complete
physical hierarchy of the DAC. Therefore, in fig. 2.1 it can be said that the analysis pro-
vides the knowledge on how the output signal functional and physical properties of the
DAC are parameterized to its excitations, responses and parameters.
Since all errors of a class share common characteristics, the line of thinking can be
inverted to see that all errors of the same class can be treated in the same principle ways;
each class of errors can be associated with specific principle techniques. Of course, treat-
ing an error requires that there is specific information about it (its actual values, its param-
eters, etc.). Consequently, once the basic properties of an error are known, and informa-
tion about it or its principle components can be extracted, in principle it can be corrected
using principal techniques shown at the bottom of fig. 2.1.
The information about the errors, their principle components, the architecture and
circuits, the input and output signals, the application, the environment, and many more,
all relevant ot the DAC that is to be realized, can be distinguished to a-priori and a-
posteriori information. A-priori information means that it is known prior the design phase
and can be taken into account in it, whereas a-posteriori information can only obtained
after manufacturing. Information is then used to process errors instantiating combinations
of techniques. As a result, the way design techniques use information can also distinguish
them in those based on a-priori, and those based on a-posteriori information.
The combination of the analysis for the CS DAC architecture and with design tech-
niques reveals a landscape plenty of unexplored paths. Specification will be made on
which paths to explore experimentally, because not all options are physical realizable, or
beneficial to do so.
 3

Current Steering DACs

I N this chapter a more detailed look is given in the Current Steering DAC architecture.
Initially, some architectural, circuit and electronic aspects of it are described, and then
an overview is given of existing technology implementations.

3.1 Basic circuit

A fully binary weighted DAC is shown in fig. 3.1. It consists of a current replication
network which generates weighted currents (shown as independent current sources), a
current switching network controlled by the binary bits, and a resistor that converts the
current to voltage. A new N bit word sets the switches in the corresponding on or off state.
The switch network combines at the output node the corresponding current and creates
the output value. This process repeats for each new word.
On the right side of fig. 3.1 a possible implementation with MOS transistors is shown.
The LSB current source consists of a MOS current source in a cascode configuration.
Both are biased at constant voltages. To build the current sources of the other bits, the
LSB transistors are sized up according to the bit weight and are biased by the same bias
voltages. The switches are made by differential pairs, and their sizes are scaled up accord-
ing to the bit values as well. In practice, partitioning is applied to the weighted sources and
each weighted current source (or cascodes, or switches) is made of a number of LSB de-
vices connected in parallel (the LSB device becomes the unit device). By partitioning the
weighted devices in units so that the MSB consists of 2N −1 unit devices, the unit devices
can be positioned according to common-centroids or other related layouting algorithms
to reduce the impact of matching error gradients etc.

25
26 Chapter 3 Current Steering DACs

Switched current cell

R V out
differential
current
MSB LSB switch

I N−1 I N−2 cascoded

I I current
source

Figure 3.1 Simple binary weighted CS DAC and transistor implementation.

This very simple and compact implementation is able to reach very high conversion
rates, being limited only by the steepness of the data waveforms carrying the bits, by the
maximum switching speed of the current switches, and by the process limitations. How-
ever, its simplicity and low power is paid with severe drawbacks that limit its performance
long before the limits of the technology are reached. There exist two main problems.
First, matching requirements for achieving good accuracy are very high because weight-
ing restricts the advantages offered by the law of the large numbers. The MSB current
(2N − 1 times larger than the LSB) needs to be matched to the LSB one within one LSB
accuracy. This dictates tough matching requirements.
The second problem relates to the weighted impact of switching problems: the so-
called MSB/LSB glitches. They can be the result of imperfect synchronization of the
data waveforms that control the current switches. For example, in a 6 bit binary weighted
DAC at the midscale transition 011111 → 100000 the MSB current source turns on and
all the remaining bits turn off. If the MSB source turns on a bit earlier than the remaining
sources turn off, then for a time interval the code 111111 will appear before the 100000.
This instanteneous voltage spike (major carry glitch) in the normal operation of the DAC
creates harmonic distortion. Glitches with lower amplitudes appear also at the transitions
at 1/4, 1/8... This type of problems has been for years the menace of CS DAC’s.
Full binary weighted converters have been primarily reported in literature until the
end of the 70’s and in some high conversion rate DACs in the 80’s [35]. Some efforts on
this direction are still made today [44, 45], mainly with an eye on the low power corners
of the design space. The solution for the MSB/LSB glitches were the famous de-glitching
circuits, which appeared already before [46,47]. The term “de-glitching” is not very much
in use today, but the concept behind it (re-sampling) is used very often [4, 7, 23, 42] at the
penalty of migrating all problems of the switches to a Track and Hold (T/H) circuit that
can not operate at very high frequencies with good dynamic performance.

3.1.1 Partitioning and segmentation

Code partitioning was introduced in [48] as a means to reduce the matching requirements
between MSB and LSB sources. However, its impact is much broader. Typical options is
3.1 Basic circuit 27

R V out R R

V out

I I I
Vb2
Vb1
Output: 2^N−1 bits
Binary to thermometer
decoder Bit 1 Bit 2^N−1
Output: 2^N−1 bits in differential form
Binary to thermometer decoder
N 1
Binary input
N 1
Binary input

Figure 3.2 Thermometer CS DAC and its circuit implementation in CMOS.

to use some binary and some thermometer bits. Other codes can be used as well. In the
following a brief overview of the existing views of code partitioning is given.
In the far opposite side of the full binary DAC lies the full thermometer DAC (fig. 3.2).
Each thermometer word consists of 2N − 1 bits, each one driving a switched current cell.
All switched current cells are identical relaxing the matching requirements substantially.
Binary weighted switching problems are eliminated and monotonicity is guaranteed be-
cause when bits change in the input, sources are either turned on, or turned off, but not
both. The matching of timing and switching behavior of the identical switching currents
becomes now a major problem. It is nowadays one of the most important issues of CS
DACs. As it will be shown later, large numbers governs equally well this problem.
The large numbers is the strong and the weak point of this method. The strong point
is the averaging principle. However, as the resolution scales up, the number of elements
increases dramatically (e.g. 4095 switched current cells for a 12 bits DAC) and requires a
tremendously complex decoder, interconnect lines, etc. This approach becomes impracti-
cal for more than 8 bits (255 elements), although there are exceptions [49]. And despite
differences in the switching currents (e.g. due to mismatch) average better with more
thermometer bits, at the same time their synchronization becomes more difficult.
A compromise between the two is the segmented (partitioned) [48] converter which
uses a coarse thermometer part, and a fine binary part. A conventional segmented archi-
tecture (fig. 3.3) consists of

1. a digital decoder responsible for encoding operations for the binary input data.

2. a delay equalizer that matches coarsely the delays of binary and thermometer data.

3. a clock-data synchronization circuit which synchronizes the data waveforms to the

28 Chapter 3 Current Steering DACs

IT IT 2B I 2I I
IT

Clocked elements (latches, or flip−flops)

B 2 1
Output: 2^T−1 bits
Binary to thermometer Clock Delay equalizer
decoder generator
Input: T bits

N B+1 B 2 1

Thermometer bits: from B+1 to N Binary bits: from 1 to B

Figure 3.3 A thermometer-binary segmented architecture.

clock with finer precision and conditions all data waveforms. It consists of a clock
generation circuit, a clock distribution network, and clocked elements.

4. the current switching network that is driven by the clocked elements.

5. the current source network where the currents are generated.

Segmentation is considered mainstream option nowadays. Opinions differ as to how

many bits should be assigned in each part. Initially, the binary to thermometer decoding
circuitry was the dominant issue [38, 50, 51]. The larger the thermometer part, the more
complex the logic-depth, the larger number of clocked elements, and the more difficult
it becomes to satisfy high data throughput with good data signal integrity, power and
substrate bounce constraints, timing, and power consumption demands. These issues
are also a strong function of the circuit styles used. Several articles [34, 37–39, 41, 50–
54] demonstrate the attention that has been given to these points. In [8] it is believed
that the main dynamic problems are all major carry related glitches, thus the number of
thermometer bits should be maximized to the level tolerated by area, power consumption
and complexity. Others [55] believe that the larger the thermometer part is, the more
difficult it becomes to satisfy the timing accuracy of the switch signals, therefore it should
not be maximized. In [42] the old-time-classic trust in re-sampling circuits is observed;
they are using segmentation only for DC matching issues.
3.1 Basic circuit 29

3.1.2 Current switching network and current sources

A current switch and a current source form together a switched current cell (SI). The
SI cells are to a great extent responsible for the performance of the DAC and occupy a
large portion of the area of the DAC. A conventional topology of an SI cell consists of a
cascoded current source configuration and a differential current switch (see fig. 3.1 and
3.2). The input of the cell is a low to medium swing differential signal and the output is a
differential current. Usually all cells share the same bias voltages. Dependent on the input
bit values the current is driven to one or the other side of the cell -thus the term current
steering. This makes the switching very fast because the large capacitances associated
with the current source terminals stay charged for most of the time. An extended list of
problems is associated with these cells, which are described very briefly in this section.
When a switch is turned on it connects a fixed impedance to the output node. When
it turns off its impedance becomes very large. The total output impedance is the parallel
combination of all switched-on cell impedances. Consequently, the output impedance is
modulated by the input signal and generates both static (INL [38]) as well as dynamic er-
rors (e.g, harmonic distortion [56]). A classical problem in a MOS switch implementation
is that the MOS transistor provides a parasitic capacitive path from the control terminal
to the output terminal (gate drain capacitance). When the switch is driven by a rapidly
changing signal, a charge is injected at the output node of the DAC. Another basic prob-
lem is that due to processing limitations the switches from different cells exhibit different
transient characteristics (e.g. timing skew). This leads to significant distortion. Finally,
the non linear I/V characteristic of switches causes on/off dynamic behavior asymmetry,
leading to spikes and non linear effects. Mismatch increases this problem.

3.1.3 Clock-data synchronization circuit

A clock-data synchronization circuitry makes re-timing and conditioning of the data wave-
forms carrying the bits. Because the resemblance and the shape of the waveforms reach-
ing the current switches is critical, this circuitry essentially transfers the information from
digital pulse waveforms of 0’s and 1’s to information contained in analog pulse signals,
in which signals issues such as distortion, gain, noise, pulse shape, timing are considered.
There are three main benefits of using this circuitry. First, the maximum conversion rate
is determined by the delay measured from the input data nodes of the DAC to the output.
Re-timing reduces this delay (pipelining). Second, it eliminates the unwanted variability
of the decoded data waveforms (time skew, different rise and fall times, and logic glitches)
introduced by different logic depths and wire interconnection lengths. Third, it adjusts the
waveform characteristics to the requirements of the current switches.
The clock-data synchronization circuit consists of

1. A global clock signal generator that generates a highly stable clock signal, with
which all clocked elements are to be synchronized.

2. Clocked data-storage and -conditioning elements that receive data and clock signals
and generate synchronized data pulses with the required shape.
30 Chapter 3 Current Steering DACs

3. Means of clock distribution and regeneration that delivers the clock signal to every
clocked element of the system in the correct format.

The three subparts have to be co-optimized together in the design phase because their re-
quirements affect each other. Many similarities exists with the clocking systems of mod-
ern high performance digital microprocessors, hence results of this area may be utilized.
The main characteristics of a DAC clocking system are:

1. Significantly smaller clocking network area than digital ICs, therefore smaller inter-
connection lengths and complexity, but problems like interference, cross-coupling,
charge feedthrough phenomena, parasitic capacitances, transmission line effects
have drastic impact on the analog output signal.

2. Small number of clocked devices (up to hundreds), but they dictate very small pro-
cessing parameter and temperature fluctuations. Increased sensitivity to the mis-
match in the shape and timing of individual pulses.

3. High operational speeds (up to GHz), however with maximum allowed clock un-
certainties in the order of one pico-second.

3.1.4 Auxiliary circuits

In the CS-DAC architecture there exist circuits that are placed in the signal flow and they
are vital for the processing of the signal components (latches, switches, decoder etc) and
circuits that are not in the signal flow, hence they are not as critical because they make
supplementary operations such as corrections, monitoring, etc.
Any supplementary circuitry that is placed in the signal flow has to face the penalty
of its location. In principle, latches are also auxiliary circuits. However, because their use
is obliged if any decent performance is to be obtained, they have been transformed into
constitutional circuits of the DAC architecture. Typical circuits that are not placed in the
signal flow are monitoring and calibration circuits. They are responsible for monitoring
and sensing some hidden signals and calibrating hardware such that the output signal is
correct.

3.2 Implementations and technology impact

Technological options for DAC realization consist of primarily GaAs CMOS, Bipolar
and BiCMOS. CMOS is today’s mainstream option to integrate the DAC as part of a
larger VLSI system. While CMOS was not initially the high speed option, the continuous
breeze coming from the rapid developments of integration technology brought CMOS in
a dominant position in the CS DAC landscape and conversion rates of 1+ GHz with more
than 10 bits of resolution have already been reached [39, 40]. A couple of examples of
high conversion rate DACs available in literature include GaAs [35, 36, 57], Si-Bipolar
[37, 50, 53], BiCMOS [55, 58–60], CMOS [8, 38–40, 43].
3.2 Implementations and technology impact 31

Non-CMOS implementations
The fast switching times offered by GaAs, Si-Bipolar and SiGe technologies offer signif-
icant advantages for high conversion rates. BiCMOS allows also partitioning of the DAC
in Bipolar and a CMOS parts in the same chip: digital operations and some non-critical
analog with CMOS and switching parts with BJT’s. The main circuit characteristics of
non-CMOS DACs aimed for high speed are:
1. Full differential current steering topology for every circuit in the signal flow. ECL
levels for input and clock, small swing in the rest of the circuits of the DAC [37].
2. Partitioning in a few thermometric bits (3-5) [34, 36, 37], or no partitioning at all
[35, 61, 62].
3. Decoder, if present, with a few alternatives (multi-level [50], row-column [37]).
4. Master-slave latches before the switches, latch buffers to filter switching noise of
the latches and condition the data properly. Low swing differential signals every-
where, and especially at the switches. This offers high crossing points in the com-
plementary switch control signals. Time multiplexing in the decoder or the latches
in some cases to increase data throughput [35, 50].
5. Speed optimized switched current cells. BJT cascoded resistors as current sources
of the thermometric part in Si-Bipolar DACs, transistors for GaAs, and R-2R lad-
ders for the binary part.
6. No output buffer, and direct connection of the current switches to the output node.
7. Re-sampling at the output in many occasions.
8. Multiple supply networks (analog, digital) to separate interference of digital switch-
ing noise in critical analog circuits.
9. DC accuracy achieved with inherent matching or post fabrication methods (e.g.
laser trimming).

CMOS implementations
CMOS CS DACs dominate (e.g. [38, 39, 41–43, 54, 63–68]) today the DAC landscape due
to their compatibility with digital processes. Their main characteristics (see fig. 3.4) are:
1. Single ended CMOS signal format for most circuits in the signal flow except from
the current cell. Single ended CMOS clock format.
2. Partitioning between a medium to large thermometer part (5 − 8) and a relatively
small binary part.
3. CMOS logic based decoder implemented with the row-column architecture [38] or
with alternative configurations [41].
32 Chapter 3 Current Steering DACs

R R

Vout

Vb2
Vb1

D T D1 φ BB B1
2 −1

Binary to thermometer Clock

Delay equalizer
decoder generator

N B+1 B 2 1

Figure 3.4 A conventional Current Steering CMOS DAC implementation.

4. Reduced swing CMOS logic, and single latch configuration implemented with
cross-coupled CMOS inverters. Also, reduced swing CMOS logic switch drivers to
tune the crossing point of the complementary switch control signals.
5. Differential current switches, and use of cascoding to increase the impedance of the
current sources, and transistor based current sources.
6. No output buffer, and direct connection of the current switches to the output node.
7. Re-sampling at the output in a few occasions.
8. Multiple supply networks (analog, digital) to separate interference of digital switch-
ing noise in critical analog circuits.
9. Calibration circuitry and switching sequences that deal with DC error correction.
At first sight, there are not that many differences in the circuitry between non-CMOS
and CMOS DACs. The main differences seem to be the larger number of thermome-
3.2 Implementations and technology impact 33

ter bits, calibration and switching sequences, single ended circuit logic, and single latch
configurations for CMOS, compared to small number of thermometer bits, no calibration
or switching sequences, full differential signals and circuit topologies, and master-slave
latch configurations for non-CMOS DACs. Apart for the DC error correction methods,
the remaining differences are mainly implications of technological differences, and as we
will explain shortly partially because of different application focus.
CMOS DACs appeared in the middle of the 80’s aiming for video applications (e.g
HDTV), and started dominating only after the beginning of 90’s. A representative differ-
ence in speed between several processes can be seen comparing CMOS and Si-Bipolar
DACs from [38] and [50] with 80 and 500 Msample/s, respectively (8 bits both). How-
ever, at the same time period CMOS DACs already started increasing significantly in con-
version rates (e.g. 400 Msample/s, 4 bit [51]) but for less bits. Applications such as arbi-
trary waveform generators for testing equipment were the main drive to build Gsample/s
DACs in GaAs with 12 bits such as the one found in [35], or later with the 14 bit GaAs
DAC [36] that reached rates up to 2 Gsample/s. A Si-Bipolar DAC reaching the same rate
at 10 bits was reported in [37]. Todays examples include a GaAs 12 bit 1.6 GSample/s
DAC [57] and a 15 bit 1.2 GSample/s [59] and a 6 bit 22 GSample/s [60] implemented
with SiGe BiCMOS process. Notice however, the cost in power consumption and area:
a total of 6 Watts and roughly 30 mm2 are used for the cause of obtaining exceptionally
good dynamic performance in [59]. For CMOS more than 1 Gsample/s was reached
in [39] for 10 bits, and in [40] for 14 bits.
One of the most important architectural aspects of the DAC was, and still is, the
segmentation to thermometer and binary bits, because it has a multi-dimensional impact
on several properties (linearity, matching requirements, complexity of design, area, power,
additional error mechanisms, etc.). Given this context, the reason of the different numbers
of thermometer bits used in CMOS and non-CMOS is easy to explain. The main aspect
of using non-CMOS processes was the need for large conversion rates. Neither low DC
errors due to mismatch [48], or low harmonic distortion -both become lower as the number
of thermometer bits increases- were significant requirements at that time. At the same
time, the main limitations for high speed (except the technology) and power was the
digital logic of the decoder, Therefore, it is not strange that non-CMOS DACs had few
numbers of thermometer bits, or none at all. Today, segmentation is exploited vigorously
for the potential it offers for high linearity, consequently high speed DACs do use large
number of thermometer bits.
Another difference between CMOS and non-CMOS is the use of calibration. Cali-
bration is a main option today for high resolution CMOS DACs making full use of the
digital processing advantages offered plentyfully by modern narrow length CMOS pro-
cesses. Interesting to note is that, while the turnover of the 80’s brought the first on-chip
calibration DAC [69] (off chip calibration was lazer trimming) reaching a static linearity
of 14 bits, still at the end of the same decade there were high resolution and high speed
DACs [35] using on chip switching functions and off-chip trimmable current sources, or
later [36] 1 − 2 Gsample/s 14 bit DACs with no more than 10 bits of static accuracy.
 4

Dynamic limitations of Current Steering DACs

I N this chapter, initially the state of the art of widebandwidth DACs will be presented.
Then the type of knowledge needed to realize widebandwidth high dynamic range
DACs will be described by comparison with existing knowledge on DACs with high sam-
pling rates and good low frequency linearity. This discussion will highlight the main
contribution of the remaining chapters of this book.

4.1 State of the art in dynamic linearity

In this section, the state of the art in widebandwidth high dynamic range DACs will be
presented and where and why CS DACs fail will be discussed.
Let us examine the maximum conversion (sampling) rate of reported high speed
DAC’s. The plot is given in fig. 4.1 (the data are given in appendix B). Some straight-
forward remarks can be made; for example, it is clear that some non-CMOS converters
have provided much higher sampling rates in their given year context (indicated by the
number next to each point). This is most likely due to the speed advantages offered by
these processes. Recent CMOS DACs have already exceeded 1 GHz conversion rate.
Since this plot says nothing about dynamic linearity at those frequencies the sampling
rates indicate, we also evaluate the magnitude of the “glitch” artifacts relatively to the LSB
level (see fig. 1.4(b)). This criterion defines that for a converter to comply dynamically
to its resolution level, the magnitude of all glitches should be confined within one LSB
value. With this criterion of dynamic linearity, significant knowledge has been developed
that links specific circuit limitations to the relevant glitches (e.g. the anomalies in the
middle of the sample to sample transients are not assumed to be a concern, but the glitches
in the beginning and end of the transition are), and also design methods were developed

35
36 Chapter 4 Dynamic limitations of Current Steering DACs

Figure 4.1 State of the art in sampling rate.

to tackle these problems. Data from literature and industry shows a gradual reduction on
the glitch level during the years (characterized by the so called glitch energy [7]) from
100 V psec at the beginning of the eighties to sub V psec levels at the end of the nineties.
When dynamic linearity was subsequently characterized with harmonic distortion,
many glitch related issues became obsolete. For example, for the glitch observed in the
middle of the pulse transition in fig. 1.4(b) because it appears at the clock frequency,
which is out of the band of interest, causes no problems. However, sample to sample
transition anomalies became important because they generate harmonic distortion.
To understand how the different meaning of the signal quality defines a completely
new learning curve on the problems and methods [35, 36] is cited as representative of
the transition phase to characterize the signal quality with frequency domain properties.
In [35] a 12 bit DAC (with 14 bit static accuracy) is reported at 1 Gsample/s sampling
rate which delivers a mere 52 dB Spurious Free Dynamic Range (SFDR) at just 1/10 of
the sampling rate (100 MHz), and 62 dB using an output sampler. In [36] despite the
1 − 2 Gsample/s rates offered by a 14 bit GaAs DAC, only 58 dB are obtained at 62 MHz
signal frequencies at a 0.75 Gsample/s rate. These results do not indicate badly designed
IC’s, but IC’s that were designed for a specific meaning of dynamic signal quality associ-
ated to a specific type of signals (step signals).
Next, representatice data of the period when signal quality is evaluated in the fre-
quency domain are presented (essentially after [55] a sound focus in spurious performance
is observed). The SFDR is here the relevant criterion. Each of the three plots in fig. 4.2,
4.1 State of the art in dynamic linearity 37

Figure 4.2 State of art SFDR at very low frequencies.

4.3 and 4.4) has on the horizontal axis the sampling rate and the vertical axis the SFDR:
each coordinate of a data point represents the SFDR of a reported IC and the sampling
rate in which it is reported. In each coordinate the resolution of the DAC is also noted.
For each plot the data correspond to a different normalized frequency, that is f / fs . In fig.
4.2 data for very low frequencies f / fs << 1/100 are shown. The second plot (fig. 4.3)
uses f / fs = 1/10. In this relative frequency the dynamic behavior of the DAC starts to
become important. The last plot in fig. 4.4 has points with f / fs = 1/3. Here, normally
the dynamic behavior of the IC dictates the SFDR. The literature sources are given in
appendix B.
Since many IC’s are evaluated for different rates, and other IC’s only for one rate and
very few points that cover a large bandwidth range some rules were applied for reliability
of conclusions. For those IC’s where plenty of points have been given for one sampling
rate the SFDR selection is straightforward. If many sampling rates and many frequency
points per sampling rate are available then we select the set of three SFDR points from a
sampling rate that the IC is designed for, and not one that pushes the IC to demonstrate
its maximum conversion rate, as in fig. 4.1. Finally, no data values were used from
curves resulting through interpolation of few specific points spanned very far way from
each other, and from points that are related to the f / fs = 1/4 and close to the Nyquist
frequencies. Lack of measurement points and interpolation may create false impression
about the true IC performance.
Let us focus now on the first plot ( f / fs < 1/100), i.e the constellation of all the
coordinates at very low frequencies. In this case the static accuracy of each IC sets the
38 Chapter 4 Dynamic limitations of Current Steering DACs

Figure 4.3 State of art SFDR with f = fs /10.

limitations in SFDR, because the frequency is so low that the inherent dynamics of the
DAC play minor role. Almost all of the data are above the 70 dB line independent of the
sampling rate, which can be as high as 1 GHz. We also see that the resolution does not
clearly separate the data in sub bands for 12 or more bits. Only a mild separation can be
seen. It seems that for more than 10 bits there is no clear advantage of having more than
12 bits SFDR-wise. An ideally quantized sinusoid exhibits third harmonic distortion at
9N dB below the fundamental [70] (N is the resolution). For example, a 9 bit ideal DAC
generates sinusoids with an ideal SFDR of 81 dB. A 12 bit DAC (ideally 108 dB SFDR)
with a static accuracy not far less than 12 bits is no wonder that it reaches more than 90 dB
SFDR [67] at low frequencies.
Considering the horizontal axis the conversion rates span from low to very high rates
with outstanding SFDR levels. Through the years (these data span within a decade) the
sampling rate has increased significantly showing clearly that it is well understood how
to make DACs with excellent low frequency linearity even at high sampling rates.
Next, the plot in fig. 4.3 is examined. It contains data from the same sampling rates
as in fig. 4.2 but at f / fs = 1/10. Strikingly the constellation has dived abruptly toward
lower SFDR values. The data seem to be divided in two main groups, one in the band
between 70 − 80 dB and one spreading below the 70 dB line. Again, there can be no
clear distinction on the basis of resolution. For example, in plot 4.2 all designs between
100 − 200 Msample/s were around the 85 dB level for very low frequencies, and with
an increase of 10 − 20 MHz only, most of them dropped by approximately 10 dB! The
results for f / fs = 1/3 seem even worse: very few data are above 70 dB, and mostly on
4.1 State of the art in dynamic linear ity 39

Figure 4.4 State of art SFDR with f = fs /3.

the low conversion rate area, whereas most of the data spread between 40 − 65 dB. In
reference to the classic issue of whether resampling at the output of the DAC helps in
eliminating the dynamic errors and facilitate good high frequency linearity, no general
statements will be made at this point since their use (such DACs are included) does not
separate them from the rest. Notice the large difference in the location of the constellation
in fig. 4.1 which showed the so called maximum conversion rate (which in fact has no
meaning except of showing the speed of the digital hardware of the DAC, because at
these operation conditions the signals are extremely distorted -thus meaningless), and the
location at fig 4.4 where the actual DAC high frequency linearity performance is shown.
The radical drop of spurious performance raises several questions. What makes the
very low frequency performance excellent even for very high conversion rates? Why does
the linearity drop so fast almost in all IC’s for almost any conversion rate and resolution?
Is in-depth knowledge about high frequency problems missing? Is DAC design method-
ology primarily focussed on low frequency design? Then again, why are some recent
designs seem to be the exceptions of the rule? In this section an attempt will be made to
formulate in detail a reasoning for those questions.
40 Chapter 4 Dynamic limitations of Current Steer ing DACs

4.2 Dynamic limitations of current steering DACs

Many generic electronic problems are pinpointed as dynamic performance limitations
(process mismatch, charge feedthrough, cross-talk, substrate and power supply noise),
and many specific manifestations of these problems have been discussed in literature in
the context of CS DACs. The most important are:

1. Process mismatch in the current sources [4] (amplitude side of mismatch).

2. Output resistance and capacitance modulation by the input signal [56].

3. The nonlinear V/I transfer function of the switch transistors which creates spikes in
the switch common source node [51, 55, 65, 71].

4. Charge feedthrough and injection phenomena from the switch control signals to the
output node, and from the common source node to the biasing nodes [54].

5. Relative timing imprecision (skew) and spread of the waveform characteristics of

the individual current pulses caused by clock skew, process mismatch in latches,
drivers and switches, unequal loading or interconnect lengths, transmission line
effects in the clock network, etc. [55, 70, 72, 73] (timing side of mismatch).

6. Power supply and ground bounce, substrate noise [37, 66].

7. Interference caused by feedthrough of data-dependent switching signals [36] on the
biasing nodes.

8. Clock or timing jitter [4].

9. Device noise [74].

Yet, although these problems are mentioned and some are analyzed properly, in overall
the picture is not clear. There exists a large difference between coarsely knowing that a
problem causes distortion and trying to solve it practically, and understanding the problem
in the details of its system, signal, circuit, and physical aspects, placing it in perspective of
other problems, verifying it experimentally and incorporating the crystallized knowledge
about it into design methodology. We will make a case on the limited existing knowledge
about the dynamic behavior of the DAC circuit considering the generic problem of mis-
match in a static and dynamic signal context, that is, points 1 and 5, respectively. The
discussion can be extended easily to other problems as well.
4.2 Dynamic limitations of current steering DACs 41

4.2.1 Matching and relative amplitude precision

A great number of articles that deal with analog circuit matching, and its impact on the
DC accuracy of CS DACs reveals that for the amplitude side of the mismatch problem
there is

1. clear distinction of the sources of current errors, and their properties (e.g. statistics
of process parameters), and knowledge of the physical mechanisms that translate to
individual current errors [75, 76];

2. precise knowledge of how the current errors are translated to static signal errors
(e.g. INL) or dynamic signal errors (harmonic distortion [56]);

3. design methodology based 1 and 2, which spans from the device level (e.g. current
source partitioning in subunits [77]), in the circuit level (trimming and calibration
[4], combinations of biasing and sizing [54]) up to the signal level (e.g. partitioning
of the code [48], switching sequences [41] and Dynamic Element Matching (DEM)
[4]);

4. clear distinction of mismatch current errors vs. other static accuracy errors (e.g.
output resistance [38]) based on their error generation mechanisms, and knowledge
of the interdependence of these problems via common design parameters (dimen-
sions of current sources, switches, etc.).

For example, amplitude mismatch current errors have been subdivided in determin-
istic and random; process gradients cause spatial deterministic errors, and short distance
mismatch causes spatial random errors). These subclasses distinguish the signal errors
(INL) on the way they scale when a specific physical parameter (dimension of transistors)
changes. If the current source transistor size is increased, the random components of mis-
match drop and the systematic increase. For every extra bit of accuracy required, the area
must increase by a factor of four to reduce the random errors, but the deterministic errors
scale up similarly [76]. Quantitative comparisons show that if one reduces random er-
rors for more than 10 bits of accuracy by sizing and biasing the current source transistors
properly, then the deterministic errors increase the INL and set the limitation.
This limitation called for the exploration of other degrees of freedom, and brought
correction methods that apply orthogonally to the two subclasses in different hierarchical
levels. One can increase the size of each current source to reduce the random matching
components, and reduce the deterministic components using the redundancy of the ther-
mometer code to employ techniques called switching sequences. Using this approach the
next limit (12 − 14 bit) in accuracy is set by the magnitude of the area that is required
to limit the random matching errors. This new limitation asks again for other solutions;
for example, hardware calibration pushed a few bits further this limit of static accuracy
breaking also the relationship between dimensions of current sources and current errors.
If now one combines the advances in processing technology and the wide adoption of
well structured knowledge, it is easy to understand why the constellation of the points in
fig. 4.2 is so high up in the SFDR scale.
42 Chapter 4 Dynamic limitations of Current Steer ing DACs

4.2.2 Matching and relative timing precision

Let us now turn our focus on switching characteristics due to mismatch. Literature shows
that the problem is well known to generate distortion, but it is nowhere explained how this
happens, and how the physical origins of the problem are translated layer by layer to the
signal at the output, or how the signal errors depend on the input signal properties. There
are many contributors (clock networks, latches, buffers, current switches, etc.) and several
physical origins that are weighted differently in these different elements, bit there is no
knowledge about the relative significance of each factor, and how it should be addressed
in a consistent and methodological way similarly to the amplitude mismatch. The most
characteristic example of coarse characterization of this dynamic problem is the link be-
tween glitches and distortion so strongly rooted into CS DACs: any overshoot like shape
in the output signal is a glitch, and all glitches somehow cause dynamic “non-linearities”;
consequently, all problems that create glitches cause distortion in a similar way.1
Limited knowledge here is strictly meant for

1. the vertical modulation mechanisms: how process spread is translated to the signal
components in the DACs algorithmic architecture embodying representative prop-
erties of the physical, electronic and circuit sides of the problem;

2. the horizontal modulation mechanisms: how the signal components resulting from
the vertical modulation mechanisms are mixed into the signal modulation flow,
which describes how the output signal is generated for the given input signal.

Let us compare now the timing with the amplitude side of mismatch In [8] the au-
thors discussed qualitatively the relationship of one particular type of mismatch based
switching problem (MSB/LSB glitches) in relation with the thermometer coding of the
DAC.2 Remember that the larger the thermometer part of a segmented DAC the smaller
this problem becomes. Then this problem was compared to the amplitude mismatch in
the way the relevant quality figures (INL and DNL for the amplitude problem, THD for
the timing problem) vary as a function of the number of thermometer bits. The number
of thermometer bits was also linked to chip area (digital decoding logic, interconnection
and latches increase by a factor of 2 per extra bit). The result was a co-optimization of the
number of thermometer bits against these three issues. The suggestion was to maximize
the thermometer bits to the limit imposed by area. However,

1. amplitude mismatch was evaluated for a static signal (thus, INL) and MSB/LSB
glitches are for a dynamic signal (THD);

2. because only one problem is evaluated dynamically and both amplitude and timing
problems reduce with more thermometer bits, there was no need to have a quanti-
tative description of the signal error (THD) for the timing problem;
1 This
is an ill heritage of the characterization of dynamic performance with glitch levels.
2 Therelationship between THD (signal) and the MSB/LSB glitches in [8] is qualitatively described by a
linear increase in THD with the number of thermometer bits.
4.2 Dynamic limitations of current steering DACs 43

What now if we want to include additional problems? How can we compare two mis-
match related switching problems, or one mismatch related with another different prob-
lem, both of which depend on the same architectural parameters in an opposing manner?
For example, consider the addition of the two following problems:

1. Timing mismatch problems in the thermometer part. The more the thermometer
bits, the larger the timing errors can be, although the errors possibly average better.

2. Power supply and substrate noise problems: the larger the number of thermometer
bits, the larger the number of digital gates and latches switching as well, hence
power supply and substrate noise related problems may scale up roughly by a factor
of 2 per extra bit.

Unless these problems are translated adequately precise to the signal (e.g. THD, SFDR)
and validated by experiments, all we may speak of is about comparisons and conclusions
dependent in the context of specific designs. In practice, comparisons of such type are
very difficult to make for there are many reasons that contribute to timing errors, and the
interpretation is most of the times very subjective.
Some clarifications with respect to the point made in [29,78] concerning the suitability
of the SC DACs for high frequency linearity at high conversion rates. It is advocated that
an SC DAC is more suitable because it does not exhibit very rapid performance degrada-
tion with frequency. However, a more careful look in the cited article of [8] shows no solid
background for these arguments, because, first, the performance reported in [8] counter-
argues the rapid degradation claimed in [29, 78], and second and more importantly, the
advantages claimed for the SC DAC are basically achieved by the resampling nature of
this architecture, and not by the SC implementation. In this sense, there is no difference
to speak of a SC charge bisect DAC as in [78] or a CS DAC; the key issue is whether
or not to use resampling. This issue was raised once more in [42, 72] and more recently
in [57, 59] that reaffirm the traditional believe in resampling at the output signal of the
DAC to improve high frequency linearity. However, despite this is often promoted as a
fundamental solution, in fact there is no sufficient reasoning to believe so, rather there ex-
ist more reasons to support that high conversion rates and high frequency linearity come
only at the absence of resampling. Recent high speed designs [8, 40, 43, 68] support this.
Finally, while we speak here of sinusoidal linearity, consider that there is already an
ongoing process toward systems that employ DACs to process broadband signals (e.g.
for QAM or similar modulation schemes) with random and deterministic components.
This means that the knowledge that we may develop to design DACs with better sinu-
soidal linearity may be less relevant if it is only meant for these signals. Therefore the
knowledge of the dynamic behavior of this circuit has to be related to more generic signal
properties such as correlation, power, probability distributions, etc. from the beginning
of any analysis. Then a generic signal can become a specific signal when certain system-,
or application-specific assumptions are made without re-defining from the beginning the
theory about the circuit behavior of the DAC.
In summary, the surgical precision with which the multi-dimensionality of the ampli-
tude side of mismatch in DACs has been examined and understood is by no means com-
44 Chapter 4 Dynamic limitations of Current Steer ing DACs

parable to the coarse knowledge available about the timing side of it. Generally speaking,
the static signal accuracy problems have been investigated and understood in much more
depth and broadness than the dynamic ones; there is absence of mature knowledge on how
to deal with dynamic problems in general. This is the major reason that the constellation
points fig. 4.1 and 4.4 drop so rapidly.

4.3 Conclusions
A review of the state of the art in the high frequency linearity of DACs has been presented.
It was discussed that by changing meaning on what we call signal quality, the meaning
on what we consider as signal errors for high frequencies changes as well. This new
meaning of quality dictates that our knowledge and designs methods have to be updated
accordingly. Such a dynamic process has a certain amount of inertia as many things in
nature. The following conclusions reflect the qualitative characteristics of this process:

There is rapid performance degradation as frequency scales up. There are always a
few exceptions to the rule, which makes its very interesting to figure out why.

The dynamic behavior of the CS DAC has not been investigated in the same depth
and broadness as static behavior. There seems to be a lack of detailed description
on how several dynamic problems cause errors at the signal. This requires the
description and identification of the error generating mechanisms of each problem.

Some problems in particular lack analysis (e.g. timing side of mismatch, power
supply and substrate noise). Their importance and the underlying physical causes
are known but the particular mechanisms of signal error generation are unknown.
For those problems there is no preventive design methodology.

The impact and the nature of dynamic problems has not been placed in perspective
of generic signal properties and also to technology scaling.
 5

Current Steering DAC circuit error analysis

T HE potential for a Current Steering Digital to Analog Converter to achieve high

speed operation is unfortunately matched with a similar potential to exhibit non-
linear behavior. In this chapter the main problems, their nature and the signal errors they
cause are investigated. Via the detailed explanation of the way errors are generated, some
important properties will be recorded to prepare for the classification that follows in the
next chapters. A coarse separation is made between amplitude and time domain errors.
Time domain errors are the most relevant for high frequency linearity.

5.1 Amplitude domain errors

The problems presented in this section are easily characterized by an input-output transfer
function neglecting the inherent dynamics of the DAC operation. This proves convenient
for analytical calculations. Their impact is constant with frequency and conversion rate.

5.1.1 Relative amplitude inaccuracies

An ideal DAC consists of 2N identical current sources grouped in ways defined by its
coding. In practice, the current sources have amplitudes that are slightly different rela-
tively to each other. The main physical origin of this problem is mismatch in the process
parameters occurring at the manufacturing phase of an IC.
Mismatch is the process that causes time-independent random variations in physical
quantities (e.g. currents) of identically designed devices [75]. The variations are the result
of many physical factors occurring in the fabrication phase. Typical physical causes are
oxide thickness variations, metal coverage, edge effects, etc. In fig. 5.1 two MOS cur-
rent sources with identical biasing conditions are shown. The mismatch of two identical
45
46 Chapter 5 Current Steering DACcircuit error analysis

I+ ∆ I
I+ ∆ I 1 I+ ∆ I 2

I ∆I Vb
mismatch
error

(a) (b)

Figure 5.1 (a) A unit current source with mismatch and (b) MOS current
sources with mismatch.

transistors with zero source-bulk potential difference is modeled by differences in their

threshold voltages Vth and their current factors β according to [75]

AV2th ∆β A2β
σ 2 (∆Vth ) = + SV2th D2 , and σ 2 ( )= + Sβ2 D2 (5.1)
WL β WL

where AVth , Aβ , SVth , Sβ are process parameters, D is the distance separating the transistors
and W, L are their geometrical dimensions. The mismatch consists of a short and a long
distance term [75]. The short distance term represents a spatially random process with
normal distribution and zero mean with short correlation distance (much smaller than the
transistor dimensions). The long distance term has deterministic origin but under some
assumptions it is modeled as a stochastic process with long correlation distance. Because
the current source array transistors are spread over a large area deterministic current errors
develop. Some of these are process related, others are caused by spatial deviations of the
biasing voltages across transistor arrays (resistive drops in the ground wires [38]), or by
environmental parameter variations (temperature), piezoelectric phenomena [76], etc).
The spatial properties of the physical causes are translated to unit current errors with
have similar properties. The exact way this translation is made is determined by the
device laws of operation. Notice also that the variations in each individual current source
are static (except of course from their possible variations due to aging). Consequently, we
may talk of an amplitude domain problem with static spatially random and deterministic
local character. The current output can be described by

1 k=w
I(w) = w · I + ∆I(w) = w(I + ∑ ∆Ik ) = wInorm (w)
w k=1

where w has its usual meaning, and ∆Ik are the unit errors of each current source when the
gain and offset components are removed. The error for a given input value is the sum of
all unit errors of the current sources employed to create the corresponding output value.
Alternatively, the normalized amplitude Inorm (w) for a given input value w is the average
value of all unit currents selected. This means that the averaging principle lies behind
this error mechanism. When mismatch is assumed Gaussian and uncorrelated, then for an
5.1 Amplitude domain errors 47

N bit binary DAC consisting of N weighted sources, each one consisting of 2k elements
(k ∈ {0, ..., N − 1}), the SNDR for a full scale sinusoidal signal is approximated with [56]
SNDR ≈ 6N + 1.76 − 10 log(1 + 6σ∆I/I
2
2N ) (5.2)

where σ∆I/I is the spread of the normalized current source error (∆I/I) . As the resolution
increases, the mismatch gradually reduces the 6 dB/bit ideal benefit to 3 dB/bit.
Notice that the SNDR does not depend on any time domain parameters, hence it is
signal frequency and conversion rate independent. In addition, because of averaging, the
impact on the SNDR is soft and not relevant for high frequencies, unless mismatch is very
large. For example, for a relative accuracy of 1% and 10 bits resolution the SNDR is ≈ 60
dB (in comparison, it is 61.76 dB for an ideal 10 bit DAC), while for 5% the SNDR drops
to 49.6 dB. For deterministic errors (e.g. gradients) other calculations are required.
As a final remark, the current errors are related to the same geometrical parameters
(width and length of devices, distance between each current source, etc.) but not neces-
sarily in the same manner. For example, in an array of MOS current sources when the
unit device geometry is increased to reduce the random current source errors, the area and
the systematic mismatch errors increase, and an optimization problem appears.

5.1.2 Output resistance modulation

DAC output resistance

RL
resistance

Vout slope Ru
Ru /w

wIu

input value

Figure 5.2 The modulation of the output resistance by the input sample value.

The output resistance of the DAC is a function of the number of switched-on cells,
therefore it is modulated by the input signal. A simple model of the DAC with the unit
resistances is shown in fig. 5.2. The input value w determines the number of switches that
are switched on, thus the resistance seen at the output node. As a result, there will be a
current loss in the parallel combination of w unit resistors Ru that depends on the input
values. The current error as a function of the input is given by [56]
ρw
∆I = (Iu w −Vdd /RL ) (5.3)
1 + ρw
where ρ = RL /Ru is the ratio of the external load resistance and the unit current source
resistance. The maximum static error should not correspond to an error larger than one
48 Chapter 5 Current Steering DAC circuit error analysis

LSB [38]. If w is a time varying signal, then the error is modulated by the signal and
creates harmonic distortion. The SFDR is

1    2
SFDR = 1 + N −1 1 + 1 + 2N ρ (5.4)
ρ2

and it is determined by the second order component (HD2).

5.2 Time domain errors

For these type of errors we may speak of a transfer function between the normalized pulse
shape and the input value, or the timing of the pulse and the input value. In comparison
with the amplitude domain errors, time domain errors are dominant at high frequencies:
the signal errors scales up as the frequency and conversion rate increase, but not in the
same way for each error.

5.2.1 Nonlinear settling and output impedance modulation

The output resistance of the DAC is a function of the input signal values. Therefore, for a
fixed output load capacitance, the time constant of the output pulses is modulated by the
input signal. In addition, the DAC output has itself also a capacitive nature due to the SI
cells. Its effect are much stronger that of the resistance.

DAC output capacitance

RL
capacitance

Vout slope C u
wCu+CT
Ru /w

wIu CL

input value

Figure 5.3 The modulation of the output capacitance by the input sample
value.

Let us assume a thermometer DAC, and also that the output impedance of each SI
cell is given by the parallel combination of a resistor and a capacitor. When the switch is
off, the resistance in infinite, and the unit capacitance equals Co f f . If the switch turns on,
the resistance is Ru and the capacitance Con . The unit capacitance Cu = Con −Co f f is the
difference in capacitance between the switched on and switched off phase of the cell. A
simple model is shown in fig. 5.3. The total output capacitance is written as

Cout = CL +Cu w +CT (5.5)

5.2 Time domain errors 49

where CT = (2N − 1)Co f f and CL are capacitances independent of the input signal. As
a result, rise/fall times for sample to sample transitions will be modulated by the input
signal.
In practice, Ru is relatively large and the time constant variations are dominated by
the capacitance modulation. Then time constant can be approximated by

τ (w) = CL RL + RLCu w = τu w + τ0 (5.6)

This says that for every additional SI cell that is switched on, the time constant increases
by τu . For example, for a 7 bit thermometer DAC with Cu = 1 f F with RL = 25 Ω, for
every SI cell switched on the time constant increases by τu = 25 f sec. A signal transient
at the output that represents one LSB step from w = 0 to w = 1 (all SI cells off, and then
one turns on) has 3.15 psec time constant difference compared to the same transient from
w = 126 to w = 127. Therefore, as the input signal varies, the normalized pulse shape at
the output becomes less or more steep accordingly.
Let us observe now the characteristics of this error mechanism. It is generated via the
interaction (coupling) of the SI cells via a common -global- node of the DAC. The param-
eter modulated by the signal is a time constant τ (w), which is a time-domain parameter
that characterizes the pulse shape. The modulated parameter modulates back the DAC
signal generation mechanism by modifying the pulse shape per transition, consequently
the error. The actual error per pulse is an integral of the error over the pulse duration Ts .
This mechanism has been analyzed in [79] with a Pulse Width Modulation (PWM)
method after translating the integrated error per pulse to a time delay. It is known in
modulation theory [80] that a pulse train PWM modulated by a deterministic function
generates Bessel components at the output spectrum that can be calculated analytically.
For every input signal frequency tone an infinite number of components rise at its spec-
tral sides. The frequency location of the components depends on the frequencies of the
signal, the frequencies contained in the modulating parameter, and the carrier of the pulse
train (the sampling frequency); the modulation parameter τ (w) contains the input signal
frequencies because it depends on w, consequently, for a single discrete sinusoidal sig-
nal w(m), harmonic products (second, third, etc.) are generated. Using the samples of
an ideal full scale sinusoid A + Asin(2π f1t), where A = 2N −1 , the amplitude of the n-th
order harmonic component is [79]

sin (π f1 nTs )
Dn = 2N −1 Jn−1 2π f1 (τu 2N −1 ) (5.7)

  (π f1 nTs )
harmonic amplitude

 
sinc(x) filtering

where the function Jp (x) defines the Bessel function of the first kind, and N is the number
of bits. The sin(x)/x filtering effect due to the rectangular pulse shape is clearly distin-
guished from the harmonic’s amplitude.
The amplitude of the Bessel products depends nonlinearly with the product order, with
the magnitude of τ (w) -thus on τu and the signal amplitude A-, and with the frequency of
the signal w. For the second order product the distortion increases with 20 dB/dec, for the
50 Chapter 5 Current Steering DAC circuit error analysis

third with 40 dB/dec, etc. The ratio of the fundamental to distortion components (rms) is

D1,rms A sin(π f1 Ts ) 1
SDRn = =√ (5.8)
Dn,rms 2 (π f1 Ts ) Dn,rms
If the fundamental f1 is much lower than fs , the sinc roll-off dissapears and the bessel
function simplifies. For example, the fundamental tone is D1 ≈ A, and D2 ≈ 2Aπ f1 τu .
Consider the previous example with fs = 1 Gsample/s (Ts = 1 nsec), tu = 25 f sec and
N = 7. The SDR for the second, third and fourth order harmonic products are given in fig.
5.4. A pair of curves is plotted for each one. The one with the notch contains the pulse
sinc filtering, which annihilate the distortion tone located at fs /2 (Nyquist frequency). For
example, the third order tone reaches fs /2 when the fundamental is at fs /6. The straight
line is the result neglecting the pulse nature of the output signal. The (SDR2 ) equals 86 dB
for a input signal of 20 MHz and 66 dB at 100 MHz while the SDR3 is much smaller but
it drops much faster with the frequency (40 dB/dec) and with τu (12 dB/oct).

250

60 dB/dec SDR
4

200
signal to distortion ratio (dB)

SDR3 40 dB/dec

150

SDR2
100 20 dB/dec

50 0 1 2 3
10 10 10 10
frequency (MHz)

Figure 5.4 Signal to distortion ratio in dB due to the time constant modulation.

Another aspect of the problem discussed in literature is the combination of the ampli-
tude losses introduced by the modulated output impedance (as in section 5.1.2) and the
frequency dependency of the impedance [81]. The implicit assumption made is that the
sample to sample transient can be neglected. Then it is assumed that the output impedance
Zu causes amplitude errors. The resulting AM problem is solved in a similar manner to the
5.2 Time domain errors 51

case in section 5.1.2, and the relationship between the distortion and the unit impedance
value Zu is formulated once more. Until this point the harmonic products do not depend
on frequency. Next, the authors make an AC analysis to see how the SI cell impedance
Zu ( f ) scales down with frequency, and then they combine this result to scale down the
SFDR accordingly, because the SFDR depends on Zu . The relation to transistor circuit
aspects comes via the AC analysis; to reach a signal bandwidth the SI cell should be de-
signed such that its AC impedance at this bandwidth equals the requirements imposed by
the AM analysis. For example, in a 12 bit DAC an SFDR of 72 dB requires an LSB SI
cell (4095 in total) output impedance of 100 MΩ over the complete Nyquist band.
In conclusion, the modulation of the output resistance and capacitance values, and the
limitation to provide high resistance and low capacitance values brings up a significant
high frequency linearity limit as well. However, because the second order distortion dom-
inates the total error, there is a large difference on whether we speak of single ended or
differential output signals. The use of differential signals reduces the errors significantly,
however it does not eliminate them.

5.2.2 Asymmetrical switching

Vdd

VA VA VB
VB
Vx Vx Vx Vx
V dd

C C C C

V ss

switching switching constant

Figure 5.5 Impact of the nonlinear MOS V/I transfer function in switching.

The non-linear V/I nature of a MOS switch generates a couple of problems at the
switching behavior of differential current switches (fig. 5.5). As the switch control signal
(in the MOS gate) makes a transient from a one voltage level to the other, the switch re-
sponds according to its V/I characteristic. This results in switching-on and switching-off
asymmetrical behavior. The transistor that turns on reaches different regions of operation
in different times compared to its complementary (turning off) transistor. Driven by com-
plementary signals, when the current is steered from one side to the other both switches
will not be conducting for a short period and cause two problems.
The first problem is that the current source is choked for a brief period and node X
discharges abruptly with steep transients (spikes) as shown in fig. 5.5. This forces the
current source to re-charge node X as soon as one of the two switches turns on, instead of
52 Chapter 5 Current Steering DAC circuit error analysis

delivering current to the output node. Consequently, the current spike is prolonged until C
is recharged. In this problem a unit DAC cell contributes to the total output spike only if
it is switching, and in proportion to its weight. If all cells are identical (e.g. thermometer
DAC), then all contribute the same. If node VX drops significantly, the cascode transistor
and the current source will go out of saturation causing extra problems. Some further
discussion follows for this problem and then only the second problem is examined.
Vdd

Vb2

Vb1

switching switching constant

Figure 5.6 Biasing node disturbances due to transients on individual nodes X.

The total glitch at the output signal for the first problem is contributed only by the
switching cells; that is, each switching cell delivers at the output a current pulse with a
glitch independently from the other switching cells. Then all pulses with unit glitches
are summed. After the transition the spiky transient dies and the pulse settles to its DC
value, while all the cells that have remained on from previous sample values have no
influence on the situation. This is shown in fig. 5.5 where dashed arrows indicate which
cells contribute to the output and which don’t. In a thermometer DAC the same pulse
shape appears every time cells are switching, and the ratio of the glitch to the sample
difference (w(m) − w(m − 1)) is always the same because cells are only switching on, or
off. Therefore, the normalized pulse always stays independent of the input signal and
it will not create a non-linear behavior. In a binary DAC the reduced pulse becomes
dependent on the binary value at the input, which creates a non linear relationship of the
reduced pulse and the binary input code, thus introducing distortion.
Let us examine now the second problem. This is the result of the first but it has a
stronger non linear nature. In this case, it will show nonlinearity to the thermometer
DACs as well. Figure 5.6 shows the mechanism of the error. The transient at node X
infiltrates in the cascode transistor biasing node (via parasitic gate drain capacitance), and
in the current source bias node; this develops transients on the biasing voltages Vb1 and Vb3
that are correlated to the number of cells switching and their weighting factor. Then, the
currents of all current cells are affected in the same way (see fig. 5.6)); all cells introduce
spikes, and each unit spike of each cell is proportional to the number of switching cells.
5.2 Time domain errors 53

The disturbances at the bias node are the result of the collective transients of all individual
VX nodes. As they constitute an excitation by an internal signal, we will call this hidden
signal excitation. Furthermore, the bias voltage operates as a parameter of the SI cells
and controls their amplitude values. Therefore, the transients modulate the parameter
bias voltage, and because this parameter is global -that is common to all SI cells- the
modulation reflects back to the responses of all currents of all SI cells independent of
whether they are switching or not.
Even if the biasing nodes have many transistors connected and possibly decoupling
capacitance, hence a large total capacitance, this problem is not easily eliminated, and es-
pecially the low frequency harmonic content is then left on the biasing nodes. This modu-
lation brings memory effects, in the sense that the amplitudes of all currents are modulated
by older and current sample transitions. This effect and the thermometer/binary one adds
to the non-linear nature of this problem. Therefore there is talk of a global signal depen-
dent dynamic problem with a deterministic nature. The errors introduced by this problem
are not coming from individual contributions of each SI cell, but they are generated by
their interaction via a common global node, which carries a signal that is parametric to
the behavior of the cells. Observe that if each cell is biased independently from the rest,
then nature of the second problem becomes similar to the first.
The first problem is a very well considered problem in literature [40, 49, 54, 55, 65, 66,
82]. If it is not taken into consideration it will give a serious limitation in distortion but
also in speed reduction [35, 76]). The second problem was briefly mentioned in [36] and
only very recently we have seen a couple of articles that take it into account [42, 43].

5.2.3 Modulation of switching behavior

The next problem discussed has similarities with the second problem described in the
previous section; it results also from the interaction of the SI cells via a common node.
The switching behavior of current and voltage switches can be modulated by the sig-
nals that pass from one terminal of a switch to the other, and by the parametric input
signals that they required for proper operation. In a voltage sampling switch the typical
problem is that the signal to be sampled modulates the switch on resistance, the sampling
moments, and the charge injected by the clock [7]. In current switches as they are used
in the DAC similar effects can take place primarily with the modulation of the voltage
difference between the substrate and source terminal by the signal via the body-effect.
Consider the situation shown in fig. 5.7. M2 is on and M1 is off. The rest of the cells
synthesize a sinusoid by proper combination of pulses. Then the upper node of M1 and
M2 varies in accordance to the signal -usually between a few mV and 1 V. Because M2
is not ideal and can not ultimately shield the node X , a smaller fraction of the sinusoid
appears in VX . For example there may be a difference of 10 − 50 mV in VX between
points A and B for a full scale sinusoid of 0.5 V . Consequently, due to the back-gate
modulation the switching behavior of a pair of current switches varies according to the
input signal amplitude. In fact, all switch transistors of the cells that switch from a sample
to another sample are affected in the same way by a function of the input signal, thus all
of them behave differently for different transitions; input signal dependent normalized
54 Chapter 5 Current Steer ing DAC circuit error analysis

output pulses is a natural consequence. Had it been not for the variation in the drain of the
switches, their source potential would be stable and this problem would not exist. This
problem has been briefly discussed in [43, 83].
A
Vdd
All V x nodes in all
cells have the same
fluctuations!

M1 M2 A
B
A
Vx
B
B

2^N−1 switched current cells

Figure 5.7 Modulation of the switching behavior of all current switches.

It is obvious that this problem originates also from the interaction of cells via a global
node -the output node. The signal responsible for the subsequent modulation represents
the actual response of the DAC, and it modulates the dynamic behavior of the switch-
ing devices, all in the same way dependent on the code value of the input signal. It can
be called a signal-dependent dynamic problem with deterministic nature. There are ad-
ditional physical origins that can cause a similar modulation problems in the switching
behavior of the switches (e.g. substrate noise). In such a case, the problem can have a lo-
cal character as well, meaning that some cells may have different modulation than others
dependent on their location on the chip.

5.2.4 Charge feedthrough and injection

Charge feedthrough and charge injection are general problems on all switched current
and switch capacitor circuits [7,84–88]. The charge injection problem originates from the
generation and dissolution of the conductive channel beneath under the gate of the MOS
device when the transistor is in the on state. Charge feedthrough is related to the parasitic
coupling between gate and drain of the MOS switch and appears during both switching on
and off phases. The problem is that the charge burst during the switching phase results in
a voltage error in the affected nodes proportionally to the node’s impedance. The charge
is a function of the size of the switch devices (size relates to capacitance), the switch
driving signal slope and swing [84, 89], and of course on several technological issues.
These problems appear mainly at the current switches of the CS DAC.
Fig. 5.8 shows the way charge feedthrough is created via the gate-drain and gate-
source overlap capacitances. During the switching transient of the switch control signal,
charge passes from the switch control node to the output node of the DAC via the parasitic
5.2 Time domain errors 55

CH
VH q
switch
control
signal G

VL q

Figure 5.8 Charge injection phenomena in a MOS switch.

gate drain capacitance Cgd = WCov , where Cov is the overlap capacitance per unit width,
and W is the width of the MOS device of the switch. The charge that is injected to the
output node is approximately q = VswiWCov with Vswi = VH −VL . If it is assumed that the
charge is injected momentarily at the output, it translates to a voltage that equals1
WCov
∆V = Vswi (5.9)
WCov +CH
In a differential switch, a data transition results in charge feedthrough (injected in from
the left node to the output, absorbed from the right node to the gate of the switch) which
dies gradually since the output nodes of the switches have a low resistance ≈ RL .
Assume now a thermometer DAC with M = 2N − 1 pairs of identical switches con-
nected in parallel. The total injected/absorbed charge is roughly equal to the number of
switching cells times the charge injected per cell which is signal independent. For each
cell, charge is only injected or absorbed, because switches are either switched on or off,
but not both. Consequently, the output charge burst does not seem harmful at first sight
because it seems to be linearly related to the sample to sample transitions. For a binary
DAC the charge depends on the switching activity of size-weighted switches. During ma-
jor carry transitions the MSB switch may inject (absorb) charge while the rest switches
absorb (inject) unequally weighted amounts of charge. Therefore, for some specific LSB
transitions at the input, the generated charge burst at the output is considerably different
than the rest of the transitions, thereby establishing a non-linear transfer function between
output charge burst and input sample transition. The impact of the charge is also influ-
enced by the impedance at the output. The charge injected to one of two outputs during
each LSB step transition is the same for all possible LSB transitions (thermometer cod-
ing). However, the impedance in the output depends on the initial code from which the
step is launched. For example, as one by one the thermometer cells are switching on
(00...00 → 00...01 → 00...11 → 01...11, etc.) more capacitance is added to the single
ended terminal, and the spike smoothens gradually. For a differential output as one output
increases in capacitance, the other decreases, thereby the spike becomes steeper.
Channel charge injection is similar with charge feedthrough in the way it depends
with coding when one excludes its dependency via the body effect (similarly to the asym-
1 Care must be taken with eq. (5.9). The total charge q will indeed cause such a voltage difference had it been

for a purely capacitive load at the switch drain, or if it was delivered momentarily. This rough approximation
is used here only to highlight the primary dependencies of the voltage spike at the output. For more accurate
evaluations additional effects should be considered [84, 87].
56 Chapter 5 Current Steer ing DAC circuit error analysis

Vdd

I_A I_B

VA VB

2^N−1 switched current cells

Figure 5.9 Charge feedthrough in a CS DAC.

metrical switching problems). The channel can be approximated with

Qch = W LCox (VGS −Vth ) (5.10)

where W and L are the width and the effective channel length of the MOS transistor,
respectively, VGS is the voltage difference between gate and source terminals, and Vth is
the threshold voltage of the transistor. Usually it is assumed that the channel charge splits
in two equal parts directed toward the drain and source. The charge reaching the output
can have a dependency with the input code via the body effect.
Therefore, there exist two different charge feedthrough error mechanisms. In the first,
the error is the contribution of each SI cell individually to the common node. This con-
tribution is related nonlinearly to the signal only via the coding of the DAC. The sec-
ond mechanism occurs via an intermediate parameters. In the first case, it appears via
the charge to voltage translation at the global output node; the relevant parameter -the
impedance- is modulated, thus the voltage errors are modulated as well. In the second
case, the common parameter is the substrate potential, which modifies the channel charge
of all SI cells. Local differences may be added on top of these mechanisms.
In DAC literature, charge injection is mentioned consistently as an issue [39, 40, 49,
53, 54, 65, 82, 90]. There exist several techniques to reduce the effects of charge injection
and charge feedthrough, which will be discussed in chapter 11.

5.2.5 Relative timing inaccuracies

The individual transitions of the SI cells are widely different in their switching charac-
teristics (delay, rise and fall times etc) [35, 37, 39, 50, 55, 70, 72, 78]. In the early days
of CS DACs variations in individual pulses were caused by non clocked decoding logic.
In modern DACs this problem is easy to solve using clocked elements, e.g. latches or
flip-flops. The focus here is on the issues beyond this problem. The sources of timing
inaccuracies are tracked down to the clock signal distribution network, the clocked units,
the drivers and the switches.
5.2 Time domain errors 57

A clock signal is supposed to reach many locations in the DAC chip simultaneously.
These locations are usually the input nodes of the clocked memory elements (latches,
flips-flops). The difference in clock arrival time between two points at different locations
in the chip is called clock skew. In the most extreme case, clock skew may cause func-
tional errors but it usually limits the performance of the DAC long before this point. Not
only different arrival times may be hazardous, but also variations of the shape of the local
clock signals may trigger the clocked elements such that they have different responses.
Clock skew can be the result of:

mismatch in geometrical characteristics of interconnecting wires (process mismatch

of their dimensions, layout complexity that forces unequal wire lengths, etc.);

imperfect balancing of interconnecting wire loading, reflections, etc.;

process variations that affect clock regeneration circuitry at the various locations
where the clock signal is distributed and regenerated locally;

power/ground supply variations that are different in different locations where clock
(re)generation circuitry operates.

crosstalk of clock lines with other lines that exhibit (switching) activity;

environmental spatial variations (temperature, mechanical stress) that affect the

clock regeneration circuitry.

The contribution of clocked data elements, buffers and current switches is caused by

mismatch in identically designed devices;

mismatch in the geometrical characteristics of wires connecting the clocked ele-

ments, the buffers and the current switches together;

uneven capacitive and resistive loading.

cross-coupling of the clocked data interconnect wires with other wires, especially
with those that exhibit switching activity.

environmental variations with topological characteristics that influence the switch-

ing behavior of clocked elements, buffers and current switches.

The main results are :

1. The switch control signals of one SI cell become different compared to those of
other cells (fig. 5.10 (b)), This generates identically shaped but skewed current
pulses relatively to each other. In the binary part major carry glitches are generated.

2. The crossing point of the control signals varies from cell to cell, thus the spikes at
the common switch nodes vary from cell to cell as well [55] (fig. 5.10 (c) ).
58 Chapter 5 Current Steering DAC circuit error analysis

(a) (b) (c)

Figure 5.10 (a) Individual current pulses, (b) switch control signal delays and
(c) variations of their crossing points.

Relative timing inaccuracy is one of the most challenging problems in high perfor-
mance DACs, but so far has never been investigated properly. Five major points concern
the nature of the problem:

1. The variations in switching characteristics per unit cell are related to many origins.

2. The relative significance of its origins is strongly influenced by architectural pa-

rameters and circuit topologies. As the number of thermometer bits in a ther-
mometer/binary partitioned DAC increases, some authors believe [55] that it be-
comes more difficult to achieve the same precision of synchronization between the
clocked elements, although it can be argued that as the number of thermometer bits
increases the required timing accuracy reduces. In practice, it is likely that as this
number varies different physical origins dominate the inaccuracies.

3. Timing accuracy optimization of all relevant blocks crosses requirements of other

problems, related to timing accuracy and not. For example, steep clock edges re-
duce timing skew introduced by mismatch, but if local clock regeneration buffers
are used to steepen the clock waveforms they add additional clock skew due to mis-
match of their own. Steep signal edges generated by clock regeneration buffers,
clocked elements and drivers increases the significance of power supply bounce
and substrate noise. Steep data waveforms drive the current switches better, but the
peak values of the charge spikes at the output node of the DAC increase.

4. The relative significance of the contributing physical factors changes with technol-
ogy, operational speeds and design methods. Until the beginning of 90’s current
pulse skew was dominated by the decoder. Using latches to synchronize the de-
coder’s output waveforms the problem was reduced by at least an order of magni-
tude, moving the limits to other problems. When mismatch in MOS devices [75]
was brought on the table of A/D and D/A conversion, gradually the timing inaccura-
cies of current switches and latches under mismatch influence became a suspect. As
frequencies increase consistently, the clock wave propagation speeds, impedance
5.2 Time domain errors 59

termination issues and interconnect behavior appear in high-speed DACs [43, 91],
already a hot topic in high performance microprocessors [92].2
5. Although the problem of timing inaccuracy was known to limit DAC performance,
it has not been handled analytically as to reveal the mechanisms that translate inac-
curacies to signal distortion. On the other hand, it was never possible to prioritize
-or even distinguish- this problem experimentally among other problems, not to
mention to prioritize its great number of physical origins.
Considering so many aspects of the problem it is impossible to draw general conclu-
sions with only one or two experiments that focus on very specific aspects of it [55]. The
following issues need to be clearly understood before strong statements can be made about
its significance, its scaling with technology evolution, or the particular design techniques
used to reduce it:

what is the impact of the relative timing imprecision in a signal, and which princi-
ples govern its modulation behavior.

How each physical origin creates relative timing imprecision, and under which con-
ditions it becomes the dominant source compared to other sources.

How each origin is related to architectural parameters, e.g partitioning in many
thermometer bits, and under which assumptions for the hardware we may speak of
tradeoffs via some parameter.

How tackling one physical origin affects other origins.

How tackling one physical origin of this problem affects other problems not related
to relative timing precision.
These issues will be addressed in following chapters.

5.2.6 Power supply bounce and substrate noise

Power supply and substrate noise (or substrate coupling) are two generic problems that
concern most areas of high performance digital and analog IC’s.These problems, and the
particular ways they apply to CS DACs are described in this section.
The origin of the power supply problem is the combination of three things: the abrupt
currents that flow through the power and ground supply networks, the inductive behavior
of (especially) the package leads that interface the internal power supplies of the IC with
the external ones, and the inherent relationship between the supply levels and the opera-
tion of a circuit [93]. The dynamic currents flowing through the power supply package
leads force the voltages on the internal rails to bounce with L · dI/dt around their nominal
2 For similar range of frequencies we have 10 − 100 psec tolerances, large interconnect length 1 − 10 mm,

and thousands of clocked devices in microprocessors, compared to 1 psec tolerance, sensitivity to individual
characteristics of switching signals, small clock interconnect length (0.1 − 1 mm) and in the order of 10 − 100
numbers of clocked elements.
60 Chapter 5 Current Steering DAC circuit error analysis

Lvdd chip Vdd

PCB Vdd

I vdd
+
− Cd
Reception by ?
another circuit

Lvss
chip Vss
PCB Vss
Vss connected to the substrate
I vss

Figure 5.11 Conceptual circuit mechanisms of power supply and substrate

bounce generation and reception.

values. The peak values of the oscillations can reach several hundreds of mV . In turn,
the variations of this parametric signal affects the operation of the circuit powered by the
noisy supplies. A simplified model of this mechanism is depicted in fig. 5.11. Notice that
the same circuit can cause and receive disturbances simultaneously. The operation of a
circuit subject to supply noise can be affected in many different ways which depends on
the function it realizes.
As for substrate coupling, it is broadly defined by its occurrence, when currents in the
substrate, typically injected by high frequency signals, couple to other devices through
the use of the common substrate and affect their operation again via the parametric role
of the substrate potential in circuit behavior. In a system comprising of digital and analog
circuits, noise due to digital or analog switching activity can couple to sensitive analog
circuits and degrade the performance of the system.
From a physical point of view, substrate noise, or substrate crosstalk between devices
can be divided into three main parts [94]: the injection phase, in which fluctuations are
injected locally by the generating devices into the substrate; in the second phase the fluc-
tuations propagate in the spatial domain of the substrate; finally, after reaching close to
other devices, the reception phase takes place and modifies the electrical behavior of a de-
vice via its device mechanics (e.g. via the body effect, via capacitive coupling to drain and
source through the junction capacitances, etc.). The main physical injection mechanisms
are dynamic currents conducting through devices, impact ionization currents, capacitive
coupling from drain, source, interconnections and wells to the substrate, etc. The currents
generated via these mechanisms will be shunted to the ground through resistive wells,
etc., setting up a spatial potential distribution throughout the substrate. This potential
fluctuation determines the impact in reception circuits, and not the current itself [94]. The
5.2 Time domain errors 61

main factors determining the characteristics of this spatial distribution of fluctuations is

the substrate material (e.g. low or high resistivity), the locations and number of con-
nections to the ground, and their impedance characteristics. For example, low resistivity
substrates behave as short circuits and globalize the noise to all devices connected to it.
High resistivity substrates allow a high degree of localization of the fluctuations.
The inductance and capacitance introduced by the package of the IC that connects the
on-chip ground to the off-chip ground is one of the most important factors in overall. The
problem with packaging is similar to the power supply bounce. Since the substrate is tied
to the ground, the substrate bounces together with the ground. The inductance magnifies
the impact of the voltage fluctuations due to the rapid current changes that flow through
it. The addition of package parasitic capacitances can lead to unwanted oscillations and
transients during switching. Generally speaking, the dominant mechanisms of substrate
noise generation is the switching currents flowing through the devices causing transient
amplitudes in the order of 100 mV , where as capacitive coupling is in the order of 10 mV ,
and impact ionization is approximately in the 1 mV level [95].
In literature, there is plenty of research available on different aspects of both problems.
There are investigations on physical aspects (e.g. substrate materials) [95–97] and their
circuit modeling [98], impact on circuits (ADC, PLLs, digital ICs [99,100], etc.), substrate
modeling of devices, circuit and layout methods to reduce noise generation and reception
[101, 102], just to name a few. It may be concluded that their impact depends on
1. the circuit function (timing, biasing, etc.) and logic (CMOS, Current Mode, etc.);
2. the number of logic and clocked elements;
3. the switching strength of the elements (noise injected per switching action);
4. the number of separate power supplies (digital, analog, clock, biasing, etc.);
5. the floorplanning and layout;
6. the packaging and number of pins per power supply;
7. the substrate material (resistivity).
8. the synchronization level of switching activity.
Therefore, the impact is significantly context dependent. In DAC literature there exist only
brief discussions on the importance of noise generated by the digital decoder and received
by other circuits. There is a tendency to forget that every DAC switching circuitry can
affect other circuits or be affected itself. It is also not considered in which ways problems
are introduced in the signal generation mechanisms. Some specific appearances of the
problem are shown in fig. 5.12. They are:
1. Supply noise can cause functional errors to the digital logic.
2. Noise infiltrating in the clock generator from the decoder or the clocked elements
affects the clock precision in a data dependent way. In return, the clock signal
affects the clocking moments of all clocked elements.
62 Chapter 5 Current Steering DAC circuit error analysis

3. Noise injected in the supply network by the clocked elements is received back by
them. The larger their number that switch is, the larger the spike on their power sup-
ply and substrate, and the larger their timing error. Hence, the switching behavior
of the latches depends on the consecutive differences of the input signal.
4. The current sources are biased at a constant bias level. Noise is picked up by the
current sources via the body effect. Consequently, the amplitude value of all cur-
rents sources may be modulated by the number of switching elements.
5. Substrate noise picked up by current switches modulates their switching behavior
through the body effect.

digital power analog power

Vddd
Vdda
integer
equivalent data Latches Switches & current out
of binary input Decoder
& drivers current sources
clk

sub sub sub

substrate substrate
network network

Vssd
Vssa

sub

digital ground clock analog ground

Vddd Vssd

from
decoder

Figure 5.12 Manifestations of power supply and substrate noise in a CS DAC.

The following statements can be made for the appearance of the problems between
latches and the decoder:
1. The magnitudes of the supply and substrate disturbances increase with higher con-
version rate because the number of excitations of the supply networks per second
increase. The voltages do not have enough time to settle before each new excitation
is applied; memory effects may appear between previous and next samples.
2. The supply disturbances depends on the derivative of the input signal. Any device
property or dynamic parameter of a used latch circuit topology dependent on the
5.2 Time domain errors 63

power supplies or the substrate potential is modulated by this derivative, subse-

quently modulating device and circuit operation.

3. The material type (resistivity) and the way the latch array, the decoder, etc. are
placed on chip influence the global/local characteristics of the problem. For exam-
ple, if all latches receive the same disturbances all of them are affected identically,
otherwise there is an additional spatial modulation in addition to the global one.

4. If the thermometer part increases by one bit, then the clocked elements and the
decoder logic gates double. If the driving strength of these circuits is fixed, then
the excitation signals applied to the supplies double, hence the magnitude of the
problem doubles as well. If the driving strength of the clocked elements is tuned
for every other number of thermometer/binary bits then the main thing changing is
the topological characteristics of the aggressor and receptor circuits.

The discussion presented here aimed to introduce attention on this problem, and to
structure it in perspective of its dimensionality. Because it depends on many choices
(architecture, circuit, layout) for each IC, there can be no single recipe to deal with it.

5.2.7 Clock (timing) jitter

Another significant problem is related to undesired variations of the clock signal period
over time, which is referred to as clock- or time- jitter. The term timing jitter describes in-
abstracto variations in the timing accuracy of time-reference signals, when compared to
ideal time references. Variations in timing are generated during the operation of circuits
such as oscillators, PLLs, clock buffers, etc. that generate and process time-reference
signals. These signals influence the performance of data converters significantly.
Conventionally, an electrical signal with a period Ts provides timing reference with its
zero crossings that are uniformly located every Ts . They form a lattice of timing moments
defined by mTs , where m is the index of the period of the signal. This lattice establishes
the conversion moments in data converters. The timing moments are modified by µm for
each mTs and they become tm = mTs + µm . For a rectangular shaped clock signal timing
jitter is shown in fig. 5.13. The uncertainty of the clock period is defined by the shaded
area. The main characteristic of this problem is that it does not change the relative timing
accuracy of the individual current sources, but it makes them switch on or off in moments
that change from sample to sample. Again, the problem is global because it is generated
via a common node that shares the same signal to all clocked circuits.
Often, it is desirable to characterize timing jitter with a single property (e.g. variance,
rms). In order to speak of a single number characterizing jitter several definitions ap-
peared in literature [99]. They provide a measure of the performance of circuits such as
oscillators, PLL’s, etc.. However, the variance alone is not sufficient for use in A/D and
D/A converters. The properties of the timing errors (e.g. stationarity, ergodicity, correla-
tion for a stochastic process), or in other words how timing errors vary in time, its spectral
content and their dependency with the input signal influence significantly the effects on
the converted signal. In a DAC, timing jitter can originate:
64 Chapter 5 Current Steering DAC circuit error analysis

timing
amplitude
uncertainty µm µm+1

Ideal period
Modified period

mTs (m+1)Ts time

Figure 5.13 Nonuniform timing in a clock signal.

Externally to the DAC, e.g. introduced by an off-chip clock reference. This is

usually random in nature and is related to device noise or power supply noisy from
the external circuits that generate the clock signal. This type of jitter generates
mainly noise that spreads in the frequency bands continuously.

Internally, e.g. generated by noise in clock buffers or the result of interference

between switching signals of the DAC and the clock circuitry via biasing, substrate
or power supply nodes. Because switching activity is correlated with the input
signal, clock jitter becomes correlated to it as well and creates distortion.

Literature is full of analysis and results about jitter in converters in general. Perspec-
tives of the role of clock jitter among other fundamental limitations in A/D converters are
given in [103]. Yet, for D/A converters there is hardly a suitable and comprehensive anal-
ysis that can apply to a wider range of architectures under generic input signal properties
and jitter properties. In the next paragraphs existing results are reviewed and discussed,
and several unknown aspects of the problem are formulated.
Surprisingly, research in A/D and D/A areas followed an independent trajectory from
non-uniform sampling and interpolation theory, which is a very well examined general-
ization of this problem in the main lines discussed so far.
In literature over Nyquist D/A’s random and deterministic timing jitter is addressed.
Random jitter is always assumed White and Gaussian, and the converter has high reso-
lution to neglect the discrete amplitude nature of the input and output signals (e.g. [70]).
Further restrictions are applied as well: while jitter affects pulses, the error power is eval-
uated as the rms value of the difference between an ideal sinusoid and the corresponding
Taylor approximation of the phase-jittered sinusoid. The limitation is that the resulting
noise Power Spectral Density (PSD) is not possible to obtain, neither the relationship of
the noise with the pulse method, the relevant input signal properties for noise generation,
and the impact of different jitter models. Non sinusoidal signals are not analyzed. A series
of articles [104–107] describes deterministic timing jitter problem using pulses instead of
sinusoids. In [105] the spectrum that results from D/A conversion of deterministic data
with deterministic sinusoidal clock timing errors is calculated (only for RZ pulses).
5.2 Time domain errors 65

Timing jitter analysis has also flourished in the Σ∆ conversion area. In Σ∆ A/D’s the
main problem is caused by the feedback DAC core that receives at its input a signal with
both signal and -rich- quantization content. In Σ∆ D/A converters, the input of the DAC
core receives a (digitally) Σ∆ modulated signal with similar properties.
The nature of the Σ∆ A/D architecture allows a strong dependency of the problem
with circuit techniques (e.g. SC vs SI). This forms a significant degree of freedom non
existing in D/A’s. The choice on SC or SI implementation plays a role due to the relation-
ship between the CT output of the DAC core and the DT output of the A/D converter via
integration and sampling. Because of this the pulse shape of the DAC in a Σ∆ A/D con-
verter can be tuned without worries that its Energy Spectral Density (ESD) will introduce
unwanted distortion at the output signal; it is the total charge per sample that matters,
and not the waveform as such. In a stand alone DAC the ESD of the rectangular pulses
used introduces the well known sinc(x) spectral distortion. For example, in [108] differ-
ent pulse shapes are investigated to minimize the jitter effects of DACs. This can not be
applied in stand-alone DACs. Lack of distinction between the D/A and A/D sides of the
problem may result in the wrong conclusions that the relative signal to noise power at the
output of a D/A converter can be modified using proper pulses, or that a D/A converter
implemented with SC techniques is not sensitive to timing jitter.
An interesting points in Σ∆ areas is the role of the DAC resolution. It is widely
accepted that the resolution of the DAC core affect significantly the amount of jitter error
power generated. However, a comprehensive discussion on how and why this happens is
not available. It is usually stated [109] that jitter modulates high frequency quantization
noise into the band of interest, hence the larger the quantization noise that is present out of
the band of interest, the larger the noise that appears in it. However, this does not explain
the type of modulation that takes place, and the dependencies with specific properties of
the quantization noise spectra. It has been shown with computer simulations (e.g. [110])
that increase of the resolution of the DAC favors significantly performance. In [111] and
elsewhere, 1.5 bit DACs are used to reduce itter induced error.
Jitter analysis in Σ∆ D/A’s (e.g. [33, 112] and elsewhere) follows combinations of
Nyquist rate D/A’s and Σ∆ A/D investigations, and is primarily conducted with computer
simulations. In [33,112] the relationship between the resolution of the D/A core in the Σ∆
DAC and the jitter induced power is established soundly. In [112] this was exploited to
lower jitter noise in an audio Σ∆ D/A converter. Noise due to jitter is generated by the total
signal present at the input of the DAC, hence both wanted signal and quantization noise.
Noticing that for low resolution high order Σ∆ D/A’s the quantization noise dominates
the generation of jitter noise, DT filtering was applied in [33] and elsewhere to remove
out-of-band quantization noise prior the D/A operation. This technique is encountered
more and more often nowadays.
Another interesting but unexplored issue was highlighted in [79, 113], and some as-
pects of it were analyzed recently in [114]). Given that noise shaping affects the properties
of the signal fed to the DAC (especially its power and PSD), it is natural to assume that it
should affect the jitter power at the DAC’s output. This would mean that the type of filters
used in the Σ∆ loop and their orders can play a role because it affects the strength of the
(dominant) quantization noise part.
66 Chapter 5 Current Steering DAC circuit error analysis

A final less understood issue with existing theories is the role of Line Coding (RZ and
NRZ pulses). It is usually stated [115] that RZ pulses generate more jitter noise because
timing jitter affects both rising and falling edges of each pulse. It will be shown that
the differences extend to the particular PSD of the jitter noise, and that different Line
Coding makes the PSD being dependent on different properties of the input signal. This
has important consequences in multi carrier type of signals.
A summary of the aspects for timing jitter analysis are given next:

Timing jitter analysis in D/A converters is generally simplified. It misses the overall
picture because it starts usually from very architecture-specific assumptions.

Only sinusoidal signals are analyzed; no insight exists on which signal properties
are important. Jitter effects in a communication system context are disregarded.

The PSD of noise or other spectral products is not known for most of the cases.

The impact of the pulse method (RZ, NRZ) and the pulse type (sinc, rectangular
etc) on noise is not precisely known.

The jitter properties have a detrimental effect on noise. Mostly Gaussian jitter is
assumed. It is not clear what is the impact of more realistic models (e.g. timing
jitter in oscillators exhibits random-walk properties [116] and is non-stationary).

5.3 Conclusions
A circuit analysis of error mechanisms in the CS DAC architecture was presented. The
error mechanisms relevant for high frequencies were reviewed, extended further, and the
main lines of analysis were given for those mechanisms that require further investigation.
Attention was given to explain in detail the exact error generation mechanism, which
is a mixture of the way the CS DAC operates combining unit elements according to the
input signal, the parameters that define the nominal behavior of the elements, and the hi-
erarchical interaction of the elements with each other. Some properties of the errors with
respect to how they are generated were also highlighted: spatially-global and -local, static
and dynamic, random and deterministic, etc. They seem to be key words that character-
ize each error mechanism. Another significant aspect discussed is how exactly the errors
depend with the input signal. This relationship depends on the error mechanism, and on
how the parameters of this mechanism depend with the properties of the input signal (as
a function of the sample value, the value of the sample to sample transition, an average
function between related errors in a transition, etc). Three particular problems were ex-
amined in more detail for their dominant appearance at high frequencies, and for reasons
related to absence of structured knowledge about them in the DAC context: relative timing
inaccuracies, power supply and substrate noise, and clock (timing) jitter.
 6

High-level modeling of Current Steering DACs

T HIS chapter deals with high-level modeling aspects of the CS DAC. It addresses
three main issues. The first is system modeling of the DAC with respect to its hi-
erarchy of description from physics to abstract signals. The errors observed at the actual
pulses of the DAC will be related to its parameters, signals, and circuit behavior in view
of their relation with amplitude, time and space. The second issue concerns the properties
of the errors. A vector of properties will be defined which facilitates the classification
of errors in classes such that their principle dependencies with the amplitude, time, and
space domains, with the input signal and with their relation to random or deterministic
behavior is extracted. The third issue addressed is the functional modeling of the errors.
A reduction method will be proposed that embodies the errors with their properties into a
general signal generation mechanism that can be studied per class of errors.

6.1 System modeling

In this section the system modeling aspects that allow us to understand why the normal-
ized pulse shape and timing vary will be explained in more detail. The discussion that
follows shows that the normalized pulse and timing variations may be attributed to:
1. parameter variations;
2. subsystem interaction;
3. circuit parameter modulation.
The approach employed to highlight these factors consists of recording the hierarchical
layers of representation of the DAC, the parameters that influence the response of its

67
68 Chapter 6 High-level modeling of Current Steering DACs

subsystems, the way it interacts with its environment with signals and its subsystems
interact with each other, and the modulation of the circuit parameters.

CS DAC CORE SYSTEM

Actual system
actual response
excitations

input
functional signal
signals
properties
Functional
amplitude and electrical
time references hidden excitations properties
physical electrical
Power and ground etc. & responses
Circuit
physical
temperature, interference properties
physical env/ntal
humidity etc. Physical

hidden responses

Figure 6.1 The general characteristics of the CS DAC system.

6.1.1 System layers

The CS DAC is a dynamic system with a predetermined set of inputs, outputs and dy-
namic behavior. Its description can be made in different layers of physical abstraction as
described in fig. 6.1, which is a more detailed version of the system placed at the center
of fig. 2.1. The DAC interacts with its environment with excitations and responses that
receives and delivers from and to it, respectively. The excitations and responses can be
described hierarchically as well. Details about them are given shortly after this general
description. A set of properties characterizes the DAC and its subcomponents in vari-
ous hierarchical layers. They comprise of signal properties (rise time, overshoot, delay,
SFDR, linearity, etc.), geometrical properties (e.g. area), environmental properties (e.g.
temperature range of operation), electrical properties (power consumption, supply voltage
range). In a specific design these properties receive specific values.
In the most abstract layer, the functional layer, the DAC is represented as a func-
tion between abstract signals. The function is divided recursively in subfunctions up to
the point is described by primitive functions. This translation is accomplished by con-
version algorithms and it is described by an algorithm architecture. The description can
be translated from the functional layer to the electrical layer with a circuit architecture.
The boundary between the two layers is defined at the transition from abstract signals to
electrical signals and from functions to electrical circuits. On the other far end of the
abstraction spectrum lies the physical layer and additional layers exist in between.
6.1 System modeling 69

In each lower abstraction layer the DAC is described with more details and its be-
havior is characterized with the corresponding theories (signal processing theory, circuit
theory, etc). The closer the description is to the physical layer, the more the quantity of
information and interdependencies of factors complicates analytical descriptions of the
DAC operation, but the more information is available about it. A typical example is the
spatial dimensions of errors of a realized DAC that are not visible in the functional layers
unless explicitly abstracted. Abstraction forms the means to translate the physical prob-
lems in the abstract output signal. It has already been observed in chapter 5 that errors
share common properties and characteristics, consequently, several rules can be used to
structure and categorize them in classes. In this way, only the generic aspects of the phys-
ical origins behind all those errors need to be passed in the next higher hierarchical layer,
and the redundant information can be discarded in favor of insight and simplicity.

6.1.2 System excitations and responses

A CS DAC receives excitations and delivers responses. Fig. 6.1 shows conceptually the
types of excitations and responses in the CS DAC. Excitations come from the left and
bottom sides of the DAC, and responses are delivered at its right and bottom side.
Excitations and responses can be divided in actual and hidden. Actual excitations
are applied or received, respectively, via the core’s functional, electrical, and physical
environment. In fig. 6.1 they are located at the left and right sides of the DAC. Hidden
excitations and responses (e.g. the outputs of the decoder, the latches) are only visible
inside the system’s hierarchy between its primitive components (bottom side of fig. 6.1);
they are electrical signals with which the subsystems of the DAC interact functionally
with each other and can be further divided to intentional and parasitic (interference).
With respect to hierarchy, we may call functional excitations those that are constitu-
tional parts of the input-output functional description of the DAC. These form the signals
with which the DAC communicates with other systems. The digital input signals and the
analog output are these signals. This distinction can be seen in the unit DAC shown in
fig. 6.2. A unit DAC is defined as a single chain consisting of a clocked element and a
SI cell that makes a single bit D/A conversion. The complete DAC can be seen as the
combination of 2N unit DACs connected at the common output node.
The excitations and responses can be random or deterministic. They are expressed in a
combination of amplitude, time and spatial domains, and they are represented in different
physical quantities. For example, a stable (time-independent) voltage or current consti-
tutes the amplitude reference; the time reference is defined by a highly stable periodic
signal; heat forms a multi-dimensional excitation that varies in amplitude as a function of
space in a silicon realized DAC, and in time.

6.1.3 System parameters

The actual behavior of transistors, resistors, functional circuits (latches, drivers, etc.) is
each characterized by a set of parameters. When so many elements are combined together
to build a DAC there will be a wide range of parameters spanning through the complete
70 Chapter 6 High-level modeling of Current Steering DACs

Figure 6.2 Input signals of a unit DAC element.

physical hierarchy that can influence the functional relationship between the input and
output of the DAC. If the DAC is ideal these values will be fixed to some nominal val-
ues. In reality there are always small variations around their nominal values, which are
translated to variations in the nominal behavior of the DAC.
These parameters can be divided in two types: parameters that stem from system ex-
citations and static parameters. Parameters that are defined by system excitations include
for example the power and ground supply voltages, the substrate potential, temperature,
etc. Static parameters correspond mainly to electrical and geometrical parameters. Ex-
amples are the parameters of the process in which electronic components are realized.
Other parameters can be functions of these two types (for example the threshold voltage,
the transonductance of transistor, etc.). All parameters have amplitude, time, and spatial
dimensions, but static parameters are usually independent over time.1
To achieve the required DAC output pulse properties, the parameters have to remain
restricted in well defined windows. The problem is that instead maintaining their nominal
values, they vary in amplitude, time and spatial domains. When this happens, the response
of the DAC to its functional excitations changes as well, hence the pulse signal outputs
vary accordingly. Therefore, it can be said that via variations in parameters -as a function
of time or space- DAC nominal normalized pulse variations from nominal values can be
anticipated because the DAC operation depends on these parameters. A couple examples
of how such variations occur are next given assuming an array of unit DACs.
Consider the parameter temperature. It can rise globally to all unit DACs in the same
way due to ambient environmental reasons that heat the complete IC in the same way, or it
can vary according to a spatial distribution (e.g. parabolic) from unit to unit as a result of
an on-chip heat source (e.g. a clock buffer). The result is that via several device and circuit
mechanisms the output responses of the individual clocked elements, current sources and
switches will follow the spatial distribution characteristics of the temperature. In another
1 Some static parameters may in fact be called quasi-static because they change in time but very slowly (e.g.

aging effects).
6.1 System modeling 71

example. consider the relationship between the speed of the response of a CMOS latch
and the level of the power supply. In an array of identically designed latches sharing
the same power supply, as the supply level changes the responses of the latches for the
same input signals change accordingly. In the end, the variations in the supply appear via
several circuit mechanisms as variations of the output pulses of the unit DACs, and finally
as pulse variations of the DAC output via its signal generation mechanisms. A spatial
distribution of the power supply voltage across the latches due to IR voltage drop maps to
a similar spatial distribution of the unit DAC responses.
Examples concerning static parameters are given next. Process parameters exhibit
a spread over their nominal values. Spread in the values results to spread in the actual
response of the unit DACs through the electrical mechanisms of the circuit topologies.
For example, oxide thickness variations manifest into variations of the threshold voltage
of a MOS device via its device laws of operation. Subsequently, via the circuit laws of
operation, variation of the oxide thickness appears as variations in currents, delays in
switching, etc. An oxide thickness spatial distribution around the nominal value in a wide
chip area occupied by unit DACs maps hierarchically to a similar distribution in current
error and switching moment distributions.
In summary, any cause of variations of parameter values relevant for the output re-
sponse of the unit DAC modifies the output pulses in corresponding ways.

6.1.4 Subsystem interaction

Although all hardware elements in the DAC may have identical parameter values, varia-
tions in the normalized pulses and timing can still occur.
This can happen via hidden excitations that carry signals from DAC subcircuit to
subcircuit. The point is that the shape of the output transients still depends on the shape
of the input transients. Therefore, even if two subcircuits of the DAC are identical with
respect to all their parameters, their outputs can still be different if they are excited slightly
differently with respect to each other. For example, the speed with which the clock drives
a DAC unit determines the delay of its output current pulse. Usually, a global clock is
inserted in the DAC and then distributed locally in the unit DACs via a clock distribution
interconnection network. If the local clock signals (intentional hidden excitations) that
trigger the operation of all switching unit DACs vary in steepness and delay according to
a spatial distribution over the unit DAC array, the corresponding unit DAC current outputs
will vary accordingly. This despite the fact that they are identical with respect to all their
parameters. Notice that the initial variation in the local clock signals may be caused by a
variation in fixed parameter values that characterize each path from the global to the local
clock location (RC constants, etc.).
In addition, electronic circuit topologies contain many nodes that provide parasitic
paths between functional nodes of the DAC subcircuits. These nodes allow interference
signals to propagate through and cause subsequent error excitations and responses in the
subcircuits. The most important paths are those that allow feedthrough of interference
signals directly to the output nodes (e.g. parasitic drain gate capacitance of the current
switches), and parasitic clock and data feed through signals from the latches to the output.
72 Chapter 6 High-level modeling of Current Steering DACs

6.1.5 System modulation

The last mechanism responsible for variations in signal pulse shape comes via the mod-
ulation of circuit parameters and hidden signals in global DAC nodes. Because the unit
DAC elements and the decoder consist of nonlinear units that switch on and off according
to the signal, parameters of the circuit are modified accordingly. For example, the switch-
ing on and off of unit DACs at the output DAC node modulates its output impedance,
thus also the output signal pulse properties. Similarly, signal dependent switching on/off
of gates, or latches changes the properties of the power and ground supply networks and
their excitations. This creates a self-reflective mechanisms of errors because the response
of the supply networks forms an excitation that affects a parameter of the DAC.

Nominal pulses actual pulses

parameters interaction modulation

Figure 6.3 Important aspects of signal pulse variations in the DAC.

In summary, the DAC can be described in several hierarchical abstraction layers to

facilitate the understanding of its operation. Its behavior is parameterized to actual and
hidden signals, and to static parameters. The combination of these factors defines the
characteristics of the DAC pulse responses. These pulses have a high level of spatial
characteristics because the DAC consists of many identical subcircuits placed in arrays
on silicon. Ideally, each parameter should have a predetermined value independent of
time and space, free of any modulation. The intentional hidden signals should be iden-
tical for all identical elements and independent of the signal, and no parasitic hidden
signals should exist. Also parameters should be free of any modulation. These conditions
are not satisfied, consequently, the DAC output pulses and timing inherit the mentioned
amplitude-time-spatial characteristics. The description given in fig. 6.3 summarizes the
main reasons why the actual normalized pulses at the DAC output vary.

6.2 Error properties and classification

The error signal that results from the variations of the actual normalized DAC pulses is
expressed in the amplitude and time domains. It is a direct function of the input signal
but it does not have an explicit spatial dimension. However the variations in the nominal
parameters values do have a spatial dimension, and can be related to the input signal,
6.2 Error proper ties and classiÝcation 73

too. The existence of three domains (amplitude, time, and space) in the error waveform
motivatesdefining some criteria to be able to distinguish them in classes. This section
deals exactly with this issue: first the error properties are defined and discussed, and then
the errors are classified accordingly.

6.2.1 Error properties

The errors that appear in the CS-DAC architecture show specific characteristic behavior
with respect to amplitude and time domains, physical and electrical topology of an ar-
chitecture (spatial characteristics), signal dependence, mechanism of creation, etc. By
formulating properly these characteristics into a vector of error properties they may later
be classified accordingly, and their properties can be embofied in the normalized pulses
of the DAC output signal.
The type of error waveform within a sample to sample transition is defined by looking
how the integrated error waveform within a sampling period -which corresponds to the
total error charge related to the transition- depends with the amplitude and time references,
and with topology. For simplicity the definitions are established using the output of a unit
DAC. The extension to the normalized pulses of a DAC (composed by many unit DACs)
is straightforward.
When a switched current cell makes a transition, it changes the state of the current it
outputs from zero to I, or from I to zero.2 There is a charge that is delivered at the output
during the whole duration of the sampling period Ts , which in the ideal case is given by
(m+1)Ts
Qideal (Ts ) = I · dt = I · Ts
mTs

Assuming some physical problems that appear in a real implementation, the charge deliv-
ered by the current cell during a sampling period is modified to
(m+1)Ts
Q(Ts ) = I(t)dt (6.1)
mTs

which results to an error charge given by

(m+1)Ts
Qε (Ts ) = (I(t) − I)dt (6.2)
mTs

Amplitude and Timing errors

Let us model the relationship between the charge error and the sampling period as

Qε (Ts ) = α Ts + β + γ /Ts + ... (6.3)

When the charge error Qε scales proportionally to the sampling period Ts , therefore the
ratio of this charge over the ideal charge Qideal = I · Ts stays constant, the error will be
2 Alternatively, it may change from a current value I1 to a current value I2 .
74 Chapter 6 High-level modeling of Current Steer ing DACs

called an amplitude error. In this case, the factor α defines the amplitude error. When
the error charge Qε is such that when the sampling period of the D/A operation scales the
error charge stays constant, or decreases (assuming the transient time to be still smaller
than the period) the error will be called a timing error; the ratio of the error charge over
the ideal charge scales according to the scaling of the sampling period, hence when Ts
decreases the error charge occupies a larger fraction of the total signal charge. In the
simplest case, Qε = β applies for timing errors, meaning that they scale linearly with Ts .
Consequently, a problem of current transients, non linear transient shapes, timing
errors, etc., that is related to an element of DAC hardware (latch, driver, SI cell) can be
translated to an equivalent3 timing, or amplitude error. In fig. 6.4 current transients of

Abstraction layer

electrical functional equivalent

amplitude
error

equivalent
timing
error

Figure 6.4 Equivalent amplitude and timing errors.

different unit DACs are shown. The origins of their differences are mismatch, capacitive
loading differences, clock signal shape differences, etc. For every waveform shown in
the left of this figure there is a net charge error Qε that defines the difference of charge
from a correspondingly ideal transient. These errors can be translated to time delays of
amplitude deviations via the charge errors they introduce compared to the ideal case. For
timing errors, the equivalent time delay is calculated with

Qε
Tε = (6.4)
I
This timing delay is defined as the equivalent timing error. This definition excludes
switching errors that have a zero net error charge. This assumption is safe for most cases.
A similar definition can be given for the amplitude errors.

Spatially local and global errors

Dependent on the relationship between the error charge and the location of the circuit(s)
that generate it, errors can be distinguished to local and global.
3 Notice that this translation does not lead necessarily to an identical error. More information will be given

in the next chapter

6.2 Error proper ties and classiÝcation 75

Local spatial errors result from localized behavior of identically designed circuits.
They originate from variations of static parameters spatially and variations of system ex-
citations that define parameters. For example, in a thermometer DAC, all unit DACs are
identical by design, however, in practice the current pulses they generate stimulated by
identical data and clock signals are not the same. Each unit pulse exhibits a spatial behav-
ior, in the sense that each one is slightly different from another because its corresponding
unit DAC is placed at a different location in which the same parameters have different
values. In other words, each one exhibits a local error.
One reason behind this behavior is spatial variations of static parameters during IC
manufacturing. For example, due to process spread the threshold voltage values of two
transistors defining switches parts of two different unit DACs, have different values de-
pendent on their chip location. If these switches are driven by the same input signal they
show different switching behavior: timing delays, switch on-resistance and charge injec-
tion. This reflects to a local timing error. Additional problems include are systematic
clock interconnection length differences that cause RC timing delays, which in the end re-
flect to skew in the current pulses and, finally possible impedance termination differences
in the clock network. Local errors come also from spatial distributions of parametric sig-
nals. Temperature fluctuations and substrate noise, biasing voltage spatial variations (e.g.
a gradient over the ground node due to high resistivity) are typical examples.
The unit DAC current pulses are combined under the control of the input signal.
Hence, signal dependency appears; for each input value, a fixed combination of unit
DACs is met, which reflects to a fixed combination of local errors. Consequently, the
input signal modulates the topological problems and transfers them to the output signal.
The error signal at the DAC output is obviously the result of the combination of these local
errors, hence it is inherits the local behavior as well. We may speak of normalized pulses
with local errors. An important property of local errors is that they can be corrected at a
different time scale than that of the signal. For example, calibration corrects local errors
in a much slower rate than that of the signal.
The other category of spatial errors is global errors. Global errors are generated via
modulation of signals by other signals -usually the input signal-, circuit interaction be-
tween cells via common nodes, and parameter modulation during operation. Because
these parameters are common to all identically designed circuits, their behavior is mod-
ulated in the same way for all, but differently for different moments in time. Examples
follow in the next paragraph.
The DAC output is a global node for all unit DACs. According to chapter 5 the
impedance of this node is modulated by the input signal. All unit DACs see at their outputs
the same load, but this changes as a function of the signal. Consequently, all provide
similar pulses, and all of the pulses are modified according to the input signal. Power
supply, ground and substrate nodes are examples of global nodes from which excitations
that define parameters of the circuits are applied. During the switching of the unit DACs
supply level disturbances are created that depend on the number of the unit DACs that
change state (the input signal derivative). As a result, all unit DACs are affected in the
same way. They generate identical current transients with timing and shape modified in
76 Chapter 6 High-level modeling of Current Steering DACs

accordance to the number of unit DACs that change state each time. Clock jitter is also
a global error. When the common clock period exhibits variations, all of the clocked
elements are affected in the same way, but differently for different samples.
An important characteristic of global errors is that they can not occur when the circuit
elements do not have means to interact with each other. Similar problems occur also when
units interact non electrically, for example when an input excitation changes globally for
all elements (e.g. heat). The characteristic of global spatial errors is that the unit DAC
elements behave in the same way but in a different manner for each input value. Most
global errors can not be considered separately from the signal generation mechanism that
forces hardware components to interact with each other during operation. This means that
most of them have to be addressed at the same time scale with that of the signal (e.g., GHz
signal, GHz the corresponding correction techniques).

Static and dynamic errors

The terms static and dynamic in the context of errors are used in literature to describe
errors that occur due to the dynamic nature of the transient response of circuits. In some
cases they also describe the type of errors in a circuit in association to time invariant and
variant signals, respectively. Here, we make a dinstinction between the use of these term
to describe the error in a pulse, and the origin of this error, which can be static or dynamic
as well. This dinstinction is based on the fact that in a DAC both static and dynamic
origins can result in dynamic errors. Hence, a dynamic error aimed to describe the actual
error pulse in itself does not give enough information about the mechanism behind it.
For some errors, their origin is static, that is, it does not change over time and for
others it does, hence it is dynamic4 For example, process parameter variations during
manufacturing cause time delays in latches. The errors are dynamic (a waveform delays
to rise) but they are caused by a static parameter variation. The property of being static
is passed to the delays as well: they are always the same. Excitations responsible for the
definition of circuit parameters can cause both static and dynamic errors; for example,
when the power supply voltage varies dynamically as the latches change state. the latches
delay according to these dynamic variations. Again, the error is dynamic but it results
from a dynamic origin as well and inherets its properties: the delays depend on how many
latches change state. In this restrictive subcase of dynamic errors the source of the pulse
shape dynamic variation is a mechanism that relates the circuit parameter to the input
signal: as the input changes, the parameter changes also. For the IR drops in the ground
supply rails of the current source array, the origin is static.

Signal dependency in the errors

Three types of error signal and input signal (data) dependencies are distinguished. In
the first case, data dependency occurs explicitly via the signal generation mechanism that
4 The definition using the word dynamic has been preferred from just using time-dependent because dynamic

describes also the forces responsible for the time-varying behavior.

6.2 Error proper ties and classiÝcation 77

combines unit DACs with errors according to the input signal. Consequently, it creates a
data dependent error signal. This is usually the case of spatially local errors.
In the second case, the DAC is ideal, but a parameter or an excitation of the DAC
(e.g. the references) is modulated by disturbances that are independent to the input signal
(e.g. phase noise in the clock signal). When they mix with the DAC signal generation
mechanism the final error in the DAC output is dependent on the input signal. A typical
example concerns random clock jitter: the clock signal is modulated by a non correlated
random noise source, and it forms a time reference with random jitter. When this clock
signal is supplied to the DAC, it causes noise at the DAC output signal which has a power
spectrum density proportional to the DAC input signal power.
In the last case the signal dependency comes via modulation of parameters or ex-
citations explicitly by the input signal of the DAC. The signal generation mechanism
determines which elements are stimulated, and their responses are combined by the sig-
nal generation mechanism to create the signal. However, during the stimulation of the
elements non-linear dynamic phenomena take place that modulate dynamically the DACs
parametric signals (e.g. in the di/dt problem the switching activity modulates the supply
levels) or the amplitude and time reference signals. The data-dependent excitations such
as the substrate potential, power and ground supplies, biasing nodes, etc. reflect back the
modulation in the responses of all switching elements, biasing units, unit current sources,
etc. These responses are collected by the signal generation mechanism and the cycle is
finished: the error signal depends with the input signal.

Random and deterministic errors

Another way to distinguish an error is to look on whether it is random (random) or de-
terministic. There may be random or deterministic spatial amplitude distributions of pa-
rameters, random or deterministic signals in time, and combinations of randomness and
determinisism in amplitude, time and spatial domains of a signal, or parameter. The errors
inherit the nature of their origin, although with additional correlation with the DAC input
signal via the DAC signal generation mechanism. For example, in the case of random or
deterministic clock jitter, the period Ts is modified in time in a random, or deterministic
way, and this is passed to the output signal as well with the addition of correlation with the
DAC input signal. In another example the spatial properties of the technological process
parameters (random and deterministic) are assigned to the amplitude and timing errors of
the circuit elements, subsequently being inherited by the output error signal.

6.2.2 Error classification

The error properties that were defined previously allow us to classify them accordingly.
An indicative classification of the errors discussed in chapter 5 can be made with the aid
of table 6.1 and figures fig. 6.5 and 6.6. In table 6.1 the origin of the error of the output
signal is shown only for timing errors. It can be seen that the error mechanisms are not
concentrated in one class only. This means that this architecture is not characterized by
a very dominant error mechanism and limitation but a wide range of error mechanisms
78 Chapter 6 High-level modeling of CurrentSteering DACs

spatial domain
local global
Non linear settling
output current summation power supply bounce
interconnect network
timing

clock skew

substrate noise
mismatch based
time skew
errors

clock reflections clock jitter

current errors due to Output impedance
amplitude

ground rail IR drop

DC errors by
mismatch based thermal noise
current errors

Figure 6.5 Error classification: amplitude, timing, and spatial errors.

Circuit problem static param. excit./param hidden signal circ. param. mod.
Power Supply bounce +
Substrate noise + +(interference)
Nonlinear settling +
Clock skew +
Mismatch in timing +
Output imped. mod. +
Clock jitter +
Charge feedthrough +(interference)

Table 6.1 Error origin.

with different origins and properties. In the design phase many tradeoffs and limitations
appear since the mechanisms depend differently on common circuit parameters.
In fig. 6.5 the errors are classified according to their amplitude, timing and spatial
properties. As expected, timing errors are dominant in numbers compared to amplitude
errors. Except from substrate noise and possibly the power supply bounce, al l other prob-
lems can be explicitly categorized to one spatial domain subclass. In fig. 6.6 local errors
are classified on whether they are spatially random or deterministic. It can be seen that
ones are related one way or another to mismatch, thus they are significantly parameter-
ized over the properties of the technology used. On the other hand, the deterministic ones
are not only more in numbers, but many of them are also related implicitly to the design
complexity in realizing interconnection networks with identical lengths.
6.3 Functional error generation mechanisms 79

random Amplitude vs. space

deterministic

e.g. due to mismatch in clock skew e.g. due to systematic

interconnects dimensions interconnect length differences

clock reflections
RC load differences
mismatch based
Spatial domain: local

e.g. local threshold e.g.threshold

mismatch effects timing skew gradients effects
on switching transistors on switching transistors

Substrate noise Output current

e.g spatial distribution of summation wires
noise in the latch array

e.g. local threshold mismatch based e.g. gradients in the

mismatch effects on current source errors current source array,
unit current sources ground rail IR drop.

Figure 6.6 Error classification: local random and deterministic errors.

6.3 Functional error generation mechanisms

To study the impact of a set of problems on the output signal of the converter a simple
functional model is required that embodies the abstracted characteristics of errors in a
simple function similar to the signal creation function described schematically in fig. 1.1.
This is the topic of this section.

6.3.1 Definitions
The generic algorithmic description of the CS DAC is easily translated to a generic circuit
architecture which contains only basic circuits blocks to realize the D/A function.
In practice, the generic CS DAC circuit architecture is enriched substantially with the
addition of auxiliary circuits that regulate, shape, resample and filter many subsignals to
improve performance. For example, latches eliminate data waveform timing differences
generated by logic propagation delays and mismatch. These modifications are the result
of measures against specific electronic problems. Electronic considerations transform the
generic CS-DAC architecture into a specific one. The specific circuit architecture shown
in fig. 6.7 is an example of the generic-specific mapping, and it will be used in the
following. An even more specific translation of it is given in fig. 3.4 in chapter 3.
Next, the impact that a specific architecture has on the models that are to be used for
the analysis is discussed. It has been explained in chapter 1 that the DT/CT conversion
is a modeling requirement imposed when the input electrical signals are restricted to DT
80 Chapter 6 High-level modeling of Current Steering DACs

clocked data− Intermediate to

storage elements SI cells integer code conversion
binary to intemediate

R
code converter
binary input

output signal

clock

Figure 6.7 Specific CS DAC architecture retiming data before the SI cells.

signals. We have mentioned also that the location of the DT/CT conversion is subjective,
in the sense that it depends on where the CT problems become important. Whether the
CT nature of subsignals in the architecture is relevant or not depends on circuit realization
choices that modify the architecture. In fig. 6.7 due to the clocked data-storage circuits
(latches, flip-flops, etc.) all major CT problems of the decoder can be safely neglected,
and we assume the DT/CT conversion located between two steps of the code conversion.
Was there now a Track/Hold (T/H) circuit at the output node of the DAC, then almost
all CT aspects of the signals before the T/H circuit could be neglected. Because our
main goal is to understand the CT problems of the CS DAC architecture without T/H, the
specific architecture from fig. 6.7 will be used for further modeling and analysis.

6.3.2 Algorithmic modeling

The block schematic of the circuit in fig. 6.7 is translated now back to a specific algorith-
mic architecture in fig. 6.8. The signal generation mechanism is the following:

1. Binary to intermediate code conversion of the N input waveforms to m output ones.

2. DT/CT conversion for each intermediate data waveform.

3. Conversion to a current for each intermediate waveform with the intermediate code
defined weighted currents I · 2weightm .

4. Conversion from the intermediate code to an integer output.

5. Conversion from the current domain to the voltage domain.

6.3 Functional error generation mechanisms 81

I
DT/CT conversion to current
conversion
2 weight m
dm
p(t)

I
Σδ(t−mTs) Int/te to integer
weight m−1
2 code conversion
binary to intermediate
dm−1
p(t)
DN
s(t) output
code converter

DN−1 I
Σδ(t−mTs) I/V
DN−2 signal
weight m−2 current to
dm−2 2
p(t) voltage
conversion
D1
Σδ(t−mTs) I
d1 weight−1
p(t) 2

Σδ(t−mTs)

Figure 6.8 Algorithmic architecture of fig. 6.7.

Had theT/H based architecture been selected, the second step would become the last one.
The subsignals flowing in the architecture of fig. 6.8 belong to three topological do-
mains. In the input stage of the converter the data words consist of binary digits: they are
digitally coded signals, assumed discrete in amplitude and in time. Then, after the DT/CT
conversion all waveforms are CT but carry information in discrete amplitude levels. The
information is encapsulated in the individual waveforms after the DT/CT conversion and
before the summing node in a digital form. However, to pass it correctly in the integer
form, the individual waveforms need to match very well in timing and shape, which means
that the similarity in the waveform characteristics is crucial. Finally, after the individual
signals are combined together there is notion of pure analog signal nature.
Differences in the individual CT waveforms (time or amplitude related) are mixed
together in ways influenced by the intermediate coding. While the intermediate coding
is defined as a purely amplitude domain degree of freedom, in fact it is a principle factor
that determines how time domain problems are translated to the signal. For example, the
time domain problem “skew between current pulses” translates to instantaneous sample
values at the output signal. The type of intermediate coding used (binary, thermometer,
segmented, etc.) has an impact on the shape and magnitude of these intermediate values.
In summary, a specific CS DAC circuit architecture was selected and its behavioral
description was given. This behavioral description was translated to a detailed algorith-
mic description with primary signal components. At this level, the results of the vertical
modulation analysis can be introduced and the reduction concept can be established.
82 Chapter 6 High-level modeling of Current Steering DACs

6.3.3 Functional modeling

The functional modeling of errors in the selected architecture consists of two steps: errors
are introduced at the primitive components of the algorithmic architecture -these errors
are assumed to be abstracted versions of the physical problems, and they posses the prop-
erties defined in the previous section-, and then the algorithmic architecture is once more
reduced back to a generic functional description, which is further studied.

Modeling of ideal behavior

The specific algorithmic description will be translated next into a generic functional de-
scription under the assumption of properly abstracted electronic problems. The architec-
ture of fig. 6.8 with thermometer encoding will be used. The N bit binary input words
D(m) are translated to thermometer words consisting of 2N − 1 bits, di ∈ {1, 2, ..., 2N − 1}.
For RZ pulses with a duration of Ts the mathematical formulation of fig. 6.8 is
∞ 2 N −1 ∞ 2 N −1
s(t) = p(t) ⊗ ∑ ∑ Idi (m)δ (t − mTs ) = ∑ ∑ Idi (m)p(t − mTs ) (6.5)
m=−∞ i=1 m=−∞ i=1

and for NRZ pulses and proper initial conditions it becomes

∞ 2 N −1 ∞ 2 N −1
s(t) = u(t) ⊗ ∑ ∑ I∆di (m)δ (t − mTs ) = ∑ ∑ I∆di (m)u(t − mTs ) (6.6)
m=−∞ i=1 m=−∞ i=1

Because there are no non-idealities introduced in the signal components, eq. (6.5) and
(6.6) can be easily reduced back to the generic signal generation mechanism
w(m) integer equivalent of D(m), and
p(t) ⊗ ∑∞ ∞
m=−∞ Iw(m)δ (t − mTs ) = ∑m=−∞ Iw(m)p(t − mTs ) RZ
s(t) =
u(t) ⊗ ∑m=−∞ I∆w(m)δ (t − mTs ) = ∑∞
∞
m=−∞ I∆w(m)u(t − mTs ) NRZ
(6.7)

Modeling of amplitude and timing errors

The translation from a generic function to a specific circuit description and then back to
a generic function is not as straightforward with non-ideal behaving circuits. Suppose
now that we have some electronic problems that we incorporate in the signal primitive
components of fig. 6.8. For example, for the matching accuracy limitations in the cur-
rent sources, we add a current error in each unit current. The distribution of current
source errors is assigned properties that encapsulate information about the physical pro-
cess that causes the current errors (e.g systematic process spread gives systematic current
error distribution). A similar assumption can be made for the switching behavior of each
current switch. All unit switching elements are slightly different due to mismatch, and
consequently each unit current pulse has a slightly different shape, while the overall dis-
tribution of switching characteristics follows the spatial distribution of the physical cause.
Furthermore, the timing of the process is also assumed non ideal.
6.3 Functional error generation mechanisms 83

To model this problems we let the unit amplitudes of the reference currents be differ-
ent, the transition shape u(t) from u = 0 to u = 1 to be also different, and the timing of
the delta pulses (clock) vary with some undefined function f (w, m), where w is the integer
equivalent of the binary input word and m is the DT index. The above are mathematically
formulated as
Amplitudes: Ii = I + ∆Ii
Transition shape: ui (t) (6.8)
Timing : mTs + f (m, w)
for i ∈ {1, ..., 2N − 1}, where ∆Ii defines the current error of each unit current reference,
ui (t) describes unit step functions that have a final value equal to 1 but perform the tran-
sition in different ways (skew, rising slopes etc). Although the electrical problems are
brought now to the primitive signal components, they are not yet in the signal itself.

Modeling of the actual behavior

The transition Tr(m − 1, m) for a NRZ DAC from a sample value w(m − 1) to w(m) can
be modified now from the ideal case I∆w(m)u(t − mTs ) to
2 N −1
Tr(m − 1, m) = ∑ Ii ∆di ui (t − mTs − f (m, w)) (6.9)
i=1

Using convolution properties, the fact that only the thermometric bits between w(m − 1)
and w(m) change state (only when ∆di = 0), and by defining
α = min{w(m), w(m − 1)}
(6.10)
β = max{w(m), w(m − 1)}
we rewrite eq. (6.9) to
2 N −1
Tr(m − 1, m) = δ (t − mTs − f (m, w)) ⊗ ∑ Ii ∆di ui (t)
i=1
β
= δ (t − mTs − f (m, w)) ⊗ sgn(∆w(m)) ∑ Ii ui (t)
i=α
(6.11)
∆w(m) β
= δ (t − mTs − f (m, w)) ⊗ ∑ Ii ui (t)
|∆w(m)| i=α
 
β
1
= δ (t − mTs − f (m, w)) ⊗ ∆w(m) · ∑ Ii ui (t)
|∆w(m)| i=α

∆w(m)
where |∆w(m)|
= sgn(∆w(m)) is the sign of ∆w(m). With the further replacement of
β
1
v̂(t, w) = ∑ Ii ui (t)
|w(m) − w(m − 1)| i=
(6.12)
α
84 Chapter 6 High-level modeling of Current Steering DACs

we can simplify the previous equation to

Tr(m − 1, m) = δ (t − mTs − f (m, w)) ⊗ ∆w(m)v̂(t, w) (6.13)

 
 
timing amplitude and shape

The complex initial formulation of eq. (6.9) is reduced to a simple interpolation based
function, in which the ideal transition shape u(t) has been replaced in eq. (6.13) by an
input signal dependent transition shape. This contains important information about the
individual bit transitions ui (t) and the unit currents Ii of the elements involved in the
transition w(m − 1) → w(m). The shape of this transition can be called the normalized
shape, and the pulse is the normalized pulse.
transition from w=11 to w=14

summation
division by
of all steps
number of steps

Normalized step transition

Transition from w=11 to w=14, three identical normalized

three unit steps are swithing on. pulses may be used
to describe the same transition

Figure 6.9 Example of normalized pulses.

The normalized transition is the average of all individual current transients involved
in the transition w(m − 1) → w(m). For a binary coding scheme some modifications are
required in eq. (6.11) to account for the weighted average of the individual waveform
shapes. To obtain insight on the meaning of the normalized step v̂(t, w), we give an
example in fig. 6.9 for the transition from w = 11 to w = 13. In the left side of fig. 6.9
three transient currents are depicted, each one different from the other. The actual output
transition in the middle of fig. 6.9 is the sum of the three transitions. The normalized
transition is extracted from the actual transition with a division by 3.
The modified signal generation mechanism can be written as
∞
s(t) = ∑ v̂(t, w) ⊗ ∆w(m)δ (t − mTs − f (m, w)) (6.14)
m=−∞
6.3 Functional error generation mechanisms 85

In the most general form eq. (6.12) generalizes to

β
1
v̂(t, w) = ∑ Ii ui (t, w)
|w(m) − w(m − 1)| i=
(6.15)
α

meaning that each unit step may as well be a function of the input signal (e.g. for dynamic
errors). The schematic description of this signal generation mechanism is given in fig.
6.10. The original signal generation mechanism is modulated in two ways. First, there is
a modulation of the conversion rate described as a pulse position modulation of the delta
pulse train. This defines a non uniform timing lattice. Second, there is a modulation of
the interpolation pulse’s shape (ideally independent of the signal). It will be shown later
that this modulation is further degenerated to well known modulation mechanisms.

∆ w(m)

w(m)
DT Modulated
s(t)
Differentiation
CT interpolation

δ(t−mTs) u i(t,w)
PPM

DAC HW: Vertical error generation

Figure 6.10 The horizontal error generation mechanism for NRZ pulses.

6.3.4 Examples
Three examples will be given to help the reader obtain insight on how the models apply
to the actual problems examined in chapter 5. In the first example the relative amplitude
precision problem is modeled (section 5.1.1), in the second the relative timing precision
problem (5.2.5), and in the third example deals with the power supply induced timing
delays that appear in the latches of the DAC (section 5.2.6).

Example 1
Consider identical unit transitions shapes for all thermometer bits, but different unit cur-
rents, each of which is constant in time (amplitude errors). The exact properties of the
86 Chapter 6 High-level modeling of Current Steering DACs

current errors (stochastic or deterministic) are not relevant at the moment. Then the nor-
malized pulse is
 
β
1
v̂(t, w) = u(t) I +
|w(m) − w(m − 1)| i= ∑ ∆Ii = u(t) I + ∆I(m,ˆ m − 1) (6.16)
α

and the output signal is described by

∞
s(t) = u(t) ⊗ ∑ ∆w(m) I + ∆I(m,
ˆ m − 1) δ (t − mTs ) (6.17)
m=−∞

Therefore, when the unit reference currents are not identical, and they do not de-
pend on time, the problem is degenerated to a typical PAM problem. In the form of
eq. (6.17), the conversion is given in a sum-of-differences . This equation defines that
for each sample value difference, a current that equals to the ideal ∆w(m)I plus an error
∆w(m)∆I(m,
ˆ m − 1) should be added. Each time, an error ∆w(m)∆I(m, ˆ m − 1) propor-
tional to the sample value difference ∆w(m) is added to the previously added errors. This
means that a memory effect appears in the Σ∆ description of the errors. Rewriting eq.
(6.17) in the following form
 
∞ w(m)
s(t) = p(t) ⊗ ∑ w(m)I + ∑ ∆Ii δ (t − mTs )
m=−∞ i=1
(6.18)
∞ ∞
= p(t) ⊗ ∑ w(m)I δ (t − mTs ) + p(t) ⊗ ∑ Ierr (m)δ (t − mTs )
m=−∞ m=−∞
w(m)
with Ierr = ∑i=1 ∆Ii it becomes evident that the specific problem can be described in a
transfer function that relates the error with the input signal.
The summation of unit errors into one current error dependent on the input signal, and
the PAM modulation caused by the error defines the horizontal error generation mech-
anism for this example. Notice how the time and signal independent current values ∆Ii
ˆ
result in a signal dependent error I(m) − w(m)I.

Example 2
Consider now that all unit current amplitudes are identical to each other, but the unit
transition shapes ui (t) are not. This corresponds to static spatially local errors. Let each
one be given by a time shift u(t − µi ) of the ideal transition shape u(t), for i ∈ {1, .., 2N −
1}. The normalized pulse is then given by
β
I
v̂(t, w) = ∑
|w(m) − w(m − 1)| α
u(t − µi ) = I û(t, w) (6.19)

where
β
1
|w(m) − w(m − 1)| ∑
û(t, w) = u(t − µi ) (6.20)
α
6.3 Functional error generation mechanisms 87

normalized transition with a few, and with many steps

Figure 6.11 Example of reduced pulses.

and the final output waveform is described by

∞
s(t) = ∑ I∆w(m)û(t, w)δ (t − mTs ) (6.21)
m=−∞

A graphical example of the normalized pulses for two different sample to sample tran-
sitions is given in fig. 6.11. Again, from a time and signal independent problem (fixed
delays per unit switching element) a data dependent error in the signal is caused. No-
tice the averaging effect that takes place during a transition. The transition that includes
many steps results in a better normalized transition. We can surmise that for a fixed res-
olution and fixed distribution of delays, the more the thermometer part of the converter
is increased, the more the averaging effect is increased and the better averaging effect
is caused during transitions. If the local errors are dynamic, e.g. they are related to the
input signal w, instead of being independent of it, then each one can be modeled with
u(t − µi , w) for i ∈ {1, .., 2N − 1}; in this case, a direct signal dependency introduced by
the individual transient shapes appears in addition to that via averaging.

Example 3
In this last example we will consider a slightly different scenario. All unit currents and
unit steps are taken identical to each other. However, the common shape uc (t) of all the
unit transition shapes ui (t) changes over time with the number of data signal transitions
(thermometric bits in this case) according to

ui (t, w) = uc (t − κ ∆w(m)) for all i

In other words, for each sample to sample transition all unit transitions of the elements that
change state are identical to each other, and all of them are delayed equally by κ ∆w(m).
88 Chapter 6 High-level modeling of Current Steering DACs

The normalized pulse becomes

β
I
|w(m) − w(m − 1)| ∑
v̂(t, w) = uc (t − κ ∆w(m)) = I · uc (t − κ ∆w(m)) (6.22)
α
and the output signal
∞
s(t) = ∑ I∆w(m)uc (t − mTs − κ ∆w(m)) (6.23)
m=−∞

In this example, the unit transition shape is modulated by the input signal (thus it
represents a dynamic timing error), before it remodulates the output signal in the signal
generation mechanism. The modulation of the timing error is made via the derivative of
the discrete time signal (∆w(m) over one sample period). Other types of dynamic errors
can be modulated in different ways, e.g. proportionally to the signal.

6.4 Conclusions
The CS DAC was described in several physical abstraction layers. With such an hierar-
chical description, it was shown that its behavior is parameterized to actual and hidden
signals with either functional or parametric role, to static physical parameters, and to
circuit parameters that have specific amplitude, time, spatial domain properties. Modi-
fication of the amplitude of these parameters and signals from their nominal values as a
function of the other domains results in errors in the actual signal pulses.
The errors inherit the properties of their origins, namely the parameters and signals
that determine their behavior. These error properties were defined and discussed. The
properties concern the amplitude, time, and spatial dimensions of the errors, the relation
with the signal, the static or dynamic behavior of their origin, and their stochastic or deter-
ministic nature. These properties gave rise to an error classification that showed that the
CS DAC architecture is plagued with errors that span all over the property spectrum, with-
out one class to have significantly more members than others. This explains conceptually
why it is so difficult to specify experimentally which error mechanisms are dominant for
the CS DAC, as for example it is possible to do in other architectures where a couple only
of error mechanisms are dominant at high frequencies.
In the final part of the chapter, the aim was to find a simple high level functional
description of the signal waveform that includes the hardware abstracted non-idealities
(e.g. the errors in the pulses) such that we can understand the complete error modulation
mechanisms for different error classes. To find such a description, a reduction method
was used founded on the concept of the normalized transition to translate the algorithmic
description of a specific circuit architecture (CS DAC without T/H) including errors back
to a generic functional one. The reduced functional description revealed the functional
error generation mechanism defined by this architecture, i.e. the mechanisms with which
abstracted problems of the amplitude, time and spatial domains mix together and affect
the output signal. The error modulation mechanisms of particular problems defined in
chapter 5 were given as examples.
 7

Functional modeling of timing errors

I N this chapter the equivalent timing error and the normalized transition concept will be
combined to translate the modified signal creation process of the timing error class into
a Pulse Width Modulation process. This provides a link with the branch of sampling and
interpolation theory that deals with non-uniform timing effects, thus facilitating insight of
the dynamic effects. The problem of non-uniform timing will be described, and relevant
sides of this problem will be addressed. In this way the link between communication
system, a D/A architecture, and its circuit problems will be established.

7.1 Non-uniform timing

In this section, first it is explained how the class of timing errors can be translated to a
non-uniform timing problem in the signal creation process. A brief description follows
of the basic aspects of non-uniform timing in sampling and reconstruction of signals that
will put the proposed functional CS DAC analysis in perspective of these theories.

7.1.1 The Equivalent Timing error of a transition

In the following, the details of the translation of the modified signal creation process into
pulse width and pulse position modulation are explained. Recall that eq. (6.15) states that

β
1
v̂(t, w) = ∑ Ii ui (t, w)
|w(m) − w(m − 1)| i=
(7.1)
α
89
90 Chapter 7 Functional modeling oftiming errors

where ui (t, w) is the transition shape of a unit switched current cell. A timing error distri-
bution modeled as µi produces the following normalized transition
β
1
û(t, w) = ∑
|w(m) − w(m − 1)| α
u(t − µi ) (7.2)

and an output waveform given by

∞
s(t) = I ∑ ∆w(m)û(t, w)δ (t − mTs ) (7.3)
m=−∞

After changing µi with µi (w) to expand the unit time delays from the static case to a
general signal dependent case, we calculate the induced charge in a transition from a
sample value w(m − 1) to the value w(m) using the normalized transition concept:
(m+1)Ts
Q(w(m), w(m − 1)) = I ∆w(m)û(t, w(m))
mTs
Ts β
1
= I∆w(m)
0
∑
|w(m) − w(m − 1)| α
u(t − µi (w))dt (7.4)

β
= I · sgn(∆w(m)) ∑(Ts − µi (w))
α

whereas the ideal transition would induce a charge equal to

Qideal (w(m), w(m − 1)) = I∆w(m)Ts

Subtracting the two we find

β
QE (w(m), w(m − 1)) = Isgn(∆w(m)) · ∑ µi (w) (7.5)
α

This charge is the error charge of the transition w(m − 1) → w(m). Consequently, it may
be mapped to an equivalent timing error TE :
β
QE w(m), w(m − 1) 1
|w(m) − w(m − 1)| ∑
TE (w(m), w(m − 1)) = = µi (w) (7.6)
∆wI α

The normalized transition is now transformed to

û(t, w) = u (t − TE (∆w)) (7.7)

The important result is that the output signal can be described now by
∞
s(t) = u(t) ⊗ I ∑ ∆w(m)δ (t − mTs − TE (w(m), w(m − 1))) (7.8)
m=−∞
7.1 Non-uniform timing 91

Equation (7.8) describes the translation of pulse shape errors to errors in timing. The
spectrum resulting from the two equations is similar, but not identical. This occurs be-
cause in the two equations the error power is distributed in time in a slightly different
manner. Nevertheless, it is still a meaningful translation, which is practice is expected to
cause only small error. In summary, the combination of the normalized transition and the
equivalent timing error concepts allows the translation of the modified signal generation
mechanism to a Pulse Width Modulation (PWM)1 problem enhancing even further our
insight on the effects of timing errors. Important conclusions of this transformation are:

1. The class of timing errors is described with PPM and PWM modulation, and can
be placed under the umbrella of non-uniform sampling and interpolation theory.

2. As the result of this unification, errors can be compared on the way this modulation
applies. Each specific member of this class generates an equivalent timing error
dependent on its other properties.

7.1.2 Non-uniform timing in the process of signal sampling

The problem of non-uniform timing can be distinguished in two parts; non-uniform sam-
pling of continuous time signals (related to A/D conversion), and the creation of signals
from their samples in non-uniform timing (related to D/A conversion). The study of
the sampling and interpolation cycle in view of practical implementation problems has
always been an important topic for sampling theory. One of its most important exten-
sions deals with the uncertainties introduced in the timing moments in which samples
are taken [117]. The physical processes that stimulated the generation of non-uniform
Amplitude

x(t) x(t)

time time
(a) (b)

Figure 7.1 (a) Non-uniform sampling and (b) uniform sampling with jitter.

sampling theory are plenty in nature. Non-uniform, or irregular measurements, occur

naturally in most applications of sampling theory such as optics [118, 119], tomography,
communications, oceanographic [120] and astronomical data measurements just to name
a few. For example, in oceanographic depth measurements [120] irregular sampling of
signals is caused by ocean waves that affect the depth at which measurements are taken.
1 PWM is often called Pulse Duration Modulation (PDM)
92 Chapter 7 Functional modeling oftiming errors

In astronomy, non-uniform sampling is the only way to obtain astronomical data because
signals are not always available for sampling.
Let us assume that the sampling operation is made in non-uniform timing moments as
depicted in fig. 7.1(a). The instants tm define a non-uniform sampling lattice and the sam-
ples are x(tm ). The lattice tm is described by various distributions dependent on the prob-
lem under consideration. For example, tm may vary periodically, it can be concentrated
in rare bursts with high intensity (many sampling moments closely located to each other
followed by large durations where the signal is not sampled at all. The lattice can also
be Poisson, Gaussian, or they may form a uniform lattice with small perturbations around
the ideal moments (timing jitter), or some samples may be missing. Typical implementa-
tion problems include burst jamming or sporadic equipment malfunction (causes missing
samples), phase noise in clocking circuits (adds timing jitter with Gaussian or Wiener like
properties) etc. Timing jitter is shown in fig. 7.1(b). The shaded areas indicate relative
small timing perturbation compared to the period Ts . Notice that non-uniform sampling
affects only the amplitude of the obtained samples x(tm ); that is, errors in the time domain
during sampling appear as errors in the amplitude domain of the signal x(tm ).
The literature on non-uniform sampling theory is enormous. Reviews on the topic
of non-uniform sampling covering bandlimited, non-bandlimited, bandpass and multi-
bandpass signals can be found in [121], in the books [118, 122, 123], and also in recent
literature [124, 125]. In brief, non-uniform sampling theory covers three main subjects

theorems and mathematical conditions for the representation of continuous time

signals x(t) from samples x(tm ) that are obtained non-uniformly in time.

Reconstruction methods to obtain the original signal from its non-uniform samples.

the relationship between the spectrum of the samples x(tm ), the reconstructed sig-
nal, having the non-uniform timing lattice timing properties as parameters.

Most relevant for A/D conversion are the last two subjects. Most of the theoreti-
cal results in this subject have appeared signal processing, communications, circuit- and
information-theory areas, but also in oceanographic research [120], astronomical mea-
surements, and in A/D conversion as a very specific case (Gaussian sampling jitter with
sinusoidal signals). It is interesting to mention that the mathematical treatments of the
non-uniform sampling theory available in literature have never been really incorporated
into the areas of A/D converters. Recent contributions in the A/D area [126] are still
neglecting the rich background existing in this area for more than four decades [127].
The shift nowdays toward signals resembling random processes rather than just single
sinusoids makes review of these results very relevant.

7.1.3 Non-uniform timing in the process of signal creation

The model that describes the signal creation process with non-uniform timing is shown
in fig. 7.2(a) and it is a straightforward extension of the model shown in fig. 1.1 and
7.1 Non-uniform timing 93

s(t)

z(m) DT pulse s(t)

h(t)
CT

non−uniform
timing
time
Σ δ (t−tm )
m

Figure 7.2 (a) signal creation with non-uniform timing and (b) example.

described by eq. 1.12. It is described by

∞
s(t) = h(t) ⊗ ∑ z(m)δ (t − tm ) (7.9)
m=−∞

for an arbitrary DT input signal z(m) and modified timing moments tm instead of mTs . For
simplicity, the samples z(m) are now expressed in current or voltage in comparison with
eq. (7.8) where the samples and the dimensionality constant are kept separate. This signal
is shown in fig. 7.2(b) using one of the many possibilities for pulse types. We may speak
of a Pulse-Position-Modulated (PPM) signal due to the timing errors tm − mTs , and Pulse-
Amplitude-Modulation (PAM) signal due to the signal values. The pulses are positioned
around the ideal moment, but their shape is not changed at all. Incorrect timing does not
result in a fixed error in amplitude, in contrast to non-uniform sampling.
The signal creation process with non-uniform timing lattices have been considered ex-
tensively in literature in the last decades for particular applications, especially for stochas-
tic uncorrelated jitter and rectangular pulses. For example, in [128] and [129] the authors
studied PAM signals with timing jitter for stationary stochastic and deterministic signals.
In [130] an analysis of the sequence of steps sampling, DT filtering and reconstruction
with stochastic jitter is presented. In communication theory textbooks (e.g. [80]) the spec-
trum of PPM and PWM (PDM) signals modulated by deterministic and random timing jit-
ter can be found as well. The Power Spectral Density (PSD) of Binary Pulse Streams with
stationary properties in the presence of independent uniform jitter is studied in [131, 132]
again with the model of fig. 7.2. Timing jitter in time-hopping spread-spectrum signals
has been studied in [133]; the analysis of this signal uses a lattice that includes the spread
spectrum modulation and the timing jitter. In [105] the spectrum that results using deter-
ministic input data with a deterministic non-uniform timing is studied in a black-box D/A
converter. If we put all these results next to each other, we see that

each one reveals a relationship between the created signal s(t), the samples z(m),
the pulse h(t), and the timing lattice properties. From an analysis perspective, the
center of gravity is on how the properties of the input signal and the pulse shape
affect the spectrum of the interpolated signal having the type of timing errors -
usually Gaussian jitter- as a parameter.
94 Chapter 7 Functional modeling oftiming errors

The main thing that distinguishes each analysis is the specific interpretation given
to the content of the samples z(m) in relation to the communication system used
and the pulse type, but generally not the type of timing errors.

From a synthesis point of view, the main degrees of freedom exploited are modu-
lation and line coding such that the available bandwidth of a channel is optimally
used under the constrains of timing errors.

Generic theory links the

Definition of the Modulation, filtering and other
signal s(t), the samples z(m)
signal’s properties operations by the architecture
and the elec. problems

D/A ALGORITHM
MODIFIED DAC
External signal source SIGNAL CREATION
FUNCTION
w1 DT/CT &
w2 modulation w(m) modulation, z(m) s(t) modulation, output
filtering filtering etc. modified filtering etc.
and encoding e.g. Σ∆
wN interpolation

non−uniform timing
vertical
modulation
Electronic circuit and physical layers

Figure 7.3 The link between the modified signal creation mechanism of the
DAC and system level aspects.

On the basis of the PWM description of all timing errors in the DAC, all existing
methods and results described previously can be adopted and facilitate the incorporation
of the DAC with its circuit imperfections into a generic system: in this way, abstract
system-defined signals are linked with specific CS DAC errors. This is shown in fig.
7.3. In this figure, an external to the D/A converter signal generator combines several
signals and creates w(m) which is applied to the D/A converter. The converter consists of
a DAC core, which is described with the modified signal generation mechanism, i.e. eq.
(7.8), and optional signal processing means that form the signal w(m) prior the DAC core.
The signal z(m) has different amplitude-time domain characteristics than the signal w(m).
Therefore, with respect to the original signal sources w1 , w2 , ... and the actual signal that
is converted, there are two types of processing operations. The errors introduced by the
DAC core error generation mechanisms depend on the actual properties of the signal z(m),
but in the scheme shown in the figure their results can be parameterized over the types
of signal processing operations introduced in the D/A architecture and the system using
the D/A converter. Optional modulation, filtering, etc. may follow after the signal s(t) is
created. Finally, although the modified signal creation mechanisms of eq. (7.8) has been
developed specifically for the CS DAC, in fact the scheme is much more generic.
7.2 Stochastic non-uniform timing analysis 95

Of vital interest for our purpose is the relationship between the spectral content of the
signal s(t) with the signal z(m) and its properties (time and frequency domain character-
istics, correlation, power, etc.), with the properties of the non uniform timing lattice, and
with the properties of the interpolation pulse h(t). The focus here will be placed on:

stationary random (stochastic) processes, or deterministic signals as inputs of the
DAC for timing errors modelled as a stationary random process with a general form
of correlation (not correlated with the signal);

deterministic signals combined with deterministic timing errors that can have cor-
relation with the signal;

arbitrary pulse types, focusing mainly in rectangular RZ and NRZ.

7.2 Stochastic non-uniform timing analysis

The analysis presented in this section assumes stationary timing errors and a ergodic and
stationary random process as an input. It is convenient to study the random modulation of
a PPM waveform with impulses instead of pulses, since PPM and PWM waveforms with
arbitrary pulse shapes are linear transformations of the results of impulse based wave-
forms [80]. Therefore, we formulate the general timing problem as

y(t) = 2 ∑ z(m)δ (t − mTs − µm ) (7.10)

n
s(t) = h(t) ⊗ y(t) (7.11)

Eq. (7.10) defines an impulse position modulation problem with delta impulses, and
eq. (7.11) shows the relationship between the impulse based signal with the pulse based
(PPM) signal for an arbitrary pulse shape h(t).

7.2.1 Correlated non-uniform timing

First, we give some definitions and notations according to [128]. The empirical autocor-
relation of a continuous time process is defined as the time average

1 D
R̂y (τ ) = y(t)y(t + τ ) = y(t)y(t + τ )dt
2D −D

and the probabilistic autocorrelation is defined as Ry (t,t + τ ) = E{y(t)y(t + τ )}. The

operation E{} defines the expectation with respect to the probability density function
(PDF) of the function under consideration. Then Ry (τ ) is the averaged probabilistic
autocorrelation and E{R̂y (τ )} the mean of the empirical autocorrelation. The same apply
for the spectrum of y(t); Sy ( f ), Ŝy ( f ) and Sy ( f ) are the probabilistic, the empirical,
and the averaged probabilistic power spectrum, respectively. For discrete-time processes
2
∑n = ∑∞
n=−∞ from hereafter
96 Chapter 7 Functional modeling oftiming errors

analogous formulas are used with the substitution of R(t,t + τ ) with R(m, m + q) and the
continuous time average with the discrete counterpart · = limN →∞ 2N+1 1 N
∑m=−N .
The random process y(t) from eq. (7.10) is not stationary in general. When the timing
errors {µm } are strictly stationary then y(t) is cyclostationary ( [128]). If {µm } is an
independent increment process, then y(t) exhibits no cyclostationarity. We assume that
the process {µm } is strictly stationary with correlation rµ (m, q), although for most cases
wide sense stationary is enough. The joint PDF of the timing uncertainties is cn−m (tn ,tm ).
The corresponding characteristic function is

Ck−l ( fk , fl ) = E{e− j2π ( fk µk + fl µl ) } (7.12)

where it can be shown that C0 ( f ) = 1 and |Cq ( f )| ≤ 1

To avoid loss of overview the details of the calculations are presented in appendix A.
It is shown that the power spectrum of eq. (7.10) is given by

1
Ts ∑
Sy ( f ) = Rz (q)Cq ( f , − f )e− j2π q f Ts (7.13)
q

The function Rz (q) = E{z(m + q)z(m)} represents the probabilistic autocorrelation of the
stationary random process z(m), and Rz (0) is its power. Eq. (7.13) gives us the power
spectrum of the impulse position modulated waveform that is subject to stationary timing
uncertainties for general statistical properties and correlation. From this solution we can
calculate easily the power spectrum of the interpolated signal with jitter for arbitrary pulse
shape. The general pulse shape defined with h(t) will be replaced by specific symbols
when we talk about the shape of specific pulse.
The power spectrum of s(t) that is found using eq. (7.11) and eq. (7.13). It is:

|H( f )|2
Ts ∑
Ss ( f ) = |H( f )|2 · Sy ( f ) = Rz (q)Cq ( f , − f )e− j2π q f Ts (7.14)
q

where |H( f )|2 is the Energy Spectral Density (ESD) of the pulse h(t). The characteristic
function Cq ( f , − f ) is one of the key factors determining the power spectrum of s(t).
If the timing error process is non correlated then the power spectrum is contaminated
with a continuous noise part. If it is correlated, then the result is generation of discrete
and continuous parts in the spectrum. The discrete part is usually described by Bessel
functions and appears at frequencies that depend on the correlation form and the sampling
carrier. Examples of the effects of correlation can be found in [127] (for the case of
sampling of signals with correlated jitter).
The results for deterministic signals are identical to those presented for random pro-
cesses. The same equations hold with the exception that in place of the probabilistic
autocorrelation function Rz (q) of the stationary random process z(m) the empirical auto-
correlation R̂z (q) is used (see appendix A).
7.2 Stochastic non-uniform timing analysis 97

7.2.2 White non-uniform timing

Further modifications can be made if we restrict the timing errors to be non correlated and
White. This generally proves sufficiently valid for most problems related to timing jitter,
which is a special case with great interest.
Because timing errors are uncorrelated, cn−m (tn ,tm ) = cn (n)cm (m) applies, and this re-
|H( f )|2
sults in Cq ( f , − f ) = |C( f )|2 for q = 0. Adding and subtracting the term Ts Rz (0)|C( f )|2
in eq. (7.14) we obtain

|H( f )|2 |H( f )|2 |C( f )|2 DT

Ss ( f ) = Rz (0)(1 − |C( f )|2 ) + Sz ( f Ts ) = N( f ) + S( f )
Ts Ts
(7.15)
where SzDT ( f Ts ) = ∑q Rz (q)e− j2π q f Ts is the PSD of the Discrete Time signal z(m). If z(m)
represents samples z(mTs ) of a CT waveform z(t) with PSD Sz ( f ) then eq. (7.15) becomes

|H( f )|2 |C( f )|2

Ts2 ∑
Ss ( f ) = Rz (0)(1 − |C( f )|2 ) + |H( f )|2 Sz ( f − q fs )
T (7.16)

s  

q

noise term N( f )
signal term S( f )

The power spectrum of s(t) consists of two frequency dependent terms; the signal
term S( f ) and the noise term N( f ). The signal term is selectively attenuated via the jitter
characteristic function |C( f )|2 . The noise term depends on |C( f )|2 , the pulse ESD, and
the total power Rz (0) of the discrete-time signal.
The characteristic function depends on the jitter process. The power shaped by |C( f )|2
degenerates to zero for low frequencies (|C( f )|2 → 1 for f → 0) and becomes equal to
one for high frequencies (|C( f )|2 → 0 for f → ∞). The higher the frequencies, the larger
the attenuation of the signal will be. At very high frequencies, the interpolated signal
consists of only noise since the signal PSD is attenuated to zero and the noise PSD is
maximized. For example, if the timing jitter is a stationary White Gaussian process, then
its characteristic function is |C( f )|2 = e−4π σ f , where σ 2 is the variance of the jitter
2 2 2

process. The attenuation vs. the normalized frequency f / fs is plotted in fig. 7.4.
The pulse h(t) has the same linear filtering effects on both the signal and noise terms.
Hence, it affects the absolute power levels of the output but it does not introduce relative
differences on the PSD’s of the signal and the noise term.
The fact that the noise PSD depends on the total power of the input signal indicates
that it may be dependent on input DC level. If the signal z(m) contains only a DC value
then we speak of a PPM train pulse modulated by jitter. For example, let the interpolated
signal be a PPM signal with no PAM modulation. Then all pulses have equal amplitude,
e.g. equal to one, and they are subject to timing jitter. It has been shown also in [80](pp.
280-284) and in [128] that the PSD of this PPM waveform is given by
|H( f )|2 |C( f )|2
Ts2 ∑
Ss ( f ) = (1 − |C( f )|2 ) + |H( f )|2 δ ( f − q fs ) (7.17)
Ts q
98 Chapter 7 Functional modeling oftiming errors

0.8

0.6
|C(f)|2

−3
0.4 σ=1e [sec]
σ=1e−2 [sec]
0.2

0 −1 0 1 2 3
10 10 10 10 10
f [Hz]

Figure 7.4 Attenuation due to white Gaussian jitter.

The images of the DC component located at multiples of the sampling frequency are
attenuated due to jitter while the DC component stays unaffected. Consequently, the
result is noise dependent on the signal DC level.
We will examine now the signal and noise parts of the power spectrum. The absolute
noise power in the Nyquist band fN is
fN 1
PN = Rz (0) |H( f )|2 (1 − |C( f )|2 )d f (7.18)
− fN Ts
Assuming that both H( f ) and C( f ) are symmetrical around f = 0 we can define the
proportionality coefficient χh ( f1 , f2 ) as
2 f2
χh ( f 1 , f 2 ) = |H( f )|2 1 − |C( f )|2 d f (7.19)
Ts f1

This coefficient defines the noise in units of Rz (0). The subscript h of χh ( f1 , f2 ) indicates
that this coefficient depends on the choice of the pulse. Because T1s |H( f )|2 is the (nor-
malized) averaged ESD of the pulse, χh ( f1 , f2 ) may be seen as the portion of the total
averaged energy (normalized) of the pulse located between f1 and f2 that becomes noise.
Using eq. (7.18) and eq. (7.19) the noise power in the band of interest is expressed as

PN = Rz (0)χh ( f1 , f2 ) (7.20)

Next, for a signal bandlimited to [ f1 , f2 ] we define

 f2 1
2
ψh ( f1 , f2 ) = |H( f )|2 |C( f )|2 Sz ( f )d f (7.21)
Rz (0) f1 Ts2
and express the signal power as

PS = Rz (0)ψh ( f1 , f2 ) (7.22)
7.2 Stochastic non-uniform timing analysis 99

The coefficient ψh ( f1 , f2 ) defines the absolute power of the signal term in units of Rz (0).
Obviously, if there is no jitter, ψh ( f1 , f2 ) is influenced only by the pulse. Knowing that
signal attenuation increases with frequency, the higher the power of the signal is dis-
tributed in frequencies within the Nyquist band, the smaller the factor ψh ( f1 , f2 ) becomes.
Consequently, the total power of the signal s(t) is

P = Rz (0)(χh ( f1 , f2 ) + ψh ( f1 , f2 )) (7.23)

and the SNR is

PS ψh ( f1 , f2 )
SNR = = (7.24)
PN χh ( f 1 , f 2 )

Until now no knowledge was required in advance on how information is encapsulated

in the signals z(m). However, because the noise in the signal s(t) is a linear function of the
power of the signal z(m), obviously the noise in s(t) becomes a function of the operations
used to generate z(m). Before we proceed in the main conclusions, it should be mentioned
that if the signal z(m) is White, then eq. (7.14) shows that the PSD of the signal s(t) is
not affected by jitter! The main conclusions so far are:

1. The PSD of the created signal s(t) consists of a signal part S( f ), which is an at-
tenuated version of the ideally created signal if there are no timing errors, and of a
continuous frequency dependent noise part N( f ).

2. The attenuation in the PSD S( f ) of the signal part, consequently the signal power
loss as well, is frequency selective. It depends on the characteristic function C( f ) of
the jitter. The signal power received at the output is PS and is expressed as a fraction
of the ideal signal power received without jitter using the coefficient ψh ( f1 , f2 ).

3. The noise PSD N( f ) depends linearly with the power of the signal z(m) applied
at the input of the DT/CT converter, but it does not depend on the way the power
is distributed in frequencies. The noise power PN due to jitter in a given band is
described as a fraction of the power of the signal z(m); that is, PN = χh ( f1 , f2 )Rz (0),
where χh is a dimensionless coefficient that depends on the sampling frequency, the
jitter characteristic function, the interpolating pulse ESD, and the band of interest.

4. The shape of the interpolating pulse affects linearly the total interpolated signal via
its ESD |H( f )|2 . Because this ESD applies equally well to both signal and noise,
the relative power of signal over noise stays the same, i.e it is independent on the
type of pulse that is used.

5. When the signal z(m) is the result of a signal processing from another signal w(m),
the noise generated is proportional to the ratio of powers between z(m) and w(m).
100 Chapter 7 Functional modeling oftiming errors

7.2.3 RZ and NRZ waveforms

The general relationship between samples z(m), interpolation function h(t) and the out-
put signal will be applied now to calculate the specific PSD for RZ and NZR rectangular
pulses with a specific signal w(m). RZ pulses (see fig. 7.5(a) ) require that the pulse
returns to zero for a portion of the sampling period. There may be two kinds of timing
problems in the realization of such pulses. In the first all pulses have same duration but
they are positioned in different moments with respect to the ideal ones. A PPM waveform
results and it is covered by eq. (7.14). Indeed, with the substitution of z(m) = w(m) and a
choice of the pulse h(t), eg. h(t) = pr (t) for a rectangular pulse, the general results of the
previous section apply directly. In the second case, each pulse has timing uncertainties in

s(t) s(t)

Figure 7.5 RZ (left) and NRZ (right) line coding.

both edges (rising and falling) and this generates a double sided PWM (PDM) waveform
(PDM2 ). PDM2 without amplitude domain modulation by the signal w(m) has been ana-
lyzed in [80]. To combine the signal and jitter modulation together, the model of fig. 7.2
requires some modifications. The calculations follow the same procedure as those shown
in appendix A.1, based on the analysis of sum of two delta pulse trains, modulated by the
same signal, but by different timing errors. The model is
∞
s(t) = u(t) ⊗ ∑ w(m) δ (t − mTs − µmr ) − δ (t − T0 − mTs − µmf ) (7.25)
m=−∞

where T0 is the duration of each pulse, µmr and µmf are the timing errors in the rising and
falling edge, respectively, u(t) is the unit step function.
Let us see now the case of NRZ pulses. For NRZ pulses the problem is described
as a PWM modulation. We use the general scheme of fig. 7.2 and 7.3 with h(t) = u(t),
and then assume that the signal w(m) is passed through a differentiator, such that z(m) =
∆w(m) = w(m) − w(m − 1). The output signal is described in a Σ∆ form
∞
s(t) = u(t) ⊗ ∑ ∆w(m)δ (t − mTs − µm ) (7.26)
m=−∞

where initial conditions have been set to zero (fig. 7.5(b) ). Notice also that ∆w(m) does
7.2 Stochastic non-uniform timing analysis 101

not have DC components.3

The results of section 7.2.2 are applied using z(m) = ∆w(m). To arrive to the desired
relationship between s(t) and w(m) the relationship between ∆w(m) and w(m) must be
examined. The power spectrum of the signal s(t) is described by

|U( f )|2  
Ss ( f ) = R∆w (0)(1 − |C( f )|2 ) + |C( f )|2 S∆w
DT
( f Ts ) (7.27)
Ts

DT ( f T ) =
where S∆w s ∑q R∆w (q)e− j2π q f Ts . and |U( f )|2 the PSD of u(t). The function R∆w (0)
is the power of the DT signal ∆w(m) of w(m). The autocorrelation of ∆w(m) is related
via R∆w (q) = 2Rw (q) − Rw (q − 1) − Rw (q + 1) with the autocorrelation of w(m), thus,

R∆w (0) = 2Rw (0) − Rw (−1) − Rw (+1) (7.28)

From the definition of the inverse Discrete Fourier Transform we have

1/2  
R∆w (q) = 2Rw (q) − Rw (q − 1) − Rw (q + 1) = Sw (λ ) 2 − e j2πλ − e− j2πλ e j2πλ q d λ
−1/2
1/2 1/2
= 2Sw (λ ) (1 − cos(2πλ )) e j2πλ q d λ = 4Sw (λ ) sin2 (πλ )e j2πλ q d λ
−1/2 −1/2
(7.29)

Consequently, the PSD of the DT signal ∆w(m) is given by

S∆w (λ ) = 4 sin2 (πλ )Sw (λ ) = 4 sin2 (πλ ) ∑ Rw (q)e− j2πλ q (7.30)

q

From this equation it can be seen that the PSD of the difference signal is obtained with the
filtering of the PSD of w(m) with 4 sin2 (πλ ). Consequently, the higher the frequencies
w(m) contains, the larger the magnitude of the PSD of ∆w(m) becomes. Applying these
results in eq. (7.27) and using |U( f )|2 = 1/(2π f )2 the PSD is translated to

1 1
Ss ( f ) = R∆w (0)(1 − |C( f )|2 ) + |C( f )|2 4 sin2 (π f Ts )SwDT ( f Ts )
Ts (2π f )2 Ts (2π f )2
1 (1 − |C( f )|2 ) 1
= R∆w (0) + |C( f )|2 |Pr ( f )|2 SwDT ( f Ts ) = N( f ) + S( f )
Ts (2π f )2 Ts
(7.31)

where |Pr ( f )|2 = Ts2 sin(π (fπT f)T2s ) is the ESD of a rectangular pulse pr (t) with duration of Ts .
2

3 The w(m) can have a constant derivative if increases or decreases continuously but only until it reaches the

maximum value allowed by w(m).

102 Chapter 7 Functional modeling oftiming errors

For the case that w(m) are samples of w(t), we have

1 (1 − |C( f )|2 ) 1
Ss ( f ) = N( f ) + S( f ) = R∆w (0) + 2 |U( f )|2 |C( f )|2 ∑ S∆w ( f − q fs )
Ts (2π f )2 Ts q

1 (1 − |C( f )|2 ) 1
= R∆w (0) + 2 |Pr ( f )|2 |C( f )|2 ∑ Sw ( f − q fs )
Ts (2π f )2 Ts q
(7.32)

This equation indicates that, had it been a scenario where the interpolation was made
with (individual) rectangular pulses pr (t) that have a fixed duration of Ts , then the signal
part’s PSD would be equal to the signal part generated with the NRZ method. However,
the noise part of eq. (7.32) depends linearly to the power of the difference signal of w(m).
If individual rectangular pulses where used, the noise power would be dependent on the
signal’s w(m) power. The power of ∆w(m) changes according to how the power of w(m)
is distributed within the frequency domain. This is a major difference between the NRZ
waveforms and any of the RZ ones. The impact of this difference is examined next.
The signal term contains a total power of

PS = R∆w (0)ψu ( f1 , f2 ) = Rw (0)ψr ( f1 , f2 ) (7.33)

with ψu ( f1 , f2 ) given by
 f2
2 1
ψu ( f1 , f2 ) = |U( f )|2 (1 − |C( f )|2 )S∆w ( f )d f (7.34)
R∆w (0) f1 Ts2

and
 f2
2 1
ψr = |Pr ( f )|2 (1 − |C( f )|2 )Sw ( f )d f (7.35)
Rw (0) f1 Ts2

The noise power is

PN = R∆w (0)χu ( f1 , f2 ) (7.36)

with χu ( f1 , f2 ) given using eq. (7.19):

2 f2 1
χu ( f 1 , f 2 ) = 1 − |C( f )|2 d f (7.37)
Ts f1 (2π f )2

Combining these equations, the total power at the output is written as

   
R∆w (0)
P = Rw (0) ψr ( f1 , f2 ) + χu ( f1 , f2 ) = Rw (0) ψr ( f1 , f2 ) + χu∆ ( f1 , f2 ) (7.38)
Rw (0)
7.3 Deterministic non-uniform timing 103

The symbol χu∆ ( f1 , f2 ) relates again the power of the noise at the output with the power
of the signal w(m). The notation used indicates that both the rectangular pulse shape
(subscript) and the assumed filter (Differentiator) affect its value. The SNR becomes

ψu ( f1 , f2 ) ψr ( f1 , f2 )
SNR = =  (7.39)
χu ( f 1 , f 2 ) R∆w (0)
χu ( f 1 , f 2 )
Rw (0)

The SNR depends now on the ratio of powers between the signal w(m) and ∆w(m). The
power of ∆w(m) varies according ot the spectral location of the power of w(m), and it
does not depend on the DC value of w(m).

7.3 Deterministic non-uniform timing

The analysis of timing errors that are deterministic, and in most cases exhibit a large
degree of correlation is made with the employment and adaptation a non-linear trans-
formation method proposed in [134] that translates the non-uniform timing lattice to a
uniform one. The input signal is deterministic.

7.3.1 Non-linear mapping of time domains

We recall that the signal s(t) is given by

s(t) = h(t) ⊗ y(t) (7.40)

where we have defined y(t) = ∑m z(m)δ (t − mTs − µm ). Similarly to the stochastic timing
case, it is sufficient to study the effects of timing in the function y(t) and then to give
proper meaning to the pulse h(t) and the signal z(m).
Based on simple reasoning4 , we change s(t) to

y(t) = z(t − µ (t)) ∑ δ (t − mTs − µ (t)) (7.41)

m

where µ (t) satisfies µ (mTs + µm ) = µm such that z(tm − µ (tm )) = z(m) = z(mTs ) and the
argument t − mTs − µ (t) to give zero at µm .
The equivalent timing error function was introduced as a transfer function between
DAC codes (or code transition) and the resulting timing error. For a given input signal
the equivalent timing error becomes a time series, too. Therefore, the time series µm
is the equivalent timing error as a function of m and it becomes important to establish a
method that relates µm with the timing modulation function µ (t), so as we can examine the
spectral impact of a specific problem. Given a proper 1 − 1 mathematical transformation
g : t → τ between the time domain t and a time domain τ , such that the non-uniform
4 In D/A conversion there is no sampling error as in A/D conversion, thus the input samples should maintain

their values. The factor −µ (t) makes sure that always the correct values z(m) are converted.
104 Chapter 7 Functional modeling oftiming errors

moments mTs + µm of t are mapped 1−1 to uniform moments mTs of τ , µ (mTs + µm ) = µm

can be changed to

θ (τ = mTs ) = µm (7.42)

where θ (τ ) = µ (t(τ )). Eq. (7.42) says that µm are the samples of a function θ (τ ) in the
uniform lattice mTs of the τ domain, or in other words that the uniform samples of µ (τ )
in the τ domain are the timing errors of the timing lattice in the t domain. The function
θ (τ ) can be written as
sin(ω0 τ )
(ω0 τ ) ∑
θ (τ ) = µm δ (τ − mTs ) (7.43)
m

which implies that θ (τ ) is bounded and bandlimited. When θ (τ ) is given in the form
Λ Λ
θ (τ ) = ∑ Lλ cos(2π fλ τ ) + ∑ Mλ sin(2π fλ τ ) (7.44)
λ =1 λ =0

the values µm are given by the samples of θ (τ ) at τ = mTs . Nevertheless, the point is that
µm and θ (τ ) are related in a very straightforward manner and it is usually these two that
are the first products of the encapsulation of a physical problem in a equivalent timing
error. Consequently, to find µ (t), which is the key to the impact of µm to the signal s(t),
we need to examine closely the non linear transformation from t to τ .
Such a non-linear transformation has been originally proposed in [134]. Further elab-
oration on the conditions for which it applies can be found in [135]. Let us take the 1 − 1
coordinate transformation

g : t = τ + θ (τ ), τ = γ (t) (7.45)

such that for τ = mTs , t = mTs + µm . The nonlinear transformation t = τ + θ (τ ), τ = γ (t)

transforms the points mTs + µm of the t-axis into the points mTs of the τ -axis. The inverse
function γ (t) exists because the transformation was assumed 1 − 1. Apparently, it is
natural to look if τ = γ (t) is of the form

γ (t) = t − µ (t) (7.46)

where µ (t) is bounded, based on what we have written in eq. (7.41). Indeed such a
transformation is valid given the conditions that
θ (τ ) µ (t)
< 1, and <1 (7.47)
dτ dt
which are not that restrictive (see [135]). It is easy to verify using eq. (7.45) and (7.46)
that θ (τ ) = µ (t), with τ being dependent to t. The next step is to express y(t) in the τ
domain. We notice that

y(t) = y(τ + θ (τ )) = yg (τ ) (7.48)

7.3 Deterministic non-uniform timing 105

In contrast to the case in [135], where the transformation is applied in the signal xs (t)
in the non-uniform timing in sampling, and in [134] where the same method has been
applied in the interpolation mechanism to correct errors that exist already in the sampled
values z(m), in our situation the coordinate transformation does not change z(m):

z(m) → zg (m), with z(m) = zg (m) (7.49)

Then in the τ domain we have

yg (τ ) = ∑ zg (m)δ (τ − mTs ) (7.50)

m

and with the substitution τ = γ (t) = t − µ (t) we go back to the t domain

1
y(t) = yg (τ ) = ∑(m)δ (t − µ (t) − mTs ) = z(t − µ (t)) ∑ e j·mωs (t −µ (t)) (7.51)
m Ts m

which is what we intuitively found in eq. (7.41).

The only question left is how to determine µ (t) from θ (τ ). We have found that
µ (t) = θ (τ ) but this equation is difficult to evaluate because the values of θ (τ ) at tm
are unknown. There exist several methods to determine µ (t) such as those proposed
in [80, 135], however, still from a practical point of view they are difficult to apply. For
example, given a timing error transfer function of the form Tε = Tε (y) we are able to
evaluate the timing errors µm = θ (mTs ) = Tε (y(m)) but it appears to be quite difficult
to obtain the exact timing modulation function µ (t) from µm . In practice, however, we
may allow the approximation µ (mTs + µm ) ≈ µ (mTs ) on the basis that the timing errors
µm will be significantly smaller than the period Ts and that the derivative of µ (t) will be
smaller than one. The approximation is equivalent to saying that µ (t) ≈ θ (t).
The impact of deterministic timing errors in the signal can be interpreted now. The
function µ (t) modulates the phase of the signal x(t) and of the sampling carrier fs , and
results in a typical phase, or frequency modulation problem. Bessel-function components
are created at multiples of the signal tones. The spectral properties of µ (t) and the de-
gree of correlation with the signal will determine the products that this phase modulation
generates. Our next task is to find a solution to eq. (7.41) for an arbitrary function µ (t).

7.3.2 Non-uniform timing in signal creation

The signal z(m) is

P P
z(m) = ∑ A p cos(ω p mTs ) = { ∑ A p e jω p mTs } (7.52)
p=1 p=1
106 Chapter 7 Functional modeling oftiming errors

(it has no DC components) and the timing modulation function is µm = M sin(2π f µ mTs ).5
The magnitude spectrum |Y ( f )| of y(t) is calculated in appendix A.2. It is given by

1 P
|Γ p,q,r (ω p M, mωs M)|
|Y ( f )| =
Ts ∑ ∑ 2
[δ ( f − fB (m, r) ± fA (p, q))] (7.53)
p=1 q,m,r

where Γ p,q,r (ω p M, mωs M) = B p,q (ω p M)Jr (mωs M), B p,q (ω p M) = A p Jq (ω p M), fA (p, q) =
f p + q f µ , and fB (m, r) = m fs + r f µ .
As expected, µ (t) produces Bessel components at frequencies given by the com-
bination of the signal tones at f p , the timing modulation frequency f µ , and the sam-
pling frequency fs . The magnitude of each component is dependent on Bessel func-
tions of the order of the component, the magnitude of the timing modulation M and
the frequencies contained in the input signal. A conceptual plot of based on a single-
sinusoidal input is given in fig. 7.6. The Fourier transformation of a pulse is defined

Magnitude
−f1 f1

−f1−f µ −f1+f µ f1− f µ f1+ f µ

−f1−2f µ −f1+2f µ f1−2f µ f1+2f µ

fs −fs/2 fs/2 fs
Frequency

Figure 7.6 Bessel products due to timing modulation.

with |H( f )|, therefore the magnitude spectrum of the signal s(t) is |H( f )||Y ( f )|. The
spectrum in fig. 7.6 is modified according by the spectral shape of the pulse’s Fourier
transform, |H( f )|. If w(m) is converted with rectangular RZ pulses we use z(t) = w(t),
h(t) = pr (t) whereas if NRZ pulses are used, we have to use z(t) = w(t) − w(t − Ts ) and
|U( f )| = |1/( j2π f | = |1/(2π f )| similarly to the stochastic case.

7.4 Conclusions
The combination of the equivalent timing error and the normalized transition concept
reveals that all problems that belong to the class of timing errors can be embodied in a non-
uniform timing process in the signal creation mechanism (D/A function). This simplifies
5 Having the single tone solution, the extension to multi-tone µ (t) is trivial.
5 Symbol M is used here locally. It should not be confused when in other places in the book is used as the
total number of steps of the DAC.
7.4 Conclusions 107

analytical calculations and it allows us to obtain insight of the modulation mechanisms of

dynamic errors. Some parts of this problems were addressed.
In particular, it has been shown that timing errors cause PPM and PWM (PDM) mod-
ulation dependent on the line coding used. It has been shown how all timing relevant
problems are united under a common modulation description and its effects were calcu-
lated. For correlated or deterministic timing errors, Bessel functions describe the discrete
frequency content of signal errors. For stochastic timing errors the spectrum consists of
both discrete and continous parts dependent on the nature of the correlation. For non cor-
related White timing errors the spectrum consists of a frequency dependent noisy term.
The input signal is a key factor that determines the output spectrum artifacts in all men-
tioned cases. Generally, what distinguishes each problem is the type of equivalent timing
error function that feeds into the PDM modulation mechanism which is a subject of the
application of this theory to specific problems.
To give better understanding one can consider the similarities of an FM system. Any
type of modulating signal that modulates the FM carrier creates a final waveform ex-
plained by the fundamentals of FM modulation, yet it is specific in its spectral content;
each modulating signal generates a specific final waveform whose spectral properties rep-
resent the signal source. In our case, each modulating signal is the result of a different
electronic problem that belongs to the same class: timing errors.
 8

Functional analysis of local timing errors

I N this chapter, a specific case of timing errors will be analyzed in detail from a func-
tional point of view. This error concerns relative timing inaccuracies. The functional
and some architectural issues of this error raised in chapter 5.2.5 will be addressed. Here
the focus is on the DAC core hardware in relation to the properties of the errors and their
relationship with the architectural parameters. The input signals are assumed sinusoidal.

8.1 Local timing error analysis

In this section a detailed functional analysis of spatially local random timing errors is
presented. The description of the problem was given in section 5.2.5. The analysis is
primarily focused on the relationship between the abstract timing errors of the individual
transients, the architectural parameters involved in the error generation mechanism, and
the errors in sinusoidal signals. It concerns mainly issues inner to the DAC.

8.1.1 Equivalent timing error calculation

Local timing errors are either spatially random or deterministic. A thorough investigation
of the random case will be presented in this section. We assign to each of the 2N − 1
unit DACs a timing error µ j , i ∈ {1, .., 2N − 1}. This means that during switching on/off,
each unit DAC delays a bit more or less according to its timing error µ j . In the ideal case
µ j = 0, or constant, for every j. The equivalent timing error for each sample to sample

109
110 Chapter 8 Functional analysis of local timing errors

transition is given by eq. (7.6)

w1
1
TE (w1 , w0 ) =
|w1 − w0 | ∑ µj (8.1)
j=w0

The equivalent timing error function is the average of all timing errors of the unit DACs
switching from sample w(m − 1) to w(m), and represents another manifestation of the
law of the large numbers. A more general way to see this effect, is to see it as windowed
averaging operation [136] where the window size is determined by the number of steps
involved, and by the type of coding applied to the DAC.
Each µ j is assumed an independent identical distributed variable with zero mean and
variance σ 2 . Eq. (8.1) defines a random variable, which is the mean of a set of identical
and independent random variables [128]. The variance of the TE will be

σ2
σT2E (w(m), w(m − 1)) = E{TE (w(m), w(m − 1))2 } = (8.2)
|w(m) − w(m − 1)|

The physical meaning of this variance is that when sample transitions include a large
number of unit steps the error converges to its mean value, which is zero in this case.
Therefore, for the same distribution of timing errors, the larger the number of unit ele-
ments, the better the averaging effect.

30

20
Timing error [psec]

10

−10

−20

−30
0 10 20 30 40 50 60 70
(a) element index

20
trial 1
15 trial 2
10 trial 3
T [psec]

trial 4
5
ε

−5

−10
0 10 20 30 40 50 60 70
(b) zero to code w step

Figure 8.1 Local timing errors (a) per element, and (b) equivalent timing error.
8.1 Local timing error analysis 111

Fig. 8.1(a) shows the four trials with Gaussian distributed errors (zero mean, and
σ = 10 psec) generated with MATLAB for a 6 bit thermometer DAC (63 elements). In
fig. 8.2(b) the equivalent timing errors are calculated using eq. (8.1). The x-axis of fig.
8.1(b) is a step starting from value zero, and ending at w for w ∈ {0, 1, ..., 63}. Each step
then uses ∆w = w − 0 = w elements. For small steps, the equivalent timing error is large
because only very few elements are used. In fact, the starting step will not start always
from zero, but this scenario is sufficient for demonstration. As the step-size becomes
larger, the average gets closer to its mean value (zero in this case). For roughly more than
20 elements per sample to sample step Tε becomes a smooth function of ∆w.
Let us consider now different thermometer DACs with resolutions ranging from 3 to
6 bits. The timing errors have the same properties (Gaussian, same sigma, zero mean)
and all DACs cover the same analog full scale: if IFS is the full scale current, the unit
current is I = IFS /(2N − 1). For a spread σ = 10 psec, representative distributions of
the timing errors are shown in 8.2(a). For each resolution N ∈ {3, 4, 5, 6}, 2N − 1 timing
errors are plotted. Then in fig. 8.2(b) the equivalent timing error function for each N for

30

20

10
µj [psec]

−10

−20

−30
0 10 20 30 40 50 60 70
element j

20
N=3
N=4
10 N=5
N=6
T [psec]

0
ε

−10

−20
0 10 20 30 40 50 60 70
number of steps

Figure 8.2 Spatially random local timing errors for several bit levels (a) error
per element and (b) equivalent timing error.

transitions between zero and a sample w is evaluated. As long as the number of elements
involved in transitions is comparable when different N are used, the equivalent timing
error shows similar hard-nonlinear behavior. However, the larger the resolution the larger
the averaging effect and the larger the region in which the TE is smoother.
112 Chapter 8 Functional analysis of local timing errors

The TE functions are plotted vs. the sample to sample steps normalized to the full
scale range of the DAC (IFS ) the benefits of increased averaging are seen easier. From

20
N=3
N=4
N=5
15 N=6

10

5
T [psec]

0
ε

−5

−10

−15

−20
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
output range

Figure 8.3 Equivalent timing error vs the normalized signal range.

fig. 8.3 we see clearly that as the resolution increases the equivalent timing error becomes
smoother, even for transitions that cover a small percentage of the full scale. However,
even for resolutions of 6 bits there is a significant percentage of the full range (10 − 20%)
that can be covered with a sample to sample step, in which the equivalent timing error
shows hard non-linear behavior. In other words, for smaller amplitude signals the effects
are much worse than in large amplitude signals, because their sample transitions include
only a few elements that reduces the averaging effect.
Before proceeding to the calculations of the impact of TE in the signal, a summary of
observations is given with respect to how the equivalent timing error is generated:

1. The equivalent timing error results from a windowed weighted averaging. The win-
dow is given by the number of switching elements, and the weighting factor is de-
termined by the coding scheme -thermometer in the examples shown. A windowed
weighted averaging belongs to the category of non-linear signal processing.

2. The implications of this functional behavior of the timing errors is interpreted via
the law of the large numbers: for a fixed distribution of local timing errors, the
larger the number of units employed to make a fixed analog output step, e.g. the
8.1 Local timing error analysis 113

larger the resolution, the √

smoother the equivalent timing error function is. This
means that TE depends 1/ ∆w as far as the relation with the signal is concerned.

3. Transitions with low normalized output amplitude result in hard-nonlinearity for

the equivalent timing error, whereas larger normalized amplitude transitions give a
smooth nonlinear behavior.

4. The key algorithmic issue that pops up is a re-arrangement of the elements such
that even for low amplitude steps the averaging is efficient.

8.1.2 Signal error calculation

The output signal is described by eq:

s(t) = u(t) ⊗ ∑ ∆w(m)δ (t − mTs − µ (m)) (8.3)

m

µ (m) = TE (w(m), w(m − 1)) (8.4)

Spatially random local timing errors generate harmonic distortion, and the harmonic prod-
ucts cause PDM effects. This means that there will be mixing products of the signal com-
ponents with the frequency components present in µ (m). In section 7.3 it was shown for
example how a single component f µ of a general µ (m) function is mixed with the fre-
quency components of the signal w(m). An obvious question is what kind of components
are present in µ (m) given in eq. 8.4.
If the function TE was a linear function of w(m), e.g. TE (w) = κ w, where κ is ex-
pressed in sec, then the content of µ (m) would be (spectral-wise) the same as that of
w(m) scaled accordingly, of course. However, for spatially local errors TE is a non-linear
function of w (see eq. (8.1), and the examples in fig. 8.1 and 8.2). Consequently, the
spectral content of µ (m) contains already more components than the signal w(m) does.
These components will modulate the components of the signal w(m) and the result will
be the generation of Bessel components as explained in the previous chapter.
The complexity of the transfer function TE (w(m), w(m − 1)) makes very difficult to
find a closed form solution of the spectrum with the straightforward application of µ (m) in
eq. (7.41) and (7.53). Under some assumptions, spatially deterministic local timing errors
prove to be more convenient for such calculations [79]. The problem can be circumvented
to a certain extend calculating the expected average error power. It should be pointed
out that random does not mean that noise is generated! The randomness of the cause is
reflected in the signal in that for every different IC sample (chip), different distortion levels
will be present in its normal operation for the same input signal; all IC’s will show spectral
distortion products at the same frequencies, but each one with different amplitudes.
Let us start by calculating the error per transition

TE (w(m), w(m − 1))

e(m) = ∆w(m) (8.5)
Ts
114 Chapter 8 Functional analysis of local timing errors

where the values w(m) are given in current. The probabilistic autocorrelation Re (m, n) =
E{e(m)e(m + m)} of e(m) with respect to the random variables µ j is given by

1
Re (m, n) = ∆w(m)∆w(m + n)RTE (m, n) (8.6)
Ts2

where

σ2
RTE (m, n) = min (|∆w(m)|, |∆w(m + n)|) (8.7)
|∆w(m)||∆w(m + n)|

is the probabilistic autocorrelation of TE . Obviously, for n = 0 the variance RTE (m, 0) =

σT2E (m, m − 1) given in eq. (8.2) results. The expected signal error power Re (m, 0) gives

∆w(m)2 σ2
Re (m, 0) = σT2E 2
= 2 |∆w(m)| (8.8)
Ts Ts

and the time averaged value of Re (m, 0) becomes

σ2
Pe = Re (m, 0) = |∆w(m)| (8.9)
Ts2

Eq. (8.8) gives the average power of the error signal caused by random local errors. Ob-
serve that the local error power is related with w(m) via |∆w(m)| , whereas for global
timing errors such as random White Gaussian jitter with NRZ pulses the error power
would depend on R̂∆w (0) = ∆w(m)2 (local errors are described by averaging whereas
global errors are not). This is precisely the result of different modulation that each sub-
class of timing errors grings as discussed in the concluding remarks of chapter 7.
The total power of the error signal will be calculated next, when the input signal is
given by the Fourier series
P
w(m) = { ∑ A p e j2π mλ p } (8.10)
p=1

where {x} is the real argument of x. The autocorrelation function R̂w (q) of w(m) is

P A2p
R̂w (q) = ∑ cos(2π q f p Ts ) (8.11)
p=1 2

After the calculations of the term |∆w(m)| we find

P
|∆w(m)| = ∑ 2A p | sin(π f p Ts ) sin(2π f p Ts (m − 1/2))| (8.12)
p=1
8.1 Local timing error analysis 115

Because the signal frequencies are bounded in the Nyquist range, it can be found that

P
sin(π f p Ts )
Pe = σ 2 fs2 ∑4 π
Ap (8.13)
p=1

The Signal to total Distortion ratio (SDR) is then calculated as

sin2 (π f p Ts )
∑ p=1 A2p /2 (π f p Ts )2
P
Ps
SDR = = (8.14)
Pe 4σ 2 fs2 /π ∑Pp=1 sin(π f p Ts )A p

where we have counted in the signal power the loss due to the sinc function, since it is
counted in the signal error power as well. A practical formula is obtained if we assume
that the input signal is a full scale single sinusoid with f1 << fs . Then its amplitude is
A = 1/2(2N − 1) 2N −1 , where N is the resolution of the assumed DAC. Then the SDR
is greatly simplified to

A1
SDR = (8.15)
8 f1 fs σ 2

and then easily translated in dB to

80 85

75 fin=0.01 N=3 80 fin=0.01 N=5

SDR in dB

SDR in dB

70 75

65 70

60 65

55 −3 −2
60 −3 −2
10 10 10 10
σ/Ts σ/Ts
90 95

85 fin=0.01 N=7 90 fin=0.01 N=8

SDR in dB

SDR in dB

80 85

75 80

70 75

65 −3 −2
70 −3 −2
10 10 10 10
σ/Ts σ/Ts

Figure 8.4 SDR for spatial random errors. Circles: average simulated values.
Bars: 3σ spread. Crosses with dashed line: Theoretical values.
116 Chapter 8 Functional analysis of local timing errors

SDR = 3.01(N − 1) − 10 log10 (σ 2 f1 fs ) − 9.03 dB (8.16)

From eq. (8.16), we see that the SDR depends on three parameters: the number of unit
transitions that cover the full scale signal range (expressed as a function of N), the timing
errors (σ ), the signal frequency f1 , and the sampling rate fs . The SDR

increases 3 dB per extra bit, under the assumption that the errors are fixed with N;

reduces 20 dB/dec with the spread σ ;

reduces 10 dB/dec with the signal and sampling frequencies.
The comparison of theory and simulations is demonstrated in fig. 8.4. The simulations
are based on MATLAB code that models the individual time delays of each thermometer
transition. For each mean value shown in the figure, 50 runs were considered. The vertical
lines show the 3σ spread of the SDR. If f1 is fixed within a fixed Nyquist frequency band
fN , and the sampling rate scales with fs = 2 fN · OSR then

SDR = 3(N − 1) − 20 log10 (σ ) − 10 log( f1 fN ) − 10 log10 (OSR) − 12.03 (8.17)

Therefore, the SDR drops with 3 dB when the OSR doubles. Observe that this result
declares exactly the opposite behavior with respect to clock jitter error power, that reduces
by 3 dB when OSR doubles!
The SDR given in eq. (8.17) assumes a sinusoid that fits to the full scale range of
the DAC. When a full scale signal is used to demonstrate the SDR of the DAC for errors
that have a significant dependence with the digital input amplitude, then the results show
only a best case situation. We have seen in section 8.1.1, the larger the number of ele-
ments involved in a transition, the better the transition errors average; in the signal, if the
amplitude A1 of the sinusoid doubles, the SDR improves by 3 dB.

8.2 High level architectural parameter tradeoffs:

segmentation
In this subsection high level tradeoffs in segmented CS DACs will be discussed. It is
indeed desirable to use the high level analysis results in design methodology defining
simple formulas that can guide a designer for the optimal level of architectural parameters
when there is a set of specifications available. However, one should be very careful not to
come to early conclusions unless the electronic issues of timing error generation are very
well understood. Otherwise, significant misinterpretation of the high level analysis can be
made. This section examines briefly how this can happen, and defines the specific goals
of the analysis that follows in the next chapter.
In a CS DAC a major architectural parameter is the number of bits in the partitioning
between thermometer and binary segments. This is called segmentation. In [8] a design
methodology is proposed to exploit optimally this degree of freedom to satisfy optimally
8.2 High level architectur al par ameter tradeoffs: segmentation 117

the combination of three signal error properties (INL, DNL and THD), and two physical
properties (silicon area and power consumption). Several subsequent articles have applied
this method, e.g. [41, 137]. Others [138] tried to extend the approach.
In the mentioned articles DNL and INL were related to limitations in matching, and
segmentation was assumed a parameter that scales matching impact on them (in fact, the
INL remains uninfluenced). The THD was related only to MSB-LSB glitch errors, which
are a particular case of local timing errors. The local timing errors in the thermometer
part were unknown to the authors. The method proposed was based on the knowledge of
how each associated property (INL, DNL, THD, area, power consumption) scales with
the degree of segmentation.
In a segmented DAC, the most significant of the MSB-SLB glitches occur at the tran-
sition between the MSB of the binary segment and a thermometer bit. In the thermometer
segment the error is related to the input signal via a windowed average of all individual
errors involved in a sample to sample transition. In the binary segment the error depends
strongly on the whether the major carry bit changes or not. The effects are here weighted,
with the MSB bit causing an error in direct proportion of its weight. In [8] it is stated
that the THD (SDR is the inverse of THD in the terminology adopted here) reduces with
6 dB every time there is one extra binary bit translated to thermometer bit. This holds
because every additional bit halves the error magnitude in the MSB-LSB transition. In
the thermometer segment,√ every additional thermometer bit improves the averaging of its
associated local errors by 2, thus 3 dB reduction in THD (increase in SDR).
However, this scaling is valid only if for every extra thermometer decoded bit the tim-
ing difference between binary weighted transients stays the same. It is not strange that
in practice this can not be taken for granted. The same applies for the errors of the ther-
mometer segment; we have already insisted that the SDR benefits hold only when timing
errors stay the same when N scales. This is a key-point that needs further discussion.
Let us consider two scaling scenarios with the segmentation as a parameter. Consider
a converter with N bits, NB of which are binary and NT thermometer. Let the binary bits
be ideally synchronized with each other, and assume that the thermometer data have local
timing errors described with a Gaussian distribution. If by scaling the thermometer-binary
ratio up the timing error variance stays the same, the results of the previous subsection
apply. However, in practice it is most likely that by changing the segmentation, the errors
will be different. How different can they be?

1. There may be a qualitative change in the error properties. For low NT /NB ratio the
local timing errors are dominated by one origin, and for a larger ratio by another.
For example, for a few thermometer bits, the number of clock lines is small and
can be designed with great precision. In this case, mismatch in switches (spatially
random) dominates. For many thermometer bits the clock network is much more
difficult to design, thus possibly clock skew dominates (e.g. spatially deterministic).

2. There may be a quantitative change in the error values; for every other NT /NB ratio
the same origin dominates but with different magnitude in each time. For exam-
ple, the local timing errors may be dominated by mismatch in the clocked buffers
118 Chapter 8 Functional analysis of local timing errors

and the current switches, however, for every other ratio different error variance ap-
plies. This is very likely to happen because when ratio NT /NB is changed, many of
the building block device properties (switch W/L ratios, conducting currents, gate
capacitances) change as well for every other ratio selected.

3. There may be no difference at all, if with the employment of proper design means
the local timing error properties and spread values remain the same.

If the second case applies such that every time the segmentation increases with one bit,
the timing error per element increases as well, for example by
√
σ (N) = σ 2N

then eq. (8.16) is modified to

SDR = −3(NT + 1) − 10 log10 (σ 2 f1 fs ) − 9.03 dB (8.18)

which proves wrong any careless application of eq. (8.16): instead of gaining 3 dB in
SDR per extra thermometer bit, there is a penalty of 3 dB.
This simple, yet representative example highlights strongly that in order to be in the
position to formulate correct IC design guidelines, the lower hierarchical layer aspects of
local timing errors must be known first, and especially their relationship to the architec-
tural and process parameters.

8.3 Conclusions
The high level modeling concepts of the class of timing errors that were developed in the
previous two chapters were applied to this chapter to analyse at a high level spatially local
timing errors (relative timing inaccuracies). This error is a specific member of this class.
The analysis was made from an signal-architectural angle focusing mainly on the re-
lation between sinusoidal signal properties, distortion, the number of thermometer bits,
and the timing error properties. Three main aspects of this error mechanism were ana-
lyzed: the equivalent timing error for abstract DT input signals that showed the windowed
averaging effect of this mechanism; the distortion caused in sinusoidal signals in relation
to the number of bits of the DAC, the sinusoidal signal properties and the sampling rate;
and the high level architectural parameter tradeoffs with respect to segmentation. Finally,
it was shown that before a high level analysis of local timing errors can give IC design
guidelines, it has to be combined properly with knowledge of the circuit mechanisms
that generate these errors, and the links of timing errors with process parameters, circuit
topologies, architectural parameters. This is the analysis of the vertical error generation
mechanisms of local timing errors, and it is the main topic of the next chapter.
 9

Circuit analysis of local timing errors

I N this chapter, local timing errors are analyzed in circuit details. An analysis with lin-
ear behavioral models will show first the main dependencies of these errors with the
circuit parameters and hidden signals of the DAC subcircuits. Second, a similar analysis
at transistor level for some circuits will show the error generation mechanisms and the in-
fluence of device properties and circuit topologies. Finally, circuit and functional analysis
will be combined to reveal tradeoffs between signal properties, architecture, design and
process parameters, and power consumption.

9.1 Circuit analysis with linear models

This section describes the circuit mechanisms with which local timing errors are generated
in the DAC. It consist of two parts, which are briefly explained.
In fig. 9.1 a chain of elements is shown that consists of a clocked data element, a
driver, and a SI cell. The CS DAC consists of multiples of these chains that are connected
together at their outputs. In the first subsection, using simple circuit behavioral models
for each block and RC networks for their intermediate nodes, the local timing errors
generated when these simple parameters vary and when offset in their transfer curves is
added will be calculated. This shows the principle dependencies of timing errors with the
circuit parameters and with the properties of the signals of the intermediate nodes.
In the second subsection, transistor details of some circuits and the clock intercon-
nection network are investigated. In practice circuit parameters relevant for local timing
errors are interdependent at the transistor level, and also dependent on process parameters.

119
120 Chapter 9 Circuit analysis of local timing errors

chain of switching elements

clock distribution
output

network
Global Clocked
Driver SI cell
clock driver data element

data

Figure 9.1 A chain of elements.

9.1.1 Circuit behavioral-level analysis of timing errors in a chain

The model shown in fig. 9.2 will be used to calculate the errors in chain. It consists of a
voltage-driven SI cell, a voltage driver, a clocked data element, e.g. a latch, and a clock
driver. The model includes several circuit imperfections: the offsets and time constants
before the blocks, and time constant at the output of each individual SI cell. This time
constant is created by the wires connecting all chains together at the output.

clocked data
CC element C2 SI cell R0 C0
RC R2 Driver C1
Voff3 Voff2 R1 Voff1
+− CK Q +− + +− +
φ(t) φ L(t) x(t) AD z(t) Gm i(t) v(t)
global local
CKb Qb − −
D
RC R1
CC R2 C2 C1 R0 C0

∆ t Total

∆t L ∆t D ∆t S ∆t W

Figure 9.2 Inner chain node behavioral modeling and timing error definitions.

We will calculate now the timing error ∆tTotal at the output due to the timing errors
∆tL , ∆tD ∆tS and ∆tW which are the individual contributions due to imperfections in clock
and latch, driver, switches, and the summing network interconnect, respectively. In each
case, the timing error is modeled by a delay introduced by the combination of the time
constant at the input of the block and the comparison level, an extra delay introduced by
offset, or by an integrated error introduced only by a time constant (see fig. 9.3). The first
error is a global error, as long as the time constants have no mismatch; their only effect
is to reduce the maximum sampling rate. The second error (offset-induced) and the effect
of mismatch on the time constants are local errors. Additional errors can be caused by
the finite values of the gains of each stage (AD , Gm, etc.). In fig. 9.4 several chains are
included. Global delay are indicated with the horizontal arrow, and local errors with the
9.1 Circuit analysis with linear models 121

ideal transition
Voltage
y(t) z(t) transition limited by RC
offseted comparison level Voff0
+−
+
nominal comparison level y(t) z(t) Gm
−

due to RC constant Time

time delays:
due to offset in the
decision point

Figure 9.3 Modeling of timing errors.

vertical ones. First, the global errors will be calculated, and later on the local ones will be
split off.
global errors (the same for all chains)

Latch Driver SI cell

CK Q + +
AD Gm
CKb Qb − −
local clock

D
Output summing RC network
Clock distribution network

T1 RL

output

RL
local clock

Latch Driver SI cell

+
clock driver

CK Q +
AD Gm
CKb Qb − −
D
A
+

T 2NT −1
global clock φ(t)
local errors (from chain to chain)

Figure 9.4 Circuit model of the DAC consisting of multiple chains.

Global errors
The model shown in fig. 9.3 applies to all intermediate nodes of the chain. The calcula-
tions are made for the differential signal. ∆tS is used for global errors, and ∆ts is left for
local errors (similarly for the other nodes). For global errors no offset is assumed.
122 Chapter 9 Circuit analysis of local timing errors

First, ∆tW is calculated. The cell generates steps from −Iu to Iu . Gm is assumed
infinite such that its output is a step current transient. For a step signal z(t) from −VD
to VD , the transient v(t) depends on τ0 = R0C0 . R0 is the parallel combination of the SI
cell output resistance, and the sum of the load resistor RL and the resistance seen by a
chain at its path to RL due to interconnection wires. Usually R0 ≈ RL . The capacitance
is contributed by the output capacitance of all SI cells (assumed constant when the cell
switches on and off), and by the interconnect capacitance. It can be expressed as

C0 = CInt + (2NT − 1)CSI (9.1)

where CSI is the contribution of each SI cell, and CInt the contribution by interconnect
capacitance. Then, v(t) = −Iu RL + 2Iu RL (1 − e−t/τ0 ) and the delay is easily calculated as

∆tW = τ0 ln(2) (9.2)

In the second step, ∆tS due to τ1 = R1C1 is calculated. The capacitance C1 and resistance
R1 are mainly determined by the driver and the SI cell and less by interconnecting capac-
itances. Initially, a step controlled saturated driver is assumed; the signal x(t) is a step
signal from −VL to VL starting at t = 0, and the output of the driver goes from −VD to VD
at t = 0. Then,

z(t) = −VD + 2VD (1 − e−t/τ1 ) (9.3)

∆tS = τ1 ln(2) (9.4)

which depends only on τ1 = R1C1 . If a step controlled non-saturated driver is considered,

the combination of the latch swing and driver gain adds to the effects, but still not the time
constant R2C2 . The result is the same timing error but different z(t):

z(t) = −ADVL + 2AVL (1 − e−t/τ1 ) (9.5)

∆tS = τ1 ln(2) (9.6)

The third step is to assume a slope controlled non-saturated driver, thus x(t) is now limited
by τ1 = R1C1 . Using the inverse Laplace transformation we find

ADVL − 2ADVL ( τ τ−1τ e−t/τ1 − τ τ−2τ e−t/τ2 + 1) τ1 = τ2
z(t) = 2 1 1 2 (9.7)
ADVL + 2ADVL (1 − (1 + t/τ1 )e−t/τ1 ) τ1 = τ2

which holds when x(t) and z(t) do not reach the saturation limits. Assuming for simplicity
τ1 = τ2 the total delay ∆tD + ∆tS is defined by the implicit function tx = τ1 ln(2) + τ ln(1 +
tx /τ1 ), where tx defines the zero crossing moment of z(t), thus

∆tD = τ2 ln(2) and ∆tD + ∆tS = tx (9.8)

Finally, the contribution ∆tL due to the clock node time constant τC = RCCC is added
(all latches receive the same clock signal). The capacitance CC on a global clock node is
9.1 Circuit analysis with linear models 123

the sum of the local input load capacitances of the latches CL , the output capacitance of
the clock driver CCD , and the capacitance of the clock interconnect network CInt,C :

CC = CInt,C +CCD + (2NT − 1)CL (9.9)

The resistance RC is mainly determined by the output resistance of the clock driver.
For a slope controlled latch that saturates instantly at the zero crossing level, its output
is always a step from −VL to VL . In this case, for a step clock signal from −VCD to VCD :

∆tL = τC ln(2) (9.10)

The total error becomes

∆tTotal = ∆tW + ∆tS + ∆tL = ln(2)(τ0 + τ1 + τ2 + τC ) or, (9.11)

∆tTotal = ln(2)(τ0 + τC ) + tx (9.12)

for infinite gains for each block, and finite gain at the driver, respectively. If the latch has
finite gain, one needs to calculate the total time delay imposed by the three time constants.

Local errors
Local timing errors are mainly caused by the following mechanisms;

different offsets between identical blocks of different chains;

mismatch in the time constants in the nodes of different chains;

contribution of the clock distribution network time delays between local clock sig-
nals and mismatch in local clock time constants).

mismatch of gains of blocks between chains leading to slope variations that are
translated to skew by subsequent comparisons.

Only offset based errors will be calculated and the remaining will be briefly discussed.
Using the model shown in fig. 9.3 SI cell timing errors due to offset are written as

Vo f f 1 Vo f f 1
∆ts = = (9.13)
dz(t) Sz (t)z=0
dt z=0

which is a function of the slope Sz (t) of z(t) near z(t) = 0. This equation can be applied
to all offset relevant nodes of the chain. It relates the timing error introduced by offset in
a switching circuit to the slope of its input signal, and to the offset voltage of its decision
point (zero crossing for differential operation): the faster the input signal transition will
be, and the smaller the offset compared to other similar circuits of other chains, the smaller
the timing error. It is often called the “zero crossing approximation”.The total timing error
124 Chapter 9 Circuit analysis of local timing errors

is due to offsets contributed by the clocked element, the driver, and the SI cell. Using the
previous equation it can be written as

Vo f f 1 Vo f f 2 Vo f f 3
∆ttotal = ∆ts + ∆td + ∆tl = + + (9.14)
Sz (t)z=0 Sx (t)x=0 SφL (t)φL =0

We will find the zero crossing slopes at each node and apply eq. (9.13) to calculate
the individual contributions. For the step controlled saturated driver eq. (9.3) gives

VD −t/τ1
Sz (t) = 2 e (9.15)
τ1
Sz=0 (t) = VD /τ1 (9.16)
Vo f f 1
∆ts = τ1 (9.17)
VD

The last equation shows that the timing error between SI cells, when their input signals are
the same, is proportional to the magnitude of the individual offsets switches, proportional
to the time constant of their inputs z(t) and inversely proportional to their input swing. A
numerical example shows that if τ1 = 100 psec (rise time 2.2τ1 = 220psec), VD = 600mV,
Vo f f 1 = 10mV, then the timing error is ∆tx = 1.65 psec. This indicates how significant
this timing error can be. Notice that as long as the driver’s swing is increased while τ1
remains the same, the slope increases, thus the timing error reduces. If we assume that
the driver is a Gm stage that delivers a current ID to the parallel combination of R1 and C1
(VD = ID R1 ), then eq. (9.17) is translated to

C1
∆ts = Vo f f 1 (9.18)
ID

and shows that extra current, hence power, can be used to reduce the error.
In the case of the step controlled non-saturated driver, eq. (9.5) and (9.13) give

VL −t/τ1
Sz (t) = 2AD e (9.19)
τ1
Vo f f 1
∆ts = τ1 (9.20)
ADVL

If the gain of the driver or its input signal magnitude is increased, the R1C1 network’s
excitation magnitude increases and the timing error reduces. In reality, neither the signal
x(t) is a step, nor the driver and switches turn on instantaneously. These effects increase
the timing errors and reveal the importance of using gain to reduce timing errors.
Next, the local timing errors for the slope controlled non-saturated driver are calcu-
lated considering both errors ∆td and ∆ts from the driver and SI cell, respectively. The
9.1 Circuit analysis with linear models 125

slopes of x(t) and z(t) are calculated from eq. (9.7) as

VL −t/τ2
Sx (t) = 2 e (9.21)
τ2

2ADVL τ −1 τ (e−t/τ2 − e−t/τ1 ) τ0 = τ1
Sz (t) = 2 1
(9.22)
2ADVL τt2 e−t/τ1 τ0 = τ1
1
(9.23)

Assuming for simplicity that τ1 = τ2 we see that the slope of z(t) is by t/τ1 different from
the slope calculated when the input of the driver is a step function. We observe that for
t < τ1 the slope is slower than in eq. (9.19) and for t > τ1 it becomes higher. The timing
error calculations give
Vo f f 2
∆td = τ2 (9.24)
VL
Vo f f 1
∆ts = (9.25)
2ADVLtx /τ12 e−t/τ1

where tx = τ1 ln(2) + τ ln(1 + tx /τ1 ) is the same as before. As expected, dependent on

when the zero crossing of z(t) is reached, the result of the combination of two time con-
stants involved via the driver’s gain stage can be of advantage or disadvantage (if the
decision point can be positioned at the steepest region, the local error is reduced but the
global delay increases). A similar optimization situation occurs in the design of gain
stages to minimize of the offset of comparators in A/D converters [88].
Next, the timing error contribution of the latch is calculated (latch with infinite gain):
Vo f f 3 Vo f f 3
∆tl = τC = (CInt +CCD + (2NT − 1)CL ) (9.26)
VCD ICD
Once more, the larger the slope, the less the timing error introduced. In this case, the
slope depends on the number of total chains, and the capacitance contribution of each one
to the clock node. The total offset based timing error becomes
Vo f f 3 Vo f f 2 Vo f f 1
∆ttotal = ∆tl + ∆td + ∆ts = τC + τ2 + (9.27)
VCD VL 2ADVLtx /τ12 e−t/τ1
This equation applies for instantly saturated latch, non-saturated driver and τ1 = τ0 .
For errors generated due to mismatch in time constants between chains only one ex-
ample will be given at the driver SI cell node. The rest can be calculated similarly. Assume
that there is a mismatch in the nominal time constant τ1 between two chains, leading to
τ̂1 = τ1 + ∆τ1 for one of them. Then the zero crossing is delayed by

∆ts = ln(2)∆τ1 (9.28)

that translates to skew at the output of the SI cell. This calculation states that the timing
error is independent on the excitation of the corresponding RC network, and depends only
126 Chapter 9 Circuit analysis of local timing errors

on the time constant. For example, if the nominal value of τ1 from the previous example
has a mismatch of 1% (5 psec), the timing error equals roughly 0.7 psec. However, if the
swing is modified (e.g. ID from different drivers have mismatch, thus for the same R1 ,
their VD ’s change) then no timing errors are generated.
It was mentioned earlier in this subsection that the clock network can generate timing
errors based on different local clock slopes, and those based on local delays. The former
translate to timing errors by the comparison of the clocked elements and their calculation
follow eq. (9.28). The latter do not depend on chain-clock interaction. We call both clock
skew because they cause skewed clocking of the clocked elements.
Clock skew is a function of interconnection network topology, material properties,
etc. Consequently, local timing errors are depend on whether or not the paths from the
global to the local clock distribution points are identical in length, physical, and electrical
environment. As a result of this, they can not be reduced by spending more power at their
driving circuits. This forms a major difference compared to the errors introduced by the
imperfections of the circuits of chains. Similar considerations can be placed for the output
summing network. Finally, local timing errors due to mismatch in gains between different
drivers, SI cells, etc. from different chains can lead to timing errors.
In summary, offset based timing errors depend on the offsets of each switching cir-
cuit, and the slopes of their driving signals, which depends on the time constant and the
amplitude of the signal applied to it. In real circuits the gain of the driving circuit can
reduce offset based timing errors of the circuit it drives. Time constant mismatch at the
inner chain nodes translates to time delays and can have a important contribution to the
total sum of local timing errors. For both types of errors, as long as the resistances of the
inner nodes are determined by the driving circuits, current can be traded for lower timing
errors given a constant swing.

9.1.2 Transistor level analysis

The analysis presented in the previous section provided a rough estimate of the relevant
factors for the generation and magnitude of timing errors. In practice, the situation is a bit
more complicated. Timing errors depend on the dynamics of transistor operation, circuit
dynamics of specific topologies for drivers, latches and also there is a certain extend
of interdependence between the circuit parameters described via transistor parameters
(dimensions, biasing currents, etc.). In this section insight is given on these issues.

SI cell switches

The switches of the SI cell are responsible for a couple of local timing errors. In the
following paragraphs we analyze in transistor level details these timing errors. MOS
switches give rise to two different mechanisms for timing errors.

1. Timing skew determined by the threshold mismatch. This phase is important both
at the switch-on and -off phases. It is related to the offset based timing errors.
9.1 Circuit analysis with linear models 127

2. Current pulse slope variations determined by channel charging time variations due
to mismatch. This mechanism applies at the phase a switch transistor is turned on.
It is related to mismatch in the gains of the SI cells.

The first mechanism is considered first. A differential switch depicted in fig. 9.5(a).
The switch pair consists of transistors Ms1 and Ms2 and it is driven by ideal drivers that
provide current transients as in fig. 9.5(b). These correspond to voltage transitions Z(t)
from VL = Vdd − VD to VH = Vdd to the gate of Ms1 , and Z̄(t) from VH to VL at the gate
of Ms2 , respectively. The differential signal is z(t) = Z(t) − Z̄(t). As Z(t) approaches the

RD RD ID
iD
Z Ms1 Ms2 Z iD
0

Iu

(a) (b)

Figure 9.5 Current switch and ideal driver.

threshold voltage region of Ms1 timing errors are created dependent on the magnitude of
the slope near the threshold region. As long as the gate capacitance is linear, the slope
is easily approximated with the equations given in the previous subsection. However, the
switch transistor exhibits a non linear gate capacitance. When Ms1 is off, no channel
is formed and the capacitance seen by the driver is gate-overlap capacitance given by
W LovCox , where Lov is the overlap length of the switch transistor, W is its width, and Cox is
the gate-oxide capacitance. As Z(t) reaches the transition point, the transistor crosses the
weak/strong inversion regions (the drain is usually large such that when Z(t) reaches Vdd
the switch operates in saturation). The formation of the channel gives rise to the channel-
bulk capacitance [139] adding capacitance CoxW L (approx.) to the driver’s load (L is the
switch length). At a first sight the slope that determines the timing error is determined by
overlap capacitances only. The situation is different for the complementary transistor Ms2
that turns off, in which case the slope is determined by the combination of gate channel
and gate overlap capacitances, because Ms2 starts the turning off phase from saturation.
To find the timing error in a switch we apply the behavioral-level circuit analysis
presented previously: eq.(9.18) can be directly applied once the capacitance at the Z
node is calculated. This capacitance is determined by the contributions of the self load
capacitance of the driver CD , the interconnect capacitance Cint and the gate capacitance.
Therefore, we can write

C1 = CG (Z) +CD +Cint (9.29)

128 Chapter 9 Circuit analysis of local timing errors

The non linear effect in the gate capacitance can be neglected observing that while the
transistor that turns off has less timing error due to the faster slope, the one that turns off
establishes the dominant error in a differential signal configuration.
The input referred offset of a MOS differential pair can be approximated by [75]:
AV
σVo f f 1 = √ t (9.30)
WL
AVt is a process parameter in mV µ m that characterizes the threshold voltage properties of
the used CMOS process, and W, L are the dimensions of the MOS switches. Let us assume
that the switch gate capacitance CoxW L dominates the three capacitive terms. The slope
of the differential signal of the driver around its zero crossing is ≈ ID /CG . The spread of
the timing error can be calculated from e.q. (9.30) and eq. (9.18)
√
WL
σ (∆ts ) = AVt Cox (9.31)
ID

The timing error spread depends linearly with two process parameters, inversely propor-

3.5

3
model
2.5 simul. with width W
spread (psec)

2 simul. with width Wx 4

1.5

0.5

0
0 50 100 150 200 250
Current (µ A)

Figure 9.6 Timing error of a differential switch.

tionally to the driver’s current, and linearly proportionally with the square root of the area
of the switch device. This means that when the device area is increased, the timing errors
due to the extra capacitance dominate. Evidence of this dependency is provided with the
simulations in fig. 9.6 where the timing spread at the differential SI cell output currents
is plotted as a function of the current ID of the ideal driver topology shown in fig. 9.5.
The simulations were performed in the following way. The thermometer SI cell that is
actually realized in the design described in chapter 11 is simulated at the transistor level
and the timing skew of its differential current pulses is recorder. The control signal has
VD = ID R1 = 0.6 V swing (from 1.2 to 1.6 V). The capacitance loading the driver is only
the intrinsic capacitance of the transistors Ms1 and Ms2 . The curve with the notation W
corresponds to the thermometer switch size used in the actual IC, the curve indicated 4W
9.1 Circuit analysis with linear models 129

corresponds to the same cell but with

√ four times the switch width, and the curve with
notation model is in fact the ideal 4 timing error upscaling of the curve W as predicted
by eq. (9.31). There seems sufficient indication that the simplistic relationship defined in
eq. (9.31) between timing error, threshold voltage spread and slope is satisfied.

CD=1fF
900 CD=2fF 2000 w=0.42µ m
CD=3fF w=.84µ m
800 w=1.68µ m
C =4fF
D w=3.36µ m

σ∆ t (fsec)
1500
σ∆ t (fsec)

700 w=6.72µ m
600
1000
500
400 500
300
0 1 2 3 4 5 6 7 0 5 10
(a) width (µ m) (b) CD (fF)

Figure 9.7 Timing errors of a differential switch including the driver’s self
loading capacitance.

Next, the impact of the self loading capacitance of the driver is added (the local inter-
connect can be treated similarly). The total capacitance now is C = CD +CG where CD is
the total output capacitance of the driver. Then
 
AV AV √ CD
σ (∆ts ) = √ t (W LCox +CD ) = t W LCox + √ (9.32)
W LID ID WL

which, has a minimum point at CoxW L = CD . In other words it means that the self load of
the driver and the interconnect should be matched with the capacitive load of the switch to
minimize σ (∆ts ). As long as CD is dominant over CG , increasing the size W L reduces the
timing errors because the threshold mismatch is reduced. When CG becomes equal to CD
the capacitive portion of the switch in the timing errors takes over. In fig. 9.7 the above
equation is plotted. Figure 9.7(a) shows the spread as a function of the switch transistor
width for several values of the driver’s self loading capacitance. The minimum values in
the figure represent the point at which CG = CD . In 9.7(b) the driver’s capacitance is the
variable and the transistor width the parameter. When the width is small CD determines
the error, but when the switch is large, the influence of CD becomes much less,
Now we will consider the second mechanism mentioned in the beginning of this sub-
section: the output slope variations due to mismatch in channel charge times [82]. In
this case the timing difference between different current pulses is zero at the initial phase
of the transients and grows as the transients develop. The channel charging time of the
switch is CG /gm [82], which is the time domain equivalent of the unity gain frequency
gm /(2π CG ). It reflects to how quickly the transistor can transfer charge from the input
130 Chapter 9 Circuit analysis of local timing errors

to the output [140], and it is a strong function of the current conducted by the switch
transistors and their dimensions. In [82] it is expressed as

CG CoxW L
τch ≈ =L (9.33)
gm µn Iu

The dominant mismatch contribution comes via the length, although current variations
(mismatch in the current sources) can contribute as well. The length mismatch contri-
bution can be evaluated using L + ∆L as it was done in [82]. However, this analytical
description is not to be taken very precisely because it is based on constant biasing con-
ditions. In reality, as the switch turns on/off, its biasing conditions change continuously,
thus revealing a role for the signal Z(t) which is not captured considering only eq. (9.33).
It may though give the main dependencies of the timing error with device parameters.
In summary, the main contribution to local timing errors by the differential MOS
switches is threshold mismatch. The errors depend linearly with the process parameters
AVt and Cox , linearly with the square root of the switch gate area, and inversely propor-
tionally with the current of the driving circuit. The following conclusions are drawn:
1. capacitance is more important than mismatch, thus minimum switch dimensions
are beneficial for low local timing errors;
2. current, thus power consumption, at constant swing can be traded for lower errors;
3. the driver’s self loading capacitance, or the interconnect should be matched to the
switch gate capacitance to keep the error in its minimum value.

Clocked elements
The timing errors generated in the clocked elements are significantly influenced by the
combination of transistor mechanisms, as for example in the switches considered previ-
ously, and the non linear switching dynamics introduced by the specific circuit topology.
Latches are particular cases of clocked elements with memory. They will be the focus
of the following discussion. Such elements are extensively used in many areas of elec-
tronics like digital IC’s, DACs and ADCs, optical transmission of data, prescalers, etc.
Their functions include sensing, amplification, and sampling of input signals that have a
wide range of properties. In high speed DACs the design priorities stem from its function
as an interface between a digital output (decoder) and an analog input (SI cell).
For the discussion that follows two static latches families have been selected. Two
representatives of the first are shown in fig. 9.8. In this family the positive feedback loop
is always active. For new data values to be loaded, the latch has to be forced to change
state. These latches are very popular in recent high speed CMOS DACs, e.g. [39, 54, 66].
Two members of the second latch family are shown in fig. 9.9. The characteristic here
is that the positive feedback loop is deactivated in the sampling phase, and activated only
when the data have settled. The circuit topology in fig. 9.9(a) is a Common Mode Logic
(or Source Coupled Logic) latch implemented in CMOS, and that of fig. 9.9(b) is a
9.1 Circuit analysis with linear models 131

Q Q

φ φ D Q Q D

D D φ φ

(a) (b)

Figure 9.8 Static latches with active feedback during sampling.

Q Q
D D
D D

φ φ
φ
bias

(a) (b)

Figure 9.9 Static latches with disconnected feedback during sampling.

CMOS logic latch. The CML latch implemented in CMOS is a direct translation of the
Emitter Coupled Logic (ECL) latch [141, 142], which was first seen in Silicon bipolar
technologies. CML latches are preferred in many applications that deal with very high
frequencies for its low power supply disturbances and low power consumption at high
speeds. ECL and CML was the primary choice for older high speed DACs [35–37, 50]
but it has been replaced in CMOS DACs by variations of the circuit in fig. 9.8.
Next, it is explain how timing errors are generated in the latches from fig. 9.8(b),
9.9(a). First, that of fig. 9.8(b) is discussed. It is a cross-coupled inverter based CMOS
latch realizing voltage sampling: it allows a direct path from the digital gates connecting
to nodes D and D̄ to the latch nodes Q and Q̄ via switches (resistors when turned on).
The cross-coupled inverter pair forms a nonlinear resistor with positive and negative re-
sistances. It defines two stable equilibrium points that constitute the memory states, and
one unstable which forms a decision point (in ADCs it is used as a comparison level).
Assume that the latch is at one stable point (e.g. Q locked to ground, and Q̄ locked to
Vdd ), and it has to sample and store new data that corresponds to the other equilibrium
state (e.g. Q should go to Vdd , and Q̄ to ground). Because the positive feedback loop is
132 Chapter 9 Circuit analysis of local timing errors

activated during the transition from the old to the new state, the latch initially impedes the
transition, and accelerates it only after the unstable equilibrium is crossed. On this tran-
sition several timing errors can be generated. Here they are explained qualitatively. For
a both qualitative and quantitative insight the author is referred to [143] where nonlinear
models were used to describe analytically the switching dynamics. These models where
verified with transistor level simulations.
The first type of timing errors is generated by threshold mismatch at the switches.
Threshold voltage induced timing errors follow the main lines discussed already for the
SI switches: fast clock slopes and small switch dimensions reduce the timing errors.
The second type of timing errors is generated by mismatch in driving strength between
different latches. When the switch turns on, currents are initially drawn/dumped from the
data source to force the latch to leave its previous state. After some critical point, the
latching mechanism takes over and forces the transition it self using local currents from
the inverter pair. The initial current values are determined by the switch on-resistance,
interconnects, the current driving capabilities of the data sources, and the initial voltage
conditions applicable at the source and drain terminals of the switches the moment they
are switched on (e.g. the voltage differences between D and Q, and D̄ and Q̄). Conse-
quently, when there is mismatch from latch to latch in these properties timing errors are
created at the latch output. Consequently, this latch has some sensitivity to local errors in
the data flow, possibly important for psec range of timing errors we are dealing with.
Another type of timing errors due to mismatch appears in the transfer function of
the non linear resistive elements (the cross-coupled CMOS inverter pair) that determines
the positive feedback. For example, if the transistors of the inner cross-coupled CMOS
inverter are subject to threshold mismatch, the positive feedback exhibited by the cross-
coupled pair changes, and this translates to timing errors.
In all the timing error mechanisms mentioned, the errors are generated when the data
D and D̄ are properly settled the moment the sampling phase is initiated. They are static
local timing errors.Now let us examine another problem when the data are not properly
settled at the beginning of the sampling phase, but they are still undergoing transients.
As mentioned mismatch in the initial voltages the switches see when turned on leads
to different delays in the latch response. Metastability is the extreme result of this mech-
anism, when the currents cannot force the latch to change state within one sample period.
As long as the initial voltage is the same for all latches, the errors are global. However,
bit waveforms have large differences, local timing errors can be generated. Notice that
this mechanism can not be captured with the linear models presented in the previous sub-
section, because it is based on a nonlinear translation between an amplitude excitation to
a delay by the specific circuit mechanisms of this latch.
In summary, the cross-coupled inverter CMOS latch shows many timing error gen-
eration mechanisms. Many of them are related to the active positive feedback during
sampling. The best situation is when the inverters have minimal strength: the stronger
the latch is, the stronger its data sources (gates) must be, the larger the W/L ratio of the
clocked switches to handle large currents and offer low resistance, and the more currents
are required from the clock driver to keep the clock slope high (keep its offset based tim-
ing errors from increasing). In other words, a chain effect appears. The size of inverters
9.1 Circuit analysis with linear models 133

is defined by the input capacitance of the subsequent switch drivers, which itself is ulti-
mately defined by the SI cell switch gate load. Once more, minimizing the SI cell switch
size is a main priority for low timing errors and power consumption.
Let us now examine the CML latch topology shown in fig. 9.9(a). The advantage here
is that the feedback loop is disconnected in the sampling phase. In the latching phase the
signals at the nodes Q and Q̄ are already settled, and the inner latching differential pair
needs only to sustain the full swing amplitude at the latching phase. At the same time, the
currents used to force the nodes Q and Q̄ to change state are never drawn from the driving
digital gates, but always from the local bias transistor.
Timing errors are created only by mismatch at the clocked transistors and by the vari-
ations of the output resistors and load capacitances. If there is mismatch between the
biasing currents of different latches, this does not generate errors for as long as the time
constant stays the same. Furthermore, in this latch, the digital gates driving nodes D and
D̄ can have minimal driving capabilities, without its operation or the associated intercon-
nect to play any role at all in timing accuracy. The combination of data amplification
and absence of latching in the sampling phase reduces substantially metastability based
timing errors, compared to the CMOS latch shown earlier. Finally, reducing the gain of
the positive feedback loop reduces associated transistor sizes in favor of smaller para-
sitic capacitances which results in faster slopes. Separate optimization of the sampling
and latching stages of this latch is exploited for many years already in very high speed
application areas, e.g. [144].
The timing error spread of the clocked switches of the CML latch will be calculated
now. First, we write the clock node total capacitance as

CC = (2NT − 1 + NB )CL +CInt +CCD (9.34)

where NT and NB are thermometer and binary bits, respectively. CL is the input capaci-
tance of a latch, CInt the clock interconnect capacitance, and CCD the clock driver’s output
capacitance. After the calculations we find
 
AV √ CInt +CCD
σ (∆tl ) = th WL LLCox (2NT − 1 + NB ) + √ (9.35)
ICD WL LL
Once more, the minimum timing error spread is achieved when the total latch loading
capacitance equals the total interconnect and clock driver’s output capacitance, i.e.
√
WL LLCox (2NT − 1 + NB ) = CInt +CCD

Furthermore, as the number of thermometer bits increases, the timing error increases.
This applies not only via the latch capacitance CL but also because the CInt roughly scales
proportional to the number of clocked elements (not obvious here).
From the discussion made about the relationship between timing error mechanisms
and latch circuit topologies, it seems that CML latches provide some advantages com-
pared to CMOS latches. However, this can not be stated strongly until we can obtain a
quantitative picture of the timing error problems.
134 Chapter 9 Circuit analysis of local timing errors

Clock interconnects

In the section the main lines of interest for clock interconnects in high speed DACs will
be described. First, a technological context is defined, and then the relation to the design
of high-speed DACs follows.
Wire interconnects in general, and clock interconnects in particular, have become
more important on the performance on synchronous systems due to fundamental pro-
cess scaling effects that result in the increase of the fraction of the chip clock cycle that
is occupied by the interconnect related delays, and coupling effects [145–147]. More-
over, the clock relative delays at different locations of the chip are only a function of the
interconnect topology, and they can not be reduced by spending extra driving current.
Gate delays and capacitance have scaled down to keep up with the increasing clock
rates, but interconnect delay has not scaled with the same rate [146]. The evolution of on-
chip interconnects is not only characterized by the shrink of the widths of wires, but also
there is change in interconnect geometry; the ratio between the width and the thickness of
the wire has been inverted. The two most important consequences of wire scaling are (1)
wire delay has not scaled as fast as gate delay, and (2) there is an increase of the lateral
coupling between wires, despite new technological measures using low κ dielectric and
copper interconnect. In addition, the clock cycle time has increased considerably.
Interconnect related delays need to be considered both in a view of maximum clock
frequency they allow a circuit to handle, and in view of local timing errors. Moreover,
Cross-talk related effects have risen in significance. Cross-talk affects both delay and
signal integrity. The high frequencies of operation reveal also an interconnect modeling
issue; dependent on the length and the properties of the line, as well as those of the driver,
inductive phenomena can have significant influence on the delay and on the waveform
shape of the signal that is transmitted through the line [92, 145, 148, 149].
In DACs, the fraction that the clock network delay has on the total delay for a fixed
sampling rate is a function of the thermometer/binary partitioning (defines the number of
clocked elements), of the area the clocked elements occupy, and of the clock loading per
element. The area that a clock network covers is roughly one third to one fourth of the
total area of the DAC, and within a few mm2 . Therefore, the clock distribution network
introduces delay that is a significant but not the dominant limiting factor for the maximum
achievable sampling rate of the DAC.
The combination of high switching speeds (50 − 100 psec transition times) with sam-
ple rates exceeding 1 GHz means that possible inductive effects should be examined dur-
ing the delay calculations. DAC clock interconnects can be regarded as “short” [148], and
they have generally small widths. These clock lines are driven by large devices, with an
effective output resistance usually larger than the interconnect resistance. For this situ-
ation, a distributed RC model for the interconnect network provides accurate means for
delay calculation [148]. Such a model neglects inductive effects in the clock lines and
predicts a delay that is in proportion with the interconnection line length l. However,
neglecting inductive effects might not always be justified, even for short interconnection
lengths because they ought to be observed from the point of view of local timing error
generation, which demands subpsec relative timing accuracy.
9.2 Local timing error tradeoffs 135

Accurate modeling of clock interconnects also shows a detrimental effect on the pre-
diction of cross-talk based delays [148, 150]. Cross-talk prediction based on simple RC
networks underestimates significantly the resulting effects. In a DAC, clock interconnec-
tions are usually in the close proximity of other lines, such as data lines which exhibit
data dependent activity. They might also be close to noise sensitive lines carrying output
signals and biasing currents or voltages. Because of the high frequencies of operation
and fast switching times for clock, data and output signals, larger cross-coupling effects
are expected. On one side, data-dependent delays for different interconnection lines, or
frequency modulation of the global clock signal can be anticipated when data-lines activ-
ity is coupled to the clock lines. On the other side, the clock network can act as a noise
source itself affecting sensitive wires of the DAC. Creating a clock network which is not
in the close proximity of sensitive signals, or biasing nodes, and yet far away, or shielded
properly from the activity of the data lines is a major challenge in the DAC floorplanning.
A final point of concern for interconnections is related to parameter variations dur-
ing the manufacturing process. Not only they affect the behavior of identically designed
clocked elements, such as clock buffers, latches and flip-flops, but the behavior of identi-
cally designed interconnection wire lines, as well [151–153].

9.2 Local timing error tradeoffs

In this section examples of design tradeoffs will be given that are related to spatially local
random timing errors. Such tradeoffs were already presented in section 8.2, however
they could not be properly captured unless functional and circuit analysis are combined
together. The circuit analysis presented in the previous sections allows this combination.
These tradeoffs have the main aim to coarsely describe interdependencies of parameters,
and not to give exact prescriptions on how the DAC should be made.
Two representative examples will be given. The first example concerns the current
switches iin combination with the signal properties of the driver-switch nodes. The second
example concerns the latch switches in combination with the global clock signal.

9.2.1 Switch timing errors

Consider an N bit segmented CS DAC with NT thermometer and NB binary bits and
assume it is limited by local random errors at the thermometer segment. In particular,
assume that the major contribution is the mismatch of the SI cell switches, and that the
capacitance at the driver-switch node is determined by the switch gate capacitance. Com-
bining eq. (8.16) and (9.31) we find
 
ID

 = −10
SDR


log1 0( f fs ) + 20 log
  AVt Cox
+ 3(NT − 1) − 10 log(W L) −9.03

 
Per f ormance Specs
  Design
Current&Process
(9.36)
136 Chapter 9 Circuit analysis of local timing errors

This equation shows the different kind of parameters contributing to the overall SDR
result. Before proceeding in the interpretation of it, assume that the output signal range
is fixed. If IFS is the full scale delivered to the output load of the DAC, then the LSB
switches conduct ILSB = IFS /(2N − 1)mA and the thermometer ones IT = IFS /(2N − 1)2NB
independent of any scaling of parameters we consider. Next, the freedom involved in the
parameters of eq. (9.36) is explained.
1. Process parameters: the product AVt Cox is a function of the CMOS process used.
2. Functional specifications f , fs and N = NT + NB : they represent the bandwidth,
sampling rate and resolution of the DAC under consideration.
3. Design parameters W, L: Usually the length is the minimum allowed by the process,
and the width is scaled accordingly to handle the signal current.
4. Design parameters NT , NB : for every extra thermometer bit, the number of latches,
drivers, SI cells, decoding logic, and associated interconnect double.
5. The current ID spent per driver assuming a constant swing VD = RD ID determines
the power consumption P = IDVdd per driver, and that of all drivers tother (2NT −
1 + NB ) via the power supply voltage Vdd .
As CMOS technology scales down in minimum allowed device dimensions, the pro-
cess parameter AVt reduces linearly to the reduction of the oxide thickness tox , whereas the
oxide gate capacitance Cox increases proportionally to tox [73]. Therefore, while for ampli-
tude matching considerations the product AV2t Cox encapsulates the relevant process scaling
influence in the speed-area-power tradeoff [154], and reduces with newer processes, for
timing errors the dependency on the product AVt Cox shows that better AVt of newer CMOS
processes do not benefit timing accuracy. Improvements come though because switch
timings errors are dominated by the capacitance CG : for each new process the minimum
length scales with α , where α is the CMOS process scaling coefficient [155]. Since the
switch length scales with α but the√switch width stays the same to sustain the fixed signal
current, performance improves by α according to eq. (9.31) for the same switch driving
current. Power consumption IDVdd decreases due to the down scaling of Vdd , and the ratio
of the timing accuracy over the power consumption also improves.
Let us now examine the design parameters W, L and the current ID . If the switch width
(or length)
√ decreases,
√ e.g. by increase of its overdrive voltage Vgs −Vt , the SDR increases
with 1/ W (1/ L). Therefore, for the region of sizes where the mismatch model of [75]
is a good approximation of reality, the switch dimensions should be to the minimum
allowed by other design objectives. The current ID has the largest impact on timing error
reduction at the cost of a similar increase of the power consumption: doubling the current
per driver provides 6 dB extra in SDR but doubles the power consumption as well.
Next, let NT to scale while
√ the rest of the factors constant. Increasing the number of
thermometer bits gives a 2 benefit in SDR, e.g. 3 dB, but it doubles the total power
consumption of the drivers (and the latches, decoder, etc.) because their number doubles
as well. If though the switch geometry is tied to the scaling of NT then the results are
9.3 Conclusions 137

different. When NT increases by one bit, each thermometer SI cell switch needs to conduct
half the current than before. Therefore, the width W of each switch can halve as well. This
gives a total of 6 dB benefit for each extra thermometer bit. Therefore, for a given power
budget it is better to maximize NT and minimize the switch dimensions to maximize the
SDR. Alternatively, when W is halved, reducing ID by cancels out SDR improvements
but maintains constant power consumption.
Consider now the resolution is increased by one bit allowing more combinations to
make with NT and NB . To comply with the new functional specifications 6 additional dB’s
of SDR are required. This can be achieved doubling the current ID per driver, reducing
the size W L by 4, increasing the thermometer bits NT by 2, or making combinations. Of
course, if the area W L or the current ID are modified, it is implicitly assumed that the time
constant of the driver-switch node is still determined by the switch gate capacitance, and
that the switch can still handle the same current. Similar results apply if the sampling rate
fs and the corresponding signal bandwidth f double when N is constant.

9.2.2 Latch timing errors

Out of the many local timing errors generated in a latch, we only focus on those gener-
ated by threshold mismatch at the clocked switches of a differential CML latch. Similar
considerations apply for other latches as well.
Direct use of eq. (9.35) and eq. (8.16), excluding the interconnect and clock driver’s
capacitance results in

SDR = −10 log10 ( f · fs ) + 20 log(ICD ) − 20 log(AVt Cox ) − 3(NT + 1) − 10 log(W L) − 9.03

(9.37)

The results show one major difference compared to the SI cell switch case: as NT in-
creases, the SDR drops with 3 dB/oct. The rest of the parameters bring the same results
as in the previous example. Therefore, for a constant power, for the threshold mismatch
based timing errors created by the latches, it is better to have as few clocked elements as
possible, with the minimum possible dimensions for their clocked switches.

9.3 Conclusions
In this chapter a circuit analysis of local timing errors has been conducted with linear
models. It was shown that there are two main types of local timing errors: those created
by variations in RC time constants in a node translated to delays by the comparison action
of the switching circuit driven by the signal at this node, and those created by different
offsets in the comparison levels between identical switching circuits that are translated
to delays. Other errors mentioned include integral errors in the individual output current
pulses of the DAC, mismatch in switching cell gains, etc.
Offset based timing errors depend on the offsets of each switching circuit, and the
slopes of their driving signals, which depends on the RC time constant and the amplitude
of the signal applied to it. For these errors, the gain of the driving circuit can reduce offset
138 Chapter 9 Circuit analysis of local timing errors

based timing errors of the circuit it drives. Time constant mismatch errors at the inner
chain nodes depend solely on the mismatch in R’s and C’s. For both types of errors, as
long as the resistances of the inner nodes are determined by the driving circuits, current
can be traded for lower timing errors given a constant swing.
Transistor level analysis revealed the transistor level mechanisms responsible for local
timing errors, and the relationship between circuit, transistor, and process parameters.
It was shown that the main contribution to local timing errors by the differential pair
MOS switches is threshold mismatch, and errors were calculated analytically. The most
important conclusions were that (1) the capacitance of the driving node is more important
than the mismatch of the circuit being driven, (2) that timing errors are minimized when
the input capacitance of a switching circuit is equal to sum of the self loading capacitance
of its driving circuit and the interconnect capacitance connecting the two, and that, (3) the
timing errors improve by spending more power, and by using newer CMOS processes.
In the last part of the chapter, the circuit analysis results of local random timing errors
were combined with the functional ones from the previous chapter and revealed inter-
esting tradeoffs between signal properties, architecture, design and process parameters,
and power consumption. A side aspect of this combination is that although the averaging
principle behind all local timing errors indicates functionally that the number of ther-
mometer bits should be maximized, in practice many thermometer bits is not beneficial
for all members of this class. This is caused by the coupling mechanisms that the tran-
sistor operation establishes, and the dependence of several circuit and signal properties of
the DAC elements with the number of thermometer bits. In particular, we have come to
the following conclusions concerning the number of thermometer bits:

1. It affects differently members of the same subclass of local timing errors, e.g. ran-
dom ones due to mismatch in SI cell switches and latches. Timing errors created
by latches require small number of thermometer bits, and those created by the SI
switches (similarly, by drivers) require large number of thermometer bits.

2. It affects differently subclasses of the same class, e.g. random and deterministic
local timing errors in SI cell switches and clock network, respectively, but other
similar subclasses similarly (random local errors in latches, and deterministic local
errors in the clock network). As the number of thermometer bits is increased, the
clock interconnect related deterministic errors most likely increase.

3. It affects differently members of different classes. For example, we know from

chapter 5 that the global error mechanisms related to power supply and substrate
noise become less important when the thermometer bits are only a few.

Given how multi-dimensional the influence of the number of thermometer bits is, there
can be no generic statement on what the optimal number of bits is. Instead, every answer
needs to be placed in the particular context of what is taken into account, and what is not.
 10

Synthesis concepts for CS DACs

C I rcuit synthesis of DACs involves three main components: a set of specifications

about the targeted circuit implementation, knowledge about the error mechanisms
of the DAC, and knowledge about design techniques, methods and algorithms to address
these errors. In this chapter initially the information sources that can be taken into account
in the synthesis of a DAC are described. Next, the main lines of circuit synthesis for CS
DACs are discussed and a specific target for experimental verification is also defined. The
final part of this chapter discusses correction concepts that can address local errors, in
particularly timing. A new correction concept called generalized mapping that aims to
address simultaneously all local errors is elaborated further.

10.1 Information management in the CS DAC

This section deals with aspects relevant to the information sources that can be taken into
account in the synthesis of a CS DAC. The information sources are also structured into
classes according to their properties.
The analysis presented in the previous chapters provides insight on the error genera-
tion mechanisms and shows which parameters, parametric signals, and properties of the
input and output signal of the DAC are relevant for each problem. Vectors of properties
from different error classes, and the knowledge of the kind of modulation effects each
class of errors has on the signal describes the behavior of each specific error modulation
mechanism. Given the knowledge of the error mechanisms, the technology in which the
DAC will be realized, the application, etc. there is also information to be exploited in
those hidden signals and parameters of the DAC that are related one way or another with

139
140 Chapter 10 Synthesis concepts for CS DACs

Output signal

(a−posteriori)
Output info
(optional)
detection

Output info
(a−priori)

(a−priori and a−posteriori) (a−priori and a−posteriori) (a−priori and a−posteriori)

processing

(optional)
(optional)

control
signal

parameters, etc.
hidden signal,
(a−posteriori)

User info
(optional)
detection
signal flow

signal, etc. info (a−priori)

Application info
parameters, hidden

Algorithms
architecture, circuit,
Generic info about

Basic HW design
Basic HW

(optional)
control
parameters, etc.
hidden signal,

Environment info
& mapping
processing

(optional)

Control (a−priori)
signal

Control (a−posteriori)
(a−posteriori)
(optional)
detection

(a−priori)
Input info
Input info
Input signal

Figure 10.1 Information stream and available processing options in a CS DAC.

the error mechanisms as their constitutional parts. These can be detected, possibly con-
trolled, and somehow be used in design techniques and algorithms to improve the output
signal quality. A conceptual description of the overall process of combining information
sources with algorithms on the basis of the error mechanism knowledge is shown in fig.
10.1. A brief description of fig. 10.1 follows in the next paragraph.
10.1 Information management in the CS DAC 141

The figure contains the basic DAC hardware that implements the D/A function and
auxiliary, or optional hardware that aids the basic hardware to improve the quality of
the output signal. Around the basic and optional hardware there is a stream of relevant
information sources about the DAC that can be used accordingly. Using information
means that the errors, the signal, hidden signals, parameters, etc. can be detected, then
this information can be processed accordingly, and the result of the processing can be
embodied into some control operations that influence the basic hardware and the input
and output signals. This applies both for error mechanisms taken into account during
the design phase, or after it. In the same figure, the term a-priori is used to describe
information available at the design phase, whereas a-posteriori describes information that
can only be extracted after the design phase.

10.1.1 The basic current steering DAC hardware

The basic CS DAC hardware (basic HW) consists of key elements such as current sources,
switches, the clock-data synchronization and conditioning circuitry, the decoder, etc. It is
shown in the middle of fig. 10.1. The basic HW is realized taking into account information
about the architecture, circuit topologies, the technology, the actual errors, requirements
of physical resources, etc., and then exploiting the available degrees of freedom within
these areas. This is symbolized with the action arrow in the middle of fig. 10.1.

10.1.2 Information sources

The types of information sources about the CS DAC are described next. To design a CS
DAC information about it is required, which can be categorized to

technology, circuit topologies, and architectural issues;

the signal and error generation mechanisms;

the input and output signals;

user, application and environmental information.

All information sources can be distinguished to a-priori and a-posteriori. With a-priori it
is meant any type of information available at the design phase of the circuit. A-posteriori
information is only obtained after the fabrication of the IC. The information stream can
easily be distinguished in fig. 10.1. In the figure only some types of information sources
are shown: information about the input and output signals; hidden signal and parameter
information; environmental information; information concerning the application, etc.
Some examples are given below:

The errors that will be addressed in the design phase are always a-priori known
(e.g. timing errors, impedance related errors, etc.). However, the actual values of
the errors are not always known a-priori. For deterministic errors there is usually
much more information known at the circuit design phase, while for random errors
142 Chapter 10 Synthesis concepts for CS DACs

the only thing known in advance is statistical properties: it may be a-priori known
that spatially random distributions of errors have Gaussian properties with a spread
around a specific value, but the exact error values of each IC can only be known
a-posteriori; spatially deterministic errors can be assumed to consist of gradients,
although their exact orientation and slope is only extracted a-posteriori; the errors
introduced by the finite impedance of the SI cells (deterministic error) are known
before the fabrication with great precision.

Information about the DAC input and output signal properties, e.g. whether the
signals to be converted are sinusoidal, Gaussian, their peak values, etc. can be
a-priori known and taken into account in the design phase. In fact, it is always
a specific category of signals with a predetermined range known beforehand that
the DAC circuits are designed for. However, the actual signal values at a given
time moment, or properties such as second order moments within a window of time
consisting of a few thousands of samples, the actual sample to sample differences
for each consecutive samples, etc., -all very relevant for the actual errors of the
output signal- can only be obtained a-posteriori when the DAC operates.
The available information about an error, or the input and output signals is always a com-
bination of a-priori and a-posteriori information. Information about the actual signals
can be a valuable source of information that is not exploited sufficiently nowadays. A-
posteriori information about the input signal can be quite useful in the sense that it can be
extracted with digital circuits, and can lead to feed-forward types of processing.
When a design phase is initiated, the relevant dominant error mechanisms and limi-
tations for the specification range are known a-priori, and the basic design options about
the architecture and the basic HW are taken on the basis of this knowledge. The more
knowledge that exists about the error mechanisms, and the more information that can be
obtained for the actual values of errors before or after the design phase and processed
accordingly, the better the IC can be made using proper design techniques.

10.1.3 Optional hardware: detection and control operations

In this subsection the optional detection and control hardware shown in fig. 10.1 will
be explained. A-priori information relies on design experience, knowledge about the be-
havior of the relevant of error generation mechanisms via analysis, the predetermined
application type that sets the types of signals that will be applied to the DAC, etc. To
acquire a-posteriori information a detection phase is required, e.g. measurements and sig-
nal processing operations. Such a phase can be made during the normal operation of the
DAC, once on the life time of the IC, or upon start-up. The kind of circuits required to
make the detection depends on the type of error or signal properties needed to be identi-
fied. For example, the DC current error value due to mismatch of each individual current
source requires current or voltage measuring circuits; nonlinear digital signal processing
circuits at the input of the DAC can extract valuable signal information about the order
statistics of the digital input signal (moving averages, median values, power estimation,
correlation, etc.)
10.1 Information management in the CS DAC 143

Similar types of error information can be obtained detecting the analog output signal
and processing it accordingly. Such detection leads to feedback type of operations (Σ∆
modulation is a very good example of this type of processing). In principle, detection
can be applied to all types of errors. However, in practice it is not always feasible to do
so. Time skew detection is one typical example that poses significant measurement chal-
lenges, explaining partially why it has not been ever used in DACs although commonly
applied in other circuits (e.g. PLLs, DLLs, Time-interleaved ADCs).
Control operations are applied to the basic or optional hardware with the aim to im-
prove the quality of the output signal. It is the last step of a correction process. Control
operations can be applied in the individual hardware components of the DAC (current
sources, switches, latches, etc.). A typical example is the modification of the unit current
sources according to a calibration method that detects the error per source, compares it
with a reference and then uses the control circuitry for the correction of each source. Con-
trol on the output signal is usually applied with the addition of correction currents directly
at the output node of the DAC. The most typical case is a feedback detection-decision-
control loop that senses the current outputs for each input digital word, compares it with
a reference, and adds correction currents to cancel the error. Finally, control can deter-
mine the way optional signal processing is made at the input signal, or mapping and other
architectural operations.

10.1.4 Algorithms
The degrees of freedom available to build the basic HW are not always sufficient to reach
the aimed specifications even with the most in-depth knowledge about the error mecha-
nisms. In many cases, circuit design techniques do offer the performance required but at
a large cost in power and/or area. Such type of limitations are described by circuit design
tradeoffs between area, power, accuracy and speed [154]. Consequently, it is necessary in
many occasions to employ supplementary correction algorithms, signal processing tech-
niques, modulation, etc. to break these tradeoffs and realize more efficient DACs. Some
important points concerning these algorithms will be mentioned in this section.
These algorithms are shown in fig. 10.1. They receive relevant information, process it,
and deliver the results to control circuits that apply modifications to the basic HW or the
input and output signals. Σ∆ modulation is a representative example for high-accuracy,
medium-bandwidth and low power applications. In high speed DACs the a representative
method is amplitude error calibration, which is relevant only for DC accuracy. For the
most dominant errors mechanisms for high frequencies the main approach is to apply
good analog circuit design on the basis of in-depth error mechanism knowledge.
The algorithms can be classified between those exploiting a-priori and those exploiting
a-posteriori information. For an algorithm that exploits only a-priori information nothing
can be done after the IC is implemented because the properties of the architecture and the
circuits can not be changed after fabrication. The efficiency of an algorithm to cope with
a specific problem depends significantly on the nature of the problem and its associated
errors, ie. the class of the errors. The more deterministic and well identified the errors
are, the better they can be taken into account during the design phase, i.e. a-priori. A
144 Chapter 10 Synthesis concepts for CS DACs

couple of examples with hierarchical order of circuit abstraction will be provided in the
next paragraph to understand better the issue of proper matching between an algorithm
used to address an error class.
The CS DAC architecture realizes a parallel-select algorithm (see fig. 1.6(a)). The
choice to use this algorithm is based on the a-priori knowledge that this algorithm is
more suitable for high speed operation because it copes better with well understood high
speed limitations of the hardware than other algorithms do. Therefore, it can be selected
straightforwardly. Now let us look within the parallel-select algorithm. The choice to
partition the binary code in binary and thermometer parts is based on the fact that large
thermometer bit numbers relax the effects of local errors in general, e.g. mismatch based
errors in current sources, impact of relative timing errors. However, the choice on the
number of bits per segment and the actual impact on performance has a higher degree of
randomness than the choice to select a parallel-select algorithm. This is because the origin
of local timing errors is random. The segmentation level is usually based on a coarse
estimation of matching requirements for a given technology, and of spreads of local timing
errors. And while for some IC’s a specific segmentation choice in NT thermometer and
NB binary bits is sufficient, for some other IC’s it may not, and for others it can be an over-
specification since the actual errors are much less than anticipated. An even more detailed
example is the sizing methods used for the current source transistors. The dimensions of
a MOS current source are usually chosen large to confine the spread of current error in an
LSB interval because device width, length and threshold voltage variations have less of
an impact on the accuracy of the current source when the dimensions increase. This again
can lead to an over-specification of the complete hardware only to be able to place within
the LSB accuracy specification range some current sources.
The mentioned examples show that the least predictable the errors are the more circuit
performance can be penalized by overdesign. Thus, when more unpredictable or random
the errors are, the more efficient the use of an a-posteriori information based algorithms
is because such algorithms allow better tuning of the DAC against specific errors valid at
the moment it operates. At the conceptual level, it can be stated that a-posteriori based
algorithms use an action of information harvesting to transform random errors to deter-
ministic ones, because once error information is obtained the error ceases being random.
Because of this transformation they allow deterministic procedures to be applied. This
holds for all types of random errors (both amplitude and timing, global and local). The
central issue becomes then how to reach a maximum level of determinism on the errors.
To use a-posteriori information based algorithms, detection and control hardware
needs to be added next to the basic hardware, and also hardware to realize the algorithms.
The detection and control hardware depends on what is to be detected and controlled
(e.g. the input or output signal, the current source amplitudes, the power supply activ-
ity, the biasing levels, the time skew of signals, etc.). The hardware programming takes
place after the details of error information have been detected (after IC fabrication). Pro-
grammability receives the specific meaning of “programmability for error correction” and
not programmability to for different specifications and standards.
An interesting observation is that by using a-posteriori information based algorithms
to correct some errors, the basic hardware design seems to be decoupled from the require-
10.1 Information management in the CS DAC 145

ments imposed by the errors that the algorithm corrects. For example, proper calibration
can allow the current source to be optimized strictly for dynamics and small area because
current source mismatch errors will be corrected after fabrication takes place. However,
from the bottom-up point of view this is not necessarily true. Detecting and controlling
signals may affect considerably the normal operation of the HW DAC, or it may require
too many additional power and area requirements. This issue is design context dependent
and no general conclusions can be drawn before specific errors, detection, algorithm and
control implementations are examined.
Orthogonality of corrections is significantly impaired when all the corrections are
made with a-priori information based algorithms. For example, applying the law of the
large numbers in the functional layer to improve accuracy is realistic up to a specific
number of elements, beyond which area and power consumption make this approach
impractical. Orthogonality is hindered even for techniques within the same hierarchi-
cal level because different problems depend on the same parameters in opposing manner
(e.g. the magnitude of stochastic and deterministic spatial errors has completely opposite
requirement on area). Consequently, it is very important to evaluate the possibility to use
a-posteriori information based algorithms because then, classes or subclasses of errors
can be corrected optimally without forcing tradeoffs and hard optimization problems.
Even when in principle a-posteriori information about errors can be used, another
problem rises. Each a-posteriori based correction concept is usually aimed at a specific
type of errors. This means that to address more than one errors, more than one set of
detection-processing-control circuits need to be added in the circuit. This can easily bring
practical limitations, but there is a way out. Each class of error mechanisms is associated
to some principle correction methods. The idea is that since all problems of a class share
common characteristics, we can invert the line of thinking and see that all problems of the
same class can be treated in the same principle ways. Ideally, we would like to have a-
posteriori correction algorithms that can apply per-classes-of-errors, hence methods that
can jointly correct all problems of the same class of errors (e.g. spatially local, or global).
In principle, it is possible to find such kind of algorithms. Later in this chapter such an
algorithm is based on the concept of mapping is described.

10.1.5 Space/Time error mapping and processing

Signal processing operations are shown at the input stage of the schematic diagram of fig.
10.1. Processing operations in both amplitude-vs.-time and amplitude-vs.-space domains
can also offer significant degrees of freedom to improve the signal quality of the DAC,
especially if they are realized in the digital domain.
It has been shown in previous chapters that each class of timing errors depends on
some basic properties of the input signal. For example, dependent on whether RZ or
NRZ pulses are used, the power, or the power of the derivative of the input signal, re-
spectively becomes the relevant property for error generation. Therefore, we can envision
the existence of fictitious signal processing and modulation means that are incorporated
in the signal flow and alter the way the wanted information is encapsulated in the signal
that is converted, such that the error generation related properties are manipulated to the
146 Chapter 10 Synthesis concepts for CS DACs

signal quality benefit. The paradigm of the modulations used in communication theory
that deal with the Shannon communication channel models (e.g. Quadrature Amplitude
Modulation) are typical examples of how the noise introduced by a physical channel can
be properly addressed. A DAC can also be seen from such a point of view.
It has been observed that for local errors the error per sample to sample transition of
the input signal depends on the elements selected for this transition. This was shown to
have similarities with windowed averaging. In fact, one can go a step beyond and observe
that an array of elements with errors constitutes a multi-dimensional signal that is mapped
to a one dimensional error signal by the combinatorial mechanisms of the DAC that for
each input sample value they combine specific elements to generate the corresponding
output signal. On this mapping, linear and nonlinear filtering operations can be applied.
This can be termed spatial (signal/error) processing because in fact it is the spatial errors
that are being processed, and it is a side of DAC synthesis that is explored today only in
limiting cases but not acknowledged as a generic concept.
To see how mapping can realize spatial signal processing operations, recall that for
each input binary word a specific group of elements is combined to represent the input
with an output electrical value. The error in the output signal depends on which elements
have been selected because their combinations results in a equivalent timing, or ampli-
tude error for that sample to sample transition. Mapping is the assignment of one or more
elements to the used code digits and it forms a degree of freedom to influence how errors
correspond to signal transitions. Changes of the association between digital digits and
elements with timing or amplitude errors correspond to changes of the impact of local
errors to the signal. Once local error information is known, this association can be manip-
ulated by algorithms such that they improve the way errors appear in the transients or in
the spectrum. The fact that the processing and control mechanisms of this concept can be
realized completely in the digital domain seems to be a significant attribute. The concept
of generalized mapping has been presented in [143].
Algorithmic concepts from another scientific area will be borrowed once more to pro-
vide a paradigm on how mapping can be applied in DACs. In the image processing area,
nonlinear signal processing [136] (order statistics filtering such as min-max, sorting, win-
dowed averaging, outlier rejection) are simple and extremely useful techniques to improve
the quality of images (two dimensional signals with errors). Order statistics filtering has
been used in analog signal processing as well (e.g. [156]).

10.2 Synthesis Policy

In the previous section the information sources available during design have been dis-
cussed. These information sources can be combined with error generating mechanisms
information into synthesis of error correction algorithmic concepts and design techniques.
In this section, the main lines of the CS DAC synthesis policy to provide wideband DACs
with high dynamic range in a power and area efficient way will be presented.
In the area of wideband high dynamic range DACs only limited information manage-
ment options from fig. 10.1 are exploited. Relatively to each other, a-priori information
10.2 Synthesis Policy 147

design methods are dominantly used: only local amplitude errors are addressed with a-
posteriori correction methods (e.g. calibration of current sources). And yet, only few
error mechanisms relevant for high frequencies are addressed properly. A similary situa-
tion applies for the use of input signal information: DACs are designed nowadays having
sinusoidal signals mostly in mind, whereas in most communication applications signals
resemble more random Gaussian signals rather than sinusoids.
Consequently, the first synthesis policy line is to pay uttermost attention to all relevant
timing error mechanisms, and to use effectively both timing error mechanism knowledge
and the properties of the signals being converted. Among them, local timing errors due
to mismatch, global timing errors due to supply and biasing node disturbances deserve
special attention. Moreover, these mechanisms should be addressed with techiques that
apply orthogonally to each other.
A second synthesis policy line is to use of a-posteriori error information based algo-
rithms for error correction. Here, the aim is to partition the error mechanisms in those that
will be addressed with a-priori and those with a-posteriori error information (yet another
application of partitioning). Local timing errors specifically seem the first candidate to
deal with such an approach. For example, all errors belonging to the local error class,
amplitude and timing, can be corrected with mapping and calibration.
To see the potential benefits of using a-posteriori error information (next to a-priori)
for local timing errors the paradigm of calibration of local amplitude errors is examined.
Generally speaking, random errors are much more difficult to cope with a-priori informa-
tion based algorithms. The only way to design a circuit robust against them with a-priori
methods is to allow statistical margins (e.g. 3σ ). Such an approach comes of course at the
expense of resources. The point beyond which design with statistical margins becomes
too costly (in area, power, etc.) depends on the type of error. In order to reduce random
local amplitude errors the current source transistor’s area must be increased; this, how-
ever, increases significantly the total area (practically prohibiting for more than 12 bits)
and causes side effects such as deterministic local amplitude errors and large capacitive
overhead due to large interconnecting wire lengths. The only way to break through this
limit effectively way is to use calibration (see also section 4.2.1). This is to be expected
since a-posteriori based correction is a very efficient way to address random errors.
The situation for local timing errors seems similar. Here, improving accuracy for ran-
dom local timing errors requires significant amount of power to be spent in proportion to
the sampling rate of the DAC and the aimed dynamic range and signal frequencies. An
example power/area efficiency limitations related to timing errors (not only limited to lo-
cal) is found in [59]: the wideband performance achieved (≈ 70dB SFDR up to 400MHz
signals at 1.2GSample/s clock) is paid dearly with a power consumption of 6W and an
area of around 30mm2 ! Seeking the amplitude error paradigm for errors by introduc-
tion of a-posteriori error correction methods is expected to bring significant advances in
performance and power efficiency.
Research in accordance with the two main synthesis policy lines defined in the previ-
ous paragraphs will be presented next. In the next chapter, the design and measurements
of a 12 bit 500 Msample/s CS DAC in a CMOS 0.18 µ m process will be presented. This
148 Chapter 10 Synthesis concepts for CS DACs

DAC is designed for dynamic performance, optimized only for a-priori knowledge of dy-
namic error mechanisms -both local and global-, and under the assumptions of sinusoidal
input signals. In this design the theory and concepts developed in the previous chapters
of this book are put in practice, and also the relative significance and interdependencies
of different error (sub)class members are examined practically.
In line of the exploitation of a-posteriori error information, two of the most promising
methods (calibration and mapping) for local amplitude and local timing error correction
are discussed in the next section of this chapter. Generalized mapping, which was pro-
posed in [143] is explained with more details. No experimental results are presented here.

10.3 A-posteriori error correction methods

This section provides a brief discussion about two potential algorithmic concepts for a-
posteriori correction of local timing errors. The first one is a natural extension of ampli-
tude calibration to the time domain. In the second method we define, structure and discuss
the generalized mapping concept, which is a novel concept developed in [143] that offers
several strong advantages compared to calibration. Its most significant advantages are:

it can deal with all spatially local errors simultaneously using the same error pro-
cessing and control hardware;

it requires no actuation to be applied in the control phase, thus no circuit properties

or hidden parametric signals of the basic HW need to be altered;

it offers the advantages of digital circuitry scalability with the process evolution
because it can be implemented solely in the digital domain.

10.3.1 Calibration in amplitude and time domain

Calibration is the act of checking and adjusting the accuracy of an instrument by com-
parison to a standard. Used in the context of circuits, it means the act of adjusting the
value or the behavior of an electrical output signal of a circuit. For example, calibration
can be applied to adjust the amplitude of current sources, the output current values of the
DAC, or the timing of its switching circuits. All calibration methods are based explicitly
on a-posteriori error information. Calibration consists of the following sequence of steps:

1. Detection of the errors (information acquiring phase) .

2. Processing of the error information, i.e. comparison with a reference and decisions
with respect to an algorithm.

3. Application of the result of the algorithm with a control circuitry.

This section offers an overview of the calibration techniques and problems encoun-
tered in literature and classifies them according to their principle of use.
10.3 A-posteriori error correction methods 149

Calibration of local amplitude errors

The overall goal in any amplitude related calibration method is to adjust the DC transfer
characteristic of the DAC within predetermined INL and DNL specifications. At which
nodes of the DAC this loop is applied, how the steps are implemented with circuits, and
how their steps are executed with respect to the normal operation of the DAC sets criteria
to differentiate them in different categories. The high level block diagram of fig. 10.2
shows this categorization.
The first distinction we can make in this figure is between methods that correct the in-
dividual current sources one by one adjusting it to the reference, and methods that correct
the total output current of the DAC for each input value. The first category can be further
distinguished in two subcategories based on whether the correction is based on modifica-
tion of parametric signals of a circuit (e.g. the biasing voltage of a MOS current source),
or it is based on the addition of correction signals (currents) that approximate the desired
value with greater precision. The information, processing and control flow of the two
categories is depicted conceptually in fig. 10.2(a) and (b), respectively. Comparing fig.
10.2 with fig. 10.1 we notice that calibration uses only a subset of information available,
namely information about the actual local amplitude errors.

Basic HW Basic HW
Input signal Input signal Output signal
Output signal

Control of Detection
correction of signal
current, etc. errors
Control Detection
of parameter, of unit a−posteriori
correction errors error information
current, etc.
Algorithm:
a−posteriori
error information (comparison, decision, etc.)

Algorithm:
(comparison, decision, etc.)

(a) (b)

Figure 10.2 Calibration conceptual diagram (a) current source correction, (b)
output current correction.

Dependent on how the three steps of the calibration method are scheduled we may
speak of Start-up Calibration methods and On-going Calibration methods. The former
is a method that is executed once when the chip is powered up. They require the use of
the output current to detect the errors, hence they require that the DAC stops its normal
operation and enter the calibration phase. The latter method is continuously carried out
and refreshes, or updates the control signals within a period of time. On-going Calibration
can be divided in two new subcategories: Off-line Calibration and On-line Calibration.
150 Chapter 10 Synthesis concepts for CS DACs

The former technique substitutes an element in DACs current cell array, calibrates it, and
returns it back. Thus, Off-line Calibration is carried out while the current cell under
calibration is not operating. On-line methods calibrate the sources without the necessity
to exchange elements during the normal operation of the DAC.
Calibrations methods that correct the output current of the DAC are the least suitable
for dynamic performance because their fine DAC must be utterly identical in switching
behavior with the main (coarse) DAC. Therefore, on top of the large number of dynamic
problems of the main DAC one has to consider the addition of the dynamic problems of
the fine DAC. For example, a very significant problem added is the synchronization of the
main DAC the fine DAC, and the synchronization of the fine’s DAC elements with respect
to each other. A significant problem related mostly to the On-going calibration methods
is that they require specific modification of the switch current cell to provide detection
means. For example, in [42] a resistor is added below each current source to convert the
unit current into a voltage that can be measured. This resistor can remove vital voltage
headroom that could allow optimization of the current cell for dynamic performance.
The best way to make calibration without jeopardizing potential for dynamic perfor-
mance is to make it in such a way that it has no dynamic characteristics, or it does not
require any critical modifications of the SI cell to operate. This can only be achieved with
fixed correction currents per unit current source using dedicated calibration DACs [43] or
fixed corrections of biasing voltages with dedicated calibration DACs [157].

Calibration of local timing errors

Timing error calibration is better well known as active deskew, or phase correction of volt-
age pulse signals. It is well known to be applied primarily in delay elements, e.g. [158],
Delay-Locked-Loops, Phase-Locked-Loops etc. as far as building blocks are concerned,
which are subsequently used to correct local and global timing errors in Time-Interleaved
applications, clock distribution networks for Microprocessors [159,160] reaching already
correction accuracies at the psec level. The way corrections are made is by sensing the
phase difference between the reference signal and the signal to be adjusted with a phase
detection circuit, convert it to a voltage level that can be processed, and then via a decision
making and control loop to modify a parameter of the circuit that affects the timing of the
signal that is to be corrected [158, 159]. Examples of parameters that are modified are the
resistance of an active device, a bias current, etc.
In DACs calibration of local timing errors has never been applied, yet. Two important
reasons for this are: first, the timing errors although discussed very often in high speed
DAC circuit implementations were never examined in detail as to reveal clearly how much
of a problem they are, and how severe impact they cause. Second, global errors mech-
anisms seem to prevail in the DAC landscape nowadays, and before timing errors are
calibrated something has to be done to deal properly with global errors.
A major difficulty lies in the detection process, which requires sub psec accuracy.
Detection of timing errors in the sub-psec region have been reported [161] for voltage
signals (e.g. in a DAC that would correspond to a local clock signal, or a switch control
signal). However in a DAC it becomes much more difficult as the detection process, first
10.3 A-posteriori error correction methods 151

it may impair the normal operation of the DAC, second it has to be applied to a large
number of signals, and third, if it has to be made in the current pulses because otherwise
no information can be obtained about the errors following the signal that is detected. .
Control is the second problem because it requires strong interaction with the main HW
switching components to correct them in the same region of 1 psec. Finally, spatial timing
errors are caused by many origins that are in the first order equal in significance with
respect to each other. Therefore, because calibration can be applied only at one signal at a
time (e.g. the clock arriving at the input of a latch) out of the many contributing to timing
errors per chain, the corrected signal should compensate the remaining errors.

10.3.2 Generalized mapping

Generalized mapping is an alternative to calibration. It is a novel concept proposed in
[143, 162, 163] that can be applied to the class of local errors in general, simultaneously
for all its members and independent of the physical origin of the local amplitude and local
timing errors. In the following paragraphs it will be further described,

The generalized mapping concept

The concept of mapping represents the assignment of an abstract code digit with the
proper weight, to a current unit with the same weight. In fact, it maps a code unit to a
specific physical element, or chain of elements that generate this current unit, and after this
mapping the current corresponds to this code unit. For example, each thermometer digit is
mapped to a specific combination of a latch, a driver and a current source. In mathematical
terminology we speak of a one-to-many mapping because different combinations of the
physical elements can be assigned to the same digit.
Let us see the case of a thermometer coded DAC with 2N −1 digits Ti , i ∈ {1, 2, ..., 2N −
1}. Each of the digits needs to be associated with a specific unit chain consisting of a latch,
driver and switched current cell (named unit DAC from hereafter). The key property of
this code is that it has redundancy; that is, given 2N − 1 physical elements it makes no
difference which code unit is associated to which unit DAC. All different mappings are
possible. Therefore in a configuration we may assign the bits Ti , i ∈ {1, 2, ..., 2N − 1} of
the decoder’s output to any of the unit DACs e j with j ∈ {1, 2, ..., 2N − 1}:

Sk : Ti → e j

In other words, assuming a ramp input signal the map decides with which order the el-
ements are used. An example of mapping is given in fig. 10.3 for a 4 bit thermometer
DAC. The possible mappings available for this case are 2N ! (factorial of 2N ), hence for
the given example 15!. Mapping is realized with the proper physical connections, e.g.
between the output of the decoder and the input of the latch,
As we know the elements composing the unit DACs create local errors in timing and
amplitude. When a fixed map Sk is selected, and an input signal is provided, a specific
output error pattern is generated. The generated errors per sample w, or sample to sample
152 Chapter 10 Synthesis concepts for CS DACs

Thermometer bits Ti unit DAC e j

1 2 3 4 1 2 3 4

Input 5 6 7 8 Mapping 5 6 7 8 Output

15
(2 −1)!
9 10 11 12 9 10 11 12
possibilities

13 14 15 13 14 15

Figure 10.3 Mapping in a 4 bit thermometer DAC.

transition w0 → w1 are described with

w
Ierr (w) = ∑ ∆Ii (10.1)
i
w1
1
TE (w1 , w0 ) =
|w1 − w0 | ∑ µj (10.2)
j=w0

where ∆Ii are the amplitude and µi are the timing errors of the unit DACs, Ierr (w) is the
equivalent amplitude error, and TE (w1 , w0 ) is the equivalent timing error for the sample
w and the sample transition w0 → w1 , respectively1 For the same input signal a differ-
ent output error is generated when different mapping is used because different elements
-thus, different local errors- are combined for the same sample to sample transitions. Con-
sequently, the mapping has an influence on the signal error created by local errors (timing
and amplitude) and it can be used as a degree of freedom.
The key information that can be used is error information: that is, a map can be
selected such that the amplitude error per sample w, and the equivalent timing error in
a sample to sample transition are minimized. For example, a properly selected map can
organize the elements in such a way that any combination of elements that corresponds to
a sample to sample transition at the input results in a equivalent timing error at the output
signal that is very close to the average equivalent timing error of all unit DACs. In this
way every possible sample transition has very similar characteristics.
The maps that can be selected is not limited by the mentioned cost functions. The
large number of possible combinations of elements and the fact that in reality globally
optimal mapping is not necessary allows to use another significant degree of freedom. An
important property of the mapping concept is that a map can jointly optimize the error
reduction of both amplitude and timing errors. In other words, the mapping algorithm can
apply multi-dimensionally in both amplitude and time with the hardware that implements
the algorithmic and the control functions, and using different hardware only for detection!
This a direct benefit of the fact that mapping can deal with all problems that belong to the
class of spatially local errors. In fig. 10.4 the mapping concept is shown as it is applied in
a DAC. This figure uses a subset of the blocks given in fig. 10.1 highlighting only the fact
that error information can lead to a proper selection of a map and also that this mapping
1 The symbol TE of the equivalent timing error is different from the symbol Ti for the thermometer bit.
10.3 A-posteriori error correction methods 153

Basic HW
Input signal Output signal
Mapping

control based on error, signal,

and other relevant information

Figure 10.4 Mapping conceptual diagram.

method is realized in the signal flow of the DAC.

Mapping in unit elements

A further application of the mapping concept is possible between physical elements. Each
physical element e j , j ∈ {1, 2, ..., 2N − 1} is partitioned to M physical subelements (e.g.
each unit current source consists of M smaller current sources connected in parallel).
Any previous association between a physical element and its specific (partitioned)
M subelements can be erased and consider simply (2N − 1) · M subelements arranged in
an array. By re-grouping the subelements in groups of M units, 2N − 1 new elements
el , k ∈ {1, 2, ..., 2N − 1} can be made. This operation (one-to-many) is in fact another
degree of freedom because having knowledge about the behavior of the spatial errors in
the subelements they can be selected such that the newly created physical elements el
have less errors compared to e j . This type of mapping is commonly applied in current
source transistors of large arrays. Each transistor is partitioned in many subelements (e.g.
16 in [41, 66]) and then the elements are placed in locations far away from each other to
average gradients errors [41], or in locations having common centroids.

Static and Dynamic mapping

Mapping can be further categorized to static and dynamic. A static map relies on opera-
tions in the spatial domain only, therefore it can be said as well that it is a static spatial
map. Once selected (before or after the fabrication phase) it does not change in time. A
dynamic mapping method means that different static maps are time interleaved at various
moments in time. Dynamic mapping applies both in the spatial and the time domain.
Hence, it may realizes space/time mapping, and can be called a spatial/temporal map.
When a static map is used the errors are confined in the bounds determined by the map.
Still, a small error remains that is associated with the input sample, only that it is much
smaller than when no proper map is used. If now a set of maps is found that have identical
or comparable performance (in practice a map does not need to be optimal, but it can be
suboptimal as well) then in different moments in time different maps can be used. In this
154 Chapter 10 Synthesis concepts for CS DACs

way, time averaging of the errors or other temporal processing operations can be used to
de-correlate the spatial errors from the signal.
How this map-hopping is realized can be a function of other constraints. It can be
randomly selected, it can follow a specific cyclic pattern, it can be input data dependent,
or it can be selected such as it realizes noise shaping. In this way the advantages of spatial
and temporal mapping can be combined.
Several of the sources of information shown in fig. 10.1 can be used to facilitate the
selection of a map if they are properly embodied in cost functions, and the proper map
selection algorithm is realized. This applies to both amplitude and timing local errors
with no exceptions. A product of fig. 10.1 is fig. 10.5 that describes in more detail the
concept of mapping selection. The information stream available for processing, the two

Basic HW
Input signal Output signal
Mapping

signal
mapping selection

Optional
A−posteriori

extra HW spatial error

(detection) error detection
detection

Output info
Input info (a−posteriori)
(a−posteriori)
Mapping selection algorithm
(a−priori) Output info (a−priori)

User info Application info Environment info

(a−priori and a−posteriori)

Figure 10.5 Mapping concept applied to the DAC.

dimensional spatial errors (amplitude and timing), and the large number of combinations
usually available makes mapping a truly multi-dimensional problem.
The possibilities that open with this concept are significant given that with the excep-
tion of the error spatial profile detection operation (which can be done at very low speeds
when the DAC does not operate) the rest of the processing is made in the digital domain.
The circuitry required for detection of errors is the same with that used for calibration.
Therefore, the signal detection process is made in the analog domain, however the er-
ror correction phase is done in the digital domain. The most important difference with
calibration is that after the processing is made no further tuning needs to be applied to
the basic HW to reduce errors. Once a map is found and the digitally realized mapping
10.3 A-posteriori error correction methods 155

circuitry is programmed no further interaction is required. Therefore, the potential capa-

bilities of this concept are only limited by digital based processing capabilities, potential
size, power consumption and other problems that are similar with the traditional binary to
thermometer decoder. In the next paragraphs we will present which special (degenerated)
cases of this overall framework have been used in literature until today, and their scope.

10.3.3 Applications of generalized mapping

In this subsection we will review briefly two degenerated cases of the generalized map-
ping concept that have appeared in literature: switching sequences, and dynamic element
matching. In both cases, the maps have been used to correct local amplitude errors only.

Switching sequences
Switching sequences is a special case of the generalized mapping concept. A switching
sequence is a map that is used specifically to reduce the impact of spatially local deter-
ministic amplitude errors on the basis of a-priori error information. If ∆Ii = ∆ID,i + ∆IS,i
from eq. (10.2) represents the total error per element as the sum of a deterministic ∆ID,i
and a stochastic ∆IS,i component, respectively, then switching sequences are used only to
cope with the deterministic term. Usually a switching sequence assigns a specific map
between a current source value and a thermometer bit. The background of switching se-
quences is the following: the choice to increase the size of the current source transistors
to reduce the stochastic component ∆IS,i of the elements according to the models of [75]
enlarges dramatically the contribution of the deterministic component ∆ID,i . The effect
beyond 8 bits is so large that only with the use of switching sequences in combination
with the partitioning and mapping concept allows larger resolutions. Yet, even with the
extensive and impractical use of their combination (e.g, in [41] M = 16, N = 8 and a chip
area of 13.2mm2 ) no more than 14 bits can be achieved.
We see that the stochastic component of the error is addressed with an hierarchically
different method than the deterministic. Because the two subclasses random and deter-
ministic local amplitude errors depend in opposing ways with area √ (deterministic errors
scale up linearly with area, while stochastic errors reduce with 1/ area) a practical limit
is set with this approach. Furthermore, modern CMOS processes do not necessarily jus-
tify the simplicity of the a-priori assumptions of perfect gradients or parabolic surfaces
that reduce the accuracy of mapping even further.
Several symmetry based maps have appeared so far in open literature and in several
patent disclosures. The main thing that distinguishes all published methods different from
each other is the mapping Sk and how extensively it is combined with the partitioning and
mapping concept. The most important are

symmetrical switching scheme [38];

hierarchical symmetrical [63];

anti-symmetrical scheme [65];

156 Chapter 10 Synthesis concepts for CS DACs

partition and mapping with common centroid configurations called double-centroid,

triple centroid (e.g. [66]), etc. dependent on the number of segments;

Q2 random walk [41] in combination with partitioning in M = 16 units, which is a

switching sequence extracted with a Branch and Bounce based algorithm;

Sequences based on Magic numbers [164]

Full partitioning in 2N units and mapping based on common centroid algorithms

[77] (used in a binary weighted DAC).

Symmetric pair switching [165].

maps generated with the algorithms in [162, 163]

The common denominator in all of these mapping algorithms but the last is that they are
fixed and can deal only with local deterministic amplitude errors (gradients and parabolic
errors). This means that the accuracy of the DAC is set by the stochastic amplitude errors.
Switching sequences are usually implemented in the current source array between the
current source and the cascoding transistors [41, 66].
A very interesting subcase of the generalized mapping concept was proposed in [166],
called “the generalized decoding mapping”. It has been proposed to correct any ampli-
tude local error (stochastic and deterministic) by measuring the individual errors in the set
of thermometer currents (a-posteriori error information about amplitude errors) and then
finding the proper map with off-chip software means. This very interesting idea was ex-
perimentally verified but no attempts have been made ever since to refine and generalize
the concept. The experimental set-up in [166] processes the measured current source er-
rors off-chip and loads the proper map in an PROM. The “generalized decoding” scheme
explores only information about spatially local amplitude errors, thus it does not justify
generality.

Dynamic Element Matching

Dynamic Element Matching is a very popular temporal mapping technique that is partic-
ularly used in low resolution DACs aimed for Σ∆ converters (see [110] for an overview).
It a special case of dynamic mapping where for every sample a new map is used, and that
no spatial domain processing is exploited, relying only in the excessive use of temporal
averaging allowed only when a high oversampling factor is used.

10.3.4 Realization issues of the generalized mapping concept

Pros, cons, and some realization issues with respect to the realization of the generalized
mapping concept in hardware will be briefly mentioned in the next paragraphs, yet in the
conceptual level.
One significant advantage of the concept appears to be that it requires the same pro-
cessing and control method and corresponding circuitry to deal with all local errors. That
10.4 Conclusions 157

is, be it timing or amplitude, once (separate) detection circuits are used and the error in-
formation is extracted, the processing and the control circuits to make the corrections are
one and the same. While usually calibration requires to actuate such that it corrects a
particular error in the circuit that generates it, mapping does not interact with the basic
hardware because it relies on a programmable digital circuit that re-associates which bits
go to which latch data inputs. At the same time, timing and amplitude local errors can
be measured at the output current pulses, meaning that this method deals with all contri-
butions of amplitude and timing errors simultaneously without any requirement to know
which one is dominant over the other. In fact, the detection circuits to obtain error infor-
mation do not interfere at all with the critical nodes at which the origins of timing errors
are generated. Had it been for calibration, then the detection phase would correspond to
a specific subcase of local timing errors (e.g. clock skew, latches), interfering with the
corresponding nodes such that it measures the errors, while the correction phase should
have to be specifically applied at the analog circuit elements by modifying electrical pa-
rameters, thus interfering with the operation of the basic HW.
Once the errors are processed, and a proper mapping is found no other actions are
required for corrections, thus the DAC can operate without any modification of the basic
hardware. The control and the mapping circuits are realized with digital circuits, thus they
are scalable and they can benefit from the continuous shrink of digital circuits. The sim-
plest form of a mapping circuit is a combination of digital multiplexer circuits. However,
the mapping circuit lies in the signal path flow of the DAC. Therefore, although the basic
HW properties will not be modified during normal operation, it is subject to the same
problems that the thermometer decoder has as well: switching disturbances in the power
supplies and substrate noise, etc.
A final point to be mentioned concerns the on-chip integration of such an approach.
In the ultimate case, the generalized mapping concept is realized on-chip with efficient
algorithms implemented in digital circuits. This would also make proper adaptations of
the maps during the life time of the IC.
It may be argued that the feasibility of such an approach is limited by the complexity
of digital operations required by the map computation algorithm. Indeed, investigation on
realization of the concept has shown that at the moment on-chip mapping computations
seems inferior to computations realized with software optimized algorithms. Also that
several practical circuit aspects need to be solved. However, this approach is expected to
benefit directly from the digital process shrink that offers more and more on-chip compu-
tational power at very small cost in area

10.4 Conclusions
A description of synthesis aspects for CS DACs was given in this chapter. A synthesis
policy for wideband high dynamic range CS DACs was defined.
The DAC circuits were distinguished at the high level between the basic and the op-
tional HW. The basic HW realizes the main conversion function, while the optional hard-
ware realizes correction algorithms that aid the efficiency of the conversion and facilitate
158 Chapter 10 Synthesis concepts for CS DACs

better signal quality, better usage of the available resources, etc. A main aspect in the
CS DAC synthesis was shown to be the management of information about the actual and
hidden signals of the DAC, its properties, the error mechanisms, the technology and other
main information sources. This high level view of DAC synthesis reflects the necessities
imposed by trends in the design of DACs as explained in the the preface.
The way this information stream is exploited by algorithmic concepts was given. In
particular, the information about the CS DAC was partitioned between information avail-
able at the design phase (a-priori) and information only extracted after it (a-posteriori). It
was discussed that algorithms exploiting a-priori information are more efficient in dealing
with deterministic errors than random errors. Algorithms based on a-posteriori informa-
tion prove to be efficient in dealing with random errors as well because they translate
randomness to determinism, which is easier to cope with. CS DAC synthesis policy lines
were defined to investigate the exploitation of a-priori and a-posteriori error information
for timing errors and to demonstrate that the analysis conducted in previous chapter can
be transfered effectively to specific synthesis of high performance DACs.
 11

Design of a 12 bit 500 Msample/s DAC

I N this chapter the design of a wideband high dynamic range Current Steering DAC
will be presented. Its design is based on a-priori error mechanism information of dom-
inant error mechanisms for high frequencies. The DAC has 12 bits and operates up to
500 Msample/s with exceptionally good high frequency linearity at low power cost and
silicon area. It is realized in a CMOS 0.18 µ m process.

11.1 Design approach

In chapter 4 it was shown that in most wideband CS DACs their SFDR starts at a very high
value (e.g. 80 dB) and drops abruptly at signals exceeding approximately a few tenths of
the conversion rate. Only a few cases of smooth degradation have been reported [43, 59,
68]. It can now be understood that such rapid degradation of linearity can be anticipated
only by global errors since local errors scale smoother with the signal frequency as the
result of the averaging principle that governs their error mechanism. This indicates that
settling behavior and impedance, power supply and substrate noise, interference in the
bias lines, seem to be most often the major cause of high frequency linearity degradation.
In this design global and local error mechanisms will be addressed with circuit tech-
niques separately to avoid compromises due to trade offs. The following principles are
followed:

1. prevention of error mechanisms is preferred than suppression, or compensation;

2. the number of global error mechanisms is reduced, or they are translated to local
ones, which are easier to cope with;

159
160 Chapter 11 Design of a 12 bit 500 Msample/s DAC

3. magnitude of local errors is reduced;

4. simple techniques are applied, e.g. no calibration or error control loops.

A summary of design specifications is given in table 11.1.

Specification Value
Resolution 12 bits
Conversion rate > 500 Msample/s
Full scale current 20 mA
Load 25 Ω
Technology CMOS, 0.18 µ m
Power supply 1.8 V
Power consumption around 200 mW
Area around 1 mm2
SFDR low frequencies 75 − 80 dB
high frequencies 60 − 75 dB

Table 11.1 Summary of specifications.

11.2 Architecture
This section gives a description of the architecture of the DAC, and explains the back-
ground of many choices taken at this level.
The architecture of the DAC is shown in fig. 11.1. It is a 6/6 thermometer/binary
segmented CS architecture that consists of a non-pipelined 6b binary to thermometer de-
coder, a delay equalizer, master-slave latches, switch drivers and switched current cells.
The subcircuits shown in fig. 11.1 are all parts of the basic HW that was shown in fig.
10.1. None of the optional circuits of fig. 10.1 that detect, process and correct errors in
a-posteriori manner exists in fig. 11.1.
In the remaining of this section the architectural issues that are discussed are the sig-
naling and circuit logic type of the DAC subcircuits, the partitioning of their biasing and
supply signals, and the thermometer/binary bits partitioning,

11.2.1 Signaling and circuit logic

Local timing errors due to mismatch, and global timing errors due to supply and substrate
noise have opposing demands. The former calls for fast switching signals and many ele-
ments, the latter for slow switching signals and a few elements. The high common mode
noise rejection of differential signals in combination with the low supply and substrate
disturbance offered by low swing Common Mode Logic (CML) [101, 167, 168] decou-
ples local and global timing problems and facilitate maximum focus on each error class.
11.2 Architecture 161

off−chip low swing data

input buffers
B6−B11 B0−B5

6b decoder delay equalizer

bias inputs
clock in
thermometer bits binary bits

master latches
clock

bias inputs
slave latches

switched current cells

output

Figure 11.1 CS DAC architecture.

This combination is used for all circuits in the signal flow from the off-chip input to the
off-chip output of the DAC.
At the analog output side, differential signaling reduces substantially the errors due to
nonlinear settling and DAC output impedance because the distortion generated by these
problems is mainly of second order. Current mode circuit implementation of the SI cells
is of course the default characteristic of the Current Steering DAC. The choice to use
low swing differential signaling and CML was until recently [68] only characteristic of
non-CMOS DACs. CMOS DACs werebased on single-ended signaling circuits realizing
CMOS logic everywhere in the signal flow but the SI cells.

11.2.2 Power supply and biasing

Biasing voltages and power supplies are crucial in CML logic circuits, which, if not prop-
erly shielded from switching signals and data-dependent activity, can give rise to signifi-
cant error mechanisms, as it was explained in chapter 5.
Separate supplies and biasing for the clock, decoder and master latches, slave latches
and drivers, and current sources were used to eliminate such error mechanisms. Multiple
of pins per supplies were used in the package to reduce the inductance of the bonding
wires interfacing the on-chip to the off-chip supplies. Furthermore, local decoupling ca-
pacitances were used as local are pools of charge to allow a portion of the switching
charge required by switching circuits to be drawn by them instead of the external power
162 Chapter 11 Design of a 12 bit 500 Msample/s DAC

supply via inductive leads. An additional solution (not used here) is to introduce comple-
mentary switching functions [43] to cancel out the data-derivative dependent modulation
of the supply voltages. This principle can be applied to any global node modulated by
data activity (e.g. [82] is applied to cancel out the charge feedthrough at the DAC output).
The clock buffer, decoder and master latches, slave latches, drivers, and SI cells have
independent biasing circuits so that switching interference from one circuit to another via
the biasing lines is avoided. Additional local biasing is used for each individual current
source cascode transistor. Finally, the off-chip to on-chip bias current mirror ratios are
large to attenuate off-chip to on-chip translation of noise and interference.

11.2.3 Thermometer/binary bits partitioning

The number of bits assigned to the thermometer and binary segments is one of the most
important architectural issues in the design phase. The 12 binary code words fed to the
DAC from the external source have been partitioned in 6 thermometer (MSB’s) and 6
binary bits (LSB’s) represented by NT and NB , respectively. This choice was based on
1. MSB/LSB glitches,
2. timing precision requirements of the thermometer segment,
3. noise generation in the supplies due to switching activity,
4. speed, area and power consumption.

Glitches
MSB/LSB glitches is the traditional error discussed in literature in association to code
partitioning. It is well understood that significant nonlinear distortion originates from all
those errors whose error generation mechanism is a function of the number of binary bits
NB . These errors reduce as the number of thermometer bits NT increases, because the non
linear mechanism is translated to linear [8]. The suggestion in [8] to maximize NT to the
point tolerated by area constrains is one-sided because it assumes that no other dynamic
problem scales with the partitioning. For this design MSB/LSB glitches caused by timing
skew, and those caused by charge feedthrough are distinguished. The magnitude of the
first type is a major function of the actual timing differences: the smaller the timing error
between thermometer and binary transients, the less the error. In contrast, the second type
still exists even with perfect timing. Both problems were evaluated with transistor level
simulations. For 6 thermometer bits, circuit level simulations showed that with a relative
tight degree of synchronization (less than 10 psec) between MSB’s and LSB’s, the distor-
tion levels are sufficiently low for up to a few hundreds of MHz of signal frequencies.

Timing accuracy in the thermometer segment

The required timing error spread for the thermometer current transients for an SDR of
74 dB (ideal 12 bit DAC) are given in table 11.2 The Signal to Distortion ratio (SDR)
11.2 Architecture 163

values for the given timing spread σ of the thermometer current transients were calculated
using eq. (8.16) in which signal frequency is fixed at the Nyquist of the corresponding
conversion rate (e.g. 200 MHz for 400 Msample/s). As it can be seen in fig. 8.4 large

NT σ at 200MS/s σ at 400MS/s σ at 650MS/s

6 2.8 psec 1.4 psec 0.9 psec
7 4.0 psec 2.0 psec 1.2 psec
8 5.6 psec 2.8 psec 1.8 psec

Table 11.2 Timing spread requirements for thermometer unit currents.

deviations can occur from IC sample to sample. Consequently, at least a 3σ specification

should be applied if the SDR is to be guaranteed for a large number of IC samples. Notice
also that although the SDR can be bounded to a small window around its mean value when
several IC’s are examined, the SFDR can vary considerably from sample IC to sample IC
(always larger or equal than the SDR of the specific IC) because of the random nature of
the errors, meaning that the total harmonic distortion power will be distributed in several
harmonics differently for each IC. As a result of this power spreading, an SDR of 74 dB
should be sufficient for an SFDR of the same or higher level.
To guarantee timing accuracy in a few psec’s the decision taken was to restrict NT to 6
so that deterministic local timing errors at the input and output nodes of the chains (clock
and output current summation networks) could be controlled well, and spend the proper
amount of power to make very steep transistions and keep random local timing errors less
than σ = 3 psec. Then, 74 dB SDR are achieved up to 120 MHz for 400 Msample/s
(67 dB at Nyquist) and up to 50 MHz for 650 Msample/s (64 dB at Nyquist). This seems
sufficient to keep the SFDR within the values mentioned in table 11.1.

Supply and substrate disturbances

The number of thermometer bits and the circuit topology of gates, drivers and latches play
a crucial role for supply disturbances and can easily generate global timing errors. Some
authors [67] mention that switching activity increases as NT goes up. To evaluate quali-
tatively the relation between disturbances and number of thermometer bits, the switching
activity (the number of switching actions of a circuit per sample to sample transition)
should be separated from the actual disturbance of each switching action. The latter is a
function of the magnitude of dynamic currents drained/dumped to the supplies and sub-
strate by a switching circuit. The disturbances are functions of both factors but not in
the same way for all the subcircuits of the DAC (decoder, latches, SI cells, clock buffer).
Therefore, the optimal number of NT with respect to such disturbances depends always
on the specific choices for the circuits and their switching strength.
Generally speaking, slow switching signals and small number of switching elements
are beneficial for low disturbances. However, this is not beneficial for low local timing
errors. Consequently, another tradeoff appears. This tradeoff was avoided altogether here.
164 Chapter 11 Design of a 12 bit 500 Msample/s DAC

Because of the logic style and power supply partitioning selected to specifically address
these disturbances, the value of NT is basically decoupled from the issue of disturbances.
In other words, NT is selected considering only local errors. Circuit simulations with RLC
models of the power supply network were used to verify this choice.

Area and power consumption

In the previous paragraphs area and power consumption were viewed from the perspec-
tive of their influence on the local timing accuracy. However, area and power are very
important also in absolute terms, and they are influenced by the choice of NT [8] because
this determines number of elements and interconnect lengths. The speed of the decoder
can be an issue because the larger the NT , the larger the logic depth of the decoder, thus
the larger fraction of the sampling period its delays occupy. The intention to achieve ap-
proximately 1 mm2 of total area and power consumption around 200 mW prohibited the
use of more than 7 thermometer bits.
As a result of all the issues mentioned in the previous paragraphs, a partitioning in 6
thermometer and 6 binary bits was selected.

11.3 Switched-Current cell

The schematic of the realized SI cell is shown in fig. 11.2. It consists of a cascoded current
source, a cascoded differential switch pair, and local biasing means. In the following the
design of the circuit blocks will be described.

Vdd M3 M4 Vdd

global
Z Ms1 Ms2 Zb
Mlb3 Vx

local V2
Mlb2 M2

Mlb1 V1 M1

Vss

Figure 11.2 Schematic of the realized SI cell.

11.3.1 Current source

The issues considered at the current source design are local amplitude errors, settling time
and impedance modulation, interference at the biasing lines, and substrate noise.
11.3 Switched-Current cell 165

Local amplitude errors

To achieve 12 bit static accuracy in the converter, the currents of the individual thermome-
ter sources should match very well to each other, and the binary ones should be scaled
with respect to the thermometer currents and relatively to each other with the proper bi-
nary scale. Several techniques were used in this design to achieve 12 bit accuracy level:

1. 6/6 code partitioning to reduce the matching requirements between the current
sources for 12 bit DNL;

2. Sizing and biasing [54, 75] aiming to reduce local random amplitude errors: when
the source area increases, the random amplitude error reduces;

3. Partitioning of each current source transistor in four subunits connected in parallel,

placed in four separate arrays, and biased locally to reduce deterministic errors [8];

4. A-priori amplitude error information mapping between thermometer bits and the
current sources to reduce local amplitude deterministic errors;

5. Common-centroid based placement of the four subunits of each source with respect
to each other to reduce the deterministic amplitude errors even further.

6. Electrical and geometrical symmetry in the layout to reduce random and determin-
istic errors (e.g. identical surroundings for each source, metal coverage, etc.

The parameter values used are 48µ m2 for the LSB transistor area, V1 = 0.85V for
the biasing, W1 = 3 µ m and L1 = 16 µ m. V1 was kept low to free voltage room for the
cascodes and switches to be optimized for dynamic performance. The width scales up
according to 1, 2, 4, 8, 16, 32, 64 according to the bit weights.

Nonlinear settling and output impedance

The next problems addressed concern output resistance modulation based errors (section
5.1.2), and most importantly the error mechanisms described in section 5.2.1): data de-
pendent settling, and the frequency dependency of the SI cell output impedance. The last
two errors are basically caused by capacitances present at the inner nodes of the SI cells.
This sets the focus of the following paragraphs.
Let us look some circuit details of these problems with the SI cell shown in fig.
11.3(a). It consists of a single MOS current source and a differential current switch (Ms1
and Ms2 ) connected directly to the resistive output load of the DAC. It is well known
in literature that this configuration is very problematic with respect to all three problems
mentioned, mainly because of the capacitance at node X (it is large because M1 is large).
If the switch is in the off state (e.g. Ms1 off, Ms2 on), the capacitance seen at the output
of Ms1 is the sum of the gate-drain overlap capacitance Cgd , and the drain-bulk junction
parasitic capacitance Cdb of the MOS switch. From these two, Cdb is voltage dependent,
that is, Cdb = Cdb (V ). As the output signal varies, the capacitance contribution Cdb of
all SI cells varies with the output signal. This capacitance is independent of whether the
166 Chapter 11 Design of a 12 bit 500 Msample/s DAC

Vdd Vdd Ms1 Ms2

Ms1 Ms2
Ms1 Ms2 X X
Ms1 Ms2 Vx
V2 M2
X
Y X
M1
V1 M1 V1 M1 M1

(a) (b) (c)

(d)

Figure 11.3 Cascoding options (a) no cascode, (b) single-cascode [38, 51], (c)
single-cascode (or combinations) on top of the switches [90], (d)
gain-boosted cascode.

switch is on, or off. When the switch turns on and operates in saturation -normally the
case- a capacitance is added to the output dependent on the capacitance of node X and the
cascoding capabilities of the switch. The output capacitance of a cell is written as

Co f f = Cgd +Cdb (V ) (11.1)

Con = Cgd +Cdb (V ) +Cu (11.2)

and for the thermometer DAC the total output capacitance becomes

C0 = (2NT − 1) Cgd +Cdb (V ) + wCu (11.3)

where w has its usual meaning. Equation (11.3) shows two types of signal dependent
global errors, one explicit and one implicit, both of which are generated by a modulation
of the DAC output capacitance (circuit parameter). The implicit one is generated by the
voltage dependent junction capacitance of the switch (this voltage is the output signal).
This capacitance depends only on the switch dimensions, hence the switch should be made
small. If the switches are small and operate deep in saturation the Cdb (V ) modulation is
small, and the explicit error mechanism is dominant.
The explicit error mechanism is generated by the on/off capacitive difference of each
cell and the number of cells turned on, assuming no dependency with the output sig-
nal. The capacitance at node X is determined by the capacitance of the switches, the
capacitance of the transistor M1 and their interconnection. The drain and interconnect ca-
pacitances are usually large. The former because of the choice to increase the area of M1
to improve matching, and the latter because of a combination of reasons. To reduce the
distance between current sources from different SI cells (thus the systematic amplitude er-
rors) and to avoid cross-talk between biasing and output signal lines with data switching
lines, the source array is split from the switch, latches and other arrays. Since M1 is large,
the source array is large, the interconnects run to establish electrical connection between
switches and sources are large, too. Substantially more interconnect is added because
each current source transistor M1 is partitioned is smaller transistors parallel-connected
11.3 Switched-Current cell 167

placed far away from each other (e.g. 16 in [41, 66]) to average systematic matching er-
rors. Therefore, improving matching with current source area seems to be the ultimate
limit for the capacitance at this node which has to be shielded by circuit design.
As mentioned earlier, the use of differential output signals reduces those errors signif-
icantly, because they introduce mainly second order harmonic distortion. However, only
this signal level technique is not enough. Other techniques that can help are

Cascoding, gain-boosting, etc. (see fig. 11.3) and reduction of transistor size and
interconnects reduces the output capacitance of the cell, thus the errors as well.

Reduction of the load each SI cell sees at its output locally at the output of each cell
with local buffers, or globally for all cells after they are connected together. Each
way can be implemented with cascode configurations (e.g. local buffering with
cascode transistors on top each switch per cell [90]) or with the current folding
method (e.g. global buffering with folding [42, 169]). The main differences are:

– Current folding requires extra power and gives also a constant DC current.
– Cascoding consumes no power, it is faster, but it occupies voltage room.
– A global buffer adds extra distortion and bandwidth limitations because it has
to process the total signal.
– Local buffers add matching related errors.

One can reduce the off-state resistance and capacitive difference by not turning off
the current cell completely in the off state [170]. The disadvantage is that in practice
significant local amplitude errors are created due to mismatch.

Compensation of the on/off capacitance modulation per cell with circuit techniques.

In this design the single cascode configuration shown in fig. 11.3(b) was selected (in
fig. 11.2 the complete cell is shown), and the capacitances were minimized by circuit and
layout design. Since the current of M1 is fixed and the width and length of M1 follow
matching considerations, the main decision left for M1 is where should its drain voltage
set. VD1 is pushed down to 0.5 V to free voltage room for the cascode and the switching
transistors. This value takes into account for remaining glitches as well.
The next decisions concern the width, length, and the value of V2 of transistor M2 .
These values determine the cascoding applied to M1 and the V1 = 0.5 V level at node Y and
most of the capacitance at node X. A small M2 size was used to reduce capacitances. The
voltage V2 was set to V2 = 1.27 V and the dimensions to L2 = 0.28 µ m, and W = 0.42 µ m
for the length and width of the LSB, respectively. The width was scaled by 2, 4, 8, 16, 32
for the remaining binary cells and 64 for the thermometer ones. These values were set
after several simulations were made with which the impact of the M2 parameters were
studied at the distortion of the DAC output signal.
The minimum allowed value of the voltage at node X determines the remaining volt-
age room left for the switches. The value of VX is set by whoever of the switches is
turned on: given that the switch high voltage level is set to the power supply level, the
168 Chapter 11 Design of a 12 bit 500 Msample/s DAC

smaller the switch overdrive (the larger the switch W/L ratio) the higher VX . Due to the
bulk-source modulation of the threshold value of M2 (Vt ≈ 0.5 V ) for V2 = 1.27 V M2 en-
ters saturation above VX = 0.7 V and its cascoding effect increases. Beyond VX = 0.85 V
there is no significant benefit. A margin of 100 mV was designated for the spikes that
appear during the steer of the current from one side to the other. The result is a DC value
VX ≈ 0.85 V (0.75 V with a margin), which leaves 0.95 V available for the gate-source
voltage difference in the switches.
Analytical calculations indicate that to achieve 80 dB SFDR for a differential signal
(amplitude domain impedance error only), the LSB SI cell’s output impedance should
be over 4 MΩ, hence 62.5 kΩ for the thermometer cell. AC simulations of the M1 − M2
combination with their designated width and length values, and for VX = 0.85V shows
that the impedance specification for 80 dB is met roughly up to 100 MHz. However, there
is still the cascoding effect of the switches as a reserve. The capacitance at node X -major
contributor to the on/off capacitive difference at the output- equals 26 f F, and only 2 f F
are associated to M1 (the drain capacitance of M1 is approximately 160 f F excluding
interconnect). Consequenty, the dominant pole at node X is defined by M2 .

local local
Vdd Vdd Vdd
global Vb Ib2 Ib2
off−chip

local V2 local V2
Mlb2 M2 Mlb2 M2

Mlb1 V1 M1 Mlb1 V1 M1
Vss Vss Vss Vss Vss Vss

Thermometer cell #1 Thermometer cell #2 other cells

Figure 11.4 The cascode global and local biasing circuit.

Interference at the biasing nodes

For the biasing interference problems (see section 5.2.2), a single cascode configuration,
and a short physical distance between the switches and the drain of the cascode transistor
help in reducing the glitch area at node X and offer fast recovery. Three main techniques
from the SI cell point of view can be used to deal with this problem:

1. reduction of the overlap capacitances Cgd of M1 − M2 to scale down the magnitude

of charge burst interfering to the bias lines;

2. filtering of the interference at the bias lines to suppress the magnitude of the global
error mechanism.
11.3 Switched-Current cell 169

3. local biasing of the cascode and current sources, thus allowing the interference in
each line separately, but preventing the appearance of the global error mechanism;

The size of M2 has been reduced as it was explained previously. Instead of suppressing
the interference with filtering (point 2), the local biasing method was used (point 3) to
avoid the error generation mechanism to appear in the first place. The advantages of such
an approach (e.g. [36, 42, 43]) have been validated with simulations.

global local
off−chip Vdd Vdd Vdd Vdd
Vdd
4Ib1 Ib1 Ib1 Ib1 Ib1

V1a V1b V1c V1d

Vss Vss Vss Vss Vss Vss

subarray1 subarray2 subarray3 subarray4

local V2
local V2 M2
M2
V1a V1b V1c V1d
V1 M1

Vss

Figure 11.5 The current source biasing circuit.

The schematic of the cascode transistor’s biasing circuit is drawn in fig. 11.4. The
local biasing circuit consists of two diode-connected transistors that build 1.27 V when
supplied by 150 µ A via a PMOS current source. All PMOS current sources are con-
nected at their gates at the same diode-connected master PMOS source. The voltage Vb
is generated with the circuit shown in the left side of the picture. A clean off-chip current
reference is fed to an NMOS current mirror that subsequently feeds the diode connected
PMOS transistor. The design requirements for the local biasing unit is low output re-
sistance, low power and small area, which are contradicting. Transistor size and current
values were determined with simulations on the complete DAC to evaluate the impact of
the impedance of the local biasing node with the DAC signal distortion. Mismatch effects
in the biasing levels were examined but they do not cause any worries.
The biasing circuit for M1 is given in fig. 11.5. As mentioned earlier in the section, M1
of the thermometer cells is split in four subunits connected in parallel at their drains, each
subunit placed in a separate subarray. This allows two techniques to be used that reduce
the impact of process gradients and other deterministic local errors. First, the subunits
are placed such that they have a common-centroid at the center. This is explained later in
more detail. Second, for all the transistors of a subarray a local bias voltage is established,
e.g. V1a,b,c,d , instead of sharing the same bias V1 [8]. This reduces the impact of process
gradients developed in the x− and y− axis of the source array because all the subunit
170 Chapter 11 Design of a 12 bit 500 Msample/s DAC

transistors refer to their local array bias, which tracks the gradients.

Substrate noise
A very critical issue for the biasing circuits and the SI cells is substrate noise. Substrate
noise can affect both the current sources and the local biasing cells in two ways: globally
and locally. Global errors appear if the bulk-source potentials are modulated in the same
way for all identical transistors (i.e. for all M1 transistors similarly, for all Mlb1 similarly,
etc.). This translates to global errors dependent on the function of the transistors under
influence. Local errors appear if the substrate noise has a spatial distribution over the
current source, or local biasing array such that some cells are affected more than others.
To reduce both error mechanisms the following measures have been taken. The cas-
code biasing circuits (local and global) are organized in one array and placed relatively
close to the current source array. All the circuits of this array are supplied with the Vdd-
Vss rails that power also the current source array. This supply pair is decoupled with
a combination of local decoupling cells placed inside the cascode local biasing circuit
cells, of dummy current source cells that are connected as decoupling capacitors, and
with sandwiched Vdd-Vss multilayer metal interconnections that connect to the external
Vdd-Vss supplies. Low resistance power and ground rails ensure that all circuits supplied
by them see the same disturbances. The substrate is subsequently tied well to the Vss
rail both in the current source and the cascode biasing circuit arrays. These actions re-
duce substantially both local and global errors. The off-chip current in fig. 11.4 is fed to
an NMOS current mirror placed inside the cascode local biasing array. Because the bulk-
source terminals of the NMOS transistors are tied very well to each other, any bulk-source
modulation is minimized. Given a clean off-chip current, the gate potential follows that
of the Vss and the substrate and provides a clean copy of the current to the PMOS current
mirrors. The PMOS N-wells are tied to the Vdd of the local bias cell array, such that the
both their source and bulk terminals bounce in the same way. In the end the local currents
Ib2 stay clean of unwanted supply based modulation and clean currents are also copied to
the local Mlb1−2 transistors.
In the current source biasing circuit of fig. 11.5 the situation is similar. As a result,
because all the currents Ib1 and Ib2 in the two biasing circuits are clean and M1 and Mlb1
see the same Vss and substrate disturbances, the local V2 and V1 potentials fluctuate in
the same way avoiding any modulation in the signal currents generated by M1 . The only
least accounted effects is the capacitive coupling of substrate noise directly via parasitic
Nwell-substrate and metal-substrate capacitances. This mechanisms allows noise to cou-
ple directly to the nodes shown in the circuit schematics.

11.3.2 Switch
The design of the switch addresses charge feedthrough phenomena (section 5.2.4), spikes
and signal dependent modulation of the switch common source node (sections 5.2.2 and
5.2.3), and local timing errors (section 5.2.5). The critical design parameters for the
switch are its width and length dimensions, and the shape of its control signals including
slope, swing VSW and the actual transient shape. All these factors have an influence in
11.3 Switched-Current cell 171

the aforementioned problems. A typical differential switch is shown in fig. 11.6(a). The
switch realized in this DAC is shown in fig. 11.6(b).

Vdd Vdd
M3 M4

V Ms1 Ms2 V V Ms1 Ms2 V

D D D D

X X

(a) (b)

Figure 11.6 Current cell switches (a) non-cascoded and (b) cascoded.

Charge feedthrough phenomena are in the first order proportional to the channel and
overlap capacitances of the switch transistors Ms1 and Ms2 , to the swing of the switch
control signal, and its slope. The capacitances and the swing determine the total charge
deposited in the output node, whereas the transition time determines how fast it is de-
posited. Fast transitions concentrate the charge in sharper spikes. Consequently, small
swing, large transition time (small slope), and small switch size favors reduction of
charge feedthrough. The translation of the charge burst to a voltage spike depends on
the impedance at the node the charge is injected to.
The glitch area at node X depends on the time both switch transistors are simultane-
ously off, thus on how fast the driving signals are (a fixed crossing point level is assumed
here). The requirement for fast signals comes in contrast to that for charge feedthrough.
Similarly, to reduce the interference of the output signal back to the node X, the switches
ought to have good cascoding capabilities, which is not necessarily compatible with low
switch sizes (charge feedthrough demands), and low capacitance at node X.
Finally, large size of the switches has a detrimental impact on the local timing errors
caused by the switches and by all circuits preceding them for a fixed power budged. The
size of the switches causes a chain effect on the capacitance values present at the driver-
switch, latch-driver, and clock-latch nodes: as the switch size increases, more current
needs to drive it, therefore larger transistors are used at the driver, subsequently requiring
larger currents from the latch, and so on. Consequently, the magnitude of local random
timing errors at a fixed power budget increases. Therefore, a low switch size in the starting
point of a design-for-timing strategy in the DAC. In the following, the way those issues
were addressed in the design phase will be described.

Charge feedthrough
Charge feedthrough has been decoupled from the other problems to allow freedom to
focus on timing accuracy. The techniques that have been considered are:

1. Decoupling of the switch output node from the DAC output node with local or
global means identically to those used for the impedance (buffers, etc.).
172 Chapter 11 Design of a 12 bit 500 Msample/s DAC

2. Reduction of the charge injected per switching action using low voltage swing.

3. Compensation of each switching action with dummy switches [84, 171].

4. Compensation of the error-data dependency with a complementary mechanism [82]:

every cell, independent of whether it switches or not delivers the same charge.

The first technique has been repeatedly used in many DAC in the past in various forms.
The use of a single (global) buffer at the DAC output [42, 169] has several disadvantages
for high frequencies. Local cascoding [90] avoids these disadvantages. It can be realized
with NMOS cascode transistors as in fig. 11.6(b), and the disadvantages mentioned are
removed at the cost of voltage headroom, a small delay and probably additional timing
errors. If realized with a local folding circuit with PMOS transistors for each SI cell then
the voltage headroom is less of a problem, but the DC currents remain, and significant
local errors are added.
Reducing the voltage swing of the switch control signals is very effective to reduce the
charge bursts per switching action, and it can be easily combined with the first method.
The compensation method using dummies is limited by matching [84, 171] and it adds
extra capacitance at the drivers. This reduces the slope of the switch control signals and
increases timing errors due to threshold mismatch unless extra current is spent at the
drivers. The last technique applied in [40, 82] has also its pros and cons. In the way this
technique is implemented, the number of latches and drivers, the load of the clock, the
capacitance at node X (see fig. 11.6) and the output node are doubled compared to the
case that no compensation is applied. This implies that either the timing precision of the
switches and the latches and drivers will decrease, or the total power consumption will
double to sustain the same timing precision. Disturbances at the supplies double as well.
The combination of local switch cascoding with low swing control signals was pre-
ferred in this design (fig. 11.6(b)). The amount of charge burst attenuation is now de-
termined by gm of transistors M3 and M4 . This parameter, and the output resistance of
these transistors control also the impedance boosting, and consequently the isolation of
the inner DAC nodes from the output signal. Since the current flowing through it is fixed,
the degree of freedom left is the ratio W3 /L = W4 /L. Although the cascoding effects of
the switches are diminished because they now operate in the linear region, the switch cas-
codes compensate for it [54,76]. This gives the final boosting of the total cell’s impedance
qualifying requirements for at least up to 400 MHz of signal frequency.
Attention has been paid to the relationship between the transistor dimensions, the
voltage requirements for proper switch operation, impedance, and added local timing
errors. Several size options were examined for M3 and M4 and their impact on SFDR was
simulated for several frequencies leading to a choice of 0.72/0.2 µ m.

The spikes at the common switch node

In theory, the voltage swing and the shape of the control signal transient are two separate
issues and one should be able to select these two separately from each other. In practice,
this is not really true because both are determined from the same circuit (the driver).
11.3 Switched-Current cell 173

The key property for the spike for NMOS switches is the crossing point level of the
complementary control signals generated by the driver. The larger this level is, the less
time both switches stop conducting simultaneously, thus the less the discharging of the
capacitance present at the switch common source node X. There are three methods to
raise the crossing point, which are shown in fig. 11.7:
1. the first method is to delay one of the two complementary switch control signals
[71, 76] shown in fig. 11.7(a);
2. the second method is to modify the rise or fall time of one of the two complementary
signals [65, 66, 172] as depicted in fig. 11.7(b);
3. the third method in fig. 11.7(c) raises the crossing point of the drive signals by
reducing the voltage swing of the control signals [51].

VD VD VD

VX VX VX

VD VD VD

(a) (b) (c)

Figure 11.7 High crossing points realized with (a) time delay, (b) rise/fall asym-
metry, and (c) low swing.

The first two methods have the disadvantage that the (differential) symmetry of the con-
trol signals must be changed, either by introducing voluntarily skew between the control
signals (first method), or modifying the width and length of the drivers (second method)
to cause voluntarily rise/fall time differences. Because these methods are implemented
with CMOS based logic, the swing that is determined by the ground and power supply
levels can not be reduced significantly otherwise the proper operation of the driver is en-
dangered. The full symmetry and the inherent low swing operation of the third method
(600mV ) due to its association with CML are the key advantages used in this design.

Timing errors
The switch design was made based on the theory given in chapter 9 aided with transistor
level simulations. The mismatch models for the simulations are based on the MOS Model-
11 by Philips. The switch size is the central point of the design-for-timing strategy for
random timing errors. Since the capacitive loading of the switch gate has a stronger
contribution to timing errors than switch mismatch, the smaller the switch transistors are
(smaller area, thus gate capacitance), the smaller the timing errors will be for all circuits
preceding the switches (chain effect) given a fixed power budget.
174 Chapter 11 Design of a 12 bit 500 Msample/s DAC

With a goal to have a total spread in the timing of the latch-driver-switch chains be-
low 3 psec the current switches should have a spread of less than σ = 1 psec. Since
the signal distortion due to local timing errors is dominated by the thermometer cells,
the thermometer switch size was optimized first, and then their size was scaled down to
the binary bits. The dimensions found could not be scaled down by a factor more than
16 (4 bits) otherwise the minimum allowed width of the process is reached. Therefore,
the first three LSB’s (1, 2, 4 current weights) were assigned the same switch dimensions.
From simulations it was determined that the small systematic timing error that is gener-
ated when all cells (thermometer and binary) are driven by the same drivers can be safely
neglected. The thermometer switches W /L ratios are 16 · 0.46/0.2, therefore the down-
scaling to the LSB’s is {8, 4, 2, 1, 1, 1}. If the binary weighting of the switches had to be
followed strictly for all, then the total capacitance of the thermometer cells would have
been roughly 3 times larger.

MSB/LSB switch design

A systematic timing error between thermometer and binary weighted currents is created if
the same drivers are used to drive all switches because the binary scaled switches have less
capacitance than the thermometer ones. This is particularly important for the most signif-
icant binary bits. To match the loads at the driver-switch nodes it is usually accustomed
to add inactive gate-capacitance (drain-source short circuited transistors [39].
However, inactive capacitance behaves differently than the active switch capacitance.
An active switch loads the driver with a non-linear capacitance due to channel formation
which causes abrupt deceleration in the switch rising transients the moment the switch
turns on. On the other hand, inactive gate capacitance is a linear capacitor, its capacitance
does not change as the driving signal rises or falls. Therefore, a thermometer switch has
much different behavior around the switching on/off voltage level than the combination
of a binary switch with inactive gate capacitance. In this design matching is realized not
only in capacitance loading, but in the actual dynamics involved in the transition as well.
By using replica switched current cells that dump their currents in the supply as in fig.
11.8 all driver-switch nodes for all bits have exactly the same dynamic transient behavior.

11.4 Decoder, data synchronization and conditioning

In this section the circuit design of the binary to thermometer decoder, the delay equalizer,
the MS latches and the clock buffer is described.

11.4.1 Binary-to-Thermometer decoder

The decoder is shown in fig. 11.1. It receives off-chip binary data after internal buffer-
ing with (differential) buffers and generates the thermometer data applied to the master
11.4 Decoder, data synchronization and conditioning 175

Thermometer cell Binary cell Replica

Vdd Vdd Vdd 1/2 1/2 1/2 1/2

1 1

global 1 1 1/2 1/2 1/2 1/2

Mlb3
Vx
local local 1/2
1 1/2

V1 1 V1 1/2 V1 1/2

Vss Vss Vss

(a) (b)

Figure 11.8 Thermometer and binary SI cell. Numbers indicate W scaling.

latches. To ensure proper reception of high speed data from off-chip sources, buffers
employing Low Voltage Differential Signaling (LVDS) has been used [173].
The digital functionality of the decoder can be easily guaranteed even at very high
frequencies. However, because it interfaces directly to sensitive analog circuits, it can
spoil the quality of the DAC output signals much earlier than its operational limits are
reached. It can affect the DAC output signal via two paths: first, via the normal signal path
(e.g. when data are contaminated with artifacts, skew, logic glitches, etc.), and second
via indirect paths such as the supplies and the substrate. Consequently, low supply and
substrate disturbances at high speeds and good signal integrity are important requirements
next to low power consumption and small area. The 6 bit full custom made decoder was
addressed as a digital circuit with analog signal requirements. Because the off-chip data
are not re-sampled on-chip, data skew from PCB, cables, and on-chip interconnect was
expected to reduce the maximum conversion rate.

11.4.2 Delay equalization

The asynchronous data decoding operation unavoidably introduces a delay. To equalize
the delay of the 6 non decoded binary bits (the LSB’s) a series of CML inverters were
added per binary bit channel. In this way, the correct data waveforms arrive at the inputs
of the master latches. The 6 chains of inverters are all placed in one block, the delay
equalizer that is shown in fig. 11.1 next to the decoder.

11.4.3 Master-slave latches and drivers

The operation of the decoder is subject to many circuit imperfections that cause data skew,
waveform shape variations and logic glitches on its output data waveforms. Latches and
176 Chapter 11 Design of a 12 bit 500 Msample/s DAC

drivers are the interfaces that translate data values embodied in these widely different
waveforms with timing skew up to a few hundreds psec’s to data embodied in clear, iden-
tical and very accurately synchronized waveforms in the order of one psec.
Recent high-speed CMOS DACs [8, 39, 43, 54, 66, 67] use a single latch configuration
based on the cross-coupled CMOS inverter latch that was discussed in chapter 9. CMOS
inverters are used as drivers for the switches. The use of only one latch proves to be
very difficult to achieve properly the mentioned translation without many compromises
and tradeoffs. Additionaly, in chapter 9 it was also shown that the cross-coupled CMOS
inverter latch has several origins of local timing errors as well. It also causes major supply
and substrate disturbances, and it is very susceptible to them. This last issue demands
extra techniques to keep it from limiting performance [43, 67]. These have their own
extra cost in local timing errors and power consumption.

Master latch & driver Slave latch & driver

coarse signal conditioning fine signal conditioning

Vddd,Vssd Vddd,Vssd Vdda,Vssa Vdda,Vssa

digital D Q D Q
to current
data Am As
Db Qb Db Qb switches

clk clkb clkb clk

Figure 11.9 Master-slave latch and data drivers block diagram.

In this design, a CML master-slave (MS) latch configuration with drivers based on
that of fig. 11.9 was used for its low swing differential operation, low power supply dis-
turbance, and low power consumption at high frequencies. This topology proves capable
of low local timing errors as well. This combination is traditionally used for high speed
DACs realized in non CMOS technologies [35–37, 50, 57, 59, 60] technologies (Emitter
Coupled Logic (ECL) latches in bipolar, or their MOS equivalent in CML).
The master latch receives the digital data from the decoder and removes data-dependent
effects. Good quality waveforms are subsequently passed to the slave latch at the next
clock phase. Matching of the master latch is not very important, and neither the steepness
of its outputs needs to be higher than that required to drive the latch at the specified sam-
pling rate. The slave latch attenuates any remaining data-dependent effects, it provides
very precise timing, very steep edges, and identical swing. The switch driver filters clock
related switching artifacts, it establishes the correct swing for the switches, and it gives
extra boosting on the slopes of the control signals. Thanks to the use of differential signals
and multiple power supplies, any global errors related to power supply disturbances are
gradually reduced as the data are passed from the master latches powered from the digital
supply toward the SI cells powered by the analog supply.
The circuit schematic of the master-slave latches and drivers is shown in fig. 11.10.
Latch and driver address separately the actions of sampling and waveform conditioning.
11.4 Decoder, data synchronization and conditioning 177

Vddd Vdda

Vm2

P Pb Vddd R Vdda
Rb
Q
D Db Qb
Vm2
Z Zb
Q Qb
R Rb
CLKb CLK P Pb CLK CLKb

200 µΑ Vd 250 µΑ
Vm1 50 µΑ Vm1 50 µΑ Vs

Vssa
Vssd Vssd Vssa

master latch driver slave latch (switch) driver

Figure 11.10 Master-slave latch and data drivers circuit schematic.

In section 9.1.2 it was explained that because a CML latch implements voltage amplifica-
tion without operation of the positive feedback loop all topological issues of the elements
preceding the latch are completely removed, hence timing errors are created only locally
by the clock switches, and by mismatch in resistance and capacitance values. In this de-
sign, the master latches removes artifacts and time skew from the decoded data, and in the
presence of mismatch they provide relative timing accuracy (spread) less than 10 psec.
The slave latches have been specifically designed to extend this precision to less that
1 psec when driven with a steep clock signal, and create steep output edges to reduce the
impact of mismatch of the following driver.
The loads of the slave latches and drivers have to be very well matched with each
other. If the resistance values change significantly at each different slave latch, according
to the analysis in chapter 9 this translates to local timing errors. The same applies for the
resistances of the drivers. If the swing of the drivers varies significantly, then in additional
local errors are created because the SI cell switches are partially on/off in a spatial manner.
Diffusion resistors were used at the slave latches for their good matching quality.
The total current drawn by a MS latch and driver chain is 550µ A. As it can be seen,
only the slave latch and the switch driver call for large current and associated power
consumption.

11.4.4 Clock buffer

A clock buffer based on two gain stages has been design to buffer a low swing differential
input sinusoidal clock to a steep pulse that can drive the master and slave latches. At
nominal biasing conditions the buffer provides a rectangular signal with very steep edges
and a swing of 0.7 V at a total of 1 pF (interconnect and active). The choice of a low
swing differential sinusoidal clock reference has been preferred for its advantages for low
interference. The first stage receives the off-chip clock reference provides higher gain
and lower bandwidth. The second amplifier offers lower gain at a higher bandwidth, and
its output drive directly the clock interconnect network that leads the master and slave
178 Chapter 11 Design of a 12 bit 500 Msample/s DAC

Figure 11.11 Die photograph.

latches. Each stage is a simple differential pair with resistive loading. The total current
drawn from the clock buffer is 31 mA independent of frequency.

11.5 Layout
Layout design plays a crucial role in the performance of the converter. A lot of attention
has been paid in realizing a well-structured layout. All circuits layouts have been made
manually, and many circuits have been extracted and back-annotated for simulations. The
main aspects of the layout will be described here.
The layout can be seen in fig. 11.11. On the right side of the figure the arrays of
the input buffers, the decoder, the MSB/LSB delay equalizer and the master latches are
located (region A). The slave latches, drivers, cascoded switches, and the current source
cascodes are located in region B. Left of region B are the Vdda/Vssa rails and their de-
coupling, the local cascode biasing circuits, the output interconnects, and other biasing
wires (region C). The foremost left part of the figure shows the current source array and
its biasing circuit (region D). The clock buffer is located at the top of region B.
Data flow from the right to the left of the picture. The differential clock network splits
in two parts for slave and master latches, respectively. A combination of a primary and
secondary binary trees connected with a rail to average errors is used for the slave clock.
The output currents are summed with binary trees and a rail. Cross coupling between
11.5 Layout 179

data, clock, output and biasing signals was almost completely avoided without significant
cost of interconnect capacitances, especially for the clock node. This translates to steeper
clock signal slopes for a fixed clock driving current.

mirror y−axis
map mirrored map
23 57 1 46 5 52 35 41 41 35 52 5 46 1 57 23
55 0 59 10 7 43 40 31 31 40 43 7 10 59 0 55
26 9 19 61 12 51 34 3 3 34 51 12 61 19 9 26
43 22 36 30 26 44 21 42 42 21 44 26 30 36 22 43
48 54 32 13 27 15 50 29 29 50 15 27 13 32 54 48
56 14 38 33 6 60 16 20 20 16 60 6 33 38 14 56
mirror x−axis

58 4 45 2 D 17 62 11 11 62 17 D 2 45 4 58
8 37 47 18 24 39 28 49 49 28 39 24 18 47 37 8

8 37 47 18 24 39 28 49 49 28 39 24 18 47 37 8
58 4 45 2 D 17 62 11 11 62 17 D 2 45 4 58
56 14 38 33 6 60 16 20 20 16 60 6 33 38 14 56
58 54 32 13 27 15 50 29 29 50 15 27 13 32 54 58
43 22 36 30 26 44 21 42 42 21 44 26 30 36 22 43
25 9 19 61 12 51 34 3 3 34 51 12 61 19 9 25
55 0 59 10 7 53 40 31 31 40 53 7 10 59 0 55
23 57 1 46 5 52 35 41 41 35 52 5 46 1 57 23
mirrored map mirrored map

Figure 11.12 The 6 bit map used and its geometrical transformations.

A significant portion of the total IC area is occupied by the current sources. The large
size of their transistors reduces random local errors but makes deterministic ones (e.g.
gradients) dominant. This requires special techniques to reduce them to the 12 bit level.
In the absence of calibration, the usual way to deal with deterministic errors is with the
combination of a switching sequence1 , partitioning of the thermometer current sources in
subunits, and separate biasing for each group of subunits.
Typical examples of a-priori error information based maps were given in section
10.3.2. Examples in [41], [163] show that computer optimized mapping search engines
can lessen the accumulation of deterministic amplitude errors for a core DAC much better
than the classic maps based on symmetry [38, 63]. Moreover, their use might alleviate the
needs for partitioning, thus reducing interconnect length and complexity significantly.
In this design, the mapping computation algorithm developed in [162, 163] was used.
This algorithm is able to cope with the complexity of multi-dimensional mapping us-
ing many different sources of a-priori and a-posteriori sources of information, or other
constrains. The required maps was extracted after feeding the algorithm with spatial er-
ror information of the normalized gradients, and with the further condition that the INL
1A switching sequence is a map that deals with a-priori known planar or parabolic current errors.
180 Chapter 11 Design of a 12 bit 500 Msample/s DAC

should be minimized in two perpendicular directions of the error plane. In this way, the
INL is invariant to the angle of the gradient. Other cost functions can be used as well.
Figure 11.12 shows the 6 bit map used and the way the current sources were con-
nected. The subunit transistors were layouted first in an array and then rows and columns
of dummy subunits were added in the periphery to provide identical surroundings for all
transistors. Each subunit transistor is a folded structure to reduce drain capacitance and to
facilitate the scaling to the binary transistors. Locally placed substrate contacts tie it very
well to the local ground to avoid any bulk-source modulation. The total array was split in
four segments, or subarrays each one receiving separate biasing voltages. A thermometer
current source consists of a quartet of these subunits there for an interconnect matrix is
required to connect them together. Using geometrical transformation of the same map in
each subarray, all quartets have a common centroid in the middle (see fig. 11.12).
The row of dummy transistors next to the left side of each subarray is reserved for the
local biasing transistors. The bottom side has also extra transistors that realize the global
NMOS current mirror of the biasing circuit. Any other remaining dummies are used as
decoupling capacitors. The ground wires are carefully designed to avoid different IR
drops per source using vertical (outside the array) and horizontal trees (inside the array).
The analog power and ground supplies are sandwiched for extra decoupling capacitance.

11.6 Experimental results

The DAC has been implemented in a 0.18 µ m moderate Ohmic single-poly five metal
CMOS process from Philips, and packaged in an LQFP 80 pin package. In this section
the DC and AC linearity measurements of the DAC are presented, its main limitations are
discussed, and a comparison is made with existing DACs from literature.

11.6.1 DC linearity measurements

The DC linearity measurements of the DAC were made using a ramp input signal and
recording the output current. The measured currents are then used to evaluate the INL
and the DNL of the converter. To reduce the impact of noise from the measurement set
up, each output current that corresponds to an input code was measured 10 times, and
then the average was used in the INL and DNL evaluation.
The INL and DNL plots as a function of the input code of a representative sample
IC are given in fig. 11.13. The INL of the DAC is at the 11b level. All chips examined
were limited to the 11b level. Measurements of several IC’s indicate that the DC accuracy
is limited by random local amplitude errors. The DNL is shown in fig. 11.13(a). Some
outlier errors around the code 2500 limit the otherwise 13 bit accuracy for this specific IC
to the 12 bit level.
11.6 Experimental results 181

Figure 11.13 Representative INL of the DAC.

11.6.2 AC linearity measurements

AC measurements have been performed connecting the output of the DAC to a trans-
former that translates the differential output signal to a single ended one. This is inter-
faced to the spectrum analyzed with a double terminated 50 Ω cable. The Printed Circuit
Board (PCB) played an important role on the quality of the measurements but its details
are omitted. The measurements were made with a 15 mA current amplitude. Spurious
Free Dynamic Range (SFDR) was used to evaluate high frequency linearity.
At the bottom of fig. 11.14 the SFDR is shown as a function of the input signal
frequency, and at the top of the same figure as a function of the normalized frequency
f / fs , both for sampling rates fs in the range 300 to 500 Msample/s. 500 Msample/s
was the maximum rate for which the specification range given in table 11.1 was reached.
Generally, an SFDR between 60 and 80 dB is achieved for all signals from DC to 250 MHz.
The radical drop of the SFDR observed in other 12 bit DAC [54, 66, 67] is not a charac-
teristic to find in this DAC.
Low frequency measurements indicate an SFDR between 78 − 80 dB. In this region it
is mainly the amplitude errors determining the performance. The fs region between 300 −
400 Msample/s is most representative for the IC performance. For fs = 350 Msample/s
the SFDR stays 70 dB up to 122.5 MHz. Close to Nyquist frequencies 70 dB at fs =
200 Msample/s can be seen, 66 dB at a rate of fs = 300 Msample/s, 65 dB at fs =
182 Chapter 11 Design of a 12 bit 500 Msample/s DAC

Figure 11.14 SFDR vs (normalized) input signal frequency.

350 Msample/s and 64 − 65 dB at fs = 400 Msample/s. For these rates, the SFDR drops
approximately with 10 dB/dec as a function of signal frequency. The SFDR curves drop
in the 300 − 400 Msample/s region in accordance to the behavior of spatially local timing
errors. For example, at the 350 → 400 Msample/s transition, theory describes a drop of
400/350 = 1.143, i.e. 20 log(1.143) = 1.16 dB, since the distortion power is proportional
to the product of the signal and sampling rate frequencies. At the 350 → 400 Msample/s
transition of the SFDR, a similar drop may be observed. Similar behavior was found in
other IC’s, which indicates that it is the deterministic local errors that set the performance
(current summing network, clock network).
The region near 400 Msample/s is a major transition point for the dynamic behavior
of the DAC. The abrupt drop of the SFDR all over the spectrum beyond this region in
combination with the notable stability of the SFDR for fs = 500 Msample/s (even at
600 Msample/s the SFDR is similarly constant but lower) is indicative of the transition
of the error mechanisms that dominate the linearity.
Comments of this unconventional behavior can be made with the aid of top subfigure
of fig. 11.14. Initially, the SFDR for 500 Msample/s drops with 20 dB/dec from DC
to roughly f / fs = 0.25 (125 MHz) Had it been the case of local timing errors, then in
addition to the 10 dB/dec reduction, the SFDR drop with fs should be in the order of
500/400 = 1.25, i.e. 20 log(1.25) ≈ 2 dB. If the global error mechanisms studied so far
11.6 Experimental results 183

were responsible for this drop, according to our analysis they should be visible already at
lower rates because none can scale so abruptly with a factor 1.25 increase of fs . More-
over, it should continue to degrade the performance beyond f / fs = 0.25, which does
not happen. It was concluded that this limitation is caused by improper data sampling
of the decoded signals by the master latches due to speed limitations. The decoder fails
completely at 600 MHz setting the operational limit of the DAC.
The SFDR peaks observed at f / fs = 0.25 for all sampling frequencies occur because
all harmonic distortion components fall either on the signal, at DC, at fs /2 and at multiples
of fs . This is a well known effect, but it is rarely mentioned in DAC literature. These
results demonstrate that interpolation between few points (e.g at DC, at fs /4 and at a
point close to the Nyquist frequency should be avoided.
The converter draws 120 mA from an 1.8 V supply independent of frequency, out of
which 24 mA are for the decoder, master latches and their biasing, 31 mA for the clock
driver, 15 mA are signal power, 10 mA for local biasing units, 6 mA for the local cascode
biasing and the current sources, and 34 mA for the slave latches, switch drivers and their
biasing. Most of the power is consumed in dealing with local random timing errors,
to isolate the biasing lines from switching interference, and to the clock buffer. The
limitations come from local deterministic timing errors that are not influence by power,
and by speed limitations of the decoder. The total area is 1.13 mm2 . The performance
summary and the die photograph are shown in table 11.3 and fig. 11.11, respectively.

Technology CMOS 0.18 µ m

Maximum conversion rate up to 600 MHz
Resolution 12 bits
INL/DNL ±1 LSB, ±0.6 LSB
SFDR low frequencies 78 − 80 dB
Nyquist, fs = 350 MHz 66 dB
Nyquist, fs = 400 MHz 65 dB
Nyquist, fs = 500 MHz 60 dB
Best SFDR 70 − 80 dB between 0 − 122.5 MHz
Power consumption 216 mW
Area 1.13 mm2

Table 11.3 Performance summary.

Finally, a comparison with other reported DACs is given in fig. 11.15. All DACs in
this figure are implemented in CMOS except from that in [59]. The DAC presented here
delivers comparable performance with the 16 bit DAC in [43] at approximately half the
area and power consumption. In [59] local resampling was used to eliminate global error
mechanisms (similarly to a Track and Hold but locally before each SI cell) and then a
large amount of power was spend to deal with local errors, which set the performance
limit. This performance is obtained at a total power of 6W and an area of 30 mm2 .
184 Chapter 11 Design of a 12 bit 500 Msample/s DAC

11.7 Conclusions
The design and measurement results of a 12 bit 500 Msample/s DAC were presented.
The design approach followed is the result of exploitation of the analysis presented in
the earlier parts of this book, and its proper matching with circuit synthesis. Some key
characteristics of the circuit design methods used are

the full differential logic and signaling method;

the extensive use of partitioning in the power supply network;

the optimum partitioning between thermometer and binary bits;

the significant attention given to both global and local timing error mechanisms;

the proper use of circuit techniques to decouple optimization tradeoffs due to inter-
dependences imposed by error mechanisms;

the novel a-priori mapping computation engine based on stochastic optimization;

the well structured and realized floorplan and layout.
As a result of the robust implementation no fast degradation of dynamic performance
was observed in the measurements as it is common in such kinds of DAC found in liter-
ature. The dynamic performance measurements compare with the state-of-the-art at high
frequency linearity, having a power consumption and silicon area comparable with other
12 bit DACs.
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 A

Output spectrum for timing errors

A.1 Power spectrum of y(t) for random timing errors

The power spectrum of y(t) from eq. (7.10) will be calculated. The assumptions made
are that the DAC input z(m) is a ergodic stationary random process, and the timing errors
a stationary random process. Then y(t) is cyclostationary.
Initially, the mean of the empirical autocorrelation R̂y (t,t + τ ) is evaluated. Then we
will obtain the mean of the empirical power spectrum E{Ŝy ( f )} with a Fourier trans-
form of R̂y (t,t + τ ), from which the averaged probabilistic power spectrum Sy ( f ) is
extracted since they are equal due to regularity [128]1 The probabilistic power spectrum
Sy ( f ) matches that of Sy ( f ) due to stationarity. We start with the evaluation of the
expected empirical autocorrelation E{R̂y (τ )}:

E{R̂y (τ )} =
1 D
E{ lim
D→∞ 2D ∑ ∑ z(m + q)z(m)δ (t + τ − (q + m)Ts − µm+q )δ (t − mTs − µm )dt}
−D q m

1 D
= E{ lim
D→∞ 2D −D m
∑ z2 (m)δ (t + τ − mTs − µm )δ (t − mTs − µm )dt}
1 D
+E{ lim
D→∞ 2D
∑ ∑ z(m + q)z(m)δ (t + τ − (q + m)Ts − µm+q )δ (t − mTs − µm )dt}
−D q=0 m

(A.1)
1 Regularity guarantees the existense of time average limits such as the empirical mean and autocorrelation.

It is less strong than ergodicity.

199
200 Appendix A Output spectrum for timing errors

Let the first and the second parts of the sum of eq. (A.1) be T1 and T2 , respectively.

Recall the definition of the expectation of a function F(x) is E{F(x)} = σ f (σ )F(σ )d σ
with f (σ ) being the pdf of the random variable x. In our case f (σ ) is the probability den-
sity function of the time-jitter µm .
The term T1 is changed to

1 (N+ 21 )Ts
T1 = E{ lim
N →∞ (2N + 1)Ts −(N+ 21 )Ts m
∑ z(m)2 δ (t + τ − mTs − µm )δ (t − mTs − µm )dt}
(A.2)
Since µm are in the neighborhood of mTs , we may rewrite (A.2) as

1 N ∞
T1 = lim ∑
N →∞ (2N + 1)Ts m=−N
Rz (0)
−∞
E{δ (t + τ − mTs − µm )δ (t − mTs − µm )}dt

1
= Rz (0)δ (τ )
Ts
(A.3)
The term T2 is written as
1 1
T2 = E{ lim ·
Ts N →∞ 2N + 1
(N+ 21 )Ts
∑ ∑ z(m + q)z(m)δ (t + τ − (q + m)Ts − µm+q )δ (t − mTs − µm )dt}
−(N+ 21 )Ts q=0 m
(A.4)
N
1 1
= E{ lim ∑ ∑
Ts N →∞ 2N + 1 q=0 m=−N
z(m + q)z(m)
∞
δ (t + τ − qTs − mTs − µm+q )δ (t − mTs − µm )dt}
−∞

and if we use
∞
Im+q,m (τ ) = δ (t + τ − qTs − mTs − µm+q )δ (t − mTs − µm )dt (A.5)
−∞

we transform T2 to
N
1 1
T2 = lim ∑ ∑
Ts N →∞ 2N + 1 q=0 m=−N
E{z(m + q)z(m)}E{Im+q,m (τ )} (A.6)

Next, we use the joint PDF cn−m (tn ,tm ) of the jitter to write kq (τ ) = E{Im+q,m (τ )} as
+∞
kq (τ ) = δ (t + τ − (q + m)Ts − µm+q )δ (t − mTs − µm )cq (µm+q , µm ) d µm+q d µm dt
−∞
(A.7)
A.1 Power spectrum of y(t) for random timing errors 201

and finally
∞
kq (τ ) = cq (t + τ − qTs ,t)dt (A.8)
−∞

The time averaged probabilistic autocorrelation is obtained combining the equations

(A.8) (A.4) and (A.6) into
1 1
E{R̂y (τ )} = Rz (0)δ (τ ) + ∑ Rz (q)kq (τ ) (A.9)
Ts Ts q=0

The function Rz (q) = E{z(m + q)z(m)} represents the probabilistic autocorrelation of the
stationary input signal z(m), and Rz (0) is its power.
The next step is to use eq. (A.9) and with a Fourier transformation to obtain the
power spectrum of the process y(t). The difficulty is posed by the transformation of
kq (τ ), defined as Kq ( f ). Therefore, we define the double Fourier integral of the jitter
Mk−l ( fk , fl ) for k = l
∞ ∞
pi( fk µk + fl µl )
Mk−l ( fk , fl ) = fk−l (µk , µl )e− j2 (A.10)
−∞ −∞

Observe that Mk−l ( fk , fl ) is related to the characteristic function

Ck−l ( fk , fl ) = E{e− j2π ( fk µk + fl µl ) }
Because the timing error process is assumed stationary the characteristic function
Cm,n ( f , − f ) depends only on the difference k − l = q, hence
C0 ( f ) = 1 (A.11)
|Cq ( f )| ≤ 1 (A.12)
Then it is easy to show that for q = 0
Kq ( f ) = e− j2π f qTs Mq ( f , − f ) = e− j2π f qTs = E{e− j2π f (µm+q +µm ) } = e− j2π f qTs Cq ( f , − f )
(A.13)
The Fourier transformation of eq. (A.4) with the use of eq. (A.10) gives
1
Ts ∑
Sy ( f ) = Rz (q)Cq ( f , − f )e− j2π q f Ts (A.14)
q

Eq. (A.14) gives us the power spectrum of the impulse position modulated waveform
that is subject to stationary timing uncertainties with for general statistical properties and
correlation.
The analysis when z(m) is deterministic is very similar. In place of the probabilistic
autocorrelation function Rz (q) of the stationary signal z(m) the empirical autocorrelation
R̂z (q) is used. This follows directly from eq. (A.2) and (A.4) where the factors T1 and T2
are calculated. Indeed, if z(m) is not a random process, the expectation in eq. does not
apply to the factors z2 (m) and z(m + q)(z(m), which subsequently are combined with the
discrete average operant  = 2N+1 1
∑m=−N to form R̂z (0) and R̂z (q), respectively.
N
202 Appendix A Output spectrum for timing errors

A.2 Spectrum of y(t) for deterministic timing errors

The general magnitude spectrum will be calculated in this section. The following two
properties of the Bessel function of the first kind are used for the calculations:

eM sin θ = ∑ Jk (M)e jkθ (A.15)

k
J−k (x) = (−1)k Jk (x) (A.16)
(A.17)

The time modulated signal z(t − µ (t)) is calculated first. Using the definition of the Bessel
function, it is found that
 
P
z(t − µ (t)) = (−1) ∑ ∑ A p Jq (ω p M)e j(ω p +qωµ )t
p=1 q
(A.18)
P
= (−1) ∑ ∑ B p,q (ω p M) cos((ω p + qωµ )t)
p=1 q

where B p,q (ω p M) = A p Jq (ω p M).

Next we calculate in the same way the factor

1 (−1)
Ts ∑ ∑ ∑ Jr (mωs M)e j(mωs +rωµ )t
e jmωs (t −µ (t)) = (A.19)
m Ts m r

The combination of eq. (A.18) and (A.19) gives

P
1
y(t) =
Ts ∑ ∑ cos((ω p + qωµ )t)B p,q (ω p M)Jr (mωs M)e j(mωs +rωµ )t (A.20)
p=1 q,m,r

where we have used Γ p,q,r (ω p M, mωs M) = B p,q (ω p M)Jr (mωs M).

Applying a Fourier transformation in y(t) leads to

1 P
Γ p,q,r (ω p M, mωs M)  
Y(f) =
Ts ∑ ∑ 2
δ f − m fs − r f µ ± ( f p + q f µ ) (A.21)
p=1 q,m,r

We define fA (p, q) = f p + q f µ and fB (m, r) = m fs + r f µ , and we evaluate the magnitude

spectrum |Y ( f )|

1 P
|Γ p,q,r (ω p M, mωs M)|
|Y ( f )| =
Ts ∑ ∑ 2
[δ ( f − fB (m, r) ± fA (p, q))] (A.22)
p=1 q,m,r
 B

Literature data

203
204 Appendix B Literature data