Microelectronic

Circuits
Differential Amplifier
BITS Pilani Anu Gupta
Pilani Campus
 BITS Pilani
Pilani Campus

Differential Amplifier
Cascode amp with current bias---
capacitor???

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Remove capacitor, but no loss of
gain. How ???

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BJT Diff Amp.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Differential input no capacitor
reqd.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Single input to Differential input

converter circuit/s
Single input to Differential
input conversion

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Converting single input to
differential input

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Alternative simple method
Using a pair of OPAMP

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Alternative simple method
More error

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Diff. Amp. --- more than CSA

Diff. amplifier
Benefits
• Same input magnitude, full voltage gain, no capacitor
• Input noise immunity (common mode operation)
• Double voltage swing
• Less harmonic distortion
• Flexibility in choosing phase of output

Drawback
• Diff. input required
• Double the no. of component
• Double power consumption ( not necessarily???)

BITS Pilani, Pilani Campus

Input notation

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Differential amplifier—
Double output signal swing

Extra node available

Bits, pilani

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Output signal swing-- doubles

vo1
2.8v 1.2v 3v

Vcm=1.6v
0.4v
vo2
vcm

1.2v

Vo1-vo2
2.4 v

Assume all overdrive 0.2v

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Differential amplifier---
2 Modes of operation

• Differential mode operation---gain

• Common mode operation– Noise immunity

𝒗𝟏 + 𝒗𝟐
𝒗𝒐𝒖𝒕 = 𝑨𝒅𝒎 𝒗𝟏 − 𝒗𝟐 + 𝑨𝒄𝒎
𝟐

BITS Pilani, Pilani Campus

 Diff operation—
No Even-Order Harmonic Distortion
• Expanding the transfer functions of circuits into a power series is a typical
way to quantify the distortion products.
• Taking a generic expansion of the outputs and assuming matched
amplifiers, we get:
Vout - = f(vin) = k1Vin + k2Vin2 + k3Vin3 + . . . , and
Vout+ = f(-vin) = k1(–Vin)+ k2(–Vin)2 + k3(–Vin)3 + . . . .

• Taking the differential output

Vod = 2k1Vin + 2k3Vin3 + . . . ,
where k1, k2 and k3 are constants.
• The quadratic terms gives rise to second-order harmonic distortion, the
cubic terms gives rise to third-order harmonic distortion, and so on.
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Diff amp
CSA-CSA coupled at source

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Diff amp.---
CSA, CDA-CGA in cascade

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Understanding of Diff Amp.—

• DC Bias,
• AC operation- Adm, Acm
• Large signal characteristics,
 BITS Pilani
Pilani Campus

DC Bias
 BITS Pilani
Pilani Campus

DC bias----
Differential Power Supply
Single Power Supply
Dual Power Supply
DC Bias

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Single Power Supply
DC Bias

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Operation of Differential
amplifier
• DC
 Large signal characteristics
 OCMR/ ICMR

• AC
 Adm, Acm
 Output signal swing
 Rin, Rout
 Range of differential operation

BITS Pilani, Pilani Campus

 BITS Pilani
Pilani Campus

DC
Large signal Characteristics
Extreme voltage/ current limits
for proper operation
• Common Mode characteristics----OCMR, ICMR

• Differential Mode characteristics

Single/ Diff vout vs. Diff. vin

Single/ Diff Iout vs. Diff. Vin

Gm diff . vs. diff vin

Single vout vs. single vin

Single Iout vs. single vin

BITS Pilani, Pilani Campus

 BITS Pilani
Pilani Campus

ICMR, OCMR
ICMR, OCMR

Input Common Mode Range

Range of possible common mode (DC) voltages at input

terminal

Output Common Mode Range

Range of possible DC voltages at output terminal

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Difference in OCMR, and
Output signal swing
• Are these same??---- NO

• OCMR (DC voltages) , common mode voltage

• Output signal swing (AC peak voltages), common/ differential

mode voltage

• Total Vout = DC Voltage + AC peak voltage

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Ex1--- ICMR, OCMR, O/P swing

ICMR

OCMR

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Ex2---- OCMR, Output signal swing

They may be same, may not be same

OCMR

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Ex3– Identical OCMR, O/ P signal
swing

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Ex4– Different OCMR, O/ P signal
swing

𝑶𝑪𝑴𝑹 → 𝑽𝑫𝑫 − |𝑽𝑮𝑺𝟑 |

Fixed value

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Example

𝑽𝑫𝑫 = 𝟒𝑽, |𝑽𝑮𝑺𝟑 | = 𝟏. 𝟓𝑽, 𝑽𝑻 = 𝟏𝑽,

𝑽𝑶𝑽 = 𝟎. 𝟓𝑽

𝑶𝑪𝑴𝑹 → 𝑽𝑫𝑫 − |𝑽𝑮𝑺𝟑 |

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Ex-- PMOS DIFF. AMP

Output signal swing—

2 [(Vdd – Vov3- Vov2 to Vov3 ]

vout

ICMR
Input common mode range-
[Vdd – Vov3 - Vsg2] to [Vov2 + Vov4- Vsg2]
;Vov2=|Vsg2|- |Vtp2|
Output common mode range–
[(Vdd – Vov5- Vov2 to Vov3 ] range here
 Ex- 5

Input common mode

range-
[(Vdd – Vov3) + Vgs1] to
[Vgs1 + Vov5]

Output common mode range–

[(Vdd – Vov4 to
Vov5 + Vov1 ] range here
 Ex- 6

Input common mode range-

[(Vdd – Vov3) + Vgs1] to
[Vgs1 + Vov5]

Output common mode range–

[(Vdd – Vov3 + IR ] to
Vov5 + Vov1 ] range here

Output signal swing range–

[(Vdd – Vov3 to Vov5 + Vov1 ]
Extreme voltage/ current limits
for proper operation
1) Differential characteristics
Single/ Diff vout vs. Diff. vin

Single/ Diff Iout vs. Diff. Vin

Gm diff . vs. diff vin (transfer characteristic)

Single vout vs. single vin

Single Iout vs. single vin

BITS Pilani, Pilani Campus

Large signal Characteristics-

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Large signal Characteristics-

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Large Signal analysis--- 𝟏
𝒈𝒎𝟏,𝒅𝒊𝒇𝒇 = 𝒈𝒎𝟏
Transfer Characteristics 𝟐

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Vid (max)—
Range of differential mode operation

Transistor remain in active/ saturation

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Range of Vid for Diff. Mode
Operation (MOSFET)

𝐼𝑆𝑆
𝐷𝑖𝑓𝑓. 𝑀𝑜𝑑𝑒 𝑜𝑝𝑒𝑟𝑎𝑡𝑖𝑜𝑛, 𝑉𝑜𝑣,𝑑𝑖𝑓𝑓 = 𝑉𝐺𝑆1 − 𝑉𝑇 =
𝑊
𝜇𝑁 𝐶𝑜𝑥
𝐿
M1 trans. Conducting Iss ,

2𝐼𝑆𝑆
𝑉𝑜𝑣,𝑆𝑙𝑒𝑤 = 𝑉𝐺𝑆1 − 𝑉𝑇 = 𝑊 = 2𝑉𝑜𝑣,𝑑𝑖𝑓𝑓 = 2 𝑉𝑜𝑣
𝜇𝑁 𝐶𝑜𝑥
𝐿

VIN1  VGS1  VP
VGS 2  VIN 2  VP  VT ; For  M 2  Cut  off
[VIN1  VIN 2 ]  (VGS1  VP )  (VT  VP )  VGS1  VT
 [VIN1  VIN 2 ]  2V0V
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Transfer characteristics
BJT Diff amp
𝑽𝜸 = 𝑽𝑩𝑬,𝒐𝒏 ⇒ 𝒄𝒖𝒕 𝒊𝒏 𝒗𝒐𝒍𝒕𝒂𝒈𝒆

𝑰𝑪
𝑽𝑩𝑬 (> 𝑽𝜸 ) = 𝑽𝒕𝒉𝒆𝒓𝒎𝒂𝒍 × 𝒍𝒏
𝑰𝒔

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Range of Vid for Diff. Mode
Operation (BJT)
𝐼𝑆𝑆
𝐷𝑖𝑓𝑓. 𝑀𝑜𝑑𝑒 𝑜𝑝𝑒𝑟𝑎𝑡𝑖𝑜𝑛, 𝑉𝐵𝐸,𝑑𝑖𝑓𝑓 = 𝑉𝑡ℎ𝑒𝑟𝑚𝑎𝑙 𝑙𝑛
2𝐼𝑆

Q1 trans. Conducting Iss current ,

𝐼𝑠𝑠 2𝐼𝑆𝑆
𝑉𝐵𝐸 ,𝑆𝑙𝑒𝑤 = 𝑉𝑡ℎ𝑒𝑟𝑚𝑎𝑙 𝑙𝑛 = 𝑉𝑡ℎ𝑒𝑟𝑚𝑎𝑙 𝑙𝑛
𝐼𝑆 2𝐼𝑆
𝐼𝑠𝑠
= 𝑉𝑡ℎ𝑒𝑟𝑚𝑎𝑙 𝑙𝑛2 + 𝑙𝑛
2𝐼𝑆
≈ 𝑉𝑡ℎ𝑒𝑟𝑚𝑎𝑙 𝑙𝑛 2 + 𝑉𝐵𝐸,𝑑𝑖𝑓𝑓

𝑉𝐵𝐸 ,𝑆𝑙𝑒𝑤 = 𝑉𝐵𝐸,𝑑𝑖𝑓𝑓 + 26𝑚𝑉 × 0.7

= 𝑉𝐵𝐸,𝑑𝑖𝑓𝑓 + 18.2𝑚𝑉
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Range of Vid for Diff. Mode
Operation (BJT) 𝑽𝜸 = 𝑽𝑩𝑬,𝒐𝒏

𝑰𝑺𝑺
𝑫𝒊𝒇𝒇. 𝑴𝒐𝒅𝒆 𝒐𝒑𝒆𝒓𝒂𝒕𝒊𝒐𝒏, 𝑽𝑩𝑬,𝒅𝒊𝒇𝒇 = 𝑽𝒕𝒉𝒆𝒓𝒎𝒂𝒍 𝒍𝒏
𝟐𝑰𝑺

𝑰𝑺𝑺 𝑰𝑺𝑺
In slew mode---𝑽𝑩𝑬,𝒔𝒍𝒆𝒘 = 𝑽𝒕𝒉𝒆𝒓𝒎𝒂𝒍 𝒍𝒏
𝑰𝑺
= 𝒍𝒏 𝟐𝑰𝑺
+ 𝒍𝒏 𝟐

𝑉𝐼𝑁1 = 𝑉𝐵𝐸,𝑠𝑙𝑒𝑤 + 𝑉𝑃 , 𝑉𝐼𝑁2 = 𝑉𝐵𝐸2 + 𝑉𝑝

𝑉𝐵𝐸2 = 𝑉𝐼𝑁2 − 𝑉𝑝 ≤ 𝑉𝛾 , 𝑀2 𝑖𝑛 𝑐𝑢𝑡 − 𝑜𝑓𝑓, slew mode

𝑉𝐼𝑁1 − 𝑉𝐼𝑁2 ≥ 𝑉𝐵𝐸,𝑠𝑙𝑒𝑤 + 𝑉𝑃 − 𝑉𝛾 + 𝑉𝑝 = 𝑉𝐵𝐸,𝑠𝑙𝑒𝑤 - 𝑉𝛾

𝑽𝒊𝒅 = 𝑽𝑰𝑵𝟏 − 𝑽𝑰𝑵𝟐 ≥ 𝑽𝑩𝑬,𝒅𝒊𝒇𝒇 + 𝟏𝟖. 𝟐𝒎𝑽 − (𝑽𝜸 )

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Behaviour of voltage at P node

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Behaviour of ID(M1) / Vp
difference/ slew mode

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Behaviour of P node
difference/ slew mode

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Large signal Characteristics-

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Large signal Characteristics-
Common Mode

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 BITS Pilani
Pilani Campus

Output voltage of Diff amp--

A combination of differential i/p, common
mode i/p , offset voltage
Output voltage of Diff amp--

A combination of of voltage due to

• differential i/p--- (desirable output)

• common mode i/p -- (noise- undesirable

output)

• offset voltage (due to mismatch)-- (undesirable

output)

𝒗𝒐𝒖𝒕(𝒕𝒐𝒕𝒂𝒍) = 𝑨𝒅𝒎 𝒗𝒊𝒅 + 𝑨𝒄𝒎 𝒗𝒊𝒄𝒎 + 𝑽𝒐𝒖𝒕,𝒐𝒇𝒇𝒔𝒆𝒕

BITS Pilani, Pilani Campus
How to find Adm, Acm,
Vout,offset??

Adm— small signal difference mode analysis

Acm—small signal difference mode analysis

Vout, offset--- DC mismatch analysis

𝒗𝒐𝒖𝒕(𝒕𝒐𝒕𝒂𝒍) = 𝑨𝒅𝒎 𝒗𝒊𝒅 + 𝑨𝒄𝒎 𝒗𝒊𝒄𝒎 + 𝑽𝒐𝒖𝒕,𝒐𝒇𝒇𝒔𝒆𝒕

BITS Pilani, Pilani Campus

Example-
𝒗𝒊𝒅 = ±𝟓 𝒎𝑽 𝒂𝒄
𝑨𝒅𝒎 = 𝟓𝟎
𝑨𝒄𝒎 = 𝟎. 𝟓; ----------------------(𝐴𝑐𝑚 ⇒0 for perfect matching)
𝒗𝒊𝒄𝒎 = 𝟓𝛍𝐕;−−−−−−−−− −(𝒓𝒎𝒔 𝒏𝒐𝒊𝒔𝒆 𝒔𝒊𝒈𝒏𝒂𝒍)
𝑽𝒐𝒖𝒕,𝒐𝒇𝒇𝒔𝒆𝒕 = ±𝟑𝒎𝑽; −−−− −𝑽𝒐𝒖𝒕,𝒐𝒇𝒇𝒔𝒆𝒕 ⇒ 0 for perfect matching)

𝒗𝒐𝒖𝒕(𝒕𝒐𝒕𝒂𝒍) = 𝑨𝒅𝒎 𝒗𝒊𝒅 + 𝑨𝒄𝒎 𝒗𝒊𝒄𝒎 + 𝑽𝒐𝒖𝒕,𝒐𝒇𝒇𝒔𝒆𝒕

𝒗𝒐𝒖𝒕(𝒕𝒐𝒕𝒂𝒍) = 𝟓𝟎 × 𝟏𝟎𝒎𝑽 ± 𝟎. 𝟓 × 𝟎. 𝟓𝒎𝑽 ± 𝟑𝒎𝑽
𝒗𝒐𝒖𝒕(𝒕𝒐𝒕𝒂𝒍) = 𝟓𝟎𝟎𝒎𝑽 ± 𝟎. 𝟐𝟓𝐦𝐕 ± 𝟑𝒎𝑽
𝒗𝒐𝒖𝒕(𝒕𝒐𝒕𝒂𝒍) = 𝟓𝟎𝟎𝒎𝑽 ± 𝟑. 𝟐𝟓𝐦𝐕

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

How to find Adm, Acm, Vout,offset??

AC Operation:
1) Difference mode (Adm)
2) Common mode operation (Acm)
1) Difference mode- AC
operation

• Rin, Rout

• Adm

• Output Signal swing

• CMRR

BITS Pilani, Pilani Campus

AC Analysis using Half circuit
concept

Vin/2 Vin/2

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Notations, Diff. amp voltage gain—
Differential Mode

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Notations
Half circuit transconductance,
𝒊𝒐𝟏
𝒈𝒎𝟏 = 𝑮𝒎,𝑯𝑪 =
𝒗𝒊𝒏𝟏
Differential input, single ended output Transconductance---
𝒊𝒐𝟏,𝟐
𝑮𝒎𝟏,𝒗𝒊𝒅 = 𝑮𝒎,𝒗𝒊𝒅 =
𝒗𝒊𝒅
Differential input, Differential output Transconductance-
±(𝒊𝒐𝟏 − 𝒊𝒐𝟐 ) 𝒊𝒐𝒅
𝑮𝒎,𝒅𝒊𝒇𝒇 = =
𝒗𝒊𝒅 𝒗𝒊𝒅
Differential input, single ended output, output conductance---
𝒗 𝒗
𝑹𝒐𝒖𝒕,𝑯𝑪 = 𝒐𝟏 = 𝒐𝟐
𝒊𝒐𝟏 𝒊𝒐𝟐
Differential input, Differential output, output conductance- -
𝒗𝒐𝒅 𝟐𝒗𝒐𝟏
𝑹𝒐𝒖𝒕,𝒅𝒊𝒇𝒇 = =
𝒊𝒐𝒅 𝟐𝒊𝒐𝟏

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Rin/ Rout

Source degeneration is not required as Rin is

already high
BITS Pilani, Pilani Campus
R out = [vx/ ix ]
Half circuit
𝑣𝑥
𝑅𝑜,𝐻𝐶 =
𝑖𝑥
𝑣𝑥1
𝑅𝑜,𝑣𝑥1 = = 𝑅𝐷 ||𝑟𝑜
𝑖𝑥1

𝑣𝑥2 −𝑣𝑥1
𝑅𝑜,𝑣𝑥2 = = = 𝑅𝐷 ||𝑟𝑜
𝑖𝑥2 −𝑖𝑥1

𝑅𝑜𝑢𝑡 = 𝑅𝑜,𝑣𝑥1 + 𝑅𝑜,𝑣𝑥2

= 𝑅𝐷 ||𝑟𝑜 + 𝑅𝐷 ||𝑟𝑜

𝑹𝒐𝒖𝒕 = 𝑹𝑫 ||𝒓𝒐
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
R out – Vx/ Ix
𝒗𝒙
𝑹𝒐𝒖𝒕 =
𝒊𝒙

𝑹𝒐𝒖𝒕 = 𝟐 𝒓𝒐 ||𝑹𝑫

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

R out = [vx/ ix ]
using principle of superposition
𝑣𝑥
𝑅𝑜 =
𝑖𝑥
𝑣𝑥1
𝑅𝑜,𝑣𝑥1 = = 𝑅𝐷 ||𝑟𝑜
𝑖𝑥1

𝑣𝑥2 −𝑣𝑥1
𝑅𝑜,𝑣𝑥2 = = = 𝑅𝐷 ||𝑟𝑜
𝑖𝑥2 −𝑖𝑥1

𝑹𝒐𝒖𝒕,𝑯𝑪 = 𝑹𝑫 ||𝒓𝒐

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Observations

𝑅𝑜𝑢𝑡 = 𝟐𝑹𝒐𝒖𝒕,𝑯𝑪

𝑰𝒔 𝑹𝒐𝒖𝒕,𝒅𝒊𝒇𝒇 ≠ 𝑹𝒐𝒖𝒕 ??? NO

𝒗𝒐𝑫 𝒗𝒙𝒅 𝒗𝒙𝟏 − (−𝒗𝒙𝟐 )

𝑹𝒐𝒖𝒕,𝒅𝒊𝒇𝒇 = = =
𝒊𝒐𝒅 𝒊𝒙𝒅 𝒊𝒙𝟏 − −𝒊𝒙𝟐

𝒗𝒙
= = 𝒓𝒐 ||𝑹𝑫
𝟐𝒊𝒙𝟏
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
R out,diff, = [vod/ iod ]
using principle of superposition
𝑣𝑜𝑑 𝑣𝑜1 − 𝑣𝑜2
𝑅𝑜,𝑑𝑖𝑓𝑓 = =
𝑖𝑜𝑑 𝑖𝑜1 − 𝑖𝑜2
𝑣𝑜𝑑 𝑣𝑜1 − 𝑣𝑜2
𝑅𝑜,𝑑𝑖𝑓𝑓 = =
𝑖𝑜𝑑 𝑖𝑜1 − 𝑖𝑜2
𝑣𝑥1 −𝑣𝑥2 𝑣𝑥1 𝑣𝑥2
= = −
𝑖𝑥1 −𝑖𝑥2 𝑖𝑥1 −𝑖𝑥2 𝑖𝑥1 −𝑖𝑥2

𝑣𝑥1 𝑣𝑥2
𝑅𝑜,𝑑𝑖𝑓𝑓 = +
2𝑖𝑥1 2𝑖𝑥2
𝑣𝑥1 𝑣𝑥2
= 𝑅𝐷 ||𝑟𝑜 ; = 𝑅𝐷 ||𝑟𝑜
𝑖𝑥1 𝑖𝑥2
1 1
𝑅𝑜,𝑑𝑖𝑓𝑓 = 𝑅𝐷 ||𝑟𝑜 + 𝑅𝐷 ||𝑟𝑜
2 2
𝑖𝑥1 = −𝑖𝑥2 = 𝑖𝑥 𝑹𝒐,𝒅𝒊𝒇𝒇 = 𝑹𝑫 ||𝒓𝒐
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BJT diff. amp ---Rin/ Rout

𝑅𝑖𝑛 = 2𝑟𝜋
𝑹𝒐𝒖𝒕 = 𝟐 𝒓𝒐 ||𝑹𝒄

𝑹𝒐𝒖𝒕,𝒅𝒊𝒇𝒇 = 𝒓𝒐 ||𝑹𝒄
𝑅𝑖𝑛,𝑑𝑖𝑓𝑓 = 𝑟𝜋 ,
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Rin, of BJT
(Using principle of superposition)

𝑅𝑖𝑛,𝑑𝑖𝑓𝑓 = 𝑅𝑖𝑛1 + 𝑅𝑖𝑛2

𝑖𝑖𝑛1 = −𝑖𝑖𝑛2 = 𝑖𝑖𝑛

𝑣𝑖𝑑 𝑣𝑖𝑛1 −|𝑣𝑖𝑛2 | 1

𝑅𝑖𝑛,𝑑𝑖𝑓𝑓 = = − = 𝑟𝜋1 + 𝑟𝜋1
𝑖𝑖𝑑 2𝑖𝑖𝑛1 2𝑖𝑖𝑛2 2
𝑹𝒊𝒏,𝒅𝒊𝒇𝒇 = 𝒓𝝅𝟏
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 With Emitter degeneration resistor

High Rin with emitter degeneration

But gain reduces

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Difference mode– AC voltage gain

Input applied differentially

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Adm----Analysis using Half circuit

Vin/2 Vin/2

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Benefit of half circuit concept

• Half circuit analysis can give the full Adm value directly

----------------------------------------------
• Diff amp gain = CSA gain only if we use double 2 vin, 2
Iss

NOTE----
• Diff amp gain is half/ Less if vid = vin
• Diff amp gain is half/ less if total bias current = Iss
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Adm using (G m diff x R out,diff )
G m diff - principle of superposition

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(G m diff
-- principle of superposition

𝑖𝑜,𝑑𝑖𝑓𝑓 𝑖𝑜1 − 𝑖𝑜2 𝑖𝑜1 𝑖𝑜2

𝐺𝑚,𝑑𝑖𝑓𝑓 = = = −
𝑣𝑖𝑑 𝑣𝑖𝑑 𝑣𝑖𝑑 𝑣𝑖𝑑
𝑖𝑜1 𝑖𝑜2 𝑔𝑚1 𝑣𝑖𝑛1 −𝑔𝑚2 𝑣𝑖𝑛2
𝐺𝑚,𝑑𝑖𝑓𝑓 = − = −
2𝑣𝑖𝑛1 2𝑣𝑖𝑛2 𝑣𝑖𝑑 𝑣𝑖𝑑
𝟐𝒈𝒎𝟏 𝒗𝒊𝒏𝟏
𝑮𝒎,𝒅𝒊𝒇𝒇 = = 𝒈𝒎𝟏 = 𝒈𝒎
𝟐𝒗𝒊𝒏𝟏

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

R out,diff, = [vod/ iod ]
using principle of superposition
𝑣𝑜𝑑 𝑣𝑜1 − 𝑣𝑜2
𝑅𝑜,𝑑𝑖𝑓𝑓 = =
𝑖𝑜𝑑 𝑖𝑜1 − 𝑖𝑜2
𝑣𝑜𝑑 𝑣𝑜1 − 𝑣𝑜2
𝑅𝑜,𝑑𝑖𝑓𝑓 = =
𝑖𝑜𝑑 𝑖𝑜1 − 𝑖𝑜2
𝑣𝑥1 −𝑣𝑥2 𝑣𝑥1 𝑣𝑥2
= = −
𝑖𝑥1 −𝑖𝑥2 𝑖𝑥1 −𝑖𝑥2 𝑖𝑥1 −𝑖𝑥2

𝑣𝑥1 𝑣𝑥2
𝑅𝑜,𝑑𝑖𝑓𝑓 = +
2𝑖𝑥1 2𝑖𝑥2
𝑣𝑥1 𝑣𝑥2
= 𝑅𝐷 ||𝑟𝑜 ; = 𝑅𝐷 ||𝑟𝑜
𝑖𝑥1 𝑖𝑥2
1 1
𝑅𝑜,𝑑𝑖𝑓𝑓 = 𝑅𝐷 ||𝑟𝑜 + 𝑅𝐷 ||𝑟𝑜
𝑖𝑥1 = −𝑖𝑥2 = 𝑖𝑥 2 2
𝑹𝒐,𝒅𝒊𝒇𝒇 = 𝑹𝑫 ||𝒓𝒐
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Adm using
(G m diff x R out,diff )

𝑮𝒎,𝒅𝒊𝒇𝒇 = ∓𝒈𝒎𝟏,𝟐 = ∓𝒈𝒎

𝑨𝒅𝒎,𝒅𝒊𝒇𝒇 = ∓𝑮𝒎,𝒅𝒊𝒇𝒇 × 𝑹𝒐,𝒅𝒊𝒇𝒇

= ∓ 𝒈𝒎 𝑹𝑫 ||𝒓𝒐

BITS Pilani, Pilani Campus

 BITS Pilani
Pilani Campus

2) Acm-- Common Mode Gain–

using half circuit
AC common mode gain,
single ended output

Common
mode
Vod ≠ 0

for perfect
symmetry

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Common mode single ended gain
Half circuit concept

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

AC common mode gain,
differential output

Common
mode
differential
gain= 0

for perfect
symmetry

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Rin/ Rout– common mode gain
Single ended output

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Common mode—
Output signal swing

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Common mode (active load)—
Output signal swing

𝑽𝒐,𝒎𝒂𝒙 = 𝑽𝑫𝑫 − 𝑽𝒐𝒗

𝑽𝒐,𝒎𝒊𝒏 = 𝑽𝒐𝒗𝟏 + 𝑽𝒐𝒗,𝑰𝒔𝒔

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 BITS Pilani
Pilani Campus

Common Mode Rejection Ratio

CMRR
Common mode rejection ratio
CMRR
CMRR= |Adm/ Acm|; figure of merit

Ability to reject common signal

For diff output----

Acm=0;
CMRR→∞ ideal case

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Common mode rejection ratio
- single ended output
CMRR= |Adm| / |Acm|;

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 BITS Pilani
Pilani Campus

Gain Comparison---
CSA gain , Diff . amp gain
CSA gain

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Differential Amp.--- Half circuit

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Diff amp gain-- Differential Mode
contd.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Diff. amp gain-- using Gm, Rout

𝑑𝑖𝑓𝑓. 𝑎𝑚𝑝 𝑔𝑎𝑖𝑛, 𝑠𝑖𝑛𝑔𝑙𝑒 𝑜𝑢𝑡𝑝𝑢𝑡, 𝑑𝑖𝑓𝑓. 𝑖𝑛𝑝𝑢𝑡

𝑽𝒐𝟏 𝒊𝒐𝟏 𝑽𝒐𝟏

𝐴𝑑𝑚,𝑠𝑖𝑛𝑔𝑙𝑒 = = ×
𝑽𝒊𝒅 𝑽𝒊𝒅 𝒊𝒐𝟏
= 𝑮𝒎,𝒗𝒊𝒅 × 𝑹𝒐𝒖𝒕,𝑯𝑪

𝟏 𝟏
= - 𝒈𝒎𝟏 𝑹𝒅 = − 𝒈 (𝑅 ||𝑟 ) = −𝟓
𝟐 𝟐 𝒎𝟏 𝐷 𝑜

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Diff. amp gain-- Gm,diff, Rout,diff

𝑑𝑖𝑓𝑓. 𝑎𝑚𝑝 𝑔𝑎𝑖𝑛, 𝑑𝑖𝑓𝑓. 𝑜𝑢𝑡𝑝𝑢𝑡, 𝑑𝑖𝑓𝑓. 𝑖𝑛𝑝𝑢𝑡

𝑽𝒐𝒅 𝒊𝒐𝒅 𝑽𝒐𝒅 𝒊𝒐𝒅 𝟐𝑽𝒐𝟏
𝐴𝑑𝑚,𝑑𝑖𝑓𝑓 = = × = ×
𝑽𝒊𝒅 𝑽𝒊𝒅 𝒊𝒐𝒅 𝑽𝒊𝒅 𝟐𝒊𝒐𝟏

= 𝑮𝒎,𝒅𝒊𝒇𝒇 × 𝑹𝒐𝒖𝒕,𝒅𝒊𝒇𝒇 = 𝟐𝑮𝒎,𝒗𝒊𝒅 × 𝑹𝒐𝒖𝒕,𝑯𝑪

𝐴𝑑𝑚,𝑑𝑖𝑓𝑓 = 𝒈𝒎𝟏 𝑹𝒅 = 𝟏𝟎

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Diff. Amp voltage gain--
Common mode

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Diff. Amp voltage gain--
Common mode

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Summary

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Conclusion--

• Diff amp gain = CSA gain only if we use double resources i.e
----double input (vid = 2vin) and
-----double total bias current (2 Iss) , and
------2 matched arm.
• Half circuit analysis can give the full Adm value directly
----------------------------------------------------------------------
• NOTE----
• Diff amp gain is half/ Less if vid = vin
• Diff amp gain is half/ less if total bias current = Iss

BITS Pilani, Pilani Campus

PMOS input differential pair

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

3) How to find Vout, offset?

DC mismatch analysis
 BITS Pilani
Pilani Campus

Random/ Systematic offset

Mismatch-
Random/ Systematic

Random--- Due to process variation, during fabrication

of design on Silicon. Can not be corrected.

Systematic-- Due to design errors. Can be corrected

while designing.

Consequence---Vout,offset Voltage is generated

𝒗𝒐𝒖𝒕(𝒕𝒐𝒕𝒂𝒍) = 𝑨𝒅𝒎 𝒗𝒊𝒅 + 𝑨𝒄𝒎 𝒗𝒊𝒄𝒎 + 𝑽𝒐𝒖𝒕,𝒐𝒇𝒇𝒔𝒆𝒕

BITS Pilani, Pilani Campus
Mismatch- (in fully differential amp.)
Random/ Systematic

𝒗𝒐𝒖𝒕(𝒕𝒐𝒕𝒂𝒍) = 𝑨𝒅𝒎 𝒗𝒊𝒅 ± 𝑨𝒄𝒎 𝒗𝒊𝒄𝒎 ± 𝑽𝒐𝒖𝒕,𝒐𝒇𝒇𝒔𝒆𝒕

= 𝑨𝒅𝒎 𝒗𝒊𝒅 ± 𝑨𝒄𝒎−𝒅𝒎 𝒗𝒊𝒄𝒎 ± 𝑽𝒐𝒖𝒕,𝒐𝒇𝒇𝒔𝒆𝒕

Consequences---
• Vout,offset Voltage is generated
𝒗𝒙 −𝒗𝒚
• 𝑨𝒄𝒎 = ≠ 𝟎; ⇒ 𝑨𝒄𝒎−𝒅𝒎 𝒗𝒊𝒄𝒎 ≠𝟎
𝒗
𝒊𝒏,𝒄𝒎

• Note----In Razavi book—term 𝑨𝒄𝒎−𝒅𝒎 𝒊𝒔 𝒖𝒔𝒆𝒅 to

represent common mode gain under mismatch
BITS Pilani, Pilani Campus
Mismatch-
Random
Sources of mismatch-- MOSFET/ BJT

• Rd (load) mismatch/ Rc (load) mismatch

• Vt mismatch/ Vɤ

• Kn’ mismatch/ Is mismatch

• (W/L) mismatch

BITS Pilani, Pilani Campus

For perfect matching
Vp is ac gnd even if M5 is diode connected

As node p at ac ground

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

With mismatch
Vp ≠ ac gnd, M5 can not be diode connected

As node p not at ac ground,

so Rss is important now which shd be largre. Why??

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Effect of Asymmetry

• Acm ≠ 0, CMRR is not infinite (noise

propagation to output
• Leads to Input offset voltage (why input??)
Remedy ----
• Rss must be large to make Acm HC ≈0

• Why Acm HC ≈ 0 ?? See Next slide/s

BITS Pilani, Pilani Campus

Why Acm HC => 0 ?? 

Why we want Acm HC =>0 ??

• Acm, diff = A cm,HC1 - Acm,HC2

IF A cm,HC1 ≠ Acm,HC2 , We want difference to be close to

zero

• But we also want, Acm HC also to be →0

Because this will give high CMRR when Output is tapped

single endedly
BITS Pilani, Pilani Campus
Real case—
Asymmetry in diff. pair
Two sources----

• Rd Asymmetry

• Transistor pair (M1, M2) Asymmetry

BITS Pilani, Pilani Campus

Acm----Rd mismatch
Contd…

𝑔𝑚
𝑣𝑥 = − 𝑅𝐷 𝑣𝑖𝑐𝑚
1 + 2𝑔𝑚 𝑅𝑠𝑠
𝑔𝑚
𝑣𝑦 = − 𝑅𝐷 + ∆𝑅𝐷 𝑣𝑖𝑐𝑚
1 + 2𝑔𝑚 𝑅𝑠𝑠
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 𝑔𝑚
𝑣𝑥 = − 𝑅𝐷 𝑣𝑖𝑐𝑚
1 + 2𝑔𝑚 𝑅𝑠𝑠
𝑔𝑚
𝑣𝑦 = − 𝑅𝐷 + ∆𝑅𝐷 𝑣𝑖𝑐𝑚
1 + 2𝑔𝑚 𝑅𝑠𝑠
𝑔𝑚
|𝑣𝑥 -𝑣𝑦 | = ± ∆𝑅𝐷 𝑣𝑖𝑐𝑚
1+2𝑔𝑚 𝑅𝑠𝑠

𝑣𝑥 −𝑣𝑦 𝑔𝑚
𝐴𝑐𝑚−𝑑𝑚 = =± ∆𝑅𝐷
𝑣𝑖𝑐𝑚 1 + 2𝑔𝑚 𝑅𝑠𝑠
|𝑣𝑥-𝑣𝑦|----due to Rd mismatch
Contd…

𝑔𝑚
𝑣𝑥 = − 𝑅𝐷 𝑣𝑖𝑐𝑚
1 + 2𝑔𝑚 𝑅𝑠𝑠
𝑔𝑚
𝑣𝑦 = − 𝑅𝐷 + ∆𝑅𝐷 𝑣𝑖𝑐𝑚
1 + 2𝑔𝑚 𝑅𝑠𝑠

𝑣𝑥 −𝑣𝑦 = 𝐴𝑐𝑚−𝑑𝑚 𝑣𝑖𝑐𝑚

𝑔𝑚
|𝑣𝑥 -𝑣𝑦 | = ± ∆𝑅𝐷 𝑣𝑖𝑐𝑚
1+2𝑔𝑚 𝑅𝑠𝑠

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Rd asymmetry— Acm calculation
contd.

𝒗𝒙 −𝒗𝒚
𝑨𝒄𝒎−𝒅𝒎 =
𝒗𝒊𝒄𝒎
𝒈𝒎 ∆𝑅𝐷
=± ;
𝟏 + 𝟐𝒈𝒎 𝑹𝒔𝒔
∆𝑅𝐷
𝑨𝒄𝒎−𝒅𝒎 ≈ ±
𝟐𝑹𝒔𝒔

Design tip---- Increase Rss to reduce 𝑨𝒄𝒎−𝒅𝒎

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
gm mismatch----- diff. output ≠ 0
Acm , CMRR calculation
Find Vx - Vy

∆𝑔𝑚 = 𝑔𝑚1 − 𝑔𝑚2

𝑔𝑚1 + 𝑔𝑚2
𝑔𝑚 =
2

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 𝑖𝑑1 = 𝑔𝑚1 𝑣𝑖𝑐𝑚 − 𝑣𝑝
𝑖𝑑2 = 𝑔𝑚2 𝑣𝑖𝑐𝑚 − 𝑣𝑝
𝑖𝑑1 + 𝑖𝑑2 = 𝑔𝑚1 + 𝑔𝑚2 𝑣𝑖𝑐𝑚 − 𝑣𝑝
𝑣𝑝 = 𝑖𝑑1 + 𝑖𝑑2 𝑅𝑠𝑠
𝑣𝑝 = 𝑔𝑚1 + 𝑔𝑚2 𝑣𝑖𝑐𝑚 − 𝑣𝑝 𝑅𝑠𝑠
𝑔𝑚1 + 𝑔𝑚2 𝑅𝑠𝑠
𝑣𝑝 = 𝑣𝑖𝑐𝑚
𝑔𝑚1 + 𝑔𝑚2 𝑅𝑠𝑠 + 1

𝒗𝒙 = −𝒈𝒎𝟏 𝒗𝒊𝒄𝒎 − 𝒗𝒑 𝑹𝒅
𝒗𝒚 = −𝒈𝒎𝟐 𝒗𝒊𝒄𝒎 − 𝒗𝒑 𝑹𝒅
 𝑔𝑚1 + 𝑔𝑚2 𝑅𝑠𝑠
𝑣𝑝 = 𝑣𝑖𝑐𝑚
1 + 𝑔𝑚1 + 𝑔𝑚2 𝑅𝑠𝑠

𝑣𝑥 = −𝑔𝑚1 𝑣𝑖𝑐𝑚 − 𝑣𝑝 𝑅𝑑
− 𝑔𝑚1 𝑅𝑑
𝑣𝑥 = 𝑣𝑖𝑐𝑚
1 + 𝑔𝑚1 + 𝑔𝑚2 𝑅𝑠𝑠

𝑣𝑦 = −𝑔𝑚2 𝑣𝑖𝑐𝑚 − 𝑣𝑝 𝑅𝑑
− 𝑔𝑚2 𝑅𝑑
𝑣𝑦 = 𝑣𝑖𝑐𝑚
1 + 𝑔𝑚1 + 𝑔𝑚2 𝑅𝑠𝑠
 − 𝑔𝑚1 𝑅𝑑
𝑣𝑥 = 𝑣𝑖𝑐𝑚
1 + 𝑔𝑚1 + 𝑔𝑚2 𝑅𝑠𝑠
− 𝑔𝑚2 𝑅𝑑
𝑣𝑦 = 𝑣𝑖𝑐𝑚
1 + 𝑔𝑚1 + 𝑔𝑚2 𝑅𝑠𝑠

− 𝒈𝒎𝟏 − 𝒈𝒎𝟐
𝒗𝒚 − 𝒗𝒚 = 𝑹𝒅 𝒗𝒊𝒄𝒎
𝟏 + 𝒈𝒎𝟏 + 𝒈𝒎𝟐 𝑹𝒔𝒔

−∆𝒈𝒎 𝑹𝒅
𝑨𝑪𝑴−𝑫𝑴 = 𝒗𝒊𝒄𝒎
𝟏 + 𝒈𝒎𝟏 + 𝒈𝒎𝟐 𝑹𝒔𝒔
 −∆𝒈𝒎 𝑹𝒅
𝑨𝑪𝑴−𝑫𝑴 =
𝟏 + 𝒈𝒎𝟏 + 𝒈𝒎𝟐 𝑹𝒔𝒔
𝒈𝒎,𝒏𝒐𝒎𝒊𝒏𝒂𝒍 = 𝒈𝒎
|𝑨𝑫𝑴 | =
𝒈𝒎𝟏 + 𝒈𝒎𝟐
𝑪𝑴𝑹𝑹 = 𝟐
|𝑨𝑪𝑴 |

𝑔𝑚1 − −𝑔𝑚2 𝑅𝑑
𝐶𝑀𝑅𝑅 = 1 + 𝑔𝑚1 + 𝑔𝑚2 𝑅𝑠𝑠
∆𝑔𝑚 𝑅𝑑
𝑔𝑚1 + 𝑔𝑚2
= 1 + 𝑔𝑚1 + 𝑔𝑚2 𝑅𝑠𝑠
∆𝑔𝑚

𝟐 𝒈𝒎
𝑪𝑴𝑹𝑹 = 𝟏 + 𝟐 𝒈𝒎 𝑹𝒔𝒔
∆𝒈𝒎
Acm , CMRR for gm
mismatch

This CMRR in
correct (why?)

We should
compute
Total Acm-dm---

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Total Acm-dm---
Rd & gm asymmetry together

𝒗𝒐𝒅 = 𝑨𝒅𝒎 𝒗𝒊𝒅 + 𝑨𝒄𝒎−𝒅𝒎 𝒗𝒊𝒄𝒎 + 𝒗𝒐𝒅,𝒐𝒇𝒇𝒔𝒆𝒕

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Total Acm-dm---
Rd & gm asymmetry together

∆𝒈𝒎 𝑹𝒅 ∆𝑅𝐷
|𝑨𝑪𝑴−𝑫𝑴 | = +
𝟏 + 𝒈𝒎𝟏 + 𝒈𝒎𝟐 𝑹𝒔𝒔 𝟐𝑹𝒔𝒔

𝒗𝒐𝒅(𝒕𝒐𝒕𝒂𝒍) = 𝑨𝒅𝒎 𝒗𝒊𝒅 ± 𝑨𝒄𝒎−𝒅𝒎 𝒗𝒊𝒄𝒎 ± 𝒗𝒐𝒅,𝒐𝒇𝒇𝒔𝒆𝒕

Rd & gm asymmetry
What is input offset????
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Input offset
Important parameter of diff amp.
• How to estimate it?
• It limits minimum peak value of vid input which can be
applied (why?)
A consequence of Rd & gm asymmetry
𝒗𝒐𝒅,𝒐𝒇𝒇𝒔𝒆𝒕 adds to desirable differential output.
𝒗𝒐𝒅 = 𝑨𝒅𝒎 𝒗𝒊𝒅 ± 𝒗𝒐𝒅,𝒐𝒇𝒇𝒔𝒆𝒕
𝒗𝒐𝒅,𝒐𝒇𝒇𝒔𝒆𝒕 is reflected at input terminals using relation-
𝑣𝑜𝑑,𝑜𝑓𝑓𝑠𝑒𝑡
𝐴𝑑𝑚 =± ;
𝑣𝑖𝑛,𝑜𝑓𝑓𝑠𝑒𝑡
𝒗𝒐𝒅,𝒐𝒇𝒇𝒔𝒆𝒕
⇒ 𝒗𝒊𝒏,𝒐𝒇𝒇𝒔𝒆𝒕 =±
𝑨𝒅𝒎
BITS Pilani, Pilani Campus
Input offset
Important parameter of diff amp.
𝒗𝒐𝒅,𝒐𝒇𝒇𝒔𝒆𝒕
⇒ 𝒗𝒊𝒏,𝒐𝒇𝒇𝒔𝒆𝒕 =±
𝑨𝒅𝒎
Why does it limit minimum peak value of vid input which can be
applied ?

Example--- let 𝒗𝒐𝒅,𝒐𝒇𝒇𝒔𝒆𝒕 = ±100mV, 𝑨𝒅𝒎 = 𝟓𝟎,

⇒ 𝒗𝒊𝒏,𝒐𝒇𝒇𝒔𝒆𝒕 = ∓2mV (-2mV vid will cause +100mV vod to become
zero)

Meaning, we can not apply vid less than 2 mV or

|𝒗𝒊𝒅 | > |𝟐𝐦𝐕|---
thus min. limit on peak amplitude of input because vid<= 2mv is not
recognized by diff amp BITS Pilani, Pilani Campus
𝒗𝒊𝒏,𝒐𝒇𝒇𝒔𝒆𝒕

For proper operation

|𝒗𝒊𝒅 | ≫ |𝒗𝒊𝒏,𝒐𝒇𝒇𝒔𝒆𝒕 |

thus min. limit on peak amplitude of input because

vid< vin,offset will not give valid differential
output

BITS Pilani, Pilani Campus

Input offset voltage
Limits minimum peak value of vid input
 Diff output (Vod) exists even with both inputs grounded----
-output offset

 Input offset Vos, in= Vod/Adm

Vin,os = (Vin1-Vin2) = Vgs1- Vgs2

Vin,os = (Vgs1- Vt) - (Vgs2-Vt)

Vin,os = (Vov1 - Vov2)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Input Offset

• The input offset voltage is defined as the diff. voltage that

must be applied between the two input terminals of the op

amp to obtain zero volts at the output.

• Ideally, the differential output of the op amp should be zero

volts when the inputs are at same potential.

• In reality , due to offset, the output terminals are at slightly

different potentials
BITS Pilani, Pilani Campus
Significance of input offset voltage

 Critical Specification in diff. amp as comparator

design

 Input offset= Output offset/ Adm

 Input less than Vos will not produce any output.

Or

 Diff. Voltages can not be compared below Vin, offset

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Significance of Vin,offset

 Critical Specification in diff. amp as comparator design.

 Polarity of Vin offset is unknown as random phenomena

 If Vin, offset = ±1mV  we need to apply Vid=-1mV to bring

Vod=0 or vice versa

 This implies if Vid= -1mV applied, output Vod may be zero or

vice versa

 In either case, user is restricted to Vid ˃ |1mV|

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Sources of input offset

Input offset in diff. amplifier is due to mismatch in dc currents

I1, I2 which causes differential current ; ∆𝑰 = 𝑰𝟐 - 𝑰𝟏

𝑮𝒎 𝑽𝒊𝒏.𝒐𝒇𝒇𝒔𝒆𝒕 = 𝒈𝒎 𝑽𝒊𝒏,𝒐𝒇𝒇𝒔𝒆𝒕 = ∆𝑰

Sources of input offset---

• Rd (load) mismatch
• Vt mismatch
• Kn’ mismatch
• (W/L) mismatch
BITS Pilani, Pilani Campus
 BITS Pilani
Pilani Campus

Input Offset calculation

Each source taken separately
Input offset due to Rd mismatch

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Vin,offset due to W/L mismatch

= 𝑔𝑚,𝑛𝑜𝑚𝑖 𝑣𝑔𝑠1

= 𝑔𝑚,𝑛𝑜𝑚𝑖 𝑣𝑔𝑠2

𝑖1 − 𝑖2 = 𝑰ൗ
𝟐 𝑰
𝒈𝒎𝟏 = =
𝑖𝑑1 − 𝑖𝑑2 𝑽𝒐𝒗 𝟐𝑽𝒐𝒗
𝑣𝑖𝑑,𝑜𝑓𝑓𝑠𝑒𝑡 = 𝑣𝑔𝑠1 − 𝑣𝑔𝑠2 =
𝑔𝑚,𝑛𝑜𝑚

𝑊 𝑊
2𝑉𝑜𝑣 𝐼 ∆ 𝑉𝑜𝑣 ∆
𝐿 𝐿
= × 𝑊 = 𝑊
𝐼 2 2 2
𝐿 𝐿

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Vin,offset due to Vt mismatch

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 2𝐼Τ2 𝐼
𝑔𝑚1 = =
𝑉𝑜𝑣 𝑉𝑜𝑣

𝑉𝑖𝑛,𝑜𝑓𝑓𝑠𝑒𝑡 = ∆𝑉𝑡

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Vin,offset due to Kn´ mismatch
𝑖𝑛𝑝𝑢𝑡 𝑜𝑓𝑓𝑠𝑒𝑡 𝑑𝑢𝑒 𝑡𝑜 𝐾𝑛′ 𝑚𝑖𝑠𝑚𝑎𝑡𝑐ℎ − −
′
1 ∆𝐾𝑛 𝑊 2
𝐼1 = 𝐾𝑛 − 𝑉𝑔𝑠 − 𝑉𝑇
2 2 𝐿
′ 𝑊 2 ∆𝐾𝑛′ 𝑊 2
𝐼1 = 0.5𝐾𝑛 𝑉𝑔𝑠 − 𝑉𝑇 − 𝑉𝑔𝑠 − 𝑉𝑇
𝐿 4 𝐿

𝐼 ∆𝐾𝑛′ 1 𝑊 2
𝐼1 = − 𝑉𝑔𝑠 − 𝑉𝑇 𝐾𝑛′
2 2𝐾𝑛′ 2 𝐿
𝐼 𝑰 ∆𝐾𝑛′
𝐼1 = −
2 𝟐 2𝐾𝑛′
𝐼 𝐼 ∆𝐾𝑛′
Similarly--- 𝐼2 = + ∆𝐼
2 2 𝐾𝑛′
𝑉𝑖𝑛,𝑜𝑓𝑓𝑠𝑒𝑡 =
𝑰 ∆𝐾𝑛′ 𝑔𝑚
∆𝑰 = 𝑰𝟐 - 𝑰𝟏 =
𝟐 𝐾𝑛′
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Vin,offset due to Kn´ (= μn Cox)
mismatch
𝑮𝒎 𝑽𝒊𝒏,𝒐𝒇𝒇𝒔𝒆𝒕 = 𝒈𝒎𝟏 𝑽𝒐𝒇𝒇𝒔𝒆𝒕 = ∆𝑰

𝐼 ∆𝐾𝑛′ 𝑰ൗ
𝟐 𝑰
𝒈𝒎𝟏 = =
∆𝐼 2 𝐾𝑛′ 𝑽𝒐𝒗 𝟐𝑽𝒐𝒗
𝑉𝑖𝑛,𝑜𝑓𝑓𝑠𝑒𝑡 = =
𝑔𝑚 𝐼ൗ
𝑉𝑜𝑣.
∆𝐾𝑛′
𝑽𝒊𝒏,𝒐𝒇𝒇𝒔𝒆𝒕 = 𝟐𝑽𝒐𝒗.
𝐾𝑛′

𝐼 ∆𝐾𝑛′
∆𝐼 = 𝐼2 - 𝐼1 =
2 𝐾𝑛′
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Total input offset
output offset= input offset x Adm

Voutput,offset= Vinput offset x Adm

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Input Offset due to Random Mismatch –
Diff. amp. with active load

ro mismatch of M3, M4
due to L , λ mismatch

Load M3, M4 mismatch

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Load M3, M4 mismatch

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Random Offset due to Random Mismatch –
BJT Diff. amp.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Active load -- Diff Amplifier

 BITS Pilani
Pilani Campus

Difference/ Common mode operation

Diff amp with Active (Current mirror) load
Why do we need single ended
output diff amp?

Convenience

Single output diff amp can easily cascade with single stage

amplifiers like CSA, CGA, CDA, CASCODE amplifiers

BITS Pilani, Pilani Campus

What do we loose?

1) Symmetry of the circuit even if we have matched devices.

So two currents through M1 and M2 will not be exactly same
(diff through current through ro component )

Consequences---

 ac currents not exactly equal,

 an ac current flows through Iss.

 source (Vp) is not at ac ground and

 Acm >0, CMRR reduces, (noise immunity reduces)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

What do we loose?

• Acm ≠ 0, CMRR less. Hence to again make that it small,

make Rss very large

• Systematic offset may be present, Careful design is

required to get differential operation here

2) Output Voltage swing reduces (not double).

3) Even order harmonics (not cancelled) present in output

BITS Pilani, Pilani Campus

 Difference mode—
single ended output

Assume input splits equally.( Will they?)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Diff. Amp. with Active load

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Diff amp with current mirror load
symmetry of two arms is lost

VDD

i
gm4vF

i -i

i = gm vin/2
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BJT Diff. amp. with Active load

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

How much Adm with AC voltage at P

node?
How much AC voltage at P node?

i = gm vin/2
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Vout---Using principle of superposition
1+2+3

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Now, Rss plays a crucial role

 If Iss is implemented as diode connected

transistor------ Vp ≠ vin/2---two inputs may not
be equal. why? DC BIAS CURRENT WILL CHANGE

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Vp
can we take it ac gnd.???
ADM— want full gain = [gm(ro||ro)]

What Limiting value Vp which can be taken as ac ground????

2 Methods to verify—
• Find Limiting value Vp which can be taken as ac ground to
obtain full gain Adm????
• Check when Rss large, if Adm is full gain using principle of
superposition

• Conclusion--- high Rss causes Vp (ac) << Limiting value Vp

BITS Pilani, Pilani Campus

Limiting value Vp which can be
taken as ac ground

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Anu Gupta
 BITS Pilani
Pilani Campus

Vout (Adm) using principle of

superposition
When Rss large
Vout Principle of superposition

• Half ckt. Concept can not

be used

• Find vout using principal

of superposition for vicm
input

• DO IT YOURSELF

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

ADM—when Vp is not ac ground

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Total ac voltage at Vp

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Source coupled node---
ac ground for intuitive analysis

Thus, node p is assumed at AC ground for all

calculations

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

What happens if Rss is small?

 The [Rss|| 1/gm] shall reduce

 so Vp will increase

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Implementation CM—
increasing Rout

 Cascode current source—

use source degeneration

For identical devices

CTR = 1
loss = 2 Vgs- Vt
Rout Rout = ro + ro + gm
Voltage loss ro2
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 High Rss current mirror

 Cascode CM

2 Vgs-Vt

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BJT Cascode current mirror
Impact of rπ1 - Rss reduces
Rss= ro4 +(rπ1 || ro4 ) +gm1 ro4 (rπ1 || ro4 )

rπ1 || ro4
(no resistance reflection
rule)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Wilson current mirror, Iref ideal

i= gm (-iro - i/gm) + [v-{i/ gm}] / ro

v/i = gm ro2 +3ro

v

i
-iro

-gm ro i/gm = = i/gm

2 Vgs-Vt

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Wilson current mirror, Iref ideal

(gain
boosting
Technique)

Using CSA to
increase Rout

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Contd…
i= gm (-iro-i/gm) + [v-i/gm] / ro

v/i = gm ro2 +3ro

2 Vgs-Vt
Modified Wilson current mirror
(to negate Vds mismatch)

M0 added to make
Vx=Vy

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BJT Wilson current mirror—
Impact of rπ - reduced Rout

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Design Tips for current mirror
design

 DESIGN TIPS---to get differential operation with

asymmetric diff. amp

 ---Rss very large

 ---Take L large to get ro very large

 Both will help in splitting vin nearly equally between

two differential transistors, to bring p node to nearly
ac ground

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Adm Gain
Using [Gm × Rout] method
Adm, Voltage gain= Gm x Rout

Thus node p is assumed

at AC ground for all
calculations

|𝑨𝒅𝒎 | = 𝑮𝒎 × 𝑹𝒐𝒖𝒕 = 𝒈𝒎𝟐 𝒓𝒐𝟐 ||𝒓𝒐𝟒

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Gm= io/vid with Assumption----
node p at ac ground

VDD
-gm4vF = gm4 [gm1/gm3] vid/2
i -gm4vF
i
As gm3=gm4
-[gm1/gm3]
vin/2
-gm4 vF = gm1 vid/2= i
i i
vid Gm
1/gm2 i
io = 2i= 2gm1 vin1
1/gm1
Rss= 1/gm5 vout

i Rout= ro4 || ro2

Gm≈ gm1
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 BITS Pilani
Pilani Campus

Rout calculation
Rout calculation

3 method

 Vp node ac ground

 when Vp not ac ground (Rss large)-method1

 when Vp not ac ground (Rss large )-method2

BITS Pilani, Pilani Campus

Rout ---(method 1) Vp node ac ground

𝑹𝒐𝒖𝒕 = 𝒓𝑶𝟒 || 𝒓𝒐𝟐

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Rout calculation (method2)-
-- when Vp not ac ground (Rss large)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

KCL at Trans. M2,
𝑣𝑥 −𝑣𝑝 1
− 𝑔𝑚2 𝑣𝑝 = 𝑣𝑝
𝑟𝑜2 𝑔𝑚1
𝑣𝑥 𝑣𝑝 1
=2 𝑔𝑚 𝑣𝑝 + = 𝑣𝑝 2 𝑔𝑚 +
𝑟𝑜2 𝑟𝑜 𝑟𝑜
𝒗𝒙
𝒗𝒑 ≈
2 𝒈𝒎 𝒓𝒐𝟐
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 𝑖𝑥 = 𝑔𝑚1 𝑣𝑝 + 𝑔𝑚4 𝑣𝐹
𝑔𝑚1 𝑣𝑝
𝑣𝐹 = ,
𝑔𝑚3
Sub. 𝑣𝐹 ----
𝑖𝑥 = 𝑣𝑝 𝑔𝑚1 + 𝑔𝑚1 = 2𝑔𝑚1 𝑣𝑝
2𝑔𝑚1 𝒗𝒙
𝑖𝑥 ≈
2𝑔𝑚1 𝒓𝒐𝟐
′
𝒗𝒙
⇒ 𝑹𝒐𝒖𝒕 = = 𝒓𝒐𝟐
𝑖𝑥

𝒗𝒙
𝑹′𝒐𝒖𝒕 = = 𝒓𝒐𝟐
𝒊𝒙
𝑹𝒐𝒖𝒕 = 𝑹′𝒐𝒖𝒕 ||𝒓𝒐𝟒 = 𝒓𝒐𝟐 ||𝒓𝒐𝟒
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Rout calculation -- method-3
Rss --large

BITS Pilani, Pilani Campus

𝑅𝑜𝑢𝑡 = 𝑅𝑈𝑝 ||𝑅𝐷𝑛 || 𝑟𝑂4
𝑅𝑜𝑢𝑡 = 𝑟𝑂4 ||𝑅𝐷𝑛 || 𝑅𝑈𝑝 = 𝑟𝑂4 ||2 𝑟𝑜2 || 2 𝑟𝑜2
𝑹𝒐𝒖𝒕 = 𝒓𝑶𝟒 || 𝒓𝒐𝟐

Where---
1 1
𝑅𝐷𝑛 = 𝑔𝑚2 𝑟𝑜2 + 𝑟𝑜2 +
𝑔𝑚1 𝑔𝑚1
𝑅𝐷𝑛 =2 𝑟𝑜2

𝑣𝑥 𝑣𝑥
𝑅𝑈𝑝 = =𝑣 = 2 𝑟𝑜2
𝑖4 𝑥
ൗ2 𝑟
𝑜2

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Active Load Diff. Amp

Common mode operation---
Acm, CMRR
Common Mode Rejection Ratio-
CMRR

 CMRR= |Adm/ Acm|; Figure of merit

 Ability to reject common signal

 For diff output---- Acm=0; CMRR→∞

ideal case

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Single ended output Diff Amp

• With resistive load

• With Active load

BITS Pilani, Pilani Campus

Resistive load diff amp—
single ended output, using half circuit concept

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

CMRR--- Resistive load diff. amp.

= ½ gmRd

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Active load diff amp - Acm
using half circuit (folding) concept

1 𝑟𝑜3,4
||
2𝑔𝑚3,4 2
𝐴𝐶𝑀 ≈ −
1
+ 𝑅𝑠𝑠
2𝑔𝑚1,2
−1 𝑔𝑚1,2
𝐴𝐶𝑀 ≈ ×
1 + 2𝑔𝑚1,2 𝑅𝑠𝑠 𝑔𝑚3,4
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Active load Diff Amp-- Adm

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Active load Diff amp--- CMRR

Rss should be large

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Active load Diff Amp-- Acm
Under mismatch condition

• Half ckt. Concept can not

be used

• Find vout using principal

of superposition for vicm
input

• DO IT YOURSELF

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Systematic Offset voltage

calculation
Random Offset due to Random Mismatch –
Diff. amp. with active load

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Systematic Offset –
Diff. amp. with active load

𝑾 𝑾 𝝁𝒏 𝑾
𝝁𝒑 = 𝝁𝒏 =
𝑳 𝟑,𝟒 𝑳 𝟏,𝟐 𝟐 𝑳 𝟓

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Systematic Offset – (for matched devices)
Diff. amp. with active load

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Active load Diff Amp– random offset
mismatch condition

• gm1 ≠gm2
• Half ckt. Concept can not
be used

• Find vout using principal

of superposition for input
vid, vicm both

• DO IT YOURSELF

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BJT Systematic offset---
more in BJT diff amp due to base current

Need base current compensation to

reduce it

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Can we apply input single endedly but obtain

differential operation??
Why??? Convenience
Can we apply input single endedly but
obtain differential operation?? Why

Benefit— Convenience

We do not need to convert single

input Vin to differential inputs
(Vin/2), (-Vin/2)

BITS Pilani, Pilani Campus

Example---
Applying input single ended
( but no loss of gain)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

What is Adm if input applied single
endedly (condition Rss large)

Input applied is single ended.

Now, Half circuit concept cannot be applied

Ac ground
Vin
Not ac gnd., for
equal input to M1,
M2, it should be
vin/2 ideally
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Derivation for Adm
Input applied single endedly, condition--- Rss large

Thevenin equivalent

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Gm= gm/2

Adm= -gm Rd (same value)

Thus input can be applied single endedly
with condition--- Rss large
 BITS Pilani
Pilani Campus

Differential amp
Single ended input/ single ended output
Single ended input/ single ended
output

Adm, Acm--Do analysis yourself

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 BITS Pilani
Pilani Campus

End
BITS Pilani
Pilani Campus