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Ehb322e 2017 Spring Final

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Ehb322e 2017 Spring Final

Uploaded by

m.esadakras
Copyright
© © All Rights Reserved
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04.06.

2017
DIGITAL ELECTRONIC CIRCUITS
Final Exam

1. Answer the following question briefly:


a) Can all the transistors have minimum geometry in a NMOS gate? Why?
b) What is the dominant element (determining the worst-case delay) on gate delays of NMOS gates? Why?
c) Which design method is preferred for CMOS gates, NAND based or NOR based? Why?
d) Which kind of functions are proper to be implemented with pass transistor logic (PTL)?
e) State the differences between EPROM and E2PROM.

2. For a CMOS process VDD= 5 V, nCox=60 A/V2, pCox=20 A/V2, VTN=0.6 V, VTP= -0.6 V, Lmin= 0.35 m are
given.

a) Calculate the VTH threshold voltage of minimum sized CMOS inverter.


b) Draw standard CMOS circuit where PMOS network realizes Y = (A+BC)(D+EFG) logic function. State
inputs and outputs of the circuit.
c) For the circuit in (b), calculate the WP /WN ratio which satisfies VTH calculated in (a) if all inputs switch
simultaneously .
d) By using the sizes found in (c), calculate the worst-case τPLH and τPHL delays of CMOS circuit with a CL=0.5
pF load.

3. For the static CMOS gate given below:


 All the NMOS and PMOS gates are identical.
Equivalent resistor for an NMOS transistor: RN= 8kΩ
Equivalent resistor for an PMOS transistor: RP= 24kΩ
 Suppose that each circuit node (including output) has a capacitance value of 10pF.

a) Derive a Boolean expression for the output F in terms of the inputs A and B.
b) Calculate the worst-case and the best-case propagation delays (tPLH and tPHL). (total of 4 values).

4. Y1=X1/.X2/.X3/ +X4/.X5/
Y2=Y1/.( X6/+X7/)(X8/+X9/)
a) Realize logic functions above with NORA (cascaded NMOS-pull-down and PMOS-pull-up dynamic
circuits) logic structure.
b) To prevent dynamic charge loss (leakage, sharing), propose a transistor level structure for both networks.
c) Suppose that Y2 output drives a new block having an inverse clock phase (while one block evaluates,
other block pre-charges). What should be used while connecting Y2 output to next block ? Draw in
transistor level with clock frequencies.

5. For the SR latch in the figure, VDD= 5 V, nCox=60 A/V2, VTN=0.6 V, Lmin= 0.35 m, R=10 kΩ and capacitances
on outputs are given as CL=300 fF. For all the transistors W/L=10.

a) Calculate maximum and minimum values for logic “0” level occuring on circuit output. Which SR input states,
causes these max. And min. Cases?
b) When the circuit input changes from SR=10 state to SR=01 state, calculate the worst-case delay (indicate that
τPLH or τPHL) occuring at Q output.
c) How can a 1-bit SRAM cell be formed by this circuit. Draw the circuit.

N
VDD  VT P  VT N
P
Vth 
N
1
P

CL 1   2VTP 3V  4VTP 
TPLH    ln DD 
P V DD  VTP  V DD  VTP V DD 

CL 1  2VTN 3V  4VTN 
TPHL    ln DD 
N V DD  VTN V 
 DD  VTN V DD 

CL  2VtD  4(VOH  VtD ) 


 PHL    ln   1
 D (VOH  VtD ) VOH  VtD  VOH  VOL 

Delay for RC circuit: tP=0.693RC

NOTE: Closed books and notes. Duration is 120 minutes. Students are not allowed to exchange
calculator, eraser, note, book etc. between them or use cell phone, computer etc. electronic devices.

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