++++++++++++++++++VALABS+++++++++++++++++++++++++ endRTL;

LibraryI EEE; ++++++++++++++++++++++++Par it

é++++++++++++++++++++++++++
USEI EEE. STD_LOGI C_1164. ALL; LIBRARYIEEE;
USEI EEE. STD_LOGI C_UNSI GNED. ALL; USEIEEE.STD_ LOGIC_1164.ALL;
ENTI TYVABSI SPORT( ENTITYPARI TEISPORT(
DIN:INSTD_ LOGI C_VECTOR( 7DOWNTO0) ; DIN:I
NSTD_ LOGI C_VECTOR( 7DOWNTO0) ;
DOUT: OUTSTD_ LOGIC_VECTOR( 7DOWNTO0) ); OI,OP:OUTSTD_ LOGI C) ;
ENDVABS; ENDPARI TE;
ARCHI TECTURERTLOFVABSI S ARCHITECTURERTLOFPARI TEIS
BEGI N BEGIN
DOUT<=not (DIN)+1whenDI N(7)='1'el
seDIN; OI<=DIN(0);
ENDRTL; OP<=NOTDI N( 0);
++++++++++++++++++++DEMUX1_ 5++++++++++++++++++++++ ENDRTL;
l
ibraryI EEE; ++++++++++++++++++++++++MUX2_ 1++++++++++++++++++++++++++
useI EEE. STD_ LOGI C_1164.all
; LIBRARYIEEE;
entityDEMUXi s USEIEEE.STD_ LOGIC_1164.ALL;
por t(S: inst d_l
ogic_vector(1downt o0); ENTITYMUX_ 1_2ISPORT(
SEL: instd_ l
ogic_vector(2downt o0); SEL:INSTD_ LOGIC;
A,B, C,D,
E: outstd_l
ogic_ vect
or(1downt o0);) ; A,B:INSTD_ LOGI C_VECTOR( 7DOWNTO0) ;
endDEMUX; O:OUTSTD_ LOGIC_VECTOR( 7DOWNTO0) );
architect ureRTLofDEMUXi s ENDMUX_ 1_2;
begin ARCHITECTURERTLOFMUX_ 1_2IS
A<=" 00" ; BEGIN
B<=" 00" ; O<=AWHENSEL=' 0' ELSE
C<=" 00" ; BWHENSEL=' 1'ELSE
D<=" 00"; "
XXXXXXXX" ;
E<=" 00" ; ENDRTL;
process( SEL)
begi n
caseSELi s ++++++++++++++++++++++++7_
SEGM ++++++++++++++++++++++++
when" 000"=>E<=S; -
-POURALLUMERUNSEGMENTONMETSONSI GNALA' 0'
--
when" 001"=>D<=S; LI
BRARYI
EEE;
when" 010"=>C<=S; USEI
EEE.
STD_
LOGI
C_1164.
ALL;
when" 011"=>B<=S;
when" 100"=>A<=S; ENTI
TYCONVERTER_ BITS_HEXAIS
PORT(NI:I
NSTD_LOGIC_VECTOR(3DOWNTO0);
-
-whenOTHERS=>A<=" 00";
B<="00"
;C<="00";
D<="
00"
;E<="
00"
;
SEG:
OUTSTD_LOGIC_VECTOR(6DOWNTO0))
;
endcase; ENDCONVERTER_ BI
TS_HEXA;
endpr ocess; ARCHITECTURERTLOFCONVERTER_ BITS_
HEXAI
S
BEGI
N "0000111"whend_in="
0111"else
PROCESS(IN)BEGI
N CASEIIS "1111111"whend_in="
1000"else
WHEN"
0000"=>SEG<="1000000"
;--
0 WHEN"
0001"=>SEG<="
1111001"
;--
1 "
1101111"whend_ i
n="1001"else
WHEN"
0010"=>SEG<="
0100100"
;--
2 WHEN"
0011"=>SEG<="
0110000"
;--
3
"
1110111"whend_ i
n="1011"else
"
1111000"whend_ i
n="1010"else
WHEN"
0100"=>SEG<="
0011001"
;--
4 WHEN"
0101"=>SEG<="
0010010"
;--
5 "0111001"whend_in="
1100"else
"1011110"whend_in="
1101"else
WHEN"
0110"=>SEG<="
0000010"
;--
6 WHEN"
0111"=>SEG<="
1111000"
;--
7 "1111001"whend_in="
1110"else
WHEN"
1000"=>SEG<="
0000000"
;--
8 WHEN"
1001"=>SEG<="
0010000"
;--
9 "1110001"whend_in="
1111"else
"0000000";
WHEN"
1010"=>SEG<="
0100000"
;--
a WHEN"
1011"=>SEG<="
0000011"
;--
b msb<=" 1000000"whend_i
n<" 1010"el
se
"
1111001"whend_ i
n<="1111";
WHEN"
1100"=>SEG<="
1000110"
;--
C WHEN"
1101"=>SEG<="
0100001"
;--
d
l
sb<=not (si
g_LSB);
WHEN"
1110"=>SEG<="
0000110"
;--
E WHEN"
1111"=>SEG<="
0001110"
;--
F endrtl
;

WHENOTHERS=>SEG<="
1111111"
;--ETEI
NT +++++++++++++++++++++Conver
t7seg++++++++++++++++++
ENDCASE; LIBRARYIEEE;
ENDPROCESS; USEIEEE.STD_LOGI
C_ 1164.
ALL;
ENDRTL; USEIEEE.STD_LOGI
C_ UNSIGNED.
ALL;
+++++++++++++++++27_ SEGM lsbetmsb+++++++++++++ useIEEE.
NUMERI C_STD.ALL;
l
ibraryi eee;
usei eee. std_ l
ogi c_1164. al
l; ENTITYAf f
_7SEGISPORT(
entit
yconv ertisseuri spor t( Data_i
n:I
NSTD_ LOGIC_VECTOR( 3DOWNTO0) ;
HEX0,HEX1:OUTSTD_ LOGIC_VECTOR( 6DOWNTO0) ;
d_in: i
nst d_ l
ogi c_vector (3downt o0);
ENDAf f _
7SEG;
l
sb: outst d_ logic_ vector(6downt o0);
ARCHI TECTURERTLOFAf f
_7SEGIS
msb: outst d_ l
ogi c_vector(6downt o0)
--
SIGNALsi g_HEX0: STD_LOGIC_VECTOR(6DOWNTO0) ;-
-pourlesuni
tes
);
--
SIGNALsi g_HEX1: STD_LOGIC_VECTOR(6DOWNTO0) ;-
-pourles
endconv ertisseur ; dizai
nes BEGI
N
architectur er tlofconv erti
sseuris PROCESS(Data_i
n)
signal sig_LSB: std_ l
ogic_vector(
6downt o0)
; BEGI
N
begin CASEData_inis
sig_LSB<=" 0111111"whend_ i
n="0000"el
se when"0000"=>HEX0<=" 1111110"
;HEX1<=" 1111110";
"0000110"whend_ in="0001"else when"0001"=>HEX0<=" 0110000"
;HEX1<=" 1111110";
"1011011"whend_ in="0010"else when"0010"=>HEX0<=" 1101101"
;HEX1<="1111110";
"1001111"whend_ in="0011"else when"0011"=>HEX0<=" 1111001"
;HEX1<="1111110";
"1100110"whend_ in="0100"else when"0100"=>HEX0<=" 0110011"
;HEX1<="1111110";
"1101101"whend_ in="0101"else when"0101"=>HEX0<=" 1011011"
;HEX1<="1111110";
"1111101"whend_ in="0110"else when"0110"=>HEX0<=" 1011111"
;HEX1<="1111110";
 when"0111"=>HEX0<="1110000"
;HEX1<="
1111110"
;
when"1000"=>HEX0<="1111111"
;HEX1<="
1111110"
; +++++++++++++++++++++adder4bi t
s++++++++++++++++++++++
when"1001"=>HEX0<="1110011"
;HEX1<="
1111110"
; l
ibraryieee;
when"1010"=>HEX0<="1111110"
;HEX1<="
0110000"
; useieee. std_l
ogic_1164.all
;
when"1011"=>HEX0<="0110000"
;HEX1<="
0110000"
; USEI EEE. STD_LOGI C_UNSIGNED. ALL;
when"1101"=>HEX0<="1111001"
;HEX1<="
0110000"
; entit
yadder _
4bi t
sispor t
(
when"1110"=>HEX0<="0110011"
;HEX1<="
0110000"
; d1,d2:instd_logic_v
ector(3downt o0);
when"1111"=>HEX0<="1011011"
;HEX1<="
0110000"
; sum: outst d_l
ogic_vector
(3downt o0));
whenother
s=>HEX0<=" XXXXXXX";
HEX1<="XXXXXXX"; endadder _4bit
s;
ENDCASE; architecturertlofadder_4bit
sis
ENDPROCESS;
begin
endRTL;
sum <=st d_l
ogic_vector(
unsigned(d1)+unsi
gned(d2)
);
endr tl;
++++++++++++++++++++decompf r
om 16++++++++++++++++++
l
ibraryi eee;
++++++++++++++++++++++t op_adder
++++++++++++++++++++++
usei eee. std_ l
ogi c_1164.all
;
l
ibr
aryieee;
usei eee. numer ic_std.al
l;
useieee.
std_
logic_1164.
all
;
ent i
tydecompt eurispor t(
useieee.
std_
logic_unsi
gned.al
l
;
clk: i
nst d_ l
ogic;
useieee.
numeric_std.
all
;
rst:i
nst d_ logic;
Dn: I
NSTD_ LOGI C;
ENTITYadder_topISPORT(
D_ out: outst d_logic_vector(3downto0));
a:
instd_l
ogic_v
ector(
3DOWNTO0)
;
enddecompt eur;
b:
instd_l
ogic_vect
or(
3DOWNTO0);
architect urer tlofdecompt euris
s:
outstd_l
ogic_vect
or(
6DOWNTO0))
;
signal compt e: UNSI GNED( 3downto0):="
1111"
;
ENDadder _
top;
begin
process( clk,
rst)
ARCHI
TECTURERTLOFadder _topIS
begin
COMPONENTadder_4bit
sISPORT(
i
f(rst='0')then
d1:
instd_l
ogi
c_v
ector (
3DOWNTO0);
compt e<=" 1111" ;
d2:
instd_l
ogi
c_v
ector (
3DOWNTO0);
elsif
(clk'ev entandcl k='1'
)then
sum:outst
d_l
ogic_vector
(3DOWNTO0)
);
IF(Dn=' 1'
)THEN
ENDCOMPONENT;
compt e<=compt e-1;
ENDI F;
COMPONENTseven_segI
SPORT(
endi f;
si
g_i
n:INSTD_LOGIC_VECTOR(3DOWNTO0);
endpr ocess;
si
g_out
:OUT STD_LOGIC_VECTOR(6DOWNTO0)
);
D_ out<=STD_ LOGI C_ VECTOR( compte)
;
ENDCOMPONENT;
endr tl;
 si
gnal
sig1:
STD_
LOGI
C_VECTOR(3DOWNTO0)
; ENDRTL;
BEGI
N +++++++++++++++++++Comp_
16++++++++++++++++
add:adder
_4bi
tsPORTMAP( ENTITYcount _
16ISPORT(
d1=>a, CLK: I
NSTD_ LOGIC;
d2=>b, RST: I
NSTD_ LOGIC;
sum=>sig1); UP:INSTD_ LOGIC;
SOUT: OUTSTD_LOGIC_VECTOR( 3DOWNTO0))
;
ENDcount _16;
seg:seven_segpor
tmap( ARCHI TECTURERTLOFcount _16IS
si
g_i
n=>si g1, SIGNALS: STD_LOGIC_VECTOR(3DOWNTO0) :
="0000"
;
si
g_out=>s); BEGIN
endrtl
; PROCESS( RST,CLK)
++++++++++++++++compt /decompt/l
oad+++++++++++++++++++ BEGIN
LIBRARYIEEE; I
F(RST=' 0'
)THENS<=" 0000"
;
USEIEEE.STD_ LOGIC_1164.ALL; USEI EEE.STD_
LOGIC_UNSIGNED.
ALL; ELSIF(CLK'
EVENTANDCLK=' 1')THENS<=S+1;
ENTITYcomptI S ENDI F;
GENERIC( Tail
le:I
NTEGER:=4) ; ENDPROCESS;
SOUT<=S;
PORT( CLK,LOAD,CLEAR,UP,DOWN: INSTD_ LOGIC;
ENDRTL;
INPUT:INSTD_ LOGIC_VECTOR( Tai
l
le-
1DOWNTO0) ;
++++++++++++++++divf
req+++++++++++++++++++
OUTPUT: OUTSTD_ LOGIC_VECTOR( Tail
le-
1DOWNTO0) )
;
==================PROF====================
ENDcompt ; l
ibraryIEEE;
USEI EEE.STD_ LOGIC_1164.ALL;
ARCHI TECTURERTLOFcomptI S USEI EEE.STD_ LOGIC_UNSIGNED.ALL;
SIGNALTEMP: STD_ LOGI
C_VECTOR( Tai
l
le-
1DOWNTO0)
; ENTITYdi v _f
reqIS
BEGIN PORT(
PROCESS( CLK, CLEAR)BEGIN CLK_ I
N: i
nSTD_ LOGIC;
IF(CLEAR=' 0'
)THEN rst
: i
nSTD_ LOGIC;
TEMP<=( OTHERS=>' 0'
); CLK_ OUT: OUTSTD_ LOGIC);
ELSIF( CLK'EVENTANDCLK=' 1'
)THEN ENDdi v_freq;
ARCHI TECTURERTLOFdi v
_freqI
S
I
F( LOAD=' 1'
)THEN
SIGNALcount :I
NTEGER=0;
TEMP<=I NPUT; BEGIN
ELSI F(UP=' 1')THEN
TEMP<=TEMP+1; PROCESS( rst,
CLK_I
N)
ELSIF(DOWN=' 1'
)THEN BEGIN
TEMP<=TEMP-1; I
F( r
st='
0')thencount<=0;
ENDI F; ELSIF(CLK_ I
N'EVENTandCLK_I
N='
1')
then
ENDI F; i
f(count=20000000)t
hencount<=0;
ENDPROCESS; el
secount<=count+1;
OUTPUT<=TEMP; endif;
ENDI F;
endpr ocess; ENDRTL;
process(CLK_IN,rst) ++++++++++++++++++++compar
ateur
_4bi
ts_
tb+++++++++++++++++
begin
if(r
st='
0')thenCLK_ OUT<='0'
; LI
BRARYI
EEE;
elsi
f(CLK_ IN'
eventandCLK_IN='
1')t
hen USEI
EEE.
STD_
LOGI
C_1164.
ALL;
i
f( count<=10000000)thenCLK_OUT<='
1'
; USEI
EEE.
STD_
LOGI
C_UNSIGNED.
ALL;
elseCLK_ OUT<='0'
;
endi f
;
ENTI
TYcompar
ateur
_4bi
ts_
tbI
S
endif;
endpr ocess;
ENDRTL; ENDcompar
ateur
_4bi
ts_
tb;
============MRREDOUANE==============
--
DIVISIONDEL' HORLOGEPAR( 32768)
10=(1000000000000000)
2
ARCHITECTUREcompar ateur_4bit
s_t
bIS
LIBRARYI EEE; COMPONENTcompar ateur_4bit
s_tbI
S
USEI EEE.STD_LOGIC_1164.ALL; PORT(A:I
NSTD_ LOGIC_VECTOR( 3DOWNTO0)
;
USEI EEE.STD_LOGIC_ARITH.ALL; B:I
NSTD_ LOGIC_VECTOR( 3DOWNTO0) ;
USEI EEE.STD_LOGIC_UNSIGNED. ALL; Ega:OUTSTD_ LOGIC;
ENTITYLENTI SPORT(HORLOGE: I
NSTD_ LOGIC; Inf
:OUTSTD_LOGI C;
H_LENTE: OUTSTD_ LOGIC); Sup:OUTSTD_ LOGIC);
ENDLENT;
ARCHI TECTUREALENTOFLENTI S ENDCOMPONENT;
SIGNALCOMPTEUR: STD_ LOGIC_VECTOR( 14DOWNTO0);-
-15BI
TS
BEGIN U0:comparateur
_4bi
tsPORTMAP(
PROCESS( HORLOGE)BEGI N A=>A;
I
F( HORLOGE'EVENTANDHORLOGE=' 1'
)THEN B=>B;
COMPTEUR<=COMPTEUR+1; Ega=>Ega;
ENDI F; Sup=>Sup;
ENDPROCESS;
I
nf=>Inf;
)
H_ LENTE<=COMPTEUR( 14);
PROCESS
ENDALENT;
BEGIN
++++++++++++++++compar
ateur
_4bi
ts+++++++++++++++++++
A<="0011";
USEIEEE.STD_LOGI
C_UNSIGNED.ALL;
ENTITYCOMPARATEURI S
B<="0011";
PORT( WAI TFOR15ns;
A,
B:I
NSTD_ LOGI
C_VECTOR(3DOWNTO0);
EGA,
SUP, I
NF:OUTSTD_LOGIC:='
0'
); A<="
1001"
;
ENDCOMPARATEUR; B<="
1110"
;
ARCHITECTURERTLOFCOMPARATEURI S WAITFOR25ns;
BEGIN
EGA<='1'
WHENA=BELSE' 0'; A<="
1100"
;
SUP<='1'
WHENA>BELSE' 0'
; B<="
0010"
;
I
NF<='1'WHENA<BELSE ' 0'
; WAITFOR31ns;
ENDPROCESS;

++++++++++++++++++++compar
ateur
_8bi
ts++++++++++++++++++++ +++++++++++++++++++r
egi
str
e_8bi
ts++++++++++++++++++++++++
LI
BRARYI
EEE; LI
BRARYI EEE;
USEI
EEE.
STD_
LOGI
C_1164.
ALL; USEIEEE.STD_ LOGIC_1164.
ALL;
USEI
EEE.
STD_
LOGI
C_UNSIGNED.
ALL; USEIEEE.STD_ LOGIC_UNSIGNED.ALL;
ENTITYreg_ 8bit
sIS
ENTI
TYcomp_ 8bitsI
SPORT( PORT(
A,
B:INSTD_LOGI C_VECTOR(7DOWNTO0)
; cl
k,
rst,EN:I NSTD_ LOGIC;
EGA,
SUP,
INF:OUTSTD_ LOGI
C); dat
a_in:I
NSTD_ LOGIC_VECTOR(7downto0)
;
ENDcomp_8bi
t s; dat
a_out: OUTSTD_ LOGIC_VECTOR(7DOWNTO0)
);
ENDr eg_8bits;
ARCHITECTURErtlofcomp_8bit
sIS
COMPONENTcomp_ 4bitsI
SPORT( ARCHI TECTURErtlOFreg_8bi
tsI
S
A,
B:I
NSTD_ LOGI
C_VECTOR( 3DOWNTO0)
; begin
EGA,
SUP,INF:OUTSTD_ LOGIC)
; PROCESS( cl
k,r
st)
ENDCOMPONENT; BEGIN
I
F( RST='0'
)t
hen
SIGNALinf_
MSB,i
nf_
LSB,
sup_
MSB,
sup_
LSB,
ega_
MSB,
ega_
LSB,
i
nf_
int
er,
sup_
int
er: data_out<=(ot
hers=>'
0')
;
STD_LOGIC;
BEGIN ELSI
F(CLK'
EVENTandCLK='1'
)THEN
U0:comp_4bit
sPORTMAP( IF(
EN='1'
)THENdata_out<=data_
in;ENDi
f;
A=>A(7DOWNTO4), ENDIF;
B=>B( 7DOWNTO4) , ENDPROCESS;
i
nf=>inf_MSB, ENDrtl
;
ega=>ega_MSB,
sup=>sup_MSB); ================OPT-
ARI
TH=================
I
BRARYI EEE;
U1:comp_4bi
tsPORTMAP( USEIEEE.STD_LOGIC_1164.ALL;
A=>A(3DOWNTO0) , USEIEEE.NUMERIC_STD. ALL;
B=>B( 3DOWNTO0) , ENTI
TYCALCULI SPORT( A,B:I
NSIGNED(7DOWNTO0);
i
nf=>inf_
LSB, ABSOL,DIV,REST,MODUL: OUTSIGNED(7DOWNTO0);
ega=>ega_LSB, MUL:OUTSI GNED( 15DOWNTO0) );
sup=>sup_LSB); ENDCALCUL;
ARCHITECTURERTLOFCALCULI S
ega<=ega_ MSBandega_ LSB; -
-PERMETTENTD’ AFFICHERLESVALEURSDESRESULTATS
sup_
inter<=ega_MSBandsup_ LSB; SI
GNALVA, VB,VABS,VD, VR,VMOD,VMUL:I
NTEGER;
sup<=sup_MSBOR sup_ i
nt er
; BEGI
N
i
nf_i
nter<=ega_MSBANDi nf_LSB; -
-SORTIES:
i
nf<=inf_MSBORi nf
_int
er; ABSOL<=ABS( A); MUL<=A*B; MODUL<=AMODB;
ENDRTL; REST<=AREM B; DIV<=A/B;
-
-SIGNAUXINTERNES(PRTESTSSLMNT): ENDCASE;
VA<=TO_I
NTEGER(A); VB<=TO_INTEGER(B)
; ENDPROCESS;
VMUL<=TO_INTEGER(A*B); VD<=TO_INTEGER(
A/B); ENDRTL;
VMOD<=TO_ I
NTEGER(AMODB) ; VR<=TO_I
NTEGER(AREM B)
; =====================TRANSI TION======================
VABS<=TO_I
NTEGER(ABS(
A)); -
-détectesiunsignalchanged’ étatent
redeuxfront
smont antsd’
hor
loge
ENDRTL; LI
BRARYI EEE;
USEIEEE.STD_LOGIC_ 1164.
ALL;
=======================ETATS======================== ENTITYTRANSI TISPORT( CLK,E: I
NSTD_ LOGIC;S:
OUTSTD_ LOGIC);
LI
BRARYI EEE; ENDTRANSI T;
USEI EEE.std_logi c_ 1164. ALL; ARCHITECTURERTLOFTRANSI TI S
ENTITYPCI SPORT( Clk, RST, SB, Comp, Fi
n: INst d_l
ogi c; SIGNALQ0, Q1:STD_ LOGIC;--st
ockerdeuxv al
ssuccessivesdeE
Sel,
Init,Enable_ d, Enabl e_ p, Enabl e_ r: OUTst d_ l
ogi c); BEGIN
ENDPC; --pasd’ état sdansl ’
ent i
t é S<=QAXORQB;
ARCHI TECTURERTLOFPCI S PROCESSBEGI N
TypeEt atIS( Etat 0, Etat1, Etat 2,Etat 3); WAITUNTI LCLK=' 1'
;-
-if(cl
k’eventandcl
k='1'
)
SIGNALc_ state, n_ state: Etat ; Q0<=E;Q1<=Q0;
BEGIN ENDPROCESS;
Updat e_State: PROCESS( RST, Cl k)BEGI N ENDRTL;
I
F( RST=' 0')THENc_ stat e<=Et at 0;
ELSIF(Cl k'ev entANDCl k=' 1')THENc_ state<=n_ state; =========================COMPT- BCD======================
ENDI F; LI
BRARYI EEE;
ENDPROCESS; USEIEEE. STD_ LOGIC_ 1164.ALL;
Etat_f
utur: PROCESS( SB, Comp, Fi n,c_ state)BEGI N USEIEEE. STD_ LOGIC_ UNSIGNED. ALL;
CASEc_ stat eI S ENTITYCOMPT_ BCDI SPORT( CLK, RST: I
NSTD_ LOGIC;
WHENEt at0=>Enabl e_p<=' 0' ; Enabl e_ d<=' 0'; LSB,MSB: OUTSTD_ LOGI C_VECTOR( 3downt
o0));
Enabl e_r<=' 0'; Sel <=' 1'
; I ni t<='0'; ENDCOMPT_ BCD;
IF( SB=' 1')THEN n_ st at e<=Et at 1; ARCHI TECTURERTLOFCOMPT_ BCDI S
ELSE n_ st ate<=Et at 0;ENDI F; SIGNALSI G_ LSB, SI
G_ MSB: STD_ LOGIC_ VECTOR( 3downto0):
="0000"
;
WHENEt at1=>Enabl e_p<=' 1' ; Enabl e_ d<=' 1'; SIGNALUP_ MSB: STD_ LOGIC:='
0';
Enabl e_r<=' 0'; Sel <=' 0'; I nit<=' 1'; BEGIN
I
F( Fin='1')THEN n_ stat e<=Et at2; PROCESS( CLK,RST) BEGI N
ELSE n_ st at e<=Et at 1;ENDI F; IF(RST=' 0')THENSI G_LSB<=" 0000";
WHENEt at2=>Enabl e_p<=' 1' ; Enabl e_ d<=' 0'; ELSIF(CLK' eventANDCLK=' 1')THEN
Enabl e_r<=' 1'; Sel <=' 0'
; I ni t
<=' 0'; IFSIG_ LSB=" 1001"THEN
IF( Comp=' 1')THEN n_ state<=Et at0; SIG_LSB<=" 0000" ; UP_MSB<='1'
;
ELSE n_ st ate<=Et at 3;ENDI F; ELSE SI G_LSB<=SI G_ LSB+1; UP_MSB<='0'
;
WHENEt at3=>Enabl e_p<=' 0' ; Enabl e_ d<=' 0'; ENDI F;ENDI F;
Enabl e_r<=' 0'; Sel <=' 0'
; I nit<='0'; ENDPROCESS;
IF( SB=' 1')THEN n_ stat e<=Et at1; PROCESS( UP_ MSB,RST) BEGI N
ELSE n_ st ate<=Et at 3; ENDI F; IF(RST=' 0')THEN SI G_MSB<=" 0000"
;
WHENOTHERS=>Enabl e_ p<=' 0'; Enabl e_ d<=' 0'; ELSIF(UP_ MSB=' 1')THEN
Enabl e_r<=' 0'; Sel <=' 0'; I nit<=' 0'
; n_ state<=Et
at0; IFSIG_ MSB=" 1001"THEN SIG_MSB<=" 0000"
;
 ELSE SIG_
MSB<=SI
G_MSB+1; i
f(rst='0')t hen
ENDIF; m_ count <=" 000000";
ENDI
F; h_up<=' 0';
ENDPROCESS; el
si f(clk'ev entandcl k='
1')then
LSB<=SI
G_LSB; MSB<=SI
G_MSB; i
f(mi n_up=' 1')
then
ENDRTL; i
f(m_ count <="111011")then
m_ count <=" 000000";
=========================MONTRE====================== h_up<=' 1';
el
se
LIBRARYI EEE; m_ count <=m_ count+1;
USEI EEE. st d_ l
ogic_1164. all
; h_up<=' 0';
USEI EEE. STD_ LOGIC_ UNSI GNED. ALL; endi f;
ENTI TYmont reIS endi f;
PORT(cl k:INst d_logic; endi f;
rst:INst d_ logic; ENDPROCESS;
Second_ count :OUTst d_logi
c_ vector(
5downto0); HEUREE: PROCESS( clk,
rst)
mi n_ count :
OUTst d_ logic_vector(5downto0); BEGI N
heur e_ count :
OUTst d_logic_vector(4downto0)
); i
f(rst='0')t hen
ENDmont re; h_count <=" 00000";
ARCHI TECTURERTLOFmont r
eI S
SIGNALmi n_ up: std_ l
ogi c; el
sif(clk'eventandclk='1'
)then
SIGNALh_ up:st d_logi c; i
f(h_up='1')t
hen
SIGNALsec_ count ,m_ count:STD_ LOGIC_VECTOR(5downt
o0)
; i
f(h_count <="10111")then
SIGNALh_ count :STD_ LOGI C_VECTOR( 4downto0); h_count <="00000";
BEGI N el
se
SECOND: PROCESS( clk,rst) h_count <=h_count+1;
BEGI N endif;
i
f(rst ='0')t hen endif;
sec_ count <=" 000000" ; endif;
mi n_ up<=' 0' ; ENDPROCESS;
elsif( clk'ev entandcl k='1')then Second_ count <=sec_count
;
i
f(sec_ count <="111011" )then min_count <=m_ count;
sec_ count <=" 000000" ; heure_count <=h_count;
mi n_ up<=' 1' ; ENDRTL;
else
sec_ count <=sec_ count +1; =========================COMPTEURMI
N======================
mi n_ up<=' 0' ; LI
BRARYI
EEE;
endi f ; USEI
EEE.
STD_
LOGI
C_1164.
ALL;
endi f; USEI
EEE.
STD_
LOGI
C_UNSIGNED.
ALL;
ENDPROCESS;
MI NUTE: PROCESS( clk,rst) ENTI
TYM_
countI
SPORT(
BEGI N
Rst: I
NSTD_ LOGIC; endpwm;
cl
k: INSTD_ LOGI
C; archi
tecturer t
l ofpwm i s
S_up: I
NSTD_ LOGIC; si
gnal di
v _
sig: unsi gned( 31downt
o0) ;
H_up: OUTSTD_ LOGIC; si
gnal duty_sig: unsi gned(31downto0);
M_ out:OUTSTD_ LOGIC_
VECTOR(
7DOWNTO0))
; si
gnal counter: unsi gned(31downto0);
ENDM_ count; si
gnal pwm_ on: std_ logi
c;

ARCHI
TECTURERTLOFM_
counti
s begi
n
di
v_sig<=unsi
gned(
div
_in)
;
SIGNALsi
g_count:
std_
logi
c_v
ect
or(
7DOWNTO0)
; duty
_sig<=unsi
gned(
duty_
in)
;
begi
n
di
vider:pr ocess(clk,
rst
)
PROCESS( clk,
Rst) begin
BEGIN i
frst='
0' then
i
f(Rst='0'
)then counter<=( others=>'
0')
;
sig_count<=(other
s=>'0')
; el
sif(
clk'ev entandclk='1'
)then
el
sif(clk'
eventandcl k='1'
)t
hen i
fcount er>=di v_
sigthen
if
(S_up='1')
then counter<=( others=>'
0')
;
i
f(si
g_count="00111011" )then el
se
sig_count<=(others=>'0'
); counter<=count er+1;
el
se endif;
sig_count<=sig_count+1; endif;
endif; endpr ocess;
endif ;
endif; duty_cycle:process(clk,
rst
)
ENDPROCESS; begin
H_up<=' 1'WHENsi g_count="00111011"el se'0'
; i
frst='0'then
M_ out<=sig_count; pwm_ on<='1'
;
endRTL; el
sif(clk'
ev entandcl k='1'
)then
i
fcount er>=dut y_si
gt hen
=========================PWM ====================== pwm_ on<='0'
;
l
ibraryieee; el
sifcount er=0t hen
usei eee.std_l
ogi c_1164.all; pwm_ on<='1'
;
usei eee.numer ic_std.al
l; endif;
entit
ypwm i spor t( endif;
clk:i
nst d_logic; endpr ocess;
rst:
instd_ l
ogic; out_port<=(others=>pwm_ on);
div_i
n: i
nst d_l
ogi c_vector(31downto0)
;
duty_ i
n:instd_ l
ogic_vector (
31downto0); endr
tl
;
out_por t
:outst d_ l
ogic_vector(
25downto0))
;
=========================PWM TOP======================
l
ibr
aryieee; dut
y<="00000000000000001111111111111111"whensel_
dut
y="01"el
se
useieee.
std_
logic_1164.
all
; "
00000000000000000000000011111111"whensel_dut
y="
11"else
useieee.
numeric_std.
all
; "
00001111111111111111111111111111"whensel_dut
y="
11"else
"
00000000000000000000000000000000";
enti
typwm_ t
opi spor t
( endrt
l;
clk:i
nst d_logic;
rst:
i
nst d_logic;
sel_di
v :i
nst d_logi
c_ v
ector(1downto0);
sel_duty:i
nst d_ l
ogic_vector
(1downto0);
pwm_ out:outst d_l
ogic_vector
(25downto0)
);
endpwm_ top;

ar
chi
tect
urer
tlofpwm_
topi
s

componentpwm i sport(
clk:i
nstd_logic;
rst:
i
nstd_ l
ogic;
div_i
n:i
nst d_l
ogic_vect
or(31downto0)
;
duty_i
n:instd_ l
ogi
c_vector(
31downto0);
out_port
:outst d_l
ogic_
vector(
25downto0))
;
endcomponent ;

si
gnal
div:
std_l
ogic_vect
or(31downto0);
si
gnal
duty:
std_l
ogic_vector
(31downto0);
si
gnal
count
er:st
d_logic_
vector
(31downto0);

begi
n

U0: pwm por tmap(

clk=>clk,
rst=>rst,
div_i
n=>di v
,
duty_in=>duty,
out_por t
=>pwm_ out
);

di
v<="00000000000000001111111111111111"whensel
_di
v="
01"el
se
"00000000000000000000001111111111"whensel
_di
v="
10"el
se
"00000000000000000000000011111111"whensel
_di
v="
11"el
se
"00000000000000000000000000000000";