Multimodal Sensor Front End

Data Sheet ADPD4000/ADPD4001

FEATURES GENERAL DESCRIPTION
Multimodal analog front end The ADPD4000/ADPD4001 operate as a complete multimodal
8 input channels with multiple operation modes to sensor front end, stimulating up to eight LEDs and measuring
accommodate the following measurements: PPG, ECG, the return signal on up to eight separate current inputs. Twelve
EDA, impedance, and temperature time slots are available, enabling 12 separate measurements per
Dual channel processing with simultaneous sampling sampling period.
12 programmable time slots for synchronized sensor
measurements The data output and functional configuration utilize an I2C
Flexible input multiplexing to support differential and interface on the ADPD4001 or a serial port interface (SPI) on
single-ended sensor measurements the ADPD4000. The control circuitry includes flexible LED
8 LED drivers, 4 of which can be driven simultaneously signaling and synchronous detection. The devices use a 1.8 V
Flexible sampling rate from 0.004 Hz to 9 kHz using internal analog core and 1.8 V/3.3 V compatible digital input/output (I/O).
oscillators The analog front end (AFE) rejects signal offsets and corruption
On-chip digital filtering from asynchronous modulated interference, typically from
SNR of transmit and receive signal chain: 90 dB ambient light, eliminating the need for optical filters or externally
Ambient light rejection: 60 dB up to 1 kHz controlled dc cancellation circuitry. Multiple operating modes
400 mA total LED drive current are provided, enabling the ADPD4000/ ADPD4001 to be a
Total system power dissipation: 50 µW (combined LED and sensor hub for synchronous measurements of photodiodes,
AFE power), continuous PPG measurement at 75 dB SNR, biopotential electrodes, resistance, capacitance, and temperature
25 Hz ODR, 100 nA/mA CTR sensors.
SPI and I2C communications supported
The ADPD4000/ADPD4001 are available in a 3.11 mm ×
256-byte FIFO
2.14 mm, 0.4 mm pitch, 33-ball WLCSP and 35-ball WLCSP.
APPLICATIONS
Wearable health and fitness monitors: heart rate monitors
(HRMs), heart rate variability (HRV), stress, blood pressure
estimation, SpO2, hydration, body composition
Industrial monitoring: CO, CO2, smoke, and aerosol detection
Home patient monitoring
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD1
LED4B ADPD4000/ADPD4001 DVDD2
LED3B IOVDD
LED2B LED LEVEL
AND
LED1B LED MUX CONTROL AGND
LED4A DRIVERS DGND
LED3A IOGND
LED2A HIGH
LED1A FREQUENCY CS
AND LOW SCLK
FREQUENCY
OSCILLATORS MOSI
LGND DIGITAL PROCESSING, MISO
INTEGRATOR INTERFACE AND
TIMING TIMING CONTROL, SCL
IN1 FIFO, PROGRAM AND SDA
CH 1 SIGNAL DATA REGISTERS,
IN2 CONDITIONING
IN3 COMMUNICATIONS GPIO0
ADC GPIO1
IN4
IN5 TIA_VREF GPIO2
IN6 GPIO3
IN7 CH 2 SIGNAL
IN8 CONDITIONING

INTEGRATOR VREF
TIMING VC1
VC1
VC2 VOLTAGE VREF
VC2 REFERENCES
TIA_VREF
NOTES
VICM
17335-001

1. CS, SCLK, MOSI, AND MISO PINS ARE ON THE ADPD4000.

2. SCL AND SDA PINS ARE ON THE ADPD4001.
3. TIA_VREF IS THE INTERNAL VOLTAGE REFERENCE SIGNAL FOR THE TRANSIMPEDANCE AMPLIFIER.
Figure 1.
Rev. A Document Feedback
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ADPD4000/ADPD4001 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Time Slot Operation .................................................................. 20
Applications ....................................................................................... 1 Execution Modes ........................................................................ 21
General Description ......................................................................... 1 Host Interface.............................................................................. 22
Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 25
Revision History ............................................................................... 2 Operating Mode Overview ....................................................... 25
Specifications..................................................................................... 3 Single Integration Mode ............................................................ 25
Temperature and Power Specifications ..................................... 3 Multiple Integration Mode ........................................................ 33
Performance Specifications ......................................................... 3 Digital Integration Mode........................................................... 34
Digital Specifications ................................................................... 5 TIA ADC Mode .......................................................................... 36
Timing Specifications .................................................................. 6 Register Map ................................................................................... 38
Absolute Maximum Ratings............................................................ 8 Register Details ............................................................................... 57
Thermal Resistance ...................................................................... 8 Global Configuration Registers ................................................ 57
Recommended Soldering Profile ............................................... 8 Interrupt Status and Control Registers .................................... 59
ESD Caution .................................................................................. 8 Threshold Setup and Control Registers .................................. 66
Pin Configurations and Function Descriptions ........................... 9 Clock and Timestamp Setup and Control Registers.............. 67
Typical Performance Characteristics ........................................... 13 System Registers ......................................................................... 68
Theory of Operation ...................................................................... 15 I/O Setup and Control Registers .............................................. 69
Introduction ................................................................................ 15 Time Slot Configuration Registers........................................... 72
Analog Signal Path ..................................................................... 15 AFE Timing Setup Registers ..................................................... 76
LED Drivers ................................................................................ 16 LED Control and Timing Registers ......................................... 78
Determining CVLED...................................................................... 17 ADC Offset Registers................................................................. 79
Datapath, Decimation, and FIFO ............................................. 17 Output Data Registers ............................................................... 79
Clocking ....................................................................................... 19 Outline Dimensions ....................................................................... 82
Time Stamp Operation .............................................................. 19 Ordering Guide .......................................................................... 82
Low Frequency Oscillator Calibration .................................... 20
High Frequency Oscillator Calibration ................................... 20

REVISION HISTORY
6/2019—Revision A: Initial Version

Rev. A | Page 2 of 82
Data Sheet ADPD4000/ADPD4001

SPECIFICATIONS
TEMPERATURE AND POWER SPECIFICATIONS
Table 1. Operating Conditions
Parameter Test Conditions/Comments Min Typ Max Unit
TEMPERATURE RANGE
Operating Range −40 +85 °C
Storage Range −65 +150 °C
POWER SUPPLY VOLTAGES
Supply Voltage, VDD Applied at the AVDD, DVDD1, and DVDD2 pins 1.7 1.8 1.9 V
Input/Output Driver Supply Voltage, IOVDD Applied at the IOVDD pin 1.7 1.8 3.6 V

AVDD = DVDD = IOVDD = 1.8 V, TA = 25°C, unless otherwise noted.

Table 2. Current Consumption

Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY (VDD) CURRENT
VDD Supply Current1 Signal-to-noise ratio (SNR) = 75 dB, 25 Hz output data rate 10 µA
(ODR), single time slot
Total System Power Combined LED and AFE power, continuous 50 μW
Dissipation photoplethysmography (PPG) measurement at 75 dB SNR,
25 Hz ODR, 100 nA/mA current transfer ratio (CTR)
Peak VDD Supply Current (1.8 V)
1-Channel Operation IVDD_PEAK Peak VDD current during time slot sampling 4.0 mA
Standby Mode Current IVDD_STANDBY 0.25 µA
LED VOLTAGE (VLED) SUPPLY
CURRENT2
Average Supply Current
VLEDA or VLEDB Peak LED current = 25 mA, LED pulse width = 3 µs
Per Pulse 25 Hz data rate 1.875 µA
100 Hz data rate 7.5 µA
1
VDD is the voltage applied at the AVDD and DVDD pins.
2
VLED applies to the external LED supply voltage for any given LED being driven by the ADPD4000/ADP4001 LED drivers under the listed conditions.
PERFORMANCE SPECIFICATIONS
AVDD = DVDD = IOVDD = 1.8 V, TA = full operating temperature range, unless otherwise noted.

Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
DATA ACQUISITION
Datapath Width 32 Bits
FIFO SIZE 256 Bytes
LED DRIVER
LED Peak Current per Driver LED pulse enabled 2 200 mA
LED Peak Current, Total Using multiple LED drivers simultaneously 400 mA
Driver Compliance Voltage For any LED driver output at ILED = 40 mA 200 mV
LED PERIOD AFE width = 4 µs1 10 µs
AFE width = 3 µs 8 µs
SAMPLING RATE2 Single time slot, four data bytes to FIFO, 2 µs LED pulse 0.004 9000 Hz
OSCILLATOR DRIFT
32 kHz Oscillator Percent variation from 25°C to 85°C 6 %
Percent variation from +25°C to −40°C −10 %
1 MHz Oscillator Percent variation from 25°C to 85°C 2 %
Percent variation from +25°C to −40°C −2 %

Rev. A | Page 3 of 82
ADPD4000/ADPD4001 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
32 MHz Oscillator Percent Variation from 25°C to 85°C 2 %
Percent Variation from +25°C to −40°C −2 %
1
Minimum LED period = (2 × AFE width) + 2 µs.
2
The maximum value in this specification is the internal ADC sampling rate using the internal 1 MHz state machine clock. The I2C and SPI read rates in some
configurations may limit the ODR.

Table 4.
Parameter Test Conditions/Comments Min Typ Max Unit
TRANSIMPEDANCE AMPLIFIER (TIA) GAIN 12.5 200 kΩ
PULSED SIGNAL CONVERSIONS, 3 μs LED 4 μs integration width, single integration mode
PULSE
ADC Resolution1 TIA feedback resistor
12.5 kΩ 6.2 nA/LSB
25 kΩ 3.1 nA/LSB
50 kΩ 1.5 nA/LSB
100 kΩ 0.77 nA/LSB
200 kΩ 0.38 nA/LSB
ADC Saturation Level2 TIA feedback resistor
12.5 kΩ 50 μA
25 kΩ 25 μA
50 kΩ 12.5 μA
100 kΩ 6.22 μA
200 kΩ 3.11 μA
PULSED SIGNAL CONVERSIONS, 2 μs LED 3 μs integration width, single integration mode
PULSE
ADC Resolution1 TIA feedback resistor
12.5 kΩ 8.2 nA/LSB
25 kΩ 4.1 nA/LSB
50 kΩ 2.04 nA/LSB
100 kΩ 1.02 nA/LSB
200 kΩ 0.51 nA/LSB
ADC Saturation Level2 TIA feedback resistor
12.5 kΩ 67 μA
25 kΩ 33 μA
50 kΩ 16.7 μA
100 kΩ 8.37 μA
200 kΩ 4.19 μA
FULL SIGNAL CONVERSIONS
TIA Linear Dynamic Range (per Total input current, 1% compression point, TIA_VREF = 1.265 V
Channel)
12.5 kΩ 72 μA
25 kΩ 38 μA
50 kΩ 18.7 μA
100 kΩ 9.3 μA
200 kΩ 4.6 μA
SYSTEM PERFORMANCE
Referred to Input Noise Single integration mode, single pulse, single channel, floating
input, TIA_VREF = 0.9 V, 4 μs integration time
12.5 kΩ TIA gain 6.8 nA rms
25 kΩ TIA gain 3.4 nA rms
50 kΩ TIA gain 1.6 nA rms
100 kΩ TIA gain 0.9 nA rms
200 kΩ TIA gain 0.5 nA rms

Rev. A | Page 4 of 82
Data Sheet ADPD4000/ADPD4001
Parameter Test Conditions/Comments Min Typ Max Unit
Referred to Input Noise Single integration mode; single pulse; single channel; 90%
full-scale input signal, no ambient light, TIA_VREF = 0.9 V,
VCx = TIA_VREF, 3 μs LED pulse, photodiode capacitance (CPD) =
70 pF, input resistor = 500 Ω
12.5 kΩ TIA gain 8.7 nA rms
25 kΩ TIA gain 4.3 nA rms
50 kΩ TIA gain 2.3 nA rms
100 kΩ TIA gain 1.3 nA rms
200 kΩ TIA gain 0.8 nA rms
SNR 12.5 kΩ TIA gain, single pulse 75 dB
25 kΩ TIA gain, single pulse 75 dB
50 kΩ TIA gain, single pulse 74 dB
100 kΩ TIA gain, single pulse 73 dB
200 kΩ TIA gain, single pulse 71 dB
200 kΩ TIA gain, 300 Hz output data rate, 16 pulses, CPD = 90 dB
70 pF, 0.5 Hz to 20 Hz bandwidth
AC Ambient Light Rejection DC to 1 kHz, linear range of TIA 60 dB
DC Power Supply Rejection Ratio (DC At 75% full scale input 25 dB
PSRR)
1
ADC resolution is listed per pulse. If using multiple pulses, divide by the number of pulses.
2
ADC saturation level applies to pulsed signal only, because ambient signal is rejected prior to ADC conversion.

DIGITAL SPECIFICATIONS
IOVDD = 1.7 V to 3.6 V, unless otherwise noted.

Table 5
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
LOGIC INPUTS
Input Voltage Level
SCL, SDA
High VIH 0.7 × IOVDD 3.6 V
Low VIL −0.3 +0.3 × IOVDD V
GPIOx, MISO, MOSI, SCLK, CS
High VIH 0.7 × IOVDD IOVDD + 0.3 V
Low VIL -0.3 0.3 × IOVDD V
Input Current Level All logic inputs
High IIH 10 µA
Low IIL −10 µA
Input Capacitance CIN 2 pF
LOGIC OUTPUTS
Output Voltage Level
GPIOx, MISO
High VOH 2 mA high level output current IOVDD − 0.5 V
Low VOL 2 mA low level output current 0.5 V
SDA
Low VOL1 3 mA low level output current 0.4 V
Output Current Level SDA
Low IOL VOL1 = 0.4 V 20 mA

Rev. A | Page 5 of 82
ADPD4000/ADPD4001 Data Sheet
TIMING SPECIFICATIONS
Table 6. I2C Timing Specifications
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
I2C PORT1 See Figure 2
SCL
Frequency 1 Mbps
Minimum Pulse Width
High t1 260 ns
Low t2 500 ns
Start Condition
Hold Time t3 260 ns
Setup Time t4 260 ns
SDA Setup Time t5 50 ns
SCL and SDA
Rise Time t6 120 ns
Fall Time t7 120 ns
Stop Condition
Setup Time t8 260 ns
1
Guaranteed by design.

Table 7. SPI Timing Specifications

Parameter Symbol Test Conditions/Comments Min Typ Max Unit
SPI PORT
SCLK
Frequency fSCLK 24 MHz
Minimum Pulse Width
High tSCLKPWH 15 ns
Low tSCLKPWL 15 ns
CS
Setup Time tCSS CS setup to SCLK rising edge 11 ns
Hold Time tCSH CS hold from SCLK rising edge 5 ns
Pulse Width High tCSPWH CS pulse width high 15 ns
MOSI
Setup Time tMOSIS MOSI setup to SCLK rising edge 5 ns
Hold Time tMOSIH MOSI hold from SCLK rising edge 5 ns
MISO Output Delay tMISOD MISO valid output delay from SCLK falling edge
Register 0x00B4 = 0x0050 (default) 21.0 ns
Register 0x00B4 = 0x005F (maximum slew rate, 14.0 ns
maximum drive strength for SPI)

Table 8. Timing Specifications for Provision of External Low Frequency Oscillator

Parameter Min Typ Max Unit
FREQUENCY
1 MHz Low Frequency Oscillator 500 2000 kHz
32 kHz Low Frequency Oscillator 10 100 kHz
DUTY CYCLE
1 MHz Low Frequency Oscillator 10 90 %
32 kHz Low Frequency Oscillator 10 90 %

Rev. A | Page 6 of 82
Data Sheet ADPD4000/ADPD4001
Timing Diagrams
t3 t5 t3

SDA

t6 t1

SCL

17335-002
t2 t7 t4 t8

Figure 2. I2C Timing Diagram

tCSH
tCSS
tCSPWH
tSCLKPWL
CS tSCLKPWH

SCLK

MOSI
tMOSIH
tMOSIS

MISO

17335-003
tMISOD

Figure 3. SPI Timing Diagram

Rev. A | Page 7 of 82
ADPD4000/ADPD4001 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 9. RECOMMENDED SOLDERING PROFILE
Parameter Rating Figure 4 and Table 11 provide details about the recommended
AVDD to AGND −0.3 V to +2.2 V soldering profile.
DVDD1, DVDD2 to DGND −0.3 V to +2.2 V
CRITICAL ZONE
tP
IOVDD to DGND −0.3 V to +3.9 V TP TL TO TP

GPIOx, MOSI, MISO, SCLK, CS, SCL, −0.3 V to +3.9 V RAMP-UP

SDA to DGND TL

TEMPERATURE
TSMAX tL
LEDxx to LGND −0.3 V to +3.6 V
Junction Temperature 150°C TSMIN

Electrostatic Discharge (ESD)

tS
Human Body Model (HBM) 2500 V PREHEAT RAMP-DOWN
Charged Device Model (CDM) 750 V
Machine Model (MM) 100 V

17335-004
t25°C TO PEAK
TIME
Stresses at or above those listed under Absolute Maximum Figure 4. Recommended Soldering Profile
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these Table 11. Recommended Soldering Profile
or any other conditions above those indicated in the operational Profile Feature Condition (Pb-Free)
section of this specification is not implied. Operation beyond Average Ramp Rate (TL to TP) 3°C/sec maximum
the maximum operating conditions for extended periods may Preheat
affect product reliability. Minimum Temperature (TSMIN) 150°C
Maximum Temperature (TSMAX) 200°C
THERMAL RESISTANCE Time (TSMIN to TSMAX) (tS) 60 sec to 180 sec
Thermal performance is directly linked to printed circuit board TSMAX to TL Ramp-Up Rate 3°C/sec maximum
(PCB) design and operating environment. Close attention to Time Maintained Above Liquidus
PCB thermal design is required. Temperature
θJA is the natural convection junction to ambient thermal Liquidus Temperature (TL) 217°C
resistance measured in a one cubic foot sealed enclosure. θJC is Time (tL) 60 sec to 150 sec
the junction to case thermal resistance. Peak Temperature (TP) +260 (+0/−5)°C
Time Within 5°C of Actual Peak <30 sec
Table 10. Thermal Resistance Temperature (tP)
Package Type θJA θJC Unit Ramp-Down Rate 6°C/sec maximum
CP-35-21 41.89 0.98 °C/W Time from 25°C to Peak Temperature 8 minutes maximum
CB-33-11 42.15 0.98 °C/W
ESD CAUTION
1
The thermal resistance values are defined as per the JESD51-12 standard.

Rev. A | Page 8 of 82
Data Sheet ADPD4000/ADPD4001

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

ADPD4000
BOTTOM VIEW, BALL SIDE UP
(Not to Scale)
5 4 3 2 1

A LED1A LED2A LED3A LED4A LED4B

B LGND LED1B LED2B LED3B GPIO2

C GPIO0 GPIO1 GPIO3 SCLK MISO

D AVDD DVDD2 IOVDD CS MOSI

E VREF AGND IOGND DGND DVDD1

F VC1 IN1 IN3 IN5 IN7

IN6 IN8

17335-005
G VC2 IN2 IN4

Figure 5. ADPD4000 Pin Configuration

Table 12. ADPD4000 Pin Function Descriptions

Pin No. Mnemonic Type1 Description
A5 LED1A AO LED Driver 1A Current Sink. If not in use, leave this pin floating.
A4 LED2A AO LED Driver 2A Current Sink. If not in use, leave this pin floating.
A3 LED3A AO LED Driver 3A Current Sink. If not in use, leave this pin floating.
A2 LED4A AO LED Driver 4A Current Sink. If not in use, leave this pin floating.
A1 LED4B AO LED Driver 4B Current Sink. If not in use, leave this pin floating.
B5 LGND S LED Driver Ground.
B4 LED1B AO LED Driver 1B Current Sink. If not in use, leave this pin floating.
B3 LED2B AO LED Driver 2B Current Sink. If not in use, leave this pin floating.
B2 LED3B AO LED Driver 3B Current Sink. If not in use, leave this pin floating.
B1 GPIO2 DIO General-Purpose I/O 2. This pin is used for interrupts and various clocking options.
C5 GPIO0 DIO General-Purpose I/O 0. This pin is used for interrupts and various clocking options.
C4 GPIO1 DIO General-Purpose I/O 1. This pin is used for interrupts and various clocking options.
C3 GPIO3 DIO General-Purpose I/O 3. This pin is used for interrupts and various clocking options.
C2 SCLK DI SPI Clock Input
C1 MISO DO SPI Master Input/Slave Output.
D5 AVDD S 1.8 V Analog Supply.
D4 DVDD2 S 1.8 V Digital Supply.
D3 IOVDD S 1.8 V/3.3 V I/O Driver Supply.
D2 CS DI SPI Chip Select Input.
D1 MOSI DI SPI Master Output/Slave Input.
E5 VREF REF Internally Generated ADC Voltage Reference. Buffer this pin with a 1 µF capacitor to AGND.
E4 AGND S Analog Ground.
E3 IOGND S I/O Driver Ground.
E2 DGND S Digital Ground.
E1 DVDD1 S 1.8 V Digital Supply.
F5 VC1 AO Output Voltage Source 1 for Photodiode Common Cathode Bias or Other Sensor Stimulus.
F4 IN1 AI Current Input 1. If not in use, leave this pin floating.
F3 IN3 AI Current Input 3. If not in use, leave this pin floating.
Rev. A | Page 9 of 82
ADPD4000/ADPD4001 Data Sheet
Pin No. Mnemonic Type1 Description
F2 IN5 AI Current Input 5. If not in use, leave this pin floating.
F1 IN7 AI Current Input 7. If not in use, leave this pin floating.
G5 VC2 AO Output Voltage Source 2 for Photodiode Common Cathode Bias or Other Sensor Stimulus.
G4 IN2 AI Current Input 2. If not in use, leave this pin floating.
G3 IN4 AI Current Input 4. If not in use, leave this pin floating.
G2 IN6 AI Current Input 6. If not in use, leave this pin floating.
G1 IN8 AI Current Input 8. If not in use, leave this pin floating.
1
AO means analog output, S means supply, DIO means digital input/output, DI means digital input, DO means digital output, REF means voltage reference, and AI
means analog input.

Rev. A | Page 10 of 82
Data Sheet ADPD4000/ADPD4001
ADPD4001
BOTTOM VIEW, BALL SIDE UP
(Not to Scale)
5 4 3 2 1

A LED1A LED2A LED3A LED4A LED4B

B LGND LED1B LED2B LED3B GPIO2

C GPIO0 GPIO1 GPIO3 SDA SCL

D AVDD DVDD2 IOVDD

E VREF AGND IOGND DGND DVDD1

F VC1 IN1 IN3 IN5 IN7

IN6 IN8

17335-006
G VC2 IN2 IN4

Figure 6. ADPD4001 Pin Configuration

Table 13. ADPD4001 Pin Function Descriptions

Pin No. Mnemonic Type1 Description
A5 LED1A AO LED Driver 1A Current Sink. If not in use, leave this pin floating.
A4 LED2A AO LED Driver 2A Current Sink. If not in use, leave this pin floating.
A3 LED3A AO LED Driver 3A Current Sink. If not in use, leave this pin floating.
A2 LED4A AO LED Driver 4A Current Sink. If not in use, leave this pin floating.
A1 LED4B AO LED Driver 4B Current Sink. If not in use, leave this pin floating.
B5 LGND S LED Driver Ground.
B4 LED1B AO LED Driver 1B Current Sink. If not in use, leave this pin floating.
B3 LED2B AO LED Driver 2B Current Sink. If not in use, leave this pin floating.
B2 LED3B AO LED Driver 3B Current Sink. If not in use, leave this pin floating.
B1 GPIO2 DIO General-Purpose I/O 2. This pin is used for interrupts and various clocking options.
C5 GPIO0 DIO General-Purpose I/O 0. This pin is used for interrupts and various clocking options.
C4 GPIO1 DIO General-Purpose I/O 1. This pin is used for interrupts and various clocking options.
C3 GPIO3 DIO General-Purpose I/O 3. This pin is used for interrupts and various clocking options.
C2 SDA DIO I2C Data Input/Output.
C1 SCL DI I2C Clock Input.
D5 AVDD S 1.8 V Analog Supply.
D4 DVDD2 S 1.8 V Digital Supply.
D3 IOVDD S 1.8 V/3.3 V I/O Driver Supply.
E5 VREF REF Internally Generated ADC Voltage Reference. Buffer this pin with a 1 µF capacitor to AGND.
E4 AGND S Analog Ground.
E3 IOGND S I/O Driver Ground.
E2 DGND S Digital Ground.
E1 DVDD1 S 1.8 V Digital Supply.
F5 VC1 AO Output Voltage Source 1 for Photodiode Common Cathode Bias or Other Sensor Stimulus.
F4 IN1 AI Current Input 1. If not in use, leave this pin floating.
F3 IN3 AI Current Input 3. If not in use, leave this pin floating.
F2 IN5 AI Current Input 5. If not in use, leave this pin floating.
F1 IN7 AI Current Input 7. If not in use, leave this pin floating.
G5 VC2 AO Output Voltage Source 2 for Photodiode Common Cathode Bias or Other Sensor Stimulus.
G4 IN2 AI Current Input 2. If not in use, leave this pin floating.
Rev. A | Page 11 of 82
ADPD4000/ADPD4001 Data Sheet
Pin No. Mnemonic Type1 Description
G3 IN4 AI Current Input 4. If not in use, leave this pin floating.
G2 IN6 AI Current Input 6. If not in use, leave this pin floating.
G1 IN8 AI Current Input 8. If not in use, leave this pin floating.
1
AO means analog output, S means supply, DIO means digital input/output, DIO means digital input, REF means voltage reference, and AI means analog input.

Rev. A | Page 12 of 82
Data Sheet ADPD4000/ADPD4001

TYPICAL PERFORMANCE CHARACTERISTICS

250 90
DRIVE SETTING 0x7F = 200mA
DRIVE SETTING 0x36 = 80mA
DRIVE SETTING 0xF = 16mA 88
200
LED DRIVER CURRENT (mA)

86

84
150

SNR (dB)
82

100
80

78
50
76 200kΩ GAIN
100kΩ GAIN
50kΩ GAIN
0 74

17335-007

17335-011
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1 10 100
LED DRIVER VOLTAGE (V) NUMBER OF PULSES

Figure 7. LED Driver Current vs. LED Driver Voltage at 16 mA, 80 mA, and Figure 10. SNR vs. Number of Pulses, CPD = 70 pF
200 mA
0 10

REFERRED TO INPUT NOISE (nA rms)

–10
8

7
–20
AC PSRR (dB)

–30 5

4
–40
3

2 12.5kΩ GAIN
–50 25kΩ GAIN
50kΩ GAIN
1 100kΩ GAIN
200kΩ GAIN
–60 0
17335-008

17335-012
1 10 100 1k 10k 100k 1M 10M 0 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (Hz) INPUT CAPACITANCE (pF)

Figure 8. AC PSRR vs. Frequency Figure 11. Referred to Input Noise vs. Input Capacitance

9 0

8
REFERRED TO INPUT NOISE (nA rms)

–10
AMBIENT LIGHT REJECTION (dB)

6 –20

5
–30
4

3 –40

2
–50
1

0 –60
17335-010

17335-013

0 50 100 150 200 1 10 100 1k 10k 100k

TIA GAIN (kΩ) FREQUENCY (Hz)

Figure 9. Referred to Input Noise vs. TIA Gain Figure 12. Ambient Light Rejection vs. Frequency

Rev. A | Page 13 of 82
 NUMBER OF DEVICES NUMBER OF DEVICES

10
20
30
40
50
60
70
10
15
20
25
30

0
0
5
0.80 25.0
0.82 25.5
0.84 26.0
0.86 26.5
0.88 27.0
0.90 27.5
0.92 28.0
0.94 28.5
0.96 29.0
0.98 29.5
1.00 30.0
ADPD4000/ADPD4001

1.02 30.5
1.04 31.0
1.06 31.5

FREQUENCY (kHz)

FREQUENCY (MHz)
1.08 32.0
1.10 32.5
1.12 33.0
1.14 33.5
1.16 34.0
1.18 34.5
1.20 35.0

Figure 14. 1 MHz Clock Frequency Distribution, Untrimmed

Figure 13. 32 kHz Clock Frequency Distribution, Untrimmed
MORE MORE
17335-015 17335-014

Rev. A | Page 14 of 82
NUMBER OF DEVICES
10
15
20
25
30
35
40
45

0
5

28.0
28.5
29.0
29.5
30.0
30.5
31.0
31.5
32.0
32.5
33.0
33.5
34.0
34.5
FREQUENCY (MHz)

35.0
35.5
36.0
36.5
37.0
37.5
38.0
Figure 15. 32 MHz Clock Frequency Distribution, Untrimmed

MORE
17335-016
Data Sheet
Data Sheet ADPD4000/ADPD4001

THEORY OF OPERATION
INTRODUCTION that require instantaneous sampling of two sensors. Each
The ADPD4000/ADPD4001 operate as a complete multimodal channel contains a TIA with programmable gain, a BPF with a
sensor front end, stimulating up to eight LEDs and measuring high-pass corner at 100 kHz and a low-pass cutoff frequency of
the return signal on up to eight separate current inputs. Twelve 390 kHz, and an integrator capable of integrating ±7.5 pC per
time slots are available, enabling 12 separate measurements per sample. Each channel is time multiplexed into a 14-bit ADC. In
sampling period. The analog inputs can be driven single-ended Figure 16, RF is the TIA feedback resistor, and RINT is the series
or in differential pairs. The eight analog inputs are multiplexed resistor to the input of the integrator.
6.3pF
into a single channel or two independent channels, enabling RF
RINT
simultaneous sampling of two sensors. IN1

IN2 TIA BPF

The analog front end (AFE) consists of a TIA, band-pass filter IN3 RINT
(BPF), integrator, and analog-to-digital converter (ADC). The IN4 RF 6.3pF
digital block provides multiple operating modes, programmable IN5 RF 6.3pF
ADC

timing, four general-purpose input/output (GPIO) pins, block IN6

RINT

averaging, and a selectable second- through fourth-order IN7 TIA BPF

cascaded integrator comb (CIC) filter. Eight independent LED IN8 RINT

17335-020
drivers are provided that can each drive up to 200 mA. Four LED RF 6.3pF
drivers can be enabled in any time slot and can be programmed
Figure 16. Analog Signal Path Block Diagram
from 2 mA to 200 mA monotonically, with a 7-bit register
setting. The LED drivers enabled in any time slot can provide a Analog Input Multiplexer
total combined maximum of 400 mA of LED current. The ADPD4000/ADPD4001 support eight analog input pins.
The core circuitry provides stimulus to the sensors connected to Each input can be used as a single-ended input or as part of a
the inputs of the device and measures the response, storing the differential pair. Figure 17 shows a single representation of the
results in discrete data locations. The eight inputs can drive two input switch matrix, which allows programmable connection to
simultaneous input channels, either in a single-ended or differen- the two AFE channels. Each pair of inputs has an exact duplicate of
tial configuration. Data is read directly by a register or through this multiplexer: IN1 and IN2, IN3 and IN4, IN5 and IN6, and
a first in, first out (FIFO) method. This highly integrated system IN7 and IN8. The connections are programmable per time slot.
includes an analog signal processing block, digital signal pro-
TIA_VREF

cessing block, an I2C communication interface on the ADPD4001

VICM
VC1
VC2

or an SPI port on the ADPD4000, programmable pulsed LED

current sources, and pulsed voltage sources for sensors that
require voltage excitation.
When making optical measurements, the ADPD4000/ADPD4001 IN1

provide 60 dB of ambient light rejection using a synchronous

TIA_VREF

TIA

modulation scheme with pulses as short as 1 µs combined with

VICM
VC1
VC2

a BPF. Ambient light rejection is automatic without the need of

external control loops, dc current subtraction, or digital
algorithms.
IN2 TIA_VREF
The LED driver is a current sink and is independent from the LED
supply voltage and the LED type. The inputs can be connected
to any sensor that provides currents up to 200 µA. The
ADPD4000/ADPD4001 can also interface with voltage output TIA
sensors with a series resistor placed between the sensor output and
the ADPD4000/ADPD4001 inputs to convert the voltage to a THERE ARE FOUR
current. The ADPD4000/ADPD4001 produce a high SNR for COPIES OF SWITCH MATRIX.
ONE COPY FOR EACH
relatively low LED power while greatly reducing the effect of INPUT PAIR.
17335-021

ambient light on the measured signal. TIA_VREF

ANALOG SIGNAL PATH Figure 17. Analog Input Multiplexer

The ADPD4000/ADPD4001 analog signal path consists of eight The PAIR12, PAIR34, PAIR56, and PAIR78 registers select
current inputs that can be configured as single-ended or whether the matching input pair is used as two single-ended
differential pairs into one of two independent channels. The inputs or as a differential pair. This selection is valid for all
two channels can be sampled simultaneously for applications active time slots. The INP12_x, INP34_x, INP56_x, and
Rev. A | Page 15 of 82
ADPD4000/ADPD4001 Data Sheet
INP78_x bit fields specify whether the input pair is enabled certain circumstances, causes the device to cease proper
during the corresponding time slot and, if enabled, which input operation. The voltage of the LED driver output pins must not
is connected to which AFE channel. be confused with the supply voltages for the LED themselves.
The sleep conditions are used for any inputs that are not enabled. VLEDx is the voltage applied to the anode of the external LED
Sleep conditions are determined by the INP_SLEEP_12, whereas the LED output driver pin is connected to the cathode
INP_SLEEP_34, INP_SLEEP_56, and INP_SLEEP_78 bit fields, of the external LED. The compliance voltage, measured at the
which specify the state for the input pairs during sleep and driver pin with respect to ground, required to maintain the
when the inputs are not active. Inputs are only considered active programmed LED current level is a function of the current
during the precondition and pulse regions for time slots where required. Figure 7 shows the typical compliance voltages
they are enabled. required at various LED current settings.

Preconditioning of the sensor connected to the input is provided to Either side of each LED driver output pair, but not both, can be
set the operating point at the input just prior to sampling. There driven in any of the 12 available time slots. Up to four LED
are several different options for preconditioning determined by driver outputs can be enabled in any time slot using the LED_
the PRECON_x bit field. A PRECON_x bit field is provided for DRIVESIDE1_x, LED_DRIVESIDE2_x, LED_DRIVESIDE3_x,
each time slot to specify the precondition for enabled inputs or and LED_DRIVESIDE4_x bit fields. The current is set on a per
input pairs during the corresponding time slot. Preconditioning driver, per time slot basis using the LED_CURRENT1_x, LED_
options include: float the input(s), VC1, VC2, input common- CURRENT2_x, LED_CURRENT3_x, and LED_CURRENT4_x
mode voltage (VICM), TIA_VREF, TIA input, and short the input bit fields. Each driver can be programmed from 2 mA to 200 mA
pair. The preconditioning time at the start of each time slot is with a monotonic 7-bit setting, as shown in Figure 19. Setting 1
programmable using the PRE_WIDTH_x bit field. The default through Setting 15 each increases the LED drive current by ~1 mA.
preconditioning period is 8 μs. Setting 16 through Setting 127 each increases the LED drive
current by ~2 mA. Setting LED_CURRENTx_x = 0 disables
Second AFE Channel that particular driver.
The second AFE channel is disabled by default. When disabled,
Although each driver can be programmed to 200 mA and up to
the three amplifiers (TIA, BPF, and integrator) are automatically
four LED drivers can be enabled in any time slot, there is a
powered down, and no ADC cycles occur for the second
limitation of a total of 400 mA of combined LED driver current
channel. Digital integration and impulse response mode do not
that can be provided in any time slot. It is up to the user to
use the second channel.
program the LED drivers such that this 400 mA limit is not
The second AFE channel can be enabled with the CH2_EN_x exceeded. If the 400 mA limit is exceeded by the user settings,
bit fields on a per time slot basis. When the second channel is priority is given, in the following order, to LED1x, LED2x,
enabled, ADC conversions and the datapath bit fields of the LED3x, and LED4x. For example, if the user settings have
second channel operate. When data is being written to the LED1A set to 150 mA, LED2B set to 150 mA, and LED3A set to
FIFO, the Channel 2 data is written after the Channel 1 data. 150 mA in a single time slot, LED1A and LED2B both provide
LED DRIVERS 150 mA. However, LED3A is limited to 100 mA to maintain the
400 mA total LED drive current limit for the device.
The ADPD4000/ADPD4001 have four LED drivers, each of
which is brought out to two LED driver outputs providing a 200
total of eight LED output drivers. The device can drive up to four
LEDs simultaneously, one from each driver pair. The LED output
LED DRIVE CURRENT (mA)

driver is a current sink. Figure 18 shows an example of a single 150

LED driver output pair.

VLED1
100
VLED2
CVLED
LEDxA
CVLED 50
LEDxB
LED_CURRENTx_x

0
17335-022

17335-023

0 20 40 60 80 100 120
LED_DRIVESIDEx_x
LED_CURRENTx_x SETTINGS (Decimal)
Figure 18. Block Diagram of LED Driver Output Pair Figure 19. LED Drive Current vs. LED_CURRENTx_x Setting
The LED driver output pins, LED1A, LED1B, LED2A, LED2B,
LED3A, LED3B, LED4A, and LED4B, have an absolute
maximum voltage rating of 3.6 V. Any voltage exposure over
this rating affects the reliability of the device operation and, in
Rev. A | Page 16 of 82
Data Sheet ADPD4000/ADPD4001
DETERMINING CVLED CVLED = (3 × 10−6 × 0.125)/(4.5 – (3.5 + 0.6)) = 1 µF (2)
To determine the CVLED capacitor value, determine the As shown in Equation 2, as the minimum supply voltage drops
maximum forward-biased voltage, VFB_LED_MAX, of the LED in close to the maximum anode voltage, the demands on CVLED
operation. The LED current, ILED_MAX, converts to VFB_LED_MAX as become more stringent, forcing the capacitor value higher. It is
shown in Figure 20. In this example, 125 mA of current through important to insert the correct values into Equation 2. For
two green LEDs in parallel yields VFB_LED_MAX = 3.5 V. Any series example, using an average value for VLED_MIN instead of the
resistance in the LED path must also be included in this voltage. worst case value for VLED_MIN can cause a serious design
When designing the LED path, keep in mind that small deficiency, resulting in a CVLED value that is too small causing
resistances can add up to large voltage drops due to the LED insufficient optical power in the application.
peak current being large. In addition, these resistances can be Additionally, multiple pulses can cause further droop on the
unnecessary constraints on the VLEDx supply. VLEDx supply if the CVLED capacitor is not fully recharged
4.5
TWO 528nm LEDs between pulses. Therefore, adding a sufficient margin on CVLED
ONE 850nm LED
is strongly recommended. Add additional margin to CVLED to
LED FORWARD BIAS VOLTAGE DROP (V)

4.0
account for multiple pulses and derating of the capacitor value
3.5 over voltage, bias, temperature, and other factors over the life of
the component.
3.0
DATAPATH, DECIMATION, AND FIFO
2.5
ADC samples are gathered for each pulse in each time slot and
combine to create a running positive and negative sum for each
2.0
time slot. These sums are each kept as a 32-bit unsigned value
1.5 register and saturate if the values overflow 32 bits. Each ADC
sample is added to either the positive or negative sum based on
1.0 the SUBTRACT_x bit for the current pulse in standard sampling
17335-051

0 50 100 150 200 250

LED DRIVER CURRENT SETTING (mA) mode, or in the lit or dark acquisition regions for digital
Figure 20. Example of the Average LED Forward Bias Voltage Drop as a integration mode. In impulse mode, the positive sum is used to
Function of the LED Driver Current Setting add two values and the result is written directly to the FIFO.
To correctly size the CVLED capacitor, do not deplete it during the Figure 21 shows the datapath structure.
pulse of the LED to the point where the voltage on the capacitor At the end of the pulse operations in each time slot, the signal
is less than the forward bias on the LED. Calculate the minimum value is calculated by subtracting the negative accumulator
value for CVLED as follows: from the positive accumulator. The signal and dark values are
t LED_PULSE × I LED_MAX then clipped to positive numbers and are processed by the
CVLED = (1) decimation unit. If the decimated value is ready, the data
VLED_MIN − (VFB_LED_MAX + 0.6 )
registers update, and the selected values are written to the FIFO.
where: The data interrupt for that time slot is also set at this time.
tLED_PULSE is the LED pulse width. The DECIMATE_FACTOR_x bit field determines the number
ILED_MAX is the maximum forward-biased current on the LED of time slot values used to create a 32-bit final sample value at a
used in operating the devices. rate of
VLED_MIN is the lowest voltage from the VLEDx supply with no load.
VFB_LED_MAX is the maximum forward-biased voltage required on Sample Rate =
the LED to achieve ILED_MAX. (1/TIMESLOT_PERIOD_x)/(DECIMATE_FACTOR_x + 1)

The numerator of Equation 1 sets up the total discharge amount If DECIMATE_FACTOR_x is 0, the output sample rate equals
in coulombs from the bypass capacitor to satisfy a single pro- the time slot rate. The final value is the sum of the decimated
grammed LED pulse of the maximum current. The denominator samples. There is no divide by (DECIMATE_FACTOR_x + 1)
represents the difference between the lowest voltage from the operation performed on the decimated data, but final data
VLEDx supply and the LED required voltage. The LED required values can be bit shifted to the right before being written to the
voltage is the voltage of the anode of the LED such that the compli- FIFO, creating a direct average when the number of samples is a
ance of the LED driver and the forward-biased voltage of the power of 2. DECIMATE_TYPE_x selects the method of
LED operating at the maximum current is satisfied. At a 125 mA decimation used. A setting of 0 selects a simple block sum with
drive current, the compliance voltage of the driver is 0.6 V. For a other settings allowing higher order CIC filters up to fourth
typical ADPD4000/ADPD4001 example, assume that the lowest order. If using higher order CIC filters for the signal data, the
dark data still uses the simple block sum at the same decimation
value for the VLEDx supply is 4.5 V and that the peak current is
125 mA for two 528 nm LEDs in parallel. The minimum value rate. Each time slot maintains its own block sum or CIC filter
for CVLED is then equal to 1 µF.
Rev. A | Page 17 of 82
ADPD4000/ADPD4001 Data Sheet
state. The entire decimation path uses a 32-bit datapath. It is up DARK_SIZE_x and SIGNAL_SIZE_x bit fields select the number
to the user to ensure that there is no undesired overflow. of bytes of each field to be written from 0 bytes to 4 bytes. When
Final data results can be read from data registers or a 256-byte set to 0, no data is written for that data type. If there are any
data FIFO. Data written to the FIFO is configurable to allow the nonzero bits at more significant bit positions than those
different data registers, formats, and data sizes as required. All selected, the data written to the FIFO is saturated. If both
time slots that write data to the FIFO must use the same output channels are enabled, all selected Channel 1 data values are
data rate by using the same decimation rate. Data from time slots written to the FIFO first, followed by the Channel 2 data.
operating at different output data rates than that which is being For example, in modes that utilize dark data, the eight upper
written to the FIFO must be read from the corresponding data bits of the dark data can be stored with 24 appropriately selected
register. bits from the signal data for each time slot to allow detection of
At the end of each time slot or decimation period, the selected whether the ambient light is becoming large, while limiting the
data is written to the FIFO as a packet. This packet can include size of the amount of data transferred.
0, 8-, 16-, 24-, or 32-bit data for each of the dark data and signal The FIFO is never written with partial packets of data. This
data values. The bit alignment of the data written to the FIFO is means that if there is not enough room for all of the data that is
selectable with a shift of 0 bits to 31 bits, with saturation to be written to the FIFO for all enabled time slots and any
provided. Lower bits are ignored. The DARK_SHIFT_x and selected status bytes, no data is written from any of the time
SIGNAL_SHIFT_x bit fields select the number of bits to shift slots during that period and the INT_FIFO_OFLOW status bit
the output data to the right before writing to the FIFO. The is set.

ADC
(14 BITS UNSIGNED) CHx_ADC_ADJUST

+ –

15 BITS SIGNED

ACCORDING TO
SUBTRACT OR DIGITAL
INTEGRATION REGION

POSITIVE ACCUMULATION NEGATIVE ACCUMULATION

32 BITS SIGNED 32 BITS SIGNED

+ –
CLIP
ADD 2048 IF
ZERO_ADJUST_x = 1

CLIP

PER CHANNEL
SIGNAL AND PER TIMESLOT DARK

DECIMATION

SIGNAL DATA DARK DATA

32 BITS UNSIGNED 32 BITS UNSIGNED
17335-024

DATA REGISTERS

Figure 21. Datapath Block Diagram

Rev. A | Page 18 of 82
Data Sheet ADPD4000/ADPD4001
The order of samples written to the FIFO (if selected) is dark The low frequency oscillator can be driven directly from an
data followed by signal data. The byte order for multibyte words external source provided on a GPIO input. To enable an
is shown in Table 14. external low frequency clock, use the following writes. Enable
one of the GPIO inputs using the GPIO_PIN_CFGx bit fields.
Table 14. Byte Order for FIFO Writes Next, use the ALT_CLK_GPIO bit field to choose the enabled
Size Byte Order (After Shift) GPIO input to be used for the external low frequency oscillator.
8 [7:0] Set the ALT_CLOCKS bit field to 0x1 to select an external low
16 [15:8], [7:0] frequency oscillator. Finally, use the LFOSC_SEL bit to match
24 [15:8], [7:0], [23:16] whether a 32 kHz or 1 MHz clock is being provided.
32 [15:8], [7:0], [31:24], [23:16]
In a third method, an external 32 MHz clock is used for both
The FIFO size is 256 bytes. When the FIFO is empty, a read opera- the high frequency clock and to be divided down to generate
tion returns 0xFF and the INT_FIFO_UFLOW status bit is set. the low frequency clock. To use this method, follow the
In addition to the FIFO, the signal and dark 32-bit registers can previous instructions for an external low frequency clock but
be directly read. These registers are effectively two-stage registers set the ALT_CLOCKS bit field to 0x3, and use the LFOSC_SEL
where there is an internal data register that updates with every bit to determine if a divide by 32 or 1000 is used to generate the
sample and a latched output data register that is accessed by the low frequency clock so that either a 32 kHz or 1 MHz clock is
host. The data interrupts can be used to align the access of these generated from the external 32 MHz clock.
registers to just after the registers are written. If using the interrupt High Frequency Oscillator
timing is troublesome, use the HOLD_REGS_x bit field to prevent
A 32 MHz high frequency oscillator is generated internally or
update of the output registers during an access not aligned to
can be provided externally. This high frequency clock clocks the
the interrupt. Setting the HOLD_REGS_x bit field blocks the
high speed state machine, which controls the AFE operations
update of the latched output data register and ensures that the
during the time slots, such as LED timing and integration times.
dark and signal values read by the host are from the same sample
point. If additional samples occur while the HOLD_REGS_x bit The high frequency oscillator can be internally generated by setting
field is set, the samples are written to the internal data register the ALT_CLOCKS bit field to 0x0 or 0x1. When selected, the
but not latched into the output data register that is accessed by internal 32 MHz oscillator is enabled automatically by the low
the host. Setting the HOLD_REGS_x bit field to 0 reenables the speed state machine during the appropriate wake-up time or
pass through of new data. during the 32 MHz oscillator calibration routine.
After all time slots have completed, the optional status bytes are The high frequency oscillator can also be driven from an
written to the FIFO. See the Optional Status Bytes section for external source. To provide an external 32 MHz high frequency
more information. oscillator, enable one of the GPIO inputs using the GPIO_PIN_
CFGx bit fields. Then, use the ALT_CLK_GPIO bit field to
CLOCKING choose the enabled GPIO input for the external high frequency
Low Frequency Oscillator oscillator. Finally, write 0x2 or 0x3 to the ALT_CLOCKS bit
A low frequency oscillator clocks the low speed state machine, field to select an external high frequency oscillator. Writing 0x2
which sets the time base used to control the sample timing, provides only the high frequency oscillator from the external
wake-up states, and overall operation. There are three options source, whereas writing 0x3 generates both the low frequency
for low frequency oscillator generation. The first option is an oscillator and high frequency oscillator from the external
internal, selectable 32 kHz or 1 MHz oscillator. The second 32 MHz source. When using an external 32 MHz oscillator, it
option is for the host to provide an low frequency oscillator must be kept running continuously for proper device operation.
externally. Finally, the low frequency oscillator can be generated TIME STAMP OPERATION
by a divide by 32 or divide by 1000 of an external high frequency
The time stamp feature is useful for calibration of the low fre-
clock source at 32 MHz. When powering up the device, it is
quency oscillator as well as providing the host with timing
expected that the low frequency oscillator is enabled and left
information during time slot operation. Timestamping is sup-
running continuously.
ported by the use of any GPIO as a time stamp request input,
To operate with the on-chip low frequency oscillator, use the the CAPTURE_TIMESTAMP bit to enable capture of the time
following writes. Set the LFOSC_SEL bit to 0 to select the stamp trigger, a time counter running in the low frequency
32 kHz clock or 1 if the 1 MHz clock is desired. Then, set either oscillator domain, and two output registers. The output bit fields
the OSC_1M_EN or OSC_32K_EN bit to 1 to turn on the include TIMESTAMP_COUNT_x, which holds the count of low
desired internal oscillator. The internal 32 kHz clock frequency frequency oscillator cycles between time stamp triggers, and
is set using the 6-bit OSC_32K_ADJUST bit field. The internal TIMESTAMP_SLOT_DELTA, which holds the number of low
1 MHz clock frequency is set using the 10-bit OSC_1M_FREQ_ frequency oscillator cycles remaining to the next time slot start.
ADJUST bit field.

Rev. A | Page 19 of 82
ADPD4000/ADPD4001 Data Sheet
The setup for using the time stamp operation is as follows: frequency oscillator cycles to the actual time stamp trigger
1. Configure a GPIO to support the time stamp input using period and adjust the OSC_32K_ADJUST or OSC_1M_FREQ_
the appropriate GPIO_PIN_CFGx bit field. Select the ADJ value accordingly.
matching GPIO to provide the time stamp using the HIGH FREQUENCY OSCILLATOR CALIBRATION
TIMESTAMP_GPIO bit field. The high frequency oscillator is calibrated by comparing
2. Configure the ADPD4000/ADPD4001 for operation and multiples of its cycles with multiple cycles of the low frequency
enable the low frequency oscillator. oscillator, which is calibrated to the system time. Calibration of
3. If the TIMESTAMP_SLOT_DELTA function is desired, the low frequency oscillator precedes calibration of the high
start time slot operation by placing the device in go mode frequency oscillator. The method for calibrating the high
using the OP_MODE bit (see Table 15). For low frequency frequency oscillator is as follows:
oscillator calibration, it is only required that the low
frequency oscillator be enabled. The device does not have 1. Write 1 to the OSC_32M_CAL_START bit.
to be in go mode for low frequency oscillator calibration. 2. The ADPD4000/ADPD4001 automatically power up the
high frequency oscillator.
Use the following procedure to capture the time stamp: 3. The device automatically waits for the high frequency
1. Set the CAPTURE_TIMESTAMP register bit to 1 to enable oscillator to be stable.
capture of the time stamp on the next rising edge on the 4. An internal counter automatically counts the number of
selected GPIO input. 32 MHz high frequency oscillations that occur during
2. The host provides the initial time stamp trigger on the 128 cycles of the 1 MHz low frequency oscillator or
selected GPIO at an appropriate time. 32 cycles of the 32 kHz low frequency oscillator, depending
3. The CAPTURE_TIMESTAMP bit is cleared when the on which low frequency oscillator is enabled based on the
time stamp signal is captured unless the TIMESTAMP_ setting of LFOSC_SEL.
ALWAYS_EN bit is set, in which case, the capture of the 5. The OSC_32M_CAL_COUNT bit field is updated with the
time stamp is always enabled. Reenable the capture if final count.
necessary. 6. The 32 MHz oscillator automatically powers down
4. The host provides a subsequent time stamp trigger on the following calibration unless time slots are active.
selected GPIO at an appropriate time. 7. The device resets the OSC_32M_CAL_START bit
5. The number of low frequency oscillator cycles that indicating the count has been updated.
occurred between time stamp triggers can now be read The OSC32M_FREQ_ADJ bit field adjusts the frequency of the
from the TIMESTAMP_COUNT_x bit fields. 32 MHz oscillator to the desired frequency. When using an external
The host must continue to handle the FIFO and/or data register low frequency oscillator, the 32 MHz oscillator calibration is per-
data normally during time stamp processing. formed with respect to the externally provided low frequency
oscillator.
If using a dedicated pin for a time stamp that does not have
transitions other than the time stamp, set the TIMESTAMP_ TIME SLOT OPERATION
ALWAYS_EN bit to avoid automatic clearing of the CAPTURE_ Operation of the ADPD4000/ADPD4001 is controlled by an
TIMESTAMP bit. This setting removes the need to enable the internal configurable controller that generates all the timing
time stamp capture each time. needed to generate sampling regions and sleep periods.
The time stamp can calibrate the low frequency oscillator as Measurements of multiple sensors and control of synchronous
described in the Low Frequency Oscillator Calibration section. stimulus sources is handled by multiple time slots. The device
The host can also use TIMESTAMP_ SLOT_DELTA to determine provides up to 12 time slots for multisensor applications. The
when the next time slot occurs. TIMESTAMP_SLOT_DELTA enabled time slots are repeated at the sampling rate, which is
can be used to determine the arrival time of the samples currently configured by the 23-bit TIMESLOT_PERIOD_x bit field in the
in the FIFO. TIMESTAMP_SLOT_DELTA does not account for TS_FREQ register. The sampling rate is determined by the
the decimation factor. following formula:
The time stamp trigger is edge sensitive and can be set to either Sampling Rate = Low Frequency Oscillator Frequency (Hz) ÷
trigger on the rising edge (default) or falling edge using TIMESLOT_PERIOD_x
TIMESTAMP_INV. Each time slot allows the creation of one or more LED and/or
LOW FREQUENCY OSCILLATOR CALIBRATION modulation pulses, and the acquisition of the photodiode or
other sensor current based on that stimulus. The operating
The time stamp circuitry can be used to calibrate either the
parameters for each time slot is highly configurable.
32 kHz or 1 MHz low frequency oscillator circuit by adjusting
the frequency to match the timing of the time stamp triggers.
Simply compare the TIMESTAMP_COUNT_x value in low

Rev. A | Page 20 of 82
Data Sheet ADPD4000/ADPD4001
Figure 22 shows the basic time slot operation sequence. Each Using External Synchronization for Sampling
time slot is repeated at the sampling rate, followed by an ultra An external signal driven to a configured GPIO pin can be used
low power sleep period. By default, subsequent time slots are to wake from sleep instead of the TIMESLOT_PERIOD_x
initiated immediately following the end of the previous time counter, which allows external control of the sample rate and time.
slot. In addition, there is an option to add an offset to the start This mode of operation is enabled using the EXT_SYNC_EN
of the subsequent time slots using the TIMESLOT_OFFSET_x bit and uses the GPIO pin selected by the EXT_SYNC_GPIO bit
bit field as shown in Figure 23, which shows the TIMESLOT_ field. If using this feature, be sure to enable the selected GPIO
OFFSET_B bit field being used to offset the start of Time Slot B. pin as an input using the appropriate GPIO_PIN_CFGx bit field.
In this case, each time slot still operates at the sampling rate, but
When operating with external synchronization, the device
there is a sleep period between Time Slot A and Time Slot B.
enters sleep first when set into go mode and waits for the next
The wake period shown in Figure 22 and Figure 23 is used to
external synchronization signal before waking up. This external
power up and stabilize the analog circuitry before data
synchronization signal is then synchronized to the low frequency
acquisition begins. If the TIMESLOT_OFFSET_B bit field is set
oscillator and then starts the wake-up sequence. If an additional
to 0, the time slot starts as soon as the previous time slot finishes.
external synchronization is provided prior to completing time
The time slot offset is always applied to the Time Slot A start slot operations, it is ignored.
time. For example, TIMESLOT_OFFSET_D is an offset added
to the beginning of Time Slot A, not Time Slot C, which EXECUTION MODES
immediately precedes Time Slot D. A state machine in the low frequency oscillator clock domain
The amount of offset applied is dependent on the low frequency controls sleep times, wake-up cycles, and the start of time slot
oscillator used. If using the 1 MHz low frequency oscillator, operations. The low frequency oscillator serves as the time base
for all time slot operations, controls the sample rates, and clocks
Offset = 64 × (Number of 1 MHz Low Frequency Oscillator the low frequency state machine. This state machine controls all
Cycles) × TIMESLOT_OFFSET_x operations and is controlled by the OP_MODE bit.
If using the 32 kHz low frequency oscillator,
Table 15. OP_MODE Bit Setting Descriptions
Offset = 2 × (Number of 32 kHz Low Frequency Oscillator OP_MODE
Cycles) × TIMESLOT_OFFSET_x Setting Mode Description
For example, if TIMESLOT_OFFSET_C is set to 0x040 and the 0 Off All operations stopped. Time slot actions
1 MHz low frequency oscillator is being used, then the offset reset. Low power standby state.
from the start of Time Slot A to the start of Time Slot C is 1 Go Transitioning to this state from off mode
starts time slot operation.
Offset = (64 × 1 µs × 64) = 4.096 ms
At power-up and following any subsequent reset operations, the
The sampling rate is controlled by the low frequency oscillator. ADPD4000/ADPD4001 is in off mode. The user can write 0 to
The low frequency oscillator is driven by one of three sources as the OP_MODE bit to immediately stop operations and return
described in the Clocking section. to off mode.
If the sampling period is set too short to allow the enabled time Register writes that affect operating modes cannot occur during
slots to complete, a full cycle of enabled time slot samples are go mode. The user must enter off mode before changing the
skipped, effectively reducing the overall sample rate. For example, control registers. Off mode resets the digital portion of the
if the sampling rate is set to 100 Hz (10 ms period) and the total ADC, all of the pulse generators, and the state machine.
amount of time required to complete all enabled time slots is
11 ms, the next cycle of time slots does not begin until t = 20 ms, When OP_MODE is set to 1, the device immediately starts the
effectively reducing the sampling rate to 50 Hz. first wake-up sequence and time slot operations unless using an
external synchronization trigger. If using an external
If TIMESLOT_OFFSET_x is set too short to allow the previous synchronization trigger, the device enters the sleep state before
time slot to finish, the time slot occurs immediately after the the first wake-up and time slot regions begin.
previous time slot. Time slots always occur in A through L order.

SLEEP WAKE TIME SLOT A TIME SLOT B TIME SLOT L SLEEP WAKE TIME SLOT A
17335-025

TIMESLOT_PERIOD_x/
LOW FREQUENCY OSCILLATOR (s)

Figure 22. Basic Time Slot Operation Sequence

SLEEP WAKE TIME SLOT A SLEEP WAKE TIME SLOT B SLEEP WAKE TIME SLOT A

TIME SLOT_OFFSET_B
17335-026

TIMESLOT_PERIOD_x/
LOW FREQUENCY OSCILLATOR (s)

Figure 23. Time Slot Operation with Offset Using TIMESLOT_OFFSET_x

Rev. A | Page 21 of 82
ADPD4000/ADPD4001 Data Sheet
HOST INTERFACE THRESH0_SHIFT_x bit field. A comparison is then made
The ADPD4000/ADPD4001 provide two methods of between the shifted threshold value and the register chosen by
communication with the host, a SPI port and I2C interface. The the THRESH0_TYPE_x bit field and the THRESH0_CHAN_x
device also provides numerous FIFO, data register, error, and bit. The INT_LEV0_x status bit is set if the selected data register
threshold status bits, each of which can be provided by an meets the criteria set in the THRESH0_DIR_x bit field. The
interrupt function from a GPIO, read from status registers, or Level 1 interrupt operates in the same fashion.
appended as optional status bytes at the end of a FIFO packet. Clearing Interrupt Status Bits
Interrupt Status Bits All status bits are set regardless of whether the status bit is routed
Data Register Interrupts to one of the interrupt outputs, Interrupt X or Interrupt Y. The
status bits are independent of the interrupt enable bits. The
The data interrupt status bits, INT_DATA_x for each time slot,
status bits are always set by the corresponding event. The
are set every time the data registers for that time slot are
interrupt bits stay set until they are either manually or
updated. The state of the HOLD_REGS_x bit has no effect on
automatically cleared.
the interrupt logic.
The user can manually clear a given interrupt by writing a 1 to
FIFO Threshold Interrupt the matching interrupt status bit. In addition, the data interrupt
The FIFO threshold interrupt status bit, INT_FIFO_TH, is set status bits can be configured to clear automatically. When the
when the number of bytes in the FIFO exceeds the value stored INT_ACLEAR_DATA_x or INT_ACLEAR_FIFO bit is set, the
in the FIFO_TH register. The INT_FIFO_TH bit is cleared appropriate interrupt status bit is automatically cleared when
automatically when a FIFO read reduces the number of bytes any matching data register or FIFO register is read. Automatic
below the value in the FIFO_TH register, which allows the user clearing of the interrupt status bits removes the need to
to set an appropriate data size for their host needs. manually clear these interrupts.
Level Interrupts Optional Status Bytes
Two level interrupt status bits, INT_LEV0_x and INT_LEV1_x, There is an option to append each data packet with status bits. This
provide an interrupt when the dark data or signal data values option is useful for hosts that cannot spare an interrupt channel
cross above or below a programmed threshold level. to service. The status bytes can each be individually selected in
Two comparison circuits are available per time slot. The the FIFO_STATUS_BYTES register. Each bit in the FIFO_
INT_LEV0_x or INT_LEV1_x status bits are set when the data STATUS_BYTES register enables a status byte that is appended
register update meets the criteria set by the associated to the data packet in the FIFO. If any bit in the FIFO_STATUS_
THRESH0_TYPE_x, THRESH0_DIR_x, THRESH0_CHAN_x BYTES register is set to 1, the byte that is appended to the data
settings, or by the associated THRESH1_TYPE_x, packet contains the status bits, as shown in Table 16. Table 16
THRESH1_DIR_x, and THRESH1_CHAN_x settings. shows the order, enable bit, and contents of each status byte.

The Level 0 interrupt operates as follows. The user sets an 8-bit The 4-bit sequence number cycles from 0 to 15 and is
threshold value in the THRESH0_VALUE_x bit field for the incremented with wraparound every time the time slot
corresponding time slot. This value is then shifted to the left by sequence completes. This sequence number can also be made
anywhere from 0 bits to 24 bits, specified by the setting of the available bitwise on the GPIO pins.

Table 16. FIFO Status Byte Order and Contents

Contents1
Byte Order Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 ENA_STAT_SUM 0 0 Any LEV1_x Any LEV0_x 4-bit sequence
1 ENA_STAT_D1 DATA_H DATA_G DATA_F DATA_E DATA_D DATA_C DATA_B DATA_A
2 ENA_STAT_D2 0 0 0 0 DATA_L DATA_K DATA_J DATA_I
3 ENA_STAT_L0 LEV0_H LEV0_G LEV0_F LEV0_E LEV0_D LEV0_C LEV0_B LEV0_A
4 ENA_STAT_L1 LEV1_H LEV1_G LEV1_F LEV1_E LEV1_D LEV1_C LEV1_B LEV1_A
5 ENA_STAT_LX LEV1_L LEV1_K LEV1_J LEV1_I LEV0_L LEV0_K LEV0_J LEV0_I
1
DATA_x refers to the data register interrupts for the corresponding time slot. LEV0_x and LEV1_x refer to Level 0 and Level 1 time slot interrupts, respectively, for
Time Slot A through Time Slot L.

Rev. A | Page 22 of 82
Data Sheet ADPD4000/ADPD4001
Interrupt Outputs, Interrupt X and Interrupt Y address and the last used address, which is 0x277. Reads from
The ADPD4000/ADPD4001 support two separate interrupt the FIFO address continue to access the next byte from the FIFO.
outputs, Interrupt X and Interrupt Y. Each interrupt has the option SPI Operations
to be driven to any of the four GPIO pins. The two different
The SPI single register write operation is shown in Figure 24.
interrupt outputs can be generated for a host processor if desired.
The first two bytes contain the 15-bit register address and specifies
For example, the FIFO threshold interrupt, INT_FIFO_TH, can
that a write is requested. The remaining two bytes are the 16
be routed to Interrupt X and used to drive the direct memory
data bits to write to the register. The register write occurs only
access (DMA) channel of the host, while the INT_FIFO_
when all 16 bits are shifted in prior to deassertion of the CS signal.
OFLOW and INT_FIFO_UFLOW interrupts can be routed to
Interrupt Y and used to drive an additional host interrupt pin. In addition, multiple registers can be written if additional 16-bit
Another example case includes routing the data interrupt from data is shifted in before deassertion of the CS signal. The
a single time slot to Interrupt X and the FIFO threshold register address automatically increments to the next register
interrupt to Interrupt Y. The host receives one interrupt when after each 16 bits of data.
the interrupt of that particular channel occurs and the host can The SPI single register read operation is shown in Figure 25.
then read that register directly. Interrupt Y, in this case, is The first two bytes contain the 15-bit register address and
handled by the host with DMA or with an interrupt. Each of the specifies that a read is requested. Register bits are shifted out
different interrupt status bits can be routed to Interrupt X or starting with the MSB. In addition, multiple registers can be
Interrupt Y, or both. read if additional 16-bit data is shifted out prior to deassertion
For each interrupt, there is an associated Interrupt X and of the CS signal.
Interrupt Y enable bit. See Table 27 for a full list of available It is recommended that reading from the FIFO is done byte
interrupts that can be brought out on Interrupt X and Interrupt Y. wise. There is no requirement to read multiples of 16 bits.
The logic for the Interrupt X and Interrupt Y function is a logic
AND of the status bit with its matching enable bit. All enabled I2C Operations
status bits are then logically OR’ed to create the interrupt The I2C operations require addressing the device as well as
function. The enable bits do not affect the status bits. choosing the register that is being read or written. An I2C
General-Purpose I/Os register write is shown in Figure 26 and Figure 27. The SDA pin
is bidirectional open drain, where different bit times are driven
The ADPD4000/ADPD4001 provide four general-purpose I/O
in a predetermined way by the master or the slave. The ADPD4001
pins: GPIO0, GPIO1, GPIO2, and GPIO3. These GPIOs can be
acts as a slave on the I2C bus. Start and stop bit operations are
used as previously described in the Interrupt Outputs, Interrupt
shown as S and P in Figure 26 and Figure 27. The I2C port
X and Interrupt Y section for interrupt outputs or for providing
supports both 7-bit and 15-bit addresses. If accessing Address
external clock signals to the device. The GPIOs can also be used
0x007F or lower, a 7-bit address can be used. If the first address
for many different control signals, as synchronization controls
bit after the slave address acknowledge (ACK) is a 0, a 7-bit
to external devices, as well as test signals that are useful during
address is used, as shown in the short read and write operations
system debugging. All of the available signals that can be
(see Figure 26 to Figure 29). If the first bit after a slave address
brought out on a GPIOx pin are listed in Table 31.
acknowledge is 1, a 15-bit address is used as shown in the long
SPI and I2C Interface read and write operations (see Figure 30 and Figure 31).
The ADPD4000 contains a SPI port, the ADPD4001 contains Figure 26 shows the first half of the short register write operation.
an I2C interface. The SPI and I2C interfaces operate synchro- The first byte indicates that the ADPD4001 is being addressed
nously with their respective input clocks and require no internal with a write operation. The ADPD4001 indicates that it has
clocks to operate. been addressed by driving an acknowledge. The next byte
The ADPD4000/ADPD4001 have an internal power-on-reset operation is a write of the address of the register to be written.
circuit that sets the device into a known idle state during the The MSB is the L/S bit (long/short). When this bit is low, a 7-bit
initial power-up. After the power-on-reset has been released, address follows. If the L/S bit is high, a 15-bit address follows.
approximately 2 µs to 6 μs after the DVDD supply is active, the The ADPD4001 sends an acknowledge following the register
device can be read and written through the SPI or I2C interface. address.
The registers are accessed using addresses within a 15-bit The rest of the write operation is shown in Figure 27, which
address space. Each address references a 15-bit register with one shows the two data bytes that are written to the 16-bit register.
address reserved for the FIFO read accesses. For both the I2C Registers are written only when all 16 bits are shifted in before a
and SPI interfaces, reads and writes auto-increment to the next stop bit occurs. The ADPD4001 sends an acknowledge for each
register if additional words are accessed as part of the same byte received. Additional pairs of byte operations can be repeated
access sequence. This automatic address increment occurs for prior to the stop bit occurring. The address auto-increments
all addresses except the FIFO address, one less than the FIFO
Rev. A | Page 23 of 82
ADPD4000/ADPD4001 Data Sheet
after each complete write. Register writes occur only after each each byte after it is sent by the ADPD4001, if additional bytes
pair of bytes is written. are to be read. The same address incrementing is used for reads
The I2C short read operations are shown in Figure 28 and as well.
Figure 29. Like the write operation, the first byte pair selects the To read multiple bytes from the FIFO or from sequential
ADPD4001 and specifies the register address (with the L/S bit registers, simply repeat the middle byte operation as shown in
low) to read from. Figure 29.
Figure 29 shows the rest of the read operation. This sequence The first portion of a long write operation is shown in Figure 30.
starts with a start bit, selects the ADPD4001, and indicates that The second half of the long write is the same as for the short
a read operation follows. The ADPD4001 sends an acknowledge write, as shown in Figure 27.
to indicate data to be sent. The ADPD4001 then shifts out the The first half of a long read operation is shown in Figure 31.
register read data one byte at a time. The host acknowledges The second half is the same as shown in Figure 29.

SCLK

17335-027
CS
MOSI A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Wr D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Figure 24. SPI Write Operation

SCLK

CS

17335-028
MOSI A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Rd

MISO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Figure 25. SPI Read Operation

SCL

SDA S SLVA6 SLVA5 SLVA4 SLVA3 SLVA2 SLVA1 SLVA WRITE ACK L/S A6 A5 A4 A3 A2 A1 A0 ACK D15

17335-029
GREY BACKGROUND MEANS DRIVEN BY ADPD4001

Figure 26. I2C Short Write First Half

SCL

17335-030
SDA D15 D14 D13 D12 D11 D10 D9 D8 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK P
2
Figure 27. I C Short Write Second Half

SCL

SDA S SLVA6 SLVA5 SLVA4 SLVA3 SLVA2 SLVA1 SLVA WRITE ACK L/S A6 A5 A4 A3 A2 A1 A0 ACK 17335-031

Figure 28. I2C Short Read First Half

17335-032

SCL

SDA S SLVA6 SLVA5 SLVA4 SLVA3 SLVA2 SLVA1 SLVA0 READ ACK D15 D14 D13 D12 D11 D10 D9 D8 ACK D7 D6 D5 D4 D3 D2 D1 D0 NACK P

2
Figure 29. I C Short Read Second Half

SCL
17335-033

SDA S SLVA6 SLVA5 SLVA4 SLVA3 SLVA2 SLVA1 SLVA0 WRITE ACK L/S A14 A13 A12 A11 A10 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D15

2
Figure 30. I C Long Write First Half

SCL
17335-034

SDA S SLVA6 SLVA5 SLVA4 SLVA3 SLVA2 SLVA1 SLVA0 WRITE ACK L/S A14 A13 A12 A11 A10 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK

2
Figure 31. I C Long Read First Half
Rev. A | Page 24 of 82
Data Sheet ADPD4000/ADPD4001

APPLICATIONS INFORMATION
OPERATING MODE OVERVIEW photodiode and is set to TIA_VREF + 250 mV to apply a
250 mV reverse bias across the photodiode, which reduces the
The ADPD4000/ADPD4001 are effectively charge measuring photodiode capacitance and reduces the noise of the signal
devices that can interface with many different sensors enabling path. Set TIA_VREF to 1.27 V using the AFE_TRIM_VREF_x
synchronous measurements of PPG, electrocardiography bit field for maximum dynamic range.
(ECG), electrodermal activity (EDA), impedance, capacitance,
and temperature measurements. A selection of operating modes The LED pulse is controlled with the LED_OFFSET_x and LED_
are built into the device to optimize each of the different sensor WIDTH_x bit field. The default LED offset (LED_OFFSET_x =
measurements supported. 0x10) is 16 μs from the end of the preconditioning period and is
suitable for most use cases. Recommended LED pulse widths
SINGLE INTEGRATION MODE are either 2 μs or 3 μs when using the BPF. Shorter LED pulse
Single integration mode is used for a single integration of widths provide the greatest amount of ambient light rejection
incoming charge per ADC conversion and is the most common and the lowest power dissipation. The period is automatically
operating mode for the ADPD4000/ADPD4001. In single calculated by the ADPD4000/ADPD4001. The automatic
integration mode, most of the dynamic range of the integrator is calculation is based on the integration width selected and the
used when integrating the charge from the sensor response to a number of ADC conversions. To use the automatic calculation,
single stimuli event, for example, an LED pulse. There is also a leave the MIN_PERIOD_x bit field at its default value of 0. If a
multiple integration mode available for situations with very longer period is desired, for example, if more settling time is
small sensor responses (see the Multiple Integration Mode required, use the MIN_PERIOD_x bit field to enable a longer
section for more information). period.
Using LED as Stimulus The integration pulses are controlled with the INTEG_
Single integration mode is the typical operating mode used for a OFFSET_x, INTEG_FINE_OFFSET_x, and INTEG_WIDTH_x
PPG measurement, where an LED is pulsed into human tissue bit fields. It is recommended that an integration width of 1 μs
and the resultant charge from the photodiode response is greater than the LED width be used because the signal spreads
integrated and subsequently converted by the ADC. Figure 32 due to the response of the BPF. By setting the integration width
shows an example of a typical PPG measurement circuit. 1 μs wider than the LED width, a maximum amount of charge
from the incoming signal is integrated.
VCx
The number of ADC conversions defaults to a single ADC
RF 6.3pF conversion. However, oversampling is available for increased
INx
RINT SNR. The ADC conversions can be set to 1, 2, 3, or 4, based on
TIA BPF RINT ADC the ADC_COUNT_x bit field. If two channels are enabled,
RF
SWITCH
Channel 1 occurs first, followed by Channel 2. The total number of
VLED1
CVLED 6.3pF pulses is equal to NUM_INT_x × NUM_REPEAT_x. In single
TIA_VREF
integration mode, NUM_INT_x = 1 for a single integration
LEDx
sequence per ADC conversion. Therefore, the total number of
pulses is controlled by NUM_REPEAT_x. Increasing the
17335-035

number of pulses reduces the noise floor of the measurement by a

factor of √n, where n is the total number of pulses.
Figure 32. Typical PPG Measurement Circuit
Figure 33 shows the timing operation where a single integration
The MOD_TYPE_x value is left at the default value of 0 so that cycle is used per ADC conversion. Table 17 details the relevant
the TIA is continuously connected to the input of the TIA. Set registers using single integration mode for a PPG measurement.
the PRECON_x bit field to 0x5 to set the anode of the photodiode
(PD) to the TIA_VREF potential during the preconditioning
period. The VCx pin is connected to the cathode of the

Rev. A | Page 25 of 82
ADPD4000/ADPD4001 Data Sheet
START OF TIME SLOT

PRECONDITION
PRE_WIDTH_x
PERIOD LED_WIDTH_x
LED_OFFSET_x (AUTOMATICALLY CALCULATED)
LED

TIA OUTPUT

BPF OUTPUT

INTEG_WIDTH_x ZERO CROSSING

INTEGRATOR INTEG_OFFSET_x + INTEG_FINE_OFFSET_x
+ – + –
SEQUENCE

INTEGRATOR
OUTPUT

ADC CH1

ADC CH2

17335-036
(IF ENABLED)
REPEAT NUM_REPEAT_x TIMES

Figure 33. Single Integration per ADC Conversion with LED as Stimulus

Table 17. Single Integration Mode Settings

Time Slot A
Group Register Address1 Bit Field Name Description
Signal Path 0x0100 SAMPLE_TYPE_x Leave at the default setting (0) for default sampling mode.
Setup 0x0101 AFE_PATH_CFG_x Set to 0x1DA for TIA, BPF, integrator, and ADC.
0x0102 INPxx_x Enable desired inputs.
0x0103 PRECON_x Set to 0x5 to precondition anode of the photodiode to TIA_VREF.
0x0103 VCx_SEL_x Set to 0x2 to set ~250 mV reverse bias across the photodiode.
0x0104 TIA_GAIN_CHx_x Select TIA gain.
0x0104 AFE_TRIM_VREF_x Set to 0x3 to set TIA_VREF = 1.27 V for maximum dynamic range.
0x0108 MOD_TYPE_x Set to 0 for continuous TIA connection to inputs following preconditioning.
Timing 0x0109 LED_OFFSET_x Sets start time of first LED pulse in 1 μs increments. 0x10 default (16 μs)
0x0109 LED_WIDTH_x Sets width of LED pulse in 1 μs increments. 2 μs or 3 μs recommended.
0x010A INTEG_WIDTH_x Integration time in µs. Set to LED_WIDTH_x + 1.
0x010B INTEG_OFFSET_x, Integration sequence start time = INTEG_OFFSET_x +
INTEG_FINE_OFFSET_x INTEG_FINE_OFFSET_x. Optimize as described in the Optimizing Position
of Integration Sequence section.
0x0107 NUM_INT_x Set to 1 for a single integration per group of ADC conversions.
0x0107 NUM_REPEAT_x With NUM_INT_x = 1, NUM_REPEAT_x sets the total number of pulses.
LED Settings 0x0105, 0x0106 LED_DRIVESIDEx_x Select LED for time slot used.
0x0105, 0x0106 LED_CURRENTx_x Set LED current for selected LED.
1
This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for
SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at
Address 0x0160, and so on.

Rev. A | Page 26 of 82
Data Sheet ADPD4000/ADPD4001
Optimizing Position of Integration Sequence combine the digitized result of each of the pulses of the sample,
It is critical that the zero crossing of the output response of the the sequences with an inverted integrator sequence are
BPF be aligned with the integration sequence such that the subtracted and the sequences with a normal integrator sequence
positive integration is aligned with the positive portion of the are added. An example diagram of the integrator chopping
BPF output response and the negative integration is aligned with sequence is shown in Figure 34.
the negative portion of the BPF output response (see Figure 33). The result of chopping is that any low frequency signal contribu-
A simple test to find the zero crossing is to set the circuit so that tion from the integrator is eliminated, leaving only the integrated
the LED is reflecting off a reflector at a fixed distance from the signal and resulting in higher SNR, especially at higher numbers of
photodiode such that a steady dc level of photodiode current is pulses and at lower TIA gains where the noise contribution of
provided to the ADPD4000/ADPD4001. Monitor the output the integrator becomes more pronounced.
while sweeping the coarse integrator offset, INTEG_OFFSET_x, Digital chopping is enabled using the registers and bits detailed
from a low value to a high value in 1 μs steps. The zero crossing in Table 18. The bit fields define the chopping operation for the
is located when a relative maxima is seen at the output. The first four pulses. This 4-bit sequence is then repeated for all
zero crossing can then be identified with much finer precision by subsequent sequence of four pulses. In Figure 34, a sequence is
sweeping the INTEG_FINE_OFFSET_x bit field in 31.25 ns shown where the second and fourth pulses are inverted while the
increments. first and third pulses remain in the default polarity (noninverted).
This configuration is achieved by setting the REVERSE_INTEG_x
Improving SNR Using Multiple Pulses
bit field = 0xA to reverse the integration sequence for the second
The ADPD4000/ADPD4001 use very short LED pulses, on the and fourth pulses. To complete the operation, the math must be
order of 2 μs or 3 μs. The SNR of a single pulse is approximately adjusted by setting the SUBTRACT_x bi field = 0xA. An even
68 dB to 74 dB, depending on the TIA gain. The SNR can be number of pulses must be used with integrator chop mode.
extended to >90 dB by increasing the number of pulses per
When using integrator chop mode, the ADC offset bit fields,
sample and filtering to a relevant signal bandwidth, for example,
CH1_ADC_ADJUST_x and CH2_ADC_ADJUST_x, must be
0.5 Hz to 20 Hz for a heart rate signal. The SNR increases as the
set to 0, because when the math is adjusted to subtract inverted
square root of the number of pulses. Thus, for every doubling of
integration sequences while default integration sequences are
pulses, 3 dB of SNR increase is achieved. The number of pulses
added, any digital offsets at the output of the ADC are
is increased with the NUM_REPEAT_x bit field.
automatically eliminated. Integrator chop mode also eliminates
Improving SNR Using Integrator Chopping the need to manually null the ADC offsets at startup in a typical
The last stage in the ADPD4000/ADPD4001 datapath is a application. Note that the elimination of the offset using chop
charge integrator. The integrator uses an on and off integration mode can clip at least half of the noise signal when no input
sequence, synchronized to the emitted light pulse, which acts as signal is present, which makes it difficult to measure the noise
an additional high-pass filter to remove offsets, drifts, and low floor during characterization of the system. There are three
frequency noise from the previous stages. However, the options for performing noise floor characterization of the system.
integrating amplifier can itself introduce low frequency signal • Chop mode disabled.
content at a low level. The ADPD4000/ADPD4001 have a mode • Chop mode enabled but with a minimal signal present at
that enables additional chopping in the digital domain to the input, which increases the noise floor enough such that
remove this signal. Chopping is achieved by using an even it is no longer clipped.
number of pulses per sample and inverting the integration • Setting the ZERO_ADJUST_x bit = 1, which adds 2048 codes
sequence for half of those sequences. When the math is done to to the end result.

PULSE 1 PULSE 2 PULSE 3 PULSE 4

LED

BPF OUTPUT

INTEGRATOR + – – + – –
SEQUENCE + +
17335-037

ADC
+ – + –

Figure 34. Diagram of Integrator Chopping Sequence

Rev. A | Page 27 of 82
ADPD4000/ADPD4001 Data Sheet
Table 18. Register Settings for Integrator Chop Mode
Time Slot A
Group Register Address1 Bit Field Name Description
Integrator 0x010D SUBTRACT_x Four-pulse subtract pattern. Set to 1 to negate the math operation in the
Chop Mode matching position in a group of four pulses. The LSB maps to the first pulse.
0x010D REVERSE_INTEG_x Four-pulse integration reverse pattern. Set to 1 to reverse the integrator
positive and negative pulse order in the matching position in a group of four
pulses. The LSB maps to the first pulse.
1
This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x010D is the location for
SUBTRACT_A. For Time Slot B, this register is at Address 0x012D, For Time Slot C, this register is at Address 0x014D. For Time Slot D, this register is at Address 0x016D,
and so on.

Connection Modulation In float mode, the signal path bypasses the BPF and uses only
The ADPD4000/ADPD4001 use three different types of modula- the TIA and integrator. The BPF is bypassed because the shape
tion connections to a sensor, controlled by the MOD_TYPE_x of the signal produced when transferring the charge from the
bit field. Table 19 shows the different functions controlled by photodiode by modulating the connection to the TIA can differ
this register. The default mode of operation is MOD_TYPE_x = across devices and conditions. A filtered signal from the BPF is
0, which is the mode where there is no modulation of the input not able to be reliably aligned with the integration sequence.
connection, and is the mode used as described in the Using Therefore, the BPF cannot be used. In float mode, the entire
LED as Stimulus section. charge transfer is integrated in the negative cycle of the
integrator and the positive cycle cancels any offsets.
Table 19. Modulation Connections Based on MOD_TYPE_x
Float LED Mode for Synchronous LED Measurements
MOD_TYPE_x Connect function
Float LED mode is desirable in low signal conditions where the
0 TIA is continuously connected to INx after the
precondition period. There is no modulation of CTR is <10 nA/mA. In addition, float mode is an ideal option
the input connection. when limiting the LED drive current of the green LEDs in a
1 Float mode operation. The TIA is connected to heart rate measurement to keep the forward voltage drop of the
INx only during the modulation pulse and green LED to a level that allows the elimination of a boost
disconnected (floated) between pulses. converter for the LED supply. For example, the LED current can
2 Nonfloat mode connection modulation. The be limited to 10 mA to ensure that the LED voltage drop is ~3 V
TIA is connected to INx during the modulation so that it can operate directly from the battery without the need
pulse and connected to the precondition value
between pulses. of a boost converter. Float mode accumulates the received
charge during longer LED pulses without adding noise from the
Float Mode Operation signal path, effectively yielding the highest SNR per photon
attainable.
The ADPD4000/ADPD4001 have a unique operating mode, float
mode, that allows high SNR at low power in low light situations. In float LED mode, multiple pulses are used to cancel electrical
In float mode, the photodiode is first preconditioned to a known offsets, drifts, and ambient light. To achieve this ambient light
state and then the photodiode anode is disconnected from the rejection, an even number of equal length pulses are used. For
receive path of the device for a preset amount of float time. every pair of pulses, the LED flashes in one of the pulses and
During the float time, light falls on the photodiode, either from does not flash in the other. The return from the combination of
ambient light, pulsed LED light, or a combination of the two the LED, ambient light, and offset is present in one of the pulses.
depending on the operating mode. Charge from the sensor is In the other, only the ambient light and offset is present. A
stored directly on the capacitance of the sensor, CPD. At the end subtraction of the two pulses is made that eliminates ambient
of the float time, the photodiode is switched into the receive light as well as any offset and drift. It is recommended to use
path of the ADPD4000/ADPD4001 and an inrush of the groups of four pulses for measurement where the LED is flashed
accumulated charge occurs, which is then integrated, allowing on Pulse 2 and Pulse 3. The accumulator adds Pulse 2 and Pulse 3
the maximum amount of charge to be processed per pulse with and then subtracts Pulse 1 and Pulse 4. To gain additional SNR,
the minimum amount of noise added by the signal path. The use multiple groups of four pulses.
charge is integrated externally on the capacitance of the For each group of four pulses, the settings of LED_DISABLE_x
photodiode for as long as it takes to acquire maximum charge, determine if the LED flashes in a specific pulse position. Which
independent of the amplifiers of the signal path, effectively pulse positions are added or subtracted is configured in the
integrating charge noise free. Float mode allows the user the SUBTRACT_x bit field. These sequences are repeated in groups
flexibility to increase the amount of charge per measurement by of four pulses. The value written to the FIFO or data registers is
either increasing the LED drive current or by increasing the dependent on the total number of pulses per sample period.
float time. With NUM_INT_x set to 1, NUM_REPEAT_x determines the
total number of pulses. For example, if the device is set up for
Rev. A | Page 28 of 82
Data Sheet ADPD4000/ADPD4001
32 pulses, the four-pulse sequence, as defined in charge from the photodiode causes the integrator to increase
LED_DISABLE_x and SUBTRACT_x, repeats eight times and a with the negative going output signal from the TIA.
single register or FIFO write of the final value based on In the example shown in Figure 35, the LED flashes in the
32 pulses executes. second and third pulses of the four-pulse sequence.
In float mode, the MIN_PERIOD_x bit field must be set to SUBTRACT_x is set up to add the second and third pulses
control the pulse period. The automatic period calculation is while subtracting the first and fourth pulses, effectively
not designed to work with float mode. Set the MIN_PERIOD_x cancelling out the ambient light, electrical offsets, and drift.
bit field, in 1 μs increments, to accommodate the amount of Additionally, set the INPUT_R_SELECT_x bit field equal to 1
float time and connect time required. to place a 6.5 kΩ resistor in series between the photodiode and
Placement of the integration sequence is such that the negative the TIA input to slow the inrush of current from the
phase of the integration is centered on the charge transfer photodiode when the input switch is closed.
phase. The TIA is an inverting stage. Therefore, placing the Table 20 details the relevant registers for float LED mode.
negative phase of the integration during the transferring of the

START OF TIME SLOT

PRECONDITION
PRE_WIDTH_x
(DEFAULT 8µs)
MOD_OFFSET_x MIN_PERIOD_x
MOD_WIDTH_x
CONNECT/FLOAT

LED PULSES MASKED LED PULSE FLASH LED FLASH LED MASKED LED PULSE
LED_OFFSET_x
MASK PULSE 1 AND PULSE 4
FLASH PULSE 2 AND PULSE 3
LED_WIDTH_x

ACCUMULATED
CHARGE ON PD

INTEGRATOR
OUTPUT

INTEG_OFFSET_x + INTEG_FINE_OFFSET_x

INTEGRATOR
SEQUENCE

INTEG_WIDTH_x
INTEGRATOR
RESET

17335-038
ADC READ
– + + –

Figure 35. Four-Pulse Float Mode Operation

Table 20. Float LED Mode Settings

Time Slot A
Group Register Address1 Bit Field Name Description
Signal Path Setup 0x0100 SAMPLE_TYPE_x Leave at the default setting (0) for default sampling mode.
0x0100 INPUT_R_SELECT_x Set to 0x1 for 6.25 kΩ series input resistor.
0x0101 AFE_PATH_CFG_x Set to 0x0E6 for TIA, integrator, and ADC. Bypass BPF.
0x0102 INPxx_x Enable desired inputs.
0x0103 PRECON_x Set to 0x4 to precondition anode of photodiode to the input of the TIA.
0x0103 VCx_SEL_x Set to 0x2 to set ~250 mV reverse bias across photodiode.
0x0104 TIA_GAIN_CHx_x Select TIA gain (100 kΩ or 200 kΩ for float mode).
0x0104 AFE_TRIM_VREF_x Set to 0x2 to set TIA_VREF = 0.9 V.
Float Mode 0x0107 NUM_INT_x Set to 1 for a single integration per group of ADC conversions.
Configuration 0x0107 NUM_REPEAT_x Number of sequence repeats. Must be set to a multiple of 2 for float
mode.
0x0108 MOD_TYPE_x Set to 0x1 for float mode operation.
0x0108 MIN_PERIOD_x Set the period to accommodate float time plus connect time, in 1 μs
increments.
0x010A INTEG_WIDTH_x Integration time in µs. Set to MOD_WIDTH_x + 1.
Rev. A | Page 29 of 82
ADPD4000/ADPD4001 Data Sheet
Time Slot A
Group Register Address1 Bit Field Name Description
0x010B INTEG_OFFSET_x Integration sequence start time. Set to (MOD_OFFSET_x −
INTEG_WIDTH_x − 1).
0x010B INTEG_FINE_OFFSET_x Set to 0x18.
0x010C MOD_WIDTH_x Sets width of connect pulse in 1 μs increments. Typical values of 2 μs or
3 μs.
0x010C MOD_OFFSET_x Sets start time of first connect pulse in 1 μs increments.
0x010D SUBTRACT_x In any given sequence of four pulses, negate the math operation in the
selected position. Selections are active high (that is, subtract if 1) and
the LSB of this register maps to the first pulse. For a float mode
sequence, add pulses when the LED flashes and subtract pulses when
the LED is disabled, according to LED_DISABLE_x.
LED Settings 0x0105, 0x0106 LED_DRIVESIDEx_x Select LED for time slot used.
0x0105, 0x0106 LED_CURRENTx_x Set LED current for selected LED.
0x0109 LED_OFFSET_x Sets start time of first LED pulse in 1 μs increments.
0x0109 LED_WIDTH_x Sets width of LED pulse in 1 μs increments.
0x010D LED_DISABLE_x In any given sequence of four pulses, disable the LED pulse in the
selected position. Selections are active high (that is, disable LED if 1)
and the LSB of this register maps to the first pulse. For a sequence of
four pulses, it is recommended to fire the LED in the second and third
pulses by writing 0x9 to this register.
1
This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for
SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at
Address 0x0160, and so on.

Float Mode Limitations

When using float mode, the limitations of the mode must be
INTEGRATED CHARGE ON PD (pC)

well understood. For example, a finite amount of charge can PD BEGINS TO

accumulate on the capacitance of the photodiode, and there is a FORWARD BIAS

maximum amount of charge that can be integrated by the

integrator. Based on an initial reverse bias of 250 mV on the
photodiode and assuming that the photodiode begins to
become nonlinear at ~200 mV of forward bias, there is ~450 mV
RECOMMENDED
of headroom for the anode voltage to increase from its starting FLOAT MODE
OPERATING REGION
point at the beginning of the float time before the charge ceases
to accumulate in a linear fashion. It is desirable to operate only
in the linear region of the photodiode (see Figure 36). To verify

17335-039
that float mode is operating in the linear region of the diode, FLOAT TIME (µs)
the user can perform a simple check. Record data at a desired Figure 36. Integrated Charge on the Photodiode (PD) vs. Float Time
float time and then record data at half the float time. The
The maximum amount of charge that can be stored on the
recommended ratio of the two received signals is 2:1. If this
photodiode capacitance and remain in the linear operating
ratio does not hold true, the diode is likely beginning to
region of the sensor is estimated by
forward bias at the longer float time and becomes nonlinear.
Q = CPDV
where:
Q is the integrated charge.
CPD is the capacitance of the photodiode.
V is the amount of voltage change across the photodiode before
the photodiode becomes nonlinear.
For a typical discrete optical design using a 7 mm2 photodiode
with 70 pF capacitance and 450 mV of headroom, the maximum
amount of charge that can be stored on the photodiode capaci-
tance is 31.5 pC.

Rev. A | Page 30 of 82
Data Sheet ADPD4000/ADPD4001
In addition, consider the maximum amount of charge the of the noise performance benefits of the full signal path using
integrator of the ADPD4000/ADPD4001 can integrate. The the BPF and integrator. Figure 38 shows a timing diagram for
integrator can integrate up to 7.6 pC. When this charge is referred pulse connect modulation type measurements.
back to the input, consider the TIA gain. When the TIA gain is Modulation of Stimulus Source
at 200 kΩ, the input referred charge is at a 1:1 ratio to the
The ADPD4000/ADPD4001 have operating modes that
integrated charge on the integrator. For 100 kΩ gain, it is 2:1.
modulate the VC1 and VC2 signals. These modes are useful for
For 50 kΩ gain, it is 4:1.For 25 kΩ gain, it is 8:1. For the previous
providing a pulsed stimulus to the sensor being measured. For
example using a photodiode with 70 pF capacitance, use a 50 kΩ
example, a bioimpedance measurement can be made where one
TIA gain and set the float timing such that, for a single pulse, the
electrode to the human is being pulsed by the VC1 or VC2
output of the ADC is at 70% of full scale, which is a typical
output and the response is measured on a second electrode
operating condition. Under these operating conditions, 5.3 pC
connected to the TIA input. This mode is also useful for a
integrates per pulse by the integrator for 21.2 pC of charge
capacitance measurement, as shown in Figure 37, where one of
accumulated on the photodiode capacitance. The amount of
the VCx pins is connected to one side of the capacitor and the
time to accumulate charge on CPD is inversely proportional to
other side is connected to the TIA input.
CTR. TIA gain settings of 100 kΩ or 200 kΩ may be required
based on the CTR of the measurement and how much charge RF
RINT
can be accumulated in a given amount of time. Ultimately, the INx

type of measurement being made (ambient or pulsed LED), the C

TIA_VREF TIA INT

photodiode capacitance, and the CTR of the system determine RINT

the float times.

17335-040
VCx RF

Pulse Connect Modulation

Figure 37. Modulate Stimulus for Capacitance Measurement
Pulse connect modulation is useful for ambient light measure-
ments or any other sensor measurements that do not require a The BPF is bypassed for this measurement. When a stimulus
synchronous stimulus. This mode works by preconditioning the pulse is provided on the VCx pin, the capacitor response is a
sensor to some level selected by the PRECON_x bit field and positive spike on the rising edge that then settles back toward
then only connecting the sensor to the input of the TIA during TIA_VREF, followed by a negative spike on the falling edge of
the modulation pulse. When not connected to the TIA, the sensor the stimulus pulse. The integration sequence is centered such
is connected to a low input impedance node at the TIA_VREF that the positive and negative integration sequences completely
voltage. Any sensor current during this time is directed into the integrate the charge from the positive and negative TIA responses,
AFE. Therefore, no charge accumulates on the sensor. This lack respectively (see Figure 39).
of charge accumulation is in contrast to float mode, which fully Pulsing of the VC1 and VC2 pins is controlled by the VCx_
disconnects the sensor between modulation pulses. The PULSE_x, VCx_ALT_x, and VCx_SEL_x bit fields while timing
MOD_TYPE_x bit field must be set to 0x2 for pulse connect of the modulation is controlled by the MOD_OFFSET_x and
mode. The advantage of using this mode for nonsynchronous MOD_WIDTH_x bit fields. Table 21 shows the relevant registers
sensor measurements is that it allows the user to take advantage for modulating the stimulus to the sensor.
START OF TIME SLOT
PRECONDITION
SENSOR PRE_WIDTH_x
(DEFAULT 8µs)
MOD_OFFSET_x PERIOD MOD_WIDTH_x
(AUTOMATICALLY CALCULATED)
CONNECT TIA
TO SENSOR

TIA OUTPUT

BPF OUTPUT

INTEG_WIDTH_x
INTEGRATOR INTEG_OFFSET_x + INTEG_FINE_OFFSET_x
+ – + –
SEQUENCE

INTEGRATOR
OUTPUT

ADC CH1

ADC CH2
17335-041

(IF ENABLED)
REPEAT NUM_REPEAT_x TIMES

Figure 38. Pulse Connect Modulation

Rev. A | Page 31 of 82
ADPD4000/ADPD4001 Data Sheet
START OF TIME SLOT
PRECONDITION
SENSOR
PRE_WIDTH_x MOD_WIDTH_x
(DEFAULT 8µs)
MOD_OFFSET_x PERIOD
(AUTOMATICALLY CALCULATED)
MODULATE
STIMULUS

TIA OUTPUT

INTEG_WIDTH_x
INTEGRATION
SEQUENCE INTEG_OFFSET_x + INTEG_FINE_OFFSET_x
+ – + –

INTEGRATOR
OUTPUT

17335-042
ADC CH1

Figure 39. Timing Diagram for Modulate Stimulus Operation

Table 21. Modulate Stimulus Settings

Time Slot A
Group Register Address1 Bit Field Name Description
Modulate Stimulus 0x0100 SAMPLE_TYPE_x Leave at the default setting (0) for default sampling mode.
Setup 0x0101 AFE_PATH_CFG_x Set to 0x0E6 for TIA, integrator, and ADC. Bypass BPF.
0x0102 INPxx_x Enable desired inputs.
0x0103 PRECON_x Set to 0x5 to precondition sensor to TIA_VREF.
0x0103 VCx_PULSE_x VCx pulse control. Set to 0x2 to pulse to the alternate
voltage during a modulation pulse.
0x0103 VCx_ALT_x Select the alternate state for VCx during the modulation
pulse.
0x0103 VCx_SEL_x Set to 0x1 to set VCx to TIA_VREF as primary state.
0x0104 TIA_GAIN_CHx_x Select TIA gain.
0x0104 AFE_TRIM_VREF_x Set to 0x2 to set TIA_VREF = 0.9 V.
Modulate Stimulus 0x010C MOD_OFFSET_x Sets start time of first modulation pulse in 1 μs
Timing increments.
0x010C MOD_WIDTH_x Sets width of modulation pulse in 1 μs increments. Typical
values of 6 μs to 12 μs.
0x010A INTEG_WIDTH_x Integration time in µs. Set to MOD_WIDTH_x + 1.
0x010B INTEG_OFFSET_x Integration sequence start time. Set to MOD_OFFSET_x − 1.
0x010B INTEG_FINE_OFFSET_x Start from 0 and sweep to find optimal operating point.
0x0107 NUM_INT_x Set to 1 for a single integration per ADC conversion
0x0107 NUM_REPEAT_x Number of sequence repeats. SNR increases as √n. where
n = NUM_REPEAT × NUM_INT.
1
This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for
SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at
Address 0x0160, and so on.

Rev. A | Page 32 of 82
Data Sheet ADPD4000/ADPD4001
MULTIPLE INTEGRATION MODE use six pulses and integrations, using most of the available
Multiple integration mode provides multiple integrations of dynamic range (75%) per ADC conversion while leaving 25% of
incoming charge per ADC conversion. This mode is most headroom for margin so that the integrator does not saturate as
useful when there is a very small response that uses a small the input level varies. As each pulse is applied to the LED, the
amount of the available dynamic range per stimuli event. charge from the response is integrated and held. The charge
Multiple integration mode allows multiple integrations of from the response to each subsequent pulse is added to the
charge prior to an ADC conversion so that a larger amount of previous total integrated charge, as shown in Figure 40, until
the available dynamic range of the integrator is utilized. NUM_INT_x integrations is reached.

Figure 40 shows multiple integration mode using the LED as In multiple integration mode, the minimum period is automati-
the stimulus. The number of LED pulses and subsequent cally calculated. In the example shown, the minimum period is
integrations of charge from the PD response is determined by calculated at 2 × INTEG_WIDTH_x so that subsequent pulses
the setting of the NUM_INT_x bit field. Following the final occur immediately following the completion of the previous
integration, there is a single ADC conversion. This process is integration. Extra time is automatically added to accommodate
repeated NUM_REPEAT_x times. the ADC conversions at the end of NUM_INT_x integrations.

Prior to setting the number of integrations using the NUM_INT_x Use NUM_REPEAT_x to increase the iterations to improve the
bit field, determine the optimal TIA gain and LED current overall SNR. The entire multiple integration per ADC conversion
setting. When the TIA gain and LED current are set, measure process repeats NUM_REPEAT_x number of times. Increasing
how much of the integrator dynamic range is used to integrate NUM_REPEAT_x serves the same purpose as multiple pulses
the charge created by a single LED pulse. If the amount of in single integration mode, where n pulses improve the SNR by
integrator dynamic range used for a single pulse is less than half √n. In multiple integration mode, the SNR increases by √n,
the available dynamic range, it may be desirable to use multiple where n = NUM_REPEAT_x. The total number of LED pulses
integrations prior to an ADC conversion. For example, if the in this mode is equal to NUM_INT_x × NUM_REPEAT_x.
amount of integrator dynamic range used for a single pulse is
1/8 of the available dynamic range, set NUM_INT_x to 0x6 to

START OF TIME SLOT

PRECONDITION
PRE_WIDTH_x CALCULATED
(DEFAULT 8µs) LED_OFFSET_x PERIOD
LED_WIDTH_x

LED

TIA OUTPUT

BPF OUTPUT

INTEG_OFFSET_x + INTEG_FINE_OFFSET_x
INTEGRATOR
SEQUENCE + – + – + – + –
INTEG_WIDTH_x
INTEGRATOR
OUTPUT

ADC CONVERT
17335-043

NUM_INT_x
NUM_REPEAT_x TIMES

Figure 40. Multiple Integration Mode with LED as Stimulus

Rev. A | Page 33 of 82
ADPD4000/ADPD4001 Data Sheet
Table 22. Relevant Settings for Multiple Integration Mode
Time Slot A
Group Register Address1 Bit Field Name Description
Multiple Integration 0x0100 SAMPLE_TYPE_x Leave at the default setting (0) for default sampling mode.
Mode Using LED 0x0101 AFE_PATH_CFG_x Set to 0x1DA for TIA, BPF, integrator, and ADC.
as Stimulus
0x0102 INPxx_x Enable desired inputs.
0x0103 PRECON_x Set to 0x5 to precondition anode of the photodiode to TIA_VREF.
0x0103 VCx_SEL_x Set to 0x2 to set ~250 mV reverse bias across photodiode.
0x0104 TIA_GAIN_CHx_x Select TIA gain.
0x0104 AFE_TRIM_VREF_x Set to 0x3 to set TIA_VREF = 1.27 V for maximum dynamic range.
Timing 0x0107 NUM_INT_x Set to a number that utilizes most of the dynamic range of integrator
available, leaving some margin for fluctuations in input level.
0x0107 NUM_REPEAT_x Set NUM_REPEAT_x to the number of times to repeat the multiple
integration sequence. SNR increases by a factor of √(NUM_REPEAT_x). Total
number of pulses is equal to NUM_REPEAT_x × NUM_INT_x.
0x010A INTEG_WIDTH_x Integration time in µs. Set to LED_WIDTH_x + 1.
0x010B INTEG_OFFSET_x, Integration sequence start time = INTEG_OFFSET_x +
INTEG_FINE_OFFSET_x INTEG_FINE_OFFSET_x. Optimize as described in the Optimizing Position of
Integration Sequence section.
LED Settings 0x0105, 0x0106 LED_DRIVESIDEx_x Select LED for time slot used.
0x0105, 0x0106 LED_CURRENTx_x Set LED current for selected LED.
0x0109 LED_OFFSET_x Sets start time of first LED pulse in 1 μs increments. 0x10 default (16 μs).
0x0109 LED_WIDTH_x Sets width of LED pulse in 1μs increments. 2 μs or 3 μs recommended.
1
This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for
SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120, For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at
Address 0x0160, and so on.

DIGITAL INTEGRATION MODE in the dark output data registers. Both signal and dark values
The ADPD4000/ADPD4001 support a digital integration mode can be written to the FIFO.
to accommodate sensors that require longer pulses than can be The ADPD4000/ADPD4001 support one-region and two-region
supported in the typical analog integration modes. Digital digital integration modes. In one-region digital integration
integration mode also allows the system to use a larger LED mode, an equal number of dark and lit samples are taken where
duty cycle than the analog integration modes, which may result all of the dark samples are taken in the dark region just prior to
in the highest achievable levels of SNR. the lit region. One-region digital integration mode is illustrated
RF in the timing diagram in Figure 42. In two-region digital
INx integration mode, an equal number of dark and lit samples are
TIA BUF ADC taken. However, the dark region is split such that half of the
TIA_VREF
samples are taken in the dark region prior to the lit region, and
the other half is taken in the dark region following the lit region.
17335-044

VCx RF
The two-region digital integration mode results in higher
Figure 41. Signal Path for Digital Integration Mode
ambient light rejection than the one-region digital integration
mode in situations with a varying ambient light level. A timing
In digital integration mode, the BPF is bypassed and the diagram for two-region digital integration mode is shown in
integrator is configured as a buffer, resulting in the signal path Figure 43.
shown in Figure 41. Digital integration regions are configured
Table 23 shows the relevant register settings for the digital
by the user and separated into lit and dark regions. The LED is
integration modes of operation. Note that only a single channel
pulsed in the lit region, and the LED is off in the dark region.
can be used in digital integration mode. Two channels are not
ADC samples are taken at 1 μs intervals within the lit and dark
supported for digital integration mode of operation. The MIN_
regions and are then digitally integrated. The integration of the
PERIOD_x bit field must also be manually set with the correct
ADC samples from the dark region is subtracted from the
period because the minimum period is not automatically
integration of the ADC samples from the lit region and the
calculated in digital integration mode.
result is written into the relevant signal output data registers.
The sum of the samples from just the dark region are available

Rev. A | Page 34 of 82
Data Sheet ADPD4000/ADPD4001
START OF TIME SLOT
PRECONDITION
MIN_PERIOD_x (MUST BE SET,
NOT AUTOMATICALLY CALCULATED)
LED_OFFSET_x LED_WIDTH_x
LED PRECONDITION
PRE_WIDTH_x

ADC
CONVERSIONS

17335-045
DARK1_OFFSET_x NUM_INT_x NUM_INT_x
LIT_OFFSET_x
NUM_REPEAT_x

Figure 42. One-Region Digital Integration Mode Timing Diagram

START OF TIME SLOT
PRECONDITION
MIN_PERIOD_x (MUST BE SET,
NOT AUTOMATICALLY CALCULATED)
LED_OFFSET_x LED_WIDTH_x
PRECONDITION
LED PRE_WIDTH_x

ADC CONVERSIONS

DARK1_OFFSET_x NUM_INT_x 2 × NUM_INT_x

LIT_OFFSET_x

17335-046
DARK2_OFFSET_x
NUM_REPEAT_x

Figure 43. Two-Region Digital Integration Mode Timing Diagram

Table 23. Relevant Settings for Digital Integration Modes

Time Slot A
Group Register Address1 Bit Field Name Description
Signal Path 0x0100 SAMPLE_TYPE_x Set to 0x1 for one-region digital integration mode. Set to 0x2 for two-
Setup region digital integration mode.
0x0101 AFE_PATH_CFG_x Set to 0x0E6 for TIA, integrator, and ADC. Bypass BPF. Integrator is
automatically configured as a buffer when one-region or two-region digital
integration mode is selected.
0x0102 INPxx_x Enable desired inputs.
0x0103 PRECON_x Set to 0x5 to precondition anode of photodiode to TIA_VREF.
0x0103 VCx_SELECT_x Set to 0x2 to set ~250 mV reverse bias across photodiode.
0x0104 TIA_GAIN_CHx_x Select TIA gain.
0x0104 AFE_TRIM_VREF_x Set to 0x3 to set TIA_VREF = 1.265 V.
Timing 0x0107 NUM_INT_x Set to the number of desired ADC conversions in the dark and lit regions.
0x0107 NUM_REPEAT_x Number of sequence repeats.
0x0108 MIN_PERIOD_x Set the period. Automatic period calculation is not supported in digital
integration mode.
0x0113 LIT_OFFSET_x Set to the time of the first ADC conversion in the lit region.
0x0114 DARK1_OFFSET_x Set to the time of the first ADC conversion in the Dark 1 region.
0x0114 DARK2_OFFSET_x Set to the time of the first ADC conversion in the Dark 2 region. Only used
in two-region digital integration mode.
LED Settings 0x0105, 0x0106 LED_DRIVESIDEx_x Select LED for time slot used.
0x0105, 0x0106 LED_CURRENTx_x Set LED current for selected LED.
0x0109 LED_OFFSET_x Sets start time of first LED pulse in 1 μs increments.
0x0109 LED_WIDTH_x Sets width of LED pulse in 1 μs increments.
1
This is the Time Slot A register address. Add 0x020 for the identical register address for each subsequent time slot. For example, Register 0x0100 is the location for
SAMPLE_TYPE_A. For Time Slot B, this register is at Address 0x0120. For Time Slot C, this register is at Address 0x0140. For Time Slot D, this register is at
Address 0x0160, and so on.

Rev. A | Page 35 of 82
ADPD4000/ADPD4001 Data Sheet
Timing Recommendations for Digital Integration Modes The recommended TIA ADC mode is one in which the BPF is
When setting the timing for digital integration mode, it is bypassed and the integrator is configured as an inverting buffer.
important to place the ADC samples such that the signal being This mode is enabled by writing 0x0E6 to the AFE_PATH_
sampled is given time to settle prior to the sample being taken. CFG_x bit field (Register 0x0101, Bits[8:0] for Time Slot A), to
Settling time of the input signal is affected by photodiode enable a signal path that includes the TIA, integrator, and ADC.
capacitance and TIA settling time. Figure 44 shows an example Additionally, to configure the integrator as a buffer, set Bit 11 of
of proper placement of the ADC sampling edges. Calculations the INTEG_SETUP_x register (Register 0x010A, Bit 11 for
for the offset values are as follows: Time Slot A). With the ADC offset registers, ADC_OFF1_x and
ADC_OFF2_x, set to 0 and TIA_VREF set to 1.265 V, the output
DARK1_OFFSET_x = (LED_OFFSET_x – (NUM_INT_x + 1))
of the ADC is at ~3,000 codes for a single pulse and a zero input
Add a value of 1 to the number of ADC conversions such that current condition. As the input current from the photodiode
there is 1 μs of margin added to placement of the Dark 1 region increases, the ADC output increases toward 16,384 LSBs.
samples with respect to the beginning of the LED pulse.
When configuring the integrator as a buffer, there is the option
LIT_OFFSET_x = (LED_OFFSET_x + tD) of either using a gain of 1 or a gain of 0.7. Using the gain of 0.7
where tD is the delay built into the offset setting to allow settling increases the usable dynamic range at the input to the TIA.
time of the signal. This value must be characterized in the final However, it is possible to overrange the ADC in this configuration
application. and care must be taken to not saturate the ADC. To set the buffer
gain, use the AFE_TRIM_INT_x bit field, (Register 0x0104,
DARK2_OFFSET_x = (LED_OFFSET_x + LED_WIDTH_x + tD)
Bits[12:11] for Time Slot A). Setting this bit field to 0x0 or 0x1
This setting only applies to two-region digital integration mode. sets a gain of 1. Setting this bit field to 0x2 or 0x3 configures the
LED_OFFSET_x LED_WIDTH_x buffer with a gain of 0.7.
LED
OUTPUT Calculate the ADC output (ADCOUT) as follows:
TIA ADCOUT = 8192 − (((2 × TIA_VREF − 2 × IINPUT_TIA × RF −
OUTPUT
1.8 V)/146 µV/LSB) × Buffer Gain) (3)
ADC
SAMPLES where:
DARK1_OFFSET_x tD tD
TIA_VREF is the internal voltage reference signal for the TIA
17335-047

LIT_OFFSET_x
DARK2_OFFSET_x (the default value is 1.265 V).
Figure 44. Proper Placement of ADC Sampling Edges in Digital Integration Mode IINPUT_TIA is the input current to the TIA.
RF is the TIA feedback resistor.
TIA ADC MODE
Buffer Gain is either 0.7 or 1 based on the setting of
Figure 45 shows TIA ADC mode, which bypasses the BPF and AFE_TRIM_INT_x.
routes the TIA output through a buffer, directly into the ADC.
Equation 3 is an approximation and does not account for
TIA ADC mode is useful in applications, such as ambient light
internal offsets and gain errors. The calculation also assumes
sensing, and measuring other dc signals, such as leakage
that the ADC offset registers are set to 0
resistance. In photodiode measurement applications using the
BPF, all background light is blocked from the signal chain and, Configuring one time slot in TIA ADC mode is useful for
therefore, cannot be measured. TIA ADC mode can measure monitoring ambient and pulsed signals at the same time. The
the amount of background and ambient light. This mode can also ambient signal is monitored during the time slot configured for
measure currents from other dc sources, such as leakage TIA ADC mode, while the pulsed signal, with the ambient
resistance. signal rejected, is monitored in the time slot configured for
RF
measuring the desired LED pulsed signal.

INx
Protecting Against TIA Saturation in Normal Operation
TIA_VREF TIA BUF ADC
One of the reasons to monitor TIA ADC mode is to protect
against environments that may cause saturation. One concern
when operating in high light conditions, especially with larger
17335-054

RF

photodiodes, is that the TIA stage may become saturated while

Figure 45. TIA ADC Mode Block Diagram the ADPD4000/ADPD4001 continue to communicate data. The
When the devices are in TIA ADC mode, the BPF is bypassed resulting saturation is not typical. The TIA, based on its settings,
and the integrator stage is reconfigured as a buffer. If both can only handle a certain level of photodiode current. Based on
Channel 1 and Channel 2 are enabled in a single time slot, the the way the ADPD4000/ADPD4001 are configured, if there is a
ADC samples Channel 1 and then Channel 2 in sequential current level from the photodiode that is larger than the TIA can
order in 1 µs intervals. handle, the TIA output during the LED pulse effectively extends
the current pulse, making it wider. The AFE timing is then violated
Rev. A | Page 36 of 82
Data Sheet ADPD4000/ADPD4001
because the positive portion of the BPF output extends into the result in saturation if light conditions change. A safe operating
negative section of the integration window. Thus, the photosignal region is typically at ¾ full scale and lower. The ADC resolution
is subtracted from itself, causing the output signal to decrease when operating in TIA ADC mode with a buffer gain = 1 is
when the effective light signal increases. shown in Table 24. These codes are not the same as in modes
To measure the response from the TIA and verify that this stage with the BPF and integrator enabled because the BPF and
is not saturating, place the device in TIA ADC mode and slightly integrator are not unity-gain elements.
modify the timing. Specifically, sweep INTEG_OFFSET_x until Table 24. ADC Resolution in TIA ADC Mode
a maximum is achieved. This procedure aligns the ADC
TIA Gain (kΩ) ADC Resolution (nA/LSB)
sampling time with the LED pulse to measure the total amount of
12.5 5.84
light falling on the photodetector (for example, background light
25 2.92
and LED pulse).
50 1.46
If this minimum value is below 16,384 LSBs, the TIA is not 100 0.73
saturated. However, take care, because even if the result is not 200 0.37
16,384 LSBs, operating the device near saturation can quickly

Rev. A | Page 37 of 82
ADPD4000/ADPD4001 Data Sheet

REGISTER MAP
Table 25. ADPD4000 Register Map Summary
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x0000 FIFO_ [15:8] CLEAR_FIFO INT_FIFO_ INT_FIFO_ Reserved FIFO_BYTE_COUNT[10:8] 0x0000 R/W
STATUS UFLOW OFLOW
[7:0] FIFO_BYTE_COUNT[7:0]
0x0001 INT_ [15:8] INT_FIFO_TH Reserved INT_ INT_ INT_ INT_ 0x0000 R/W
STATUS_ DATA_L DATA_K DATA_J DATA_I
DATA [7:0] INT_DATA_H INT_DATA_G INT_ INT_ INT_ INT_ INT_ INT_
DATA_F DATA_E DATA_D DATA_C DATA_B DATA_A
0x0002 INT_ [15:8] Reserved INT_LEV0_L INT_ INT_ INT_ 0x0000 R/W
STATUS_ LEV0_K LEV0_J LEV0_I
LEV0 [7:0] INT_LEV0_H INT_LEV0_G INT_ INT_ INT_LEV0_D INT_ INT_ INT_
LEV0_F LEV0_E LEV0_C LEV0_B LEV0_A
0x0003 INT_ [15:8] Reserved INT_LEV1_L INT_ INT_ INT_ 0x0000 R/W
STATUS_ LEV1_K LEV1_J LEV1_I
LEV1 [7:0] INT_LEV1_H INT_LEV1_G INT_ INT_ INT_LEV1_D INT_ INT_ INT_
LEV1_F LEV1_E LEV1_C LEV1_B LEV1_A
0x0006 FIFO_TH [15:8] Reserved 0x0000 R/W
[7:0] FIFO_TH[7:0]
0x0007 INT_ACLEAR [15:8] INT_ Reserved INT_ INT_ INT_ INT_ 0x8FFF R/W
ACLEAR_ ACLEAR_ ACLEAR_ ACLEAR_ ACLEAR_
FIFO DATA_L DATA_K DATA_J DATA_I
[7:0] INT_ INT_ INT_ INT_ INT_ INT_ INT_ INT_
ACLEAR_ ACLEAR_ ACLEAR_ ACLEAR_ ACLEAR_ ACLEAR_ ACLEAR_ ACLEAR_
DATA_H DATA_G DATA_F DATA_E DATA_D DATA_C DATA_B DATA_A
0x0008 CHIP_ID [15:8] Version 0x00C0 R
[7:0] CHIP_ID
0x0009 OSC32M [15:8] Reserved 0x0090 R/W
[7:0] OSC_32M_FREQ_ADJ[7:0]
0x000A OSC32M_ [15:8] OSC_32M_ OSC_32M_CAL_COUNT[14:8] 0x0000 R/W
CAL CAL_START
[7:0] OSC_32M_CAL_COUNT[7:0]
0x000B OSC1M [15:8] Reserved OSC_1M_FREQ_ 0x02B2 R/W
ADJ[9:8]
[7:0] OSC_1M_FREQ_ADJ[7:0]
0x000C OSC32K [15:8] CAPTURE_ Reserved 0x0012 R/W
TIMESTAMP
[7:0] Reserved OSC_32K_ADJUST[5:0]
0x000D TS_FREQ [15:8] TIMESLOT_PERIOD_L[15:8] 0x2710 R/W
[7:0] TIMESLOT_PERIOD_L[7:0]
0x000E TS_FREQH [15:8] Reserved 0x0000 R/W
[7:0] Reserved TIMESLOT_PERIOD_H[7:0]
0x000F SYS_CTL [15:8] SW_RESET Reserved ALT_CLOCKS[1:0] 0x0000 R/W
[7:0] ALT_CLK_GPIO[1:0] Reserved LFOSC_ OSC_ OSC_
SEL 1M_EN 32K_EN
0x0010 OPMODE [15:8] Reserved TIMESLOT_EN[3:0] 0x0000 R/W
[7:0] Reserved OP_
MODE
0x0011 STAMP_L [15:8] TIMESTAMP_COUNT_L[15:8] 0x0000 R
[7:0] TIMESTAMP_COUNT_L[7:0]
0x0012 STAMP_H [15:8] TIMESTAMP_COUNT_H[15:8] 0x0000 R
[7:0] TIMESTAMP_COUNT_H[7:0]
0x0013 STAMPDELTA [15:8] TIMESTAMP_SLOT_DELTA[15:8] 0x0000 R
[7:0] TIMESTAMP_SLOT_DELTA[7:0]
0x0014 INT_ENABLE_ [15:8] INTX_EN_ INTX_EN_ INTX_EN_ Reserved INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ 0x0000 R/W
XD FIFO_TH FIFO_ FIFO_ DATA_L DATA_K DATA_J DATA_I
UFLOW OFLOW
[7:0] INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_
DATA_H DATA_G DATA_F DATA_E DATA_D DATA_C DATA_B DATA_A
Rev. A | Page 38 of 82
Data Sheet ADPD4000/ADPD4001
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x0015 INT_ENABLE_ [15:8] INTY_EN_ INTY_EN_ INTY_EN_ Reserved INTY_EN_ INTY_EN_ INTY_EN_ INTY_ EN_ 0x0000 R/W
YD FIFO_TH FIFO_ FIFO_ DATA_L DATA_K DATA_J DATA_I
UFLOW OFLOW
[7:0] INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_
INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_
DATA_H DATA_G DATA_F DATA_E
DATA_D DATA_C DATA_B DATA_A
0x0016 INT_ENABLE_ [15:8] Reserved INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ 0x0000 R/W
XL0 LEV0_L LEV0_K LEV0_J LEV0_I
[7:0] INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_
LEV0_H LEV0_G LEV0_F LEV0_E LEV0_D LEV0_C LEV0_B LEV0_A
0x0017 INT_ENABLE_ [15:8] Reserved INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ 0x0000 R/W
XL1 LEV1_L LEV1_K LEV1_J LEV1_I
[7:0] INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_ INTX_EN_
LEV1_H LEV1_G LEV1_F LEV1_E LEV1_D LEV1_C LEV1_B LEV1_A
0x001A INT_ENABLE_ [15:8] Reserved INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_ 0x0000 R/W
YL0 LEV0_L LEV0_K LEV0_J LEV0_I
[7:0] INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_
LEV0_H LEV0_G LEV0_F LEV0_E LEV0_D LEV0_C LEV0_B LEV0_A
0x001B INT_ENABLE_ [15:8] Reserved INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_ 0x0000 R/W
YL1 LEV1_L LEV1_K LEV1_J LEV1_I
[7:0] INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_ INTY_EN_
LEV1_H LEV1_G LEV1_F LEV1_E LEV1_D LEV1_C LEV1_B LEV1_A
0x001E FIFO_ [15:8] Reserved 0x0000 R/W
STATUS_ [7:0] Reserved ENA_ ENA_ ENA_STAT_ ENA_ ENA_ ENA_
BYTES STAT_LX STAT_L1 L0 STAT_D2 STAT_D1 STAT_
SUM
0x0020 INPUT_SLEEP [15:8] INP_SLEEP_78[3:0] INP_SLEEP_56[3:0] 0x0000 R/W
[7:0] INP_SLEEP_34[3:0] INP_SLEEP_12[3:0]
0x0021 INPUT_CFG [15:8] Reserved 0x0000 R/W
[7:0] VC2_SLEEP[1:0] VC1_SLEEP[1:0] PAIR78 PAIR56 PAIR34 PAIR12
0x0022 GPIO_CFG [15:8] GPIO_SLEW[1:0] GPIO_DRV[1:0] GPIO_PIN_CFG3[2:0] GPIO_PIN 0x0000 R/W
_CFG2[2]
[7:0] GPIO_PIN_CFG2[1:0] GPIO_PIN_CFG1[2:0] GPIO_PIN_CFG0[2:0]
0x0023 GPIO01 [15:8] Reserved GPIOOUT1[6:0] 0x0000 R/W
[7:0] Reserved GPIOOUT0[6:0]
0x0024 GPIO23 [15:8] Reserved GPIOOUT3[6:0] 0x0000 R/W
[7:0] Reserved GPIOOUT2[6:0]
0x0025 GPIO_IN [15:8] Reserved 0x0000 R
[7:0] Reserved GPIO_INPUT[3:0]
0x0026 GPIO_EXT [15:8] Reserved 0x0000 R/W
[7:0] TIMESTAMP_ TIMESTAMP_ TIMESTAMP_GPIO[1:0] Reserved EXT_ EXT_SYNC_GPIO[1:0]
INV ALWAYS_EN SYNC_EN
0x002E DATA_ [15:8] Reserved HOLD_ HOLD_ HOLD_ HOLD_ 0x0000 R/W
HOLD_FLAG REGS_L REGS_K REGS_J REGS_I
[7:0] HOLD_ HOLD_REGS_ HOLD_ HOLD_ HOLD_ HOLD_ HOLD_ HOLD_
REGS_H G REGS_F REGS_E REGS_D REGS_C REGS_B REGS_A
0x002F FIFO_DATA [15:8] FIFO_DATA[15:8] 0x0000 R
[7:0] FIFO_DATA[7:0]
0x0030 SIGNAL1_L_A [15:8] SIGNAL1_L_A[15:8] 0x0000 R
[7:0] SIGNAL1_L_A[7:0]
0x0031 SIGNAL1_H_A [15:8] SIGNAL1_H_A[15:8] 0x0000 R
[7:0] SIGNAL1_H_A[7:0]
0x0032 SIGNAL2_L_A [15:8] SIGNAL2_L_A[15:8] 0x0000 R
[7:0] SIGNAL2_L_A[7:0]
0x0033 SIGNAL2_H_A [15:8] SIGNAL2_H_A[15:8] 0x0000 R
[7:0] SIGNAL2_H_A[7:0]
0x0034 DARK1_L_A [15:8] DARK1_L_A[15:8] 0x0000 R
[7:0] DARK1_L_A[7:0]
0x0035 DARK1_H_A [15:8] DARK1_H_A[15:8] 0x0000 R
[7:0] DARK1_H_A[7:0]

Rev. A | Page 39 of 82
ADPD4000/ADPD4001 Data Sheet
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x0036 DARK2_L_A [15:8] DARK2_L_A[15:8] 0x0000 R
[7:0] DARK2_L_A[7:0]
0x0037 DARK2_H_A [15:8] DARK2_H_A[15:8] 0x0000 R
[7:0] DARK2_H_A[7:0]
0x0038 SIGNAL1_L_B [15:8] SIGNAL1_L_B[15:8] 0x0000 R
[7:0] SIGNAL1_L_B[7:0]
0x0039 SIGNAL1_H_B [15:8] SIGNAL1_H_B[15:8] 0x0000 R
[7:0] SIGNAL1_H_B[7:0]
0x003A SIGNAL2_L_B [15:8] SIGNAL2_L_B[15:8] 0x0000 R
[7:0] SIGNAL2_L_B[7:0]
0x003B SIGNAL2_H_B [15:8] SIGNAL2_H_B[15:8] 0x0000 R
[7:0] SIGNAL2_H_B[7:0]
0x003C DARK1_L_B [15:8] DARK1_L_B[15:8] 0x0000 R
[7:0] DARK1_L_B[7:0]
0x003D DARK1_H_B [15:8] DARK1_H_B[15:8] 0x0000 R
[7:0] DARK1_H_B[7:0]
0x003E DARK2_L_B [15:8] DARK2_L_B[15:8] 0x0000 R
[7:0] DARK2_L_B[7:0]
0x003F DARK2_H_B [15:8] DARK2_H_B[15:8] 0x0000 R
[7:0] DARK2_H_B[7:0]
0x0040 SIGNAL1_L_C [15:8] SIGNAL1_L_C[15:8] 0x0000 R
[7:0] SIGNAL1_L_C[7:0]
0x0041 SIGNAL1_H_C [15:8] SIGNAL1_H_C[15:8] 0x0000 R
[7:0] SIGNAL1_H_C[7:0]
0x0042 SIGNAL2_L_C [15:8] SIGNAL2_L_C[15:8] 0x0000 R
[7:0] SIGNAL2_L_C[7:0]
0x0043 SIGNAL2_H_C [15:8] SIGNAL2_H_C[15:8] 0x0000 R
[7:0] SIGNAL2_H_C[7:0]
0x0044 DARK1_L_C [15:8] DARK1_L_C[15:8] 0x0000 R
[7:0] DARK1_L_C[7:0]
0x0045 DARK1_H_C [15:8] DARK1_H_C[15:8] 0x0000 R
[7:0] DARK1_H_C[7:0]
0x0046 DARK2_L_C [15:8] DARK2_L_C[15:8] 0x0000 R
[7:0] DARK2_L_C[7:0]
0x0047 DARK2_H_C [15:8] DARK2_H_C[15:8] 0x0000 R
[7:0] DARK2_H_C[7:0]
0x0048 SIGNAL1_L_D [15:8] SIGNAL1_L_D[15:8] 0x0000 R
[7:0] SIGNAL1_L_D[7:0]
0x0049 SIGNAL1_H_D [15:8] SIGNAL1_H_D[15:8] 0x0000 R
[7:0] SIGNAL1_H_D[7:0]
0x004A SIGNAL2_L_D [15:8] SIGNAL2_L_D[15:8] 0x0000 R
[7:0] SIGNAL2_L_D[7:0]
0x004B SIGNAL2_H_D [15:8] SIGNAL2_H_D[15:8] 0x0000 R
[7:0] SIGNAL2_H_D[7:0]
0x004C DARK1_L_D [15:8] DARK1_L_D[15:8] 0x0000 R
[7:0] DARK1_L_D[7:0]
0x004D DARK1_H_D [15:8] DARK1_H_D[15:8] 0x0000 R
[7:0] DARK1_H_D[7:0]
0x004E DARK2_L_D [15:8] DARK2_L_D[15:8] 0x0000 R
[7:0] DARK2_L_D[7:0]
0x004F DARK2_H_D [15:8] DARK2_H_D[15:8] 0x0000 R
[7:0] DARK2_H_D[7:0]
0x0050 SIGNAL1_L_E [15:8] SIGNAL1_L_E[15:8] 0x0000 R
[7:0] SIGNAL1_L_E[7:0]
0x0051 SIGNAL1_H_E [15:8] SIGNAL1_H_E[15:8] 0x0000 R
[7:0] SIGNAL1_H_E[7:0]

Rev. A | Page 40 of 82
Data Sheet ADPD4000/ADPD4001
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x0052 SIGNAL2_L_E [15:8] SIGNAL2_L_E[15:8] 0x0000 R
[7:0] SIGNAL2_L_E[7:0]
0x0053 SIGNAL2_H_E [15:8] SIGNAL2_H_E[15:8] 0x0000 R
[7:0] SIGNAL2_H_E[7:0]
0x0054 DARK1_L_E [15:8] DARK1_L_E[15:8] 0x0000 R
[7:0] DARK1_L_E[7:0]
0x0055 DARK1_H_E [15:8] DARK1_H_E[15:8] 0x0000 R
[7:0] DARK1_H_E[7:0]
0x0056 DARK2_L_E [15:8] DARK2_L_E[15:8] 0x0000 R
[7:0] DARK2_L_E[7:0]
0x0057 DARK2_H_E [15:8] DARK2_H_E[15:8] 0x0000 R
[7:0] DARK2_H_E[7:0]
0x0058 SIGNAL1_L_F [15:8] SIGNAL1_L_F[15:8] 0x0000 R
[7:0] SIGNAL1_L_F[7:0]
0x0059 SIGNAL1_H_F [15:8] SIGNAL1_H_F[15:8] 0x0000 R
[7:0] SIGNAL1_H_F[7:0]
0x005A SIGNAL2_L_F [15:8] SIGNAL2_L_F[15:8] 0x0000 R
[7:0] SIGNAL2_L_F[7:0]
0x005B SIGNAL2_H_F [15:8] SIGNAL2_H_F[15:8] 0x0000 R
[7:0] SIGNAL2_H_F[7:0]
0x005C DARK1_L_F [15:8] DARK1_L_F[15:8] 0x0000 R
[7:0] DARK1_L_F[7:0]
0x005D DARK1_H_F [15:8] DARK1_H_F[15:8] 0x0000 R
[7:0] DARK1_H_F[7:0]
0x005E DARK2_L_F [15:8] DARK2_L_F[15:8] 0x0000 R
[7:0] DARK2_L_F[7:0]
0x005F DARK2_H_F [15:8] DARK2_H_F[15:8] 0x0000 R
[7:0] DARK2_H_F[7:0]
0x0060 SIGNAL1_L_G [15:8] SIGNAL1_L_G[15:8] 0x0000 R
[7:0] SIGNAL1_L_G[7:0]
0x0061 SIGNAL1_H_G [15:8] SIGNAL1_H_G[15:8] 0x0000 R
[7:0] SIGNAL1_H_G[7:0]
0x0062 SIGNAL2_L_G [15:8] SIGNAL2_L_G[15:8] 0x0000 R
[7:0] SIGNAL2_L_G[7:0]
0x0063 SIGNAL2_H_G [15:8] SIGNAL2_H_G[15:8] 0x0000 R
[7:0] SIGNAL2_H_G[7:0]
0x0064 DARK1_L_G [15:8] DARK1_L_G[15:8] 0x0000 R
[7:0] DARK1_L_G[7:0]
0x0065 DARK1_H_G [15:8] DARK1_H_G[15:8] 0x0000 R
[7:0] DARK1_H_G[7:0]
0x0066 DARK2_L_G [15:8] DARK2_L_G[15:8] 0x0000 R
[7:0] DARK2_L_G[7:0]
0x0067 DARK2_H_G [15:8] DARK2_H_G[15:8] 0x0000 R
[7:0] DARK2_H_G[7:0]
0x0068 SIGNAL1_L_H [15:8] SIGNAL1_L_H[15:8] 0x0000 R
[7:0] SIGNAL1_L_H[7:0]
0x0069 SIGNAL1_H_H [15:8] SIGNAL1_H_H[15:8] 0x0000 R
[7:0] SIGNAL1_H_H[7:0]
0x006A SIGNAL2_L_H [15:8] SIGNAL2_L_H[15:8] 0x0000 R
[7:0] SIGNAL2_L_H[7:0]
0x006B SIGNAL2_H_H [15:8] SIGNAL2_H_H[15:8] 0x0000 R
[7:0] SIGNAL2_H_H[7:0]
0x006C DARK1_L_H [15:8] DARK1_L_H[15:8] 0x0000 R
[7:0] DARK1_L_H[7:0]
0x006D DARK1_H_H [15:8] DARK1_H_H[15:8] 0x0000 R
[7:0] DARK1_H_H[7:0]

Rev. A | Page 41 of 82
ADPD4000/ADPD4001 Data Sheet
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x006E DARK2_L_H [15:8] DARK2_L_H[15:8] 0x0000 R
[7:0] DARK2_L_H[7:0]
0x006F DARK2_H_H [15:8] DARK2_H_H[15:8] 0x0000 R
[7:0] DARK2_H_H[7:0]
0x0070 SIGNAL1_L_I [15:8] SIGNAL1_L_I[15:8] 0x0000 R
[7:0] SIGNAL1_L_I[7:0]
0x0071 SIGNAL1_H_I [15:8] SIGNAL1_H_I[15:8] 0x0000 R
[7:0] SIGNAL1_H_I[7:0]
0x0072 SIGNAL2_L_I [15:8] SIGNAL2_L_I[15:8] 0x0000 R
[7:0] SIGNAL2_L_I[7:0]
0x0073 SIGNAL2_H_I [15:8] SIGNAL2_H_I[15:8] 0x0000 R
[7:0] SIGNAL2_H_I[7:0]
0x0074 DARK1_L_I [15:8] DARK1_L_I[15:8] 0x0000 R
[7:0] DARK1_L_I[7:0]
0x0075 DARK1_H_I [15:8] DARK1_H_I[15:8] 0x0000 R
[7:0] DARK1_H_I[7:0]
0x0076 DARK2_L_I [15:8] DARK2_L_I[15:8] 0x0000 R
[7:0] DARK2_L_I[7:0]
0x0077 DARK2_H_I [15:8] DARK2_H_I[15:8] 0x0000 R
[7:0] DARK2_H_I[7:0]
0x0078 SIGNAL1_L_J [15:8] SIGNAL1_L_J[15:8] 0x0000 R
[7:0] SIGNAL1_L_J[7:0]
0x0079 SIGNAL1_H_J [15:8] SIGNAL1_H_J[15:8] 0x0000 R
[7:0] SIGNAL1_H_J[7:0]
0x007A SIGNAL2_L_J [15:8] SIGNAL2_L_J[15:8] 0x0000 R
[7:0] SIGNAL2_L_J[7:0]
0x007B SIGNAL2_H_J [15:8] SIGNAL2_H_J[15:8] 0x0000 R
[7:0] SIGNAL2_H_J[7:0]
0x007C DARK1_L_J [15:8] DARK1_L_J[15:8] 0x0000 R
[7:0] DARK1_L_J[7:0]
0x007D DARK1_H_J [15:8] DARK1_H_J[15:8] 0x0000 R
[7:0] DARK1_H_J[7:0]
0x007E DARK2_L_J [15:8] DARK2_L_J[15:8] 0x0000 R
[7:0] DARK2_L_J[7:0]
0x007F DARK2_H_J [15:8] DARK2_H_J[15:8] 0x0000 R
[7:0] DARK2_H_J[7:0]
0x0080 SIGNAL1_L_K [15:8] SIGNAL1_L_K[15:8] 0x0000 R
[7:0] SIGNAL1_L_K[7:0]
0x0081 SIGNAL1_H_K [15:8] SIGNAL1_H_K[15:8] 0x0000 R
[7:0] SIGNAL1_H_K[7:0]
0x0082 SIGNAL2_L_K [15:8] SIGNAL2_L_K[15:8] 0x0000 R
[7:0] SIGNAL2_L_K[7:0]
0x0083 SIGNAL2_H_K [15:8] SIGNAL2_H_K[15:8] 0x0000 R
[7:0] SIGNAL2_H_K[7:0]
0x0084 DARK1_L_K [15:8] DARK1_L_K[15:8] 0x0000 R
[7:0] DARK1_L_K[7:0]
0x0085 DARK1_H_K [15:8] DARK1_H_K[15:8] 0x0000 R
[7:0] DARK1_H_K[7:0]
0x0086 DARK2_L_K [15:8] DARK2_L_K[15:8] 0x0000 R
[7:0] DARK2_L_K[7:0]
0x0087 DARK2_H_K [15:8] DARK2_H_K[15:8] 0x0000 R
[7:0] DARK2_H_K[7:0]
0x0088 SIGNAL1_L_L [15:8] SIGNAL1_L_L[15:8] 0x0000 R
[7:0] SIGNAL1_L_L[7:0]
0x0089 SIGNAL1_H_L [15:8] SIGNAL1_H_L[15:8] 0x0000 R
[7:0] SIGNAL1_H_L[7:0]

Rev. A | Page 42 of 82
Data Sheet ADPD4000/ADPD4001
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x008A SIGNAL2_L_L [15:8] SIGNAL2_L_L[15:8] 0x0000 R
[7:0] SIGNAL2_L_L[7:0]
0x008B SIGNAL2_H_L [15:8] SIGNAL2_H_L[15:8] 0x0000 R
[7:0] SIGNAL2_H_L[7:0]
0x008C DARK1_L_L [15:8] DARK1_L_L[15:8] 0x0000 R
[7:0] DARK1_L_L[7:0]
0x008D DARK1_H_L [15:8] DARK1_H_L[15:8] 0x0000 R
[7:0] DARK1_H_L[7:0]
0x008E DARK2_L_L [15:8] DARK2_L_L[15:8] 0x0000 R
[7:0] DARK2_L_L[7:0]
0x008F DARK2_H_L [15:8] DARK2_H_L[15:8] 0x0000 R
[7:0] DARK2_H_L[7:0]
0x00B4 IO_ADJUST [15:8] Reserved (set to 0x005) 0x0050 R/W
[7:0] Reserved (set to 0x005) SPI_SLEW[1:0] SPI_DRV[1:0]
0x00B6 I2C_KEY [15:8] I2C_KEY_MATCH[3:0] I2C_KEY[11:8] 0x0000 R/W
[7:0] I2C_KEY[7:0]
0x00B7 I2C_ADDR [15:8] I2C_SLAVE_KEY2[7:0] 0x0048 R/W
[7:0] I2C_SLAVE_ADDR[6:0] Reserved
0x0100 TS_CTRL_A [15:8] Reserved CH2_EN_A SAMPLE_TYPE_A[1:0] INPUT_R_SELECT_A[1:0] TIMESLOT_OFFSET_ 0x0000 R/W
A[9:8]
[7:0] TIMESLOT_OFFSET_A[7:0]
0x0101 TS_PATH_A [15:8] PRE_WIDTH_A[3:0] Reserved AFE_ 0x41DA R/W
PATH_
CFG_A[8]
[7:0] AFE_PATH_CFG_A[7:0]
0x0102 INPUTS_A [15:8] INP78_A[3:0] INP56_A[3:0] 0x0000 R/W
[7:0] INP34_A[3:0] INP12_A[3:0]
0x0103 CATHODE_A [15:8] Reserved PRECON_A[2:0] VC2_PULSE_A[1:0] VC2_ALT_A[1:0] 0x0000 R/W
[7:0] VC2_SEL_A[1:0] VC1_PULSE_A[1:0] VC1_ALT_A[1:0] VC1_SEL_A[1:0]
0x0104 AFE_TRIM_A [15:8] Reserved (set to 0x7) AFE_TRIM_INT_A[1:0] VREF_ AFE_TRIM_VREF_ 0xE3C0 R/W
PULSE_A A[1:0]
[7:0] VREF_PULSE_VAL_A[1:0] TIA_GAIN_CH2_A[2:0] TIA_GAIN_CH1_A[2:0]
0x0105 LED_ [15:8] LED_ LED_CURRENT2_A[6:0] 0x0000 R/W
POW12_A DRIVESIDE2_
A
[7:0] LED_ LED_CURRENT1_A[6:0]
DRIVESIDE1_
A
0x0106 LED_ [15:8] LED_ LED_CURRENT4_A[6:0] 0x0000 R/W
POW34_A DRIVESIDE4_
A
[7:0] LED_ LED_CURRENT3_A[6:0]
DRIVESIDE3_
A
0x0107 COUNTS_A [15:8] NUM_INT_A[7:0] 0x0101 R/W
[7:0] NUM_REPEAT_A[7:0]
0x0108 PERIOD_A [15:8] Reserved MOD_TYPE_A[1:0] Reserved MIN_PERIOD_A[9:8] 0x0000 R/W
[7:0] MIN_PERIOD_A[7:0]
0x0109 LED_ [15:8] LED_WIDTH_A[7:0] 0x0210 R/W
PULSE_A [7:0] LED_OFFSET_A[7:0]
0x010A INTEG_ [15:8] SINGLE_ CH2_AMP_DISABLE_A[2:0] AFE_INT_ CH1_AMP_DISABLE_A[2:0] 0x0003 R/W
SETUP_A INTEG_A C_BUF_A
[7:0] ADC_COUNT_A[1:0] Reserved INTEG_WIDTH_A[4:0]
0x010B INTEG_OS_A [15:8] Reserved INTEG_FINE_OFFSET_A[4:0] 0x1410 R/W
[7:0] INTEG_OFFSET_A[7:0]
0x010C MOD_ [15:8] MOD_WIDTH_A[7:0] 0x0100 R/W
PULSE_A [7:0] MOD_OFFSET_A[7:0]
0x010D PATTERN_A [15:8] LED_DISABLE_A[3:0] MOD_DISABLE_A[3:0] 0x0000 R/W
[7:0] SUBTRACT_A[3:0] REVERSE_INTEG_A[3:0]

Rev. A | Page 43 of 82
ADPD4000/ADPD4001 Data Sheet
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x010E ADC_OFF1_A [15:8] Reserved CH1_ADC_ADJUST_A[13:8] 0x0000 R/W
[7:0] CH1_ADC_ADJUST_A[7:0]
0x010F ADC_OFF2_A [15:8] ZERO_ Reserved CH2_ADC_ADJUST_A[13:8] 0x0000 R/W
ADJUST_A
[7:0] CH2_ADC_ADJUST_A[7:0]
0x0110 DATA_ [15:8] DARK_SHIFT_A[4:0] DARK_SIZE_A[3:0] 0x0003 R/W
FORMAT_A [7:0] SIGNAL_SHIFT_A[4:0] SIGNAL_SIZE_A[3:0]
0x0112 DECIMATE_A [15:8] Reserved DECIMATE_FACTOR_A[6:4] 0x0000 R/W
[7:0] DECIMATE_FACTOR_A[3:0] DECIMATE_TYPE_A[3:0]
0x0113 DIGINT_ [15:8] Reserved LIT_ 0x0026 R/W
LIT_A OFFSET_
A[8]
[7:0] LIT_OFFSET_A[7:0]
0x0114 DIGINT_ [15:8] DARK2_OFFSET_A[8:1] 0x2306 R/W
DARK_A [7:0] DARK2_ DARK1_OFFSET_A[6:0]
OFFSET_A[0]
0x0115 THRESH_ [15:8] Reserved 0x0000 R/W
CFG_A [7:0] THRESH1_ THRESH1_ THRESH1_TYPE_A[1:0] THRESH0_ THRESH0_ THRESH0_
CHAN_A DIR_A CHAN_A DIR_A TYPE_A[1:0]
0x0116 THRESH0_A [15:8] Reserved THRESH0_SHIFT_A[4:0] 0x0000 R/W
[7:0] THRESH0_VALUE_A[7:0]
0x0117 THRESH1_A [15:8] Reserved THRESH1_SHIFT_A[4:0] 0x0000 R/W
[7:0] THRESH1_VALUE_A[7:0]
0x0120 TS_CTRL_B [15:8] Reserved CH2_EN_B SAMPLE_TYPE_ B[1:0] INPUT_R_SELECT_B[1:0] TIMESLOT_ 0x0000 R/W
OFFSET_B[9:8]
[7:0] TIMESLOT_OFFSET_B[7:0]
0x0121 TS_PATH_B [15:8] PRE_WIDTH_B[3:0] Reserved AFE_ 0x41DA R/W
PATH_
CFG_B[8]
[7:0] AFE_PATH_CFG_B[7:0]
0x0122 INPUTS_B [15:8] INP78_B[3:0] INP56_B[3:0] 0x0000 R/W
[7:0] INP34_B[3:0] INP12_B[3:0]
0x0123 CATHODE_B [15:8] Reserved PRECON_B[2:0] VC2_PULSE_B[1:0] VC2_ALT_B[1:0] 0x0000 R/W
[7:0] VC2_SEL_B[1:0] VC1_PULSE_B[1:0] VC1_ALT_B[1:0] VC1_SEL_B[1:0]
0x0124 AFE_TRIM_B [15:8] Reserved (set to 0x7) AFE_TRIM_INT_B[1:0] VREF_ AFE_TRIM_ 0xE3C0 R/W
PULSE_B VREF_B[1:0]
[7:0] VREF_PULSE_VAL_B[1:0] TIA_GAIN_CH2_B[2:0] TIA_GAIN_CH1_B[2:0]
0x0125 LED_ [15:8] LED_ LED_CURRENT2_B[6:0] 0x0000 R/W
POW12_B DRIVESIDE2_
B
[7:0] LED_ LED_CURRENT1_B[6:0]
DRIVESIDE1_
B
0x0126 LED_ [15:8] LED_ LED_CURRENT4_B[6:0] 0x0000 R/W
POW34_B DRIVESIDE4_
B
[7:0] LED_ LED_CURRENT3_B[6:0]
DRIVESIDE3_
B
0x0127 COUNTS_B [15:8] NUM_INT_B[7:0] 0x0101 R/W
[7:0] NUM_REPEAT_B[7:0]
0x0128 PERIOD_B [15:8] Reserved MOD_TYPE_B[1:0] Reserved MIN_PERIOD_B[9:8] 0x0000 R/W
[7:0] MIN_PERIOD_B[7:0]
0x0129 LED_ [15:8] LED_WIDTH_B[7:0] 0x0210 R/W
PULSE_B [7:0] LED_OFFSET_B[7:0]
0x012A INTEG_ [15:8] SINGLE_ CH2_AMP_DISABLE_B[2:0] AFE_INT_C_ CH1_AMP_DISABLE_B[2:0] 0x0003 R/W
SETUP_B INTEG_B BUF_B
[7:0] ADC_COUNT_B[1:0] Reserved INTEG_WIDTH_B[4:0]
0x012B INTEG_OS_B [15:8] Reserved INTEG_FINE_OFFSET_B[4:0] 0x1410 R/W
[7:0] INTEG_OFFSET_B[7:0]

Rev. A | Page 44 of 82
Data Sheet ADPD4000/ADPD4001
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x012C MOD_ [15:8] MOD_WIDTH_B[7:0] 0x0100 R/W
PULSE_B [7:0] MOD_OFFSET_B[7:0]
0x012D PATTERN_B [15:8] LED_DISABLE_B[3:0] MOD_DISABLE_B[3:0] 0x0000 R/W
[7:0] SUBTRACT_B[3:0] REVERSE_INTEG_B[3:0]
0x012E ADC_OFF1_B [15:8] Reserved CH1_ADC_ADJUST_B[13:8] 0x0000 R/W
[7:0] CH1_ADC_ADJUST_B[7:0]
0x012F ADC_OFF2_B [15:8] ZERO_ Reserved CH2_ADC_ADJUST_B[13:8] 0x0000 R/W
ADJUST_B
[7:0] CH2_ADC_ADJUST_B[7:0]
0x0130 DATA_ [15:8] DARK_SHIFT_B[4:0] DARK_SIZE_B[2:0] 0x0003 R/W
FORMAT_B [7:0] SIGNAL_SHIFT_B[4:0] SIGNAL_SIZE_B[2:0]
0x0132 DECIMATE_B [15:8] Reserved DECIMATE_FACTOR_B[6:4] 0x0000 R/W
[7:0] DECIMATE_FACTOR_B[3:0] DECIMATE_TYPE_B[3:0]
0x0133 DIGINT_LIT_B [15:8] Reserved LIT_ 0x0026 R/W
OFFSET_
B[8]
[7:0] LIT_OFFSET_B[7:0]
0x0134 DIGINT_ [15:8] DARK2_OFFSET_B[8:1] 0x2306 R/W
DARK_B [7:0] DARK2_ DARK1_OFFSET_B[6:0]
OFFSET_B[0]
0x0135 THRESH_ [15:8] Reserved 0x0000 R/W
CFG_B
[7:0] THRESH1_ THRESH1_ THRESH1_TYPE_B[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_
CHAN_B DIR_B CHAN_B DIR_B B[1:0]
0x0136 THRESH0_B [15:8] Reserved THRESH0_SHIFT_B[4:0] 0x0000 R/W
[7:0] THRESH0_VALUE_B[7:0]
0x0137 THRESH1_B [15:8] Reserved THRESH1_SHIFT_B[4:0] 0x0000 R/W
[7:0] THRESH1_VALUE_B[7:0]
0x0140 TS_CTRL_C [15:8] Reserved CH2_EN_C SAMPLE_TYPE_C[1:0] INPUT_R_SELECT_C[1:0] TIMESLOT_OFFSET_ 0x0000 R/W
C[9:8]
[7:0] TIMESLOT_OFFSET_C[7:0]
0x0141 TS_PATH_C [15:8] PRE_WIDTH_C[3:0] Reserved AFE_PATH 0x41DA R/W
_CFG_C[8]
[7:0] AFE_PATH_CFG_C[7:0]
0x0142 INPUTS_C [15:8] INP78_C[3:0] INP56_C[3:0] 0x0000 R/W
[7:0] INP34_C[3:0] INP12_C[3:0]
0x0143 CATHODE_C [15:8] Reserved PRECON_C[2:0] VC2_PULSE_C[1:0] VC2_ALT_C[1:0] 0x0000 R/W
[7:0] VC2_SEL_C[1:0] VC1_PULSE_C[1:0] VC1_ALT_C[1:0] VC1_SEL_C[1:0]
0x0144 AFE_TRIM_C [15:8] Reserved (set to 0x7) AFE_TRIM_INT_C[1:0] VREF_ AFE_TRIM_ 0xE3C0 R/W
PULSE_C VREF_C[1:0]
[7:0] VREF_PULSE_VAL_C[1:0] TIA_GAIN_CH2_C[2:0] TIA_GAIN_CH1_C[2:0]
0x0145 LED_ [15:8] LED_ LED_CURRENT2_C[6:0] 0x0000 R/W
POW12_C DRIVESIDE2_
C
[7:0] LED_ LED_CURRENT1_C[6:0]
DRIVESIDE1_
C
0x0146 LED_ [15:8] LED_ LED_CURRENT4_C[6:0] 0x0000 R/W
POW34_C DRIVESIDE4_
C
[7:0] LED_ LED_CURRENT3_C[6:0]
DRIVESIDE3_
C
0x0147 COUNTS_C [15:8] NUM_INT_C[7:0] 0x0101 R/W
[7:0] NUM_REPEAT_C[7:0]
0x0148 PERIOD_C [15:8] Reserved MOD_TYPE_C[1:0] Reserved MIN_PERIOD_C[9:8] 0x0000 R/W
[7:0] MIN_PERIOD_C[7:0]
0x0149 LED_ [15:8] LED_WIDTH_C[7:0] 0x0210 R/W
PULSE_C [7:0] LED_OFFSET_C[7:0]

Rev. A | Page 45 of 82
ADPD4000/ADPD4001 Data Sheet
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x014A INTEG_ [15:8] SINGLE_ CH2_AMP_DISABLE_C[2:0] AFE_INT_C_ CH1_AMP_DISABLE_C[2:0] 0x0003 R/W
SETUP_C INTEG_C BUF_C
[7:0] ADC_COUNT_C[1:0] Reserved INTEG_WIDTH_C[4:0]
0x014B INTEG_OS_C [15:8] Reserved INTEG_FINE_OFFSET_C[4:0] 0x1410 R/W
[7:0] INTEG_OFFSET_C[7:0]
0x014C MOD_ [15:8] MOD_WIDTH_C[7:0] 0x0100 R/W
PULSE_C [7:0] MOD_OFFSET_C[7:0]
0x014D PATTERN_C [15:8] LED_DISABLE_C[3:0] MOD_DISABLE_C[3:0] 0x0000 R/W
[7:0] SUBTRACT_C[3:0] REVERSE_INTEG_C[3:0]
0x014E ADC_OFF1_C [15:8] Reserved CH1_ADC_ADJUST_C[13:8] 0x0000 R/W
[7:0] CH1_ADC_ADJUST_C[7:0]
0x014F ADC_OFF2_C [15:8] ZERO_ Reserved CH2_ADC_ADJUST_C[13:8] 0x0000 R/W
ADJUST_C
[7:0] CH2_ADC_ADJUST_C[7:0]
0x0150 DATA_ [15:8] DARK_SHIFT_C[4:0] DARK_SIZE_C[2:0] 0x0003 R/W
FORMAT_C
[7:0] SIGNAL_SHIFT_C[4:0] SIGNAL_SIZE_C[2:0]
0x0152 DECIMATE_C [15:8] Reserved DECIMATE_FACTOR_C[6:4] 0x0000 R/W
[7:0] DECIMATE_FACTOR_C[3:0] DECIMATE_TYPE_C[3:0]
0x0153 DIGINT_LIT_C [15:8] Reserved LIT_ 0x0026 R/W
OFFSET_
C[8]
[7:0] LIT_OFFSET_C[7:0]
0x0154 DIGINT_ [15:8] DARK2_OFFSET_C[8:1] 0x2306 R/W
DARK_C
[7:0] DARK2_ DARK1_OFFSET_C[6:0]
OFFSET_C[0]
0x0155 THRESH_ [15:8] Reserved 0x0000 R/W
CFG_C [7:0] THRESH1_ THRESH1_ THRESH1_TYPE_C[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_
CHAN_C DIR_C CHAN_C DIR_C C[1:0]
0x0156 THRESH0_C [15:8] Reserved THRESH0_SHIFT_C[4:0] 0x0000 R/W
[7:0] THRESH0_VALUE_C[7:0]
0x0157 THRESH1_C [15:8] Reserved THRESH1_SHIFT_C[4:0] 0x0000 R/W
[7:0] THRESH1_VALUE_C[7:0]
0x0160 TS_CTRL_D [15:8] Reserved CH2_EN_D SAMPLE_TYPE_D[1:0] INPUT_R_SELECT_D[1:0] TIMESLOT_OFFSET_ 0x0000 R/W
D[9:8]
[7:0] TIMESLOT_OFFSET_D[7:0]
0x0161 TS_PATH_D [15:8] PRE_WIDTH_D[3:0] Reserved AFE_ 0x41DA R/W
PATH_
CFG_D[8]
[7:0] AFE_PATH_CFG_D[7:0]
0x0162 INPUTS_D [15:8] INP78_D[3:0] INP56_D[3:0] 0x0000 R/W
[7:0] INP34_D[3:0] INP12_D[3:0]
0x0163 CATHODE_D [15:8] Reserved PRECON_D[2:0] VC2_PULSE_D[1:0] VC2_ALT_D[1:0] 0x0000 R/W
[7:0] VC2_SEL_D[1:0] VC1_PULSE_D[1:0] VC1_ALT_D[1:0] VC1_SEL_D[1:0]
0x0164 AFE_TRIM_D [15:8] Reserved (set to 0x7) AFE_TRIM_INT_D[1:0] VREF_ AFE_TRIM_VREF_ 0xE3C0 R/W
PULSE_D D[1:0]
[7:0] VREF_PULSE_VAL_D[1:0] TIA_GAIN_CH2_D[2:0] TIA_GAIN_CH1_D[2:0]
0x0165 LED_ [15:8] LED_ LED_CURRENT2_D[6:0] 0x0000 R/W
POW12_D DRIVESIDE2_
D
[7:0] LED_ LED_CURRENT1_D[6:0]
DRIVESIDE1_
D
0x0166 LED_ [15:8] LED_ LED_CURRENT4_D[6:0] 0x0000 R/W
POW34_D DRIVESIDE4_
D
[7:0] LED_ LED_CURRENT3_D[6:0]
DRIVESIDE3_
D

Rev. A | Page 46 of 82
Data Sheet ADPD4000/ADPD4001
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x0167 COUNTS_D [15:8] NUM_INT_D[7:0] 0x0101 R/W
[7:0] NUM_REPEAT_D[7:0]
0x0168 PERIOD_D [15:8] Reserved MOD_TYPE_D[1:0] Reserved MIN_PERIOD_D[9:8] 0x0000 R/W
[7:0] MIN_PERIOD_D[7:0]
0x0169 LED_ [15:8] LED_WIDTH_D[7:0] 0x0210 R/W
PULSE_D [7:0] LED_OFFSET_D[7:0]
0x016A INTEG_ [15:8] SINGLE_ CH2_AMP_DISABLE_D[2:0] AFE_INT_C_ CH1_AMP_DISABLE_D[2:0] 0x0003 R/W
SETUP_D INTEG_D BUF_D
[7:0] ADC_COUNT_D[1:0] Reserved INTEG_WIDTH_D[4:0]
0x016B INTEG_OS_D [15:8] Reserved INTEG_FINE_OFFSET_D[4:0] 0x1410 R/W
[7:0] INTEG_OFFSET_D[7:0]
0x016C MOD_ [15:8] MOD_WIDTH_D[7:0] 0x0100 R/W
PULSE_D [7:0] MOD_OFFSET_D[7:0]
0x016D PATTERN_D [15:8] LED_DISABLE_D[3:0] MOD_DISABLE_D[3:0] 0x0000 R/W
[7:0] SUBTRACT_D[3:0] REVERSE_INTEG_D[3:0]
0x016E ADC_OFF1_D [15:8] Reserved CH1_ADC_ADJUST_D[13:8] 0x0000 R/W
[7:0] CH1_ADC_ADJUST_D[7:0]
0x016F ADC_OFF2_D [15:8] ZERO_ Reserved CH2_ADC_ADJUST_D[13:8] 0x0000 R/W
ADJUST_D
[7:0] CH2_ADC_ADJUST_D[7:0]
0x0170 DATA_ [15:8] DARK_SHIFT_D[4:0] DARK_SIZE_D[2:0] 0x0003 R/W
FORMAT_D [7:0] SIGNAL_SHIFT_D[4:0] SIGNAL_SIZE_D[2:0]
0x0172 DECIMATE_D [15:8] Reserved DECIMATE_FACTOR_D[6:4] 0x0000 R/W
[7:0] DECIMATE_FACTOR_D[3:0] DECIMATE_TYPE_D[3:0]
0x0173 DIGINT_LIT_D [15:8] Reserved LIT_ 0x0026 R/W
OFFSET_
D[8]
[7:0] LIT_OFFSET_D[7:0]
0x0174 DIGINT_ [15:8] DARK2_OFFSET_D[8:1] 0x2306 R/W
DARK_D [7:0] DARK2_ DARK1_OFFSET_D[6:0]
OFFSET_D[0]
0x0175 THRESH_ [15:8] Reserved 0x0000 R/W
CFG_D [7:0] THRESH1_ THRESH1_ THRESH1_TYPE_D[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_D[1:0]
CHAN_D DIR_D CHAN_D DIR_D
0x0176 THRESH0_D [15:8] Reserved THRESH0_SHIFT_D[4:0] 0x0000 R/W
[7:0] THRESH0_VALUE_D[7:0]
0x0177 THRESH1_D [15:8] Reserved THRESH1_SHIFT_D[4:0] 0x0000 R/W
[7:0] THRESH1_VALUE_D[7:0]
0x0180 TS_CTRL_E [15:8] Reserved CH2_EN_E SAMPLE_TYPE_E[1:0] INPUT_R_SELECT_E[1:0] TIMESLOT_OFFSET_ 0x0000 R/W
E[9:8]
[7:0] TIMESLOT_OFFSET_E[7:0]
0x0181 TS_PATH_E [15:8] PRE_WIDTH_E[3:0] Reserved AFE_PATH 0x41DA R/W
_CFG_E[8]
[7:0] AFE_PATH_CFG_E[7:0]
0x0182 INPUTS_E [15:8] INP78_E[3:0] INP56_E[3:0] 0x0000 R/W
[7:0] INP34_E[3:0] INP12_E[3:0]
0x0183 CATHODE_E [15:8] Reserved PRECON_E[2:0] VC2_PULSE_E[1:0] VC2_ALT_E[1:0] 0x0000 R/W
[7:0] VC2_SEL_E[1:0] VC1_PULSE_E[1:0] VC1_ALT_E[1:0] VC1_SEL_E[1:0]
0x0184 AFE_TRIM_E [15:8] Reserved (set to 0x7) AFE_TRIM_INT_E[1:0] VREF_ AFE_TRIM_ 0xE3C0 R/W
PULSE_E VREF_E[1:0]
[7:0] VREF_PULSE_VAL_E[1:0] TIA_GAIN_CH2_E[2:0] TIA_GAIN_CH1_E[2:0]
0x0185 LED_ [15:8] LED_ LED_CURRENT2_E[6:0] 0x0000 R/W
POW12_E DRIVESIDE2_
E
[7:0] LED_ LED_CURRENT1_E[6:0]
DRIVESIDE1_
E

Rev. A | Page 47 of 82
ADPD4000/ADPD4001 Data Sheet
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x0186 LED_ [15:8] LED_ LED_CURRENT4_E[6:0] 0x0000 R/W
POW34_E DRIVESIDE4_
E
[7:0] LED_ LED_CURRENT3_E[6:0]
DRIVESIDE3_
E
0x0187 COUNTS_E [15:8] NUM_INT_E[7:0] 0x0101 R/W
[7:0] NUM_REPEAT_E[7:0]
0x0188 PERIOD_E [15:8] Reserved MOD_TYPE_E[1:0] Reserved MIN_PERIOD_E[9:8] 0x0000 R/W
[7:0] MIN_PERIOD_E[7:0]
0x0189 LED_PULSE_E [15:8] LED_WIDTH_E[7:0] 0x0210 R/W
[7:0] LED_OFFSET_E[7:0]
0x018A INTEG_ [15:8] SINGLE_ CH2_AMP_DISABLE_E[2:0] AFE_INT_ CH1_AMP_DISABLE_E[2:0] 0x0003 R/W
SETUP_E INTEG_E C_BUF_E
[7:0] ADC_COUNT_E[1:0] Reserved INTEG_WIDTH_E[4:0]
0x018B INTEG_OS_E [15:8] Reserved INTEG_FINE_OFFSET_E[4:0] 0x1410 R/W
[7:0] INTEG_OFFSET_E[7:0]
0x018C MOD_ [15:8] MOD_WIDTH_E[7:0] 0x0100 R/W
PULSE_E [7:0] MOD_OFFSET_E[7:0]
0x018D PATTERN_E [15:8] LED_DISABLE_E[3:0] MOD_DISABLE_E[3:0] 0x0000 R/W
[7:0] SUBTRACT_E[3:0] REVERSE_INTEG_E[3:0]
0x018E ADC_OFF1_E [15:8] Reserved CH1_ADC_ADJUST_E[13:8] 0x0000 R/W
[7:0] CH1_ADC_ADJUST_E[7:0]
0x018F ADC_OFF2_E [15:8] ZERO_ Reserved CH2_ADC_ADJUST_E[13:8] 0x0000 R/W
ADJUST_E
[7:0] CH2_ADC_ADJUST_E[7:0]
0x0190 DATA_ [15:8] DARK_SHIFT_E[4:0] DARK_SIZE_E[2:0] 0x0003 R/W
FORMAT_E [7:0] SIGNAL_SHIFT_E[4:0] SIGNAL_SIZE_E[2:0]
0x0192 DECIMATE_E [15:8] Reserved DECIMATE_FACTOR_E[6:4] 0x0000 R/W
[7:0] DECIMATE_FACTOR_E[3:0] DECIMATE_TYPE_E[3:0]
0x0193 DIGINT_LIT_E [15:8] Reserved LIT_ 0x0026 R/W
OFFSET_
E[8]
[7:0] LIT_OFFSET_E[7:0]
0x0194 DIGINT_ [15:8] DARK2_OFFSET_E[8:1] 0x2306 R/W
DARK_E [7:0] DARK2_ DARK1_OFFSET_E[6:0]
OFFSET_E[0]
0x0195 THRESH_ [15:8] Reserved 0x0000 R/W
CFG_E [7:0] THRESH1_ THRESH1_ THRESH1_TYPE_E[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_E[1:0]
CHAN_E DIR_E CHAN_E DIR_E
0x0196 THRESH0_E [15:8] Reserved THRESH0_SHIFT_E[4:0] 0x0000 R/W
[7:0] THRESH0_VALUE_E[7:0]
0x0197 THRESH1_E [15:8] Reserved THRESH1_SHIFT_E[4:0] 0x0000 R/W
[7:0] THRESH1_VALUE_E[7:0]
0x01A0 TS_CTRL_F [15:8] Reserved CH2_EN_F SAMPLE_TYPE_F[1:0] INPUT_R_SELECT_F[1:0] TIMESLOT_OFFSET_ 0x0000 R/W
F[9:8]
[7:0] TIMESLOT_OFFSET_F[7:0]
0x01A1 TS_PATH_F [15:8] PRE_WIDTH_F[3:0] Reserved AFE_PATH 0x41DA R/W
_CFG_F[8]
[7:0] AFE_PATH_CFG_F[7:0]
0x01A2 INPUTS_F [15:8] INP78_F[3:0] INP56_F[3:0] 0x0000 R/W
[7:0] INP34_F[3:0] INP12_F[3:0]
0x01A3 CATHODE_F [15:8] Reserved PRECON_F[2:0] VC2_PULSE_F[1:0] VC2_ALT_F[1:0] 0x0000 R/W
[7:0] VC2_SEL_F[1:0] VC1_PULSE_F[1:0] VC1_ALT_F[1:0] VC1_SEL_F[1:0]
0x01A4 AFE_TRIM_F [15:8] Reserved (set to 0x7) AFE_TRIM_INT_F[1:0] VREF_ AFE_TRIM_VREF_ 0xE3C0 R/W
PULSE_F F[1:0]
[7:0] VREF_PULSE_VAL_F[1:0] TIA_GAIN_CH2_F[2:0] TIA_GAIN_CH1_F[2:0]

Rev. A | Page 48 of 82
Data Sheet ADPD4000/ADPD4001
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x01A5 LED_ [15:8] LED_ LED_CURRENT2_F[6:0] 0x0000 R/W
POW12_F DRIVESIDE2_
F
[7:0] LED_ LED_CURRENT1_F[6:0]
DRIVESIDE1_
F
0x01A6 LED_ [15:8] LED_ LED_CURRENT4_F[6:0] 0x0000 R/W
POW34_F DRIVESIDE4_
F
[7:0] LED_ LED_CURRENT3_F[6:0]
DRIVESIDE3_
F
0x01A7 COUNTS_F [15:8] NUM_INT_F[7:0] 0x0101 R/W
[7:0] NUM_REPEAT_F[7:0]
0x01A8 PERIOD_F [15:8] Reserved MOD_TYPE_F[1:0] Reserved MIN_PERIOD_F[9:8] 0x0000 R/W
[7:0] MIN_PERIOD_F[7:0]
0x01A9 LED_PULSE_F [15:8] LED_WIDTH_F[7:0] 0x0210 R/W
[7:0] LED_OFFSET_F[7:0]
0x01AA INTEG_ [15:8] SINGLE_ CH2_AMP_DISABLE_F[2:0] AFE_INT_C_ CH1_AMP_DISABLE_F[2:0] 0x0003 R/W
SETUP_F INTEG_F BUF_F
[7:0] ADC_COUNT_F[1:0] Reserved INTEG_WIDTH_F[4:0]
0x01AB INTEG_OS_F [15:8] Reserved INTEG_FINE_OFFSET_F[4:0] 0x1410 R/W
[7:0] INTEG_OFFSET_F[7:0]
0x01AC MOD_ [15:8] MOD_WIDTH_F[7:0] 0x0100 R/W
PULSE_F [7:0] MOD_OFFSET_F[7:0]
0x01AD PATTERN_F [15:8] LED_DISABLE_F[3:0] MOD_DISABLE_F[3:0] 0x0000 R/W
[7:0] SUBTRACT_F[3:0] REVERSE_INTEG_F[3:0]
0x01AE ADC_OFF1_F [15:8] Reserved CH1_ADC_ADJUST_F[13:8] 0x0000 R/W
[7:0] CH1_ADC_ADJUST_F[7:0]
0x01AF ADC_OFF2_F [15:8] ZERO_ Reserved CH2_ADC_ADJUST_F[13:8] 0x0000 R/W
ADJUST_F
[7:0] CH2_ADC_ADJUST_F[7:0]
0x01B0 DATA_ [15:8] DARK_SHIFT_F[4:0] DARK_SIZE_F[2:0] 0x0003 R/W
FORMAT_F [7:0] SIGNAL_SHIFT_F[4:0] SIGNAL_SIZE_F[2:0]
0x01B2 DECIMATE_F [15:8] Reserved DECIMATE_FACTOR_F[6:4] 0x0000 R/W
[7:0] DECIMATE_FACTOR_F[3:0] DECIMATE_TYPE_F[3:0]
0x01B3 DIGINT_LIT_F [15:8] Reserved LIT_ 0x0026 R/W
OFFSET_
F[8]
[7:0] LIT_OFFSET_F[7:0]
0x01B4 DIGINT_ [15:8] DARK2_OFFSET_F[8:1] 0x2306 R/W
DARK_F [7:0] DARK2_ DARK1_OFFSET_F[6:0]
OFFSET_F[0]
0x01B5 THRESH_ [15:8] Reserved 0x0000 R/W
CFG_F [7:0] THRESH1_ THRESH1_ THRESH1_TYPE_F[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_F[1:0]
CHAN_F DIR_F CHAN_F DIR_F
0x01B6 THRESH0_F [15:8] Reserved THRESH0_SHIFT_F[4:0] 0x0000 R/W
[7:0] THRESH0_VALUE_F[7:0]
0x01B7 THRESH1_F [15:8] Reserved THRESH1_SHIFT_F[4:0] 0x0000 R/W
[7:0] THRESH1_VALUE_F[7:0]
0x01C0 TS_CTRL_G [15:8] Reserved CH2_EN_G SAMPLE_TYPE_G[1:0] INPUT_R_SELECT_G[1:0] TIMESLOT_OFFSET_ 0x0000 R/W
G[9:8]
[7:0] TIMESLOT_OFFSET_G[7:0]
0x01C1 TS_PATH_G [15:8] PRE_WIDTH_G[3:0] Reserved AFE_PATH 0x41DA R/W
_CFG_G[8]
[7:0] AFE_PATH_CFG_G[7:0]
0x01C2 INPUTS_G [15:8] INP78_G[3:0] INP56_G[3:0] 0x0000 R/W
[7:0] INP34_G[3:0] INP12_G[3:0]
0x01C3 CATHODE_G [15:8] Reserved PRECON_G[2:0] VC2_PULSE_G[1:0] VC2_ALT_G[1:0] 0x0000 R/W
[7:0] VC2_SEL_G[1:0] VC1_PULSE_G[1:0] VC1_ALT_G[1:0] VC1_SEL_G[1:0]
Rev. A | Page 49 of 82
ADPD4000/ADPD4001 Data Sheet
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x01C4 AFE_TRIM_G [15:8] Reserved (set to 0x7) AFE_TRIM_INT_G[1:0] VREF_ AFE_TRIM_VREF_G[1:0] 0xE3C0 R/W
PULSE_G
[7:0] VREF_PULSE_VAL_G[1:0] TIA_GAIN_CH2_G[2:0] TIA_GAIN_CH1_G[2:0]
0x01C5 LED_ [15:8] LED_ LED_CURRENT2_G[6:0] 0x0000 R/W
POW12_G DRIVESIDE2_
G
[7:0] LED_ LED_CURRENT1_G[6:0]
DRIVESIDE1_
G
0x01C6 LED_ [15:8] LED_ LED_CURRENT4_G[6:0] 0x0000 R/W
POW34_G DRIVESIDE4_
G
[7:0] LED_ LED_CURRENT3_G[6:0]
DRIVESIDE3_
G
0x01C7 COUNTS_G [15:8] NUM_INT_G[7:0] 0x0101 R/W
[7:0] NUM_REPEAT_G[7:0]
0x01C8 PERIOD_G [15:8] Reserved MOD_TYPE_G[1:0] Reserved MIN_PERIOD_G[9:8] 0x0000 R/W
[7:0] MIN_PERIOD_G[7:0]
0x01C9 LED_PULSE_G [15:8] LED_WIDTH_G[7:0] 0x0210 R/W
[7:0] LED_OFFSET_G[7:0]
0x01CA INTEG_ [15:8] SINGLE_ CH2_AMP_DISABLE_G[2:0] AFE_INT_C_ CH1_AMP_DISABLE_G[2:0] 0x0003 R/W
SETUP_G INTEG_G BUF_G
[7:0] ADC_COUNT_G[1:0] Reserved INTEG_WIDTH_G[4:0]
0x01CB INTEG_OS_G [15:8] Reserved INTEG_FINE_OFFSET_G[4:0] 0x1410 R/W
[7:0] INTEG_OFFSET_G[7:0]
0x01CC MOD_ [15:8] MOD_WIDTH_G[7:0] 0x0100 R/W
PULSE_G [7:0] MOD_OFFSET_G[7:0]
0x01CD PATTERN_G [15:8] LED_DISABLE_G[3:0] MOD_DISABLE_G[3:0] 0x0000 R/W
[7:0] SUBTRACT_G[3:0] REVERSE_INTEG_G[3:0]
0x01CE ADC_OFF1_G [15:8] Reserved CH1_ADC_ADJUST_G[13:8] 0x0000 R/W
[7:0] CH1_ADC_ADJUST_G[7:0]
0x01CF ADC_OFF2_G [15:8] ZERO_ Reserved CH2_ADC_ADJUST_G[13:8] 0x0000 R/W
ADJUST_G
[7:0] CH2_ADC_ADJUST_G[7:0]
0x01D0 DATA_ [15:8] DARK_SHIFT_G[4:0] DARK_SIZE_G[2:0] 0x0003 R/W
FORMAT_G [7:0] SIGNAL_SHIFT_G[4:0] SIGNAL_SIZE_G[2:0]
0x01D2 DECIMATE_G [15:8] Reserved DECIMATE_FACTOR_G[6:4] 0x0000 R/W
[7:0] DECIMATE_FACTOR_G[3:0] DECIMATE_TYPE_G[3:0]
0x01D3 DIGINT_LIT_G [15:8] Reserved LIT_ 0x0026 R/W
OFFSET_
G[8]
[7:0] LIT_OFFSET_G[7:0]
0x01D4 DIGINT_ [15:8] DARK2_OFFSET_G[8:1] 0x2306 R/W
DARK_G [7:0] DARK2_ DARK1_OFFSET_G[6:0]
OFFSET_G[0]
0x01D5 THRESH_ [15:8] Reserved 0x0000 R/W
CFG_G [7:0] THRESH1_ THRESH1_ THRESH1_TYPE_G[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_
CHAN_G DIR_G CHAN_G DIR_G G[1:0]
0x01D6 THRESH0_G [15:8] Reserved THRESH0_SHIFT_G[4:0] 0x0000 R/W
[7:0] THRESH0_VALUE_G[7:0]
0x01D7 THRESH1_G [15:8] Reserved THRESH1_SHIFT_G[4:0] 0x0000 R/W
[7:0] THRESH1_VALUE_G[7:0]
0x01E0 TS_CTRL_H [15:8] Reserved CH2_EN_H SAMPLE_TYPE_H[1:0] INPUT_R_SELECT_H[1:0] TIMESLOT_OFFSET_ 0x0000 R/W
H[9:8]
[7:0] TIMESLOT_OFFSET_H[7:0]
0x01E1 TS_PATH_H [15:8] PRE_WIDTH_H[3:0] Reserved AFE_PATH 0x41DA R/W
_CFG_H[8]
[7:0] AFE_PATH_CFG_H[7:0]

Rev. A | Page 50 of 82
Data Sheet ADPD4000/ADPD4001
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x01E2 INPUTS_H [15:8] INP78_H[3:0] INP56_H[3:0] 0x0000 R/W
[7:0] INP34_H[3:0] INP12_H[3:0]
0x01E3 CATHODE_H [15:8] Reserved PRECON_H[2:0] VC2_PULSE_H[1:0] VC2_ALT_H[1:0] 0x0000 R/W
[7:0] VC2_SEL_H[1:0] VC1_PULSE_H[1:0] VC1_ALT_H[1:0] VC1_SEL_H[1:0]
0x01E4 AFE_TRIM_H [15:8] Reserved (set to 0x7) AFE_TRIM_INT_H[1:0] VREF_ AFE_TRIM_ 0xE3C0 R/W
PULSE_H VREF_H[1:0]
[7:0] VREF_PULSE_VAL_H[1:0] TIA_GAIN_CH2_H[2:0] TIA_GAIN_CH1_H[2:0]
0x01E5 LED_ [15:8] LED_ LED_CURRENT2_H[6:0] 0x0000 R/W
POW12_H DRIVESIDE2_
H
[7:0] LED_ LED_CURRENT1_H[6:0]
DRIVESIDE1_
H
0x01E6 LED_ [15:8] LED_ LED_CURRENT4_H[6:0] 0x0000 R/W
POW34_H DRIVESIDE4_
H
[7:0] LED_ LED_CURRENT3_H[6:0]
DRIVESIDE3_
H
0x01E7 COUNTS_H [15:8] NUM_INT_H[7:0] 0x0101 R/W
[7:0] NUM_REPEAT_H[7:0]
0x01E8 PERIOD_H [15:8] Reserved MOD_TYPE_H[1:0] Reserved MIN_PERIOD_H[9:8] 0x0000 R/W
[7:0] MIN_PERIOD_H[7:0]
0x01E9 LED_PULSE_H [15:8] LED_WIDTH_H[7:0] 0x0210 R/W
[7:0] LED_OFFSET_H[7:0]
0x01EA INTEG_ [15:8] SINGLE_ CH2_AMP_DISABLE_H[2:0] AFE_INT_C_ CH1_AMP_DISABLE_H[2:0] 0x0003 R/W
SETUP_H INTEG_H BUF_H
[7:0] ADC_COUNT_H[1:0] Reserved INTEG_WIDTH_H[4:0]
0x01EB INTEG_OS_H [15:8] Reserved INTEG_FINE_OFFSET_H[4:0] 0x1410 R/W
[7:0] INTEG_OFFSET_H[7:0]
0x01EC MOD_ [15:8] MOD_WIDTH_H[7:0] 0x0100 R/W
PULSE_H [7:0] MOD_OFFSET_H[7:0]
0x01ED PATTERN_H [15:8] LED_DISABLE_H[3:0] MOD_DISABLE_H[3:0] 0x0000 R/W
[7:0] SUBTRACT_H[3:0] REVERSE_INTEG_H[3:0]
0x01EE ADC_OFF1_H [15:8] Reserved CH1_ADC_ADJUST_H[13:8] 0x0000 R/W
[7:0] CH1_ADC_ADJUST_H[7:0]
0x01EF ADC_OFF2_H [15:8] ZERO_ Reserved CH2_ADC_ADJUST_H[13:8] 0x0000 R/W
ADJUST_H
[7:0] CH2_ADC_ADJUST_H[7:0]
0x01F0 DATA_ [15:8] DARK_SHIFT_H[4:0] DARK_SIZE_H[2:0] 0x0003 R/W
FORMAT_H [7:0] SIGNAL_SHIFT_H[4:0] SIGNAL_SIZE_H[2:0]
0x01F2 DECIMATE_H [15:8] Reserved DECIMATE_FACTOR_H[6:4] 0x0000 R/W
[7:0] DECIMATE_FACTOR_H[3:0] DECIMATE_TYPE_H[3:0]
0x01F3 DIGINT_LIT_H [15:8] Reserved LIT_ 0x0026 R/W
OFFSET_
H[8]
[7:0] LIT_OFFSET_H[7:0]
0x01F4 DIGINT_ [15:8] DARK2_OFFSET_H[8:1] 0x2306 R/W
DARK_H [7:0] DARK2_ DARK1_OFFSET_H[6:0]
OFFSET_H[0]
0x01F5 THRESH_ [15:8] Reserved 0x0000 R/W
CFG_H [7:0] THRESH1_ THRESH1_ THRESH1_TYPE_H[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_H[1:0]
CHAN_H DIR_H CHAN_H DIR_H
0x01F6 THRESH0_H [15:8] Reserved THRESH0_SHIFT_H[4:0] 0x0000 R/W
[7:0] THRESH0_VALUE_H[7:0]
0x01F7 THRESH1_H [15:8] Reserved THRESH1_SHIFT_H[4:0] 0x0000 R/W
[7:0] THRESH1_VALUE_H[7:0]
0x0200 TS_CTRL_I [15:8] Reserved CH2_EN_I SAMPLE_TYPE_I[1:0] INPUT_R_SELECT_I[1:0] TIMESLOT_ 0x0000 R/W
OFFSET_I[9:8]
[7:0] TIMESLOT_OFFSET_I[7:0]
Rev. A | Page 51 of 82
ADPD4000/ADPD4001 Data Sheet
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x0201 TS_PATH_I [15:8] PRE_WIDTH_I[3:0] Reserved AFE_PATH 0x41DA R/W
_CFG_I[8]
[7:0] AFE_PATH_CFG_I[7:0]
0x0202 INPUTS_I [15:8] INP78_I[3:0] INP56_I[3:0] 0x0000 R/W
[7:0] INP34_I[3:0] INP12_I[3:0]
0x0203 CATHODE_I [15:8] Reserved PRECON_I[2:0] VC2_PULSE_I[1:0] VC2_ALT_I[1:0] 0x0000 R/W
[7:0] VC2_SEL_I[1:0] VC1_PULSE_I[1:0] VC1_ALT_I[1:0] VC1_SEL_I[1:0]
0x0204 AFE_TRIM_I [15:8] Reserved (set to 0x7) AFE_TRIM_INT_I[1:0] VREF_ AFE_TRIM_ 0xE3C0 R/W
PULSE_I VREF_I[1:0]
[7:0] VREF_PULSE_VAL_I[1:0] TIA_GAIN_CH2_I[2:0] TIA_GAIN_CH1_I[2:0]
0x0205 LED_ [15:8] LED_ LED_CURRENT2_I[6:0] 0x0000 R/W
POW12_I DRIVESIDE2_
I
[7:0] LED_ LED_CURRENT1_I[6:0]
DRIVESIDE1_
I
0x0206 LED_ [15:8] LED_ LED_CURRENT4_I[6:0] 0x0000 R/W
POW34_I DRIVESIDE4_
I
[7:0] LED_ LED_CURRENT3_I[6:0]
DRIVESIDE3_
I
0x0207 COUNTS_I [15:8] NUM_INT_I[7:0] 0x0101 R/W
[7:0] NUM_REPEAT_I[7:0]
0x0208 PERIOD_I [15:8] Reserved MOD_TYPE_I[1:0] Reserved MIN_PERIOD_I[9:8] 0x0000 R/W
[7:0] MIN_PERIOD_I[7:0]
0x0209 LED_PULSE_I [15:8] LED_WIDTH_I[7:0] 0x0210 R/W
[7:0] LED_OFFSET_I[7:0]
0x020A INTEG_ [15:8] SINGLE_ CH2_AMP_DISABLE_I[2:0] AFE_INT_ CH1_AMP_DISABLE_I[2:0] 0x0003 R/W
SETUP_I INTEG_I C_BUF_I
[7:0] ADC_COUNT_I[1:0] Reserved INTEG_WIDTH_I[4:0]
0x020B INTEG_OS_I [15:8] Reserved INTEG_FINE_OFFSET_I[4:0] 0x1410 R/W
[7:0] INTEG_OFFSET_I[7:0]
0x020C MOD_ [15:8] MOD_WIDTH_I[7:0] 0x0100 R/W
PULSE_I [7:0] MOD_OFFSET_I[7:0]
0x020D PATTERN_I [15:8] LED_DISABLE_I[3:0] MOD_DISABLE_I[3:0] 0x0000 R/W
[7:0] SUBTRACT_I[3:0] REVERSE_INTEG_I[3:0]
0x020E ADC_OFF1_I [15:8] Reserved CH1_ADC_ADJUST_I[13:8] 0x0000 R/W
[7:0] CH1_ADC_ADJUST_I[7:0]
0x020F ADC_OFF2_I [15:8] ZERO_ Reserved CH2_ADC_ADJUST_I[13:8] 0x0000 R/W
ADJUST_I
[7:0] CH2_ADC_ADJUST_I[7:0]
0x0210 DATA_ [15:8] DARK_SHIFT_I[4:0] DARK_SIZE_I[2:0] 0x0003 R/W
FORMAT_I [7:0] SIGNAL_SHIFT_I[4:0] SIGNAL_SIZE_I[2:0]
0x0212 DECIMATE_I [15:8] Reserved DECIMATE_FACTOR_I[6:4] 0x0000 R/W
[7:0] DECIMATE_FACTOR_I[3:0] DECIMATE_TYPE_I[3:0]
0x0213 DIGINT_LIT_I [15:8] Reserved LIT_ 0x0026 R/W
OFFSET_
I[8]
[7:0] LIT_OFFSET_I[7:0]
0x0214 DIGINT_ [15:8] DARK2_OFFSET_I[8:1] 0x2306 R/W
DARK_I [7:0] DARK2_ DARK1_OFFSET_I[6:0]
OFFSET_I[0]
0x0215 THRESH_ [15:8] Reserved 0x0000 R/W
CFG_I [7:0] THRESH1_ THRESH1_ THRESH1_TYPE_I[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_I[1:0]
CHAN_I DIR_I CHAN_I DIR_I
0x0216 THRESH0_I [15:8] Reserved THRESH0_SHIFT_I[4:0] 0x0000 R/W
[7:0] THRESH0_VALUE_I[7:0]
0x0217 THRESH1_I [15:8] Reserved THRESH1_SHIFT_I[4:0] 0x0000 R/W
[7:0] THRESH1_VALUE_I[7:0]
Rev. A | Page 52 of 82
Data Sheet ADPD4000/ADPD4001
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x0220 TS_CTRL_J [15:8] Reserved CH2_EN_J SAMPLE_TYPE_J[1:0] INPUT_R_SELECT_J[1:0] TIMESLOT_ 0x0000 R/W
OFFSET_J[9:8]
[7:0] TIMESLOT_OFFSET_J[7:0]
0x0221 TS_PATH_J [15:8] PRE_WIDTH_J[3:0] Reserved AFE_PATH 0x41DA R/W
_CFG_J[8]
[7:0] AFE_PATH_CFG_J[7:0]
0x0222 INPUTS_J [15:8] INP78_J[3:0] INP56_J[3:0] 0x0000 R/W
[7:0] INP34_J[3:0] INP12_J[3:0]
0x0223 CATHODE_J [15:8] Reserved PRECON_J[2:0] VC2_PULSE_J[1:0] VC2_ALT_J[1:0] 0x0000 R/W
[7:0] VC2_SEL_J[1:0] VC1_PULSE_J[1:0] VC1_ALT_J[1:0] VC1_SEL_J[1:0]
0x0224 AFE_TRIM_J [15:8] Reserved (set to 0x7) AFE_TRIM_INT_J[1:0] VREF_ AFE_TRIM_ 0xE3C0 R/W
PULSE_J VREF_J[1:0]
[7:0] VREF_PULSE_VAL_J[1:0] TIA_GAIN_CH2_J[2:0] TIA_GAIN_CH1_J[2:0]
0x0225 LED_ [15:8] LED_ LED_CURRENT2_J[6:0] 0x0000 R/W
POW12_J DRIVESIDE2_
J
[7:0] LED_ LED_CURRENT1_J[6:0]
DRIVESIDE1_
J
0x0226 LED_POW34_ [15:8] LED_ LED_CURRENT4_J[6:0] 0x0000 R/W
J DRIVESIDE4_
J
[7:0] LED_ LED_CURRENT3_J[6:0]
DRIVESIDE3_
J
0x0227 COUNTS_J [15:8] NUM_INT_J[7:0] 0x0101 R/W
[7:0] NUM_REPEAT_J[7:0]
0x0228 PERIOD_J [15:8] Reserved MOD_TYPE_J[1:0] Reserved MIN_PERIOD_J[9:8] 0x0000 R/W
[7:0] MIN_PERIOD_J[7:0]
0x0229 LED_PULSE_J [15:8] LED_WIDTH_J[7:0] 0x0210 R/W
[7:0] LED_OFFSET_J[7:0]
0x022A INTEG_ [15:8] SINGLE_ CH2_AMP_DISABLE_J[2:0] AFE_INT_ CH1_AMP_DISABLE_J[2:0] 0x0003 R/W
SETUP_J INTEG_J C_BUF_J
[7:0] ADC_COUNT_J[1:0] Reserved INTEG_WIDTH_J[4:0]
0x022B INTEG_OS_J [15:8] Reserved INTEG_FINE_OFFSET_J[4:0] 0x1410 R/W
[7:0] INTEG_OFFSET_J[7:0]
0x022C MOD_ [15:8] MOD_WIDTH_J[7:0] 0x0100 R/W
PULSE_J [7:0] MOD_OFFSET_J[7:0]
0x022D PATTERN_J [15:8] LED_DISABLE_J[3:0] MOD_DISABLE_J[3:0] 0x0000 R/W
[7:0] SUBTRACT_J[3:0] REVERSE_INTEG_J[3:0]
0x022E ADC_OFF1_J [15:8] Reserved CH1_ADC_ADJUST_J[13:8] 0x0000 R/W
[7:0] CH1_ADC_ADJUST_J[7:0]
0x022F ADC_OFF2_J [15:8] ZERO_ Reserved CH2_ADC_ADJUST_J[13:8] 0x0000 R/W
ADJUST_J
[7:0] CH2_ADC_ADJUST_J[7:0]
0x0230 DATA_ [15:8] DARK_SHIFT_J[4:0] DARK_SIZE_J[2:0] 0x0003 R/W
FORMAT_J [7:0] SIGNAL_SHIFT_J[4:0] SIGNAL_SIZE_J[2:0]
0x0232 DECIMATE_J [15:8] Reserved DECIMATE_FACTOR_J[6:4] 0x0000 R/W
[7:0] DECIMATE_FACTOR_J[3:0] DECIMATE_TYPE_J[3:0]
0x0233 DIGINT_LIT_J [15:8] Reserved LIT_ 0x0026 R/W
OFFSET_
J[8]
[7:0] LIT_OFFSET_J[7:0]
0x0234 DIGINT_ [15:8] DARK2_OFFSET_J[8:1] 0x2306 R/W
DARK_J [7:0] DARK2_ DARK1_OFFSET_J[6:0]
OFFSET_J[0]
0x0235 THRESH_ [15:8] Reserved 0x0000 R/W
CFG_J [7:0] THRESH1_ THRESH1_ THRESH1_TYPE_J[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_J[1:0]
CHAN_J DIR_J CHAN_J DIR_J

Rev. A | Page 53 of 82
ADPD4000/ADPD4001 Data Sheet
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x0236 THRESH0_J [15:8] Reserved THRESH0_SHIFT_J[4:0] 0x0000 R/W
[7:0] THRESH0_VALUE_J[7:0]
0x0237 THRESH1_J [15:8] Reserved THRESH1_SHIFT_J[4:0] 0x0000 R/W
[7:0] THRESH1_VALUE_J[7:0]
0x0240 TS_CTRL_K [15:8] Reserved CH2_EN_K SAMPLE_TYPE_K[1:0] INPUT_R_SELECT_K[1:0] TIMESLOT_ 0x0000 R/W
OFFSET_K[9:8]
[7:0] TIMESLOT_OFFSET_K[7:0]
0x0241 TS_PATH_K [15:8] PRE_WIDTH_K[3:0] Reserved AFE_PATH 0x41DA R/W
_CFG_K[8]
[7:0] AFE_PATH_CFG_K[7:0]
0x0242 INPUTS_K [15:8] INP78_K[3:0] INP56_K[3:0] 0x0000 R/W
[7:0] INP34_K[3:0] INP12_K[3:0]
0x0243 CATHODE_K [15:8] Reserved PRECON_K[2:0] VC2_PULSE_K[1:0] VC2_ALT_K[1:0] 0x0000 R/W
[7:0] VC2_SEL_K[1:0] VC1_PULSE_K[1:0] VC1_ALT_K[1:0] VC1_SEL_K[1:0]
0x0244 AFE_TRIM_K [15:8] Reserved (set to 0x7) AFE_TRIM_INT_K[1:0] VREF_ AFE_TRIM_ 0xE3C0 R/W
PULSE_K VREF_K[1:0]
[7:0] VREF_PULSE_VAL_K[1:0] TIA_GAIN_CH2_K[2:0] TIA_GAIN_CH1_K[2:0]
0x0245 LED_ [15:8] LED_ LED_CURRENT2_K[6:0] 0x0000 R/W
POW12_K DRIVESIDE2_
K
[7:0] LED_ LED_CURRENT1_K[6:0]
DRIVESIDE1_
K
0x0246 LED_ [15:8] LED_ LED_CURRENT4_K[6:0] 0x0000 R/W
POW34_K DRIVESIDE4_
K
[7:0] LED_ LED_CURRENT3_K[6:0]
DRIVESIDE3_
K
0x0247 COUNTS_K [15:8] NUM_INT_K[7:0] 0x0101 R/W
[7:0] NUM_REPEAT_K[7:0]
0x0248 PERIOD_K [15:8] Reserved MOD_TYPE_K[1:0] Reserved MIN_PERIOD_K[9:8] 0x0000 R/W
[7:0] MIN_PERIOD_K[7:0]
0x0249 LED_PULSE_ [15:8] LED_WIDTH_K[7:0] 0x0210 R/W
K [7:0] LED_OFFSET_K[7:0]
0x024A INTEG_ [15:8] SINGLE_ CH2_AMP_DISABLE_K[2:0] AFE_INT_C_ CH1_AMP_DISABLE_K[2:0] 0x0003 R/W
SETUP_K INTEG_K BUF_K
[7:0] ADC_COUNT_K[1:0] Reserved INTEG_WIDTH_K[4:0]
0x024B INTEG_OS_K [15:8] Reserved INTEG_FINE_OFFSET_K[4:0] 0x1410 R/W
[7:0] INTEG_OFFSET_K[7:0]
0x024C MOD_ [15:8] MOD_WIDTH_K[7:0] 0x0100 R/W
PULSE_K [7:0] MOD_OFFSET_K[7:0]
0x024D PATTERN_K [15:8] LED_DISABLE_K[3:0] MOD_DISABLE_K[3:0] 0x0000 R/W
[7:0] SUBTRACT_K[3:0] REVERSE_INTEG_K[3:0]
0x024E ADC_OFF1_K [15:8] Reserved CH1_ADC_ADJUST_K[13:8] 0x0000 R/W
[7:0] CH1_ADC_ADJUST_K[7:0]
0x024F ADC_OFF2_K [15:8] ZERO_ Reserved CH2_ADC_ADJUST_K[13:8] 0x0000 R/W
ADJUST_K
[7:0] CH2_ADC_ADJUST_K[7:0]
0x0250 DATA_ [15:8] DARK_SHIFT_K[4:0] DARK_SIZE_K[2:0] 0x0003 R/W
FORMAT_K [7:0] SIGNAL_SHIFT_K[4:0] SIGNAL_SIZE_K[2:0]
0x0252 DECIMATE_K [15:8] Reserved DECIMATE_FACTOR_K[6:4] 0x0000 R/W
[7:0] DECIMATE_FACTOR_K[3:0] DECIMATE_TYPE_K[3:0]
0x0253 DIGINT_LIT_K [15:8] Reserved LIT_ 0x0026 R/W
OFFSET_
K[8]
[7:0] LIT_OFFSET_K[7:0]
0x0254 DIGINT_ [15:8] DARK2_OFFSET_K[8:1] 0x2306 R/W
DARK_K [7:0] DARK2_ DARK1_OFFSET_K[6:0]
OFFSET_K[0]
Rev. A | Page 54 of 82
Data Sheet ADPD4000/ADPD4001
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x0255 THRESH_ [15:8] Reserved 0x0000 R/W
CFG_K [7:0] THRESH1_ THRESH1_ THRESH1_TYPE_K[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_
CHAN_K DIR_K CHAN_K DIR_K K[1:0]
0x0256 THRESH0_K [15:8] Reserved THRESH0_SHIFT_K[4:0] 0x0000 R/W
[7:0] THRESH0_VALUE_K[7:0]
0x0257 THRESH1_K [15:8] Reserved THRESH1_SHIFT_K[4:0] 0x0000 R/W
[7:0] THRESH1_VALUE_K[7:0]
0x0260 TS_CTRL_L [15:8] Reserved CH2_EN_L SAMPLE_TYPE_L[1:0] INPUT_R_SELECT_L[1:0] TIMESLOT_ 0x0000 R/W
OFFSET_L[9:8]
[7:0] TIMESLOT_OFFSET_L[7:0]
0x0261 TS_PATH_L [15:8] PRE_WIDTH_L[3:0] Reserved AFE_PATH 0x41DA R/W
_CFG_L[8]
[7:0] AFE_PATH_CFG_L[7:0]
0x0262 INPUTS_L [15:8] INP78_L[3:0] INP56_L[3:0] 0x0000 R/W
[7:0] INP34_L[3:0] INP12_L[3:0]
0x0263 CATHODE_L [15:8] Reserved PRECON_L[2:0] VC2_PULSE_L[1:0] VC2_ALT_L[1:0] 0x0000 R/W
[7:0] VC2_SEL_L[1:0] VC1_PULSE_L[1:0] VC1_ALT_L[1:0] VC1_SEL_L[1:0]
0x0264 AFE_TRIM_L [15:8] Reserved (set to 0x7) AFE_TRIM_INT_L[1:0] VREF_ AFE_TRIM_ 0xE3C0 R/W
PULSE_L VREF_L[1:0]
[7:0] VREF_PULSE_VAL_L[1:0] TIA_GAIN_CH2_L[2:0] TIA_GAIN_CH1_L[2:0]
0x0265 LED_ [15:8] LED_ LED_CURRENT2_L[6:0] 0x0000 R/W
POW12_L DRIVESIDE2_
L
[7:0] LED_ LED_CURRENT1_L[6:0]
DRIVESIDE1_
L
0x0266 LED_ [15:8] LED_ LED_CURRENT4_L[6:0] 0x0000 R/W
POW34_L DRIVESIDE4_
L
[7:0] LED_ LED_CURRENT3_L[6:0]
DRIVESIDE3_
L
0x0267 COUNTS_L [15:8] NUM_INT_L[7:0] 0x0101 R/W
[7:0] NUM_REPEAT_L[7:0]
0x0268 PERIOD_L [15:8] Reserved MOD_TYPE_L[1:0] Reserved MIN_PERIOD_L[9:8] 0x0000 R/W
[7:0] MIN_PERIOD_L[7:0]
0x0269 LED_PULSE_L [15:8] LED_WIDTH_L[7:0] 0x0210 R/W
[7:0] LED_OFFSET_L[7:0]
0x026A INTEG_ [15:8] SINGLE_ CH2_AMP_DISABLE_L[2:0] AFE_INT_C_ CH1_AMP_DISABLE_L[2:0] 0x0003 R/W
SETUP_L INTEG_L BUF_L
[7:0] ADC_COUNT_L[1:0] Reserved INTEG_WIDTH_L[4:0]
0x026B INTEG_OS_L [15:8] Reserved INTEG_FINE_OFFSET_L[4:0] 0x1410 R/W
[7:0] INTEG_OFFSET_L[7:0]
0x026C MOD_ [15:8] MOD_WIDTH_L[7:0] 0x0100 R/W
PULSE_L [7:0] MOD_OFFSET_L[7:0]
0x026D PATTERN_L [15:8] LED_DISABLE_L[3:0] MOD_DISABLE_L[3:0] 0x0000 R/W
[7:0] SUBTRACT_L[3:0] REVERSE_INTEG_L[3:0]
0x026E ADC_OFF1_L [15:8] Reserved CH1_ADC_ADJUST_L[13:8] 0x0000 R/W
[7:0] CH1_ADC_ADJUST_L[7:0]
0x026F ADC_OFF2_L [15:8] ZERO_ Reserved CH2_ADC_ADJUST_L[13:8] 0x0000 R/W
ADJUST_L
[7:0] CH2_ADC_ADJUST_L[7:0]
0x0270 DATA_ [15:8] DARK_SHIFT_L[4:0] DARK_SIZE_L[2:0] 0x0003 R/W
FORMAT_L [7:0] SIGNAL_SHIFT_L[4:0] SIGNAL_SIZE_L[2:0]
0x0272 DECIMATE_L [15:8] Reserved DECIMATE_FACTOR_L[6:4] 0x0000 R/W
[7:0] DECIMATE_FACTOR_L[3:0] DECIMATE_TYPE_L[3:0]
0x0273 DIGINT_LIT_L [15:8] Reserved LIT_ 0x0026 R/W
OFFSET_
L[8]
[7:0] LIT_OFFSET_L[7:0]
Rev. A | Page 55 of 82
ADPD4000/ADPD4001 Data Sheet
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x0274 DIGINT_ [15:8] DARK2_OFFSET_L[8:1] 0x2306 R/W
DARK_L [7:0] DARK2_ DARK1_OFFSET_L[6:0]
OFFSET_L[0]
0x0275 THRESH_ [15:8] Reserved 0x0000 R/W
CFG_L [7:0] THRESH1_ THRESH1_ THRESH1_TYPE_L[1:0] THRESH0_ THRESH0_ THRESH0_TYPE_L[1:0]
CHAN_L DIR_L CHAN_L DIR_L
0x0276 THRESH0_L [15:8] Reserved THRESH0_SHIFT_L[4:0] 0x0000 R/W
[7:0] THRESH0_VALUE_L[7:0]
0x0277 THRESH1_L [15:8] Reserved THRESH1_SHIFT_L[4:0] 0x0000 R/W
[7:0] THRESH1_VALUE_L[7:0]

Rev. A | Page 56 of 82
Data Sheet ADPD4000/ADPD4001

REGISTER DETAILS
GLOBAL CONFIGURATION REGISTERS
Table 26. Global Configuration Register Details
Addr Name Bits Bit Name Description Reset Access
0x000D TS_FREQ [15:0] TIMESLOT_PERIOD_L Lower 16 bits of time slot period in low frequency oscillator cycles. 0x2710 R/W
The time slot rate is (low frequency oscillator frequency) ÷
(TIMESLOT_PERIOD_x). The default value operates at 100 Hz when
using the 1 MHz low frequency oscillator.
0x000E TS_FREQH [15:7] Reserved Reserved. 0x0 R
[6:0] TIMESLOT_PERIOD_H Upper seven bits of time slot period in low frequency oscillator 0x0 R/W
cycles. The time slot rate is (low frequency oscillator frequency) ÷
(TIMESLOT_PERIOD_x). The default value operates at 100 Hz when
using the 1 MHz low frequency oscillator.
0x000F SYS_CTL 15 SW_RESET Software reset. Write 1 to this bit to assert a software reset, which 0x0 R/W
stops all AFE operations and resets the device to its default values.
Software reset does not reset the SPI or I2C port.
[14:10] Reserved Reserved. 0x0 R
[9:8] ALT_CLOCKS External clock select. 0x0 R/W
00: use internal low frequency oscillator and high frequency
oscillator.
01: use external low frequency oscillator.
02: use external high frequency oscillator and internal low
frequency oscillator.
03: use external high frequency oscillator and generate low
frequency oscillator from high frequency oscillator.
[7:6] ALT_CLK_GPIO Alternate clock GPIO select. 0x0 R/W
00: use GPIO0 for alternate clock.
01: use GPIO1 for alternate clock.
10: use GPIO2 for alternate clock.
11: use GPIO3 for alternate clock.
[5:3] Reserved Write 0x0. 0x0 R/W
2 LFOSC_SEL Selects low frequency oscillator. This bit selects between the 0x0 R/W
32 kHz and 1 MHz low speed oscillator.
0: use the 32 kHz oscillator as the low frequency clock.
1: use the 1 MHz oscillator as the low frequency clock.
1 OSC_1M_EN Enable 1 MHz low frequency oscillator. This bit turns on the 1 MHz 0x0 R/W
low frequency oscillator, which must be left running during all
operations while using this oscillator.
0 OSC_32K_EN Enable 32 kHz low frequency oscillator. This bit turns on the 32 kHz 0x0 R/W
low frequency oscillator, which must be left running during all
operations while using this oscillator.
0x0010 OPMODE [15:12] Reserved Reserved. 0x0 R
[11:8] TIMESLOT_EN Time slot enable control. 0x0 R/W
0000: Time Slot Sequence A only.
0001: Time Slot Sequence AB.
0010: Time Slot Sequence ABC.
0011: Time Slot Sequence ABCD.
0100: Time Slot Sequence ABCDE.
0101: Time Slot Sequence ABCDEF.
0110: Time Slot Sequence ABCDEFG.
0111: Time Slot Sequence ABCDEFGH.
1000: Time Slot Sequence ABCDEFGHI.
1001: Time Slot Sequence ABCDEFGHIJ.
1010: Time Slot Sequence ABCDEFGHIJK.
1011: Time Slot Sequence ABCDEFGHIJKL.

Rev. A | Page 57 of 82
ADPD4000/ADPD4001 Data Sheet
Addr Name Bits Bit Name Description Reset Access
[7:1] Reserved Reserved. 0x0 R
0 OP_MODE Operating mode selection. 0x0 R/W
0: standby.
1: go mode. Operate selected time slots.
0x0020 INPUT_SLEEP [15:12] INP_SLEEP_78 Input pair sleep state for IN7 and IN8 inputs. 0x0 R/W
0x0: both inputs float.
0x1: floating short of IN7 to IN8. Only if PAIR78 is set to 1.
0x2: IN7 and IN8 connected to VC1. Also shorted together if PAIR78
is set to 1.
0x3: IN7 and IN8 connected to VC2. Also shorted together if PAIR78
is set to 1.
0x4: IN7 connected to VC1. IN8 floating.
0x5: IN7 connected to VC1. IN8 connected to VC2.
0x6: IN7 connected to VC2. IN8 floating.
0x7: IN7 connected to VC2. IN8 connected to VC1.
0x8: IN7 floating. IN8 connected to VC1.
0x9: IN7 floating. IN8 connected to VC2.
[11:8] INP_SLEEP_56 Input pair sleep state for IN5 and IN6 inputs. 0x0 R/W
0x0: both inputs float.
0x1: floating short of IN5 to IN6. Only if PAIR56 is set to 1.
0x2: IN5 and IN6 connected to VC1. Also shorted together if PAIR56
is set to 1.
0x3: IN5 and IN6 connected to VC2. Also shorted together if PAIR78
is set to 1.
0x4: IN5 connected to VC1. IN6 floating.
0x5: IN5 connected to VC1. IN6 connected to VC2.
0x6: IN5 connected to VC2. IN6 floating.
0x7: IN5 connected to VC2. IN6 connected to VC1.
0x8: IN5 floating. IN6 connected to VC1.
0x9: IN5 floating. IN6 connected to VC2.
[7:4] INP_SLEEP_34 Input pair sleep state for IN3 and IN4 inputs. 0x0 R/W
0x0: both inputs float.
0x1: floating short of IN3 to IN4. Only if PAIR34 is set to 1.
0x2: IN3 and IN4 connected to VC1. Also shorted together if PAIR34
is set to 1.
0x3: IN3 and IN4 connected to VC2. Also shorted together if PAIR34
is set to 1.
0x4: IN3 connected to VC1. IN4 floating.
0x5: IN3 connected to VC1. IN4 connected to VC2.
0x6: IN3 connected to VC2. IN4 floating.
0x7: IN3 connected to VC2. IN4 connected to VC1.
0x8: IN3 floating. IN4 connected to VC1.
0x9: IN3 floating. IN4 connected to VC2.
[3:0] INP_SLEEP_12 Input pair sleep state for IN1 and IN2 inputs. 0x0 R/W
0x0: both inputs float.
0x1: floating short of IN1 to IN2. Only if PAIR12 is set to 1.
0x2: IN1 and IN2 connected to VC1. Also shorted together if PAIR12
is set to 1.
0x3: IN1 and IN2 connected to VC2. Also shorted together if PAIR12
is set to 1.
0x4: IN1 connected to VC1. IN2 floating.
0x5: IN1 connected to VC1. IN2 connected to VC2.
0x6: IN1 connected to VC2. IN2 floating.

Rev. A | Page 58 of 82
Data Sheet ADPD4000/ADPD4001
Addr Name Bits Bit Name Description Reset Access
0x7: IN1 connected to VC2. IN2 connected to VC1.
0x8: IN1 floating. IN2 connected to VC1.
0x9: IN1 floating. IN2 connected to VC2.
0x0021 INPUT_CFG [15:8] Reserved Reserved. 0x0 R
[7:6] VC2_SLEEP VC2 sleep state. 0x0 R/W
0: VC2 set to AVDD during sleep.
1: VC2 set to ground during sleep.
10: VC2 floating during sleep.
[5:4] VC1_SLEEP VC1 sleep state. 0x0 R/W
0: VC1 set to AVDD during sleep.
1: VC1 set to ground during sleep.
10: VC1 floating during sleep.
3 PAIR78 Input pair configuration. 0x0 R/W
0: IN7 and IN8 configured as two single-ended inputs.
1: IN7 and IN8 configured as a differential pair.
2 PAIR56 Input pair configuration. 0x0 R/W
0: IN5 and IN6 configured as two single-ended inputs.
1: IN5 and IN6 configured as a differential pair.
1 PAIR34 Input pair configuration. 0x0 R/W
0: IN3 and IN4 configured as two single-ended inputs.
1: IN3 and IN4 configured as a differential pair.
0 PAIR12 Input pair configuration. 0x0 R/W
0: IN1 and IN2 configured as two single-ended inputs.
1: IN1 and IN2 configured as a differential pair.
INTERRUPT STATUS AND CONTROL REGISTERS
Table 27. Interrupt Status and Control Register Details
Addr Name Bits Bit Name Description Reset Access1
0x0000 FIFO_STATUS 15 CLEAR_FIFO Clear FIFO. Write a 1 to empty the FIFO while the FIFO is 0x0 R/W1C
not being accessed. This resets FIFO_BYTE_COUNT and
clears the INT_FIFO_OFLOW, INT_FIFO_UFLOW, and
INT_FIFO_TH status bits.
14 INT_FIFO_UFLOW FIFO underflow error. This bit is set when the FIFO is read 0x0 R/W1C
while empty. Write 1 to this bit to clear the interrupt. This
bit is also cleared if the FIFO is cleared using the
CLEAR_FIFO bit.
13 INT_FIFO_OFLOW FIFO overflow error. This bit is set when data was not 0x0 R/W1C
written to the FIFO due to lack of space. Write 1 to this bit
to clear the interrupt. This bit is also cleared if the FIFO is
cleared with the CLEAR_FIFO bit.
[12:11] Reserved Reserved. 0x0 R
[10:0] FIFO_BYTE_COUNT This field indicates the number of bytes in the FIFO. 0x0 R
0x0001 INT_STATUS_DATA 15 INT_FIFO_TH FIFO_TH interrupt status. This bit is set during a FIFO write 0x0 R/W1C
when the number of bytes in the FIFO exceeds the
FIFO_TH register value. Write 1 to this bit to clear this
interrupt. This bit can also be automatically cleared when
the FIFO_DATA register is read if the INT_ACLEAR_FIFO bit
is set.
[14:12] Reserved Reserved. 0x0 R
11 INT_DATA_L Time Slot L data register interrupt status. This bit is set 0x0 R/W1C
every time the Time Slot L data registers are updated.
Write 1 to this bit to clear the interrupt. The interrupt is
cleared automatically when the Time Slot L data registers
are read if the INT_ACLEAR_DATA_L bit is set.

Rev. A | Page 59 of 82
ADPD4000/ADPD4001 Data Sheet
Addr Name Bits Bit Name Description Reset Access1
10 INT_DATA_K Time Slot K data register interrupt status. This bit is set 0x0 R/W1C
every time the Time Slot K data registers are updated.
Write 1 to this bit to clear the interrupt. The interrupt is
cleared automatically when the Time Slot K data registers
are read if the INT_ACLEAR_DATA_K bit is set.
9 INT_DATA_J Time Slot J data register interrupt status. This bit is set 0x0 R/W1C
every time the Time Slot J data registers are updated.
Write 1 to this bit to clear the interrupt. The interrupt is
cleared automatically when the Time Slot J data registers
are read if the INT_ACLEAR_DATA_J bit is set.
8 INT_DATA_I Time Slot I data register interrupt status. This bit is set 0x0 R/W1C
every time the Time Slot I data registers are updated. Write
1 to this bit to clear the interrupt. The interrupt is cleared
automatically when the Time Slot I data registers are read
if the INT_ACLEAR_DATA_I bit is set.
7 INT_DATA_H Time Slot H data register interrupt status. This bit is set 0x0 R/W1C
every time the Time Slot H data registers are updated.
Write 1 to this bit to clear the interrupt. The interrupt is
cleared automatically when the Time Slot H data registers
are read if the INT_ACLEAR_DATA_H bit is set.
6 INT_DATA_G Time Slot G data register interrupt status. This bit is set 0x0 R/W1C
every time the Time Slot G data registers are updated.
Write 1 to this bit to clear the interrupt. The interrupt is
cleared automatically when the Time Slot G data registers
are read if the INT_ACLEAR_DATA_G bit is set.
5 INT_DATA_F Time Slot F data register interrupt status. This bit is set 0x0 R/W1C
every time the Time Slot F data registers are updated.
Write 1 to this bit to clear the interrupt. The interrupt is
cleared automatically when the Time Slot F data registers
are read if the INT_ACLEAR_DATA_F bit is set.
4 INT_DATA_E Time Slot E data register interrupt status. This bit is set 0x0 R/W1C
every time the Time Slot E data registers are updated.
Write 1 to this bit to clear the interrupt. The interrupt is
cleared automatically when the Time Slot E data registers
are read if the INT_ACLEAR_DATA_E bit is set.
3 INT_DATA_D Time Slot D data register interrupt status. This bit is set 0x0 R/W1C
every time the Time Slot D data registers are updated.
Write 1 to this bit to clear the interrupt. The interrupt is
cleared automatically when the Time Slot D data registers
are read if the INT_ACLEAR_DATA_D bit is set.
2 INT_DATA_C Time Slot C data register interrupt status. This bit is set 0x0 R/W1C
every time the Time Slot C data registers are updated.
Write 1 to this bit to clear the interrupt. The interrupt is
cleared automatically when the Time Slot C data registers
are read if the INT_ACLEAR_DATA_C bit is set.
1 INT_DATA_B Time Slot B data register interrupt status. This bit is set 0x0 R/W1C
every time the Time Slot B data registers are updated.
Write 1 to this bit to clear the interrupt. The interrupt is
cleared automatically when the Time Slot B data registers
are read if the INT_ACLEAR_DATA_B bit is set.
0 INT_DATA_A Time Slot A data register interrupt status. This bit is set 0x0 R/W1C
every time the Time Slot A data registers are updated.
Write 1 to this bit to clear the interrupt. The interrupt is
cleared automatically when the Time Slot A data registers
are read if the INT_ACLEAR_DATA_A bit is set.

Rev. A | Page 60 of 82
Data Sheet ADPD4000/ADPD4001
Addr Name Bits Bit Name Description Reset Access1
0x0002 INT_STATUS_LEV0 [15:12] Reserved Reserved. 0x0 R
11 INT_LEV0_L Time Slot L Level 0 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
10 INT_LEV0_K Time Slot K Level 0 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
9 INT_LEV0_J Time Slot J Level 0 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
8 INT_LEV0_I Time Slot I Level 0 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
7 INT_LEV0_H Time Slot H Level 0 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
6 INT_LEV0_G Time Slot G Level 0 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
5 INT_LEV0_F Time Slot F Level 0 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
4 INT_LEV0_E Time Slot E Level 0 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
3 INT_LEV0_D Time Slot D Level 0 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
2 INT_LEV0_C Time Slot C Level 0 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
1 INT_LEV0_B Time Slot B Level 0 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
0 INT_LEV0_A Time Slot A Level 0 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
0x0003 INT_STATUS_LEV1 [15:12] Reserved Reserved. 0x0 R
11 INT_LEV1_L Time Slot L Level 1 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
10 INT_LEV1_K Time Slot K Level 1 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
9 INT_LEV1_J Time Slot J Level 1 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
8 INT_LEV1_I Time Slot I Level 1 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
7 INT_LEV1_H Time Slot H Level 1 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
6 INT_LEV1_G Time Slot G Level 1 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
5 INT_LEV1_F Time Slot F Level 1 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
4 INT_LEV1_E Time Slot E Level 1 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
3 INT_LEV1_D Time Slot D Level 1 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
2 INT_LEV1_C Time Slot C Level 1 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
1 INT_LEV1_B Time Slot B Level 1 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
0 INT_LEV1_A Time Slot A Level 1 interrupt status. This bit is set during a 0x0 R/W1C
data register update when the configured criteria is met.
0x0007 INT_ACLEAR 15 INT_ACLEAR_FIFO FIFO threshold interrupt autoclear enable. Set this bit to 0x1 R/W
enable automatic clearing of the FIFO_TH interrupt each
time the FIFO is read.
[14:12] Reserved Reserved. 0x0 R
11 INT_ACLEAR_DATA_L Time Slot L interrupt autoclear enable. Set this bit to 0x1 R/W
enable automatic clearing of the INT_DATA_L interrupt
each time the Time Slot L data registers are read.

Rev. A | Page 61 of 82
ADPD4000/ADPD4001 Data Sheet
Addr Name Bits Bit Name Description Reset Access1
10 INT_ACLEAR_DATA_K Time Slot K interrupt autoclear enable. Set this bit to 0x1 R/W
enable automatic clearing of the INT_DATA_K interrupt
each time the Time Slot K data registers are read.
9 INT_ACLEAR_DATA_J Time Slot J interrupt autoclear enable. Set this bit to 0x1 R/W
enable automatic clearing of the INT_DATA_J interrupt
each time the Time Slot J data registers are read.
8 INT_ACLEAR_DATA_I Time Slot I interrupt autoclear enable. Set this bit to 0x1 R/W
enable automatic clearing of the INT_DATA_I interrupt
each time the Time Slot I data registers are read.
7 INT_ACLEAR_DATA_H Time Slot H interrupt autoclear enable. Set this bit to 0x1 R/W
enable automatic clearing of the INT_DATA_H interrupt
each time the Time Slot H data registers are read.
6 INT_ACLEAR_DATA_G Time Slot G interrupt autoclear enable. Set this bit to 0x1 R/W
enable automatic clearing of the INT_DATA_G interrupt
each time the Time Slot G data registers are read.
5 INT_ACLEAR_DATA_F Time Slot F interrupt autoclear enable. Set this bit to 0x1 R/W
enable automatic clearing of the INT_DATA_F interrupt
each time the Time Slot F data registers are read.
4 INT_ACLEAR_DATA_E Time Slot E interrupt autoclear enable. Set this bit to 0x1 R/W
enable automatic clearing of the INT_DATA_E interrupt
each time the Time Slot E data register is read.
3 INT_ACLEAR_DATA_D Time Slot D interrupt autoclear enable. Set this bit to 0x1 R/W
enable automatic clearing of the INT_DATA_D interrupt
each time the Time Slot D data registers are read.
2 INT_ACLEAR_DATA_C Time Slot C interrupt autoclear enable. Set this bit to 0x1 R/W
enable automatic clearing of the INT_DATA_C interrupt
each time the Time Slot C data registers are read.
1 INT_ACLEAR_DATA_B Time Slot B interrupt autoclear enable. Set this bit to 0x1 R/W
enable automatic clearing of the INT_DATA_B interrupt
each time the Time Slot B data registers are read.
0 INT_ACLEAR_DATA_A Time Slot A interrupt autoclear enable. Set this bit to 0x1 R/W
enable automatic clearing of the INT_DATA_A interrupt
each time the Time Slot A data registers are read.
0x0014 INT_ENABLE_XD 15 INTX_EN_FIFO_TH INT_FIFO_TH interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of the FIFO threshold status on Interrupt X.
14 INTX_EN_FIFO_UFLOW INT_FIFO_UFLOW interrupt enable for Interrupt X. Write a 0x0 R/W
1 to this bit to enable drive of the FIFO underflow status
on Interrupt X.
13 INTX_EN_FIFO_OFLOW INT_FIFO_OFLOW interrupt enable for Interrupt X. Write a 0x0 R/W
1 to this bit to enable drive of the FIFO overflow status on
Interrupt X.
12 Reserved Reserved. 0x0 R
11 INTX_EN_DATA_L INT_DATA_L interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_L status on Interrupt X.
10 INTX_EN_DATA_K INT_DATA_K interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_K status on Interrupt X.
9 INTX_EN_DATA_J INT_DATA_J interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_J status on Interrupt X.
8 INTX_EN_DATA_I INT_DATA_I interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_DATA_I status on Interrupt X.
7 INTX_EN_DATA_H INT_DATA_H interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_H status on Interrupt X.
6 INTX_EN_DATA_G INT_DATA_G interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_G status on Interrupt X.
5 INTX_EN_DATA_F INT_DATA_F interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_F status on Interrupt X.
4 INTX_EN_DATA_E INT_DATA_E interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_E status on Interrupt X.

Rev. A | Page 62 of 82
Data Sheet ADPD4000/ADPD4001
Addr Name Bits Bit Name Description Reset Access1
3 INTX_EN_DATA_D INT_DATA_D interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_D status on Interrupt X.
2 INTX_EN_DATA_C INT_DATA_C interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_C status on Interrupt X.
1 INTX_EN_DATA_B INT_DATA_B interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_B status on Interrupt X.
0 INTX_EN_DATA_A INT_DATA_A interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_A status on Interrupt X.
0x0015 INT_ENABLE_YD 15 INTY_EN_FIFO_TH INT_FIFO_TH Interrupt Enable. Write a 1 to this bit to 0x0 R/W
enable drive of the FIFO threshold status on Interrupt Y.
14 INTY_EN_FIFO_UFLOW INT_FIFO_UFLOW Interrupt enable for Interrupt Y. Write a 0x0 R/W
1 to this bit to enable drive of the FIFO underflow status
on Interrupt Y.
13 INTY_EN_FIFO_OFLOW INT_FIFO_OFLOW Interrupt enable for Interrupt Y. Write a 0x0 R/W
1 to this bit to enable drive of the FIFO overflow status on
Interrupt Y.
12 Reserved Reserved. 0x0 R
11 INTY_EN_DATA_L INT_DATA_L interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_L status on Interrupt Y.
10 INTY_EN_DATA_K INT_DATA_K interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_K status on Interrupt Y.
9 INTY_EN_DATA_J INT_DATA_J interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_J status on Interrupt Y.
8 INTY_EN_DATA_I INT_DATA_I interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_DATA_I status on Interrupt Y.
7 INTY_EN_DATA_H INT_DATA_H interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_H status on Interrupt Y.
6 INTY_EN_DATA_G INT_DATA_G interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_G status on Interrupt Y.
5 INTY_EN_DATA_F INT_DATA_F interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_F status on Interrupt Y.
4 INTY_EN_DATA_E INT_DATA_E interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_E status on Interrupt Y.
3 INTY_EN_DATA_D INT_DATA_D interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_D status on Interrupt Y.
2 INTY_EN_DATA_C INT_DATA_C interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_C status on Interrupt Y.
1 INTY_EN_DATA_B INT_DATA_B interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_B status on Interrupt Y.
0 INTY_EN_DATA_A INT_DATA_A interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_DATA_A status on Interrupt Y.
0x0016 INT_ENABLE_XL0 [15:12] Reserved Reserved. 0x0 R
11 INTX_EN_LEV0_L INT_LEV0_L interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV0_L status on Interrupt X.
10 INTX_EN_LEV0_K INT_LEV0_K interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV0_K status on Interrupt X.
9 INTX_EN_LEV0_J INT_LEV0_J interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV0_J status on Interrupt X.
8 INTX_EN_LEV0_I INT_LEV0_I interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV0_I status on Interrupt X.
7 INTX_EN_LEV0_H INT_LEV0_H interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV0_H status on Interrupt X.
6 INTX_EN_LEV0_G INT_LEV0_G interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV0_G status on Interrupt X.
5 INTX_EN_LEV0_F INT_LEV0_F interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV0_F status on Interrupt X.

Rev. A | Page 63 of 82
ADPD4000/ADPD4001 Data Sheet
Addr Name Bits Bit Name Description Reset Access1
4 INTX_EN_LEV0_E INT_LEV0_E interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV0_E status on Interrupt X.
3 INTX_EN_LEV0_D INT_LEV0_D interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV0_D status on Interrupt X.
2 INTX_EN_LEV0_C INT_LEV0_C interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV0_C status on Interrupt X.
1 INTX_EN_LEV0_B INT_LEV0_B interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV0_B status on Interrupt X.
0 INTX_EN_LEV0_A INT_LEV0_A interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV0_A status on Interrupt X.
0x0017 INT_ENABLE_XL1 [15:12] Reserved Reserved. 0x0 R
11 INTX_EN_LEV1_L INT_LEV1_L interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV1_L status on Interrupt X.
10 INTX_EN_LEV1_K INT_LEV1_K interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV1_K status on Interrupt X.
9 INTX_EN_LEV1_J INT_LEV1_J interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV1_J status on Interrupt X.
8 INTX_EN_LEV1_I INT_LEV1_I interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV1_I status on Interrupt X.
7 INTX_EN_LEV1_H INT_LEV1_H interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV1_H status on Interrupt X.
6 INTX_EN_LEV1_G INT_LEV1_G interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV1_G status on Interrupt X.
5 INTX_EN_LEV1_F INT_LEV1_F interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV1_F status on Interrupt X.
4 INTX_EN_LEV1_E INT_LEV1_E interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV1_E status on Interrupt X.
3 INTX_EN_LEV1_D INT_LEV1_D interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV1_D status on Interrupt X.
2 INTX_EN_LEV1_C INT_LEV1_C interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV1_C status on Interrupt X.
1 INTX_EN_LEV1_B INT_LEV1_B interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV1_B status on Interrupt X.
0 INTX_EN_LEV1_A INT_LEV1_A interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV1_A status on Interrupt X.
0x001A INT_ENABLE_YL0 [15:12] Reserved Reserved. 0x0 R
11 INTY_EN_LEV0_L INT_LEV0_L interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV0_L status on Interrupt Y.
10 INTY_EN_LEV0_K INT_LEV0_K interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV0_K status on Interrupt Y.
9 INTY_EN_LEV0_J INT_LEV0_J interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV0_J status on Interrupt Y.
8 INTY_EN_LEV0_I INT_LEV0_I interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV0_I status on Interrupt Y.
7 INTY_EN_LEV0_H INT_LEV0_H interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV0_H status on Interrupt Y.
6 INTY_EN_LEV0_G INT_LEV0_G interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV0_G status on Interrupt Y.
5 INTY_EN_LEV0_F INT_LEV0_F interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV0_F status on Interrupt Y.
4 INTY_EN_LEV0_E INT_LEV0_E interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV0_E status on Interrupt Y.
3 INTY_EN_LEV0_D INT_LEV0_D interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV0_D status on Interrupt Y.

Rev. A | Page 64 of 82
Data Sheet ADPD4000/ADPD4001
Addr Name Bits Bit Name Description Reset Access1
2 INTY_EN_LEV0_C INT_LEV0_C interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV0_C status on Interrupt Y.
1 INTY_EN_LEV0_B INT_LEV0_B interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV0_B status on Interrupt Y.
0 INTY_EN_LEV0_A INT_LEV0_A interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV0_A status on Interrupt Y.
0x001B INT_ENABLE_YL1 [15:12] Reserved Reserved. 0x0 R
11 INTY_EN_LEV1_L INT_LEV1_L interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV1_L status on Interrupt Y.
10 INTY_EN_LEV1_K INT_LEV1_K interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV1_K status on Interrupt Y.
9 INTY_EN_LEV1_J INT_LEV1_J interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV1_J status on Interrupt Y.
8 INTY_EN_LEV1_I INT_LEV1_I interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV1_I status on Interrupt Y.
7 INTY_EN_LEV1_H INT_LEV1_H interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV1_H status on Interrupt Y.
6 INTY_EN_LEV1_G INT_LEV1_G interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV1_G status on Interrupt Y.
5 INTY_EN_LEV1_F INT_LEV1_F interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV1_F status on Interrupt Y.
4 INTY_EN_LEV1_E INT_LEV1_E interrupt enable. Write a 1 to this bit to enable 0x0 R/W
drive of INT_LEV1_E status on Interrupt Y.
3 INTY_EN_LEV1_D INT_LEV1_D interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV1_D status on Interrupt Y.
2 INTY_EN_LEV1_C INT_LEV1_C interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV1_C status on Interrupt Y.
1 INTY_EN_LEV1_B INT_LEV1_B interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV1_B status on Interrupt Y.
0 INTY_EN_LEV1_A INT_LEV1_A interrupt enable. Write a 1 to this bit to 0x0 R/W
enable drive of INT_LEV1_A status on Interrupt Y.
0x001E FIFO_STATUS_BYTES [15:6] Reserved Reserved. 0x0 R
5 ENA_STAT_LX Enable Level 0 and Level 1 interrupt status byte for 0x0 R/W
Time Slot I through Time Slot L. This byte contains the
interrupt status for the Level 0 and Level 1 interrupts for
Time Slot I through Time Slot L.
4 ENA_STAT_L1 Enable Level 1 interrupt status byte for Time Slot A 0x0 R/W
through Time Slot H. This byte contains the interrupt
status for the Level 1 interrupts for Time Slot A through
Time Slot H.
3 ENA_STAT_L0 Enable Level 0 interrupt status byte for Time Slot A 0x0 R/W
through Time Slot H. This byte contains the interrupt
status for Level Interrupt 0 for Time Slot A through Time
Slot H.
2 ENA_STAT_D2 Enable data interrupt status byte for Time Slot I through 0x0 R/W
Time Slot L. This byte contains the data interrupt status for
Time Slot I through Time Slot L.
1 ENA_STAT_D1 Enable data interrupt status byte for Time Slot A through 0x0 R/W
Time Slot H. This byte is the data interrupt status for Time
Slot A through Time Slot H.
0 ENA_STAT_SUM Enable status summary byte. When enabled write a status 0x0 R/W
byte containing the summary pattern to the FIFO
following the last enabled time slot data.
1
R/W1C means write 1 to clear.

Rev. A | Page 65 of 82
ADPD4000/ADPD4001 Data Sheet
THRESHOLD SETUP AND CONTROL REGISTERS
Table 28. Register Details
Addr Name Bits Bit Name Description Reset Access
0x0006 FIFO_TH [15:8] Reserved Reserved. 0x0 R
[7:0] FIFO_TH FIFO interrupt generation threshold. Generate FIFO interrupt during a 0x0 R/W
FIFO write when the number of bytes in the FIFO exceeds this value.
The FIFO is 256 bytes. Therefore, the maximum value for FIFO_TH is
0xFF.
0x0115 THRESH_CFG_A [15:8] Reserved Reserved. 0x0 R
0x0135 THRESH_CFG_B 7 THRESH1_CHAN_x Select channel for Level 1 interrupt. 0x0 R/W
0x0155 THRESH_CFG_C 0: use Channel 1.
0x0175 THRESH_CFG_D 1: use Channel 2.
0x0195 THRESH_CFG_E 6 THRESH1_DIR_x Direction of comparison for Level 1 interrupt. 0x0 R/W
0x01B5 THRESH_CFG_F 0: set when below Level 1 interrupt threshold.
0x01D5 THRESH_CFG_G 1: set when above Level 1 interrupt threshold.
0x01F5 THRESH_CFG_H [5:4] THRESH1_TYPE_x Type of comparison for Level 1 interrupt. 0x0 R/W
0x0215 THRESH_CFG_I 0: off (no comparison).
0x0235 THRESH_CFG_J 1: compare to signal.
0x0255 THRESH_CFG_K 10: compare to dark.
0x0275 THRESH_CFG_L 11: reserved.
3 THRESH0_CHAN_x Select channel for Level 0 interrupt. 0x0 R/W
0: use Channel 1.
1: use Channel 2.
2 THRESH0_DIR_x Direction of comparison for Level 0 interrupt. 0x0 R/W
0: set when below Level 0 interrupt threshold.
1: set when above Level 0 interrupt threshold.
[1:0] THRESH0_TYPE_x Type of comparison for Level 0 interrupt. 0x0 R/W
0: off (no comparison).
1: compare to signal.
10: compare to dark.
11: reserved.
0x0116 THRESH0_A [15:13] Reserved Reserved. 0x0 R
0x0136 THRESH0_B [12:8] THRESH0_SHIFT_x Shift for Level 0 interrupt comparison threshold. Shift 0x0 R/W
0x0156 THRESH0_C THRESH0_VALUE_x by this amount before comparing.
0x0176 THRESH0_D [7:0] THRESH0_VALUE_x Value for Level 0 interrupt comparison threshold. 0x0 R/W
0x0196 THRESH0_E
0x01B6 THRESH0_F
0x01D6 THRESH0_G
0x01F6 THRESH0_H
0x0216 THRESH0_I
0x0236 THRESH0_J
0x0256 THRESH0_K
0x0276 THRESH0_L
0x0117 THRESH1_A [15:13] Reserved Reserved. 0x0 R
0x0137 THRESH1_B [12:8] THRESH1_SHIFT_x Shift for Level 1 interrupt comparison threshold. Shift 0x0 R/W
0x0157 THRESH1_C THRESH1_VALUE_x by this amount before comparing.
0x0177 THRESH1_D [7:0] THRESH1_VALUE_x Value for Level 1 interrupt comparison threshold. 0x0 R/W
0x0197 THRESH1_E
0x01B7 THRESH1_F
0x01D7 THRESH1_G
0x01F7 THRESH1_H
0x0217 THRESH1_I
0x0237 THRESH1_J
0x0257 THRESH1_K
0x0277 THRESH1_L

Rev. A | Page 66 of 82
Data Sheet ADPD4000/ADPD4001
CLOCK AND TIMESTAMP SETUP AND CONTROL REGISTERS
Table 29. Register Details
Addr Name Bits Bit Name Description Reset Access
0x0009 OSC32M [15:8] Reserved Reserved. 0x0 R
[7:0] OSC_32M_FREQ_ADJ
High frequency oscillator frequency control. 0x00 is the lowest 0x90 R/W
frequency, and 0xFF is maximum frequency.
0x000A OSC32M_CAL 15 OSC_32M_CAL_START Start high frequency oscillator calibration cycle. Writing a 1 to 0x0 R/W
this bit causes the high frequency oscillator calibration cycle to
occur. 32 MHz oscillator cycles are counted during 128 low
frequency oscillator cycles if using the 1 MHz low frequency
oscillator, or 32 low frequency oscillator cycles if using the
32 kHz low frequency oscillator. The OSC_32M_CAL_COUNT
bit field is updated with the count. The calibration circuit clears
the OSC_32M_CAL_START bit when the calibration cycle is
completed.
[14:0] OSC_32M_CAL_COUNT High frequency oscillator calibration count. This bit field 0x0 R
contains the total number of 32 MHz cycles that occurred
during the last high frequency oscillator calibration cycle.
0x000B OSC1M [15:10] Reserved Reserved. 0x0 R
[9:0] OSC_1M_FREQ_ADJ Low frequency oscillator frequency control. 0x000 is the lowest 0x2B2 R/W
frequency, and 0x3FF is maximum frequency.
0x000C OSC32K 15 CAPTURE_TIMESTAMP Enable time stamp capture. This bit field is used to activate the 0x0 R/W
time stamp capture function. When set, the next rising edge
on the time stamp input (defaults to GPIO0) causes a time
stamp capture. This bit field is cleared when the time stamp
occurs.
[14:6] Reserved Reserved. 0x0 R
[5:0] OSC_32K_ADJUST 32 kHz oscillator trim. 0x12 R/W
00 0000: maximum frequency.
01 0010: default frequency.
11 1111: minimum frequency.
0x0011 STAMP_L [15:0] TIMESTAMP_COUNT_L Count at last time stamp. Lower 16 bits. 0x0 R
0x0012 STAMP_H [15:0] TIMESTAMP_COUNT_H Count at last time stamp. Upper 16 bits. 0x0 R
0x0013 STAMPDELTA [15:0] TIMESTAMP_SLOT_DELTA Count remaining until next time slot start. 0x0 R

Rev. A | Page 67 of 82
ADPD4000/ADPD4001 Data Sheet
SYSTEM REGISTERS
Table 30. Register Details
Addr Name Bits Bit Name Description Reset Access
0x0008 CHIP_ID [15:8] Version Mask version. 0x0 R
[7:0] CHIP_ID Chip ID. 0xC0 R
0x002E DATA_HOLD_FLAG [15:12] Reserved Reserved. 0x0 R
11 HOLD_REGS_L Prevent update of Time Slot L data registers. 0x0 R/W
0: allow data register update.
1: hold current contents of data register.
10 HOLD_REGS_K Prevent update of time Slot K data registers. 0x0 R/W
0: allow data register update.
1: hold current contents of data register.
9 HOLD_REGS_J Prevent update of Time Slot J data registers. 0x0 R/W
0: allow data register update.
1: hold current contents of data register.
8 HOLD_REGS_I Prevent update of Time Slot I data registers. 0x0 R/W
0: allow data register update.
1: hold current contents of data register.
7 HOLD_REGS_H Prevent Update of Time Slot H data registers. 0x0 R/W
0: allow data register update.
1: hold current contents of data register.
6 HOLD_REGS_G Prevent update of Time Slot G data registers. 0x0 R/W
0: allow data register update.
1: hold current contents of data register.
5 HOLD_REGS_F Prevent update of Time Slot F data registers. 0x0 R/W
0: allow data register update.
1: hold current contents of data register.
4 HOLD_REGS_E Prevent update of Time Slot E data registers. 0x0 R/W
0: allow data register update.
1: hold current contents of data register.
3 HOLD_REGS_D Prevent update of Time Slot D data registers. 0x0 R/W
0: allow data register update.
1: hold current contents of data register.
2 HOLD_REGS_C Prevent update of Time Slot C data registers. 0x0 R/W
0: allow data register update.
1: hold current contents of data register.
1 HOLD_REGS_B Prevent update of Time Slot B data registers. 0x0 R/W
0: allow data register update.
1: hold current contents of data register.
0 HOLD_REGS_A Prevent update of Time Slot A data registers. 0x0 R/W
0: allow data register update.
1: hold current contents of data register.
0x00B6 I2C_KEY [15:12] I2C_KEY_MATCH Write the I2C_KEY_MATCH bit field to specify which GPIO pins 0x0 R/W
must be high to change the slave address. A 0 ignores that
specific GPIO input. A 1 selects which GPIO must be high to
change the address. Any combination is allowed. Use Bit 12 for
GPIO0, Bit 13 for GPIO1, Bit 14 for GPIO2, and Bit 15 for GPIO3.
[11:0] I2C_KEY I2C address change key. Must write these bits to 0x4AD to change 0x0 R0/W
address. Write this bit field at the same time that the
I2C_KEY_MATCH bit field is written.

Rev. A | Page 68 of 82
Data Sheet ADPD4000/ADPD4001
Addr Name Bits Bit Name Description Reset Access
0x00B7 I2C_ADDR [15:8] I2C_SLAVE_KEY2 I2C key Part 2. Must be written to 0xAD immediately following the 0x0 R/W
write of the I2C_KEY bit field. The GPIO bits as selected in the
I2C_KEY_MATCH bit field must also be set high at this time.
[7:1] I2C_SLAVE_ADDR I2C slave address update field. Write the desired 7-bit slave 0x24 R/W
address along with proper keys to change the I2C slave address.
0 Reserved Reserved. 0x0 R

I/O SETUP AND CONTROL REGISTERS

Table 31. Register Details
Addr Name Bits Bit Name Description Reset Access
0x0022 GPIO_CFG [15:14] GPIO_SLEW Slew control for GPIO pins. 0x0 R/W
0: slowest.
1: slow.
10: fastest.
11: fast.
[13:12] GPIO_DRV Drive control for GPIO pins. 0x0 R/W
0: medium.
1: weak.
10: strong.
11: strong.
[11:9] GPIO_PIN_CFG3 GPIO3 pin configuration. 0x0 R/W
000: disabled (tristate, input buffer off ).
001: enabled input.
010: output—normal.
011: output—inverted.
100: pull-down only—normal.
101: pull-down only—inverted.
110: pull-up only—normal.
111: pull-up only—inverted.
[8:6] GPIO_PIN_CFG2 GPIO2 pin configuration. 0x0 R/W
000: disabled (tristate, input buffer off ).
001: enabled input.
010: output—normal.
011: output—inverted.
100: pulldown only—normal.
101: pull-down only—inverted.
110: pull-up only—normal.
111: pull-up only—inverted.
[5:3] GPIO_PIN_CFG1 GPIO1 pin configuration. 0x0 R/W
000: disabled (tristate, input buffer off ).
001: enabled input.
010: output—normal.
011: output—inverted.
100: pull-down only—normal.
101: pull-down only—inverted.
110: pull-up only—normal.
111: pull-up only—inverted.
[2:0] GPIO_PIN_CFG0 GPIO0 pin configuration. 0x0 R/W
000: disabled (tristate, input buffer off ).
001: enabled input.
010: output—normal.
011: output—inverted.
100: pull-down only—normal.
Rev. A | Page 69 of 82
ADPD4000/ADPD4001 Data Sheet
Addr Name Bits Bit Name Description Reset Access
101: pull-down only—inverted.
110: pull-up only—normal.
111: pull-up only—inverted.
0x0023 GPIO01 15 Reserved Reserved. 0x0 R
[14:8] GPIOOUT1 GPIO1 output signal select. 0x0 R/W
0x00: Output Logic 0.
0x01: Output Logic 1.
0x02: Interrupt X.
0x03: Interrupt Y.
0x08: LED1A pulse.
0x09: LED1B pulse.
0x0A: LED2A pulse.
0x0B: LED2B pulse.
0x0C: LED3A pulse.
0x0D: LED3B pulse.
0x0E: LED4A pulse.
0x0F: LED4B pulse.
0x10: any LED pulse.
0x11: in sleep state.
0x16: low frequency oscillator output.
0x17: 32 MHz oscillator output.
0x18: 32 MHz oscillator output divided by 32 (1 MHz).
0x30: Time Slot A LED pulse.
0x31: Time Slot B LED pulse.
0x32: Time Slot C LED pulse.
0x33: Time Slot D LED pulse.
0x34: Time Slot E LED pulse.
0x35: Time Slot F LED pulse.
0x36: Time Slot G LED pulse.
0x37: Time Slot H LED pulse.
0x38: Time Slot I LED pulse.
0x39: Time Slot J LED pulse.
0x3A: Time Slot K LED pulse.
0x3B: Time Slot L LED pulse.
0x3F: any timeslot LED pulse.
0x40: Time Slot A modulation pulse.
0x41: Time Slot B modulation pulse.
0x42: Time Slot C modulation pulse.
0x43: Time Slot D modulation pulse.
0x44: Time Slot E modulation pulse.
0x45: Time Slot F modulation pulse.
0x46: Time Slot G modulation pulse.
0x47: Time Slot H modulation pulse.
0x48: Time Slot I modulation pulse.
0x49: Time Slot J modulation pulse.
0x4A: Time Slot K modulation pulse.
0x4B: Time Slot L modulation pulse.
0x4F: any time slot modulation pulse.
0x50: output data cycle occurred in Time Slot A, which is useful
when synchronizing an external device to a decimated data rate
from the ADPD4000/ADPD4001.
0x51: output data cycle occurred in Time Slot B.
0x52: output data cycle occurred in Time Slot C.
0x53: output data cycle occurred in Time Slot D.
Rev. A | Page 70 of 82
Data Sheet ADPD4000/ADPD4001
Addr Name Bits Bit Name Description Reset Access
0x54: output data cycle occurred in Time Slot E.
0x55: output data cycle occurred in Time Slot F.
0x56: output data cycle occurred in Time Slot G.
0x57: output data cycle occurred in Time Slot H.
0x58: output data cycle occurred in Time Slot I.
0x59: output data cycle occurred in Time Slot J.
0x5A: output data cycle occurred in Time Slot K.
0x5B: output data cycle occurred in Time Slot L.
0x5F: output data cycle occurred in any time slot.
7 Reserved Reserved. 0x0 R
[6:0] GPIOOUT0 GPIO0 output signal select. Options are identical to those 0x0 R/W
described in GPIOOUT1.
0x0024 GPIO23 15 Reserved Reserved. 0x0 R
[14:8] GPIOOUT3 GPIO3 output signal select. Options are identical to those 0x0 R/W
described in GPIOOUT1.
7 Reserved Reserved. 0x0 R
[6:0] GPIOOUT2 GPIO2 output signal select. Options are identical to those 0x0 R/W
described in GPIOOUT1.
0x0025 GPIO_IN [15:4] Reserved Reserved. 0x0 R
[3:0] GPIO_INPUT GPIO input value (if enabled). Read back the value present on any 0x0 R
GPIO enabled as an input. Bit 0 is GPIO1, Bit 1 is GPIO1, Bit 2 is
GPIO2, and Bit 3 is GPIO3.
0x0026 GPIO_EXT [15:8] Reserved Reserved. 0x0 R
7 TIMESTAMP_INV Time stamp trigger invert. 0x0 R/W
0: time stamp trigger is rising edge.
1: time stamp trigger is falling edge.
6 TIMESTAMP_ALWAYS_EN Enable time stamp always on. When set, do not automatically 0x0 R/W
clear CAPTURE_TIMESTAMP. This bit provides an always activated
time stamp.
[5:4] TIMESTAMP_GPIO Time stamp GPIO select. 0x0 R/W
0x0: use GPIO0 for time stamp (default).
0x1: use GPIO1 for time stamp.
0x2: use GPIO2 for time stamp.
0x3: use GPIO3 for time stamp
3 Reserved Reserved. 0x0 R/W
2 EXT_SYNC_EN External sync enable. When enabled, use the GPIO selected by 0x0 R/W
EXT_SYNC_GPIO to trigger samples rather than the period
counter.
[1:0] EXT_SYNC_GPIO External synchronization GPIO select. 0x0 R/W
00: use GPIO0 for external synchronization
01: use GPIO1 for external synchronization.
10: use GPIO2 for external synchronization.
11: use GPIO3 for external synchronization.
0x00B4 IO_ADJUST [15:4] Reserved Set to 0x005. 0x005 R/W
[3:2] SPI_SLEW Slew control for SPI pins. 0x0 R/W
0: slowest.
1: slow.
10: fastest.
11: fast.
[1:0] SPI_DRV Drive control for SPI pins. 0x0 R/W
0: medium.
1: weak.
10: strong.
11: strong.

Rev. A | Page 71 of 82
ADPD4000/ADPD4001 Data Sheet
TIME SLOT CONFIGURATION REGISTERS
Table 32. Register Details
Addr Name Bits Bit Name Description Reset Access
0x0100 TS_CTRL_A 15 Reserved Reserved. 0x0 R
0x0120 TS_CTRL_B 14 CH2_EN_x Channel 2 enable. 0x0 R/W
0x0140 TS_CTRL_C 0: Channel 2 disabled.
0x0160 TS_CTRL_D 1: Channel 2 enabled.
0x0180 TS_CTRL_E [13:12] SAMPLE_TYPE_x Time Slot x sampling type. 0x0 R/W
0x01A0 TS_CTRL_F 00: standard sampling modes.
0x01C0 TS_CTRL_G 01: one-region digital integration mode.
0x01E0 TS_CTRL_H 10: two-region digital integration mode.
0x0200 TS_CTRL_I 11: impulse response mode.
0x0220 TS_CTRL_J [11:10] INPUT_R_SELECT_x Input resistor (RIN) select. 0x0 R/W
0x0240 TS_CTRL_K 00: 500 Ω.
0x0260 TS_CTRL_L 01: 6.25 kΩ.
10: reserved.
11: reserved.
[9:0] TIMESLOT_OFFSET_x Time Slot x offset in 64 × number of 1 MHz low frequency 0x0 R/W
oscillator cycles or 2 × number of 32 kHz low frequency
oscillator cycles.
0x0101 TS_PATH_A [15:12] PRE_WIDTH_x Preconditioning duration for Time Slot x. This value is in 2 μs 0x4 R/W
0x0121 TS_PATH_B increments. A value of 0 skips the preconditioning state.
0x0141 TS_PATH_C Default is 8 μs.
0x0161 TS_PATH_D [11:9] Reserved Write 0x0. 0x0 R
0x0181 TS_PATH_E [8:0] AFE_PATH_CFG_x Signal path selection. 0x1DA R/W
0x01A1 TS_PATH_F 0x1DA: TIA, BPF, integrator, and ADC.
0x01C1 TS_PATH_G 0x0E6: TIA, integrator, and ADC.
0x01E1 TS_PATH_H 0x106: TIA and ADC.
0x0201 TS_PATH_I 0x101: ADC.
0x0221 TS_PATH_J 0x0E1: buffer and ADC.
0x0241 TS_PATH_K
0x0261 TS_PATH_L
0x0102 INPUTS_A [15:12] INP78_x IN7 and IN8 input pair enable. 0x0 R/W
0x0122 INPUTS_B 0000: input pair disabled. IN7 and IN8 disconnected.
0x0142 INPUTS_C 0001: IN7 connected to Channel 1. IN8 disconnected.
0x0162 INPUTS_D 0010: IN7 connected to Channel 2. IN8 disconnected.
0x0182 INPUTS_E 0011: IN7 disconnected. IN8 connected to Channel 1.
0x01A2 INPUTS_F 0100: IN7 disconnected. IN8 connected to Channel 2.
0x01C2 INPUTS_G 0101: IN7 connected to Channel 1. IN8 connected to Channel 2.
0x01E2 INPUTS_H 0110: IN7 connected to Channel 2. IN8 connected to Channel 1.
0x0202 INPUTS_I 0111: IN7 and IN8 connected to Channel 1. Single-ended or
0x0222 INPUTS_J differentially based on PAIR78.
0x0242 INPUTS_K 1000: IN7 and IN8 connected to Channel 2. Single-ended or
0x0262 INPUTS_L differentially based on PAIR78.
[11:8] INP56_x IN5 and IN6 input pair enable. 0x0 R/W
0000: input pair disabled. IN5 and IN6 disconnected.
0001: IN5 connected to Channel 1. IN6 disconnected.
0010: IN5 connected to Channel 2. IN6 disconnected.
0011: IN5 disconnected. IN6 connected to Channel 1.
0100: IN5 disconnected. IN6 connected to Channel 2.
0101: IN5 connected to Channel 1. IN6 connected to Channel 2.

Rev. A | Page 72 of 82
Data Sheet ADPD4000/ADPD4001
Addr Name Bits Bit Name Description Reset Access
0110: IN5 connected to Channel 2. IN6 connected to Channel 1.
0111: IN5 and IN6 connected to Channel 1. Single-ended or
differentially based on PAIR56.
1000: IN5 and IN6 connected to Channel 2. Single-ended or
differentially based on PAIR56.
[7:4] INP34_x IN3 and IN4 input pair enable. 0x0 R/W
0000: input pair disabled. IN3 and IN4 disconnected.
0001: IN3 connected to Channel 1. IN4 disconnected.
0010: IN3 connected to Channel 2. IN4 disconnected.
0011: IN3 disconnected. IN4 connected to Channel 1.
0100: IN3 disconnected. IN4 connected to Channel 2.
0101: IN3 connected to Channel 1. IN4 connected to Channel 2.
0110: IN3 connected to Channel 2. IN4 connected to Channel 1.
0111: IN3 and IN4 connected to Channel 1. Single-ended or
differentially based on PAIR34.
1000: IN3 and IN4 connected to Channel. Single-ended or
differentially based on PAIR34.
[3:0] INP12_x IN1 and IN2 input pair enable. 0x0 R/W
0000: input pair disabled. IN1 and IN2 disconnected.
0001: IN1 connected to Channel 1. IN2 disconnected.
0010: IN1 connected to Channel 2. IN2 disconnected.
0011: IN1 disconnected. IN2 connected to Channel 1.
0100: IN1 disconnected. IN2 connected to Channel 2.
0101: IN1 connected to Channel 1. IN2 connected to Channel 2.
0110: IN1 connected to Channel 2. IN2 connected to Channel 1.
0111: IN1 and IN2 connected to Channel 1. Single-ended or
differentially based on PAIR12.
1000: IN1 and IN2 connected to Channel 2. Single-ended or
differentially based on PAIR12.
0x0103 CATHODE_A 15 Reserved Reserved. 0x0 R
0x0123 CATHODE_B [14:12] PRECON_x Precondition value for enabled inputs during Time Slot x. 0x0 R/W
0x0143 CATHODE_C 000: float input(s).
0x0163 CATHODE_D 001: precondition to VC1.
0x0183 CATHODE_E 010: precondition to VC2.
0x01A3 CATHODE_F 011: precondition to VICM. Used when inputs are configured
0x01C3 CATHODE_G differentially.
0x01E3 CATHODE_H 100: precondition with TIA input.
0x0203 CATHODE_I 101: precondition with TIA_VREF.
0x0223 CATHODE_J 110: precondition by shorting differential pair.
0x0243 CATHODE_K [11:10] VC2_PULSE_x VC2 pulse control for Time Slot x. 0x0 R/W
0x0263 CATHODE_L 00: no pulsing.
01: alternate VC2 on each subsequent Time Slot x.
10: pulse to alternate value specified in VC2_ALT_x using
modulation pulse.
[9:8] VC2_ALT_x VC2 alternate pulsed state for Time Slot x. 0x0 R/W
00: VDD.
01: TIA_VREF.
10: TIA_VREF + 250 mV.
11: GND.
[7:6] VC2_SEL_x VC2 active state for Time Slot x. 0x0 R/W
00: VDD.
01: TIA_VREF.
10: TIA_VREF + 250 mV.
11: GND.

Rev. A | Page 73 of 82
ADPD4000/ADPD4001 Data Sheet
Addr Name Bits Bit Name Description Reset Access
[5:4] VC1_PULSE_x VC1 pulse control for Time Slot x. 0x0 R/W
00: no pulsing.
01: alternate VC1 on each subsequent Time Slot x.
10: pulse to alternate value specified in VC1_ALT_x using
modulation pulse.
[3:2] VC1_ALT_x VC1 alternate pulsed state for Time Slot x. 0x0 R/W
00: VDD.
01: TIA_VREF.
10: TIA_VREF + 250 mV.
11: GND.
[1:0] VC1_SEL_x VC1 active state for Time Slot x. 0x0 R/W
00: VDD.
01: TIA_VREF.
10: TIA_VREF + 250 mV.
11: GND.
0x0104 AFE_TRIM_A [15:13] Reserved Write to 0x7. 0x7 R/W
0x0124 AFE_TRIM_B [12:11] AFE_TRIM_INT_x Set the integrator input resistor when AFE_INT_C_BUF_x = 0. 0x0 R/W
0x0144 AFE_TRIM_C Set the buffer gain when AFE_INT_C_BUF_x = 1
0x0164 AFE_TRIM_D AFE_INT_C_BUF_x = 0 AFE_INT_C_BUF_x = 1
0x0184 AFE_TRIM_E 00: 400 kΩ. 00: gain = 1.
0x01A4 AFE_TRIM_F 01: 200 kΩ. 01: gain = 1.
0x01C4 AFE_TRIM_G 10: 100 kΩ. 10: gain = 0.7.
0x01E4 AFE_TRIM_H 11: 100 kΩ. 11: gain = 0.7.
0x0204 AFE_TRIM_I 10 VREF_PULSE_x TIA_VREF pulse control. 0x0 R/W
0x0224 AFE_TRIM_J 0: no pulsing.
0x0244 AFE_TRIM_K 1: pulse TIA_VREF based on modulation pulse.
0x0264 AFE_TRIM_L [9:8] AFE_TRIM_VREF_x Voltage select for TIA_VREF. 0x3 R/W
00: TIA_VREF = 1.1385 V.
01: TIA_VREF = 1.012 V.
10: TIA_VREF = 0.8855 V.
11: TIA_VREF = 1.265 V.
[7:6] VREF_PULSE_VAL_x TIA_VREF pulse alternate value. 0x3 R/W
00: modulate TIA_VREF = 1.1385 V.
01: modulate TIA_VREF = 1.012 V.
10: modulate TIA_VREF = 0.8855 V.
11: modulate TIA_VREF = 1.265 V.
[5:3] TIA_GAIN_CH2_x TIA resistor gain setting for Channel 2. 0x0 R/W
000: 200 kΩ.
001: 100 kΩ.
010: 50 kΩ.
011: 25 kΩ.
100: 12.5 kΩ.
[2:0] TIA_GAIN_CH1_x TIA resistor gain setting for Channel 1. 0x0 R/W
000: 200 kΩ.
001: 100 kΩ.
010: 50 kΩ.
011: 25 kΩ.
100: 12.5 kΩ.

Rev. A | Page 74 of 82
Data Sheet ADPD4000/ADPD4001
Addr Name Bits Bit Name Description Reset Access
0x010D PATTERN_A [15:12] LED_DISABLE_x Four-pulse LED disable pattern. Set to 1 to disable the LED 0x0 R/W
0x012D PATTERN_B pulse in the matching position in a group of four pulses. The
0x014D PATTERN_C LSB maps to the first pulse.
0x016D PATTERN_D [11:8] MOD_DISABLE_x Four-pulse modulation disable pattern. Set to 1 to disable 0x0 R/W
0x018D PATTERN_E the modulation pulse in the matching position in a group of
0x01AD PATTERN_F four pulses. The LSB maps to the first pulse.
0x01CD PATTERN_G [7:4] SUBTRACT_x Four-pulse subtract pattern. Set to 1 to negate the math 0x0 R/W
0x01ED PATTERN_H operation in the matching position in a group of four pulses.
0x020D PATTERN_I The LSB maps to the first pulse.
0x022D PATTERN_J [3:0] REVERSE_INTEG_x Four-pulse integration reverse pattern. Set to 1 to reverse the 0x0 R/W
0x024D PATTERN_K integrator positive/negative pulse order in the matching
0x026D PATTERN_L position in a group of four pulses. The LSB maps to the first
pulse.
0x0110 DATA_FORMAT_A [15:11] DARK_SHIFT_x Number of bits to shift the dark data to the right before 0x0 R/W
0x0130 DATA_FORMAT_B writing to the FIFO for Time Slot x. Selectable between 0 bits
0x0150 DATA_FORMAT_C and 32 bits.
0x0170 DATA_FORMAT_D [10:8] DARK_SIZE_x Number of bytes of dark data to be written to the FIFO for 0x0 R/W
0x0190 DATA_FORMAT_E Time Slot x. Selectable between 0 bytes and four bytes.
0x01B0 DATA_FORMAT_F [7:3] SIGNAL_SHIFT_x Number of bits to shift the signal data to the right before 0x0 R/W
0x01D0 DATA_FORMAT_G writing to the FIFO for Time Slot x. Selectable between 0 bits
0x01F0 DATA_FORMAT_H and 32 bits.
0x0210 DATA_FORMAT_I [2:0] SIGNAL_SIZE_x Number of bytes of signal data to be written to the FIFO for 0x3 R/W
0x0230 DATA_FORMAT_J Time Slot x. Selectable between 0 bytes and four bytes.
0x0250 DATA_FORMAT_K
0x0270 DATA_FORMAT_L
0x0112 DECIMATE_A [15:11] Reserved Write 0x0. 0x0 R
0x0132 DECIMATE_B [10:4] DECIMATE_FACTOR_x Decimate sample divider. Output data rate is sample rate ÷ 0x0 R/W
0x0152 DECIMATE_C (DECIMATE_FACTOR_x + 1). Decimate by 1 to 128.
0x0172 DECIMATE_D [3:0] DECIMATE_TYPE_x Decimation type select. 0x0 R/W
0x0192 DECIMATE_E 0: block sum, CIC first order.
0x01B2 DECIMATE_F 1: signal uses CIC second order.
0x01D2 DECIMATE_G 10: signal uses CIC third order.
0x01F2 DECIMATE_H 11: signal uses CIC fourth order.
0x0212 DECIMATE_I 100: reserved.
0x0232 DECIMATE_J
0x0252 DECIMATE_K
0x0272 DECIMATE_L

Rev. A | Page 75 of 82
ADPD4000/ADPD4001 Data Sheet
AFE TIMING SETUP REGISTERS
Table 33. Register Details
Addr Name Bits Bit Name Description Reset Access
0x0107 COUNTS_A [15:8] NUM_INT_x Number of ADC cycles or acquisition width. Number of analog 0x1 R/W
0x0127 COUNTS_B integration cycles per ADC conversion or the acquisition width
0x0147 COUNTS_C for digital integration and impulse mode. A setting of 0 is not
allowed.
0x0167 COUNTS_D
0x0187 COUNTS_E [7:0] NUM_REPEAT_x Number of sequence repeats. Total number of pulses = 0x1 R/W
0x01A7 COUNTS_F NUM_INT_x × NUM_REPEAT_x. A setting of 0 is not allowed.
0x01C7 COUNTS_G
0x01E7 COUNTS_H
0x0207 COUNTS_I
0x0227 COUNTS_J
0x0247 COUNTS_K
0x0267 COUNTS_L
0x0108 PERIOD_A [15:14] Reserved Reserved. 0x0 R
0x0128 PERIOD_B [13:12] MOD_TYPE_x Modulation connection type. 0x0 R/W
0x0148 PERIOD_C 00: TIA is continuously connected to input after precondition.
0x0168 PERIOD_D No connection modulation.
0x0188 PERIOD_E 01: float type operation. Pulse connection from input to TIA
0x01A8 PERIOD_F with modulation pulse, floating between pulses.
0x01C8 PERIOD_G 10: nonfloat type connection modulation. Pulse connection
0x01E8 PERIOD_H from input to TIA. Connect to precondition value between
0x0208 PERIOD_I pulses.
0x0228 PERIOD_J [11:10] Reserved Reserved. 0x0 R
0x0248 PERIOD_K [9:0] MIN_PERIOD_x Minimum period for pulse repetition in μs. Override for the 0x0 R/W
0x0268 PERIOD_L automatically calculated period. Used in float type operations
to set the float time of second and subsequent floats using the
formula: Float Time = MIN_PERIOD_x − MOD_WIDTH_x.
0x010A INTEG_SETUP_A 15 SINGLE_INTEG_x Use single integrator pulse 0x0 R/W
0x012A INTEG_SETUP_B 0: use both generated integrator clocks.
0x014A INTEG_SETUP_C 1: skip the second integrator clock.
0x016A INTEG_SETUP_D [14:12] CH2_AMP_DISABLE_x Amplifier disables for power control. Set the appropriate bit to 0x0 R/W
disable the Channel 2 amplifier in Time Slot x.
0x018A INTEG_SETUP_E 0: TIA.
0x01AA INTEG_SETUP_F 1: band-pass filter.
0x01CA INTEG_SETUP_G 2: integrator.
0x01EA INTEG_SETUP_H
0x020A INTEG_SETUP_I 11 AFE_INT_C_BUF_x Set to 1 to configure the integrator as a buffer in Time Slot x. 0x0 R/W
0x022A INTEG_SETUP_J [10:8] CH1_AMP_DISABLE_x Amplifier disables for power control. Set the appropriate bit to 0x0 R/W
0x024A INTEG_SETUP_K disable the Channel 1 amplifier in Time Slot x.
0x026A INTEG_SETUP_L 0: TIA.
1: band-pass filter.
2: integrator.
[7:6] ADC_COUNT_x ADC conversions per pulse. Number of conversions = 0x0 R/W
ADC_COUNT + 1.
5 Reserved Reserved. 0x0 R
[4:0] INTEG_WIDTH_A Integrator clock width in μs. 0x3 R/W

Rev. A | Page 76 of 82
Data Sheet ADPD4000/ADPD4001
Addr Name Bits Bit Name Description Reset Access
0x010B INTEG_OS_A [15:13] Reserved Reserved. 0x0 R
0x012B INTEG_OS_B [12:8] INTEG_FINE_OFFSET_x Integrator clock fine offset for Time Slot x in 31.25 ns 0x14 R/W
0x014B INTEG_OS_C increments per LSB.
0x016B INTEG_OS_D [7:0] INTEG_OFFSET_x Integrator clock coarse offset for Time Slot x in 1 µs increments 0x10 R/W
0x018B INTEG_OS_E per LSB.
0x01AB INTEG_OS_F
0x01CB INTEG_OS_G
0x01EB INTEG_OS_H
0x020B INTEG_OS_I
0x022B INTEG_OS_J
0x024B INTEG_OS_K
0x026B INTEG_OS_L
0x010C MOD_PULSE_A [15:8] MOD_WIDTH_x Modulation pulse width for Time Slot x in μs. 0 = disable. 0x1 R/W
0x012C MOD_PULSE_B [7:0] MOD_OFFSET_x Modulation pulse offset for Time Slot x in μs. 0x0 R/W
0x014C MOD_PULSE_C
0x016C MOD_PULSE_D
0x018C MOD_PULSE_E
0x01AC MOD_PULSE_F
0x01CC MOD_PULSE_G
0x01EC MOD_PULSE_H
0x020C MOD_PULSE_I
0x022C MOD_PULSE_J
0x024C MOD_PULSE_K
0x026C MOD_PULSE_L
0x0113 DIGINT_LIT_A [15:9] Reserved Reserved. 0x0 R
0x0133 DIGINT_LIT_B [8:0] LIT_OFFSET_x Digital integration mode, acquisition window lit offset in μs for 0x26 R/W
0x0153 DIGINT_LIT_C Time Slot x. Also, impulse response mode offset.
0x0173 DIGINT_LIT_D
0x0193 DIGINT_LIT_E
0x01B3 DIGINT_LIT_F
0x01D3 DIGINT_LIT_G
0x01F3 DIGINT_LIT_H
0x0213 DIGINT_LIT_I
0x0233 DIGINT_LIT_J
0x0253 DIGINT_LIT_K
0x0273 DIGINT_LIT_L
0x0114 DIGINT_DARK_A [15:7] DARK2_OFFSET_x Digital integration mode, acquisition window Dark Offset 2 for 0x046 R/W
0x0134 DIGINT_DARK_B Time Slot x in μs.
0x0154 DIGINT_DARK_C [6:0] DARK1_OFFSET_x Digital integration mode, acquisition window Dark Offset 1 for 0x6 R/W
0x0174 DIGINT_DARK_D Time Slot x in μs.
0x0194 DIGINT_DARK_E
0x01B4 DIGINT_DARK_F
0x01D4 DIGINT_DARK_G
0x01F4 DIGINT_DARK_H
0x0214 DIGINT_DARK_I
0x0234 DIGINT_DARK_J
0x0254 DIGINT_DARK_K
0x0274 DIGINT_DARK_L

Rev. A | Page 77 of 82
ADPD4000/ADPD4001 Data Sheet
LED CONTROL AND TIMING REGISTERS
Table 34. Register Details
Addr Name Bits Bit Name Description Reset Access
0x0105 LED_POW12_A 15 LED_DRIVESIDE2_x LED output select for LED2x. 0x0 R/W
0x0125 LED_POW12_B 0: drive LED on Output LED2A.
0x0145 LED_POW12_C 1: drive LED on Output LED2B.
0x0165 LED_POW12_D [14:8] LED_CURRENT2_x LED current setting for LED2A or LED2B output. Set to 0 to disable. 0x0 R/W
0x0185 LED_POW12_E Output current varies monotonically from 2 mA to 200 mA for values
0x01A5 LED_POW12_F between 0x01 and 0x7F.
0x01C5 LED_POW12_G 7 LED_DRIVESIDE1_x LED output select for LED1x. 0x0 R/W
0x01E5 LED_POW12_H 0: drive LED on Output LED1A.
0x0205 LED_POW12_I 1: drive LED on Output LED1B.
0x0225 LED_POW12_J [6:0] LED_CURRENT1_x LED current setting for LED1A or LED1B output. Set to 0 to disable. 0x0 R/W
0x0245 LED_POW12_K Output current varies monotonically from 2 mA to 200 mA for values
0x0265 LED_POW12_L between 0x01 and 0x7F.
0x0106 LED_POW34_A 15 LED_DRIVESIDE4_x LED output select for LED4x. 0x0 R/W
0x0126 LED_POW34_B 0: drive LED on Output LED4A.
0x0146 LED_POW34_C 1: drive LED on Output LED4B.
0x0166 LED_POW34_D [14:8] LED_CURRENT4_x LED current setting for LED4A or LED4B output. Set to 0 to disable. 0x0 R/W
0x0186 LED_POW34_E Output current varies monotonically from 2 mA to 200 mA for values
0x01A6 LED_POW34_F between 0x01 and 0x7F.
0x01C6 LED_POW34_G 7 LED_DRIVESIDE3_x LED output select for LED3x. 0x0 R/W
0x01E6 LED_POW34_H 0: drive LED on Output LED3A.
0x0206 LED_POW34_I 1: drive LED on Output LED3B.
0x0226 LED_POW34_J [6:0] LED_CURRENT3_x LED current setting for LED3A or LED3B output. Set to 0 to disable. 0x0 R/W
0x0246 LED_POW34_K Output current varies monotonically from 2 mA to 200 mA for values
0x0266 LED_POW34_L between 0x01 and 0x7F.
0x0109 LED_PULSE_A [15:8] LED_WIDTH_x LED pulse width in μs. 0x2 R/W
0x0129 LED_PULSE_B [7:0] LED_OFFSET_x LED pulse offset in μs. Set to a minimum of 25 μs (0x19). 0x10 R/W
0x0149 LED_PULSE_C
0x0169 LED_PULSE_D
0x0189 LED_PULSE_E
0x01A9 LED_PULSE_F
0x01C9 LED_PULSE_G
0x01E9 LED_PULSE_H
0x0209 LED_PULSE_I
0x0229 LED_PULSE_J
0x0249 LED_PULSE_K
0x0269 LED_PULSE_L

Rev. A | Page 78 of 82
Data Sheet ADPD4000/ADPD4001
ADC OFFSET REGISTERS
Table 35. Register Details
Addr Name Bits Bit Name Description Reset Access
0x010E ADC_OFF1_A [15:14] Reserved Reserved. 0x0 R
0x012E ADC_OFF1_B [13:0] CH1_ADC_ADJUST_x Adjustment to ADC value. This value is subtracted from the ADC 0x0 R/W
0x014E ADC_OFF1_C value for Channel 1 in Time Slot x.
0x016E ADC_OFF1_D
0x018E ADC_OFF1_E
0x01AE ADC_OFF1_F
0x01CE ADC_OFF1_G
0x01EE ADC_OFF1_H
0x020E ADC_OFF1_I
0x022E ADC_OFF1_J
0x024E ADC_OFF1_K
0x026E ADC_OFF1_L
0x010F ADC_OFF2_A 15 ZERO_ADJUST_x 0x0 R/W
0x012F ADC_OFF2_B 14 Reserved Reserved.
0x014F ADC_OFF2_C [13:0] CH2_ADC_ADJUST_x Adjustment to ADC value. This value is subtracted from the ADC 0x0 R/W
0x016F ADC_OFF2_D value for Channel 2 in Time Slot x.
0x018F ADC_OFF2_E
0x01AF ADC_OFF2_F
0x01CF ADC_OFF2_G
0x01EF ADC_OFF2_H
0x020F ADC_OFF2_I
0x022F ADC_OFF2_J
0x024F ADC_OFF2_K
0x026F ADC_OFF2_L
OUTPUT DATA REGISTERS
Table 36. Register Details
Addr Name Bits Bit Name Description Reset Access
0x002F FIFO_DATA [15:0] FIFO_DATA FIFO data port 0x0 R
0x0030 SIGNAL1_L_A [15:0] SIGNAL1_L_A Signal Channel 1 lower half Time Slot A 0x0 R
0x0031 SIGNAL1_H_A [15:0] SIGNAL1_H_A Signal Channel 1 upper half Time Slot A 0x0 R
0x0032 SIGNAL2_L_A [15:0] SIGNAL2_L_A Signal Channel 2 lower half Time Slot A 0x0 R
0x0033 SIGNAL2_H_A [15:0] SIGNAL2_H_A Signal Channel 2 upper half Time Slot A 0x0 R
0x0034 DARK1_L_A [15:0] DARK1_L_A Dark Channel 1 value lower half Time Slot A 0x0 R
0x0035 DARK1_H_A [15:0] DARK1_H_A Dark Channel 1 value upper half Time Slot A 0x0 R
0x0036 DARK2_L_A [15:0] DARK2_L_A Dark Channel 2 value lower half Time Slot A 0x0 R
0x0037 DARK2_H_A [15:0] DARK2_H_A Dark Channel 2 value upper half Time Slot A 0x0 R
0x0038 SIGNAL1_L_B [15:0] SIGNAL1_L_B Signal Channel 1 lower half Time Slot B 0x0 R
0x0039 SIGNAL1_H_B [15:0] SIGNAL1_H_B Signal Channel 1 upper half Time Slot B 0x0 R
0x003A SIGNAL2_L_B [15:0] SIGNAL2_L_B Signal Channel 2 lower half Time Slot B 0x0 R
0x003B SIGNAL2_H_B [15:0] SIGNAL2_H_B Signal Channel 2 upper half Time Slot B 0x0 R
0x003C DARK1_L_B [15:0] DARK1_L_B Dark Channel 1 value lower half Time Slot B 0x0 R
0x003D DARK1_H_B [15:0] DARK1_H_B Dark Channel 1 value upper half Time Slot B 0x0 R
0x003E DARK2_L_B [15:0] DARK2_L_B Dark Channel 2 value lower half Time Slot B 0x0 R
0x003F DARK2_H_B [15:0] DARK2_H_B Dark Channel 2 value upper half Time Slot B 0x0 R
0x0040 SIGNAL1_L_C [15:0] SIGNAL1_L_C Signal Channel 1 lower half Time Slot C 0x0 R
0x0041 SIGNAL1_H_C [15:0] SIGNAL1_H_C Signal Channel 1 upper half Time Slot C 0x0 R
0x0042 SIGNAL2_L_C [15:0] SIGNAL2_L_C Signal Channel 2 lower half Time Slot C 0x0 R
0x0043 SIGNAL2_H_C [15:0] SIGNAL2_H_C Signal Channel 2 upper half Time Slot C 0x0 R
0x0044 DARK1_L_C [15:0] DARK1_L_C Dark Channel 1 value lower half Time Slot C 0x0 R

Rev. A | Page 79 of 82
ADPD4000/ADPD4001 Data Sheet
Addr Name Bits Bit Name Description Reset Access
0x0045 DARK1_H_C [15:0] DARK1_H_C Dark Channel 1 value upper half Time Slot C 0x0 R
0x0046 DARK2_L_C [15:0] DARK2_L_C Dark Channel 2 value lower half Time Slot C 0x0 R
0x0047 DARK2_H_C [15:0] DARK2_H_C Dark Channel 2 value upper half Time Slot C 0x0 R
0x0048 SIGNAL1_L_D [15:0] SIGNAL1_L_D Signal Channel 1 lower half Time Slot D 0x0 R
0x0049 SIGNAL1_H_D [15:0] SIGNAL1_H_D Signal Channel 1 upper half Time Slot D 0x0 R
0x004A SIGNAL2_L_D [15:0] SIGNAL2_L_D Signal Channel 2 lower half Time Slot D 0x0 R
0x004B SIGNAL2_H_D [15:0] SIGNAL2_H_D Signal Channel 2 upper half Time Slot D 0x0 R
0x004C DARK1_L_D [15:0] DARK1_L_D Dark Channel 1 value lower half Time Slot D 0x0 R
0x004D DARK1_H_D [15:0] DARK1_H_D Dark Channel 1 value upper half Time Slot D 0x0 R
0x004E DARK2_L_D [15:0] DARK2_L_D Dark Channel 2 value lower half Time Slot D 0x0 R
0x004F DARK2_H_D [15:0] DARK2_H_D Dark Channel 2 value upper half Time Slot D 0x0 R
0x0050 SIGNAL1_L_E [15:0] SIGNAL1_L_E Signal Channel 1 lower half Time Slot E 0x0 R
0x0051 SIGNAL1_H_E [15:0] SIGNAL1_H_E Signal Channel 1 upper half Time Slot E 0x0 R
0x0052 SIGNAL2_L_E [15:0] SIGNAL2_L_E Signal Channel 2 lower half Time Slot E 0x0 R
0x0053 SIGNAL2_H_E [15:0] SIGNAL2_H_E Signal Channel 2 upper half Time Slot E 0x0 R
0x0054 DARK1_L_E [15:0] DARK1_L_E Dark Channel 1 value lower half Time Slot E 0x0 R
0x0055 DARK1_H_E [15:0] DARK1_H_E Dark Channel 1 value upper half Time Slot E 0x0 R
0x0056 DARK2_L_E [15:0] DARK2_L_E Dark Channel 2 value lower half Time Slot E 0x0 R
0x0057 DARK2_H_E [15:0] DARK2_H_E Dark Channel 2 value upper half Time Slot E 0x0 R
0x0058 SIGNAL1_L_F [15:0] SIGNAL1_L_F Signal Channel 1 lower half Time Slot F 0x0 R
0x0059 SIGNAL1_H_F [15:0] SIGNAL1_H_F Signal Channel 1 upper half Time Slot F 0x0 R
0x005A SIGNAL2_L_F [15:0] SIGNAL2_L_F Signal Channel 2 lower half Time Slot F 0x0 R
0x005B SIGNAL2_H_F [15:0] SIGNAL2_H_F Signal Channel 2 upper half Time Slot F 0x0 R
0x005C DARK1_L_F [15:0] DARK1_L_F Dark Channel 1 value lower half Time Slot F 0x0 R
0x005D DARK1_H_F [15:0] DARK1_H_F Dark Channel 1 value upper half Time Slot F 0x0 R
0x005E DARK2_L_F [15:0] DARK2_L_F Dark Channel 2 value lower half Time Slot F 0x0 R
0x005F DARK2_H_F [15:0] DARK2_H_F Dark Channel 2 value upper half Time Slot F 0x0 R
0x0060 SIGNAL1_L_G [15:0] SIGNAL1_L_G Signal Channel 1 lower half Time Slot G 0x0 R
0x0061 SIGNAL1_H_G [15:0] SIGNAL1_H_G Signal Channel 1 upper half Time Slot G 0x0 R
0x0062 SIGNAL2_L_G [15:0] SIGNAL2_L_G Signal Channel 2 lower half Time Slot G 0x0 R
0x0063 SIGNAL2_H_G [15:0] SIGNAL2_H_G Signal Channel 2 upper half Time Slot G 0x0 R
0x0064 DARK1_L_G [15:0] DARK1_L_G Dark Channel 1 value lower half Time Slot G 0x0 R
0x0065 DARK1_H_G [15:0] DARK1_H_G Dark Channel 1 value upper half Time Slot G 0x0 R
0x0066 DARK2_L_G [15:0] DARK2_L_G Dark Channel 2 value lower half Time Slot G 0x0 R
0x0067 DARK2_H_G [15:0] DARK2_H_G Dark Channel 2 value upper half Time Slot G 0x0 R
0x0068 SIGNAL1_L_H [15:0] SIGNAL1_L_H Signal Channel 1 lower half Time Slot H 0x0 R
0x0069 SIGNAL1_H_H [15:0] SIGNAL1_H_H Signal Channel 1 upper half Time Slot H 0x0 R
0x006A SIGNAL2_L_H [15:0] SIGNAL2_L_H Signal Channel 2 lower half Time Slot H 0x0 R
0x006B SIGNAL2_H_H [15:0] SIGNAL2_H_H Signal Channel 2 upper half Time Slot H 0x0 R
0x006C DARK1_L_H [15:0] DARK1_L_H Dark Channel 1 value lower half Time Slot H 0x0 R
0x006D DARK1_H_H [15:0] DARK1_H_H Dark Channel 1 value upper half Time Slot H 0x0 R
0x006E DARK2_L_H [15:0] DARK2_L_H Dark Channel 2 value lower half Time Slot H 0x0 R
0x006F DARK2_H_H [15:0] DARK2_H_H Dark Channel 2 value upper half Time Slot H 0x0 R
0x0070 SIGNAL1_L_I [15:0] SIGNAL1_L_I Signal Channel 1 lower half Time Slot I 0x0 R
0x0071 SIGNAL1_H_I [15:0] SIGNAL1_H_I Signal Channel 1 upper half Time Slot I 0x0 R
0x0072 SIGNAL2_L_I [15:0] SIGNAL2_L_I Signal Channel 2 lower half Time Slot I 0x0 R
0x0073 SIGNAL2_H_I [15:0] SIGNAL2_H_I Signal Channel 2 upper half Time Slot I 0x0 R
0x0074 DARK1_L_I [15:0] DARK1_L_I Dark Channel 1 value lower half Time Slot I 0x0 R
0x0075 DARK1_H_I [15:0] DARK1_H_I Dark Channel 1 value upper half Time Slot I 0x0 R
0x0076 DARK2_L_I [15:0] DARK2_L_I Dark Channel 2 value lower half Time Slot I 0x0 R
0x0077 DARK2_H_I [15:0] DARK2_H_I Dark Channel 2 value upper half Time Slot I 0x0 R
0x0078 SIGNAL1_L_J [15:0] SIGNAL1_L_J Signal Channel 1 lower half Time Slot J 0x0 R
0x0079 SIGNAL1_H_J [15:0] SIGNAL1_H_J Signal Channel 1 upper half Time Slot J 0x0 R

Rev. A | Page 80 of 82
Data Sheet ADPD4000/ADPD4001
Addr Name Bits Bit Name Description Reset Access
0x007A SIGNAL2_L_J [15:0] SIGNAL2_L_J Signal Channel 2 lower half Time Slot J 0x0 R
0x007B SIGNAL2_H_J [15:0] SIGNAL2_H_J Signal Channel 2 upper half Time Slot J 0x0 R
0x007C DARK1_L_J [15:0] DARK1_L_J Dark Channel 1 value lower half Time Slot J 0x0 R
0x007D DARK1_H_J [15:0] DARK1_H_J Dark Channel 1 value upper half Time Slot J 0x0 R
0x007E DARK2_L_J [15:0] DARK2_L_J Dark Channel 2 value lower half Time Slot J 0x0 R
0x007F DARK2_H_J [15:0] DARK2_H_J Dark Channel 2 value upper half Time Slot J 0x0 R
0x0080 SIGNAL1_L_K [15:0] SIGNAL1_L_K Signal Channel 1 lower half Time Slot K 0x0 R
0x0081 SIGNAL1_H_K [15:0] SIGNAL1_H_K Signal Channel 1 upper half Time Slot K 0x0 R
0x0082 SIGNAL2_L_K [15:0] SIGNAL2_L_K Signal Channel 2 lower half Time Slot K 0x0 R
0x0083 SIGNAL2_H_K [15:0] SIGNAL2_H_K Signal Channel 2 upper half Time Slot K 0x0 R
0x0084 DARK1_L_K [15:0] DARK1_L_K Dark Channel 1 value lower half Time Slot K 0x0 R
0x0085 DARK1_H_K [15:0] DARK1_H_K Dark Channel 1 value upper half Time Slot K 0x0 R
0x0086 DARK2_L_K [15:0] DARK2_L_K Dark Channel 2 value lower half Time Slot K 0x0 R
0x0087 DARK2_H_K [15:0] DARK2_H_K Dark Channel 2 value upper half Time Slot K 0x0 R
0x0088 SIGNAL1_L_L [15:0] SIGNAL1_L_L Signal Channel 1 lower half Time Slot L 0x0 R
0x0089 SIGNAL1_H_L [15:0] SIGNAL1_H_L Signal Channel 1 upper half Time Slot L 0x0 R
0x008A SIGNAL2_L_L [15:0] SIGNAL2_L_L Signal Channel 2 lower half Time Slot L 0x0 R
0x008B SIGNAL2_H_L [15:0] SIGNAL2_H_L Signal Channel 2 upper half Time Slot L 0x0 R
0x008C DARK1_L_L [15:0] DARK1_L_L Dark Channel 1 value lower half Time Slot L 0x0 R
0x008D DARK1_H_L [15:0] DARK1_H_L Dark Channel 1 value upper half Time Slot L 0x0 R
0x008E DARK2_L_L [15:0] DARK2_L_L Dark Channel 2 value lower half Time Slot L 0x0 R
0x008F DARK2_H_L [15:0] DARK2_H_L Dark Channel 2 value upper half Time Slot L 0x0 R

Rev. A | Page 81 of 82
ADPD4000/ADPD4001 Data Sheet

OUTLINE DIMENSIONS
2.180
2.140
2.100
0.225
BSC 5 4 3 2 1

A
BALL A1 B
IDENTIFIER
C
3.150 2.40
3.110 REF D
3.070 E
0.40
BSC F
0.485
G BSC

TOP VIEW BOTTOM VIEW

(BALL SIDE DOWN) 0.225 (BALL SIDE UP) 0.315
BSC BSC
1.60
0.330 REF
0.560
0.500 0.300
SIDE VIEW
0.440 0.270
COPLANARITY
0.05

SEATING 0.300 0.230

PLANE 0.260 0.200

06-03-2019-B
0.220 0.170
PKG-005711

Figure 46. 35-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-35-2)
Dimensions shown in millimeters
2.180
2.140
2.100
0.225
BSC 5 4 3 2 1

A
BALL A1 B
IDENTIFIER
C
3.150 2.40
3.110 REF D
3.070 E
0.40
BSC F
0.485
G BSC

TOP VIEW BOTTOM VIEW

(BALL SIDE DOWN) 0.225 (BALL SIDE UP) 0.315
BSC BSC
1.60
0.330 REF
0.560
0.500 0.300
SIDE VIEW
0.440 0.270
COPLANARITY
0.05

SEATING 0.300 0.230

PLANE 0.260 0.200
06-03-2019-B

0.220 0.170
PKG-005914

Figure 47. 33-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-33-1)
Dimensions shown in millimeters

ORDERING GUIDE
Model1, 2 Temperature Range Package Description Package Option
ADPD4000BCBZR7 −40°C to +85°C 35-Ball Wafer Level Chip Scale Package [WLCSP] CB-35-2
ADPD4001BCBZR7 −40°C to +85°C 33-Ball Wafer Level Chip Scale Package [WLCSP] CB-33-1
EVAL-ADPD4000Z-PPG Evaluation Board
1
Z = RoHS Compliant Part.
2
EVAL-ADPDUCZ is the microcontroller board, ordered separately, which is required to interface with the EVAL-ADPD4000Z-PPG evaluation board.

©2019 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D17335-0-6/19(A)

Rev. A | Page 82 of 82