EC8691- Microprocessor and Microcontrollers

Important Questions

Unit- I

 Architecture of 8086
 Addressing Modes
 Instruction set & Byte & String Manipulation
 Interrupts ( 7 Marks)

Unit – II

 Maximum mode of 8086 with timing diagrams

 Minimum mode of 8086 with timing diagram
 Coprocessor/ closely and loosely coupled
 System design- Interfacing RAM and ROM problem discussed in class ( will come in Part C)

Unit- III

Set A Set B
8255-PPI 8279- Keyboard / display interface
8251- Serial Interface 8259- Interrupt controller
A/D & D/A 8237/8257- DMA Controller
8253- Timer

Choose any one Set (All Questions) to study

 Traffic Light controller ( Part C)

 Alarm Controller

Unit-IV

 Architecture of 8051 microcontroller

 Addressing mode (7 marks)
 Instruction set (7 Marks)
 Special function registers
 Ports

Unit V

 Programming timers & serial port

 LCD Interface (7 marks)
 Stepper motor Interface ( Will come in Part C)
 ADC and DAC interface

Assembly Language program:

 Arithmetic operations ( Addition, Subtraction, Multiplication and Division)

 Logical operations ( AND, OR, NOT, EX-OR)
 Largest & Smallest
 Ascending and Descending
 Sum of N natural numbers
 Average of N numbers.

General Instructions for Exam

 Nagoor Kani e-Book is available in teams. Please download and keep. It has all the five units and will be
very useful for the exam.
 Microprocessor paper always will be lengthy and time consuming. Please maintain time.
 Strictly write to the marks. Don’t waste too much time in writing Architecture and addressing mode questions
(Normally students waste time in these questions writing very elaborately). 5 marks given to Diagram, only
remaining 8 marks for the theory you write, so please remember that. Same applicable to Addressing mode 8
addressing mode each 2 marks exceeds 13 marks
 Draw Interrupt vector Table if you are writing Interrupts of 8086
 For Min and Max mode of 8086, along with the diagram any one Timing diagram please draw even though it’s
not asked.
 Practise the Memory interfacing problem (16KB EPROM and 8 KB RAM) which was taught in the class. It will
not available in some books. It’s a very important part C question which you can easily score.
 For all Interfacing IC’s neatly draw the architecture, write some features. You must draw the control word
compulsorily for the interfacing IC even if asked or not. 8279 & 8259 has multiple control word (8279- Keyboard
/display mode) , draw only the important ones.
 For traffic light controller please follow my lecture. You must generate sequence for at least four green signals.
Diagram and program is must
 8051- Microcontroller, follow the same instructions given for architecture, addressing mode and Instruction set
of 8086. For ports multiple functions, draw the diagram with flip flops and explain each ports.
 Various Interfaces of 8051 are available in all books. Stepper motor interface – you need to show / explain how
the 4 Hexadecimal count (09, 06, 03, 0C) is generated.

*****All the best****

 Unit I

Architecture of 8086

Features

 16-bit microprocessors

 Data bus width of 8086 is 16 bit and 8 bit for 8088

 1 MB main memory

 400 nanoseconds clock cycle time

 6 byte instruction cache for 8086 and 4 byte for 8088

 Other improvements included more registers and additional instructions

The 8086 is mainly divided into mainly two blocks

1. Execution Unit (EU) 2.Bus interface Unit (BIU)
Dividing the work between these two will speedup the processing
1) EXECUTION UNIT( EU)

The Execution unit tells the BIU where to fetch instructions or data
from
• decodes instructions and
• Executes instructions The Execution unit contains:
1) Control circuitry
2) ALU
3) FLAGS
4) General purpose Registers
5) Pointer and Index Registers

Control Circuitry:
• It directs internal operations.
• A decoder in the EU translates instructions fetched from memory Into series of
actions which the EU carries out

Arithmetic Logic Unit:

16 bit ALU
Used to carry the operations such as
 ADD
 SUBTRACT
 XOR
 INCREMENT
 DECREMENT
 COMPLEMENT
 SHIFT BINARY NUMBERS
FLAG REGISTERS:
 A flag is a flip flop that indicates some condition produced by execution of an instruction or
controls certain operation of the EU.
 It is 16 bit
 It has nine active flags Divided into two types
1. Conditional flags

2. Control flags
Conditional Flags

Carry Flag (CY): This flag indicates an overflow condition for unsigned integer arithmetic. It is also
used in multiple-precision arithmetic.

Auxiliary Flag (AC): If an operation performed in ALU generates a carry/barrow from lower nibble
(i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AC flag is set i.e. carry given by D3 bit to D4 is AC
flag. This is not a general-purpose flag, it is used internally by the Processor to perform Binary to
BCD conversion.

Parity Flag (PF):This flag is used to indicate the parity of result. If lower order 8-bits of the result
contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity flag is reset.
Zero Flag (ZF):It is set; if the result of arithmetic or logical operation is zero else it is reset.

Sign Flag (SF):In sign magnitude format the sign of number is indicated by MSB bit. If the result of
operation is negative, sign flag is set.

Control Flags

Control flags are set or reset deliberately to control the operations of the execution unit. Control flags
are as follows:

Trap Flag (TF): It is used for single step control. It allows user to execute one instruction of a
program at a time for debugging. When trap flag is set, program can be run in single step mode.

Interrupt Flag (IF):It is an interrupt enable/disable flag. If it is set, the maskable interrupt of 8086 is
enabled and if it is reset, the interrupt is disabled. It can be set by executing instruction sit and can be
cleared by executing CLI instruction.

Direction Flag (DF):It is used in string operation. If it is set, string bytes are accessed from higher
memory address to lower memory address. When it is reset, the string bytes are accessed from
lower memory address to higher memory address.

General Purpose Registers:

It was designed in such a way that many programs written could easily be translated to run on
8086.The advantage of using internal registers for the temporary storage of data is that since data
already in the EU ., it can be accessed much more quickly than it could be accessed from external
memory.
General Purpose Registers
The registers AX, BX, CX, and DX are the general 16-bit registers.
AX Register: Accumulator register consists of two 8-bit registers AL and AH, which can be combined
together and used as a 16- bit register AX. AL in this case contains the low-order byte of the word,
and AH contains the high- order byte. Accumulator can be used for I/O operations, rotate and string
manipulation.
BX Register: This register is mainly used as a base register. It holds the starting base location of a
memory region within a data segment. It is used as offset storage for forming physical address in
case of certain addressing mode.
 CX Register: It is used as default counter or count register in case of string and loop
instructions.
DX Register: Data register can be used as a port number in I/O operations and implicit
operand or destination in case of few instructions. In integer 32-bit multiply and divide
instruction the DX register contains high-order word of the initial or resulting number.
2) BUS INTERFACE UNIT (BIU)
The BIU sends out
 Addresses
 Fetches instructions from memory
 Read data from ports and memory Or
The BIU handles all transfer of data and addresses on the buses for the Execution Unit
The Bus interface unit contains
1) Instruction Queue
2) Instruction pointer
3) Segment registers
4) Address Generator
Instruction Queue:
BIU gets upto 6 bytes of next instructions and stores them in the instruction queue. When EU
executes instructions and is ready for its next instruction, then it simply reads the instruction
from this instruction queue resulting in increased execution speed. Fetching the next
instruction while the current instruction executes is called pipelining.( based on FIFO) .This is
much faster than sending out an addresses to the system memory and waiting for memory to
send back the next instruction byte or bytes .Here the Queue will be dumped and then
reloaded from the new Address.
Segment Register:
The 8086 20 bit addresses So it can address upto 220 in memory ( 1 Mbyte) but at any instant
it can address upto 4 64 KB segments. This four segments holds the upper 16 bits of the
starting address of four memory segments that the 8086 is working with it at particular time
.The BIU always inserts zeros for the lowest 4 bits of the 20 bit starting address
Example : If the code segment register contains 348AH then the code segment starts at
348A0H .In other words a 64Kbyte segment can be located anywhere within 1MByte address
Space but the segment will always starts at an address with zeros in the lowest 4 bits

Four segment registers

 Code segment register

 Stack segment register
 Data segment register
 Extra segment register
Stack: is a section of memory set aside to store addresses and data while subprogram executes is
often called segment base . The stack segment register always holds the upper 16 bit starting
address of program stack.
The extra segment register and data segment register is used to hold the upper 16 bit starting
addresses of two memory segments that are used for data .
Instruction Pointer holds the 16 bit address or offset of the next code byte within the code segment.
The value contained in the Instruction Pointer called as Offset because the value must be added to
the segment base address in CS to produce the required 20 bit address.

CS register contains the Upper 16 bit of the starting address of the code segment in the 1 Mbyte
address range the instruction pointer contains a 16 bit offset which tells wherein that 64 Kbyte code
segment the next instruction byte has to be fetched from.
Stack Register and Stack Pointer:
Stack: is a section of memory set aside to store addresses and data while subprogram executes is
often called segment base . The stack segment register always holds the upper 16 bit starting
address of program stack. The Stack pointer (SP) holds the 16 bit offset from the starting of the
segment to the memory location where a word was most recently stored
.The memory location where the word is stored is called as top of the stack

Pointer and Index registers:

In addition to stack pointer register EU has Base pointer Register (BP)
Source Pointer Register(SP) Destination Pointer Register(DP)

These three registers are used to store temporary storage of data like general purpose registers
.They hold the 16 bit offset data of the data word in one of the segment

Two Index registers, Source Index and Destination Index

 Addressing Modes

The different ways in which a source operand is denoted in an instruction are known as
addressing mode the addressing modes for sequential control flow instructions are

1. Immediate Addressing Mode

2. Direct Addressing mode
3. Register Addressing mode
4. Register Indirect Addressing mode
5. Indexed Addressing Mode
 6. Register Relative addressing mode
7. Based indexed addressing mode
8. Relative based indexed Addressing mode

IMMEDIATE ADDRESSING MODE

The addressing mode in which the data operand is a part of the instruction itself is known as
immediate addressing mode.

Example

MOV DL, 08H

The 8-bit data (08H) given in the instruction is moved to DL (DL)

08H
MOV AX, 0A9FH

The 16-bit data (0A9FH) given in the instruction is moved to AX register (AX) 
0A9FH

DIRECT ADDRESSING MODE

The addressing mode in which the effective address of the memory location at which the data
operand is stored is given in the instruction. The effective address (Offset) is just a 16-bit number
written directly in the instruction.
Example:MOV BX, [1354H] MOV
BL, [0400H]

The square brackets around the 1354H denote the contents of the memory location. When
executed, this instruction will copy the contents of the memory location into BX register. This
addressing mode is called direct because the displacement of the operand from the segment
base is specified directly in the instruction.

REGISTER ADDRESSING MODE

The instruction will specify the name of the register which holds the data to be operated by the instruction. All
registers except IP may be used in this mode

Example:

MOV CL, DH
The content of 8-bit register DH is moved to another 8-bit register CL (CL)
(DH)

REGISTER INDIRECT ADDRESSING MODE

This addressing mode allows data to be addressed at any memory location through an offset
address held in any of the following registers: BP, BX, DI & SI.

Example

MOV AX, [BX]; suppose the register BX contains 4895H, then the contents
; 4895H are moved to AX
ADD CX, {BX}

INDEXED ADDRESSING MODE

In this addressing mode, the operands offset address is found by adding the contents of SI or DI
register and 8-bit/16-bit displacements. DS and ES are the default segments for index registers
SI and DI respectively. This is the special case of the of register indirect addressing mode.

Example

MOV BX, [SI+16], ADD AL, [DI+16]

REGISTER RELATIVE ADDRESSING MODE

In register relative Addressing, BX, BP, SI and DI is used to hold the base value for
effective address and a signed 8-bit or unsigned 16-bit displacement will be specified in the
instruction. In case of 8-bit displacement, it is sign extended to 16-bit before adding to the base
value. When BX holds the base value of EA, 20-bit physical address is calculated from BX and
DS.When BP holds the base value of EA, BP and SS is used.
Example:

MOV AX, [BX + 08H] MOV AX, 08H [BX]

BASED INDEXED ADDRESSING MODE

In this addressing mode, the offset address of the operand is computed by summing the base
register to the contents of an Index register. The default segment registers may be ES or DS
Example:

MOV DX, [BX + SI] MOV DX, [BX][SI]

RELATIVE BASED INDEXED ADDRESSING MODE

In this addressing mode, the operands offset is computed by adding the base register contents.
An Index registers contents and 8 or 16-bit displacement.
Example

MOV AX, [BX+DI+08]

ADD CX, [BX+SI+16]

CONTROL TRANSFER INSTRUCTIONS ADDRESSING MODES /BRANCH ADDRESSING

MODE

The control transfer instructions transfer control to some predefined address or the address
somehow specified in the instruction after their execution
Examples : INT , CALL ,RET and JUMP instructions
The control transfer instruction the addressing modes depend upon whether destination location
is within the same segment or a different one .It also depends on the method of passing the
destination address to the processor
Basically there are two methods for passing control transfer instructions
1. Intersegment addressing mode
2. Intrasegment addressing mode
INTRASEGMENT ADDRESSING MODE

If the destination location is within the same segment the mode is called intrasegment addressing
mode
There are two types
1. Intrasegement direct mode
2. Intrasegment indirect mode
INTRASEGMENT DIRECT MODE:

In this mode the address to which the control is to be transferred lies within the segment in which
the control transfer instruction lies and appears directly in the instruction as an immediate
displacement value .The displacement is computed relative to the content of the instruction
pointer IP.
JMP SHORT LABEL;
is a control transfer instruction following intra segment direct mode. Here, SHORT LABEL
represents a signed displacement.
INTRASEGMENT INDIRECT MODE :

In this mode the displacement to which the control is to be transferred is in the same segment in
which the control transfer instruction lies but it is passed to the instruction indirectly Here the
branch address is found as the content of a register or a memory location .
Example
JMP [A

INTERSEGMENT ADDRESSING MODE

If the destination location is in the different segment the mode is called intersegment addressing
mode
There are two types
1. Intersegment direct mode
2. Intersegment indirect mode
INTERSEGMENT DIRECT MODE:

In this mode the address to which the control is to be transferred is in a different segment this
addressing mode provides a means of branching from one code segment to another code
segment. Here the CS and IP of the destination address are specified directly in the instruction.
Example

JMP 2000H: 3000H;

INTERSEGMENT INDIRECT MODE :

In this the address to which the control is to be transferred lies in a different segment and it is
passed to the instruction indirectly .Content of memory block containing four bytes IP(LSB)
,IP(MSB),CS(LSB) and CS(MSB) sequentially The starting address of the memory block may be
referred using any of the addressing mode except immediate mode .
Example

JMP [5000H];
INSTRUCTION SET OF 8086

The 8086 microprocessor supports 8 types of instructions −

 Data Transfer Instructions

 Arithmetic Instructions
 logical Instructions
 String Instructions
 Program Execution Transfer Instructions (Branch & Loop Instructions)
 Processor Control Instructions
 Iteration Control Instructions
 Interrupt Instructions

1. DATA TRANSFERINSTRUCTIONS
These instructions are used to transfer the data from the source operand to the
destination operand. Following are the list of instructions under this group −

INSTRUCTION TO TRANSFER A WORD

 MOV − Used to copy the byte or word from the provided source to the provided
destination.
 PPUSH − Used to put a word at the top of the stack.
 POP − Used to get a word from the top of the stack to the provided location.
 PUSHA − Used to put all the registers into the stack.
 POPA − Used to get words from the stack to all registers.
  XCHG − Used to exchange the data from two locations.
 XLAT − Used to translate a byte in AL using a table in the memory.

INSTRUCTIONS FOR INPUT AND OUTPUT PORT TRANSFER

 IN − Used to read a byte or word from the provided port to the accumulator.
 OUT − Used to send out a byte or word from the accumulator to the provided
port.

INSTRUCTIONS TO TRANSFER THE ADDRESS

 LEA − Used to load the address of operand into the provided register.
 LDS − Used to load DS register and other provided register from the memory
 LES − Used to load ES register and other provided register from the memory.

INSTRUCTIONS TO TRANSFER FLAG REGISTERS

 LAHF − Used to load AH with the low byte of the flag register.
 SAHF − Used to store AH register to low byte of the flag register.
 PUSHF − Used to copy the flag register at the top of the stack.
 POPF − Used to copy a word at the top of the stack to the flag register.

2. ARITHMETIC INSTRUCTIONS
These instructions are used to perform arithmetic operations like addition,
subtraction, multiplication, division, etc.
Following is the list of instructions under this group −

INSTRUCTIONS TO PERFORM ADDITION

 ADD − Used to add the provided byte to byte/word to word.

 ADC − Used to add with carry.
 INC − Used to increment the provided byte/word by 1.
 AAA − Used to adjust ASCII after addition.
 DAA − Used to adjust the decimal after the addition/subtraction operation.

INSTRUCTIONS TO PERFORM SUBTRACTION

 SUB − Used to subtract the byte from byte/word from word.

 SBB − Used to perform subtraction with borrow.
 DEC − Used to decrement the provided byte/word by 1.
 NPG − Used to negate each bit of the provided byte/word and add 1/2’s
complement.
 CMP − Used to compare 2 provided byte/word.
  AAS − Used to adjust ASCII codes after subtraction.
 DAS − Used to adjust decimal after subtraction.
INSTRUCTION TO PERFORM MULTIPLICATION

 MUL − Used to multiply unsigned byte by byte/word by word.

 IMUL − Used to multiply signed byte by byte/word by word.
 AAM − Used to adjust ASCII codes after multiplication.

INSTRUCTIONS TO PERFORM DIVISION

 DIV − Used to divide the unsigned word by byte or unsigned double word by
word.
 IDIV − Used to divide the signed word by byte or signed double word by word.
 AAD − Used to adjust ASCII codes after division.
 CBW − Used to fill the upper byte of the word with the copies of sign bit of the
lower byte.
 CWD − Used to fill the upper word of the double word with the sign bit of
the lower word.

3. LOGICAL INSTRUCTIONS
These instructions are used to perform operations where data bits are involved,
i.e. operations like logical, shift, etc.
Following is the list of instructions under this group −

INSTRUCTIONS TO PERFORM LOGICAL OPERATION

 NOT − Used to invert each bit of a byte or word.

 AND − Used for adding each bit in a byte/word with the corresponding bit in
another byte/word.
 OR − Used to multiply each bit in a byte/word with the corresponding bit in
another byte/word.
 XOR − Used to perform Exclusive-OR operation over each bit in a
byte/word with the corresponding bit in another byte/word.
 TEST − Used to add operands to update flags, without affecting operands.

INSTRUCTIONS TO PERFORM SHIFT OPERATIONS

 SHL/SAL − Used to shift bits of a byte/word towards left and put zero(S) in LSBs.
 SHR − Used to shift bits of a byte/word towards the right and put zero(S) in
MSBs.
 SAR − Used to shift bits of a byte/word towards the right and copy the old
MSB into the new MSB.

INSTRUCTIONS TO PERFORM ROTATE OPERATIONS

 ROL − Used to rotate bits of byte/word towards the left, i.e. MSB to LSB and to
 Carry Flag [CF].

 ROR − Used to rotate bits of byte/word towards the right, i.e. LSB to MSB and to
Carry Flag [CF].
 RCR − Used to rotate bits of byte/word towards the right, i.e. LSB to CF and CF to
MSB.
 RCL − Used to rotate bits of byte/word towards the left, i.e. MSB to CF and CF to
LSB.

4. STRING INSTRUCTIONS
String is a group of bytes/words and their memory is always allocated in a
sequential order.
Following is the list of instructions under this group −
 REP − Used to repeat the given instruction till CX ≠ 0.
 REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.
 REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF
= 1.
 MOVS/MOVSB/MOVSW − Used to move the byte/word from one string to
another.
 COMS/COMPSB/COMPSW − Used to compare two string bytes/words.
 INS/INSB/INSW − Used as an input string/byte/word from the I/O port to
the provided memory location.
 OUTS/OUTSB/OUTSW − Used as an output string/byte/word from the provided
memory location to the I/O port.
 SCAS/SCASB/SCASW − Used to scan a string and compare its byte with a byte in
AL or string word with a word in AX.
 LODS/LODSB/LODSW − Used to store the string byte into AL or string word into
AX.

5. PROGRAM EXECUTION TRANSFER INSTRUCTIONS (BRANCH AND LOOP

INSTRUCTIONS) These instructions are used to transfer/branch the instructions
during an execution. It includes the following instructions −
Instructions to transfer the instruction during an execution without any condition −
 CALL − Used to call a procedure and save their return address to the stack.
 RET − Used to return from the procedure to the main program.
 JMP − Used to jump to the provided address to proceed to the next
instruction. Instructions to transfer the instruction during an execution with some
conditions −
 JA/JNBE − Used to jump if above/not below/equal instruction satisfies.
 JAE/JNB − Used to jump if above/not below instruction satisfies.
 JBE/JNA − Used to jump if below/equal/ not above instruction satisfies.
  JC − Used to jump if carry flag CF = 1
 JE/JZ − Used to jump if equal/zero flag ZF = 1
 JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.
 JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.
 JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.
 JLE/JNG − Used to jump if less than/equal/if not greater than instruction
satisfies.
 JNC − Used to jump if no carry flag (CF = 0)
 JNE/JNZ − Used to jump if not equal/zero flag ZF = 0
 JNO − Used to jump if no overflow flag OF = 0
 JNP/JPO − Used to jump if not parity/parity odd PF = 0
 JNS − Used to jump if not sign SF = 0
 JO − Used to jump if overflow flag OF = 1
 JP/JPE − Used to jump if parity/parity even PF = 1
 JS − Used to jump if sign flag SF = 1

6. PROCESSOR CONTROLINSTRUCTIONS
These instructions are used to control the processor action by setting/resetting the
flag values.
Following are the instructions under this group −
 STC − Used to set carry flag CF to 1
 CLC − Used to clear/reset carry flag CF to 0
 CMC − Used to put complement at the state of carry flag CF.
 STD − Used to set the direction flag DF to 1
 CLD − Used to clear/reset the direction flag DF to 0
 STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.
 CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.

7. ITERATION CONTROL INSTRUCTIONS

These instructions are used to execute the given instructions for number of times.
Following is the list of instructions under this group −
 LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX
=0
 LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1
& CX = 0
 LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 &
CX = 0
 JCXZ − Used to jump to the provided address if CX = 0
8. INTERRUPT INSTRUCTIONS
These instructions are used to call the interrupt during program execution.
 INT − Used to interrupt the program during execution and calling service
specified.
 INTO − Used to interrupt the program during execution if OF = 1
 IRET − Used to return from interrupt service to the main program
 Unit II
 Minimum mode of 8086 with timing diagram

Minimum Mode 8086 System and Timings

In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by strapping its
MN/MX* pin to logic1. In this mode, all the control signals are given out by the microprocessor chip itself.
There is a single microprocessor in the minimum mode system. The remaining components in the system
are latches, transreceivers, clock generator, memory and I/O devices. Some type of chip selection logic
may be required for selecting memory or I/O devices, depending upon the address map of the system.

Latches:

The latches are generally buffered output D-type flip-flops, like, 74LS373 or 8282. They are used for
separating the valid address from the multiplexed address/data signals and are controlled by the ALE
signal generated by 8086.

Transreceivers

Transreceivers are the bidirectional buffers and some times they are called as data amplifiers. They are
required to separate the valid data from the time multiplexed address/data signal. They are controlled by
two signals, namely, DEN* and DT/R*. The DEN* signal indicates that the valid data is available on the
data bus, while DT/R indicates the direction of data, i.e. from or to the processor.

Memory:

The system contains memory for the monitor and users program storage. Usually, EPROMS are used for
monitor storage, while RAMs for users program storage.
IO Devices:

A system may contain I/O devices for communication with the processor as well as some special purpose
I/O devices.

Clock Generator:

The clock generator generates the clock from the crystal oscillator and then shapes it and divides to make
it more precise so that it can be used as an accurate timing reference for the system. The clock generator
also synchronizes some external signals with the system clock.

The general system organization is shown in above fig .Since it has 20 address lines and 16 data lines,
the 8086 CPU requires three octal address latches and two octal data buffers for the complete address
and data separation.

The working of the minimum mode configuration system can be better described in terms of the timing
diagrams rather than qualitatively describing the operations. The opcode fetch and read cycles are
similar. Hence the timing diagram can be categorized in two parts.

1) Timing diagram for read cycle

2) Timing diagram for write cycle.

Timing diagram for Read cycle :

The read cycle begins in T1 with the assertion of the address latch enable (ALE) signal and also M/IO*
signal. During the negative going edge of this signal, the valid address is latched on the local bus. The
BHE* and A0 signals address low, high or both bytes. From Tl to T4, the M/IO* signal indicates a
memory or I/O operation. At T2 the address is removed from the local bus and is sent to the output. The
bus is then tristated. The read (RD*) control signal is also activated in T2
  Maximum mode of 8086 with timing diagrams

In the maximum mode, the 8086 is operated by strapping the MN/MX* pin to ground.

In this mode, the processor derives the status signals S2*, S1* and S0*. Another chip called bus
controller derives the control signals using this status information. In the maximum mode, there may be
more than one microprocessor in the system configuration. The other components in the system are the
same as in the minimum mode system. The general system organization is as shown

The basic functions of the bus controller chip IC8288, is to derive control signals like RD* and WR* (for
memory and I/O devices), DEN*, DT/R*, ALE, etc. using the information made available by the processor
on the status lines.

The bus controller chip has input lines S2*, S1* and S0* and CLK. These inputs to 8288 are driven by the
CPU. It derives the outputs ALE, DEN*, DT/R*, MWTC*, AMWC*, IORC*, IOWC* and AIOWC*.

The AEN*, IOB and CEN pins are specially useful for multiprocessor systems. AEN* and IOB are
generally grounded. CEN pin is usually tied to +5V

INTA* pin is used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting
device.IORC*, IOWC* are I/O read command and I/O write command signals respectively. These signals
enable an IO interface to read or write the data from or to the addressed port. The MRDC*, MWTC* are
memory read command and memory write command signals respectively and may be used as memory
read and write signals. All these command signals instruct the memory to accept or send data from or to
the bus. For both of these write command signals, the advanced signals namely AIOWC* and AMWTC*
are available. They also serve the same purpose, but are activated one clock cycle earlier than the
IOWC* and MWTC* signals, respectively.

The maximum mode system timing diagrams are also divided in two portions as read (input) and write
(output) timing diagrams. The address/data and address/status timings are similar to the minimum mode.
ALE is asserted in T1, just like minimum mode. The only difference lies in the status signals used and the
available control and advanced command signals.

 Multi Processor Configuration or ( Coprocessor/ closely and loosely coupled)

Multiprocessor means a multiple set of processors that executes instructions simultaneously. There are
three basic multiprocessor configurations.

Coprocessor configuration

Closely coupled configuration

Loosely coupled configuration

Coprocessor Configuration

A Coprocessor is a specially designed circuit on microprocessor chip which can perform the same task
very quickly, which the microprocessor performs. It reduces the work load of the main processor. The
coprocessor shares the same memory, IO system, bus, control logic and clock generator. The
coprocessor handles specialized tasks like mathematical calculations, graphical display on screen, etc.

The 8086 and 8088 can perform most of the operations but their instruction set is not able to perform
complex mathematical operations, so in these cases the microprocessor requires the math coprocessor
like Intel 8087 math coprocessor, which can easily perform these operations very quickly.

 The coprocessor and the processor is connected via TEST, RQ-/GT- and QS0 & QS1 signals.

 The TEST signal is connected to BUSY pin of coprocessor and the remaining 3 pins are
connected to the coprocessor’s 3 pins of the same name.

 TEST signal takes care of the coprocessor’s activity, i.e. the coprocessor is busy or idle.

 The RT-/GT-is used for bus arbitration.

 The coprocessor uses QS0 & QS1 to track the status of the queue of the host processor.

Closely Coupled Configuration

Closely coupled configuration is similar to the coprocessor configuration, i.e. both share the same
memory, I/O system bus, control logic, and control generator with the host processor. However, the
coprocessor and the host processor fetches and executes their own instructions. The system bus is
controlled by the coprocessor and the host processor independently.
  Communication between the host and the independent processor is done through memory space.

 None of the instructions are used for communication, like WAIT, ESC, etc.

 The host processor manages the memory and wakes up the independent processor by sending
commands to one of its ports.

 Then the independent processor accesses the memory to execute the task.

 After completion of the task, it sends an acknowledgement to the host processor by using the
status signal or an interrupt request.

Loosely Coupled Configuration

Loosely coupled configuration consists of the number of modules of the microprocessor based systems,
which are connected through a common system bus. Each module consists of their own clock generator,
memory, I/O devices and are connected through a local bus.
  Having more than one processor results in increased efficiency.
 Each of the processors have their own local bus to access the local memory/I/O devices. This
makes it easy to achieve parallel processing.
 The system structure is flexible, i.e. the failure of one module doesn’t affect the whole system
failure; faulty module can be replaced later.

BASIS OF
LOOSELY COUPLED SYSTEMS CLOSELY COUPLED SYSTEMS
COMPARISON
Loosely coupled systems have a CLOSELY coupled systems have a shared
Memory Concept
distributed memory concept. memory concept.
The interconnections in a CLOSELY
coupled system are Processor-memory
The interconnection network in a
interconnection network (PMIN), I/O-
Interconnection loosely coupled system is Message
Processor interconnection network (IOPIN)
Transfer System (MTS).
and the interrupt-signal interconnection
network (ISIN).
Data rate of the loosely coupled The data rate of CLOSELY coupled system
Data Rate
system is low. is high.
They are widely used in distributed They are widely used in parallel processing
Application
computing systems. systems.
Throughput in this type of systems is
Throughput Throughput in this type of systems is high.
low.
Power Power consumption is high. Power consumption is low.
Operating It operates on multiple operating
It operates on single operating system.
System systems.
Delay It has high delay. It has low delay.
Unit-IV

 Architecture of 8051 microcontroller

 Addressing mode (7 marks)
 Instruction set (7 Marks)
 Special function registers
 Ports

1. Architecture of 8051 Microcontroller

The 8051 architecture consists of these specific features:

 Eight-bit CPU with registers A (the accumulator) and B

 Sixteen-bit program counter (PC) and data pointer (DPTR)
 Eight-bit program status word (PSW)
 Eight-bit stack pointer (SP)
 Internal ROM or EPROM (8751) of 0 (8031) to 4K (8051)
 Internal RAM of 128 bytes:
 Four register banks, each containing eight registers
 Sixteen bytes, which may be addressed at the bit level
 Eighty bytes of general-purpose data memory
 Thirty-two input/output pins arranged as four 8-bit ports: PO-P3
 Two 16-bit timer/counters: TO and Tl
 Full duplex serial data receiver/transmitter: SBUF
 Control registers: TCON, TMOD, SCON, PCON, IP, and IE
 Two external and three internal interrupt sources
 Oscillator and clock circuits

The Block diagram consists of

 Program counter,
 ALU
 Working registers
 Clock circuits.
 Internal ROM and RAM
 I/O ports with programmable pins
 Timers and counters
 Serial data communication
A and B Registers
The A and B registers are called CPU registers. They are used to hold the data for most of the
CPU (ALU) operations. The size of A and B registers are 8-bit and they are mapped as on-chip data
memory with byte address E0H and F0H respectively. These registers are also bit-addressable.
In most of the ALU operations, the result is stored in the A-register and so, it is also known
as the accumulator.

The Program Counter

The 8051 has a 16 bit program counter. It is used to hold the address of the memory location from which
the next instruction is to be fetched.

Data Pointer (DPTR)

The data pointer is a 16-bit register used to hold the 16-bit address of data memory. The 16-bit data
pointer can also be used as two numbers of 8-bit data pointers, namely, DPH and DPL. The 8-bit data
pointers are used for accessing internal RAM and SFR. The 16-bit data pointer is used for accessing
external data memory. The 8-bit data pointer DPH and DPL are mapped as internal memory with byte
address 83H and 82H respectively. The contents of the data pointer are programmable using instructions.

Special Function Register (SFR)

The 8031/8051 is provided with 21 special function registers and they are used for selecting
various programmable features of the microcontroller. The special functions of most of the SFR
are distinguishable. Each SFR has an internal one-byte address assigned to it. Some of the registers
are both byte and bit-addressable.

I/O Ports

The 8051 has four numbers of 8-bit ports, namely, port-0, port-1, port-2 and port-3. Each
port has a latch and driver (or buffer). When external memory is employed the port-0 lines will
function as multiplexed low byte address/data lines and port-2 lines will function as high byte
address lines. Also, the port pins P3.7 and P3.6 are used to output read and write control signals
respectively. In fact, each pin of port-3 has an alternate function

Program Status Word (PSW)

The program status word store the status of the result of the ALU operations and some of the
status of the processor by means of a 1-bit status called flags. The PSW is also known as a flag
register. The flags are useful for the programmer to test the condition of the result and make decisions.
The format of the PSW of an 8031/8051 microcontroller
PSW consists of four math flags and two register bank select bits. The math flags are carry, auxiliary
carry, overflow and parity flags. These flags are altered after arithmetic and logical operations
depending on the result. The carry flag is set when the result has a carry. When there is a carry
from the lower nibble to the upper nibble, the auxiliary carry is set. When the result has even parity,
the parity flag is set. In certain mathematical operations if the size of the result exceeds the size of
the destination register then the overflow flag is set.
 2.Addressing mode of 8051

In 8051 There are six types of addressing modes.

 Immediate AddressingMode
 Register AddressingMode
 Direct AddressingMode
 Register IndirectAddressing Mode
 Indexed AddressingMode
 Implied AddressingMode
Immediate addressing mode
In this Immediate Addressing Mode, the operand is the part of the instruction. The data is
provided immediately after the opcode.
These are some examples of Immediate Addressing Mode.
MOVA, #0AFH;
MOVR3, #45H;
MOVDPTR, #FE00H;
Register addressing mode
In the register addressing mode the source or destination operand is present in a register (R0
to R7). These are some examples of Register Addressing Mode.
MOVA, R5;
MOVR0, A;
In 8051, there is no instruction like MOVR5, R7.
Direct Addressing Mode
In the Direct Addressing Mode, the source or destination (operand) address is specified by
using 8-bit data in the instruction. Only the internal data memory can be used in this mode. Here
some of the examples of direct Addressing Mode.
MOV80H, R6;
MOVR2, 45H;
MOVR0, 05H;
The first instruction will send the content of registerR6 to port P0 (Address of Port 0 is 80H). The
second one is forgetting content from 45H to R2. The third one is used to get data from Register
R5 (When register bank RB0 is selected) to register R5.
Register indirect addressing Mode
In this mode, the operand source or destination address is given in the register. By using
register indirect addressing mode, the internal or external addresses can be accessed. The R0
and R1 are used for 8-bit addresses, and DPTR is used for 16-bit addresses, no other registers
can be used for addressing purposes. Let us see some examples of this mode.
MOV0E5H, @R0;
MOV@R1, 80H
In the instructions, the @ symbol is used for register indirect addressing. In the first instruction, it
is showing that theR0 register is used. If the content of R0 is 40H, then that instruction will take
the data which is located at location 40H of the internal RAM. In the second one, if the content
of R1 is 30H, then it indicates that the content of port P0 will be stored at location 30H in the
internal RAM.
MOVXA, @R1;
MOV@DPTR, A;
In these two instructions, the X in MOVX indicates the external data memory. The external data
memory can only be accessed in register indirect mode. In the first instruction if the R0 is
holding 40H, then A will get the content of external RAM location40H. And in the second one,
the content of A is overwritten in the location pointed by DPTR.
Indexed addressing mode
In the indexed addressing mode, the source memory can only be accessed from program
memory only. The destination operand is always the register A. These are some examples of
Indexed addressing mode.
MOVCA, @A+PC;
MOVCA, @A+DPTR;
The C in MOVC instruction refers to code byte. For the first instruction, let us consider A holds
30H. And the PC value is1125H. The contents of program memory location 1155H (30H +
1125H) are moved to register A.
Implied Addressing Mode
In the implied addressing mode, there will be a single operand. These types of instruction can
work on specific registers only. These types of instructions are also known as register specific
instruction. Here are some examples of Implied Addressing Mode.
RLA;
SWAPA;
These are 1- byte instruction. The first one is used to rotate the A register content to the Left.
The second one is used to swap the nibbles in A.

3.Instruction Set of 8051

The instruction set of microcontroller 8051 can be divided into the following groups:

 Data transfer instructions.

 Arithmetic instructions.
 Logical Instructions (Boolean).
 Program Control Instructions (jumps).
 Bit manipulation instructions.

DATA ARITHMETIC LOGICAL BIT PROGRAM

TRANSFER MANIPULATION CONTROL
MOV ADD ANL CLR LJMP
MOVC ADDC ORL SETB AJMP
MOVX SUBB XRL MOV SJMP
PUSH INC CLR JC JZ
POP DEC CPL JNC JNZ
XCH MUL RL JB CJNE
XCHD DIV RLC JNB DJNZ
DA A RR JBC NOP
RRC ANL LCALL
SWAP ORL ACALL
CPL RET
RETI
JMP

Explain any 1 or 2 instructions based on Marks

 4.Memory Organization and Special function registers

Memory

Since the size of the address pointers are 16-bit they can address up to 216 = 64 k memory
locations. Hence 8031/8051 supports two memory banks of 64 kb each, one for program and
the other
for data. In 8051, when the EA pin is tied to the VCC (logic-1), the first 4 kb of program
memory address
space refers to 4 kb internal ROM and the remaining 60 kb refer to external (EPROM/RAM)
memory.
In 8051, when the EA pin is tied to the ground (logic-0), the entire 64 kb of program address
space
refers to external (EPROM/RAM) memory. In 8031 there is no internal ROM and so EA pin is
always
grounded and in this case the entire program memory is external.
The 8031/8051 has separate 256 bytes internal RAM accessed by using an 8-bit address. In
this 256 bytes address space, the first 128 addresses are allotted to internal RAM and the
next 128
bytes are allotted to SFR. The internal RAM/SFR can be accessed by using MOV
instructions and
external data memory (RAM) can be accessed by using MOVX instruction.

Special Function Registers

The 8031/8051 is provided with 21 special function registers and they are used for selecting
various programmable features of the microcontroller. The special functions of most of the
SFR
are distinguishable. Each SFR has an internal one-byte address assigned to it. Some of the
registers
are both byte and bit-addressable.
 5.Ports

Port 0

Port 0 pins may serve as inputs, outputs, or, when used together, as a bi-
directional low order address and data bus for external memory.

For example, when a pin is to be used as an input, a 1 must be written to

the corresponding port 0 latch by the program, thus turning both of the
output transistors off, which in turn causes the pin to "float" in a high
impedance state, and the pin is essentially connected to the input buffer.

When used as an output, the pin latches that are programmed to a 0 will
turn on the lower FET, grounding the pin. All latches that are
programmed to a 1 still float; thus, external pullup resistors will be
needed to supply a logic high when using port 0 as an output . When port
0 is used as an address bus to external memory, internal control signals
switch the address lines to the gates of the Field Effect Transistories
(FETs). A logic I on an address bit will turn the upper FET on and the
lower FET off to provide a logic high at the pin. When the address bit is a
zero, the lower FET is on and the upper FET off to provide a logic low at
the pin. After the address has been formed and latched into external
circuits by the Address Latch Enable (ALE) pulse, the bus is turned
around to become a data bus. Port 0 now reads data from the external
memory and must be configured as an input, so a logic 1 is automatically
written by internal control logic to all port 0 latches.
Port l

Port 1 pins have no dual functions. Therefore, the output latch is

connected directly to the gate of the lower FET, which has an FET circuit
labeled "Internal FET Pull up" as an active pull up load.

Used as an input, a 1 is written to the latch, turning the lower FET off; the
pin and the input to the pin buffer are pulled high by the FET load. An
external circuit can overcome the high impedance pull up and drive the
pin low to input a 0 or leave the input high for a 1.

If used as an output, the latches containing a I can drive the input of an

external circuit high through the pull up. If a 0 is written to the latch, the
lower FET is on, the pull up is off, and the pin can drive the input of the
external circuit low.

To aid in speeding up switching times when the pin is used as an output,

the internal FET pull up has another FET in parallel with it. The second
FET is turned on for two oscillator time periods during a low-to-high
transition on the pin, as shown in Figure 2.7.

This arrangement provides a low impedance path to the positive voltage

supply to help reduce rise times in charging any parasitic capacitances in
the external circuitry.

Port 2

Port 2 may be used as an input/output port similar in operation to port 1.

The alternate use of port 2 is to supply a high-order address byte in
conjunction with the port 0 low-order byte to address external memory.

Port 2 pins are momentarily changed by the address control signals when
supplying the high byte of a 16-bit address. Port 2 latches remain stable
when external memory is addressed, as they do not have to be turned
around (set to 1) for data input as is the case for port 0.
 Port3

Port 3 is an input/output port similar to port I. The input and output functions can be
programmed under the control of the P3 latches or under the control of various other special
function registers. The port 3 alternate uses are shown in the following table:-

Unlike ports 0 and 2, which can have external addressing functions and change
all eight port bits when in alternate use, each pin of port 3 may be individually
programmed to be used either as I/O or as one of the alternate functions
Unit V

 Programming timers & serial port

 Interrupt Enable
 LCD Interface (7 marks)
 Stepper motor Interface ( Will come in Part C)
 ADC and DAC interface

Timers of 8051

The 8051 has two timers: timer0 and timer1. They can be used either as timers or as counters. Both
timers are 16 bits wide. Since the 8051 has an 8-bit architecture, each 16-bit is accessed as two separate
registers of low byte and high byte.

Timer0 registers is a 16 bits register and accessed as low byte and high byte. The low byte is referred as
a TL0 and the high byte is referred as TH0. These registers can be accessed like any other registers.

Timer1 registers is also a 16 bits register and is split into two bytes, referred to as TL1 and TH1.

TMOD (timer mode) Register: This is an 8-bit register which is used by both timers 0 and 1 to
set the various timer modes. In this TMOD register, lower 4 bits are set aside for timer0 and the
upper 4 bits are set aside for timer1. In each case, the lower 2 bits are used to set the timer
mode and upper 2 bits to specify the operation.

In upper or lower 4 bits, first bit is a GATE bit. Every timer has a means of starting and
stopping.. The hardware way of starting and stopping the timer by an external source is
achieved by making GATE=1 in the TMOD register. And if we change to GATE=0 then we do
no need external hardware to start and stop the timers.

The second bit is C/T bit and is used to decide whether a timer is used as a time delay
generator or an event counter. If this bit is 0 then it is used as a timer and if it is 1 then it is used
as a counter.
In upper or lower 4 bits, the last bits third and fourth are known as M1 and M0 respectively.
These are used to select the timer mode.

M1 M2 Mode

0 0 13-bit timer mode.

0 1 16-bit timer mode.

1 0 8-bit auto reload mode.

1 1 Spilt mode.

Mode0- Both Timer 1 and Timer 0 in Mode 0 operate as 8-bit counters (with a divide-by-32
prescaler). Timer register is configured as a 13-bit register consisting of all the 8 bits of TH1 and
the lower 5 bits of TL1. The upper 3 bits of TL1 are indeterminate and should be ignored.
Setting the run flag (TR1) does not clear the register. The timer interrupt flag TF1 is set when
the count rolls over from all 1s to all 0s. Mode 0 operation is the same for Timer 0 as it is for
Timer 1.

Mode 1- It is a 16-bit timer; therefore it allows values from 0000 to FFFFH to be loaded into the
timer’s registers TL and TH. After TH and TL are loaded with a 16-bit initial value, the timer must
be started. We can do it by “SETB TR0” for timer 0 and “SETB TR1” for timer 1.

After the timer is started. It starts count up until it reaches its limit of FFFFH. When it rolls over
from FFFF to 0000H, it sets high a flag bit called TF (timer flag). This timer flag can be
monitored. When this timer flag is raised, one option would be stop the timer with the
instructions “CLR TR0“ or CLR TR1 for timer 0 and timer 1 respectively. Again, it must be noted
that each timer flag TF0 for timer 0 and TF1 for timer1.

After the timer reaches its limit and rolls over, in order to repeat the process the registers TH
and TL must be reloaded with the original value and TF must be reset to 0.
 .

Mode 2-

Both the timer registers are configured as 8-bit counters (TL1 and TL0) with automatic reload.
Overflow from TL1 (TL0) sets TF1 (TF0) and also reloads TL1 (TL0) with the contents of Th1
(TH0), which is preset by software. The reload leaves TH1 (TH0) unchanged.

Mode3- Mode 3 is also known as a split timer mode. Timer 0 and 1 may be programmed to be
in mode 0, 1 and 2 independently of similar mode for other timer. This is not true for mode 3;
timers do not operate independently if mode 3 is chosen for timer 0. Placing timer 1 in mode 3
causes it to stop counting; the control bit TR1 and the timer 1 flag TF1 are then used by timer0.
TCON register- Bits and symbol and functions of every bits of TCON are as follows:

BIT Symbol Functions

7 TF1 Timer1 over flow flag. Set when timer rolls from all 1s to 0. Cleared
When the processor vectors to execute interrupt service routine.

6 TR1 Timer 1 run control bit. Set to 1 by programmer to enable timer to

count; Cleared to 0 by program to halt timer.

5 TF0 Timer 0 over flow flag. Same as TF1.

4 TR0 Timer 0 run control bit. Same as TR1.

3 IE1 External interrupt 1 Edge flag. Not related to timer operations.
2 IT1 External interrupt1 signal type control bit. Set to 1 by program to

1 IE0 External interrupt 0 Edge flag. Not related to timer operations.

0 IT0 External interrupt 0 signal type control bit. Same as IT0.

Serial Communication

The 8051 microcontroller is parallel device that transfers eight bits of data simultaneously over eight data
lines to parallel I/O devices. Parallel data transfer over a long is very expensive. Hence, a serial
communication is widely used in long distance communication. In serial data communication, 8-bit data is
converted to serial bits using a parallel in serial out shift register and then it is transmitted over a single
data line. The data byte is always transmitted with least significant bit first.

The 8051 supports a full duplex serial port.

Three special function registers support serial communication.

1. SBUF Register: Serial Buffer (SBUF) register is an 8-bit register. It has separate SBUF registers for
data transmission and for data reception. For a byte of data to be transferred via the TXD line, it must be
placed in SBUF register. Similarly, SBUF holds the 8-bit data received by the RXD pin and read to accept
the received data.

2. SCON register: The contents of the Serial Control (SCON) register are shown below. This register
contains mode selection bits, serial port interrupt bit (TI and RI) and also the ninth data bit for
transmission and reception (TB8 and RB8).
INITIALIZATION AND ACCESSING SERIAL PORT REGISTERS

Receiver Enable The receiver enable bit (REN) in SCON must be set by software to enable the reception
of characters. This is usually done at the beginning of a program when the serial port, timers, etc., are
initialized.

This can be done in two ways. The instruction sets REN and sets or clears the other bits in SCON, as
required. SETB REN ; explicitly sets REN, or the instruction Interrupt Flags

The receive and transmit interrupt flags (RI and TI) in SCON play an important role in 8051 serial
communications. Both bits are set by hardware, but must be cleared by software.

Typically, RI is set at the end of character reception and indicates "receive buffer full." This condition is
tested in software or programmed to cause an interrupt.

TI is set at the end of character transmission and indicates "transmit buffer empty." If software wishes to
send a character to the device connected to the serial port, it must first check that the serial port is ready.
In other words, if a previous character was sent, wait until transmission is finished before sending the next
character.

3. PCON register: The SMOD bit (bit 7) of PCON register controls the baud rate in asynchronous mode
transmission.

SERIAL COMMUNICATION MODES

Mode 0 In this mode serial port runs in synchronous mode. The data is transmitted and received through
RXD pin and TXD is used for clock output. In this mode the baud rate is 1/12 of clock frequency.

Mode 1 In this mode SBUF becomes a 10 bit full duplex transceiver. The ten bits are 1 start bit, 8 data bit
and 1 stop bit. The interrupt flag TI/RI will be set once transmission or reception is over. In this mode the
baud rate is variable and is determined by the timer 1 overflow rate.

Baud rate = [2smod/32] x Timer 1 overflow Rate

= [2smod/32] x [Oscillator Clock Frequency] / [12 x [256 – [TH1]]]

Mode 2
This is similar to mode 1 except 11 bits are transmitted or received. The 11 bits are, 1 start bit, 8 data bit,
a programmable 9th data bit, 1 stop bit. Baud rate = [2smod/64] x Oscillator Clock Frequency

Mode 3 This is similar to mode 2 except baud rate is calculated as in mode 1

In programming the 8051 to transfer character bytes serially

1. TMOD register is loaded with the value 20H, indicating the use of timer 1 in mode 2 (8-bit auto-reload)
to set baud rate

2. The TH1 is loaded with one of the values to set baud rate for serial data transfer

3. The SCON register is loaded with the value 50H, indicating serial mode 1, where an 8- bit data is
framed with start and stop bits

4. TR1 is set to 1 to start timer 1

5. TI is cleared by CLR TI instruction

6. The character byte to be transferred serially is written into SBUF register

7. The TI flag bit is monitored with the use of instruction JNB TI, xx to see if the character has been

transferred completely

8. To transfer the next byte, go to step 5

Stepper motor Interface

Stepper Motor

Stepper motors are used to translate electrical pulses into mechanical movements. In some disk drives,
dot matrix printers, and some other different places the stepper motors are used. The main advantage of
using the stepper motor is the position control. Stepper motors generally have a permanent magnet shaft
(rotor), and it is surrounded by a stator.
Interfacing Stepper Motor with 8051 Microcontroller
Weare using Port P0 of 8051 for connecting the stepper motor. HereULN2003 is used. This is basically a
high voltage, high current Darlington transistor array. Each ULN2003 has seven NPN Darlington pairs. It
can provide high voltage output with common cathode clamp diodes for switching inductive loads.

The Unipolar stepper motor works in three modes.

 Wave Drive Mode − In this mode, one coil is energized at a time. So all four coils are energized
one after another. This mode produces less torque than full step drive mode.

The following table is showing the sequence of input states in different windings .

Steps Winding A Winding B Winding C Winding D

1 1 0 0 0

2 0 1 0 0

3 0 0 1 0

4 0 0 0 1

 Full Drive Mode − In this mode, two coils are energized at the same time. This mode
produces more torque. Here the power consumption is also high
The following table is showing the sequence of input states in different windings.

Steps Winding A Winding B Winding C Winding D

1 1 1 0 0

2 0 1 1 0

3 0 0 1 1

4 1 0 0 1

 Half Drive Mode − In this mode, one and two coils are energized alternately. At first,
one coil is energized then two coils are energized. This is basically a combination of
wave and full drive mode. It increases the angular rotation of the motor
The following table is showing the sequence of input states in different windings.

Steps Winding A Winding B Winding C Winding D

1 1 0 0 0

2 1 1 0 0

3 0 1 0 0

4 0 1 1 0

5 0 0 1 0

6 0 0 1 1
 Steps Winding A Winding B Winding C Winding D

7 0 0 0 1

8 1 0 0 1

ADC and DAC Interfacing

In many applications, an analog device has to be interfaced to the digital system. But the digital devices
cannot accept the analog signals directly and so the analog signals are converted to equivalent digital
signal (data) using an Analog-to-Digital Converter (ADC).

The analog to digital (A/D) conversion is the reverse process of Digital-to-Analog (D/A) conversion. The
A/D conversion is also called quantization, in which the analog signal is represented by an equivalent
binary data.

The analog signals vary continuously and defined for any interval of time. The digital signals (or data) can
take only finite values and defined only for discrete instant of time. If the digital data is represented by n-
bit binary then it can have 2n different values. In A/D conversion the given analog signal has to divided
into steps of 2n values, and each step is represented by one of the 2n values.

Analog to digital converters can be classified into two groups based on the technique involved for
conversion. The first group includes successive-approximation, counter and flash-type converters. The
technique involved in these devices is that the given analog signal is compared with internally generated
analog signal. The second group includes integrator converters and voltage to frequency converters. In
the devices of the second group, the given analog signal is converted to time or frequency and the new
parameters (time or frequency) is compared with known values to produce digital signal.

. The successive-approximation type converters are used for high speed conversion and integrating type
converters are used for high accuracy.

The resolution of the converter is the minimum analog value that can be represented by the digital data. If
the ADC gives n-bit digital output and the full scale analog input is X volts, then the resolution is 1 /2n × X
volts.

In ADC, another critical parameter is conversion time. The conversion time is defined as the total time
required to convert an analog signal into its digital equivalent. It depends on the conversion technique and
the propagation delay in various circuits.

A successive-approximation ADC consist of D/A converter, successive approximation register and

comparator. The conversion process is initiated by a Start Of Conversion (SOC) signal from the processor
to ADC. On receiving the SOC, the control unit of ADC will give a start command to successive
approximation register and it starts generating digital signal by successive approximation method.

The generated digital data is converted to analog signal by D/A converter and then compared with given
analog signal. When the analog signals are equal, the comparator output informs the control unit to stop
generation of digital signal. The digital data available at this instant is given as output through output
register. Also, the control unit generates a signal to indicate the End Of Conversion (EOC) process to the
processor.

Interfacing ADC0809 with 8031/8051 microcontroller

In simple systems when the ports are free the ADC0809 can be directly interfaced through the port pins of
8x5x family of controllers. An example of a ADC interface with a 8x5x controller

In this system the channel address (A, B, C) and the control signals (ALE,SOC, EOC, OE) are applied
through port-0 pins. The ADC data (i.e, converted digital data) is read through port 1. The program for
ADC conversion can be permanently stored in the internal program memory of the controller.

The ADC interface can work as follows:

1. First the controller has to send the channel address through P0.0 to P0.2 port lines. Then the port pin P0.3 is
asserted high and then low to latch the address into the ADC.
2. The ADC conversion is initiated by asserting SOC as high and then low through the P0.4 pin.
3. Then the controller keeps on polling the status of the EOC through the P0.5 pin. (At the end of conversion
the ADC
will assert EOC as high.)
4. When the controller finds a valid EOC, it will read the digital data from the output buffer by sending a logic
high enable signal through the P0.6 pin.

The ADC0809 can also be interfaced to an 8031/8051 microcontroller as memory-mapped IO as

The address lines A0, A1 and A2 are used to select the desired channel for conversion. The signals SOC
and OE are generated using a decoder. The signal EOC is read by the controller through a tristate buffer.
The clock signal at X2 pin is divided by a suitable clock divider and used as an ADC clock. A separate
source is provided for reference voltage.
DAC Interface
In many applications, the microprocessor has to produce analog signals for controlling certain analog
devices. Basically, the microprocessor system can produce only digital signals. In order to convert the
digital signal to analog signal a Digital-to-Analog Converter (DAC) has to be employed.

The DAC will accept a digital (binary) input and convert to analog voltage or current. Every DAC will have
"n" input lines and an analog output. The DAC requires a reference analog voltage (Vref) or current (Iref)
source. The smallest possible analog value that can be represented by the n-bit binary code is called
resolution. The resolution of DAC with n-bit binary input is 1 / 2 n of reference analog value. Every analog
output will be a multiple of the resolution.
In some converters, the input reference analog signal will be multiplied or divided by a constant to get full
scale value. In this case, the resolution will be 1 / 2 n of full scale value.

For example, consider an 8-bit DAC with reference analog voltage of 5-Volts. Now the resolution of the
DAC is (1/28 ) × 5-Volts. The 8-bit digital input can take, 28 = 256 different values. The analog values for all
possible digital

The DAC0800 is an 8-bit, high speed, current output DAC with a typical settling time (conversion time) of
100 ns. It produces complementary current output which can be converted to voltage by using simple
resistor load.

In simple systems, when the ports are free the DAC0800 can be directly interfaced to an 8-bit port of any
8x5x family of controller, as shown in Fig. 9.87. In this system, the controller can be programmed to work
as a signal generator for various applications and the program can be permanently stored in the internal
program memory of the controller. Since the 8x5x ports are internally provided with latch there is no need
for external latch to interface DAC0800.

The DAC0800 can also be interfaced to an 8031/8051 microcontroller as memory-mapped IO, as shown
in Fig. 9.88. In this case an 8-bit latch such as 74LS273 is interfaced to the system bus and mapped in
the data memory address space with 16-bit address. The DAC0800 is connected to output lines of the
latch. The controller will load the digital data to the latch and it will hold the data on its output lines. The
next data will be loaded to the latch only when previous data has been converted to analog value. The
loading of consecutive data to the latch of DAC is controlled by software time delay.
The address lines A13, A14 and A15 are decoded to generate 8 chip select signals and in this the
signal CS3 is used as logic low enable for the DAC latch 74LS273. The signals RD and WR are
logically ANDed and used as logic low enable for the decoder and the signal PSEN is used as logic
high enable for the decoder.

LCD interfacing with 8051 microcontroller

LCD PIN DISCRIPTION
Pin 1 GND (0v)

Pin 2 Vcc (5v)

Pin 3 VEE (contrast adjustment through variable resistor)

Pin 4 RS (command register when low, data register when high)

Pin 5 R/W (high for read from register, low for write to the register)

Pin 6 EN (sends data to data pins when high to low pulse is given)

Pin 7-14 DB0-DB7 (8-bit data pins)

Pin 15 LED+ (backlight, Vcc 5v)

Pin 16 LED- (backlight, GND 0v)

LCD interfacing WORKING

EN pin is for enabling the module. A high to low transition at this pin will enable the LCD module.
ThisLM016L has two built in registers namely:

Data register
Command register
Data register: It is for placing the data which is to be displayed. Data can be any character, alphabet or
number.High logic at the RS pin will select the data register. By making RS pin high and putting data in
the 8 bit data line (DB0 to DB7), the LCD module will recognize it as a data to be displayed.

Command register:It is for placing the commands. There is a set of commands for LCD to perform
specific tasks. Low logic at the RS pin will select the command register.By making RS pin low and putting
data on the data line, the LCD module will recognize it as a command.Some of the
instructions/commands are given below:

Code (in Hex) Working of LCD commands

0x01 Clear displays

0x02 return home

0x06 for entry mode

0x80 Force cursor to beginning of 1st line

0xC0 Force cursor to beginning of 2nd line

0x90 Force cursor to beginning of 3rd line

0xD0 Force cursor to beginning of 4th line

0x08 Display off, cursor off

0x0E Display on, cursor on

0x0C Display on, cursor off

0x0F Display on, cursor blinking

0x10 Shift cursor position to left

0x14 Shift cursor position to right

0x38 2 lines and 5×7 matrix (8-bit mode)

0x28 2 lines and 5×7 matrix (4-bit mode)

R/W pin is for selecting between read and write modes. High level at this pin enables read mode and low
level at this pin enables write mode.

DB0 to DB7 are the data pins. The data to be displayed and the commands are placed on these pins.

For glowing backlight LED, LED+ (anode of back light LED)is connected to Vcc through a suitable series
current limiting resistor (for contrast adjustment). LED-(cathode of the back light LED) is connected to
ground.

LCD INTERFACING WITH 8051 MICROCONTROLLER

This LCD can be operated in 4-bit mode (using only 4 data lines) or 8-bit mode (using all 8 data lines).
Here we will useit in 8-bit mode. First of all LCD is initialized and then it can be used for sending data and
commands. Reset and Enable of LCD is connected to port 1 of 8051 microcontroller. Data lines of LCD
are connected to port 2 of 8051 microcontroller. R/W is connected to ground since we have to just write
data and command (not read operation). This gives a little ease so that we don’t need to make this pin
low in the code.
TO INITIALIZE LCD for interfacing with 8051 microcontroller
To initialize LCD with 8051 microcontroller, following instruction are to be executed:
0x38 (is used for 8-bit data initialization)
0x0C (display on, cursor off)
0x01 (for clearing screen)
st
0x80 (force cursor to beginning of 1 line)
TO SENDDATA:
For displaying any character whether it is number, alphabet or character, following steps should be follow:
 For display data, register select (RS pin) should be high, RS = 1.
 Place data byte on the data register.
 Pulse the Enable pin (EN pin) from high to low.
 Configure the R/W to write mode. For write mode,R/W = 0.
 Repeat above steps for sending another data.
TO SEND COMMAND:
To instruct LCD for performing specific task for example displaying character in second row instead of
one, following steps should be taken:
 For command mode, register select (RS pin) should be low, RS = 0.
 Place data byte on the command register.
 Pulse the Enable pin (EN pin) from high to low.
 Read/Write should be low (write mode), R/W = 0.
 Repeat above steps for sending another command.