Module – 1 Subject: ES (Embedded Systems)

Embedded Systems
and MicroControllers

By
Venkata Sridhar .T M.Tech,PhD,MIETE

Assistant Professor of ETC.

IIIT-Bhubaneswar.
 Overview and Prerequisite
Overview:
The field of embedded systems is wide and varied, and it is
difficult to pin down exact definitions or descriptions.
However, an embedded system
(Electronic) can be broadly defined
as a device that contains tightly
coupled ‘hardware’ and ‘software’
components to perform a single
function, forms part of a larger
system, is not intended to be
independently programmable by the
user, and is expected to work with
minimal or no human interaction.

2
By T.VenkataSridhar , ETC
 Overview and Prerequisite
Overview contd..:
Early Forms of Embedded Systems

Fig.2 AGC user interface

module (public photo
EC96- 43408-1 by
NASA)

Fig. 1. Control panel and paper tape transport view of a Colossus Mark II
3 computer (public image by the British Public Record Office, London)
By T.VenkataSridhar , ETC
 Overview and Prerequisite
Overview contd..: :
Birth and Evolution of Modern Embedded Systems
The beginning of the decade of 1970 witnessed the development of the first
micro-processor designs. By the end of 1971, almost simultaneously and
independently, design teams working for Texas Instruments, Intel, and the US
Navy had developed implementations of the first microprocessors.

Fig.4 Die microphotograph (left) and packaged

part for the Intel 4004 (Courtesy of Intel
Fig.3 Die microphotograph (left) packaged
Corporation)
part for the TMS1000 (Courtesy of Texas
Instruments, Inc.)
4 By T.VenkataSridhar , ETC
 Overview and Prerequisite
Overview contd..: :
After these developments, it did not take long for designers to realize the
potential of microprocessors and its advantages for implementing embedded
applications.

Microprocessor designs soon evolved from 4-bit to 8-bit CPUs. By the end of
the 1970s, the design arena was dominated by 8-bit CPUs and the market for
microprocessors-based embedded applications had grown to hundreds of
millions of dollars.

The list of initial players grew to more than a dozen of chip manufacturers that,
besides Texas Instruments and Intel, included Motorola, Zilog, Intersil, National
Instruments, MOS Technology, and Signetics, to mention just a few of the most
renowned.

Despite this flourishing in CPU sizes and manufacturers, the applications for
embedded systems have been dominated for decades by 8, 16 and 32-bit
microprocessors and so on.-
5 By T.VenkataSridhar , ETC
 Overview and Prerequisite
Overview contd..: :

Fig.5 Estimates of processor market distribution (Source Embedded systems

design—www. embedded.com)

6 By T.VenkataSridhar , ETC
 Overview and Prerequisite
Overview contd..: :

Prerequisite: Analog electronics, Digital Electronics, Basic

programming concepts, Processors and programming.
7 By T.VenkataSridhar , ETC
 Syllabus : Module-1

Introduction to Embedded Electronic Systems and Microcontrollers: An Embedded

System-Definition, Embedded System Design and Development Life Cycle, An Introduction to
Embedded system Architecture, The Embedded Systems Model. 2 Hrs
Embedded Hardware: The Embedded Board and the von Neumann Model.
Embedded Processors: ISA Architecture Models, Internal Processor Design, Processor
Performance. 2 Hrs
Board Memory: Read-Only Memory (ROM), Random-Access Memory (RAM), Auxiliary Memory,
Memory Management of External Memory and Performance, Approaches to Embedded Systems,
Small Microcontrollers, Anatomy of a Typical Small Microcontroller, Small Microcontrollers
Memory, Embedded Software, Introduction to small microcontroller (MSP430). 4 Hrs

Architecture of the MSP430 Processor: Central Processing Unit, Addressing Modes, Constant
Generator and Emulated Instructions, Instruction Set, Examples, Reflections on the CPU and
Instruction Set, Resets, Clock System, Memory and Memory Organization. 2 Hrs
Functions, Interrupts, and Low-Power Mode: Functions and Subroutines, Storage for Local
Variables, Passing Parameters to a Subroutine and Returning a Result, Mixing C and Assembly
Language, Interrupts, Interrupt Service Routines, Issues Associated with Interrupts, Low-Power
Modes of Operation. 2 Hrs

8 By T.VenkataSridhar , ETC
 Module-1
Introduction to Embedded Electronic Systems and
Microcontrollers
Definition:
❖ An embedded system is an applied computer system, as
distinguished from other types of computer systems such as
personal computers (PCs) or supercomputers.

❖ However, you will find that the definition of “embedded

system” is fluid and difficult to pin down, as it constantly
evolves with advances in technology and dramatic decreases
in the cost of implementing various hardware and software
components.
Following are a few of the more common descriptions of an embedded
system:
Embedded systems are more limited in hardware and/or
software functionality than a personal computer (PC).
9
By T.VenkataSridhar , ETC
 An embedded system is designed to perform a dedicated function

An embedded system is a computer system with higher quality and

reliability requirements than other types of computer systems.

Some devices that are called embedded systems, such as PDAs or

web pads, are not really embedded systems.

Electronic devices in just about every engineering market segment

are classified as embedded systems (see Table 1-1). In short,
outside of being “types of computer systems,” the only specific
characterization that continues to hold true for the wide spectrum of
embedded system devices is that there is no single definition
reflecting them all.

10
By T.VenkataSridhar , ETC
11
By T.VenkataSridhar , ETC
12 By T.VenkataSridhar , ETC
 Embedded Systems Design
When approaching embedded systems architecture design from a
systems engineering point of view, several models can be applied to
describe the cycle of embedded system design.

Most of these models are based upon one or some combination of the
following development models.

The big-bang model, in which there is essentially no planning or

processes in place before and during the development of a system.

The code-and-fix model, in which product requirements are

defined but no formal processes are in place before the start of
development.

13 By T.VenkataSridhar , ETC
 The waterfall model, in which there is a process for developing a
system in steps, where results of one step flow into the next step.

The spiral model, in which there is a process for developing a

system in steps, and throughout the various steps, feedback is
obtained and incorporated back into the process.

Embedded Systems Design and Development Lifecycle Model

▪ This model is based on a combination of the popular waterfall and
spiral industry models.
▪ It is identified that the successful projects contained at least one common
factor that the problem projects lacked.

▪ This factor is the process shown in Figure 1-1, and this is why this model is
introduce as an important tool in understanding an embedded system’s
design process.
14 By T.VenkataSridhar , ETC
 Figure 1-1: Embedded Systems Design and Development
Lifecycle Model.
15 By T.VenkataSridhar , ETC
 As shown in Figure 1-1, the embedded system design and development
process is divided into four phases:
o Creating the architecture,
o Implementing the architecture,
o Testing the system, and
o Maintaining the system.

An Introduction to Embedded Systems Architecture

The architecture of an embedded system is an abstraction of the
embedded device:
Meaning that it is a generalization of the system that typically doesn’t
show detailed implementation information such as software source code
or hardware circuit design.
At the architectural level, the hardware and software components in an
embedded system are instead represented as some composition of
interacting elements.
16 By T.VenkataSridhar , ETC
 Figure 1-2: Embedded Systems Architecture (sample)

17 By T.VenkataSridhar , ETC
 Architecture-level information is physically represented in the form of
structures. A structure is one possible representation of the architecture,
containing its own set of represented elements, properties, and
inter-relationship information. A structure is therefore a “snapshot” of the
system’s hardware and software at design time and/or at run-time, given a
particular environment and a given set of elements. Since it is very
difficult for one “snapshot” to capture all the complexities of a system, an
architecture is typically made up of more than one structure. All structures
within an architecture are inherently related to each other, and it is the sum
of all these structures that is the embedded architecture of a device.

Table 1-2 summarizes some of the most common structures that

can make up embedded architectures, and shows generally what
the elements of a particular structure represent and how these
elements interrelate.

18 By T.VenkataSridhar , ETC
 Table 1-2

19 By T.VenkataSridhar , ETC
 The Embedded Systems Model
A variety of architectural structures are used to introduce technical
concepts and fundamentals of an embedded system. This is an emerging
architectural tools (i.e., reference models) used as the foundation for these
architectural structures.
At the highest level, the primary architectural tool used to introduce the
major elements located within an embedded system design is what refer to
as the Embedded Systems Model, shown in Figure 1-2.

Figure 1-3: Embedded Systems Model

20 By T.VenkataSridhar , ETC
 Embedded Systems Model indicates that all embedded systems share one
similarity at the highest level; that is,

1. They all have at least one layer (hardware) or all layers (hardware,
system software and application software) into which all components
fall.

2. The hardware layer contains all the major physical components

located on an embedded board.

3. whereas the system and application software layers contain all of the
software located on and being processed by the embedded system.

This reference model is essentially a layered (modular) representation of an

embedded systems architecture from which a modular architectural
structure can be derived. Regardless of the differences between the devices
shown in Table 1-1, it is possible to understand the architecture of all of
these systems by visualizing and grouping the components within these
devices as layers.
21 By T.VenkataSridhar , ETC
 Figure 1-4: Host and target system diagram

Figure 1-5: a) Compilation diagram, b) C Example compilation/linking steps

22 and object file results By T.VenkataSridhar , ETC
 Table 1-3: Evolution of programming languages

23 By T.VenkataSridhar , ETC
 Embedded Hardware
Prerequisite:
✔Basic Hardware Materials: Conductors, Insulators, and Semiconductors
✔Common Passive Components on Boards & in Chips: Resistors, Capacitors, & Inductors.
✔Semiconductors and the Active Building Blocks of Processors and Memory
✔Putting It All Together: The Integrated Circuit (IC): SSI to ULSI

Importance of understand Hardware

1. Every embedded designer should understand the diagrams and symbols that
hardware has which describe hardware designs to the outside world.

2. These diagrams and symbols are the keys to quickly and efficiently
understanding even the most complex hardware design, regardless of how
much or little practical experience one has in designing real hardware.

3. They also contain the information an embedded programmer needs to design

any software that requires compatibility with the hardware, and they provide
insight to a programmer as to how to successfully communicate the hardware
requirements of the software to a hardware.
24 By T.VenkataSridhar , ETC
 There are several different types of engineering hardware drawings, including:

Block diagrams
They typically depict the major components of a board (processors, buses, I/O,
memory) or a single component (a processor, for example) at a systems
architecture or higher level. In short, a block diagram is a basic overview of the
hardware, with implementation details abstracted out. While a block diagram can
reflect the actual physical layout of a board containing these major components, it
mainly depicts how different components or units within a component function
together at a systems architecture level.
Schematics.
Schematics are electronic circuit diagrams that provide a more detailed view of
all of the devices within a circuit or within a single component everything from
processors down to resistors. A schematic diagram is not meant to depict the
physical layout of the board or component, but provides information on the flow
of data in the system, defining what signals are assigned where—which signals
travel on the various lines of a bus, appear on the pins of a processor, and so on.
In schematic diagrams, schematic symbols are used to depict all of the
components within the system.
25 By T.VenkataSridhar , ETC
 Wiring diagrams.
These diagrams represent the bus connections between the major and minor
components on a board or within a chip. In wiring diagrams, vertical and horizontal
lines are used to represent the lines of a bus, and either schematic symbols or more
simplified symbols (that physically resemble the other components on the board or
elements within a component) are used. These diagrams may represent an
approximate depiction of the physical layout of a component or board.
Logic diagrams/prints.
Logic diagrams/prints are used to show a wide variety of circuit information using
logical symbols (AND, OR, NOT, XOR, and so on), and logical inputs and
outputs (the 1’s and 0’s). These diagrams do not replace schematics, but they can
be useful in simplifying certain types of circuits in order to understand how they
function.
Timing diagrams.
Timing diagrams display timing graphs of various input and output signals of a
circuit, as well as the relationships between the various signals. They are the most
common diagrams (after block diagrams) in hardware user manuals and data
sheets.
26 By T.VenkataSridhar , ETC
 Regardless of the type, in order to understand how to read and
interpret these diagrams, it is first important to learn the standard
symbols, conventions, and rules used.

Table 1-4: Timing diagrams symbol table.

27 By T.VenkataSridhar , ETC
 An example of a timing diagram is shown in Figure 1-6. In this
figure, each row represents
a different signal.

Figure 1-6: Timing diagram example

Schematic diagrams are much more complex than their timing

diagram counterparts. Figure 1-7 shows an example of a
schematic diagram.
28 By T.VenkataSridhar , ETC
 Figure 1-7: Schematic diagram example.
29 By T.VenkataSridhar , ETC
 In the case of schematic diagrams, some of the conventions and rules include:

A title section located at the bottom of each schematic page, listing information
that includes, but is not limited to, the name of the circuit, the name of the
hardware engineer responsible for the design, the date, and a list of revisions made
to the design since its conception.

The use of schematic symbols indicating the various components of a circuit

Along with the assigned symbol comes a label that details information about
the component (i.e., size, type, power ratings, etc.). Labels for components of a
symbol, such as the pin numbers of an IC, signal names associated with wires, and
so forth are usually located outside of the schematic symbol.

Abbreviations and prefixes are used for common units of measurement (i.e., k
for kilo or 103, M for mega or 106) and these prefixes replace writing out the units
and larger numbers.

Functional groups and subgroups of components are typically separated onto

different pages.
30 By T.VenkataSridhar , ETC
 I/O and Voltage Source/Ground Terminals. In general, positive voltage supply
terminals are located at the top of the page, and negative supply/ground at the
bottom. Input components are usually on the left, and output components are on
the right.

One of the most efficient ways of learning how to learn to read and/or create a
hardware diagram is via the Traister and Lisk method, which involves:

Step 1. Learning the basic symbols that can make up the type of diagram, such
as timing or schematic symbols. To aid in the learning of these symbols,
rotate between this step and steps 2 and/or 3.

Step 2. Reading as many diagrams as possible, until reading them becomes

boring (in that case rotate between this step and steps 1 and/or 3) or
comfortable (so there is no longer the need to look up every other
symbol while reading).

Step 3. Writing a diagram to practice simulating what has been read, again until
it either becomes boring (which means rotating back through steps 1
and/or 2) or comfortable.
31 By T.VenkataSridhar , ETC
 The Embedded Board and the von Neumann Model

Embedded Board

❖ In embedded devices, all the electronics hardware resides on a board, also

referred to as a printed wiring board (PW) or printed circuit board (PCB).

❖ PCBs are often made of thin sheets of fiber-glass. The electrical path of the
circuit is printed in copper, which carries the electrical signals between the
various components connected on the board.

❖ All electronic components that make up the circuit are connected to this
board, either by soldering, plugging in to a socket, or some other connection
mechanism.

❖ All of the hardware on an embedded board is located in the hardware layer of

the Embedded Systems Model (see Figure 1-8).

32 By T.VenkataSridhar , ETC
 Figure 1-8: Embedded board
and the Embedded Systems
Model

At the highest level, the major hardware components of most boards can be
classified into five major categories:

Central Processing Unit (CPU) – the master processor

Memory – where the system’s software is stored
Input Device(s) – input slave processors and relative electrical components
Output Device(s) – output slave processors and relative electrical components
Data Pathway(s)/Bus(es) – interconnects the other components, providing a
“highway” for data to travel on from one component to another, including any
wires, bus bridges, and/or bus controllers.

33 By T.VenkataSridhar , ETC
 These five categories are based upon the major elements defined by the von
Neumann model (see Figure 1-9), a tool that can be used to understand any
electronic device’s hardware architecture.
The von Neumann model

Figure 1-9: Embedded system board organization

34 {Based upon the von Neumann architecture model (also referred to as the Princeton Architecture.}
By T.VenkataSridhar , ETC
 1. The von Neumann model is a result of the published work of
John von Neumann in 1945, which defined the requirements of a
general-purpose electronic computer.

2. Because embedded systems are a type of computer system, this

model can be applied as a means of understanding embedded
systems hardware.

3. While board designs can vary widely as demonstrated in the

examples of Figures 1-10a, b, c, d, and e ball of the major
elements on these embedded boards.

4. And on just about any embedded board can be classified as

either the master CPU(s), memory, input/output, or bus
components.

35 By T.VenkataSridhar , ETC
 Figure 1-10a: AMD/National Semiconductor ×86 reference board.
© 2004 Advanced Micro Devices, Inc. Reprinted with permission.
36 By T.VenkataSridhar , ETC
 Figure 1-10b: Net Silicon ARM7 reference board
37 By T.VenkataSridhar , ETC
 Figure 1-10c: Ampro MIPS reference board

38 By T.VenkataSridhar , ETC
 Figure 1-10d: Ampro PowerPC reference board .
Copyright of Freescale Semiconductor, Inc. 2004. Used by permission.

39 By T.VenkataSridhar , ETC
 Figure 1-10e: Mitsubishi analog TV reference board

Embedded Processors
Processors are the main functional units of an embedded board, and are primarily
responsible for processing instructions and data. An electronic device contains at
least one master processor, acting as the central controlling device, and can have
additional slave processors that work with and are controlled by the master
processor. As shown in Figure 1-11, the Atlas STPC is the master processor, and
the super I/O and ethernet controllers are slave processors.
40 By T.VenkataSridhar , ETC
 As shown in Figure
1-11, embedded
boards are designed
around the master
processor. The
complexity of the
master processor
usually determines
whether it is
classified as a
microprocessor
or a
microcontroller.

Figure 1-11: Ampro’s Encore 400 board

41 By T.VenkataSridhar , ETC
 ❑ There are literally hundreds of embedded processors available, and not one of
them currently dominates embedded system designs.

❑ Despite the sheer number of available designs, embedded processors can be

separated into various “groups” called architectures.

❑ What differentiates one processor group’s architecture from another ?

❑ The set of machine code instructions that the processors within the architecture
group can execute.

❑ Processors are considered to be of the same architecture when they can execute
the same set of machine code instructions.

❑ Table 1-5 lists some examples of real-world processors and the architecture
families they fall under.

42 By T.VenkataSridhar , ETC
 Table 1-5: Real-world architectures and processors.

43 By T.VenkataSridhar , ETC
 ISA Architecture
▪Models
The features that are built into an architecture’s instruction set are commonly
referred to as the Instruction Set Architecture or ISA.
▪ The ISA defines such features as the operations that can be used by
programmers to create programs for that architecture, the operands (data) that are
accepted and processed by an architecture, storage, addressing modes used to
gain access to and process operands, and the handling of interrupts.
Operations
Operations are made up of one or more instructions that execute certain
commands. (Note that operations are commonly referred to simply as
instructions.) Different processors can execute the exact same operations using a
different number and different types of instructions. An ISA typically defines the
types and formats of operations.

Types of Operations
Operations are the functions that can be performed on the data, and they
typically include the following.
44 By T.VenkataSridhar , ETC
 The instruction set on a popular lower-end processor, the 8051, includes just over
100 instructions for math, data transfer, bit variable manipulation, logical
operations, branch flow and control, and so on. In comparison, a higher end
MPC823 (Motorola/Freescale PowerPC) has an instruction set a little larger than
that of the 8051, but with many of the same types of operations contained in the
8051 set along with an additional handful, including integer
operations/floating-point (math) operations, load and store operations, branch and
flow control operations, processor control operations, memory synchronization
operations, PowerPC VEA operations, and so on.

45 By T.VenkataSridhar , ETC
 In short, different processors can have similar types of operations, but usually
have different overall instruction sets. For example,

Figure 1-12: MPC823 compare operation

Copyright of Freescale Semiconductor, Inc. 2004. Used by permission

Figure 1-13: MIPS32/MIPS I – compare operation

46 By T.VenkataSridhar , ETC
 Operation Formats
The format of an operation is the actual number and combination of bits (1s and
0s) that represent the operation, and is commonly referred to as the operation
code or opcode.
MPC823 opcodes, for instance, are structured the same and are all 6 bits long
(0-63 decimal) (see Figure 1-14a).
MIPS32/MIPS I opcodes are also 6 bits long, but the opcode can vary as to where
it is located, as shown in Figure 1-14b.

Figure 1-14a: MPC823 “CMP” operation size.

© 2004 Freescale Semiconductor, Inc. Used by permission.

Figure 1-14b: MIPS32/MIPSI “CMP” and “ADD” operation sizes and locations.
47 By T.VenkataSridhar , ETC
 Operands

▪ Operands are the data that operations manipulate. An ISA defines the types and
formats of operands for a particular architecture.
▪ For example, in the case of the MPC823(Motorola/Freescale PowerPC),
SA-1110 (Intel StrongARM), and many other architectures, the ISA defines
simple operand types of bytes (8 bits), half words (16 bits), and words (32 bits).
More complex data types such as integers, characters, or floating point are
based on the simple types shown in Figure 1-15a.

Figure 1-15a: Simple operand types.

An ISA also defines the

operand formats (how the data
looks) that a particular
architecture can support, such Figure 1-15ab: Operand formats
as binary, decimal, and pseudocode example.
hexadecimal.
48 By T.VenkataSridhar , ETC
❑ Storage
The ISA specifies the features of the programmable storage used to store the data
being operated on, primarily the organization of memory used to store operands
and register set, and how registers are used.

Memory is simply an array of programmable storage, like that shown in Figure

1-16, that stores data, including operations and operands.

The Organization of Memory Used to Store Operands

• Linear Table 1-6: “x-Bit” Architecture Examples

• Segmented.
• Containing any special address regions.
• Limited
• Register Set

❑ Addressing Modes

Load-store architecture: Register-memory architecture:

49 By T.VenkataSridhar , ETC
❑ Interrupts and Exception Handling
Interrupts (also referred to as exceptions or traps depending on the type) are
mechanisms that stop the standard flow of the program in order to execute another
set of code in response to some event, such as problems with the hardware, resets,
and so forth. The ISA defines what, if any, type of hardware support a processor
has for interrupts.

ISA Models
There are several different ISA models that architectures are based upon, each
with their own definitions for the various features.

The most commonly implemented ISA models are .

Application-specific,
General-purpose,
Instruction-level parallel,
or some Hybrid combination of these three ISAs.

50 By T.VenkataSridhar , ETC
 Application-specific ISA Models
Application-specific ISA models define processors that are intended for
specific embedded applications, such as processors made only for TVs. There are
several types of application specific ISA models implemented in embedded
processors, the most common models being:
Controller Model
The Controller ISA is implemented in processors that are not required to perform
complex data manipulation, such as video and audio processors that are used as
slave processors on a TV board, for example (see Figure 1-16).

Figure 1-16: Analog TV board example with

51 controller ISA implementations. By T.VenkataSridhar , ETC
 Datapath Model
The Datapath ISA is implemented in processors whose purpose is to repeatedly
perform fixed computations on different sets of data, a common example being
digital signal processors (DSPs), shown in Figure 1-17.

Figure 1-17: Board example with datapath ISA

implementation—digital cellphone
52 By T.VenkataSridhar , ETC
 Finite State Machine with Datapath (FSMD) Model
The FSMD ISA is an implementation based upon a combination of the Datapath ISA
and the Controller ISA for processors that are not required to perform complex data
manipulation and must repeatedly perform fixed computations on different sets of
data. Common examples of an FSMD implementation are application-specific
integrated circuits (ASICs) shown in Figure 4-9, programmable logic devices (PLDs),
and field-programmable gate-arrays (FPGAs, which are essentially more complex
PLDs).

Figure 1-18: Board example with FSMD ISA

53 implementation—solid-state digital camcorder By T.VenkataSridhar , ETC
 Java Virtual Machine (JVM) Model
The JVM ISA is based upon one of the Java Virtual Machine standards from, Sun
Microsystem’s Java Language. A real-world JVMs can be implemented in an
embedded system via hardware, such as in aJile’s aj-80 and aj-100 processors, for
example (Figure 1-19).

Figure 1-19: JVM ISA implementation example

54 By T.VenkataSridhar , ETC
 General-purpose ISA Models
General-purpose ISA models are typically implemented in
processors targeted to be used in a wide variety of systems, rather
than only in specific types of embedded systems.

The most common types of general-purpose ISA architectures

implemented in embedded processors are:

Complex Instruction Set Computing (CISC) Model

The CISC ISA, as its name implies, defines complex operations

made up of several instructions. Common examples of
architectures that implement a CISC ISA are

• Intel’s x86 and

• Motorola/Freescale’s 68000 families of processors.
55 By T.VenkataSridhar , ETC
 Figure 1-20: CISC ISA implementation example.
© 2004 Advanced Micro Devices, Inc.
56 By T.VenkataSridhar , ETC
 Reduced Instruction Set Computing (RISC) Model
In contrast to CISC, the RISC ISA usually defines:
o an architecture with simpler and/or fewer operations made up of fewer
instructions.
o an architecture that has a reduced number of cycles per available operation.

Many RISC processors have

only one-cycle operations,
whereas CISCs typically have
multiple cycle operations. ARM,
PowerPC, SPARC, and MIPS
are just a few examples of
RISC-based architectures.

Figure 1-21:
RISC ISA implementation
example.

57 By T.VenkataSridhar , ETC
Instruction-level parallel ISA Models
Instruction-level Parallelism ISA architectures are similar to
general-purpose ISAs, except that they execute multiple
instructions in parallel, as the name implies.
In fact, instruction level parallelism ISAs are considered higher
evolutions of the RISC ISA, which typically has one-cycle
operations, one of the main reasons why RISCs are the basis for
parallelism.
Examples of instruction-level parallelism ISAs include:
58 By T.VenkataSridhar , ETC
 Single Instruction Multiple Data (SIMD) Model
The SIMD Machine ISA is designed to process an instruction simultaneously on
multiple data components that require action to be performed on them.

Figure 1-22: SIMD ISA implementation example (Colour Laser Printer)

59 By T.VenkataSridhar , ETC
 Superscalar Machine Model
The superscalar ISA is able to process multiple instructions simultaneously within
one clock cycle through the implementation of multiple functional components
within the processor [multiple arithmetic logic units (ALUs)].

Figure 1-23: Superscalar ISA implementation example

60 By T.VenkataSridhar , ETC
 Very Long Instruction Word Computing (VLIW) Model
The VLIW ISA defines an architecture in which a very long instruction word is
made up of multiple operations. These operations are then broken down and
processed in parallel by multiple execution units within the processor.

Figure 1-24: VLIW ISA implementation example—(VLIW) Trimedia-based DTV board

61 By T.VenkataSridhar , ETC
 Internal Processor Design
The ISA defines what a processor can do, and it is the processor’s
internal interconnected hardware components that physically
implement the ISA’s features.
Interestingly, the fundamental components that make up an
embedded board are the same as those that implement an ISA’s
features in a processor: a CPU, memory, input components, output
components, and buses.
As mentioned in Figure 1-25, these components are the basis of
the von Neumann model.
Many current real-world processors are more complex in design
than the von Neumann model has defined. However, most of these
processors’ hardware designs are still based upon von Neumann
components, or a version of the von Neumann model called the
Harvard architecture model.
62 By T.VenkataSridhar , ETC
 Figure 1-25: Von Neumann-based processor diagram

63 By T.VenkataSridhar , ETC
 These two models primarily differ in one area, and that is memory. A von
Neumann architecture defines a single memory space to store instructions and
data. A Harvard architecture defines separate memory spaces for instructions
and data; separate data and instruction buses allow for simultaneous fetches and
transfers to occur. The main reasoning behind using von Neumann versus a
Harvard-based model for an architecture design is performance.

Figure 1-26: Von Neumann vs. Harvard architectures

64 By T.VenkataSridhar , ETC
 As mentioned previously, most processors are based upon some variation of the
von Neumann model (in fact, the Harvard model itself is a variation of the von
Neumann model). Real-world examples of Harvard-based processor designs
include ARM’s ARM9/ARM10, MPC860, 8031, and DSPs (see Figure 1-27a),
while ARM’s ARM7 and x86 are von Neumann- based designs (see Figure 1-27b).

Figure 1-27a: Harvard architecture example – MPC860

65 Copyright of Freescale Semiconductor, Inc. 2004. By T.VenkataSridhar , ETC
 Figure 1-27b: Von Neumann architecture example – x86
66 By T.VenkataSridhar , ETC
Central Processing Unit (CPU)

The processing unit within a processor is the CPU.

The CPU is responsible for executing the cycle of fetching, decoding, and
executing instructions (see Figure 1-28).

This three-step process is commonly referred to as a three-stage pipeline and

most recent CPUs are pipelined designs.

As defined by the von Neumann model, this cycle is implemented through some
combination of four major CPU components:

❖ The internal CPU buses: interconnect the ALU, registers, and the CU.
❖ The arithmetic logic unit (ALU): implements the ISA’s operations.
❖ Registers: a type of fast memory.
❖ The control unit (CU): manages the entire fetching and execution cycle.

67 By T.VenkataSridhar , ETC
 Figure 1-28: Fetch, decode, and execution cycle of CPU
68 By T.VenkataSridhar , ETC
Internal CPU Buses
The CPU buses are the mechanisms that interconnect the CPU’s other components:
the ALU, the CU, and registers (see Figure 1-29). Buses are simply wires that
interconnect the various other components within the CPU (Driver controlled
wires). Each bus’s wire is typically divided into logical functions, such as data
(which carries data, bi-directionally, between registers and the ALU), address
(which carries the locations of the registers that contain the data to be transferred),
control (which carries control signal information, such as timing and control
signals, between the registers, the ALU, and the CU), and so on.

69 Figure 1-29: PowerPC core and buses By T.VenkataSridhar , ETC

 Arithmetic Logic Unit (ALU)
The arithmetic logic unit (ALU) implements the comparison, mathematical and
logical operations defined by the ISA. The format and types of operations
implemented in the CPU’s ALU can vary depending on the ISA.

Considered the core of any processor, the ALU is responsible for accepting
multiple n-bit binary operands and performing any logical (AND, OR, NOT, etc.),
mathematical (+, –, *, etc.), and comparison (=, <, >, etc.) operations on these
operands.

The ALU is a combinational logic circuit that can have one or more inputs and
only one output. An ALU’s output is dependent only on inputs applied at that
instant, as a function of time, and “no” past conditions

The basic building block of most ALUs (from the simplest to the
multifunctional) is considered the full adder, a logic circuit that takes three 1-bit
numbers as inputs and produces two 1-bit numbers.

70 By T.VenkataSridhar , ETC
 Figure 1-30a: All ALU adders at a glance
71 By T.VenkataSridhar , ETC
 Figure 1-30a: All ALU adders at a glance (contd..)
72 By T.VenkataSridhar , ETC
 Multifunction ALUs that provide addition operations, along with other
mathematical and logical operations, are designed around the adder circuitry, with
additional circuitry incorporated for performing subtraction, logical AND, logical
OR, and so on (see Table 1-7).

Table 1-7: Multifunction ALU truth table and logic equations

73 By T.VenkataSridhar , ETC
 Figure 1-31: Multifunction ALU gate-level circuitry
74 By T.VenkataSridhar , ETC
 Figure 1-32: PowerPC core and the ALU

75 By T.VenkataSridhar , ETC
 Registers
✔Registers are simply a combination of various flip-flops that can be used to
temporarily store data or to delay signals.
✔A storage register is a form of fast programmable internal processor memory
usually used to temporarily store, copy, and modify operands that are
immediately or frequently used by the system.

✔Shift registers delay signals by passing the signals between the various internal
flip-flops with every clock pulse.

✔Registers are made up of a set of flip-flops that can be activated either

individually or as a set. In fact, it is the number of flip-flops in each register that
is actually used to describe a processor (for example, a 32-bit processor has
working registers that are 32 bits wide containing 32 flip-flops, a 16-bit processor
has working registers that are 16 bits wide containing 16 flipflops, and so on).

✔The number of flip-flops within these registers also determines the width of the
data buses used in the system. Figure 1-33 shows an example of how eight
flip-flops could comprise an 8-bit register, and thus impact the size of the data
bus.
76 By T.VenkataSridhar , ETC
77 Figure 1-33: a: 8-bit register with 8 D flip-flops example , b: Example of gate level circuit of flip-flop
 While ISA designs do not all use registers in the same way to process the data,
storage typically falls under one of two categories, either general purpose or
special purpose (see Figure 1-34).

Flags

Counters

Figure 1-34: PowerPC core and register usage

78 By T.VenkataSridhar , ETC
Control Unit (CU)
The control unit (CU) is primarily responsible for generating timing signals, as well as
controlling and coordinating the fetching, decoding, and execution of instructions in the
CPU. After the instruction has been fetched from memory and decoded, the control unit
then determines what operation will be performed by the ALU, and selects and writes
signals appropriate to each functional unit within or outside of the CPU (i.e., memory,
registers, ALU, etc.). As shown in Figure 1-35, the PowerPC core’s CU is called a
“sequencer unit,” and is the heart of the PowerPC core.

79 Figure 1-35: PowerPC core and the CU By T.VenkataSridhar , ETC

The CPU and the System (Master) Clock
A processor’s execution is ultimately synchronized by an external system or master
clock, located on the board.The master clock is an oscillator along with a few other
components, such as a crystal. It produces a fixed frequency sequence of regular on/off
pulse signals (square waves), as seen in Figure 1-36.

Figure 1-36: Clock Signal

On-Chip Memory
The CPU goes to memory to get what it needs to process, because it is in memory that
all of the data and instructions to be executed by the system are stored. Embedded
platforms have a memory hierarchy, a collection of different types of memory, each
with unique speeds, sizes, and usages (see Figure 1-37).

Figure 1-37: Memory hierarchy

80 By T.VenkataSridhar , ETC
 Read-Only Memory (ROM)

Figure 1-38: 8 x 8
ROM logic circuit

81 By T.VenkataSridhar , ETC
 Acheaper and faster variation of the EEPROM is Flash memory. Where
EEPROMs are written and erased at the byte level, Flash can be written and
82 erased in blocks or sectors (a group of bytes). By T.VenkataSridhar , ETC
 Random-Access Memory (RAM)
RAM (random access memory), commonly referred to as main memory, is memory in
which any location within it can be accessed directly (randomly, rather than
sequentially from some starting point), and whose content can be changed more than
once (the number depending on the hardware). Unlike ROM, contents of RAM are
erased if RAM loses power, meaning RAM is volatile. The two main types of RAM are
static RAM (SRAM) and dynamic RAM (DRAM).

Figure 1-39: a: SRAM circuit b: DRAM circuit

83 By T.VenkataSridhar , ETC
 Cache (Level-1 Cache)
Cache is the level of memory between the CPU and main memory in the memory
hierarchy (see Figure 1-40). Cache can be integrated into a processor or can be
off-chip. Cache existing on-chip is commonly referred to as level-1 cache, and SRAM
memory is usually used as level-1 cache. Because (SRAM) cache memory is typically
more expensive due to its speed, processors usually have a small amount of cache,
whether on-chip or off-chip.

Figure 1-40: Level-1 cache in the memory hierarchy

84 By T.VenkataSridhar , ETC
 Cache is used to store subsets of main memory that are used or accessed often.
Some processors have one cache for both instructions and data, while other
processors have separate on-chip caches for each.

Figure 1-40: Level-1 cache in the von Neumann and Harvard models

85 By T.VenkataSridhar , ETC
 Processor Input/Output (I/O)
Input/output components of a processor are responsible for moving information
to and from the processor’s other components to any memory and I/O outside of
the processor, on the board (see Figure 1-41).

86 Figure 1-41: Processor I/O diagram By T.VenkataSridhar , ETC

 Processor Performance
❖ There are several measures of processor performance, but are all based upon the
processor’s behaviour over a given length of time.

❖ One of the most common definitions of processor performance is a processor’s

throughput, the amount of work the CPU completes in a given period of time.

87 By T.VenkataSridhar , ETC
❖ A processor’s execution is ultimately synchronized by an external system or
master clock, located on the board.

❖ The master clock is simply an oscillator producing a fixed frequency sequence

of regular on/off pulse signals that is usually divided or multiplied within the
CPU’s CU (control unit) to generate at least one internal clock signal running at a
constant number of clock cycles per second, or clock rate, to control and
coordinate the fetching, decoding, and execution of instructions.

❖ The CPU’s clock rate is expressed in MHz or GHz (mega or giga hertz) .

❖ Using the clock rate, the CPU’s execution time, which is the total time the
processor takes to process some program in seconds per program (total number of
bytes), can be calculated.

❖ From the clock rate, the length of time a CPU takes to complete a clock cycle is
the inverse of the clock rate (1/clock rate), called the clock period or cycle time
and expressed in seconds per cycle.

❖ Looking at the instruction set, the CPI (average number of clock cycles per
instruction) can be determined in several ways.
88 By T.VenkataSridhar , ETC
 At this point the total CPU’s execution time can be determined by:

The processor’s average execution rate, also referred to as throughput or

bandwidth, reflects the amount of work the CPU does in a period of time and is the
inverse of the CPU’s execution time:

Knowing the performance of two architectures (Geode and SA-1100, for

example), the speedup of one architecture over another can then be calculated as
follows:

89 By T.VenkataSridhar , ETC
 Other definitions of performance besides throughput include:

Benchmarks

90 By T.VenkataSridhar , ETC
 Reading a Processor’s Datasheet
A processor’s datasheet provides key areas of useful processor information.

One shouldn’t assume that what they read from a vendor is

100% accurate, until they have seen the processor running and
verified the features themselves.

Datasheets exist for almost any component, both hardware and software, and the
information they contain varies between vendors.

Some datasheets are a couple of pages long and list only the main features of a
system, while others contain over 100 pages of technical information.

MPC860 Datasheet Example: Overview of the Processor’s Features

Figure 1-42a shows a block diagram of the MPC860, which is described in the
datasheet’s feature list shown in Figure 1-42b

91 By T.VenkataSridhar , ETC
 Figure 1-42a: MPC860 processor block diagram.© 2004 Freescale Semiconductor, Inc.

92 By T.VenkataSridhar , ETC
 Figure 1-42b: MPC860 overview from datasheet.© 2004 Freescale Semiconductor, Inc.
93 By T.VenkataSridhar , ETC
 Figure 1-42b: MPC860 overview from datasheet. Continued…
94 By T.VenkataSridhar , ETC
 Figure 1-42b: MPC860 overview from datasheet. Continued…

95 By T.VenkataSridhar , ETC
 Figure 1-42b: MPC860 overview from datasheet. Continued…
96 By T.VenkataSridhar , ETC
97 Figure 1-42b: MPC860 overview from datasheet. Continued… By T.VenkataSridhar , ETC
98 Figure 1-42b: MPC860 overview from datasheet. Continued… By T.VenkataSridhar , ETC
99 Figure 1-42b: MPC860 overview from datasheet. Continued… By T.VenkataSridhar , ETC
 MPC860 Processor Thermal Characteristics

100
Figure 1-42b: MPC860 overview from datasheet. Continued…
By T.VenkataSridhar , ETC
101 Figure 1-42b: MPC860 overview from datasheet. Continued… By T.VenkataSridhar , ETC
102 Figure 1-42b: MPC860 overview from datasheet. Continued… By T.VenkataSridhar , ETC
 Figure 1-43: MPC860 Thermal parameters Figure 1-44: Memory Hierarchy

Board Memory
❑ Embedded platforms can have a memory hierarchy, a collection of different
types of memory, each with unique speeds, sizes, and usages (see Figure 1-44).

❑ Some of this memory can be physically integrated on the processor, like registers
and certain types of primary memory, which is memory connected directly to or
integrated in the processor such as ROM, RAM, and level-1 cache.

103 By T.VenkataSridhar , ETC

❑ Now we will study memory that is typically located outside of the processor, or
that can both be either integrated into the processor or located outside the
processor.

❑ This includes other types of primary memory, such as ROM, level-2+ cache, and
main memory, and secondary/tertiary memory, which is memory that is connected
to the board but not the master processor directly, such as CD-ROM, floppy drives,
hard drives, tape, pen drive memory, SD card, Flash Drives, and external Hard
discs.
Primary memory is typically a part of a memory subsystem (shown in Figure 5-2)
made up of three components:

• The memory IC.

• An address bus.
• A data bus.

In general, a memory IC is made up of three units: the memory array, the address
decoder, and the data interface.

104 By T.VenkataSridhar , ETC

 The locations of each of
the cells within the
two-dimensional memory
array are commonly
referred to as the physical
memory addresses, made up
of the column and row
parameters.

Memory ICs that can

connect to a board come in
a variety of packages,
depending on the type
Figure 1-45: Hardware primary memory subsystem. of memory.

Types of packages include

• Single in-line packages (SIPs)
• Dual in-line packages (DIPs),
• Single in-line memory modules (SIMMs), and
• Dual in-line memory modules (DIMMs). As shown in figure 1-46.
105 By T.VenkataSridhar , ETC
 Figure 1-46a:
SIP Example

Figure 1-46d:
Figure 1-46b: Figure 1-46c:
168-pin DIMM example
DIP Example 30-pin SIMM Example.
106 By T.VenkataSridhar , ETC
 ROM
ROM is a type of non-volatile
memory that can be used to
store data on an embedded
system permanently, typically
through a smaller on-board
battery source that is separate
from the board’s main power
source. The type of data stored
on ROM in an embedded
system is (at the very least) the
software required by the device
to function in the field after
being shipped out of the
factory. The contents of ROM
can typically only be read by
the master processor; however,
depending on the type of ROM,
Figure 1-47: the master processor may or
8 × 8 ROM logic circuit.
may not be able to erase or
107 modify the By data located , ETC
T.VenkataSridhar in
❑ The circuit in Figure 1-47 includes three address lines ( ) for all eight
words, meaning the 3-bit addresses ranging from 000 to 111 each represent one
of the 8 bytes.

(Note: Different ROM designs can include a wide variety of addressing

configurations for the exact same matrix size, and this addressing scheme is just
an example of one such scheme.)

❑ D0–D7 are the output lines from which data is read—one output line for each
bit. Adding additional rows to the ROM matrix increases its size in terms of the
number of address spaces, whereas adding additional columns increases a
ROM’s data size, or the number of bits per address it can store.

❑ In this example, the 8 × 8 ROM is an 8 × 8 matrix, meaning it can store eight

different 8-bit words, or 64 bits of information.

❑ Every intersection of a row and column in this matrix is a memory location,

called a memory cell. Each memory cell can contain either a bipolar or MOSFET
transistor (depending on the type of ROM) and a fusible link (see Figure 1-48).

108 By T.VenkataSridhar , ETC

 Figure 1-47: 8 × 8 MOSFET and bipolar memory cells
The most common types of ROM used on embedded boards are:
❑ Mask ROM (MROM or ROM). Data bits are permanently programmed into a microchip
by the manufacturer of the external MROM chip. MROM designs are usually based upon
MOS (NMOS, CMOS) or bipolar transistor-based circuitry.
❑ This was the original type of ROM design. Because of expensive setup costs for a
manufacturer of MROMs, it is usually only produced in high volumes and there is a wait
time of several weeks to several months. However, using MROMs in design of products is a
cheaper solution.
❑ One-Time Programmable ROM (OTP or OTPRom or PROM). This type of ROM can
only be programmed (permanently) one time as its name implies, but it can be programmed
outside the manufacturing factory, using a ROM burner. OTPs are based upon bipolar
transistors, in which the ROM burner burns out fuses of cells to program them to “1” using
high voltage/current pulses.
109 By T.VenkataSridhar , ETC
❑ Erasable Programmable ROM (EPROM). An EPROM can be erased more than
one time using a device that outputs intense short-wavelength, ultraviolet light into
the EPROM package’s built-in transparent window. (OTPs are one-time
programmable EPROMs without the window to allow for erasure; the packaging
without the window used in OTPs is cheaper.)

❑ EPROMs are made up of MOS (i.e., CMOS, NMOS) transistors whose extra
“floating gate” (gate capacitance) is electrically charged, and the charge trapped, to
store a “0” by the Romizer (memory programmer) through “avalanche induced
migration”—a method in which a high voltage is used to expose the floating gate.

❑ The floating gate is made up of a conductor floating within the insulator, which
allows enough of a current flow to allow for electrons to be trapped within the gate,
with the insulator of that gate preventing electron leakage.

❑ The floating gates are discharged via UV light, to store a “1” for instance. This is
because the high-energy photons emitted by UV light provide enough energy for
electrons to escape the insulating portion of the floating gate.

❑ Electrically Erasable Programmable ROM (EEPROM). Like EPROM,

EEPROMs can be erased and reprogrammed more than once. The number of times
erasure and reuse occur depends on the EEPROMs.
110 By T.VenkataSridhar , ETC
❑ Unlike EPROMs, the content of EEPROM can be written and erased “in bytes”
without using any special devices. In other words, the EEPROM can stay on its
residing board, and the user can connect to the board interface to access and
modify an EEPROM.

❑ EEPROMs are based upon NMOS transistor circuitry, except insulation of the
floating gate in an EEPROM is thinner than that of the EPROM, and the method
used to charge the floating gates is called the Fowler–Nordheim tunneling method
(in which the electrons are trapped by passing through the thinnest section of the
insulating material).

❑ Erasing an EEPROM which has been programmed electrically is a matter of

using a high-reverse polarity voltage to release the trapped electrons within the
floating gate. Electronically discharging an EEPROM can be tricky, though, in
that any physical defects in the transistor gates can result in an EEPROM not
being discharged completely before a new reprogram.

❑ EEPROMs typically have more erase/write cycles than EPROMs, but are also
usually more expensive. A cheaper and faster variation of the EEPROM is Flash
memory.
111 By T.VenkataSridhar , ETC
 RAM
❑ With RAM, commonly referred to as main memory, any location within it can be
accessed directly and randomly, rather than sequentially from some starting point,
and its content can be changed more than once—the number of times depending on
the hardware.

❑ Unlike ROM, contents of RAM are erased if the board loses power, meaning
RAM is volatile.

❑ The two main types of RAM are static RAM (SRAM) and dynamic RAM
(DRAM).
❑ As shown in Figure 1-48, SRAM memory cells are made up of transistor-based
flip-flop circuitry that typically holds its data, due to a moving current being
switched bidirectionally on a pair of inverting gates in the circuit, until power is
cut off or the data is overwritten.
❑ To get a clearer understanding of
how SRAM works, let us examine a
sample logic circuit of 4 K × 8 SRAM
shown in Figure 1-48b. DRAM in
Figure 1-50.
112 Figure 1-48a: Six-transistor SRAM cell, DRAM cell.
 In this example, the 4 K × 8 SRAM is a 4
K × 8 matrix, meaning it can store 4096 (4
× 1024) different 8-bit bytes, or 32 768
bits of information. As shown in Figure
1-48b, 12 address lines (A0–A11) are
needed to address all 4096
(000000000000b– 111111111111b)
possible addresses—one address line for
every address digit of the address. There
are eight input and output lines
(D0–D7)—a byte for every byte stored at
an address.
There are also CS (chip
select) and WE (write
enable) input signals to
indicate whether the
data pins are enabled
(CS) and to indicate

whether the operation is

a READ or WRITE
operation (WE),
respectively. And their
timings are defined in
Figure 1-49.

Figure 1-48b: 4 K × 8 SRAM logic circuit.

113 By T.VenkataSridhar , ETC
 Figure 1-49: SRAM timing diagram.

114 By T.VenkataSridhar , ETC

 Figure 1-50: 16 K × 8 DRAM logic circuit.
115 By T.VenkataSridhar , ETC
 Figure 1-51a:
DRAM read timing diagram.

Figure 1-51b:
DRAM write timing diagram.

116 By T.VenkataSridhar , ETC

 Level 2+ Caches
❑ Level 2+ (level 2 and higher) cache is the level of memory that exists between the
CPU and main memory in the memory hierarchy (see Figure 1-44: Memory
Hierarchy).

❑ The purpose of cache is to improve the performance of the memory system.

Basically, cache is used to store subsets of main memory that are used or accessed
often, capitalizing on the locality of reference and making main memory seem to
execute faster.

❑ Because cache holds copies of what is in main memory, it gives the illusion to the
master processor that it is operating from main memory even if actually operating
from cache.

As with any scheme, each of the cache schemes has its strengths and drawbacks.
Whereas the set associative and full associative schemes are slower than the direct
mapped, the direct mapped cache scheme runs into performance problems when
the block sizes get too big. On the flip side, the cache and full associative schemes
are less predictable than the direct mapped cache scheme, since their algorithms
are more complex.
117 By T.VenkataSridhar , ETC
 Finally, the actual cache swapping scheme is determined by the architecture. The
most common cache selection and replacement schemes include:
❑ Optimal, using future reference time, swapping out pages that won’t be used in
the near future.
❑ Least Recently Used (LRU), which swaps out pages that were used the least
recently.
❑ First In First Out (FIFO), another scheme that, as its name implies, swaps out
the pages that are the oldest, regardless of how often they are accessed in the
system. While a simpler algorithm then LRU, FIFO is much less efficient.
❑ Not Recently Used (NRU), which swaps out pages that were not used within a
certain time period.
❑ Second Chance, a FIFO scheme with a reference bit, if “0” will be swapped out
(a reference bit is set to “1” when access occurs, and reset to “0” after the check).
❑ Clock Paging, pages being replaced according to clock (how long they have
been in memory), in clock order, if they haven’t been accessed (a reference bit is
set to “1” when access occurs, and reset to “0” after the check).

118 By T.VenkataSridhar , ETC

 Auxiliary Memory

❑ Certain types of memory can be connected directly to the master processor, such
as RAM, ROM, and cache, while other types of memory, called secondary memory,
are connected to the master processor indirectly via another device.

❑ This type of memory, as shown in Figure 1-44: Memory Hierarchy, is the

external secondary memory and tertiary memory and is commonly referred to as
auxiliary or storage memory.

❑Auxiliary memory is typically non-volatile memory used to store larger amounts of

regular, archival, and/or backups of data, for longer periods of time to indefinitely.

❑ Auxiliary memory can only be accessed by a device that is plugged into an

embedded board, such as the disks in a hard drive, the CD via a CD-ROM, a floppy
disk via a floppy drive, or magnetic tape via a magnetic tape drive or Pendrive via
USB or SD card via memory slot etc.

❑ A few of these are shown in the figure 1-52.

119 By T.VenkataSridhar , ETC

 Figure 1-52 a: Sequential access tape drive.

Figure 1-52 b: Magnetic tape.

120 By T.VenkataSridhar , ETC

 Figure 1-52 c: Internals of hard drive.

Figure 1-52 e: CD

Figure 1-52 d: Hard drive

121
platter.
By T.VenkataSridhar , ETC
Memory Management of External Memory

❑ There are several different types of memory that can be integrated into a system,
and there are also differences in how software running on the CPU views
logical/virtual memory addresses and the actual physical memory addresses—the
two-dimensional array or row and column.
❑Memory managers are ICs designed to manage these issues. In some cases, they
are integrated onto the master processor.

The two most common types of memory managers found on an embedded board
are MEMCs and MMUs (Memory controller and Memory management unit
respectively).

A MEMC, shown in Figure 1-53, is used to implement and provide glueless

interfaces to the different types of memory in the system, such as SRAM and
DRAM, synchronizing access to memory and verifying the integrity of the data
being transferred. MEMCs access memory directly with the memory’s own
physical two-dimensional addresses.

122 By T.VenkataSridhar , ETC

 Figure 1-53: MEMC sample circuit

MMUs mainly allow for the flexibility in a system of having a larger virtual
memory (abstract) space within an actual smaller physical memory. An MMU,
shown in Figure 1-54, can exist outside the master processor and is used to
translate logical (virtual) addresses into physical addresses (memory mapping), as
well as handle memory security (memory protection), controlling cache, handling
bus arbitration between the CPU and memory, and generating appropriate
exceptions.
123 By T.VenkataSridhar , ETC
 Figure 1-54: Motorola/Freescale M68020 external memory management.

Board Memory and Performance

❑ One of the most common measures of a processor’s performance is its
throughput (bandwidth), or the CPU’s average execution rate.

❑ The performance throughput can be negatively impacted by main memory

especially, since the DRAM used for main memory can have a much lower
bandwidth than that of the processors.

❑ There are specific timing parameters associated with memory (memory access
times, refresh cycle times for DRAM, etc.) that act as indicators of memory
performance.
124 By T.VenkataSridhar , ETC
 Solutions for improving the bandwidth of main memory include:

❑ Integrating a Harvard-based architecture, with separate instruction and data

memory buffers and ports, for systems that expect to perform a high number of
memory accesses and computations on a large amount of data.

❑ Using DRAMs, such as DRDRAM and SLDRAM, that integrate bus signals
into one line, to decrease the time it takes to arbitrate the memory bus to access
memory.

❑ Using more memory interface connections (pins), increasing transfer bandwidth.

❑ Using a higher signalling rate on memory interface connections (pins).

❑ Implementing a memory hierarchy with multiple levels of cache, which has

faster memory access times than those of other types of memory.

Approaches to Embedded Systems:

All the above specified designs with a proper application software are the best
approach for an Embedded System design (SSI, MSI, LSI, VLSI so on).
125 By T.VenkataSridhar , ETC
 Small Microcontrollers
A microprocessor contains a complete digital processor, which includes at
least the arithmetic logic unit and associated registers. The earliest devices, such
as the Intel 4004 and Texas Instruments’ TMS1000, were introduced at the
beginning of the 1970s. Their breathtaking evolution since then has been toward
increasing computational power and complexity. They are also more powerful in
an electrical sense. Large, modern microprocessors need huge heat sinks and fans
and can draw over 100A of current.
The reduction of power dissipation is a major thrust of current development,
now that so many microprocessors are used in portable equipment, whose battery
should last for as long as possible. A microprocessor needs many other
components to support it. These include a (large) external memory and the other
components that can be found on the motherboard of a personal computer.
It was realized from the start that microprocessors would also be useful to
control electronic equipment, such as photocopiers. Here the emphasis was less on
computational power; the drive was more to reduce the complexity of the
hardware and increase reliability. The trend was therefore to integrate as many
functions as possible on to the same chip as the processor. This gave rise to the
microcontroller (MCU or C), which typically contains all of the functions needed
126 to make a complete computer system, including memory. By T.VenkataSridhar , ETC
 Figure :
Essential components
of a microcontroller.

127 By T.VenkataSridhar , ETC

128 By T.VenkataSridhar , ETC
129 By T.VenkataSridhar , ETC
 These are used to download the program into the MCU and communicate with a desktop
computer during development.

The processor communicates with these peripherals by reading from, and writing to,
particular addresses in memory.

These memory locations are called special function registers or peripheral registers to
distinguish them from ordinary memories, which simply store data, but exactly the same
commands are used—no special commands are needed.

In practice, microcontrollers spend much of their time handling the peripheral registers.
This shows the central role of memory in a microcontroller.
130 By T.VenkataSridhar , ETC
 MSP430
The MSP430 is a mixed-signal microcontroller family from Texas
Instruments, first introduced on 14 February 1992. Built around a 16-bit CPU,
the MSP430 was designed for use with low power consumption embedded
applications and for low cost.
In summary, it is a particularly straightforward 16-bit processor with a von
Neumann architecture, designed for low-power applications.

The CPU is often described as a reduced instruction set computer (RISC).

A wide range of peripherals is available, many of which can run autonomously

without the CPU for most of the time.

Many portable devices include liquid crystal displays, which the MSP430 can
drive directly.

Some MSP430 devices are classed as application-specific standard products

(ASSPs) and contain specialized analog hardware for various types of
measurement.
131 By T.VenkataSridhar , ETC
 Currently four families of MSP430 are available. Most part numbers include F for
flash memory but some have C for ROM.

MSP430x1xx: Provides a wide range of general-purpose devices from simple

versions to complete systems for processing signals. There is a broad selection of
peripherals and some include a hardware multiplier, which can be used as a
rudimentary digital signal processor. Packages have 20–64 pins.

MSP430F2xx: A newer, general-purpose family introduced in 2005. Its CPU can

run at 16 MHz, double the speed of earlier devices, while consuming only half the
current at the same speed. Some come in 14-pin packages, including a traditional
plastic dual-in-line (PDIP) option, which is attractive for anybody who has to build
circuits by hand. They do not require a crystal for their low-frequency clock.
Pull-up or pull-down resistors are provided on the inputs to reduce the number of
external components needed. There are many options for analog inputs. Even the
smallest, 14-pin devices offer a 16-bit sigma–delta ADC.

MSP430x3xx: The original family, which includes drivers for LCDs. It is now
obsolescent.
132 By T.VenkataSridhar , ETC
 MSP430x4xx: Can drive LCDs with up to 160 segments. Many of them are
ASSPs, but there are general-purpose devices as well. Their packages have
48–113 pins, many of which are needed for the LCD.

MSP430X: The original MSP430 architecture, extended to give the MSP430X

in 2006, mainly so that it can address extra memory but with other
improvements as well.

Curiously, this is not marketed as a separate family: The devices are included in
the MSP430F2xx and MSP430F4xx families with nothing in their part number
to distinguish them. The CPU is a MSP430x if there is more than 64KB of
memory.

The letters MSP stand for mixed signal processor, which

is a reminder that many practical applications require
analog inputs. There is a selection of analog-to-digital
converters with a resolution of up to 16 bits.
133 By T.VenkataSridhar , ETC
 The Texas Instruments MSP430

Pin-Out
The pin-out shows which interior functions are connected to each pin of the
package.

There are several diagrams for each device, corresponding to the different
packages in which it is produced.

The F2013 is available in a traditional 14-pin plastic dual-in-line package (PDIP)

with pins 0.1 apart, which is a boon for hobbyists and students—a device that is
large enough to solder easily by hand.

There is also a plastic small-outline thin package (TSSOP). This has a similar
shape but is a surface-mount device with pins 0.65mm (about 0.025) apart.

A general warning: Packages with the same shape do not always have the same
pin-out.

134 By T.VenkataSridhar , ETC

 The pin-out for the PDIP and TSSOP packages is shown in Figure below.

Perhaps the most obvious feature is that almost all pins have several functions.

This is typical of a modern, small microcontroller.

Silicon is cheap but pins are expensive.

The aim is therefore to integrate as many functions into as small a package as

possible.

Most applications do not use all the peripherals so, with luck, there is no conflict
where a design needs more than one function on a pin simultaneously.

135 By T.VenkataSridhar , ETC

 Figure : Pin-out of the
MSP430F2003 and F2013.

136 By T.VenkataSridhar , ETC

137 By T.VenkataSridhar , ETC
138 By T.VenkataSridhar , ETC
 MSP430 Features:
The MSP430 is a 16-bit microcontroller that has a number of special features not
commonly available with other microcontrollers:
Complete system on-a-chip — includes LCD control, ADC, I/O ports, ROM,
RAM, basic timer, watchdog timer, UART, etc.
Extremely low power consumption — only 4.2 nW per instruction, typical.
High speed — 300 ns per instruction @ 3.3 MHz clock, in register and register
addressing mode.
RISC structure — 27 core instructions.
Orthogonal architecture (any instruction with any addressing mode)
Seven addressing modes for the source operand.
Four addressing modes for the destination operand.
Constant generator for the most often used constants (–1, 0, 1, 2, 4, 8).
Only one external crystal required — a frequency locked loop (FLL) oscillator
derives all internal clocks.
Full real-time capability — stable, nominal system clock frequency is available
after only six clocks when the MSP430 is restored from low-power mode (LPM) 3;
— no waiting for the main crystal to begin oscillation and stabilize
The 27 core instructions combined with these special features make it easy to
program the MSP430 in assembler or in C, and provide exceptional flexibility and
139functionality. By T.VenkataSridhar , ETC
 Functional Block Diagram

140 By T.VenkataSridhar , ETC

 Architecture of the MSP430 Processor
Memory
The memory address bus is 16 bits wide so there are 216 = 65,536 = 64K =
0x10000 addresses. The first address is 0, like arrays in C, so the range is 0x0000
to 0xFFFF although not all these may be meaningful in a particular device.

The memory data bus is 16 bits wide and can transfer either a word of 16 bits or a
byte of 8 bits. Bytes may be accessed at any address but words need more care.
The address of a word is defined to be the address of the byte with the lower
address, which must be even.

An important case is that instructions are composed of words and must therefore
lie on even addresses.

Figure: Ordering of
bits, bytes, and
words in memory.

141 By T.VenkataSridhar , ETC

 Suppose that a word contains the hexadecimal value 0x1234. Its more significant
(high-order) byte is 0x12 and the less significant (low-order) byte is 0x34.

There are two ways in which these two bytes can be stored in the two bytes of a
word in memory and both are in use.

Little-endian ordering: The low-order byte is stored at the lower address and the
high-order byte at the higher address. This is used by the MSP430 and is the more
common format.

Big-endian ordering: The high-order byte is stored at the lower address. This is
used by the Freescale HCS08, for instance.

Memory Map
Figure below shows the memory map of the F2013. Maps are sometimes drawn
with addresses increasing up the page, as one would normally draw the vertical
axis on a graph. Most MSP430 devices have a similar memory map, differing only
in the size of the regions for RAM and code.

142 By T.VenkataSridhar , ETC

 Figure: Memory map
of the MSP430F2013.
Gray regions are
unused and their size
varies considerably
between
devices. The F2013
does not have a
bootstrap loader but
have shown its
location because it is
present in most
variants of the
MSP430.

143 By T.VenkataSridhar , ETC

 Here is a brief description of each region:
Special function registers: Mostly concerned with enabling functions of some
modules and enabling and signalling interrupts from peripherals.

Peripheral registers with byte access and peripheral registers with word
access: Provide the main communication between the CPU and peripherals. Some
must be accessed as words and others as bytes. They are grouped in this way to
avoid wasting addresses. If the bytes and words were mixed, numerous unused
bytes would be needed to ensure that the words were correctly aligned on even
addresses.

Random access memory: Used for variables. This always starts at address
0x0200 and the upper limit depends on the size of the RAM. The F2013 has 128
B.

Bootstrap loader: Contains a program to communicate using a standard serial

protocol, often with the COM port of a PC. This can be used to program the chip
but improvements in other methods of communication have made it less important
than in the past, particularly for development. All MSP430s had a bootstrap loader
until the F20xx, from which it was omitted to improve security.
144 By T.VenkataSridhar , ETC
 Information memory: A 256B block of flash memory that is intended for storage
of Non-volatile data.

Code memory: Holds the program, including the executable code itself and any
constant data. The F2013 has 2KB but the F2003 only 1KB.

Interrupt and reset vectors: Used to handle “exceptions,” when normal

operation of the processor is interrupted or when the device is reset. This table
was smaller and started at 0xFFE0 in earlier devices.

Central Processing Unit

The central processing unit (CPU) executes the instructions stored in memory. It
steps through the instructions in the sequence in which they are stored in memory
until it encounters a branch or when an exception occurs (interrupt or reset).

It includes the arithmetic logic unit (ALU), which performs computation, a set of
16 registers designated R0–R15 and the logic needed to decode the instructions
and implement them. The CPU can run at a maximum clock frequency fMCLK of
16MHz in the MSP430F2xx family and some newer MSP430x4xx devices, and
8MHz in the others.
145 By T.VenkataSridhar , ETC
 Figure: Registers in the CPU of the MSP430.

Program counter, PC: This contains the address of the next instruction to be
executed, “points to” the instruction in the usual jargon. Instructions are composed
of 1–3 words, which must be aligned to even addresses, so the lsb of the PC is
hard-wired to 0.

Stack pointer, SP: When a subroutine is called, the CPU jumps to the subroutine,
executes the code there, then returns to the instruction after the call. It must
therefore keep track of the contents of the PC before jumping to the subroutine, so
that it can return afterward. This is the primary purpose of the stack.
146 By T.VenkataSridhar , ETC
147 By T.VenkataSridhar , ETC
 Status register, SR: This contains a set of flags (single bits).

Constant generator: This provides the six most frequently used values so that they
need not be fetched from memory whenever they are needed. It uses both R2 and
R3 to provide a range of useful values by exploiting the CPU’s addressing modes.

General purpose registers: The remaining 12 registers, R4–R15, are general

working registers. They may be used for either data or addresses because both are
16-bit values, which simplifies the operation significantly.

Memory-Mapped Input and Output

Simple digital input and output takes place through sets of pins on the package of
the integrated circuit called ports. Each port has up to 8 pins although not all may
be available in a particular package.
Many manufacturers label the ports with letters but TI uses numbers and the ports
are called P1, P2, and so on (there is no P0 in current devices).
For example, the F2013 has all pins of port P1 available, labelled P1.0–P1.7, but
only pins P2.6 and P2.7 of port P2.
148 By T.VenkataSridhar , ETC
 Clock Generator
Clocks for microcontrollers used to be simple.

• A fast clock to drive the CPU, which can be started and stopped rapidly to
conserve energy but usually need not be particularly accurate.

• A slow clock that runs continuously to monitor real time, which must therefore
use little power and may need to be accurate.

Crystal: Accurate (the frequency is close to what it says on the can, typically
within 1 part in 105) and stable (does not change greatly with time or temperature).
Crystals for microcontrollers typically run at either a high frequency of a few MHz
to drive the main bus or a low frequency of 32,768 Hz for a real-time clock.

The MSP430 addresses the conflicting demands for high performance, low power,
and a precise frequency by using three internal clocks, which can be derived from
up to four sources. These are the internal clocks, which are the same in all devices:

• Master clock, MCLK, is used by the CPU and a few peripherals.

• Subsystem master clock, SMCLK, is distributed to peripherals.
149
• Auxiliary clock, ACLK, is also distributed to peripherals.
By T.VenkataSridhar , ETC
 Exceptions: Interrupts and Resets
Execution of a program usually proceeds predictably, but there are two classes
of exception to this rule: interrupts and resets:

Interrupts: Usually generated by hardware (although they can be initiated by

software) and often indicate that an event has occurred that needs an urgent
response.

Resets: Again usually generated by hardware, either when power is applied or

when something catastrophic has happened and normal operation cannot
continue. This can happen accidentally if the watchdog timer has not been
disabled, which is easy to forget. A reset causes the device to (re)start from a
well-defined state.

Addressing Modes
A key feature of any CPU is its range of addressing modes, the ways in which
operands can be specified.

The MSP430 has four basic modes for the source but only two for the destination
in instructions with two operands.
150 By T.VenkataSridhar , ETC
 All 16 of these are treated on an almost equal basis, including the four
special-purpose registers.

An instruction itself fits into a single word of 16 bits, although it may be followed
by further words to provide addresses or an immediate value.

There are three formats of instruction of TI’s standard abbreviations of src for
source and dst for destination. It is important to distinguish between these because
the destination has fewer addressing modes.

Double operand (Format I): Arithmetic and logical operations with two operands
such as add.w src, dst, which is the equivalent of dst += src in C.

Single operand (Format II): A mixture of instructions for control or to

manipulate a single operand, which is effectively the source for the addressing
modes.

Jumps: The jump to the destination rather than its absolute address, in other words
the offset that must be added to the program counter.

The “return from interrupt” instruction reti is unique in requiring no operands.

151 By T.VenkataSridhar , ETC
 1. Register Mode
This uses one or two of the registers in the CPU. It is the most straightforward
addressing mode and is available for both source and destination. For example,

152 By T.VenkataSridhar , ETC

 2. Indexed Mode
This looks much like an element of an array in C. The address is formed by adding
a constant base address to the contents of a CPU register; the value in the register
is not changed. Indexed addressing can be used for both source and destination.
For example, suppose that R5 contains the value 4 before this instruction:

Symbolic Mode (PC Relative)

In this case the program counter PC is used as the base address, so the constant is
the offset to the data from the PC.
For example, suppose that a program uses the variable LoopCtr, which occupies a
word. The following instruction stores the value of LoopCtr in R6 using symbolic
mode:
153 By T.VenkataSridhar , ETC
 Absolute Mode

The constant in this form of indexed addressing is the absolute address of the data.
This is already the complete address required so it should be added to a register that
contains 0.

Absolute addressing is shown by the prefix & and should be used for special
function and peripheral registers, whose addresses are fixed in the memory map.

This example copies the port 1 input register into register R6:

154 By T.VenkataSridhar , ETC

 SP-Relative Mode

For example, suppose that the stack were as (shown in stack Figure) with
SP=0x027C. Then the preceding instruction would load 0x1234 into R6.

3. Indirect Register Mode

This is available only for the source and is shown by the symbol @ in front of a
register, such as @R5. It means that the contents of R5 are used as the address of
the operand. In other words, R5 holds a pointer rather than a value.

155 By T.VenkataSridhar , ETC

 Suppose that R5 contains the value 4 before this instruction:

4. Indirect Auto-increment Register Mode

Again this is available only for the source and is shown by the symbol @ in front
of a register with a + sign after it, such as @R5+. It uses the value in R5 as a
pointer and automatically increments it afterward by 1 if a byte has been fetched
or by 2 for a word. Suppose yet again that R5 contains the value 4 before this
instruction:
156 By T.VenkataSridhar , ETC
 Immediate Mode
This is a special case of auto-increment addressing that uses the program counter
PC. Look at this example:

The PC is automatically incremented after the instruction is fetched and

therefore points to the following word. The instruction loads this word into R6
and increments PC to point to the next word, which in this case is the next
instruction.
157 By T.VenkataSridhar , ETC
 Constant Generator and Emulated Instructions
Constant Generator (CG):
A complex instruction set computer (CISC) has special instructions for
performing many common operations.

For example, there may be a “clear” operation to reset a register to 0 and an

“increment” operation to increase its value by 1.

In contrast, a reduced instruction set computer (RISC) uses general instructions

for these operations. Instead of clearing a register it stores 0 into it, in the same
way as it would store any other number. Similarly, it increments a value by using
the standard addition instruction to add 1.

This could require commonly used values like 0 and 1 to be stored frequently in
the code, which would be wasteful of both memory and time because the values
would have to be fetched from memory whenever they were needed.

To improve efficiency, most RISCs therefore have one or more registers that are
“hardwired” to commonly used values.
158 By T.VenkataSridhar , ETC
 Typically there is only one value per register but the designers of the MSP430
cleverly exploited its four addressing modes for a source to get four values from
its dedicated constant generator R3/CG2.
The status register R2/SR/CG1 can be read and written almost normally in
Register mode. It therefore acts as constant generator CG1 when it is used as a
source in the other three addressing modes.
Thus seven constants are available from the two registers. These provide the base
of 0 for absolute addressing, and the six immediate values 0, 1, 2, 4, 8, and
0xFFFF=−1 for signed values.

Emulated Instructions (EI):

These constants are combined with many of the 27 native instructions to provide
a further 24 emulated instructions. They can be written in the same way as “real”
instructions and the assembler converts them to native instructions with the
appropriate constant from CG1 or CG2.

A problem with this approach is that the constants can be used only as the source.
Do not attempt to use any of the constant generators as a destination.
159 By T.VenkataSridhar , ETC
 Instruction Set
The MSP430 has 27 native instructions, and a further 24 emulated instructions are
defined to make coding easier for the programmer.

These include common operations such as “clear,” which is implemented as an

ordinary move with a value of 0 provided by the constant generator.

The instruction set is orthogonal with few exceptions, meaning that all addressing
modes can be used with all instructions and registers.

It show the .w form for operations that can use either bytes or words.

The general syntax of writing the instruction is as follows.

Instruction [Space] src ,dst ; Comment.

Assembler is case insensitive, but C compiler is case sensitive.

160 By T.VenkataSridhar , ETC

 Movement Instructions

Stack Operations
These push data onto the stack and pop them off.

161 By T.VenkataSridhar , ETC

 The compare operation cmp is the same as subtraction sub except that only the
bits in SR are affected; the result is not written back to the destination.

162 By T.VenkataSridhar , ETC

 Decimal Arithmetic

These instructions are used when operands are binary-coded decimal (BCD) rather
than ordinary binary values.

This means that the value of each nibble is restricted to the range of unsigned,
decimal integers 0–9 instead of the full hexadecimal range 0–F.

163 By T.VenkataSridhar , ETC

164 By T.VenkataSridhar , ETC
 Shift and Rotate Instructions
Processors often offer three types of shifts and rotations although the treatment of
the carry bit varies. They differ in the treatment of the bits that are shifted out of
and into the register.
165 By T.VenkataSridhar , ETC
Flow of Control
Subroutines, Interrupts, and Branches
These are mainly straightforward but there is a tricky point about addresses:
166 By T.VenkataSridhar , ETC
167 By T.VenkataSridhar , ETC
 Instruction Timing

The number of MCLK cycles required for most instructions is limited by access to
memory. This is a typical feature of a RISC-like CPU with a von Neumann
architecture and also applies to the ARM7, for instance.

168 By T.VenkataSridhar , ETC

169 By T.VenkataSridhar , ETC
 Illegal Operations
Fetching Data

Here are three possible illegal operations.

• Data can be fetched from a nonexistent address: empty regions of the memory
map. Execution proceeds as normal but the “fetched” value is random.

• Data for a word should be aligned to even addresses but you could attempt to
fetch a word from an odd address. I found that the lsb of the address was ignored
and the word was fetched from the resulting even address.

• A related case of this is the range of peripheral registers with word access. It
appears that the lsb of their addresses is ignored because they are intended to be
read only as words. It is possible to read the lower byte alone but not the upper
byte: An attempt to read the upper byte returns the lower byte instead.

Illegal Instructions

Instructions are 16-bit words in the MSP430 but not all 216 possible binary values
are used; roughly one eighth have no operations associated with them. The
instruction map is available at “RISC 16-bit CPU” in the family user’s guides.
170 By T.VenkataSridhar , ETC
 Examples
Copying Strings

The first example is based on the standard library function strcpy (destination,
source), which copies a null-terminated string from source to destination.

171 By T.VenkataSridhar , ETC

 Copying Blocks of Data
Part of program blockcpy1 , which copies a block of memory between fixed
addresses.

172 By T.VenkataSridhar , ETC

 Reflections on the CPU and Instruction Set

• Simplicity
• Registers of the CPU
• Is the MSP430 a RISC—and Should It Be?
* Small set of general-purpose instructions:
* Large bank of general-purpose registers:
* Load–store architecture:
* Single-cycle execution:
• Addressing Modes
• Instruction Set

173 By T.VenkataSridhar , ETC

 Resets

A reset is a sequence of operations that puts the device into a well-defined

state, from which the user’s program may start.

This is obviously necessary when power is first applied. A reset is also

generated if the device detects a serious fault in hardware or software from
which the user’s program cannot be expected to recover.

174 By T.VenkataSridhar , ETC

 Conditions after Reset

The initial conditions for all registers and peripherals after a POR and PUC are
specified in the family user’s guides.
175 By T.VenkataSridhar , ETC
 It is important to identify the source of a reset when debugging. No single register
holds all the relevant flags but most are in the interrupt flag register 1, IFG1. This
may contain the following flags, depending on the variant:

• WDTIFG shows that the watchdog timed out or its security key was violated.
• OFIFG indicates an oscillator fault (this causes a nonmaskable interrupt, not a
reset).
• RSTIFG shows a reset caused by a signal on the RST/NMI pin.
• PORIFG is set for a power-on reset.
• NMIIFG flags a nonmaskable interrupt (not reset) caused by a signal on the
RST/NMI pin.

Clock System
All microcontrollers contain a clock module to drive the CPU and peripherals.
Figure below shows a simplified diagram of the Basic Clock Module+ (BCM+)
for the MSP430F2xx family.
176 By T.VenkataSridhar , ETC
177 By T.VenkataSridhar , ETC
178 By T.VenkataSridhar , ETC
 Functions, Interrupts, and Low-Power Modes
A well-structured program should be divided into separate modules—functions in
C or subroutines in assembly language. There is nothing special about this in
embedded systems.

Interrupts are a major feature of most embedded software. They are vaguely like
functions that are called by hardware rather than software. The distinction sounds
trivial but it makes them much harder to handle because the processor must be
able to return correctly to its activity before it was interrupted.

The low-power modes of operation: they are described here because the MSP430
needs an interrupt to wake it from a low-power mode. In fact we see that no extra
effort is usually needed to handle low-power modes in interrupts:

The MSP430 automatically goes to active mode when an interrupt is requested,

services the interrupt, and resumes its low-power mode afterward.

179 By T.VenkataSridhar , ETC

 Functions and Subroutines

It is good practice to break programs into short functions or subroutines.

It makes programs easier to write and more reliable to test and maintain.

Functions are obviously useful for code that is called from more than one place
but should be used much more widely, to encapsulate every distinct function.

They hide the detailed implementation of an activity from the high-level,

strategic level of the software.

Functions can readily be reused and incorporated into libraries, provided that
their documentation is clear.
What Happens when a Subroutine Is Called?

The basic operation of subroutines in assembly language are studied earlier.

To recap briefly, the call instruction first causes the return address, which is the
current value in the PC, to be pushed on to the stack.
180 By T.VenkataSridhar , ETC
 The address of the subroutine is then loaded into the PC and execution continues
from there.

At the end of the subroutine the ret instruction pops the return address off the stack
into the PC so that execution resumes with the instruction following the call of the
subroutine.

Storage for Local Variables

Most functions need local variables and there are three ways in which space for
these can be allocated:

CPU registers are simple and fast and is done by pushing their values on to the
stack.

A second approach is to use a fixed location in RAM.

The third approach is to allocate variables on the stack and is generally used
when a program has run out of CPU registers.

181 By T.VenkataSridhar , ETC

 Listing below shows the delay subroutine which saves and restores R4 before
using it as a loop counter within the subroutine. The operation of the stack when
the subroutine is called is illustrated in Figure below.

182 By T.VenkataSridhar , ETC

 Subroutine from substk1, whose delay loop uses two local variables on the stack.

183 By T.VenkataSridhar , ETC

 Passing Parameters to a Subroutine and Returning a Result

184 By T.VenkataSridhar , ETC

185 By T.VenkataSridhar , ETC
 Mixing C and Assembly Language

Most programs are now written in C but it is occasionally worthwhile to write parts
of the code in assembly language. This can be done in several ways, described in
the reference guide for the EW430 C compiler and in the application note Mixing C
and Assembler with the MSP430. It is not complicated in principle but there are
plenty of pitfalls.

Check first to see whether an intrinsic function is available to do the job without
leaving C. Many of these are declared in the header file intrinsics.h to perform
functions that are not possible in standard C. For example, the _ _swap_bytes()
intrinsic function calls the swpb instruction.

Another possibility, when only a line or two of assembly language is needed, is to

use inline assembly. This looks like a function asm() whose argument is the line(s)
of assembly code, such as asm ("mov.b &P1IN,&dest“) approach, set out in the
compiler reference guide.

The third method is to write a complete subroutine in assembly language and call it
from C. Obviously it is essential to get the calling convention correct.
186 By T.VenkataSridhar , ETC
 Interrupts
Interrupts are like functions but with the critical distinction that they are requested
by hardware at unpredictable times rather than called by software in an orderly
manner.
A periodic interrupt should be highly predictable in real time, but this is not
apparent to the CPU. Interrupts are commonly used for a range of applications:

187 By T.VenkataSridhar , ETC

 What Happens when an Interrupt Is Requested?
A lengthy chain of operations lies between the cause of a maskable interrupt and
the start of its ISR. It starts when a flag bit is set in the module when the
condition for an interrupt occurs.

188 By T.VenkataSridhar , ETC

 Interrupt Service Routines
Interrupt Service Routines in Assembly Language

189 By T.VenkataSridhar , ETC

 Program timrint1, in assembly language to toggle LEDs using interrupts generated by
timer_A in up mode.

190 By T.VenkataSridhar , ETC

 Low-Power Modes of Operation
The MSP430 was designed from the outset for low power and this is reflected in a range of
low-power modes of operation. There are five in all but two are rarely employed in current
devices (they were useful with earlier versions of the DCO).

191 By T.VenkataSridhar , ETC

 End of Module-1

192
By T.VenkataSridhar , ETC
 Further Refer
Systems Architecture: A Comprehensive Guide for
Engineers and Programmers (Elsevier(Singapore) Pvt.Ltd.Publications, 2005)

By
Tammy Noergaard

MSP430 Microcontroller Basics (Elsevier Ltd Publications, Copyright 2008)

By
John H. Davies

193
UP
By T.VenkataSridhar , ETC