SOLOMON SYSTECH

SEMICONDUCTOR TECHNICAL DATA

SSD2832

Advanced Information

MIPI C&D-PHY TX Bridge Chip

This document contains information on a new product. Specifications and information herein are subject to change
without notice.

http://www.solomon-systech.com
SSD2832 Rev 1.5 P 1/178 Aug. 2020 Copyright  2020 Solomon Systech Limited
APPENDIX: IC REVISION HISTORY OF SSD2832 SPECIFICATION

Version Change Items Effective Date

1.0 1st Release 22-Sep-2017
1.1 1. Modified the following pin assignment 18-Oct-2017
H19 changed from NC to VSS
H20 changed from NC to VSS
B14 changed from NC to Data0_12
H18 changed from HSYNC2 to NC
A1 changed from HSYNC3 to NC
H8 changed from VSYNC3 to NC
D22 changed from VSYNC 2 to NC
K16 changed from DEN2 to NC
E6 changed from DEN3 to NC
A2 changed from PCLK3 to NC
E10 changed from PCLK2 to NC
H2 changed from DATA0_60 to NC
H1 changed from DATA0_61 to NC
J3 changed fromDATA0_62 to NC
K2 changed from DATA0_63 to NC
N1 changed from CSX1 to NC
2. changed TX0_B1 to TXA_B1
1.2 1. Added 4 lane mode in 0xDE 02-Mar-2018
2. Revised 0xBA bit[15:14] from PEN to FR
3. Added mipi timing description on local(APB) register CPHY_TX_GR1
4. Added mipi timing description on local(APB) register CPHY_TX_GR4
5. Added mipi timing description on local(APB) register CPHY_TX_GR5
6. Added 0xC9
7. Added 0xCA
8. Added 0xCB
9. Added 0xCC
10. Added 0xCD
11. Added 0xCE
1.3 17-Jan-2019
1. Modified ball name of N16 from IF_SEL1 to VSS
1.4 1. Removed all information about quad-pixel 28-Mar-2019
2. Removed 0x22h and 0x32h packet type description
3. Modified power pin AVDD_CDR to AVDD
4. Corrected typo of 0xB7h register bit 6 description
5. Modified minimum horizontal porch values
6. Added note for COP usage
1.5 1. Corrected DCS command descriptions of 0x09, 0x19, 0x29 according to the 01-Sep-2020
MIPI Spec.
2. Removed the byte offset markings in VBist Mode description.
3. Added timing configuration equations for RGB input.
4. Corrected the LP clock calculation formula.
5. Rearranged section 5 functional description and section 15 application
reference.
6. Corrected the “Color Order” register description.

Solomon Systech Aug. 2020 2/178 Rev 1.5 SSD2832

CONTENTS

1 GENERAL DESCRIPTION ............................................................................................ 9

2 FEATURES........................................................................................................................ 9
2.1 GENERAL ................................................................................................................................................. 9
3 ORDERING INFORMATION ...................................................................................... 10
4 BLOCK DIAGRAM ....................................................................................................... 11
5 FUNCTIONAL DESCRIPTION ................................................................................... 12
5.1 RGB INTERFACE ................................................................................................................................... 12
5.2 COMMAND INTERFACE .......................................................................................................................... 12
5.2.1 SPI Interface ................................................................................................................................. 13
5.2.2 MCU Interface .............................................................................................................................. 17
5.3 DATA BUFFER ....................................................................................................................................... 25
5.4 COMMAND BUFFER ............................................................................................................................... 25
5.5 MIPI DSI-TX ........................................................................................................................................ 25
5.5.1 PHY controller .............................................................................................................................. 28
5.5.2 Contention Detection and Timer Operation ................................................................................. 28
5.6 XTAL OSC ........................................................................................................................................... 29
5.6.1 Clock Source Example .................................................................................................................. 29
5.7 PLL ....................................................................................................................................................... 30
5.8 PMU ..................................................................................................................................................... 31
5.9 PIXEL PEEK ........................................................................................................................................... 31
5.10 IMAGE FLIPPING (HORIZONTAL) ............................................................................................................ 32
6 PIN ARRAGEMENT ...................................................................................................... 33
7 POWER SUPPLY PIN ................................................................................................... 39
7.1 POWER SUPPLY PIN ............................................................................................................................... 39
7.2 MIPI PIN ............................................................................................................................................... 39
7.3 CONTROL SIGNAL PIN ........................................................................................................................... 40
7.4 INTERFACE LOGIC PIN ........................................................................................................................... 41
8 COMMAND TABLE ...................................................................................................... 43
8.1 LOCAL REGISTERS (NON-APB) DESCRIPTIONS ...................................................................................... 43
8.1.1 RGB Interface Control Register 1 ................................................................................................. 43
8.1.2 RGB Interface Control Register 2 ................................................................................................. 44
8.1.3 RGB Interface Control Register 3 ................................................................................................. 46
8.1.4 RGB Interface Control Register 4 ................................................................................................. 47
8.1.5 RGB Interface Control Register 5 ................................................................................................. 48
8.1.6 RGB Interface Control Register 6 ................................................................................................. 49
8.1.7 Configuration Register ................................................................................................................. 52
8.1.8 Virtual Channel Control Register ................................................................................................. 55
8.1.9 PLL Control Register .................................................................................................................... 56
8.1.10 PLL Configuration Register .......................................................................................................... 57
8.1.11 Clock Control Register ................................................................................................................. 58
8.1.12 Packet Size Control Register 1 ..................................................................................................... 59
8.1.13 Packet Size Control Register 2 ..................................................................................................... 61
8.1.14 Packet Size Control Register 3 ..................................................................................................... 62
8.1.15 Packet Drop Register .................................................................................................................... 63
8.1.16 Operational Control Register ....................................................................................................... 64
8.1.17 Maximum Return Size Register ..................................................................................................... 65
8.1.18 Return Data Count Register.......................................................................................................... 66
8.1.19 Acknowledge Response Status Register ........................................................................................ 67

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 8.1.20 Line Control Register.................................................................................................................... 68
8.1.21 Interrupt Control Register ............................................................................................................ 71
8.1.22 Interrupt Status Register ............................................................................................................... 74
8.1.23 Error Status Register .................................................................................................................... 78
8.1.24 Delay Adjustment Register 1 ......................................................................................................... 81
8.1.25 Delay Adjustment Register 2 ......................................................................................................... 82
8.1.26 Delay Adjustment Register 3 ......................................................................................................... 83
8.1.27 Delay Adjustment Register 4 ......................................................................................................... 84
8.1.28 Delay Adjustment Register 5 ......................................................................................................... 85
8.1.29 Delay Adjustment Register 6 ......................................................................................................... 86
8.1.30 HS TX Timer Register 1 ................................................................................................................ 87
8.1.31 HS TX Timer Register 2 ................................................................................................................ 88
8.1.32 TE Status Register ......................................................................................................................... 89
8.1.33 SPI Read Register ......................................................................................................................... 91
8.1.34 PLL Lock Register ........................................................................................................................ 92
8.1.35 Test Register ................................................................................................................................. 93
8.1.36 TE Count Register......................................................................................................................... 95
8.1.37 Analog Control Register 1 ............................................................................................................ 96
8.1.38 RGB Interface Control Register 7 ................................................................................................. 98
8.1.39 INOUT Configuration Control Register ..................................................................................... 100
8.1.40 APB Write Register ..................................................................................................................... 102
8.1.41 APB Read Register...................................................................................................................... 103
8.2 LOCAL (APB) REGISTER DESCRIPTIONS .............................................................................................. 104
8.2.1 SCM Registers Descriptions ....................................................................................................... 105
8.2.2 CPHY Analog Front End Registers Descriptions ....................................................................... 109
8.2.3 Video BIST Register Descriptions .............................................................................................. 117
8.2.4 Pixel Peek Registers Descriptions .............................................................................................. 124
9 MAXIMUM RATING .................................................................................................. 128
10 DC OPERATION CONDICTION .............................................................................. 129
10.1 DC CHARACTERISTIC .................................................................................................................... 130
11 AC CHARACTERISTIC ............................................................................................. 131
11.1 POWER UP TIMING .............................................................................................................................. 131
11.2 RESET TIMING ................................................................................................................................... 131
11.3 INTERFACE TIMING.............................................................................................................................. 131
11.3.1 MCU Interface (Type A) Timing ................................................................................................. 131
11.3.2 MCU Interface (Type B) Timing ................................................................................................. 133
11.3.3 SPI Interface Timing ................................................................................................................... 135
11.3.4 RGB Interface Timing ................................................................................................................. 136
12 POWER UP SEQUENCE ............................................................................................ 137
13 POWER OFF SEQUENCE .......................................................................................... 138
14 MIPI CHARACTERISTIC .......................................................................................... 139
14.1 MIPI CPHY CHARACTERISTIC...................................................................................................... 139
14.1.1 MIPI CPHY HS CHARACTERISTICS ........................................................................................ 140
14.1.2 MIPI CPHY LP CHARACTERISTICS ........................................................................................ 141
14.2 MIPI DPHY CHARACTERISTIC ..................................................................................................... 143
14.21 MIPI DPHY HS CHARACTERISTICS ........................................................................................ 145
15 APPLICATION REFERENCE ................................................................................... 148
15.1 CONTROLLING AND PROGRAMMING .................................................................................................... 148
15.1.1 Access Local (non-APB) Registers ............................................................................................. 149
15.1.2 Access Local (APB) Registers for Write ..................................................................................... 150
15.1.3 Access Local (APB) Registers for Read ...................................................................................... 152
15.2 VIDEO MODE USE CASES .................................................................................................................... 154

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 15.2.1 Interleaving Non-Video Packets with Video Packets .................................................................. 157
15.2.2 Video Bandwidth Consideration (RGB Parallel Interface) ........................................................ 157
15.3 COMMAND MODE USE CASES ............................................................................................................. 159
15.3.1 Programming Sequence .............................................................................................................. 160
15.3.2 Partition Mode ............................................................................................................................ 161
15.4 VIDEO TO COMMAND MODE................................................................................................................ 162
15.4.1 Example of switching sequence .................................................................................................. 163
15.5 MIPI PACKET CONTROL ...................................................................................................................... 163
15.5.1 Write Operation .......................................................................................................................... 164
15.5.2 Read Operation ........................................................................................................................... 165
15.5.3 Internal Buffer Status .................................................................................................................. 166
15.6 INTERRUPT OPERATION ....................................................................................................................... 168
15.7 STATE MACHINE OPERATION ............................................................................................................... 170
15.8 ACKNOWLEDGEMENT OPERATION....................................................................................................... 170
15.9 TEARING EFFECT (TE) OPERATION ..................................................................................................... 172
15.9.1 Using IO Pins ............................................................................................................................. 172
15.9.2 Using MIPI Escape Mode ........................................................................................................... 172
15.10 VIDEO BIST ........................................................................................................................................ 173
16 PACKAGE INFORMATION ...................................................................................... 177
16.1 373 BALLS TFBGA ............................................................................................................................... 177

SSD2832 Rev 1.5 5/178 Aug. 2020 Solomon Systech

TABLES

TABLE 3-1: ORDERING INFORMATION ................................................................................................................... 10

TABLE 5-1 SSD2832 RGB DATA ARRANGEMENT ................................................................................................. 12
TABLE 5-2: MCU INTERFACE DATA PIN MAPPING FOR COMMAND CYCLE .......................................................... 22
TABLE 5-3: MCU INTERFACE DATA PIN MAPPING FOR PARAMETER CYCLES ...................................................... 22
TABLE 5-4: COMMAND ADDRESS TO ENABLE MCU SWAP .................................................................................... 23
TABLE 5-5: COMMAND DATA TO ENABLE MCU SWAP 2’B11 ............................................................................... 24
TABLE 5-6: DSI-TX SUPPORT FORMAT................................................................................................................. 27
TABLE 7-1: POWER SUPPLY PIN DESCRIPTION ...................................................................................................... 39
TABLE 7-2: MIPIRX PIN DESCRIPTION ................................................................................................................. 39
TABLE 7-3: MIPI PIN DESCRIPTION....................................................................................................................... 40
TABLE 7-4: CONTROL SIGNAL PIN DESCRIPTION .................................................................................................. 41
TABLE 7-5: MCU/RGB INTERFACE DESCRIPTION ................................................................................................ 42
TABLE 7-6: SPI INTERFACE DESCRIPTION ............................................................................................................. 42
TABLE 8-1: RGB INTERFACE CONTROL REGISTER 1 DESCRIPTION ....................................................................... 43
TABLE 8-2: RGB INTERFACE CONTROL REGISTER 2 DESCRIPTION ....................................................................... 44
TABLE 8-3: RGB INTERFACE CONTROL REGISTER 3 DESCRIPTION ....................................................................... 46
TABLE 8-4: RGB INTERFACE CONTROL REGISTER 4 DESCRIPTION ....................................................................... 47
TABLE 8-5: RGB INTERFACE CONTROL REGISTER 5 DESCRIPTION ....................................................................... 48
TABLE 8-6: RGB INTERFACE CONTROL REGISTER 6 DESCRIPTION ....................................................................... 49
TABLE 8-7: CONFIGURATION REGISTER DESCRIPTION .......................................................................................... 52
TABLE 8-8: VIRTUAL CHANNEL CONTROL REGISTER DESCRIPTION ..................................................................... 55
TABLE 8-9: PLL CONTROL REGISTER DESCRIPTION ............................................................................................. 56
TABLE 8-10: PLL CONFIGURATION REGISTER DESCRIPTION ................................................................................ 57
TABLE 8-11: CLOCK CONTROL REGISTER DESCRIPTION ....................................................................................... 58
TABLE 8-12: PACKET SIZE REGISTER 1 DESCRIPTION ........................................................................................... 59
TABLE 8-13: PACKET SIZE REGISTER 2 DESCRIPTION ........................................................................................... 61
TABLE 8-14: PACKET SIZE REGISTER 3 DESCRIPTION ........................................................................................... 62
TABLE 8-15: PACKET DROP REGISTER DESCRIPTION ............................................................................................ 63
TABLE 8-16: OPERATIONAL CONTROL REGISTER DESCRIPTION ............................................................................ 64
TABLE 8-17: MAXIMUM RETURN SIZE REGISTER DESCRIPTION ............................................................................ 65
TABLE 8-18: RETURN DATA COUNT REGISTER DESCRIPTION ............................................................................... 66
TABLE 8-19: ACKNOWLEDGE RESPONSE STATUS REGISTER DESCRIPTION ........................................................... 67
TABLE 8-20: LINE CONTROL REGISTER DESCRIPTION ........................................................................................... 68
TABLE 8-21: INTERRUPT CONTROL REGISTER DESCRIPTION ................................................................................. 71
TABLE 8-22: INTERRUPT STATUS REGISTER DESCRIPTION .................................................................................... 74
TABLE 8-23: ERROR STATUS REGISTER DESCRIPTION .......................................................................................... 78
TABLE 8-24: DELAY ADJUSTMENT REGISTER 1 DESCRIPTION............................................................................... 81
TABLE 8-25: DELAY ADJUSTMENT REGISTER 2 DESCRIPTION............................................................................... 82
TABLE 8-26: DELAY ADJUSTMENT REGISTER 3 DESCRIPTION............................................................................... 83
TABLE 8-27: DELAY ADJUSTMENT REGISTER 4 DESCRIPTION............................................................................... 84
TABLE 8-28: DELAY ADJUSTMENT REGISTER 5 DESCRIPTION............................................................................... 85
TABLE 8-29: DELAY ADJUSTMENT REGISTER 6 DESCRIPTION............................................................................... 86
TABLE 8-30: HS TX TIMER REGISTER 1 DESCRIPTION .......................................................................................... 87
TABLE 8-31: HS TX TIMER REGISTER 2 DESCRIPTION .......................................................................................... 88
TABLE 8-32: TE STATUS REGISTER DESCRIPTION ................................................................................................. 89
TABLE 8-33: SPI READ REGISTER DESCRIPTION ................................................................................................... 91
TABLE 8-34: PLL LOCK REGISTER DESCRIPTION .................................................................................................. 92
TABLE 8-35: TEST REGISTER DESCRIPTION ........................................................................................................... 93
TABLE 8-36: TE COUNT REGISTER DESCRIPTION .................................................................................................. 95
TABLE 8-37: ANALOG CONTROL REGISTER 1 DESCRIPTION .................................................................................. 96
TABLE 8-38: RGB INTERFACE CONTROL REGISTER 7 DESCRIPTION ..................................................................... 98
TABLE 8-39: INOUT CONFIGURATION REGISTER DESCRIPTION ......................................................................... 100
TABLE 8-40: DELAY ADJUSTMENT REGISTER DESCRIPTION ............................................................................... 102
TABLE 8-41: APB READ REGISTER DESCRIPTION ............................................................................................... 103
TABLE 8-42: DEVICE IDENTIFICATION REGISTER DESCRIPTION .......................................................................... 105
TABLE 8-43: SCM MISCELLANEOUS CONTROL DESCRIPTION ............................................................................. 106
TABLE 8-44: SCM SCRATCH REGISTER DESCRIPTION......................................................................................... 108

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TABLE 8-45: CPHY TX GLOBAL REGISTER 1 DESCRIPTION ............................................................................... 109
TABLE 8-46: CPHY TX GLOBAL REGISTER 2 DESCRIPTION ............................................................................... 111
TABLE 8-47: CPHY TX GLOBAL REGISTER 3 DESCRIPTION ............................................................................... 112
TABLE 8-48: CPHY TX GLOBAL REGISTER 4 DESCRIPTION ............................................................................... 113
TABLE 8-49: CPHY TRANSMIT GLOBAL REGISTER 5 DESCRIPTION .................................................................... 114
TABLE 8-50: VIDEO BIST REGISTER 0 DESCRIPTION .......................................................................................... 117
TABLE 8-51: VIDEO BIST REGISTER 1 DESCRIPTION .......................................................................................... 118
TABLE 8-52: VIDEO BIST REGISTER 2 DESCRIPTION .......................................................................................... 119
TABLE 8-53: VIDEO BIST REGISTER 3 DESCRIPTION .......................................................................................... 120
TABLE 8-54: VIDEO BIST REGISTER 4 DESCRIPTION .......................................................................................... 121
TABLE 8-55: VIDEO BIST REGISTER 5 DESCRIPTION .......................................................................................... 122
TABLE 8-56: VIDEO BIST REGISTER 6 DESCRIPTION .......................................................................................... 123
TABLE 8-57: PIXEL PEEK REGISTER 0 DESCRIPTION ........................................................................................... 124
TABLE 8-58: PIXEL PEEK REGISTER 1 DESCRIPTION ........................................................................................... 125
TABLE 8-59: PIXEL PEEK REGISTER 2 DESCRIPTION ........................................................................................... 126
TABLE 8-60: PIXEL PEEK REGISTER 3 DESCRIPTION ........................................................................................... 127
TABLE 9-1: MAXIMUM RATING (VOLTAGE REFERENCED TO VSS) ...................................................................... 128
TABLE 10-1 : RECOMMENDED OPERATING CONDITIONS ..................................................................................... 129
TABLE 11-1 MCU INTERFACE (TYPE A) TIMING CHARACTERISTICS .................................................................. 131
TABLE 11-2: MCU INTERFACE (TYPE B) TIMING CHARACTERISTICS ................................................................. 133
TABLE 11-3 RGB INTERFACE TIMING CHARACTERISTICS ................................................................................... 136
TABLE 14-1 HS TRANSMITTER DC SPECIFICATIONS ........................................................................................... 140
TABLE 14-2 HS TRANSMITTER AC SPECIFICATIONS ........................................................................................... 141
TABLE 14-3 LP TRANSMITTER DC SPECIFICATIONS ........................................................................................... 141
TABLE 14-4 LP TRANSMITTER AC SPECIFICATIONS ........................................................................................... 142
TABLE 14-5 : CLOCK SIGNAL SPECIFICATION ...................................................................................................... 144
TABLE 14-6 HS TRANSMITTER DC SPECIFICATIONS ........................................................................................... 145
TABLE 14-7 HS TRANSMITTER AC SPECIFICATIONS ........................................................................................... 145
TABLE 14-8 LP TRANSMITTER DC SPECIFICATIONS ........................................................................................... 146
TABLE 14-9 LP TRANSMITTER AC SPECIFICATIONS ........................................................................................... 147
TABLE 15-1: MCU INTERFACE DATA PIN MAPPING FOR COMMAND CYCLE FOR LEGACY REGISTERS ............... 149
TABLE 15-2: MCU INTERFACE DATA PIN MAPPING FOR LEGACY REGISTER ...................................................... 149
TABLE 15-3: MCU INTERFACE DATA PIN MAPPING FOR COMMAND CYCLE FOR EXTENDED REGISTERS WRITE 150
TABLE 15-4: MCU INTERFACE DATA PIN MAPPING FOR EXTENDED REGISTERS WRITE .................................... 150
TABLE 15-5: MCU INTERFACE DATA PIN MAPPING FOR EXTENDED REGISTERS ADDRESS SET 1 ...................... 152
TABLE 15-6: MCU INTERFACE DATA PIN MAPPING FOR EXTENDED REGISTERS ADDRESS SET 2 ...................... 152
TABLE 15-7: MCU INTERFACE DATA PIN MAPPING FOR EXTENDED REGISTERS DATA READ 1 ......................... 152
TABLE 15-8: MCU INTERFACE DATA PIN MAPPING FOR EXTENDED REGISTERS DATA READ 2 ......................... 153
TABLE 15-9 VIDEO BIST MODE 0 ....................................................................................................................... 173
TABLE 15-10 VIDEO BIST MODE 1 & 2 .............................................................................................................. 173
TABLE 15-11 VIDEO BIST MODE 3 ..................................................................................................................... 174
TABLE 15-12 VIDEO BIST MODE 4 & 5 .............................................................................................................. 174
TABLE 15-13 VIDEO BIST MODE 6 ..................................................................................................................... 174
TABLE 15-14 VIDEO BIST MODE 7 ..................................................................................................................... 175
TABLE 15-15 VIDEO BIST MODE 8 & 9 .............................................................................................................. 175
TABLE 15-16 VIDEO BIST MODE A .................................................................................................................... 175
TABLE 15-17 VIDEO BIST MODE B .................................................................................................................... 176
TABLE 15-18 VIDEO BIST MODE C ................................................................................................................... 176
TABLE 15-19 VIDEO BIST MODE D & E ............................................................................................................. 176
TABLE 15-20 VIDEO BIST MODE F ..................................................................................................................... 176

SSD2832 Rev 1.5 7/178 Aug. 2020 Solomon Systech

FIGURES
FIGURE 4-1: SSD2832 BLOCK DIAGRAM .............................................................................................................. 11
FIGURE 5-1: SPI INTERFACE 8-BIT 4 WIRE FOR WRITE ........................................................................................... 13
FIGURE 5-2: SPI INTERFACE 8-BIT 4 WIRE FOR READ............................................................................................. 14
FIGURE 5-3: SPI INTERFACE 8-BIT 3 WIRE FOR WRITE ........................................................................................... 15
FIGURE 5-4: SPI INTERFACE 8-BIT 3 WIRE FOR READ............................................................................................. 15
FIGURE 5-5: SPI INTERFACE 3-BIT 24 WIRE FOR WRITE ......................................................................................... 16
FIGURE 5-6: SPI INTERFACE 3-BIT 24 WIRE FOR READ........................................................................................... 17
FIGURE 5-7: ILLUSTRATION OF WRITE OPERATION FOR TYPE A, FIXED E MODE INTERFACE ............................... 18
FIGURE 5-8: ILLUSTRATION OF READ OPERATION FOR TYPE A, FIXED E MODE INTERFACE ................................. 19
FIGURE 5-9: ILLUSTRATION OF WRITE OPERATION FOR TYPE A, CLOCKED E MODE INTERFACE ......................... 19
FIGURE 5-10: ILLUSTRATION OF READ OPERATION FOR TYPE A, CLOCKED E MODE INTERFACE ......................... 20
FIGURE 5-11: ILLUSTRATION OF WRITE OPERATION FOR TYPE B INTERFACE ....................................................... 21
FIGURE 5-12: ILLUSTRATION OF READ OPERATION FOR TYPE B INTERFACE......................................................... 21
FIGURE 5-13 SSD2832 CLOCK DIAGRAM ............................................................................................................. 30
FIGURE 11-1 MCU INTERFACE (TYPE A) TIMING DIAGRAM ............................................................................... 132
FIGURE 11-2 SPI INTERFACE TIMING CHARACTERISTICS .................................................................................... 135
FIGURE 11-3: SPI INTERFACE TIMING DIAGRAM ................................................................................................ 135
FIGURE 11-4: RGB INTERFACE TIMING DIAGRAM .............................................................................................. 136
FIGURE 14-1C-PHY SIGNALING LEVELS ............................................................................................................ 139
FIGURE 14-2 D-PHY SIGNALING LEVELS ........................................................................................................... 143
FIGURE 14-3 DDR CLOCK DEFINITION ............................................................................................................... 143
FIGURE 15-1: ILLUSTRATION OF RGB INTERFACE PARAMETERS FOR NON-BURST MODE WITH SYNC PULSES ... 156
FIGURE 15-2: ILLUSTRATION OF RGB INTERFACE PARAMETERS FOR NON-BURST MODE WITH SYNC EVENTS AND
BURST MODE .............................................................................................................................................. 156
FIGURE 15-3: COMMAND USE CASE SEQUENCE WITH TDC < PST....................................................................... 160
FIGURE 15-4: COMMAND USE CASE SEQUENCE WITH TDC > PST....................................................................... 161
FIGURE 16-1: PACKAGE INFORMATION ............................................................................................................... 177

Solomon Systech Aug. 2020 8/178 Rev 1.5 SSD2832

1 GENERAL DESCRIPTION
SSD2832 is a MIPI master bridge chip that converts different input interfaces to MIPI DSI Output. It
connects directly to the MIPI DSI receivers (both CPHY and DPHY supported).

For RGB interface, it can support resolution up to WQXGA (2560x1600) (native) and DCI 4K
(4096x2160) (compressed in/out) format with 60Hz refresh rate.
For MCU interface, it can support resolution up to WQXGA (2560x1600) (native) and DCI 4K
(4096x2160) (compressed in/out) format with 30Hz refresh rate.

2 FEATURES

2.1 General
 Support panel with resolution up to DCI 4K (4096 x 2160) at refresh rate of 60Hz;
 Support MIPI DSI-2 standard version 1.0 with either D-option or C-option for TX;
 Support MIPI C-PHY standard version 1.1;
 Support MIPI D-PHY standard version 1.1;
 Support MIPI DCS standard version 1.02;
 Support 2 MIPI C-option DSI engines with throughput up to 20.52Gbps using 6 C-PHY lanes
for each DSI-TX (Each lane is up to 1.5Gsps);
 Support 2 MIPI D-option DSI engines with throughput up to 12Gbps using 8 D-PHY lanes
for each DSI-TX (Each lane is up to 1.5Gbps);
 Support 16, 18, 24, 30 bits per pixel color at RGB input;
 Support 2 parallel MCU interface (DBI version 2.0) up to 48-bit bus width at the input;
 Support 2 parallel RGB interface (DPI version 2.0) up to 60-bit bus width with SDR or DDR
pixel clock at the input;
 Support serial SPI interface (DBI version 2.0) up to 16-bit data at the input;
 Support both Video and Command mode MIPI output;
 Support Video BIST pattern generation at the DSI-TX output with different color patterns;
 Support input Left-right or odd-even split at the RGB input;
 Support Burst or Non-burst video modes at DSI-TX;
 Number of lanes at each DSI-TX port can be controlled independently;
 On-chip PLL with variable output frequency;
 Power supply required: (VDD_CORE and AVDD) 1.3V +/-10%, (VCIP) 3.3V +/-10%;
 IO Power supply required : 1.8V and 3.3V +/-10%;

SSD2832 Rev 1.5 9/178 Aug. 2020 Solomon Systech

3 ORDERING INFORMATION
Table 3-1: Ordering Information
Ordering Part Number Package Form

SSD2832G24 BGA, 15x15

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 4 BLOCK DIAGRAM

xtal_in/
XTAL
out PLL
OSC

RGB
RGB Interface
RGB

DSI TX
0 (C)
MIPI
Data Buffer CPHY
DSI TX
MIPI 1 (C)
DSI
TX DSI TX
MCU Command 0 (D)
Command MIPI
Interface Buffer DPHY DSI TX
SPI
1 (D)

Local
Register

APB Master PMU

Figure 4-1: SSD2832 Block Diagram

SSD2832 Rev 1.5 11/178 Aug. 2020 Solomon Systech

5 FUNCTIONAL DESCRIPTION

5.1 RGB Interface

SSD2832 supports RGB interface with up to 2 pixels per PCLK cycle using SDR or DDR input pixel
clock.
To support different bpp settings, the following data pins are used. For all cases, Red component
should be at the higher bits and Blue component should be at the lower bits. The type of video packets
supported at RGB interface is shown below.

Data Bus RGB format

[15:0] 16 bits per pixel for Pixel 1
[45:30] 16 bits per pixel for Pixel 2
[17:0] 18 bits per pixel for Pixel 1
[47:30] 18 bits per pixel for Pixel 2
[23:0] 24 bits per pixel for Pixel 1
[53:30] 24 bits per pixel for Pixel 2
[29:0] 30 bits per pixel for Pixel 1
[59:30] 30 bits per pixel for Pixel 2
[23:0] Compressed Stream Data (lower)
[53:30] Compressed Stream Data (Higher)

Table 5-1 SSD2832 RGB data arrangement

D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

30bpp R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

24bpp X X X X X X R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0

18bpp X X X X X X X X X X X X R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0

16bpp X X X X X X X X X X X X X X R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0

SSD2832 will also monitor the status of CM and SHUT signal. When there is a change in these
signals, it will send out appropriate packets. On the rising edge of CM, the “CM on” packet will be
sent. On the falling edge of CM, the “CM off” packet will be sent. On the rising edge of SHUT, the
“Shut Down Peripheral” packet will be sent. On the falling edge of SHUT, the “Turn On Peripheral”
packet will be sent. With these packets, the MIPI receiver will be able to reconstruct the video signals.

User can also send command mode data through SPI interface, during the video mode transmission.
The data will be sent during the horizontal or vertical blanking period. Since the RGB and SPI interface
are completely separated, the two interfaces can operate independently. The RGB interface is used to
provide display data for the video mode. The SPI interface is used to program the local registers of
SSD2832, or to send command across the link to the MIPI receiver.

5.2 Command Interface

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The Command interface receives parallel MCU data or SPI data and routes them to the command
buffer. MCU interface supports 8, 16, 24 or 48-bit data width. The maximum speed for the MCU
interface is 160MHz.
Any write to the address ranges from 0x00 to 0xAF will be sent out as MIPI command packets. The
type of packet, whether it is short or long packet, DCS or generic packet is determined by the
SSD2832 local registers. Hence the user should program the local registers prior to any transmission
at the MIPI link.
If the host wants to send any addresses in the range of 0xB0 to 0xFF to external MIPI receiver, it can
do so using the 0xBF packet drop register.

5.2.1 SPI Interface

SSD2832 supports three types of SPI interface,
 8-bit 3 wire (type C option 1, DBI 2.0)
 8-bit 4 wire (type C option 3, DBI 2.0)
 24-bit 3 wire
The selection is controlled by PS[1:0] pins. For 8-Bit interface, the least significant byte should be
written first. For 24-bit interface, the lease significant word should be written first.

5.2.1.1 SPI Interface 8-Bit 4 Wire

This interface consists of sdcx, sck, sdin, sdout and csx. It only supports 8-Bit data. Each cycle
contains 8-Bit data. The first cycle should be a command write cycle to specify the register address to
access. The subsequent cycles are read or write cycles for read or write operations.
The csx should be driven from 1 to 0 to start an operation and from 0 to 1 to end an operation. During
the operation, the application processor can write or read multiple bytes.
Sdcx indicates whether the operation is for data or command. When sdcx is 1, the operation is for
data. When sdcx is 0, the operation is for command. sdcx is sampled at every 8th rising edge of sck
during 1 operation.
During write operation, sdin will be sampled by SSD2832 at the rising edge of sck. The first rising
edge of sck after the falling edge of csx samples the bit 7 of the 8-Bit data. The second rising edge of
sck samples the bit 6 of the 8-Bit data, and so on. The value of sdcx is sampled at the 8th rising edge of
sck, together with bit 0 of the 8-Bit data. Please see the diagram below for illustration. Optionally,
the csx can be driven to 1 in between cycles.

sdcx

sck
sdin D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

sdout

csx
Command Data Data
Write Cycle Write Cycle Write Cycle

Figure 5-1: SPI Interface 8-bit 4 wire for write

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 sdcx

sck
sdin A 7 A6 A 5 A 4 A3 A 2 A1 A0 1 1 1 1 1 0 1 0

sdout D7 D6 D 5 D 4 D3 D 2 D 1 D0 D 7 D 6 D5 D 4 D 3 D2 D 1 D 0

csx
Command Command Return Data 0 Return Data 1
Write Cycle Write Cycle Read Cycle Read Cycle
(Write the actual (Write special
address to read) Command(0xFA) to enter
read mode)
sdcx

sck
sdin 1 1 1 1 1 0 1 0

sdout D7 D6 D 5 D 4 D3 D 2 D 1 D0 D 7 D 6 D5 D 4 D 3 D2 D 1 D 0

csx
Command Return Data 2 Return Data 3
Write Cycle Read Cycle Read Cycle
(Write special
Command(0xFA) to enter
read mode)

Figure 5-2: SPI Interface 8-bit 4 wire for read

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5.2.1.2 SPI Interface 8-Bit 3 Wire

This interface consists of sck, sdin, sdout and csx. It only supports 8-Bit data. Each cycle contains 8-
Bit data. The first cycle should be a write cycle to specify the register address to access. The
subsequent cycles are read or write cycles for read or write operations.

The csx should be driven from 1 to 0 to start an operation and from 0 to 1 to end an operation. During
the operation, the application processor can write or read multiple bytes.

Instead of sdcx, an sdcx bit is used to indicate whether the operation is for data or command. Each
byte is associated with an sdcx bit at the start. When the sdcx bit is 1, the operation is for data. When
sdcx bit is 0, the operation is for command. The sdcx bit is sent prior to each data byte. In other
words, the sdcx bit is the first bit of every 9 bits during a cycle.

During write operation, sdin will be sampled by SSD2832 at the rising edge of sck. The first rising
edge of sck after the falling edge of csx samples the sdcx bit. The second rising edge samples bit 7 of
the 8-Bit data. The third rising edge of sck samples the bit 6 of the 8-Bit data, and so on. Please see
the diagram below for illustration. Optionally, the csx can be driven to 1 in between cycles.

sck

sdin 0 D7 D6 D5 D4 D3 D2 D1 D0 1 D7 D6 D5 D4 D3 D2 D1 D0 1 D7 D6 D5 D4 D3 D2 D1 D0

sdout

csx
Command Data Data
Write Cycle Write Cycle Write Cycle

Figure 5-3: SPI Interface 8-bit 3 wire for write

sck
sdin 0 A7 A6 A5 A4 A 3 A 2 A1 A0 0 1 1 1 1 1 0 1 0

sdout D 7 D 6 D5 D 4 D 3 D2 D1 D 0 D7 D6 D5 D4 D3 D 2 D 1 D0

csx
Command Command Return Data 0 Return Data 1
Write Cycle Write Cycle Read Cycle Read Cycle
(Write special
(Write the actual
Command(0xFA) to enter
address to read)
read mode)

sck
sdin 0 1 1 1 1 1 0 1 0

sdout D 7 D 6 D5 D 4 D3 D2 D1 D 0 D 7 D6 D 5 D 4 D3 D 2 D 1 D0

csx
Command Return Data 2 Return Data 3
Write Cycle Read Cycle Read Cycle
(Write special
Command(0xFA) to enter
read mode)

Figure 5-4: SPI Interface 8-bit 3 wire for read

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5.2.1.3 SPI Interface 24-Bit 3 Wire

This interface consists of sck, sdin, sdout and csx. It only supports 16-bit data. Each cycle contains
16-bit data. The first cycle should be a write cycle to specify the register address to access. The
subsequent cycles are read or write cycles for read or write operations.

The csx should be driven from 1 to 0 to start cycle and from 0 to 1 to end a cycle. During the
operation, the application processor can have multiple write or read cycles. However, the csx must go
from 0 to 1 at the end of each cycle.

Each cycle contains 24 bits. Among the 24 bits, the first 8 bits are for control and the next 16-bit are
the actual data. The first 6 bits are the ID bit for SSD2832, which must be 011100. If this field does
not match, the cycle will not be taken in. The 7th bit is the sdcx bit which is the same as the 8-Bit 3
wire interface. The 8th bit is the RW bit which indicates whether the current cycle is a read or write
cycle. When RW is 1, the cycle is a read cycle. When RW is 0, the cycle is a write cycle.

Note: User needs to de-assert CSX for read of every 16-bit data.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
sck

0 0 0 A0
sdin 0 1 1 1 0 0 0 0 0 0 0 0 0 A7 A6 A5 A4 A3 A2 A1
SDC RW

csx
First Transmission : Command Write Cycle

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
sck

D15 D14 D13 D12 D11 D10 D9 D4 D1 D0

sdin 0 1 1 1 0 0 1 0 D8 D7 D6 D5 D3 D2
SDC RW

csx
Second Transmission : Data Write Cycle

Figure 5-5: SPI Interface 3-bit 24 wire for write

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 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
sck

0 0 0 A0
sdin 0 1 1 1 0 0 0 0 0 0 0 0 0 A7 A6 A5 A4 A3 A2 A1
SDC RW

csx
First Transmission : Command Write Cycle

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
sck

sdin 0 1 1 1 0 0 1 1
SDC RW
sdout D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

csx
Second Transmission : Data Read Cycle

Figure 5-6: SPI Interface 3-bit 24 wire for read

5.2.2 MCU Interface

The SSD2832 supports three types of MCU interfaces,

 Type A, fixed E mode, DBI 2.0

 Type A, clocked E mode, DBI 2.0
 Type B, DBI 2.0
The selection is controlled by PS[4:2] pins.

PS[4:2] is for the MCU interface

 000: 8-bit MCU interface (MIPI DBI type B)
 001: 16-bit MCU interface (MIPI DBI type B)
 010: 8-bit MCU interface (MIPI DBI type A, fixed E or clocked E mode)
 011: 16-bit MCU interface (MIPI DBI type A, fixed E or clocked E mode)
 100: 24-bit MCU interface (MIPI DBI type B)
 110: 24-bit MCU interface (MIPI DBI type A, fixed E or clocked E mode)
 101: 48-bit MCU interface (MIPI DBI type B)
 111: 48-bit MCU interface (MIPI DBI type A, fixed E or clocked E mode)

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The interface supports 8-bit, 16-bit, 24-bit and 48-bit data bus. Below are the data pins used for each
interface. For 8-Bit interface, the least significant byte should be written first. For 16, 24, or 48-bit
interfaces, the lease significant word should be written first.

 data[7:0] for 8-bit interface

 data[15:0] for 16-bit interface
 data[23:0] for 24-bit interface
 data[47:0] for 48-bit interface

The local registers are always accessed in 16-bit data word for the data phase of the MCU cycle,
irrespective of any bus width selection.

5.2.2.1 MCU Interface Type A, fixed E mode

This interface consists of data, rwx, dcx, e and csx. It supports 48-bit, 24-bit, 16-bit and 8-bit data bus.
The first cycle should be a command write cycle to specify the register address to access. The
subsequent cycles are read or write cycles for read or write operations.
‘e’ signal should be driven to 1 in this mode.
rwx indicates whether the operation is a read or a write operation. When rwx is 1, the operation is a
read operation. When rwx is 0, the operation is a write operation.
During write operation, dcx indicates whether the operation is for data or command. When dcx is 1,
the operation is for data. When dcx is 0, the operation is for command. During the read operation,
the dcx should be 1.
During the write operation, data are sampled at the rising edge of csx. During read operation, data are
provided at the falling edge of csx and the application processor should use the rising edge of csx to
sample.

rwx

dcx

data Command Data Data

csx

Write Cycle Write Cycle Write Cycle

Figure 5-7: Illustration of Write Operation for Type A, Fixed E Mode Interface

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 rwx

dcx

data Command Return Data Return Data

csx

Write Cycle Read Cycle Read Cycle

Figure 5-8: Illustration of Read Operation for Type A, Fixed E Mode Interface

5.2.2.2 MCU Interface Type A, Clocked E Mode

This interface consists of data, rwx, dcx, e and csx. It supports 48-bit, 24-bit, 16-bit and 8-bit data
bus. The first cycle should be a command write cycle to specify the register address to access. The
subsequent cycles are read or write cycles for read or write operations.
csx should be driven to 0 in this mode.
rwx indicates whether the operation is a read or a write operation. When rwx is 0, the operation is a
write operation. When rwx is 1, the operation is a read operation.
During write operation, dcx indicates whether the operation is for data or command. When dcx is 1,
the operation is for data. When dcx is 0, the operation is for command. During the read operation,
the dcx should be 1.
During the write operation, data are sampled at the falling edge of E. During read operation, data are
provided at the rising edge of e and the application processor should use the falling edge of e to
sample.
Below is a diagram for illustration. Please see section 11 for the detailed waveform and timing
parameters.

rwx

dcx

data Command Data Data

csx

Write Cycle Write Cycle Write Cycle

Figure 5-9: Illustration of Write Operation for Type A, Clocked E Mode Interface

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 rwx

dcx

data[23:0] Command Return Data Return Data

csx

Write Cycle Read Cycle Read Cycle

Figure 5-10: Illustration of Read Operation for Type A, Clocked E Mode Interface

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5.2.2.3 MCU Interface Type B
This interface consists of data, rdx, wrx, dcx, and csx. It supports 48-bit, 24-bit, 16-bit and 8-bit data
bus. The first cycle should be a command write cycle to specify the register address to access. The
subsequent cycles are read or write cycles for read or write operations.
csx should be driven to 0 in this mode.
When wrx is driven from 1 to 0 and 0 to 1, the operation is a write operation. When rdx is driven from
1 to 0 and 0 to 1, the operation is a read operation.
During write operation, dcx indicates whether the operation is for data or command. When dcx is 1,
the operation is for data. When dcx is 0, the operation is for command. During the read operation, the
dcx should be 1.
During the write operation, data are sampled at the rising edge of wrx. During read operation, data
are provided at the falling edge of rdx and the application processor should use the rising edge of rdx
to sample.
Below is a diagram for illustration.

rdx

dcx

wrx

data Command Data Data

csx

Write Cycle Write Cycle Write Cycle

Figure 5-11: Illustration of Write Operation for Type B Interface

rdx

dcx

wrx

data Command Return Data Return Data

csx

Write Cycle Read Cycle Read Cycle

Figure 5-12: Illustration of Read Operation for Type B Interface

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5.2.2.4 MCU Interface for MIPI Command Packet

In the first write cycle, only 8-Bit data are written into the SSD2832, as the command can only be 8-
Bit. No matter whether the interface is 8-bit, 16-bit, 24-bit or 48-bit, lower 8-bits are used. Please
refer to the table below.

Interface Data pins

types
D47-D24 D23-D16 D15-D8 D7-D0
48-bit Don’t care Don’t care Don’t care Command
24-bit Don’t care Don’t care Don’t care Command
16-bit Don’t care Don’t care Don’t care Command
8-Bit Don’t care Don’t care Don’t care Command
Table 5-2: MCU Interface Data Pin Mapping for Command Cycle

In the sub-sequent read or write cycles, command parameters can be written into the SSD2832.
Depending on the interface width, different data pin mapping is adopted. Please refer to the table
below. When the number of parameters is not a multiple of the width of the data bus, the remaining
bytes should be put on the lower data buses at the next data cycle.

Interface Data pins

types Cycle
D47-D24 D23-D16 D15-D8 D7-D0
1st Parameter 4 to 6 Parameter 3 Parameter 2 Parameter 1

48-Bit 2nd Parameter 10 to 12 Parameter 9 Parameter 8 Parameter 7

3rd Parameter 16 to 18 Parameter 15 Parameter 14 Parameter 13
24-bit 1st Don’t care Parameter 3 Parameter 2 Parameter 1
2nd Don’t care Parameter 6 Parameter 5 Parameter 4
3rd Don’t care Parameter 9 Parameter 8 Parameter 7
16-bit 1st Don’t care Don’t care Parameter 2 Parameter 1
2nd Don’t care Don’t care Parameter 4 Parameter 3
3rd Don’t care Don’t care Parameter 6 Parameter 5
1st Don’t care Don’t care Don’t care Parameter 1

8-Bit 2nd Don’t care Don’t care Don’t care Parameter 2

3rd Don’t care Don’t care Don’t care Parameter 3
Table 5-3: MCU Interface Data Pin Mapping for Parameter Cycles

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5.2.2.5 MCU Initialization Sequence

When MCU interface is used (IF_SEL0==2’b1), the following initialization is recommended:

1. Host wait for 500us to ensure reset and OSC clock is ready.

2. Host shall configure to enable PLL using the command below:

Write to PLL Configuration Register (0xBA) to set ms/ns/fr for PLL.

Write to PLL Control Register (0xB9) to set PEN for PLL enable.
3. After PLL is enabled, host shall wait for 1ms for PLL to lock.

5.2.2.6 MCU Pin Swap Configuration

MCU Pin Swap configuration is supported using register in command table. The following steps
shall be performed to enable MCU pin swap:

1. Set MCU Swap mode bit to enable MCU Swap. This bit is located at bit 9-10 of In/out
Configuration Register 0xDE.

MCU Swap mode[0]

0 – No Swap for MCU0
1 –Swap MCU data from MSB to LSB for MCU0

MCU Swap mode[1]

0 – No Swap for MCU1
1 –Swap MCU data from MSB to LSB for MCU1

2. If MCU Data Bus is swapped from interface connectivity, host cannot do a normal
configuration but instead need to configure the register in swapped bit order. The special
command is described in tables below:

MCU Interface Type Command (actual =0xDE)

MCU 8-bit 8’h7B
MCU 16-bit 16’h7B00
MCU 24-bit 24’h7B_0000
MCU 48-bit 48’h7B00_0000_0000
Table 5-4: Command Address to enable MCU Swap

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 MCU Interface Type Command (actual =0x0600_0020)
MCU 8-bit 8’h04
8’h00
8’h00
8’h60
MCU 16-bit 16’h0400
16’h0060
MCU 24-bit 24’h04_0000
24’h00_6000
MCU 48-bit 48’h0400_0000_0000
48’h0060_0000_0000
Table 5-5: Command Data to enable MCU Swap 2’b11

3. After configuration, wait for minimum 6us to ensure that MCU Swap bit has taken effect. The
subsequent programming after step 2 does not require bit swap. The rest of the programming
sequence is same as normal MCU programming sequence.

5.2.2.7 MCU Programming Limitation

MCU has some programming limitation as below:
1. Before PLL is locked, SSD2832 cannot accept back-to-back MCU local register access. User
needs to have at least 2us in between register access before PLL is locked.
2. After PLL is locked, MCU external clock speed for internal register access be capped as
below:

Maximum MCU clk freq <= system_clock freq (refer to Clock Programming)

MCU external clock speed for sending external packet however does not have this limitation.
Refer to the bandwidth consideration on (4) below for maximum MCU clock frequency
calculation.

3. MCU external read clock freq should not be higher than system_clock freq /8, and with
additional delay of 150ns before reading first read-data.
4. When sending external MIPI DSI TX command using MCU, MCU external clock speed shall
fulfil the bandwidth consideration as below:

Bandwidth Requirement:

Bitrate input <= 90% of Bitrate output (capped at 160MHz)

Bitrate input = MCU clk freq * MCU bus width; MCU bus width: 8/16/24/48 bit depending
on PS setting

DPHY Mode:
Bitrate output = Total number of DPHY lanes * bitrate per lane,
where: bitrate per lane = bit clock frequency (refer to PLL and Clock Programming)

CPHY Mode:
Bitrate output = Total number of CPHY lanes * symbol rate per lane * 2.28,

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 where: symbol rate per lane = dual symbol clock frequency * 2 (refer to PLL and Clock
Programming)

Note:
The bandwidth consideration is always based on per single MCU and single DSI interface
because merge/split is not supported for MCU command mode.

Example of MCU external clock calculation:

Input : MCU 48-bit Type A Interface ( if_sel=2’b01, PS[4:2]=3’b111)
Output: DSI C-PHY 3 lanes (tx_ls0=2, test_mode[0]=1’b1, pll_clk_freq=500MHz)
Maximum MCU clk freq = ( 0.9 * pll_clk_freq * 2 * 2.28 * (tx_ls0+1)) / MCU bus width
= ( 0.9 * 500 * 2 * 2.28 * 3 )/48
= 128.25MHz

5.3 Data Buffer

The data buffer consists of line buffers to store one line worth of video data before packetizing them
for MIPI TX transmission. Data for command 0x2C and 0x3C also make use of the data buffer for
storage, instead of going to the command buffer.

There are one data buffer per MIPI DSI TX port. For DSI TX0, the data buffer size is 2560 pixels. For
DSI TX1, the size is 2064 pixels. Dual DSI TX port can support up to 2 x 2064 = 4128 pixels.

5.4 Command Buffer

The command buffer consist of a 4096-byte deep FIFO to store commands before packetizing them to
command packets for MIPI TX transmission. Command 0x2C and 0x3C are excluded in this command
buffer. They are routed to use data buffer instead.

There are one command FIFO per MIPI DSI TX port.

5.5 MIPI DSI-TX

MIPI DSI-TX is a dual DSI TX module, supporting up to 2 clock lanes, 8 data lanes for D-option and
up to 6 lanes for C-option.

Each DSI is capable of transferring up to 1.5Gbps per lane for D-option and 3.42Gbps (1.5Gsps) per
lane for C-option.

The main features of MIPI DSI-TX transmitter pairs are:

 Dual DSI-TX D-option up to 8 lanes;
 4 data lanes for each DSI-TX D-option;
 Dual DSI-TX C-option up to 6 lanes;
 3 lanes for each DSI-TX C-option;
 Support up to 2560 pixel/line for DSI0;
 Up to 1.5Gbps per lane for each D-option lane or 12Gbps for 2 DSI DPHY;
 Up to 3.42Gbps per lane for each C-option lane or 20.52Gbps for 2 DSI CPHY;
 Single or dual DSI mode;
 Support 16, 18, 24, 30-bit per pixel in video mode;

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  Support burst or non-burst mode;
 Support new commands in DSI-2, such as Execute Queue, Scrambler On/Off, Compressed
packets;
 Support MIPI Alliance Standard for Display Serial Interface-2, version 1.0
 Support MIPI Alliance Standard for Display Command Set, version 1.02
 Support MIPI Alliance Standard for D-PHY, version 1.1

The MIPI packets that are supported by MIPI DSI-TX are listed in the table below.
Packet ID Type Packet
0x01 Short Sync Event V Start
0x11 Short Sync Event V End
0x21 Short Sync Event H Start
0x31 Short Sync Event H End
0x08 Short End of Transmission
0x02 Short Color Mode(CM) Off
0x12 Short Color Mode(CM) On
0x03 Short Generic Short Write, no parameter
0x13 Short Generic Short Write, 1 parameter
0x23 Short Generic Short Write, 2 parameters
0x04 Short Generic Read, no parameter
0x14 Short Generic Read, 1 parameter
0x24 Short Generic Read, 2 parameters
0x05 Short DCS Short Write, no parameter
0x15 Short DCS Short Write, 1 parameter
0x06 Short DCS Read, no parameter
0x16 Short Execute Queue
0x37 Short Set Maximum Return Size
0x27 Short Scrambling Mode Command
0x09 Long Null Packet
0x19 Long Blanking Packet
0x29 Long Generic Long Write
0x39 Long DCS Long Write
0x0A Long Picture Parameter Set
0x0B Long Compressed Pixel Stream
0x0E Long Packed Pixel Stream, 16-bit RGB, 5-6-5 format
0x1E Long Packed Pixel Stream, 18-bit RGB, 6-6-6 format
0x2E Long Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6 format
0x3E Long Packed 24-bit RGB, 8-8-8 format
0x0D Long Packed 30-bit RGB, 10-10-10 format

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 0x02 Short Acknowledge and Error Report
0x11 Short Generic Short Read Response, 1 byte returned
0x21 Short Generic Short Read Response, 2 bytes returned
0x1A Long Generic Long Read Response
0x1C Long DCS Long Read Response
0x21 Short DCS Short Read Response, 1 byte returned
0x22 Short DCS Short Read Response, 2 bytes returned
Table 5-6: DSI-TX Support Format

MIPI DSI Link controller provides MIPI DSI packet assembly and disassembly. During transmission,
it will form the DSI packet according to the instruction from the state machine. During reception, it
will extract necessary information from the packet and pass to the higher level block. The MIPI DSI
Link Controller is also responsible for generating the CRC and ECC for the out-going bit stream.
During reception, it will check the correctness of the ECC and CRC field of the incoming stream.

When operated in 2-DSI mode, the MIPI DSI Link Controller is able to split the incoming video into
2 equal portions and send each half of the line to each of the MIPI DSI engines. Each MIPI DSI
engine take the half video data and reformat it into RGB 16/18/24/30 bpp packet and send out as 1
packet per line.

A data buffer is used to buffer a single video line from the upstream module and it will regenerate the
Video timing with the video settings stored inside the local registers. The output rate from the buffer
must be greater than the input rate to prevent data overflow.

MIPI DSI Link controller is also capable of sending DCS/Generic commands to external MIPI DSI
drivers via multiple sources.

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5.5.1 PHY controller

PHY-controller controls the operation of the analog transceiver. It controls whether the serial link is in
high speed or low power mode and whether it’s in transmit or receive mode.

In transmit mode, the PHY controller will perform the handshaking procedure when switching
between LP mode and HS mode according to the control from PCU. During HS mode, PHY
controller will provide parallel data and clock to the analog transmitter for transmitting in differential
signals serially. During LP mode, the PHY controller will provide the serial data to the analog
transmitter.

In receive mode, the PHY controller will detect the handshaking sequence in LP mode and inform the
PCU. Once entered escape mode, it will collect the serial data from analog receiver and put them in
parallel form for the PCU to process.

Various timing parameter has been defined in MIPI DPHY and CPHY specification. The timing
parameters are a mixture of absolute time and cycle counts. Hence, for different operation speed,
there is different timing requirement. The user can adjust the value in these registers to have different
DPHY timing parameters. This gives maximum flexibility for different operation speed.

5.5.2 Contention Detection and Timer Operation

Two timers have been defined in SSD2832 to resolve the potential contention issue on the bus. The
two timers are the HS TX timer and LP RX timer. Please see the register description for the detailed
usage.

Whenever the SSD2832 sees a contention being detected, it will reset the state machine and enter the
default mode, which is LP TX idle mode. The data line will be kept at LP11.

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 5.6 XTAL OSC

This is a crystal oscillator pad. From a circuit point of view, the crystal oscillator I/O cells are not real
oscillators, but amplifiers used to generate high quality clock signals. Full range configurable output
driving capability.

5.6.1 Clock Source Example

Pin Connection
XTAL_OUT Open

Solution 2

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 5.7 PLL

This is a PLL that can control the MIPI output frequency.

The clocks are programmed at 0xBA and 0xBB commands. The programming is mainly to set the bit
clock rate for each TX DPHY lane, or dual symbol clock for each TX CPHY lane. Note that the
bitrate for each TX CPHY lane is equivalent to (dual symbol clock * 2 * 2.28). Each “dual symbol
clock” would transmit 2 symbols, and each symbol can encode 2.28 bits (MIPI specifications states
that 7 symbols can be used to encode 16bit of data).

The clock programming also set the TLPX for DSI TX

The diagram below shows the clock tree and the programming model.

byp_bit_div (in command 0xBB)

PLL 1 DPHY: bit clock

0 CPHY: dual symbol clock
/2

/8 0 System_clock

/7 1
Divide by
((tx_lpd+1)*2) TX_LP_clock
CPHY mode
Divide by
((rx_lpd+1)*2) RX_LP_clock

Note:
TLPX (DSI TX) = 1 / 2*(FTX_LP_clock)

Figure 5-13 SSD2832 Clock Diagram

The PLL output frequency is calculated by the equations below,

f IN
f PRE 
MS
f OUT  f PRE * NS

where the f IN is the input reference clock frequency and f OUT is the output clock frequency of the
PLL.
The clock frequencies need to satisfy the constraint below.
8𝑀𝐻𝑧 < 𝑓𝐼𝑁 ≤ 40𝑀𝐻𝑧
8𝑀𝐻𝑧 < 𝑓𝑅𝐸𝐹 ≤ 100𝑀𝐻𝑧
62.5𝑀𝐻𝑧 < 𝑓𝑂𝑈𝑇 ≤ 1500𝑀𝐻𝑧

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The value of FR, MS, and NS are controlled in the register PCR.
All the values of FR, MS and NS can only be modified when the PLL is turned off (PEN=0). Hence,
the sequence for modification is to turn off PLL, modify register value, and turn on PLL.

5.8 PMU
The PMU (Power Management Unit) is responsible for putting SSD2832 into deep-sleep mode,
cutting the power consumption to ultra-low level. Internally, it uses APB interface for register
programming

5.9 Pixel Peek

SSD2832 supports pixel peek, which is allows user to peek at the pixel value on a programmable
pixel location in the video frame. The pixel location can be configured to be marked out on the screen
(through SSD2832 MIPI TX output) through a cursor (example shown below).

Note:
Pixel peek can only be supported for the following modes:

For single RGB0 input and 2 DSI_TX output(1 to 2)

RICR6.RGB_PACK_SEQ = 1: Left/Right split. pixel[0] to pixel[n/2-1] on DSI_TX0, pixel[n/2] to pixel[n-1] on
DSI_TX1.

 The cursor shown

crosses at the (x,y)
location programmed by
the user.
 The cursor is
programmed to be
visible, with ‘blue’color.
 The actual pixel value of
the location is stored in
the register for user to
read-back

Please refer to Pixel Peek Registers Descriptions for the related registers for this feature.

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5.10 Image Flipping (Horizontal)
Each of the dual MIPI TX can be configured to perform horizontal flip independently of each other.
For example:

No Flip Left: Flip

Right: Flip

Left: Flip Left: No Flip

Right: No Flip Right: Flip

Solomon Systech Aug. 2020 32/178 Rev 1.5 SSD2832

6 PIN ARRAGEMENT
TFBGA 373 15*15*1.1P0.65B12

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Pin Assignment
Ball number Pin Name Ball number Pin Name
AB1 NC Y4 NC
AB2 NC Y5 NC
AB3 NC Y6 AVDD
AB4 NC Y8 TXB_A2/TXB_DP0
AB5 AVDD Y9 TXB_C0/TXB_DP1
AB7 AVDD Y11 VSS
AB8 TXB_C1/TXB_CN Y12 AVDD_RC
AB10 TXB_A1/TXB_DN1 Y14 TXA_C2/TXA_DP3
AB11 VDRV Y15 TXA_DN3
AB13 AVDD Y17 AVDD
AB14 VDRV_REG Y18 TXA_B1/TXA_CP
AB16 NC Y20 NC
AB18 NC Y21 NC
AB19 VDRV Y22 VSS
AB21 VSS W1 NC
AB22 NC W2 NC
AA1 AVDD W3 NC
AA3 NC W6 NC
AA4 NC W8 NC
AA5 NC W9 NC
AA6 NC W11 NC
AA7 AVSS W12 NC
AA8 TXB_B1/TXB_CP W13 NC
AA9 TXB_A0/TXB_DP2 W14 TXA_B2/TXA_DN0
AA10 TXB_B0/TXB_DN2 W15 VSS
AA11 VDRV W17 VDRV
AA12 VDRV_REG W21 TXA_A0/TXA_DP2
AA13 AVDD W22 NC
AA14 VDRV_REG V2 NC
AA15 VCIP V3 NC
AA16 TXA_A2/TXA_DP0 V4 NC
AA17 VDRV V5 NC
AA18 NC V6 NC
AA19 TXA_C0/TXA_DP1 V8 NC
AA20 TXA_B0/TXA_DN2 V9 NC
AA21 VSS V10 VSS
AA22 NC V11 NC
Y1 NC V12 NC
Y2 NC V14 NC
Y3 NC V15 NC

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Ball number Pin Name Ball number Pin Name
V17 AVDD R5 NC
V18 AVDD R6 VSS
V19 TXA_C1/TXA_CN R7 NC
V20 TXA_A1/TXA_DN1 R8 NC
V21 NC R9 AVDD
V22 NC R10 AVDD
U1 AVDD R11 NC
U2 NC R12 VDRV
U3 AVDD R13 TXB_DN3
U4 NC R14 TXB_B2/TXB_DN0
U5 NC R15 NC
U6 VSS R16 NC
U8 VSS R17 NC
U9 VSS R18 NC
U11 VSS R19 VSS
U12 VSS R20 NC
U14 VSS R21 NC
U15 AVDD R22 AVDD
U17 VSS P1 PS0
U18 NC P2 PS1
U19 VSS P3 PS2
U20 VSS P4 PS4
U21 NC P5 NC
T1 AVDD P6 NC
T2 NC P7 NC
T7 NC P9 NC
T8 NC P10 AVSS
T9 AVSS P13 DATA0_53
T10 NC P14 NC
T11 NC P16 NC
T12 AVDD P17 VSS
T13 TXB_C2/TXB_DP3 P18 NC
T14 VSS P19 NC
T15 AVDD P20 NC
T16 AVDD P21 NC
T21 NC N1 NC
T22 NC N2 PS3
R2 NC N4 NC
R3 NC N7 VDD_CORE
R4 NC N9 SDI

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Ball number Pin Name Ball number Pin Name
N10 SDO L16 TEST_MODE0
N11 NC L17 VSS
N12 NC L18 VSS
N13 NC L19 RESET
N14 VDD_CORE L20 VSS
N16 VSS L21 HSYNC0
N21 CLK_IN K1 VDD_CORE
N22 CSX0 K2 NC
M2 NC K5 TE_IN_0
M3 NC K7 PCLK1
M4 SDC K9 NC
M5 NC K10 NC
M6 VSS K11 DATA0_51
M7 INT_B K12 NC
M8 VSS K13 DATA0_29
M9 DATA0_55 K14 DATA0_28
M10 DATA0_56 K16 NC
M13 VDD_CORE K21 PCLK0
M14 VDD_CORE K22 NC
M15 VSS J2 VSS
M16 IF_SEL0 J3 NC
M17 NC J4 DATA0_58
M18 NC J5 NC
M19 NC J6 VSS
M20 NC J7 HSYNC1
M21 VSYNC0 J9 DATA0_50
M22 PD_N J10 NC
L1 NC J13 DATA0_25
L2 NC J14 DATA0_24
L3 NC J16 VDDIO
L4 NC J17 NC
L5 VDD_CORE J18 NC
L6 TE_IN_1 J19 DEN0
L7 VSYNC1 J20 NC
L8 DEN1 J21 NC
L9 SCK J22 DATA0_0
L10 DATA0_54 H1 NC
L13 NC H2 NC
L14 XTAL_OUT H3 DATA0_59
L15 XTAL_IN H4 DATA0_57

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Ball number Pin Name Ball number Pin Name
H5 NC F12 NC
H6 DATA0_45 F14 VSS
H7 NC F15 NC
H8 NC F17 NC
H9 NC F18 NC
H10 NC F19 NC
H11 NC F20 VSS
H12 DATA0_26 F21 VDD_CORE
H13 NC F22 NC
H14 NC E1 NC
H15 NC E2 DATA0_48
H16 VDD_CORE E3 DATA0_47
H17 NC E4 NC
H18 NC E5 NC
H19 VSS E6 NC
H20 VSS E8 NC
H21 DATA0_1 E9 NC
G1 VDD_CORE E10 NC
G2 NC E11 DATA0_22
G5 VSS E12 VSS
G7 NC E14 NC
G8 NC E15 NC
G9 VDDIO E17 NC
G10 NC E18 DATA0_8
G11 NC E19 DATA0_7
G12 DATA0_27 E20 DATA0_6
G13 NC E21 NC
G14 DATA0_10 D1 DATA0_49
G15 NC D2 NC
G16 NC D6 NC
G21 DATA0_2 D8 DATA0_31
G22 NC D9 VDD_CORE
F2 NC D11 DATA0_15
F3 DATA0_52 D12 DATA0_20
F4 NC D14 NC
F5 DATA0_46 D15 DATA0_9
F6 VSS D17 VDDIO
F8 VSS D21 DATA0_4
F9 VSS D22 NC
F11 VSS C1 NC

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Ball number Pin Name Ball number Pin Name
C2 NC B13 DATA0_14
C4 DATA0_39 B14 DATA0_12
C5 DATA0_40 B15 NC
C6 DATA0_37 B16 DATA0_11
C8 DATA0_34 B17 NC
C9 DATA0_30 B18 NC
C11 DATA0_23 B19 DATA0_3
C12 DATA0_17 B20 NC
C14 NC B22 NC
C15 NC A1 NC
C17 NC A2 NC
C18 VDD_CORE A3 DATA0_43
C20 NC A4 DATA0_41
C21 NC A6 DATA0_36
C22 DATA0_5 A7 DATA0_32
B1 NC A9 TE_OUT_0
B2 NC A10 DATA0_21
B3 DATA0_44 A12 DATA0_18
B4 DATA0_42 A13 DATA0_13
B5 DATA0_38 A15 NC
B6 NC A16 NC
B7 DATA0_35 A18 NC
B8 DATA0_33 A19 NC
B9 VSS A20 NC
B10 TE_OUT_1 A21 NC
B11 DATA0_19 A22 NC
B12 DATA0_16

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7 POWER SUPPLY PIN
Key:
I = Input
O =Output
IO = Bi-directional (input/output)
P = Power pin

7.1 Power Supply Pin

Table 7-1: Power Supply Pin Description
When not
Pin name Type Connect to Description
in use
VDD_CORE P Power Core Power Supply, 1.3V -
VDDIO P Power I/O Power Supply, 1.8V or 3.3V -
VSS P GND Ground -
AVDD_RC P Power Analog Power Supply 1.3V -
AVDD P Power Analog Power Supply 1.3V -
AVSS P GND Ground -
VCIP P Power Power for Bandgap, 3.3V -
VDRV_REG P Power LV Regulator Output -
Power for MIPI TX Driver (to be connected to -
VDRV P Power
VDRV_REG, 0.5V)

7.2 MIPI Pin

Table 7-2: MIPIRX Pin Description

Pin name Type Connect to Description When not in use

TXA_DP2/ Out/ TXA DSI D Data Lane Positive 2 / Open
TXA_A0 Inout TXA DSI C Data Lane A0
TXA_DN2/ Out/ TXA DSI Data Lane Negative 2 /
TXA_B0 Inout TXA DSI C Data Lane B0
TXA_DP1/ Out/ TXA DSI D Data Lane Positive 1 /
TXA_C0 Inout TXA DSI C Data Lane C0
TXA_DN1/ Out/ TXA DSI D Data Lane Negative 1 /
TXA_A1 Out TXA DSI C Data Lane A1
TXA_CP/ Out/ TXA DSI D Clock Lane Positive /
TXA_B1 Out TXA DSI C Data Lane B1
MIPI DSI_TX
TXA_CN/ Out/ TXA DSI D Clock Lane Negative /
TXA_C1 Out TXA DSI C Data Lane C1
TXA_DP0/ Inout/ TXA DSI D Data Lane Positive 0 /
TXA_A2 Out TXA DSI C Data Lane A2
TXA_DN0/ Inout/ TXA DSI D Data Lane Negative 0 /
TXA_B2 Out TXA DSI C Data Lane B2
TXA_DP3/ Out/ TXA DSI D Data Lane Positive 3 /
TXA_C2 Out TXA DSI C Data Lane A2
TXA_DN3 Out TXA DSI Data Lane Negative 3
TXB_DP2/ Out/ TXB DSI D Data Lane Positive 2 /

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 TXB_A0 Inout TXB DSI C Data Lane A0
TXB_DN2/ Out/ TXB DSI Data Lane Negative 2 /
TXB_B0 Inout TXB DSI C Data Lane B0
TXB_DP1/ Out/ TXB DSI D Data Lane Positive 1 /
TXB_C0 Inout TXB DSI C Data Lane C0
TXB_DN1/ Out/ TXB DSI D Data Lane Negative 1 /
TXB_A1 Out TXB DSI C Data Lane A1
TXB_CP/ Out/ TXB DSI D Clock Lane Positive /
TXB_B1 Out TXB DSI C Data Lane B1
TXB_CN/ Out/ TXB DSI D Clock Lane Negative /
TXB_C1 Out TXB DSI C Data Lane C1
TXB_DP0/ Inout/ TXB DSI D Data Lane Positive 0 /
TXB_A2 Out TXB DSI C Data Lane A2
TXB_DN0/ Inout/ TXB DSI D Data Lane Negative 0 /
TXB_B2 Out TXB DSI C Data Lane B2
TXB_DP3/ Out/ TXB DSI D Data Lane Positive 3 /
TXB_C2 Out TXB DSI C Data Lane A2
TXB_DN3 Out TXB DSI Data Lane Negative 3

Table 7-3: MIPI Pin Description

7.3 Control Signal Pin

When not
Pin name Type Connect to Description
in use
VDDIO /
RESET I System Reset signal to the whole chip, active low
GND VDDIO
INT_B O - Output Interrupt Signal Open
VDDIO /
PD_N I Power Down, active low
GND VDDIO
Interface selection signals
VDDIO / - 0 : A combination of RGB and SPI interface is
IF_SEL0 I
GND selected VDDIO /
- 1 : MCU interface is selected GND

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 Interface selection signal
PS[1:0] is for SPI interface
- 00: 3 wire 24-bit SPI interface
- 01: 3 wire 8-Bit SPI interface
- 10: 4 wire 8-Bit SPI interface
- 11: Reserved

PS[4:2] is for the MCU interface

When if_sel is ‘1’
- 000: 8-Bit MCU interface (MIPI DBI type B)
VDDIO /
PS[4:0] I - 001: 16-bit MCU interface (MIPI DBI type B)
GND
- 010: 8-Bit MCU interface (MIPI DBI type A,
fixed E or clocked E mode)
- 011: 16-bit MCU interface (MIPI DBI type A,
fixed E or clocked E mode)
- 100: 24-bit MCU interface (MIPI DBI type B)
- 110: 24-bit MCU interface (MIPI DBI type A,
fixed E or clocked E mode)
- 101: 48-bit MCU interface (MIPI DBI type B)
- 111: 48-bit MCU interface (MIPI DBI type A, VDDIO /
fixed E or clocked E mode) GND
MIPI CPHY / MIPI DPHY output selection
TEST_MODE0 I VDDIO/GND - 0 : MIPI CPHY output is selected
- 1 : MIPI DPHY output is selected
CLK_IN I - Reserved Open
XTAL_OUT I - Crystal inout for System PLL Open
Crystal in for System PLL
XTAL_IN I External CLK
Frequency range: 8MHz to 40MHz -
Table 7-4: Control Signal Pin Description

7.4 Interface Logic Pin

When not
Pin name Type Connect to Description
in use
RGB data for RGB Interface Open
DATA0[59:0] I/O
MCU data for MCU interface
- Vsync for lower RGB interface VDDIO /
- E clock signal for MCU interface GND
VSYNC / E /
I (This is for MIPI DBI type A interface)
WRX
- Write enable signal for MCU interface. Enabled
when low. (This is for MIPI DBI type B interface)
- pclk for lower RGB interface VDDIO /
MCU/RGB
- Read/Write selection signal for MCU interface. GND
Signals
PCLK / RWX / Read cycle when high, write cycle when low.
I
RDX (This is for MIPI DBI type A interface)
- Read enable signal for MCU interface. Enabled
when low. (This is for MIPI DBI type B interface.)
- Hsync for lower RGB interface VDDIO /
HSYNC I
GND
- Den of lower RGB interface VDDIO /
DEN; DCX I
- Data or command signal of MCU interface GND

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 Input Tearing Effect Signal from DDI VDDIO /
TE_IN_0 I
GND
TE_OUT_0 O Output Tearing Effect Signal to MCU Open
Reserved VDDIO /
TE_IN_1 I
GND
TE_OUT_1 O Reserved Open

Table 7-5: MCU/RGB Interface Description

When not
Pin name Type Connect to Description
in use
CSX0 I Chip Select of SPI interface VDDIO
VDDIO /
SDC I Data or Command of SPI interface (for 8-bit 4 wire)
GND
VDDIO /
SCK I SPI Signal Serial clock of SPI interface
GND
VDDIO /
SDI I Serial data input of SPI interface
GND
SDO O Serial data output of SPI interface Open
Table 7-6: SPI Interface Description

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8 COMMAND TABLE

8.1 Local Registers (non-APB) Descriptions

8.1.1 RGB Interface Control Register 1

Offset Address
RICR1 RGB Interface Control Register 1 0xB1
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME VSA
TYPE RW
RESET 0x02

BIT 7 6 5 4 3 2 1 0
NAME HSA
TYPE RW
RESET 0x0A

Table 8-1: RGB Interface Control Register 1 Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
VSA VSA – Vertical Sync Active Period Per Application Condition, please
Bit 15-8 refer to section 15
These bits specify the Vsync active period. APPLICATION REFERENCE for
The Hsync active period is from the Vsync reference.
falling edge to rising edge, in terms of Hsync
lines. It is only used in non-burst mode with
Sync pulses.
(Refer to section 15.2 Video Mode Use Cases)
HSA HSA – Horizontal Sync Active Period Per Application Condition, please
Bit 7-0 refer to section 15
These bits specify the Hsync active period. APPLICATION REFERENCE for
The Hsync active period is from the Hsync reference.
falling edge to rising edge, in terms of pclk. It is
only used in non-burst mode with Sync pulses.
(Refer to section 15.2 Video Mode Use Cases)

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8.1.2 RGB Interface Control Register 2
Offset Address
RICR2 RGB Interface Control Register 2 0xB2
BIT 31 30 29 28 27 26 25 24
NAME VBP[15:8]
TYPE RW
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME HBP[15:8]
TYPE RW
RESET 0x00

BIT 15 14 13 12 11 10 9 8
NAME VBP[7:0]
TYPE RW
RESET 0x02

BIT 7 6 5 4 3 2 1 0
NAME HBP[7:0]
TYPE RW
RESET 0x14

Table 8-2: RGB Interface Control Register 2 Description

Name Description Setting
VBP[15:8] VBP – Vertical Back Porch Period High Byte Per Application Condition, please
Bit 31-24 refer to section 15
Refer to VBP[7:0] for description APPLICATION REFERENCE for
reference.
HBP[15:8] HBP – Horizontal Back Porch Period High Byte Per Application Condition, please
Bit 23-16 refer to section 15
Refer to HBP[7:0] for description APPLICATION REFERENCE for
reference.
VBP[7:0] VBP – Vertical Back Porch Period Low Byte Per Application Condition, please
Bit 15-8 refer to section 15
These bits specify the vertical back porch period APPLICATION REFERENCE for
in terms of Hsync pulses. The vertical back reference.
porch period depends on the video mode setting.

If the mode is non-burst mode with Sync pulses,

it is from the Vsync rising edge to the Hsync of
the first line of active display.
If the mode is non-burst mode with Sync events
or burst mode, it is from the Vsync falling edge
to the Hsync of the first line of active display.
(Refer to section 15.2 Video Mode Use Cases)
HBP[7:0] HBP – Horizontal Back Porch Period Low Byte Per Application Condition, please
Bit 7-0 refer to section 15
These bits specify the horizontal back porch APPLICATION REFERENCE for
period in terms of pclk. The horizontal back reference.
porch period depends on the non-burst mode
setting.

Solomon Systech Aug. 2020 44/178 Rev 1.5 SSD2832

 Name Description Setting
If the mode is non-burst mode with Sync pulses,
it is from the Hsync rising edge to the start of
the valid display pixel.
If the mode is non-burst mode with Sync events
or burst mode, it is from the Hsync falling edge
to the start of the valid display pixel.
(Refer to section 15.2 Video Mode Use Cases)

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8.1.3 RGB Interface Control Register 3
Offset Address
RICR3 RGB Interface Control Register 3 0xB3
BIT 31 30 29 28 27 26 25 24
NAME VFP[15:8]
TYPE RW
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME HFP[15:8]
TYPE RW
RESET 0x00

BIT 15 14 13 12 11 10 9 8
NAME VFP[7:0]
TYPE RW
RESET 0x02

BIT 7 6 5 4 3 2 1 0
NAME HFP[7:0]
TYPE RW
RESET 0x14

Table 8-3: RGB Interface Control Register 3 Description

Name Description Setting
VFP[15:8] VFP – Vertical Front Porch Period High Byte Per Application Condition, please
Bit 31-24 refer to section 15
Refer to VFP[7:0] for description APPLICATION REFERENCE for
reference.
HFP[15:8] HFP – Horizontal Front Porch Period High Byte Per Application Condition, please
Bit 23-16 refer to section 15
Refer to HFP[7:0] for description APPLICATION REFERENCE for
reference.
VFP[7:0] VFP – Vertical Front Porch Period Low Byte Per Application Condition, please
Bit 15-8 refer to section 15
These bits specify the vertical front porch period APPLICATION REFERENCE for
in terms of Hsync pulses. The vertical front reference.
porch period is from the first Hsync after the last
line of active display to the next Vsync falling
edge.
HFP[7:0] HFP – Horizontal Front Porch Period Low Byte Per Application Condition, please
Bit 7-0 refer to section 15
These bits specify the horizontal front porch APPLICATION REFERENCE for
period in terms of pclk. The horizontal front reference.
porch period is from the end of the valid display
pixel to the next Hsync falling edge.

Solomon Systech Aug. 2020 46/178 Rev 1.5 SSD2832

8.1.4 RGB Interface Control Register 4
Offset Address
RICR4 RGB Interface Control Register 4 0xB4
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME HACT[15:8]
TYPE RW
RESET 0x07

BIT 7 6 5 4 3 2 1 0
NAME HACT[7:0]
TYPE RW
RESET 0x80

Table 8-4: RGB Interface Control Register 4 Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
HACT HACT – Horizontal Active Period Per Application Condition, please
Bit 15-0 refer to section 15
These bits specify the horizontal active period in APPLICATION REFERENCE for
terms of pclk. During the horizontal active reference.
period, the den signal should always be high.

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8.1.5 RGB Interface Control Register 5
Offset Address
RICR5 RGB Interface Control Register 5 0xB5
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME VACT[15:8]
TYPE RW
RESET 0x04

BIT 7 6 5 4 3 2 1 0
NAME VACT[7:0]
TYPE RW
RESET 0x38

Table 8-5: RGB Interface Control Register 5 Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
VACT VACT – Vertical Active Period Per Application Condition, please
Bit 15-0 refer to section 15
These bits specify the vertical active period in APPLICATION REFERENCE for
terms of Hsync pulses. reference.

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8.1.6 RGB Interface Control Register 6
Offset Address
RICR6 RGB Interface Control Register 6 0xB6
BIT 31 30 29 28 27 26 25 24
NAME VSD
TYPE RW
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME HSD
TYPE RW
RESET 0x02

BIT 15 14 13 12 11 10 9 8
NAME VS_P HS_P PCLK_P SDR RGB_PACK_SEQ VPF_EXT CBM
TYPE RW RW RW RW RW RW RW
RESET 0x0 0x0 0x0 0x1 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME NVB NVD BLLP VCS VM VPF
TYPE RW RW RW RW RW RW
RESET 0x0 0x0 0x1 0x0 0x1 0x0

Table 8-6: RGB Interface Control Register 6 Description

Name Description Setting
VSD VSD – Vertical Sync Delay Per Application Condition
Bit 31-24
These bits control the internal pipeline delay of
the Vsync input.
HSD HSD – Horizontal Sync Delay Per Application Condition
Bit 23-16
These bits control the internal pipeline delay of
the Hsync input.
VS_P VS_P – Vertical Sync Polarity 0 – Vsync Pulse is active low
Bit 15 1 – Vsync Pulse is active high
This bit control the polarity of the Vsync pulse
input.
HS_P HS_P – Horizontal Sync Polarity 0 – Hsync Pulse is active low
Bit 14 1 – Hsync Pulse is active high
This bit control the polarity of the Hsync pulse
input.
PCLK_P PCLK_P – Pixel Clock Polarity 0 – Data is launch at falling edge,
Bit 13 SSD2832 latch data at rising edge
This bit control the polarity of the PCLK input. 1 – Data is launch at rising edge,
This bit is valid when SDR is 1. SSD2832 latch data at falling edge

SDR SDR - Single Data Rate 0 – Data is launch at both rising and
Bit 12 falling edge
This bit control whether the RGB input is single 1 – Data is launch at either rising or
data rate or dual data rate. falling edge, depends on the
PCLK_P bit
RGB_PACK RGB_PACK_SEQ - RGB Packing Sequence For RGB input and 2 DSI_TX
_SEQ output(1 to 2)

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 Name Description Setting
Bit 11-10 This is applicable for 1 RGB to 2 DSI_TX 0 - Odd/Even split. RGB lower order
output (1 to 2) configurations. pixel = pixel[0] on DSI_TX0, RGB
higher order pixel = pixel[1] on
DSI_TX1.
1 - Left/Right split. pixel[0] to
pixel[n/2-1] on DSI_TX0, pixel[n/2]
to pixel[n-1] on DSI_TX1.
2 - Broadcast split. DSI_TX0(RGB)
is duplicated to DSI_TX1
3 - Reserved
VPF_EXT VPF_EXT - Video Pixel Format Extension [VPF_EXT, VPF]
Bit 9 000 - 16-bit
This bit is used in conjunction with the 001 - 18-bit
VPF[1:0] bits to define the output pixel format. 010 - 18-bit loosely
011 - 24-bit
100 - 30-bit
111 - Compressed pixel
CBM CBM – Compress Burst Mode Control 0 – Video with blanking packet.
Bit 8 1 – Video with no blanking packet
If the video mode is burst(VM=0x2) and this
bit is 1, MIPITX will send video packet in
compressed burst mode (i.e. no blanking packet
after horizontal sync packet)
NVB NVB – Non Video Data Burst Mode Control 0 - Non video data will be
Bit 7 transmitted during any BLLP period
This bit specifies how non video data will be 1 - Non video data will only be
interleaved with video data transmission in burst transmitted during vertical blanking
mode. period
NVD NVD – Non Video Data Transmission Control 0 – Non video data will be
Bit 6 transmitted using HS mode
This bit specifies how non video data will be 1 – Non video data will be
interleaved with video data transmission. transmitted using LP mode
The SSD2832 will send non video data (written
from the SPI interface) during the vertical Refer to section 15 Interleaving Non-
blanking period (non-burst mode) or any BLLP Video Packets with Video Packets
period in burst mode (depends on NVB setting). for detailed information.
The data can be sent either in high speed mode
or low power mode. This bit selects which
mode to use. If LP mode is selected, the data
lane will enter LP mode for BLLP period, even
if there is no non-video data to send.
Please note that sending data in LP mode is
much slower than HS mode. It is the
responsibility of the host processor to make sure
that the duration is long enough to finish the
data transfer and the timing of Hsync and Vsync
is not affected.

BLLP BLLP – Blanking and Low Power Control 0 – Blanking packet will be sent
Bit 5 during BLLP period
This bit specifies the SSD2832 operation during 1 – LP mode will be used during
BLLP period. This bit takes effect only for non- BLLP period
burst mode and NVD being 0.
Refer to section 15 Interleaving Non-
Video Packets with Video Packets
for detailed information.

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 Name Description Setting
When the video mode is burst mode, the
SSD2832 will not send any blanking packet
during BLLP. It will enter LP mode.
When NVD is 1 in non-burst mode, the
SSD2832 will stay in LP mode after sending the
non-video data (if there is any), until the BLLP
period ends.

When NVD is 0 in non-burst mode, the

SSD2832 will use this bit to decide whether to
send blanking packet or enter LP mode after
sending non video data (if there is any), until the
BLLP period ends.
Please note that entering and exiting from LP
mode needs more time, as the speed of LP mode
is slow. It is the responsibility of the host
processor to make sure that the period is long
enough to finish the data transfer and the timing
of Hsync and Vsync is not affected.
VCS VCS – Video Clock Suspend 0 – During burst mode, the clock
Bit 4 lane remains in HS mode, when there
This bit specifies how non video data will be is no data to transmit. During non-
interleaved with video data transmission in burst burst mode, the clock lane will
mode. remain in HS mode all the time.
This bit specifies the clock lane behavior 1 – During burst mode, the clock
lane enters LP mode when there is no
data to transmit. During non-burst
mode, the clock lane enters LP mode
during vertical blanking period.
VM VM – Video Mode 00 – Non burst mode with sync
Bit 3-2 pulses
These bits specify the video mode when RGB 01 – Non burst mode with sync
interface is selected. events
10 – Burst mode
11 – Reserved
VPF VPF – Video Pixel Format [VPF_EXT, VPF]
Bit 1-0 000 - 16-bit
This bit is used in conjunction with the 001 - 18-bit
VPF_EXT bit to define the output pixel format. 010 - 18-bit loosely
011 - 24-bit
100 - 30-bit
111 - Compressed pixel

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8.1.7 Configuration Register
Offset Address
CFR Configuration Register 0xB7
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
OTHER_
NAME VEN_CTR SCR_EN TXD LPE EOT ECD
CMD
TYPE RO RW RW RW RW RW RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x1 0x1

BIT 7 6 5 4 3 2 1 0
NAME REN DCS CSS HCLK VEN SLP CKE HS
TYPE RW RW RW RW RW RW RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-7: Configuration Register Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-15
VEN_CTR VEN_CTR – Video Enable Control 0 – Internal video enable follows
Bit 14 the VEN bit
This bit specifies whether the SSD2832 will 1 – Internal video enable extends
extend the internal video enable bit until frame until the frame boundary
boundary.

SCR_EN SCR_EN – Scrambler Mode Enable 0 – Scrambling is disable

Bit 13 1 – Scrambling is enable
This bit specifies whether the SSD2832 will
send the long packets with scrambled data.
SSD2832 will send the Scrambling Mode Packet
prior to the Long packet.
OTHER_C OTHER_CMD – Other Command 0 – DCS bit defines DCS or
MD Generic command.
Bit 12 This bit defines how DCS, Generic, PPS or 1 – DCS bit defines PPS or
Compression Mode packet is sent. Compression mode packet.

TXD TXD –Transmit Disable 0 – Transmit on

Bit 11 1 – Transmit halt
This bit specifies whether the SSD2832 will
disable the sending of MIPI Packets stored in
the buffers. Software can enable TXD, fill out
the buffers and then disable it to send all packets
out in 1 burst.
LPE LPE –Long Packet Enable 0 – Short Packet

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 Name Description Setting
Bit 10 1 – Long Packet
This bit specifies whether the SSD2832 will
send out a Generic Long Write Packet or
Generic Short Write Packet when the payload is
no more than 2 bytes.
It also specifies whether the SSD2832 will send
out a DCS Long Write Packet or DCS Short
Write Packet when the payload is no more than
1 byte.

EOT EOT – EOT Packet Enable 0 – Do not send

Bit 9 1 – Send
This bit specifies whether the SSD2832 will
send out the EOT packet at the end of HS
transmission or not.
ECD ECD – ECC CRC Check Disable 0 – Enable
Bit 8 1 – Disable
This bit specifies whether SSD2832 will
perform ECC and CRC checking for the packets
received from the MIPI slave.
REN REN – Read Enable 0 – Write operation
Bit 7 1 – Read operation
This bit specifies whether the next operation is a
write or read operation.
DCS DCS – DCS or Generic When OTHER_CMD is 0,
Bit 6
This bit specifies whether the packet to be sent 0 – Generic packet (The packet
is DCS packet or generic packet. This bit applies can be any one of Generic Long
for both write and read operation. When Write, Generic Short Write,
OTHER_CMD bit is set, this bit specifies Generic Read packet, depending
whether the packet to be sent is PPS or on the configuration.)
Compress Mode packet. 1 – DCS packet (The packet can
be any one of DCS Long Write,
DCS Short Write, DCS Read
packet, depending on the
configuration.)

When OTHER_CMD is 1,

0 – Picture Parameter Setting

Packet
1 – Compress Mode Packet
CSS CSS – Clock Source Select 0 – The clock source is XTAL_IN
Bit 5 1 – The clock source is pclk
This bit selects the clock source for the PLL.
The CSS setting should be programmed only
when PEN is 0. It has no effect when PEN is 1.
HCLK HCLK – High Speed Clock Disable 0 – HS clock is enabled
Bit 4 1 – HS clock is disabled
This bit controls the clock lane behavior during
the reverse direction communication. This bit
takes effect only when CKE is 0 and VEN is 0.
VEN VEN – Video Mode Enable 0 – Video mode is disabled
Bit 3 This bit controls the video mode operation. 1 – Video mode is enabled
Only after this bit is set to 1, video mode is
enabled.

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 Name Description Setting
SLP SLP – Sleep Mode Enable 0 – Sleep mode is disabled
Bit 2 1 – Sleep mode is enabled Only
This bit controls the sleep mode operation. the register interface is active
When this bit is set to 1, the HS bit will be
cleared to 0 automatically.
CKE CKE – Clock Lane Enable 0 – Clock lane will enter LP mode,
Bit 1 if it is not in reverse direction
This bit controls the clock lane mode when data communication.
lane enters LP mode. Clock lane will follow the setting
of HCLK, if it is in reverse
direction communication.
1 – Clock lane will enter HS mode
for all the cases
HS HS – High Speed Mode 0 – LP mode
Bit 0 1 – HS mode
This bit controls whether the SSD2832 is using
HS or LP mode to send data.
This bit can be affected by the SLP bit value.

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8.1.8 Virtual Channel Control Register
Offset Address
VCCR Virtual Channel Control Register 0xB8
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME VCM VCE VC2 VC1
TYPE RW RW RW RW
RESET 0x1 0x0 0x1 0x1

Table 8-8: Virtual Channel Control Register Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-8
VCM VCM – Virtual Channel ID for Maximum Per Application Condition
Bit 7-6 Return Size Packet

These bits specify the VC ID for the Maximum

Return Size Packet sent by SSD2832.
This VC ID might be different from the
VC ID for the packets carrying the actual data.
VCE VCE – Virtual Channel ID for EOT Packet Per Application Condition
Bit 5-4
These bits specify the VC ID for the EOT
Packet sent by SSD2832.
This VC ID might be different from the VC ID
for the packets carrying the actual data.
VC2 VC2 – Virtual Channel ID for SPI Interface Per Application Condition
Bit 3-2
These bits specify the VC ID for the packets
written in through the SPI interface when
if_sel[0] = 0.
VC1 VC1 – Virtual Channel ID for RGB and MCU Per Application Condition
Bit 1-0 Interface

These bits specify the VC ID for the packets

written in through the RGB interface when
if_sel[0] = 0) or the MCU interface when
if_sel[0] = 1.

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8.1.9 PLL Control Register
Offset Address
PCR PLL Control Register 0xB9
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME PEN
TYPE RO RO RO RO RO RO RO RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-9: PLL Control Register Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-1
PEN PEN – PLL Enable 0 – PLL power down
Bit 0 1 – PLL enable
This bit controls the PLL operation.

Note: Frequency of PLL can only be changed during PEN=0

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8.1.10 PLL Configuration Register
Offset Address
PCFR PLL Configuration Register 0xBA
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
PLL_TES
NAME FR MS
T
TYPE RW RW RW
RESET 0x3 0x0 0x01

BIT 7 6 5 4 3 2 1 0
NAME NS
TYPE RW
RESET 0x20

Table 8-10: PLL Configuration Register Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
FR FR – Frequency Range 00 – 62.5 to 125
Bit 15-14 01 – 126 to 250
These bits select the range of the output clock. 10 – 251 to 500
11 – 501 to 1500
PLL_TEST PLL_TEST – PLL Test Mode Not Applicable
Bit 13
It should be set to 0 in normal mode.
MS MS – PLL frequency Divider 0x00 - Reserved
Bit 12-8 0x01 - MS=1
These bits specify the PLL pre-divider value, 0x02 - MS=2
MS. …
0x1F - MS=31
NS NS – PLL frequency Multiplier 0x00 - NS=1
Bit 7-0 0x01 - NS=1
These bits specify the PLL output frequency 0x02 - NS=2
multiplier value, NS. …
0xFF - NS=255

e.g. XTAL_IN = 20MHz, 0xBAh = 0xC132h

For MIPI CPHY: PLL = 50 x 20 / 1 = 1Gsps

For MIPY DPHY: PLL = 50 x 20 / 1 = 1Gbps

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8.1.11 Clock Control Register
Offset Address
CCR Clock Control Register 0xBB
BIT 31 30 29 28 27 26 25 24
BYP_BIT
NAME
_DIV
TYPE RO RO RO RW RW
RESET 0x0 0x0 0x0 0x1 0x6

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RW
RESET 0x07

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME TX_LPD
TYPE RW
RESET 0x03

Table 8-11: Clock Control Register Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-29
BYP_BIT_D BYP_BIT_DIV – Bypass bit clock divider for 0 – bit_clk is divided by 2 from
IV bit clock PLL clock
Bit 28 1 – bit_clk is directly from PLL
This bit when set will bypass the bit_div for the clock
bit clock.
Reserved Reserved Not Applicable
Bit 27-24
Reserved Reserved Not Applicable
Bit 23-16
Reserved Reserved Not Applicable
Bit 15-8
TX_LPD TX_LPD – LP Clock Divider for MIPITX 0x0 – Divide by 0
Bit 7-0 0x1 – Divide by 1
These bits give the divider value for generating 0x2 – Divide by 2
the LP mode clock from the system clock. …
0x3F – Divide by 64

Remark: e.g. LPD = 0x9

For MIPY CPHY: PLL = 1Gsps

LP clock = 1Gsps / 2(LPD+1) / 7 = 7.14286MHz

For MIPY DPHY: PLL=1Gbps

LP clock = 1Gbps / 2(LPD+1) / 8 = 6.25MHz

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8.1.12 Packet Size Control Register 1
Offset Address
PSCR1 Packet Size Control Register 1 0xBC
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME TDC_L[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME TDC_L[7:0]
TYPE RW
RESET 0x00

Table 8-12: Packet Size Register 1 Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
TDC_L TDC_L – Transmit Data Count Low Per Application Condition, please
Bit 15-0 refer to section 15 for reference.
These bits, together with TDC_H, forms the 32
bit value for TDC.

TDC set the total number of data bytes to be

transmitted by the SSD2832 in the next
operation. The SSD2832 will use the value in
this field to decide what type of packet to send
out.

The settings of TDC and PST will configure the

transfer mode into partition and non-partition
mode when the command is 0x2C or 0x3C.

Partition mode(TDC > PST) - For DCS Long

Write packet with DCS command being 0x2C or
0x3C, there is no limit in the maximum number
of bytes to be transmitted in 1 write. The PST
value can be set to maximum of 8191 bytes. The
SSD2832 will auto insert 0x3C command at
these boundaries. This is valid in RGB+SPI
mode.

Non-Partition mode(TDC <= PST) For DCS

Long Write packet with DCS command being
0x2C or 0x3C, the maximum number of bytes to

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 Name Description Setting
be transmitted in 1 write is 10560 bytes for
MIPITX0 and 8544 bytes for MIPITX1. In this
mode,
the PST value is the same or greater than the
TDC value.
Not Applicable

e.g.
1 1440
1

LCD
1440 (H) x 2560 (V)
2560

Total transmitted data per frame = 1440 x 2560 x 3 = 11,059,200 (= 0xA8C000h)

1 line data = 1440 x 3 =4,320 (=0x10E0h)
0xBC = 0xC000 //1 frame RAM (lower 16 bits)
0xBD = 0x00A8 //1 frame RAM (higher 16 bits)
0xBE = 0x10E0 //1 line RAM

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8.1.13 Packet Size Control Register 2
Offset Address
PSCR2 Packet Size Control Register 2 0xBD
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME TDC_H[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME TDC_H[7:0]
TYPE RW
RESET 0x00

Table 8-13: Packet Size Register 2 Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
TDC_H TDC_H – Transmit Data Count High Per Application Condition, please
Bit 15-0 refer to section 15 for reference.
Please see TDC_L for description.

SSD2832 Rev 1.5 61/178 Aug. 2020 Solomon Systech

8.1.14 Packet Size Control Register 3
Offset Address
PSCR3 Packet Size Control Register 3 0xBE
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME PST[12:8]
TYPE RO RO RO RW
RESET 0x0 0x0 0x0 0x1F

BIT 7 6 5 4 3 2 1 0
NAME PST[7:0]
TYPE RW
RESET 0xFF

Table 8-14: Packet Size Register 3 Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-13
PST PST – Packet Size Threshold Per Application Condition, please
Bit 12-0 refer to section 15 for reference.
These bits give the threshold value for
partitioning the incoming long packet data into
smaller packets. The partitioning only applies to
the DCS Long Write packet with DCS
command being 0x2C or 0x3C in Command
mode (if_sel[0]=1). The payload will be
partitioned into multiple packets. The PST
represents the threshold in term of bytes.

Solomon Systech Aug. 2020 62/178 Rev 1.5 SSD2832

8.1.15 Packet Drop Register
Offset Address
PDR Packet Drop Register 0xBF
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME PD[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME PD[7:0]
TYPE RW
RESET 0x00

Table 8-15: Packet Drop Register Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
PD PD – Packet Drop Per Application Condition
Bit 15-0
This register is not a true register. It is the entry
point for the internal buffer.

The application processor can treat this register

as an FIFO and continuously write data into it.

Since the register is only the entry point of the

internal buffer, the application processor is not
able to read the data written into the buffer.

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8.1.16 Operational Control Register
Offset Address
OCR Operational Control Register 0xC0
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME SWR
TYPE RO RO RO RO RO RO RO RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME COP
TYPE RO RO RO RO RO RO RO RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-16: Operational Control Register Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-9
SWR SWR - Software Reset Per Application Condition
Bit 8
Writing a ‘1’ to this bit will reset the entire
module. This bit will be cleared after the reset is
completed. MIPI link enters TX stop state
immediately and any outgoing MIPI packet will
be terminated immediately.
Reserved Reserved Not Applicable
Bit 7-1
COP COP – Cancel Operation Per Application Condition
Bit 0
This bit is to cancel the current operation.
When this bit is set to 1, SSD2832 will still
finish transmitting the current packet.
Afterwards, SSD2832 will stop any further
transmission. It will clear its internal buffer and
bring the state machine to its initial state.
Once this process is finished, the COP bit will
be automatically set to 0. At the same time, the
PO bit of the status register will be set to 1 too.
At this stage, there is no data in the internal
buffer. The application processor can start a new
operation.

Note: Do not use COP = 1 in video mode

(VEN=1).

Solomon Systech Aug. 2020 64/178 Rev 1.5 SSD2832

8.1.17 Maximum Return Size Register
Offset Address
MRSR Maximum Return Size Register 0xC1
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME MRS[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME MRS[7:0]
TYPE RW
RESET 0x01

Table 8-17: Maximum Return Size Register Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
MRS MRS – Maximum Return Size Per Application Condition
Bit 15-0
These bits set the maximum return size of the
read response packet returned by the MIPI slave.
The SSD2832 will automatically send out the
Set Maximum Return Size packet using the
value in this field, before every read operation.
It informs the MIPI slave about the limit of the
SSD2832. The application processor does not
need to program the register before every read
operation, if the maximum return size does not
change. The Set Maximum Return Size packet
will always be sent.

SSD2832 Rev 1.5 65/178 Aug. 2020 Solomon Systech

8.1.18 Return Data Count Register
Offset Address
RDCR Return Data Count Register 0xC2
BIT 31 30 29 28 27 26 25 24
NAME RDC1[15:8]
TYPE RO
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME RDC1[7:0]
TYPE RO
RESET 0x00

BIT 15 14 13 12 11 10 9 8
NAME RDC0[15:8]
TYPE RO
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME RDC0[7:0]
TYPE RO
RESET 0x00

Table 8-18: Return Data Count Register Description

Name Description Setting
RDC1 RDC1 – Return Data Count from MIPITX1 Per Application Condition
Bit 31-16
These bits reflect the number of data bytes
received from the MIPI slave read response
packet from MIPITX1. This register can only be
updated by the SSD2832.
RDC0 RDC0 – Return Data Count from MIPITX0 Per Application Condition
Bit 15-0
These bits reflect the number of data bytes
received from the MIPI slave read response
packet from MIPITX0. This register can only be
updated by the SSD2832.

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8.1.19 Acknowledge Response Status Register
Offset Address
ARSR Acknowledge Response Status Register 0xC3
BIT 31 30 29 28 27 26 25 24
NAME ACK1[15:8]
TYPE RO
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME ACK1[7:0]
TYPE RO
RESET 0x00

BIT 15 14 13 12 11 10 9 8
NAME ACK0[15:8]
TYPE RO
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME ACK0[7:0]
TYPE RO
RESET 0x00

Table 8-19: Acknowledge Response Status Register Description

Name Description Setting
ACK1 ACK1 – ACK Response from MIPITX1 Per Application Condition
Bit 31-16
These bits contain the ACK response from the
MIPI slave from MIPITX1. The register will be
updated when ACK with Error Report packet is
received. Otherwise, the value will be set to 0.
The bits in this register follow the definition in
MIPI DSI.
This register can only be updated by the
SSD2832.
ACK0 ACK0 – ACK Response from MIPITX0 Per Application Condition
Bit 15-0
These bits contain the ACK response from the
MIPI slave from MIPITX0. The register will be
updated when ACK with Error Report packet is
received. Otherwise, the value will be set to 0.
The bits in this register follow the definition in
MIPI DSI.
This register can only be updated by the
SSD2832.

SSD2832 Rev 1.5 67/178 Aug. 2020 Solomon Systech

8.1.20 Line Control Register
Offset Address
LCR Line Control Register 0xC4
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME RT1 RTB1 FBC1 FBT1 FBW1
TYPE RO RO RO RWAC RWAC RWAC RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME RT0 RTB0 FBC0 FBT0 FBW0
TYPE RO RO RO RWAC RWAC RWAC RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-20: Line Control Register Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-21
RT1 RT1 – Reset Trigger for MIPITX1 0 – Do not send
Bit 20 1 – Send Reset Trigger
This bit is to send a Reset Trigger Message.
When this bit is set to 1, the SSD2832 will send
a Reset Trigger Message. It is recommended to
enter LP mode and send this trigger message. If
this bit is programmed during vertical active
data is being sent on MIPI link, the reset trigger
will be delayed to next vertical blanking period
so that the reset trigger message will not disturb
the video timing on the MIPI link. Once the
Reset Trigger Message is sent out, RT1 bit will
be automatically set to 0.
RTB1 RTB1 – Register Triggered BTA for MIPITX1 0 – Do not send
Bit 19 1 – Send BTA
This bit automatically perform Bus Turnaround
(BTA) when link is not used.
When bus is returned back from the slave, the
link will remains in Low Power state until a new
request come in where HS bit determination the
transfer mode.
FBC1 FBC1 – Force Bus Contention for MIPITX1 0 – Do not force
Bit 19 1 – Force Bus Contention
This bit controls whether to force a bus
contention on the data lane. This bit will be

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 Name Description Setting
changed to 0, after the bus contention is not
detected.
FBT1 FBT1 – Force Bus Turnaround Tearing for 0 – Do not force
Bit 18 MIPITX1 1 – Force BTA for Tearing

This bit controls whether to perform automatic

BTA after previous BTA so as to get the TE
response from MIPI slave.
FBW1 FBW1 – Force Bus Turnaround after write for 0 – Do not force
Bit 17 MIPITX1 1 – Force BTA after write

This bit controls whether to automatically

generate a BTA after a write operation. It is only
valid for write operation.
After performing BTA, the bus authority has
been passed to the MIPI slave. The SSD2832 is
not able to send any data to the MIPI slave
before the bus authority is passed back. It is the
responsibility of the application processor to
check the status of the bus before sending any
data.
Reserved Reserved
Bit 16-5
RT0 RT0 – Reset Trigger for MIPITX0 0 – Do not send
Bit 4 1 – Send Reset Trigger
This bit is to send a Reset Trigger Message.
When this bit is set to 1, the SSD2832 will send
a Reset Trigger Message. It is recommended to
enter LP mode and send this trigger message. If
this bit is programmed during vertical active
data is being sent on MIPI link, the reset trigger
will be delayed to next vertical blanking period
so that the reset trigger message will not disturb
the video timing on the MIPI link. Once the
Reset Trigger Message is sent out, RT1 bit will
be automatically set to 0.
RTB0 RTB0 – Register Triggered BTA for MIPITX0 0 – Do not send
Bit 3 1 – Send BTA
This bit automatically perform Bus Turnaround
(BTA) when link is not used.
When bus is returned back from the slave, the
link will remains in Low Power state until a new
request come in where HS bit determination the
transfer mode.
FBC0 FBC0 – Force Bus Contention for MIPITX0 0 – Do not force
Bit 2 1 – Force Bus Contention
This bit controls whether to force a bus
contention on the data lane. This bit will be
changed to 0, after the bus contention is not
detected.
FBT0 FBT0 – Force Bus Turnaround Tearing for 0 – Do not force
Bit 1 MIPITX0 1 – Force BTA for Tearing

This bit controls whether to perform automatic

BTA after previous BTA so as to get the TE
response from MIPI slave.

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 Name Description Setting
FBW0 FBW0 – Force Bus Turnaround after write for 0 – Do not force
Bit 0 MIPITX0 1 – Force BTA after write

This bit controls whether to automatically

generate a BTA after a write operation. It is only
valid for write operation.
After performing BTA, the bus authority has
been passed to the MIPI slave. The SSD2832 is
not able to send any data to the MIPI slave
before the bus authority is passed back. It is the
responsibility of the application processor to
check the status of the bus before sending any
data.

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8.1.21 Interrupt Control Register
Offset Address
ICR Interrupt Control Register 0xC5
BIT 31 30 29 28 27 26 25 24
NAME CBEE1 CBAE1 MLEE1 MLAE1
TYPE RW RW RO RO RO RO RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME LPTOE1 HSTOE1 ARRE1 BTARE1 RDRE1
TYPE RO RW RW RO RW RW RO RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME CBEE0 CBAE0 MLEE0 MLAE0
TYPE RW RW RO RO RO RO RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME PLSE LPTOE0 HSTOE0 ARRE0 BTARE0 RDRE0
TYPE RW RW RW RO RW RW RO RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-21: Interrupt Control Register Description

Name Description Setting
CBEE1 CBEE1 – Command Buffer Empty Enable for 0 – Do not enable
Bit 31 MIPITX1 1 – Enable

This bit enables the mapping of CBE1 interrupt

to the interrupt pin, INT_B.
CBAE1 CBAE1 – Command Buffer Available Enable 0 – Do not enable
Bit 30 for MIPITX1 1 – Enable

This bit enables the mapping of CBA1 interrupt

to the interrupt pin, INT_B.
Reserved Reserved Not Applicable
Bit 29-26
MLEE1 MLEE1 – MCU Long Buffer Empty Enable for 0 – Do not enable
Bit 25 MIPITX1 1 – Enable

This bit enables the mapping of MLE1 interrupt

to the interrupt pin, INT_B.
MLAE1 MLAE1 – MCU Long Buffer Available Enable 0 – Do not enable
Bit 24 for MIPITX1 1 – Enable

This bit enables the mapping of MLA1 interrupt

to the interrupt pin, INT_B.
Reserved Reserved Not Applicable
Bit 23
LPTOE1 LPTOE1 – LP RX Time Out Enable for 0 – Do not enable
Bit 22 MIPITX1 1 – Enable

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 Name Description Setting
This bit enables the mapping of LPTO1
interrupt to the interrupt pin, INT_B.
HSTOE1 HSTOE1 – HP TX Time Out Enable for 0 – Do not enable
Bit 21 MIPITX1 1 – Enable

This bit enables the mapping of HSTO1

interrupt to the interrupt pin, INT_B.
Reserved Reserved Not Applicable
Bit 20
ARRE1 ARRE1 – ACK Response Ready Enable for 0 – Do not enable
Bit 19 MIPITX1 1 – Enable

This bit enables the mapping of ARR1 interrupt

to the interrupt pin, INT_B.
BTARE1 BTARE1 – Bus Turnaround Response Enable 0 – Do not enable
Bit 18 for MIPITX1 1 – Enable

This bit enables the mapping of BTAR1

interrupt to the interrupt pin, INT_B.
Reserved Reserved Not Applicable
Bit 17
RDRE1 RDRE1 – Read Data Ready Enable for 0 – Do not enable
Bit 16 MIPITX1 1 – Enable

This bit enables the mapping of RDR1 interrupt

to the interrupt pin, INT_B.
CBEE0 CBEE0 – Command Buffer Empty Enable for 0 – Do not enable
Bit 15 MIPITX0 1 – Enable

This bit enables the mapping of CBE0 interrupt

to the interrupt pin, INT_B.
CBAE0 CBAE0 – Command Buffer Available Enable 0 – Do not enable
Bit 14 for MIPITX0 1 – Enable

This bit enables the mapping of CBA0 interrupt

to the interrupt pin, INT_B.
Reserved Reserved Not Applicable
Bit 13-10
MLEE0 MLEE0 – MCU Long Buffer Empty Enable for 0 – Do not enable
Bit 9 MIPITX0 1 – Enable

This bit enables the mapping of MLE0 interrupt

to the interrupt pin, INT_B.
MLAE0 MLAE0 – MCU Long Buffer Available Enable 0 – Do not enable
Bit 8 for MIPITX0 1 – Enable

This bit enables the mapping of MLA0 interrupt

to the interrupt pin, INT_B.
PLSE PLSE – PLL Lock Status Enable 0 – Do not enable
Bit 7 1 – Enable
This bit enables the mapping of PLS interrupt to
the interrupt pin, INT_B.
LPTOE0 LPTOE0 – LP RX Time Out Enable for 0 – Do not enable
Bit 6 MIPITX0 1 – Enable

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 Name Description Setting

This bit enables the mapping of LPTO0

interrupt to the interrupt pin, INT_B.
HSTOE0 HSTOE0 – HP TX Time Out Enable for 0 – Do not enable
Bit 5 MIPITX0 1 – Enable

This bit enables the mapping of HSTO0

interrupt to the interrupt pin, INT_B.
Reserved Reserved Not Applicable
Bit 4
ARRE0 ARRE0 – ACK Response Ready Enable for 0 – Do not enable
Bit 3 MIPITX0 1 – Enable

This bit enables the mapping of ARR0 interrupt

to the interrupt pin, INT_B.
BTARE0 BTARE0 – Bus Turnaround Response Enable 0 – Do not enable
Bit 2 for MIPITX0 1 – Enable

This bit enables the mapping of BTAR0

interrupt to the interrupt pin, INT_B.
Reserved Reserved Not Applicable
Bit 1
RDRE0 RDRE0 – Read Data Ready Enable for 0 – Do not enable
Bit 0 MIPITX0 1 – Enable

This bit enables the mapping of RDR0 interrupt

to the interrupt pin, INT_B.

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8.1.22 Interrupt Status Register
Offset Address
ISR Interrupt Status Register 0xC6
BIT 31 30 29 28 27 26 25 24
NAME CBE1 CBA1 CLS1 DLS1 MLE1 MLA1
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME LPTO1 HSTO1 ATR1 ARR1 BTAR1 RDR1
TYPE RO RESW1C RESW1C RESW1C RESW1C RESW1C RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME CBE0 CBA0 CLS0 DLS0 MLE0 MLA0
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME PLS LPTO0 HSTO0 ATR0 ARR0 BTAR0 RDR0
TYPE RO RESW1C RESW1C RESW1C RESW1C RESW1C RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-22: Interrupt Status Register Description

Name Description Setting
CBE1 CBE1 – Command Buffer Empty for MIPITX1 0 – The command buffer is not
Bit 31 empty
This bit reflects the status of the internal 1 – The command buffer is
command buffer of the SPI/MCU interface. If empty
the command buffer is empty, this bit will be set
to 1. The application processor can write up to
the maximum size of the command buffer.
CBA1 CBA1 – Command Buffer Available for 0 – The command buffer is not
Bit 30 MIPITX1 available
1 – The command buffer is
This bit reflects the status of the internal available
command buffer of the SPI/MCU interface. If
the command buffer is not full, this bit will be
set to 1. The application processor can write at
least 1 packet to the command buffer.
Reserved Reserved Not Applicable
Bit 29-28
CLS1 CLS1 – Clock Lane Status for MIPITX1 0 – Clock lane is not in LP-11
Bit 27 1 – Clock lane is in LP-11
This bit reflects the status at the MIPI Clock
lane in MIPITX1.
DLS1 DLS1 – Data Lane Status for MIPITX1 0 – Data lanes are not in LP-11
Bit 26 1 – Data lanes are in LP-11
This bit reflects the status at the MIPI Clock
lane in MIPITX1.
MLE1 MLE1 – MCU Long Buffer Empty for 0 – The long buffer is not empty
Bit 25 MIPITX1 1 – The long buffer is empty

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 Name Description Setting
This bit reflects the status of the internal long
buffer of the MCU interface. If the long buffer is
empty, this bit will be set to 1. The application
processor can write up to the maximum size of
the long buffer for DCS command 0x2C and
0x3C.
MLA1 MLA1 – MCU Long Buffer Available for 0 – The long buffer is not
Bit 24 MIPITX1 available
1 – The long buffer is available
This bit reflects the status of the internal long
buffer of the MCU interface. If the long buffer is
not full, this bit will be set to 1. The application
processor can write at least 1 packet to the long
buffer for DCS command 0x2C and 0x3C.
Reserved Reserved Not Applicable
Bit 23
LPTO1 LPTO1 – LP RX Time Out for MIPITX1 0 – The LP RX timer has expired
Bit 22 1 – The LP RX timer has not
This bit reflects the status of the LP RX timer. expired

It will remain as 1 until the application

processor writes 1 to clear it.
HSTO1 HSTO1 – HS TX Time Out for MIPITX1 0 – The HS TX timer has expired
Bit 21 1 – The HS TX timer has not
This bit reflects the status of the HS TX timer. expired

It will remain as 1 until the application

processor writes 1 to clear it.
ATR1 ATR1 – ACK Trigger Response for MIPITX1 0 – ACK trigger message has not
Bit 20 been received
This bit reflects whether the ACK trigger 1 – ACK trigger message has been
message has been received or not. received

It will remain as 1 until the application

processor writes 1 to clear it.
ARR1 ARR1 – ACK Response Ready for MIPITX1 0 – Response has not been
Bit 19 received
This bit reflects whether the ACK response has 1 – Response has been received
been received or not. The ACK response can be
an ACK trigger message or ACK with Error
Report packet.

It will remain as 1 until the application

processor writes 1 to clear it.
BTAR1 BTAR1 – Bus Turnaround Response for 0 – The MIPI slave has not passed
Bit 18 MIPITX1 the lane authority back
1 – The MIPI slave has passed the
This bit reflects the data lane status after lane authority back
SSD2832 has made a BTA.

It will remain as 1 until the application

processor writes 1 to clear it.
Reserved Reserved Not Applicable
Bit 17
RDR1 RDR1 – Read Data Ready for MIPITX1 0 – Not ready

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 Name Description Setting
Bit 16 1 – Ready
This bit reflects whether the data from the MIPI
slave is ready for read by the application
processor. This bit is valid only during the read
operation.

This bit will be automatically cleared when all

the received data are read out.
CBE0 CBE0 – Command Buffer Empty for MIPITX0 0 – The command buffer is not
Bit 15 empty
This bit reflects the status of the internal 1 – The command buffer is
command buffer of the SPI/MCU interface. If empty
the command buffer is empty, this bit will be set
to 1. The application processor can write up to
the maximum size of the command buffer.
CBA0 CBA0 – Command Buffer Available for 0 – The command buffer is not
Bit 14 MIPITX0 available
1 – The command buffer is
This bit reflects the status of the internal available
command buffer of the SPI/MCU interface. If
the command buffer is not full, this bit will be
set to 1. The application processor can write at
least 1 packet to the command buffer.
Reserved Reserved Not Applicable
Bit 13-12
CLS0 CLS0 – Clock Lane Status for MIPITX0 0 – Clock lane is not in LP-11
Bit 11 1 – Clock lane is in LP-11
This bit reflects the status at the MIPI Clock
lane in MIPITX0.
DLS0 DLS0 – Data Lane Status for MIPITX0 0 – Data lanes are not in LP-11
Bit 10 1 – Data lanes are in LP-11
This bit reflects the status at the MIPI Clock
lane in MIPITX0.
MLE0 MLE0 – MCU Long Buffer Empty for 0 – The long buffer is not empty
Bit 9 MIPITX0 1 – The long buffer is empty

This bit reflects the status of the internal long

buffer of the MCU interface. If the long buffer is
empty, this bit will be set to 1. The application
processor can write up to the maximum size of
the long buffer for DCS command 0x2C and
0x3C.
MLA0 MLA0 – MCU Long Buffer Available for 0 – The long buffer is not
Bit 8 MIPITX0 available
1 – The long buffer is available
This bit reflects the status of the internal long
buffer of the MCU interface. If the long buffer is
not full, this bit will be set to 1. The application
processor can write at least 1 packet to the long
buffer for DCS command 0x2C and 0x3C.
PLS PLS – PLL Lock Status 0 – PLL is not locked
Bit 7 1 – PLL is locked
This bit reflects the status of the PLL. Before the
PLL is locked, the whole system is running at
the reference clock input of the PLL, as the PLL

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 Name Description Setting
has no output before getting lock. Hence, the
application processor must access the registers
using slow speed.
LPTO0 LPTO0 – LP RX Time Out for MIPITX0 0 – The LP RX timer has expired
Bit 6 1 – The LP RX timer has not
This bit reflects the status of the LP RX timer. expired

It will remain as 1 until the application

processor writes 1 to clear it.
HSTO0 HSTO0 – HP TX Time Out for MIPITX0 0 – The HS TX timer has expired
Bit 5 1 – The HS TX timer has not
This bit reflects the status of the HS TX timer. expired

It will remain as 1 until the application

processor writes 1 to clear it.
ATR0 ATR0 – ACK Trigger Response for MIPITX0 0 – ACK trigger message has not
Bit 4 been received
This bit reflects whether the ACK trigger 1 – ACK trigger message has been
message has been received or not. received

It will remain as 1 until the application

processor writes 1 to clear it.
ARR0 ARR0 – ACK Response Ready for MIPITX0 0 – Response has not been
Bit 3 received
This bit reflects whether the ACK response has 1 – Response has been received
been received or not. The ACK response can be
an ACK trigger message or ACK with Error
Report packet.

It will remain as 1 until the application

processor writes 1 to clear it.
BTAR0 BTAR0 – Bus Turnaround Response for 0 – The MIPI slave has not passed
Bit 2 MIPITX0 the lane authority back
1 – The MIPI slave has passed the
This bit reflects the data lane status after lane authority back
SSD2832 has made a BTA.

It will remain as 1 until the application

processor writes 1 to clear it.
Reserved Reserved Not Applicable
Bit 1
RDR0 RDR0 – Read Data Ready for MIPITX0 0 – Not ready
Bit 0 1 – Ready
This bit reflects whether the data from the MIPI
slave is ready for read by the application
processor. This bit is valid only during the read
operation.

This bit will be automatically cleared when all

the received data are read out.

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8.1.23 Error Status Register
Offset Address
ESR Error Status Register 0xC7
BIT 31 30 29 28 27 26 25 24
NAME CRCE1 ECCE2_1 ECCE1_1
TYPE RO RO RO RO RO RESW1C RESW1C RESW1C
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME CBO1 MLO1 CONT1 VMM1
TYPE RESW1C RO RO RESW1C RO RO RO RESW1C
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME CRCE0 ECCE2_0 ECCE1_0
TYPE RO RO RO RO RO RESW1C RESW1C RESW1C
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME CBO0 MLO0 CONT0 VMM0
TYPE RESW1C RO RO RESW1C RO RO RO RESW1C
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-23: Error Status Register Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-27
CRCE1 CRCE1 – CRC Error for MIPITX1 0 – No CRC error since this bit is
Bit 26 cleared
This bit reflects the status of CRC checking for 1 – At least 1 CRC error since
the packets received from the MIPI slave. The this bit is cleared
status is valid only when the ECD bit is set to 0.
Once a CRC error occurs, this bit will be set to
1.

It will remain as 1 until the application

processor writes 1 to clear it.
ECCE2_1 ECCE2_1 – ECC Multi Bit Error for MIPITX1 0 – No ECC multi-bit error since
Bit 25 this bit is cleared
This bit reflects the status of ECC checking for 1 – At least 1 ECC multi-bit
the packets received from the MIPI slave. The error since this bit is cleared
status is valid only when the ECD bit is set to 0.
Once an ECC multi-bit error occurs, this bit will
be set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
ECCE1_1 ECCE1_1 – ECC Single Bit Error for MIPITX1 0 – No ECC single bit error since
Bit 24 this bit is cleared
This bit reflects the status of ECC checking for 1 – At least 1 ECC single bit
the packets received from the MIPI slave. The error since this bit is cleared
status is valid only when the ECD bit is set to 0.

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 Name Description Setting
Once an ECC single-bit error occurs, this bit
will be set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
CBO1 CBO1 – Command Buffer Overflow for 0 – Overflow has not occurred
Bit 23 MIPITX1 1 – Overflow has occurred

This bit reflects the status of internal command

buffer of the SPI/MCU interface. If the
command buffer has overflowed, this bit will be
set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
Reserved Reserved Not Applicable
Bit 22-21
MLO1 MLO1 – MCU Long Buffer Overflow for 0 – Overflow has not occurred
Bit 20 MIPITX1 1 – Overflow has occurred

This bit reflects the status of internal long buffer

of the MCU interface. If the long buffer has
overflowed, this bit will be set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
Reserved Reserved Not Applicable
Bit 19
CONT1 CONT1 – Contention Detected for MIPITX1 0 – No contention
Bit 18 1 – Contention has occurred
This bit reflects the status of the data lane
contention detector.
Reserved Reserved
Bit 17
VMM1 VMM1 – VC Mis-Match for MIPITX1 0 – No mismatch
Bit 16 1 – Mismatch has occurred
This bit reflects whether there is a mismatch
between the VC ID transmitted by the SSD2832
and the VC ID received from the MIPI slave.

It will remain as 1 until the application

processor writes 1 to clear it.
Reserved Reserved Not Applicable
Bit 15-11
CRCE0 CRCE0 – CRC Error for MIPITX0 0 – No CRC error since this bit is
Bit 10 cleared
This bit reflects the status of CRC checking for 1 – At least 1 CRC error since
the packets received from the MIPI slave. The this bit is cleared
status is valid only when the ECD bit is set to 0.
Once a CRC error occurs, this bit will be set to
1.

It will remain as 1 until the application

processor writes 1 to clear it.

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 Name Description Setting
ECCE2_0 ECCE2_0 – ECC Multi Bit Error for MIPITX0 0 – No ECC multi-bit error since
Bit 9 this bit is cleared
This bit reflects the status of ECC checking for 1 – At least 1 ECC multi-bit
the packets received from the MIPI slave. The error since this bit is cleared
status is valid only when the ECD bit is set to 0.
Once an ECC multi-bit error occurs, this bit will
be set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
ECCE1_0 ECCE1_0 – ECC Single Bit Error for MIPITX0 0 – No ECC single bit error since
Bit 8 this bit is cleared
This bit reflects the status of ECC checking for 1 – At least 1 ECC single bit
the packets received from the MIPI slave. The error since this bit is cleared
status is valid only when the ECD bit is set to 0.
Once an ECC single-bit error occurs, this bit
will be set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
CBO0 CBO0 – Command Buffer Overflow for 0 – Overflow has not occurred
Bit 7 MIPITX0 1 – Overflow has occurred

This bit reflects the status of internal command

buffer of the SPI/MCU interface. If the
command buffer has overflowed, this bit will be
set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
Reserved Reserved Not Applicable
Bit 6-5
MLO0 MLO0 – MCU Long Buffer Overflow for 0 – Overflow has not occurred
Bit 4 MIPITX0 1 – Overflow has occurred

This bit reflects the status of internal long buffer

of the MCU interface. If the long buffer has
overflowed, this bit will be set to 1.

It will remain as 1 until the application

processor writes 1 to clear it.
Reserved Reserved Not Applicable
Bit 3
CONT0 CONT0 – Contention Detected for MIPITX0 0 – No contention
Bit 2 1 – Contention has occurred
This bit reflects the status of the data lane
contention detector.
Reserved Reserved Not Applicable
Bit 1
VMM0 VMM0 – VC Mis-Match for MIPITX0 0 – No mismatch
Bit 0 1 – Mismatch has occurred
This bit reflects whether there is a mismatch
between the VC ID transmitted by the SSD2832
and the VC ID received from the MIPI slave.

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 Name Description Setting
It will remain as 1 until the application
processor writes 1 to clear it.

8.1.24 Delay Adjustment Register 1

Offset Address
DAR1 Delay Adjustment Register 1 0xC9
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME HZD
TYPE RW
RESET 0x14

BIT 7 6 5 4 3 2 1 0
NAME HPD
TYPE RW
RESET 0x02

Table 8-24: Delay Adjustment Register 1 Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
HZD HZD – HS Zero Delay Per Application Condition
Bit 15-8
These bits specifies the number of system clock
for HS zero delay period THS-ZERO.

The minimum value is 1.

HPD HPD – HS Prepare Delay Per Application Condition
Bit 7-0
These bits specifies the number of system clock
for HS prepare delay period THS-PREPARE.

The minimum value is 1.

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8.1.25 Delay Adjustment Register 2
Offset Address
DAR2 Delay Adjustment Register 2 0xCA
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME CZD
TYPE RW
RESET 0x28

BIT 7 6 5 4 3 2 1 0
NAME CPD
TYPE RW
RESET 0x03

Table 8-25: Delay Adjustment Register 2 Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
CZD CZD – Clock Zero Delay Per Application Condition
Bit 15-8
These bits specifies the number of system clock
for HS zero delay period TCLK-ZERO.

The minimum value is 1.

CPD CPD – Clock Prepare Delay Per Application Condition
Bit 7-0
These bits specifies the number of system clock
for HS prepare delay period TCLK-PREPARE.

The minimum value is 1.

Solomon Systech Aug. 2020 82/178 Rev 1.5 SSD2832

8.1.26 Delay Adjustment Register 3
Offset Address
DAR3 Delay Adjustment Register 3 0xCB
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME CPED
TYPE RW
RESET 0x04

BIT 7 6 5 4 3 2 1 0
NAME CPTD
TYPE RW
RESET 0x16

Table 8-26: Delay Adjustment Register 3 Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
CPED CPED – Clock Pre Delay Per Application Condition
Bit 15-8
These bits specifies the number of system clock
for CLK pre delay period TCLK-PRE.

The minimum value is 1.

CPTD CPTD – Clock Prepare Delay Per Application Condition
Bit 7-0
These bits specifies the number of system clock
for CLK post delay period TCLK-POST.

The minimum value is 1.

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8.1.27 Delay Adjustment Register 4
Offset Address
DAR4 Delay Adjustment Register 4 0xCC
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME CTD
TYPE RW
RESET 0x0A

BIT 7 6 5 4 3 2 1 0
NAME HTD
TYPE RW
RESET 0x0A

Table 8-27: Delay Adjustment Register 4 Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
CTD CTD – Clock Pre Delay Per Application Condition
Bit 15-8
These bits specifies the number of system clock
for CLK trail delay period TCLK-TRAIL.

The minimum value is 1.

HTD HTD – Clock Prepare Delay Per Application Condition
Bit 7-0
These bits specifies the number of system clock
for HS trail delay period THS-TRAIL.

The minimum value is 1.

Solomon Systech Aug. 2020 84/178 Rev 1.5 SSD2832

8.1.28 Delay Adjustment Register 5
Offset Address
DAR5 Delay Adjustment Register 5 0xCD
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME WUD[15:8]
TYPE RW
RESET 0x10

BIT 7 6 5 4 3 2 1 0
NAME WUD[7:0]
TYPE RW
RESET 0x00

Table 8-28: Delay Adjustment Register 5 Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
WUD WUD – Wake Up Delay Per Application Condition
Bit 15-0
These bits specifies the number of clock cycles
for wake up delay period TWAKEUP. The
delay is used to wake up the MIPI slave from
ULPS state. The clock is the low power clock.

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8.1.29 Delay Adjustment Register 6
Offset Address
DAR6 Delay Adjustment Register 6 0xCE
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME TGO
TYPE RO RO RO RO RW
RESET 0x0 0x0 0x0 0x0 0x4

BIT 7 6 5 4 3 2 1 0
NAME TGET
TYPE RO RO RO RO RW
RESET 0x0 0x0 0x0 0x0 0x5

Table 8-29: Delay Adjustment Register 6 Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-12
TGO TGO – TA Go Delay Per Application Condition
Bit 11-8
These bits specifies the number of TLPX for TA
go delay period TTA-GO.
Reserved Reserved Not Applicable
Bit 7-4
TGET TGET – TA Get Delay Per Application Condition
Bit 3-0
These bits specifies the number of TLPX for TA
get delay period TTA-GET.

Solomon Systech Aug. 2020 86/178 Rev 1.5 SSD2832

8.1.30 HS TX Timer Register 1
Offset Address
HTTR1 HS TX Timer Register 1 0xCF
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME HTT_L[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME HTT_L[7:0]
TYPE RW
RESET 0x00

Table 8-30: HS TX Timer Register 1 Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
HTT_L HTT_L – HS TX Timer Low Per Application Condition
Bit 15-0
These bits are the lower 16 bits of the HTT.

These bits specify the HS TX timer timeout

value. PLL reference clock is used to increment
an internal timer. The timer starts when the
SSD2832 enters HS transmit mode. When the
SSD2832 exits from HS transmit mode, the
timer will be reset. If the timer expires before
the end of HS transmission, the SSD2832 will
signal an error and switch to LP mode to
continue the transmission. At the same time, the
HS bit will be cleared to 0. Software
intervention is required so that the SSD2832 can
go back to proper HS transmission mode.

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8.1.31 HS TX Timer Register 2
Offset Address
HTTR2 HS TX Timer Register 2 0xD0
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME HTT_H[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME HTT_H[7:0]
TYPE RW
RESET 0x00

Table 8-31: HS TX Timer Register 2 Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
HTT_H HTT_H – HS TX Timer High Per Application Condition
Bit 15-0
These bits are the higher 16 bits of the HTT.

These bits specify the HS TX timer timeout

value. PLL reference clock is used to increment
an internal timer. The timer starts when the
SSD2832 enters HS transmit mode. When the
SSD2832 exits from HS transmit mode, the
timer will be reset. If the timer expires before
the end of HS transmission, the SSD2832 will
signal an error and switch to LP mode to
continue the transmission. At the same time, the
HS bit will be cleared to 0. Software
intervention is required so that the SSD2832 can
go back to proper HS transmission mode.

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8.1.32 TE Status Register
Offset Address
TESR TE Status Register 0xD3
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
TE_OUT_ TE_OUT_ TE_IN_SE TE_IN_SE
NAME CMD_BC TER1 TER0
SEL1 SEL0 L1 L0
TYPE RO RW RW RW RW RW RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-32: TE Status Register Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-7
CMD_BC CMD_BC – Command Broadcast 0 - No Broadcast
Bit 6 1 - Broadcast
This bit select whether to broadcast the 2C/3C
content from MIPITX0 to MIPITX1 when the
configuration is 1x2(TX_DUAL=1) for MCU.
TE_OUT_SE Reserved Not Applicable
L1
Bit 5
TE_OUT_SE TE_OUT_SEL0 – TE output from MIPITX0 0 - Internal TE is sent to
L0 TE_OUT_0 pin
Bit 4 This bit select whether to send the TE output 1 - Reserved
from MIPITX0 via TE_OUT0 pin.
TE_IN_SEL Reserved Not Applicable
1
Bit 3
TE_IN_SEL TE_IN_SEL0 – TE input from MIPITX0 0 - TE is taken from TE_IN_0 pin
0 1 - TE is taken from MIPITX0
Bit 2 This bit select which TE input to be used for
pulse shaping.
TE_RESP1 Reserved Not Applicable
Bit 1
TE_RESP0 TE_RESP0 – TE Response from MIPITX0 0 –TE response has not been
Bit 0 received
This bit reflects whether a TE response has been 1 – TE response has been
received or not. Once a TE response is received, received

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 Name Description Setting
this bit will be set to 1. At the same time, the
output TE signal will go high. The host
processor can write 1 to clear this bit. Once the
bit is cleared, the TE signal will go low.

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8.1.33 SPI Read Register
Offset Address
SRR SPI Read Register 0xD4
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME RRA
TYPE RW
RESET 0xFA

Table 8-33: SPI Read Register Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-8
RRA RRA – Register Read Address Per Application Condition
Bit 7-0
These bits specify the address of the register to
be read through the SPI interface, when the
interface is SPI 8-bit (either 3 wire or 4 wire).

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8.1.34 PLL Lock Register
Offset Address
PLR PLL Lock Register 0xD5
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME LOCK[15:8]
TYPE RW
RESET 0x14

BIT 7 6 5 4 3 2 1 0
NAME LOCK[7:0]
TYPE RW
RESET 0x50

Table 8-34: PLL Lock Register Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-16
LOCK LOCK – Lock Counter Per Application Condition
Bit 15-0
These bits specify the PLL lock range in term of
PLL reference frequency. The maximum PLL
lock period is 500us and the default setting
assumed the reference clock is 10Mhz.

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8.1.35 Test Register
Offset Address
TR Test Register 0xD6
BIT 31 30 29 28 27 26 25 24
NAME EHS
TYPE RO RO RO RW RW
RESET 0x0 0x0 0x0 0x1 0x0

BIT 23 22 21 20 19 18 17 16
NAME COMP_SLICE
TYPE RW RO RW
RESET 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
DIS_CON
NAME TM EIC
T
TYPE RW RW RW
RESET 0x0 0x00 0x1

BIT 7 6 5 4 3 2 1 0
NAME PNB END CO
TYPE RW RW RW
RESET 0x01 0x0 0x1

Table 8-35: Test Register Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-29
EHS EHS – Early High Speed clock 0 - disable
Bit 28 1 - enable
This bit is used to allow MIPI output to enter HS
1 line earlier before the video data transmission.
Reserved Reserved Not Applicable
Bit 27-21
Reserved Reserved Not Applicable
Bit 20
COMP_SLI COMP_SLICE – Number of Compressed Slice 0 – 1 slice per line
CE per Line ..
Bit 19-16 15 –16 slices per line
These bits indicate the number of slice per line
when the input video stream is compressed data.
TM TM – Test Mode 00 – Normal mode
Bit 15-14 01 – Inject CRC error
These bits selects whether to inject CRC/ECC 10 – Inject 1 bit ECC error
error for the outgoing streams. They are used for 11 – Inject 2 bit ECC error
debugging purpose only. They should be set to
00 in normal mode.
EIC EIC – Error Injection Control Per Application Condition
Bit 13-9
These bits control the position of the error being
injected for testing. It is only applicable when
TM is 01.

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 Name Description Setting
DIS_CONT DIS_CONT – Disable Contention input from 0 – Enable
Bit 8 Analog 1 – Disable

This bit selects whether to ignore the error

contention signals output from the Phy.

PNB PNB – Packet Number during Blanking Per Application Condition

Bit 7-2
These bits control the number of packet to send
during video mode blanking period.
END END – Endian-ness 0 – Least significant byte sent first
Bit 1 1 – Most significant byte sent first
This bit specifies the endian-ness of the data
transmitted over the serial link. During video
mode transmission, this bit must be set to 0 so as
to follow the MIPI DSI specification.
CO CO – Color Order 0 – RGB. B is in the higher
Bit 0 portion of the pixel
This bit specifies the order of the color 1 – BGR. R is in the higher
component in the pixel. During video mode portion of the pixel
transmission, this bit must be set to 1 so as to
follow the MIPI DSI specification.

Example: 24-bit arrangement

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8.1.36 TE Count Register
Offset Address
TECR TE Count Register 0xD7
BIT 31 30 29 28 27 26 25 24
NAME TEC1[15:8]
TYPE RW
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME TEC1[7:0]
TYPE RW
RESET 0x01

BIT 15 14 13 12 11 10 9 8
NAME TEC0[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME TEC0[7:0]
TYPE RW
RESET 0x01

Table 8-36: TE Count Register Description

Name Description Setting
TEC1 TEC1 – TE Counter for MIPITX1 Per Application Condition
Bit 31-16
These bits determines the pulse width of the
output TE signal. A counter will be started after
the TE signal goes to 1. When the counter
reaches the value in TEC1 field, the TE signal
will be set to 0. The counter uses the PLL
reference clock to do counting.

The minimum value is 1.

TEC0 TEC0 – TE Counter for MIPITX0 Per Application Condition
Bit 15-0
These bits determines the pulse width of the
output TE signal. A counter will be started after
the TE signal goes to 1. When the counter
reaches the value in TEC0 field, the TE signal
will be set to 0. The counter uses the PLL
reference clock to do counting.

The minimum value is 1.

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8.1.37 Analog Control Register 1
Offset Address
ACR1 Analog Control Register 1 0xD8
BIT 31 30 29 28 27 26 25 24
THFT_T THFT_TL LPTX_DS
NAME EN_REG HSTX_RO_IN
LFT1 FT0 [2]
TYPE RW RW RW RW RW
RESET 0x0 0x0 0x1 0x5 0x0

BIT 23 22 21 20 19 18 17 16
NAME LPTX_DS[1:0] BG_TRIM_V0P6
TYPE RW RW RW
RESET 0x0 0x3 0x4

BIT 15 14 13 12 11 10 9 8
BG_IDUT
NAME BG_TC BG_TEN BG_TRIM_0P5
Y[2]
TYPE RW RW RW RW
RESET 0x4 0x0 0x3 0x1

BIT 7 6 5 4 3 2 1 0
NAME BG_IDUTY[1:0] BG_IREG BG_ISEL EN_BG
TYPE RW RW RW RW
RESET 0x0 0x1 0x4 0x1

Table 8-37: Analog Control Register 1 Description

Name Description Setting
THFT_TLF THFT_TLFT1 – Low Power Receiver Input Per Application Condition
T1 Threshold High/Low Adjust Bit 1
Bit 31
THFT_TLF THFT_TLFT0 – Low Power Receiver Input Per Application Condition
T0 Threshold High/Low Adjust Bit 0
Bit 30
EN_REG EN_REG – 0.5V LDO enable Per Application Condition
Bit 29
HSTX_RO_I HSTX_RO_IN – Driver output resistance Per Application Condition
N control
Bit 28-25
LPTX_DS LPTX_DS – Low Power Transmitter Drive Per Application Condition
Bit 24-22 Strength
BG_TRIM_ BG_TRIM_V0P6 – Voltage trimming bits Per Application Condition
V0P6
Bit 21-19
Reserved Reserved Not Applicable
Bit 18-16
BG_TC BG_TC – Temperature coefficient Per Application Condition
Bit 15-13 programming bits of bandgap
BG_TEN BG_TEN – Bandgap Test Enable Per Application Condition
Bit 12
BG_TRIM_0 BG_TRIM_0P5 – Voltage trimming bits of Per Application Condition
P5 0.5V LDO
Bit 11-9

Solomon Systech Aug. 2020 96/178 Rev 1.5 SSD2832

 Name Description Setting
BG_IDUTY BG_IDUTY – Biasing current adjustment of Per Application Condition
Bit 8-6 duty cycle regulation circuit
BG_IREG BG_IREG – Biasing current adjustment of Per Application Condition
Bit 5-4 0.5V LDO
BG_ISEL BG_ISEL – Biasing current adjustment of Per Application Condition
Bit 3-1 contention detection
EN_BG EN_BG – Bandgap Enable Per Application Condition
Bit 0

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8.1.38 RGB Interface Control Register 7
Offset Address
RICR7 RGB Interface Control Register 7 0xDD
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME VEC XEQ1 XEQ0
TYPE RO RO RO RO RO RW RWAC RWAC
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME VBN VFN
TYPE RW RW
RESET 0x0 0x0

Table 8-38: RGB Interface Control Register 7 Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-11
VEC VEC – Video Enable Control 0 - Any command received will
Bit 10 output immediately if there is no
This bit controls how command is handled video packet to send.
during video mode, VEN.
1 - Any command received will
only be output during the blanking
period after first video packet is
received. If there is no video
packet to be sent, the command is
held.
XEQ1 XEQ1 – Execute Queue for MIPITX1 0 - Do nothing
Bit 9 1 - Send Execute Queue Packet
This bit will cause SSD2832 to generate (0x16) at the last line of the
Execute Queue Packet (0x16) at the last line of current frame, after hsync.
the frame, after hsync packet. It will be cleared
when Execute Queue Packet is sent out.

This bit is auto cleared by hardware.

XEQ0 XEQ – Execute Queue for MIPITX0 0 - Do nothing
Bit 8 1 - Send Execute Queue
This bit will cause SSD2832 to generate Packet (0x16) at the last line of the
Execute Queue Packet (0x16) at the last line of current frame, after hsync.
the frame, after hsync packet. It will be cleared
when Execute Queue Packet is sent out.

This bit is auto cleared by hardware.

Solomon Systech Aug. 2020 98/178 Rev 1.5 SSD2832

 Name Description Setting
VBN VBN – Vertical Back Porch Non Video Data Per Application Condition
Bit 7-4 Window

These fields specify the number of vertical back

porch counting backward from the first vertical
active line in which non-video data is not
allowed to be sent via MIPI link.
This field is only valid when VEN is 1 and the
interface setting is RGB + SPI (if_sel[0] = 0).

This field should not larger than VBP

VFN VFN – Vertical Front Porch Non Video Data Per Application Condition
Bit 3-0 Window

These fields specify the number of vertical front

porch counting forward from the last vertical
active line in which non-video data is not
allowed to be sent via MIPI link.
This field is only valid when VEN is 1 and the
interface setting is RGB + SPI (if_sel[0] = 0).

This field should not larger than VFP.

SSD2832 Rev 1.5 99/178 Aug. 2020 Solomon Systech

8.1.39 INOUT Configuration Control Register
Offset Address
IOCR INOUT Configuration Register 0xDE
BIT 31 30 29 28 27 26 25 24
MCU_SW MCU_SW BIT_SWA
NAME
AP1 AP0 P1
TYPE RO RO RO RO RO RW RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
BIT_SW PIXEL_S PIXEL_S
NAME
AP0 WAP1 WAP0
TYPE RW RW RW RW RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
TX_REA
NAME TX_WRITE TX_DUAL TX_LS1 TX_LS0
D
TYPE RW RW RW RW RW
RESET 0x0 0x1 0x0 0x0 0x0

Table 8-39: INOUT Configuration Register Description

Name Description Setting
Reserved Reserved Not Applicable
Bit 31-27
Reserved Reserved Not Applicable
Bit 26
MCU_SWA MCU_SWAP0 – MCU data swap for MCU 0 – No Swap
P0 1 –Swap MCU data MSB to
Bit 25 This bit defines how the SSD2832 interpret the LSB
MCU input.
BIT_SWAP1 Reserved Not Applicable
Bit 24
BIT_SWAP0 BIT_SWAP0 – RGB bit swap for RGB 0 – No Swap
Bit 23 1 –Swap RGB pixel MSB to
This bit defines how the SSD2832 interpret the LSB
RGB video input.
PIXEL_SW Reserved Not Applicable
AP1
Bit 22
PIXEL_SW BIT_SWAP0 – RGB pixel swap for RGB 0 – No Swap
AP0 1 –Swap RGB pixel higher and
Bit 21 This bit defines how the SSD2832 interpret the lower
RGB video input.
Reserved Reserved Not Applicable
Bit 20
Reserved Reserved Not Applicable

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 Name Description Setting
Bit 19-18
Reserved Reserved Not Applicable
Bit 17-16
Reserved Reserved Not Applicable
Bit 15-8
TX_READ TX_READ – TX read 0 - Read from MIPITX0
Bit 7 1 - Read from MIPITX1
This bit determines the destination of the read
command when SSD2832 is configured as Keep at 0 for MCU input.
RGB+SPI input.
TX_WRITE TX_WRITE – TX write 00 - Discard
Bit 6-5 01 - Write to MIPITX0
This bit determines the destination of the write 10 - Write to MIPITX1
command when SSD2832 is configured as 11 - Write to MIPITX0 and
RGB+SPI input. MIPITX1

Keep at 01 for MCU input.

TX_DUAL TX_DUAL – MIPITX dual mode 0 – Single mode
Bit 4 1 – Dual mode
This bit defines the dual/single mode of
MIPITX.
TX_LS1 TX_LS1 – Lane Select for MIPITX1 00 – 1 lane mode
Bit 3-2 01 – 2 lane mode
These bits define the number of lane to be used 10 – 3 lane mode
for MIPITX1 in SSD2832. 11 – 4 lane mode(for DPHY only)
TX_LS0 TX_LS0 – Lane Select for MIPITX0 00 – 1 lane mode
Bit 1-0 01 – 2 lane mode
These bits define the number of lane to be used 10 – 3 lane mode
for MIPITX0 in SSD2832. 11 – 4 lane mode(for DPHY only)

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8.1.40 APB Write Register
Offset Address
AWR APB Write Register 0xE0
BIT 47 46 45 44 43 42 41 40
NAME DATA[31:24]
TYPE W
RESET 0x00

BIT 39 38 37 36 35 34 33 32
NAME DATA[23:16]
TYPE W
RESET 0x00

BIT 31 30 29 28 27 26 25 24
NAME DATA[15:8]
TYPE W
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME DATA[7:0]
TYPE W
RESET 0x00

BIT 15 14 13 12 11 10 9 8
NAME ADDR[15:8]
TYPE W
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME ADDR[7:0]
TYPE W
RESET 0x00

Table 8-40: Delay Adjustment Register Description

Name Description Setting
DATA DATA – 32-bit write data for APB Refer to APB write section
Bit 47-16
ADDR ADDR – 16-bit address for APB write/read Refer to APB write section
Bit 15-0

Solomon Systech Aug. 2020 102/178 Rev 1.5 SSD2832

8.1.41 APB Read Register
Offset Address
ARR APB Read Register 0xE1
BIT 31 30 29 28 27 26 25 24
NAME DATA[31:24]
TYPE R
RESET 0x0

BIT 23 22 21 20 19 18 17 16
NAME DATA[23:16]
TYPE R
RESET 0x0

BIT 15 14 13 12 11 10 9 8
NAME DATA[15:8]
TYPE R
RESET 0x0

BIT 7 6 5 4 3 2 1 0
NAME DATA[7:0]
TYPE R
RESET 0x0

Table 8-41: APB Read Register Description

Name Description Setting
DATA DATA – 32 bits read data Refer to APB read section
Bit 31-0

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 8.2 Local (APB) Register Descriptions
The APB registers have 16 bit address, of which the most significant 4 bits represent the base address
of the APB peripheral, and the least significant 16 bits represent the offset within the APB peripheral.
The table below shows the APB peripherals and their respective base address & address range.

Address Module

0x0000 – 0x0FFF SCM

0x1000 – 0x1FFF CPHY Analog Front End 0

0x2000 – 0x2FFF CPHY Analog Front End 1

0x3000 – 0x3FFF Reserved

0x4000 – 0x4FFF Reserved

0x5000 – 0x5FFF Video BIST

0x6000 – 0x6FFF Pixel Peek

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8.2.1 SCM Registers Descriptions

8.2.1.1 SCM Device Identification Register

Base Address: 0x0000
SCM _IDR SCM Identification Register Offset Address: 0x000
BIT 31 30 29 28 27 26 25 24
NAME id[31:24]
RO
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x1 0x0 0x1 0x0 0x0 0x0

BIT 23 22 21 20 19 18 17 16
NAME id[23:16]
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x1 0x1 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME id[15:8]
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0

BIT 7 6 5 4 3 2 1 0
NAME id[7:0]
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1

Table 8-42: Device Identification Register Description

Name Description Setting
ID[31:0]
Chip ID 0x2832_0001
Bit31-0

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8.2.1.2 SCM Miscellaneous Control Register
Base Address: 0x0000
SCM_MISC SCM Miscellaneous Control Register Offset Address: 0x010
BIT 31 30 29 28 27 26 25 24
NAME ckmon lpstate
TYPE RO RO RW RW RW RW RW
RESET 0x0 0x0 0x1 0x0 0x1 0x1 0x0

BIT 23 22 21 20 19 18 17 16
NAME v2c
TYPE RW RW RW RW RW RW
RESET 0x2 0x1 0x0 0x0 0x0 0x0

BIT 15 14 13 12 11 10 9 8
NAME
TYPE RW RW RW RW
RESET 0x0 0x3 0x1 0x0

BIT 7 6 5 4 3 2 1 0
NAME flip1 flip0
TYPE RW RW RW RW RW RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0

Table 8-43: SCM Miscellaneous Control Description

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 Name Description Setting
Reserved Not Applicable
Reserved
Bit31-30
Clock Monitor on TE_OUT0 – Per Application Condition
clkmon
This bit enable the TE_OUT0 to be used as
Bit29
clkout monitor signals
LP State – 0=LP00
lpstate
This bit controls the state of the link when the 1=LP11
Bit28
chip is powered down
Reserved
Reserved Not Applicable
Bit 27-17
v2c Video to Cmd – Indicates whether video is 0=Disable
Bit 16 converted to 2C/3C commands. 1=Enable
Reserved Not Applicable
Reserved
Bit 15-12
Reserved Not Applicable
Reserved
Bit 11-9
Reserved Reserved Not Applicable
Bit 8
MIPI Left/Right Flip for DSI1 – 0x0 = Data received from read
mtx_flip1 This bit configures the left and right image swap from left to right (Default)
Bit 7 at the MIPI output. 0x1 = Data received from read
from right to left
MIPI Left/Right Flip for DSI0 – 0x0 = Data received from read
mtx_flip0 This bit configures the left and right image swap from left to right (Default)
Bit 6 at the MIPI output. 0x1 = Data received from read
from right to left
Reserved Reserved Not Applicable
Bit 5-4
Reserved Reserved Not Applicable
Bit 3
Reserved Reserved Not Applicable
Bit 2-1
Reserved Reserved Not Applicable
Bit 0

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8.2.1.3 SCM Scratch Register
Base Address: 0x0000
SCM_SCRATCH SCM Scratch Register Offset Address: 0x014
BIT 31 30 29 28 27 26 25 24
NAME scratch[31:24]
TYPE RW
RESET 0x00

BIT 23 22 21 20 19 18 17 16
NAME scratch[23:16]
TYPE RW
RESET 0x00

BIT 15 14 13 12 11 10 9 8
NAME scratch[15:8]
TYPE RW
RESET 0x00

BIT 7 6 5 4 3 2 1 0
NAME scratch0[7:0]
TYPE RW
RESET 0x00

Table 8-44: SCM Scratch Register Description

Name Description Setting
scratch Scratch Register – User can use this register to Per Application Condition
Bit 31-0 store any value

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8.2.2 CPHY Analog Front End Registers Descriptions
The following register descriptions are for a single CPHY. Users need to use the correct base address
to program the desired CPHY (0 or 1)

8.2.2.1 CPHY Transmit Global Register 1

Base Address: 0x1000/0x2000
CPHY_TX_GR1 CPHY Transmit Global Register 1 Offset Address: 0x000
BIT 31 30 29 28 27 26 25 24
NAME sym1_pp sym0_pp
TYPE RO RO RW RW
RESET 0x0 0x0 0x3 0x3
BIT 23 22 21 20 19 18 17 16
NAME dir post_len
TYPE RO RO RO RW
RESET 0x0 0x0 0x0 0x08
BIT 15 14 13 12 11 10 9 8
NAME enb_pp bplen
TYPE RW RO RW
RESET 0x0 0x0 0x1e
BIT 7 6 5 4 3 2 1 0
ben_dsi_se
NAME clk_buf_sel ben_ln2 ben_ln1 ben_ln0 ben
l
TYPE RW RO RW RW RW RW RW
RESET 0x01 0x0 0x0 0x0 0x0 0x0 0x0
Table 8-45: CPHY TX Global Register 1 Description
Name Description Setting
ben Burst Enable – Start the high speed test burst 0 = Disabled
Bit 0 1 = Enabled
ben_ln0 Burst enable for lane 0 0 = Disabled
Bit 1 Individual start high speed test for lane 0 1 = Enabled
ben_ln1 Burst enable for lane 1 0 = Disabled
Bit 2 Individual start high speed test for lane 1 1 = Enabled
ben_ln2 Burst enable for lane 2 0 = Disabled
Bit 3 Individual start high speed test for lane 2 1 = Enabled
ben_dsi_sel Burst enable test DSI select 0 = DSI 0
Bit 4 Determine which DSI is select for either PRBS 1 = DSI 1
or Loopback Test
Reserved Reserved Not Applicable
Bit 5
clk_buf_sel Transmitter clock buffer enable 00 = XTAL_IN_buf_en low all the
Bit 7-6 time
01 = XTAL_IN_buf_en follow
tx_hs_en (default)
10 = XTAL_IN_buf_en high all
the time
11 = Reserved
bplen Begin Preamble Length (t3-PREBEGIN) – Per Application Condition
Bit 13-8 The number of symbols in the PreBegin section
of the preamble is:
(begin_Preamble_Length+1)*7.
Reserved Reserved Not Applicable
Bit 14

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enb_pp Enable Preamble Progseq (t3-PROGSEQ) – 0 = Disabled
Bit 15 Enable or disable the Preamble Programmable 1 = Enabled
Sequence
post_len Post Length (t3-POST) – The number of Per Application Condition
Bit 20-16 symbol in the Post field is:
(post_length+1)*7
Reserved Reserved Not Applicable
Bit 22-21
dir Direction 0: TX
Bit 23 Indication the TXLP direction 1: RX
sym0_pp Symbol 0 preamble progseq – symbol value Per Application Condition
Bit 26-24 for Symbol 0.
Only 000 to 100 is allowed.
sym1_pp Symbol 1 preamble progseq – symbol value Per Application Condition
Bit 29-27 for Symbol 1.
Only 000 to 100 is allowed.
Reserved Reserved Not Applicable
Bit 31-30

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8.2.2.2 CPHY Transmit Global Register 2
Base Address: 0x1000/0x2000
CPHY_TX_GR2 CPHY Transmit Global Register 2 Offset Address: 0x004
BIT 31 30 29 28 27 26 25 24
NAME sym9_pp sym8_pp
TYPE RO RO RW RW
RESET 0x0 0x0 0x3 0x3
BIT 23 22 21 20 19 18 17 16
NAME sym7_pp sym6_pp
TYPE RO RO RW RW
RESET 0x0 0x0 0x3 0x3
BIT 15 14 13 12 11 10 9 8
NAME sym5_pp sym4_pp
TYPE RO RO RW RW
RESET 0x0 0x0 0x3 0x3
BIT 7 6 5 4 3 2 1 0
NAME sym3_pp sym2_pp
TYPE RO RO RW RW
RESET 0x0 0x0 0x3 0x3
Table 8-46: CPHY TX Global Register 2 Description
Name Description Setting
sym2_pp Symbol 2 preamble progseq – symbol value Per Application Condition
Bit 2-0 for Symbol 2
Only 000 to 100 is allowed.
sym3_pp Symbol 3 preamble progseq – symbol value Per Application Condition
Bit 5-3 for Symbol 3.
Only 000 to 100 is allowed.
Reserved Reserved Not Applicable
Bit 7-6
sym4_pp Symbol 4 preamble progseq – symbol value Per Application Condition
Bit 10-8 for Symbol 4.
Only 000 to 100 is allowed.
Sym5_pp Symbol 5 preamble progseq – symbol value Per Application Condition
Bit 13-11 for Symbol 5.
Only 000 to 100 is allowed.
Reserved Reserved Not Applicable
Bit 15-14
sym6_pp Symbol 6 preamble progseq – symbol value Per Application Condition
Bit 18-16 for Symbol 6.
Only 000 to 100 is allowed.
sym7_pp Symbol 7 preamble progseq – symbol value Per Application Condition
Bit 21-19 for Symbol 7.
Only 000 to 100 is allowed.
Reserved Reserved Per Application Condition
Bit 23-22
sym8_pp Symbol 8 preamble progseq – symbol value Per Application Condition
Bit 26-24 for Symbol 8.
Only 000 to 100 is allowed.
sym9_pp Symbol 9 preamble progseq – symbol value Per Application Condition
Bit 29-27 for Symbol 9.
Only 000 to 100 is allowed.
Reserved Reserved Not Applicable
Bit 31-30

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8.2.2.3 CPHY Transmit Global Register 3
Base Address: 0x1000/0x2000
CPHY_TX_GR3 CPHY 3 Register Offset Address: 0x008
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
BIT 15 14 13 12 11 10 9 8
NAME sym13_pp sym12_pp
TYPE RO RO RW RW
RESET 0x0 0x0 0x3 0x3
BIT 7 6 5 4 3 2 1 0
NAME sym11_pp sym10_pp
TYPE RO RO RW RW
RESET 0x0 0x0 0x3 0x3
Table 8-47: CPHY TX Global Register 3 Description
Name Description Setting
sym10_pp Symbol 10 preamble progseq – symbol value Per Application Condition
Bit 2-0 for Symbol 10
Only 000 to 100 is allowed.
sym11_pp Symbol 11 preamble progseq – symbol value Per Application Condition
Bit 5-3 for Symbol 11
Only 000 to 100 is allowed.
Reserved Reserved Not Applicable
Bit 7-6
sym12_pp Symbol 12 preamble progseq – symbol value Per Application Condition
Bit 10-8 for Symbol 12
Only 000 to 100 is allowed.
sym13_pp Symbol 13 preamble progseq – symbol value Per Application Condition
Bit 13-11 for Symbol 13
Only 000 to 100 is allowed.
Reserved Reserved Not Applicable
Bit 31-14

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8.2.2.4 CPHY Transmit Global Register 4
Base Address: 0x1000/0x2000
CPHY_TX_GR4 CPHY Transmit Global Register 4 Offset Address: 0x00C
BIT 31 30 29 28 27 26 25 24
NAME t_ulps_wu[15:8]
TYPE RW
RESET 0x20
BIT 23 22 21 20 19 18 17 16
NAME t_ulps_wu[7:0]
TYPE RW
RESET 0x00
BIT 15 14 13 12 11 10 9 8
NAME t_ta_go
TYPE RO RO RO RO RW
RESET 0x0 0x0 0x0 0x0 0x4
BIT 7 6 5 4 3 2 1 0
NAME t_ta_get
TYPE RO RO RO RO RW
RESET 0x0 0x0 0x0 0x0 0x5
Table 8-48: CPHY TX Global Register 4 Description
Name Description Setting
t_ta_get Turnaround Get (t-TA-GET) – Count in term Default value = 0x5
Bit 3-0 of tLPX for period that the new transmitter drives
the Bridge state (LP-000) after accepting control
during turnaround.
Reserved Reserved Not Applicable
Bit 7-4
t_ta_go Turnaround Go (t-TA-GO) – Count in term of Default value = 0x4
Bit 11-8 tLPX for period that the transmitter drives the
Bridge state (LP-000) before releasing control
during a link control
Reserved Reserved Not Applicable
Bit 15-12
t_ulps_wu ULPS Wakeup Timer (t-WAKEUP) – Time Default value = 0x2000
Bit 31-16 that a transmitter drives a Mark-1 stat prior to a
Stop state in order to initial an exit from ULPS.
Count using tLPX.

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8.2.2.5 CPHY Transmit Global Register 5
Base Address: 0x1000/0x2000
CPHY_TX_GR5 CPHY Transmit Global Register 5 Offset Address: 0x010
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
BIT 15 14 13 12 11 10 9 8
NAME t_hs_prepare
TYPE RW
RESET 0x01
BIT 7 6 5 4 3 2 1 0
NAME t_hs_exit
TYPE RO RO RW
RESET 0x0 0x0 0x10
Table 8-49: CPHY Transmit Global Register 5 Description
Name Description Setting
t_hs_exit HS Exit Timer (t-HS-EXIT) – Count in term Default value = 0x10
Bit 5-0 of double symbol clock for time to drive LP-11
following a HS burst
(t_hs_exit*symbol clock + 300ns)
Reserved Reserved Not Applicable
Bit 7-6
t_hs_prepare HS Prepare Timer (t-HS-PREPARE) - These Default value = 0x01
Bit 15-8 bits specifies the number of system clock for HS
prepare delay period
(t_hs_prepare*symbol clock)
Reserved Reserved Not Applicable
Bit 31-16

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8.2.2.6 CPHY Transmit Lane Register 1
Base Address: 0x1000/0x2000
CPHY_TX_LPR CPHY Transmit Loopback Register Offset Address: 0x0F0
BIT 31 30 29 28 27 26 25 24
NAME
TYPE R0 R0 R0 R0 R0 R0 R0 R0
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
BIT 23 22 21 20 19 18 17 16
NAME
TYPE R0 R0 R0 R0 R0 R0 R0 R0
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
BIT 15 14 13 12 11 10 9 8
NAME lptocnt
TYPE RW
RESET 0xF0
BIT 7 6 5 4 3 2 1 0
lp_byenc_
NAME lpcomp lpen lpstatus lpcon
ctrl
TYPE RW RW RO RO RW RO RO
RESET 0x0 0x0 0x0 0x0 0x1 0x0 0x0
Table 8-6: CPHY TX Loopback Register Description
Name Description Setting
Reserved Reserved Not Applicable
Bit 1-0
lp_byenc_ctr Loopback Bypass Encoder Control 0 = Not bypass
l To bypass encoder in serializer during loopback 1 = Bypass (default)
test
lpcon Loopback Failure 0 = Not lock
Bit 3 Indicate loopback failure condition 1 = Data Mismatch
lpstatus Loopback Status 0 = Fail
Bit 4 Indicate loopback test status 1 = Pass
Only valid during lpen=1
lpen Enable internal loopback test 0 = Disabled
Bit 5 1 = Enabled
lpcomp Loopback Lane Compare 0: Lane 0 (default)
Bit 7-6 Select which lane to compared for internal 1: Lane 1
loopback test 2: Lane 2
3: reserved
lptocnt Loopback Timeout Counter 0xF0 (default)
Bit 15-8 Set the timer to timeout if the SYNC WORD is
not found during the setting
Reserved Reserved Not Applicable
Bit 31-16

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8.2.2.7 CPHY Transmit Lane Register 2
Base Address: 0x1000/0x2000
CPHY_TX_LNR2 CPHY Transmit Lane Register 2 Offset Address: 0x104
BIT 31 30 29 28 27 26 25 24
NAME prbs_seed[17:16]
TYPE RO RO RO RO RO RO RW
RESET 0x0 0x0 0x0 0x0 0x0 0x0 0x2
BIT 23 22 21 20 19 18 17 16
NAME prbs_seed[15:8]
TYPE RW
RESET 0x78
BIT 15 14 13 12 11 10 9 8
NAME prbs_seed[7:0]
TYPE RW
RESET 0X9A
BIT 7 6 5 4 3 2 1 0
NAME prbs_pat debug_pat
TYPE RW RO RW
RESET 0x0 0x0 0x0
Table 8-8: CPHY TX Lane Register 2 Description
Name Description Setting
debug_pat Debug Pattern Default value = 0
Bit 3-0 0: select output of 16-to-7 Mapper (normal) or
PRBS pattern, as selected by
prbs_pattern
1: debug pattern is a sequence of 14 symbols
defined by programmable sequence of the
preamble
2: debug pattern is a sequence of wire
states that are defined by the same
programmable sequence of the preamble
prbs_pat PRBS Pattern Default value = 0
Bit 7-5 0: select tx_data_hs from Lane Distribution
Function (normal operation)
1-3: reserved for future use
4: select PRBS9
5: select PRBS11
6: select PRBS18
7: reserved for future use
prbs_seed PRBS Seed Default value = 0x789A
Bit 25-8 Used to initialize the seed of PRBS9, PRBS11 prbs_seed[7:0]: prsb_seed_0
and PRBS18 prbs_seed[15:8]: prbs_seed_1
prbs_seed[17:16]: prbs_seed_2
Reserved Reserved Not Applicable
Bit 31-26

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8.2.3 Video BIST Register Descriptions

8.2.3.1 Video BIST Register 0

Base Address: 0x5000
VBISTR0 Video BIST Register 0 Offset Address: 0x000
BIT 31 30 29 28 27 26 25 24
NAME VB_REPEAT_CNT[15:8]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME VB_REPEAT_CNT[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME VB_MODE{3:0} VB_CFG_MODE[1:0] VB_CSPF VB_EN
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
Table 8-50: Video BIST Register 0 Description
Name Description Setting
VB_REPEAT_CNT[15:0] Video BIST Repeat Count – These bits set the Please refer to 15.10Video BIST section
Bit 31-16 repeat count for video pattern generation. It will for more information.
have different meaning for different
VB_MODE.
Reserved Reserved Not Applicable
Bit15-8
VB_MODE[3:0] Video BIST Mode – These bits select the Video Please refer to Video BIST section for
Bit 7-4 BIST image pattern. more information.
VB_CFG_MODE[1:0] Video BIST Config Mode – These bits select 0 – Single data buffer mode (Normal)
Bit 3-2 the mode that video bist generate the pattern 1 – Dual data buffer mode (Odd/Even)
2 – Dual data buffer mode (Left/Right)
3 – Dual data buffer mode (Broadcast)
VB_CSPF Video BIST Color Swap per Frame – This bit 0 – Disable
Bit 1 enable the color swap per frame 1 – Enable
VB_EN Video BIST Enable – This bit enable the Video 0 – Disable
Bit 0 BIST function 1 – Enable

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8.2.3.2 Video BIST Register 1
Base Address: 0x5000
VBISTR1 Video BIST Register 1 Offset Address: 0x004
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME VB_COLOR_X_R[9:8]
TYPE RO RO RO RO RO RO RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME VB_COLOR_X_R[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
Table 8-51: Video BIST Register 1 Description
Name Description Setting
Reserved Reserved Not Applicable
Bit 31-10
VB_COLOR_X_R[9:0] Video BIST Color X Red Component – These 30bpp – [9:0]
Bit 9-0 bits specify the Color X Red Component. 24bpp – [7:0]

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8.2.3.3 Video BIST Register 2
Base Address: 0x5000
VBISTR2 Video BIST Register 2 Offset Address: 0x008
BIT 31 30 29 28 27 26 25 24
NAME VB_COLOR_X_G[9:8]
TYPE RO RO RO RO RO RO RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME VB_COLOR_X_G[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME VB_COLOR_X_B[9:8]
TYPE RO RO RO RO RO RO RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME VB_COLOR_X_B[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
Table 8-52: Video BIST Register 2 Description
Name Description Setting
Reserved Reserved Not Applicable
Bit 31–26
VB_COLOR_X_G[9:0] Video BIST Color X Green Component – These 30bpp – [9:0]
Bit 25–16 bits specify the Color X Red Component. 24bpp – [7:0]
Reserved Reserved Not Applicable
Bit 15–10
VB_COLOR_X_B[9:0] Video BIST Color X Blue Component – These 30bpp – [9:0]
Bit 9-0 bits specify the Color X Red Component. 24bpp – [7:0]

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8.2.3.4 Video BIST Register 3
Base Address: 0x5000
VBISTR3 Video BIST Register 3 Offset Address: 0x00C
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME VB_COLOR_Y_R[9:8]
TYPE RO RO RO RO RO RO RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME VB_COLOR_Y_R[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
Table 8-53: Video BIST Register 3 Description
Name Description Setting
Reserved Reserved Not Applicable
Bit 31–10
VB_COLOR_Y_R[9:0] Video BIST Color Y Red Component – These 30bpp – [9:0]
Bit 9-0 bits specify the Color X Red Component. 24bpp – [7:0]

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8.2.3.5 Video BIST Register 4
Base Address: 0x5000
VBISTR4 Video BIST Register 4 Offset Address: 0x010
BIT 31 30 29 28 27 26 25 24
NAME VB_COLOR_Y_G[9:8]
TYPE RO RO RO RO RO RO RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME VB_COLOR_Y_G[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME VB_COLOR_Y_B[9:8]
TYPE RO RO RO RO RO RO RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME VB_COLOR_Y_B[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
Table 8-54: Video BIST Register 4 Description
Name Description Setting
Reserved Reserved Not Applicable
Bit 31–26
VB_COLOR_Y_G[9:0] Video BIST Color Y Green Component – These 30bpp – [9:0]
Bit 25–16 bits specify the Color Y Red Component. 24bpp – [7:0]
Reserved Reserved Not Applicable
Bit 15–10
VB_COLOR_Y_B[9:0] Video BIST Color Y Blue Component – These 30bpp – [9:0]
Bit 9-0 bits specify the Color Y Red Component. 24bpp – [7:0]

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8.2.3.6 Video BIST Register 5
Base Address: 0x5000
VBISTR5 Video BIST Register 5 Offset Address: 0x014
BIT 31 30 29 28 27 26 25 24
NAME VB_X_START[15:8]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME VB_X_START[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME VB_X_END[15:8]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME VB_X_END[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
Table 8-55: Video BIST Register 5 Description
Name Description Setting
VB_X_START[15:0] Video BIST X Start – These bits define the X Per Application Condition
Bit 31–16 starting position.
VB_X_END[15:0] Video BIST X End – These bits define the X end Per Application Condition
Bit 15–0 position.

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8.2.3.7 Video BIST Register 6
Base Address: 0x5000
VBISTR6 Video BIST Register 6 Offset Address: 0x018
BIT 31 30 29 28 27 26 25 24
NAME VB_Y_START[15:8]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME VB_Y_START[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME VB_Y_END[15:8]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME VB_Y_END[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
Table 8-56: Video BIST Register 6 Description
Name Description Setting
VB_Y_START[15:0] Video BIST Y Start – These bits define the Y Per Application Condition, please
Bit 31–16 starting position.
refer to section 15 for reference.
VB_Y_END[15:0] Video BIST Y End – These bits define the Y end Per Application Condition, please
Bit 15–0 position.
refer to section 15 for reference.

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8.2.4 Pixel Peek Registers Descriptions

8.2.4.1 Pixel Peek Register 0

Base Address: 0x6000
PIXELPEEKR0 Pixel Peek Register 0 Offset Address: 0x000
BIT 31 30 29 28 27 26 25 24
NAME CURSOR_POSITION_Y[15:8]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME CURSOR_POSITION_Y[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME CURSOR_POSITION_X[15:8]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME CURSOR_POSITION_X[7:0]
TYPE RW RW RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
Table 8-57: Pixel Peek Register 0 Description
Name Description Setting
CURSOR_POSITION_Y[15:0] Cursor Position Y – These bits set the y- Per Application Condition
Bit 31–16 coordinate to measure
CURSOR_POSITION_X[15:0] Cursor Position X – These bits set the x- Per Application Condition
Bit 15–0 coordinate to measure

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8.2.4.2 Pixel Peek Register 1
Base Address: 0x6000
PIXELPEEKR1 Pixel Peek Register 1 Offset Address: 0x004
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
CURSOR
PREVEN
CURSOR _COLOR_
NAME T_UPDAT CURSOR_COLOR_RGB[2:0]
_VISIBLE DYNAMI
E
C
TYPE RO RO RW RW RW RW RW RW
RESET 0 0 0 0 0 0 0 0
0x0
Table 8-58: Pixel Peek Register 1 Description
Name Description Setting
Reserved Reserved Not Applicable
Bit 31–6
PREVENT_UPDATE Prevent Update – Set this bit before Per Application Condition
Bit 5 reading the values.
CURSOR_VISIBLE Cursor Visible – This bit enable cursor 0 = disable
Bit 4 display. 1 = enable
CURSOR_COLOR_DYNAMIC Cursor Color Dynamic – This bit enable 0 = disable
Bit 3 dynamic color for cursor 1 = enable
CURSOR_COLOR_BGR[2:0] Cursor Color BGR – These bits set the Per Application Condition
Bit 2–0 color for cursor (BGR, B on MSB).

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8.2.4.3 Pixel Peek Register 2
Base Address: 0x6000
PIXELPEEKR2 Pixel Peek Register 2 Offset Address: 0x008
BIT 31 30 29 28 27 26 25 24
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x00
BIT 23 22 21 20 19 18 17 16
NAME
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x00
BIT 15 14 13 12 11 10 9 8
NAME MEAS_VALUE_B[15:8]
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x00
BIT 7 6 5 4 3 2 1 0
NAME MEAS_VALUE_B[7:0]
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x00
Table 8-59: Pixel Peek Register 2 Description
Name Description Setting
Reserved Reserved Not Applicable
Bit 31–16
MEAS_VALUE_B[15:0] Measure Value B – Measured value for Blue. Per Application Condition
Bit 15–0

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8.2.4.4 Pixel Peek Register 3
Base Address: 0x6000
PIXELPEEKR3 Pixel Peek Register 3 Offset Address: 0x00C
BIT 31 30 29 28 27 26 25 24
NAME MEAS_VALUE_G[15:8]
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 23 22 21 20 19 18 17 16
NAME MEAS_VALUE_G[7:0]
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 15 14 13 12 11 10 9 8
NAME MEAS_VALUE_R[15:8]
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
BIT 7 6 5 4 3 2 1 0
NAME MEAS_VALUE_R[7:0]
TYPE RO RO RO RO RO RO RO RO
RESET 0 0 0 0 0 0 0 0
0x0
Table 8-60: Pixel Peek Register 3 Description
Name Description Setting
MEAS_VALUE_G[15:0] Measure Value G – Measured value for Green. Per Application Condition
Bit 31–16
MEAS_VALUE_R[15:0] Measure Value R – Measured value for Red. Per Application Condition
Bit 15–0

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9 MAXIMUM RATING
Table 9-1: Maximum Rating (Voltage Referenced to Vss)

Symbol Parameter Min Typ Max Unit

AVDD Power Supply for MIPI and PLL -0.3 - 1.44 V

VDD Core Power Supply -0.3 - 1.44 V

VDDIO I/O Power Supply -0.3 - 3.96 V

VDRV Power for MIPI TX Driver -0.3 - 1.44 V

VCIP Power for Bandgap -0.3 - 3.96 V

TSTG Storage Temperature -40 150 o

C

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10 DC OPERATION CONDICTION

Table 10-1 : Recommended Operating Conditions

Symbol Parameter Min Typ Max Unit

AVDD Analog Power Supply 1.17 1.3 1.43 V

AVDD_RC Analog Power Supply 1.17 1.3 1.43 V

VDD_CORE Digital Core Power Supply 1.17 1.3 1.43 V

I/O Power Supply 1.62 1.8 1.98 V

VDDIO
I/O Power Supply 1.62/2.7 1.8/3.3 1.98/3.6 V

TA Operating Temperature -40 25 85 o

C

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 10.1 DC CHARACTERISTIC

Symbol Parameter Test Condition Min Typ Max Unit

Current for all 1.3V

IDD_1.3V_active supplies for active Active Mode (Video Mode) - 165 300 mA
mode 4096x2160@60Hz,
Current for all 1.8V [email protected] X 6 lanes
IDD_1.8V_active supplies for active - 7 15 mA
mode

Current for all 1.3V

IDD_1.3V_powerdown supplies for power - 120 300 A
down mode Power Down mode
MIPITX off
Current for all 1.8V
IDD_1.8V_powerdown supplies for power - 300 600 A
down mode

Output High Voltage

VOH (CMOS)
(CMOS)
IOH = -2 ~ -16 mA VDDIO*80% - - V

Output Low Voltage

VOL (CMOS)
(CMOS)
IOL= 2 ~ 16 mA - - VDDIO*15% V

Input High Voltage

VIH (CMOS) - VDDIO*70% - - V
(CMOS)

Input Low Voltage

VIL (CMOS)
(CMOS)
- - - VDDIO*20% V

Tri-state Output
IOZ
Leakage Current
- -1 - +1 A

Input Leakage
IIN - -1 - +1 A
Current

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11 AC CHARACTERISTIC

11.1 Power Up Timing

Symbol Parameters Min Typ Max Units

Rise time for all 1.3V VDD supplies (10% to

TVDD13_RISE 1 - 10 ms
90%)

Rise time for all 1.8V VDD supplies (10% to

TVDD18_RISE 1 - 10 ms
90%)

Time from 1.3V supplies on to 1.8V and 3.3V

supplies on.
TVDD18_ON Note: If VDD18 is applied before VDD13 is applied, there -5 - 30 ms
could be up to 1mA of additional leakage during the period
when VDD13 is still not available.

11.2 RESET Timing

Symbol Parameters Min Typ Max Units

TRESET RESET_IN “Low” Pulse Width 10 - - us

11.3 Interface Timing

11.3.1 MCU Interface (Type A) Timing

Symbol Parameter Min Typ Max Unit

TMC MCU clock frequency - - 160 Mhz
tCYCLE_W
Clock Cycle Time(Write) 1 - - TMC
R
tCYCLE_RD Clock Cycle Time(Read) 8 - - TMC
pwCSL Control Pulse Low Width 0.5 - - TMC
pwCSH Control Pulse High Width 0.5 - - TMC
tAS Address Setup Time 1.6 - - ns
tAH Address Hold Time 1.6 - - ns
tDSW Data Setup Time 1.6 - - ns
tDHW Data Hold Time 1.6 - - ns
tACC Data Access Time 12 - - ns
tDHR Read Data Hold time tCYCLE_RD - -
ns
/2
tR Rise time 1 - - ns
tF Fall time 1 - - ns

Table 11-1 MCU Interface (Type A) Timing Characteristics

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 VIH VIH
dcx
VIL VIH
tAS
tAH
VIH VIH
rwx
VIL VIL

VIH VIH
tR
csx tF
VIL VIL
tCYCLE_WR /tCYCLE_RD
pwCSH pwCSL
e

tDHW
tDSW
VIH VIH
data
(WRITE) Valid Data
VIL VIL

tACC tDHR
data VIH VIH
(READ)
Valid Data
VIL VIL

Figure 11-1 MCU Interface (Type A) Timing Diagram

Note: VIL and VIH refers to DC CHARACTERISTICS

Note: When PLL is off (0xB0h 0x0000h), max. clock freq. = OSC or crystal freq.

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11.3.2 MCU Interface (Type B) Timing

Symbol Parameter Min Typ Max Unit

TMC MCU Clock Frequency - - 160 Mhz
tCYCLE_W
Clock Cycle Time(Write) 1 - - TMC
R
tCYCLE_RD Clock Cycle Time(Read) 8 - - TMC
pwCSL Control Pulse Low Width 0.5 - - TMC
pwCSH Control Pulse High Width 0.5 - - TMC
tAS Address Setup Time 1.6 - - ns
tAH Address Hold Time 1.6 - - ns
tDSW Data Setup Time 1.6 - - ns
tDHW Data Hold Time 1.6 - - ns
tACC Data Access Time 12 - - ns
tDHR Read Data Hold time tCYCLE_RD - -
ns
/2
tR Rise time 1 - - Ns
tF Fall time 1 - - Ns
Table 11-2: MCU Interface (Type B) Timing Characteristics

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Note: When PLL is off (0xB0h 0x0000h), max. clock freq. = OSC or crystal freq.

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11.3.3 SPI Interface Timing
Symbol Parameters Min Typ Max Units
TMC SPI Clock Frequency - - 50 Mhz
tCYCLE_WR Clock Cycle Time(Write) 1 - - TMC
tCYCLE_RD Clock Cycle Time(Read) 4 - - TMC
tCSS Chip Select Setup Time 2 - - ns
tCSH Chip Select Hold Time 4 - - ns
tDCS Chip Select Setup Time(for 4 wire 8 bit mode) 2 - - ns
tDCH Chip Select Hold Time(for 4 wire 8 bit mode) 4 - - ns
tDSW Write Data Setup Time 2 - - ns
tOHW Write Data Hold Time 4 - - ns
tACC Read Data Access Time 8 - - ns
tCYCLE_RD
tDHR Read Data Hold Time - - ns
/2
tCSWD Chip Select Write Delay Time 1 - - TBC
tCSRD Chip Select Read Delay Time 1 - - TBC
tR Rise time 1 - - ns
tF Fall time 1 - - ns
Figure 11-2 SPI Interface Timing Characteristics
Write

csx/dcx tCSS /tDCS tCSH /tDCH VIH VIH

VIL VIL tCSWD

tCYCLE_WR
VIH
VIH VIH
sck VIL
tF VIL tR VIL

tDSW tDHW
VIH VIH
sdin Valid Data
VIL VIL

Read

tCSS VIH VIH

tCSH
csx
VIL VIL
tCSRD
tCYCLE_RD

VIH VIH VIH

sck
VIL VIL VIL
tF tR

tACC tDHR

VIH VIH
sdout Valid Data
VIL VIL

Figure 11-3: SPI Interface Timing Diagram

Note: VIL and VIH refers to DC CHARACTERISTICS

Note: When PLL is off (0xB0h 0x0000h), max. clock freq. = OSC or crystal freq.

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11.3.4 RGB Interface Timing
Symbol Parameters Min Typ Max Units
tpclk pclk Period 5.5 - - ns
tvsys Vertical Sync Setup Time 1.7 - - ns
tvsyh Vertical Sync Hold Time 1.7 - - ns
thsys Horizontal Sync Setup Time 1.7 - - ns
thsyh Horizontal Sync Hold Time 1.7 - - ns
thv Phase difference of Sync Signal Falling Edge -1 0 1 tpclk
tds Data Setup Time 1.7 - - ns
tdh Data hold Time 1.7 - - ns
tch2ch Phase difference of channel 0 and 1 -1 0 2 tpclk

Table 11-3 RGB Interface Timing Characteristics

Note: The link should run at greater or equal than the pclk frequency * bit per pixel (bpp).

tvsys tvsyh

vsync
thsys thsyh

hsync
thv
tDOTCLK

pclk

tds tdh

data

Tch2ch

Ch 0 RGB

Ch 1 RGB

Figure 11-4: RGB Interface Timing Diagram

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12 POWER UP SEQUENCE

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13 POWER OFF SEQUENCE

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14 MIPI CHARACTERISTIC

14.1 MIPI CPHY CHARACTERISTIC

Figure 14-1C-PHY Signaling Levels

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14.1.1 MIPI CPHY HS CHARACTERISTICS

Table 14-1 HS Transmitter DC Specifications

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 Table 14-2 HS Transmitter AC Specifications

14.1.2 MIPI CPHY LP CHARACTERISTICS

Table 14-3 LP Transmitter DC Specifications

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 Table 14-4 LP Transmitter AC Specifications

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 14.2 MIPI DPHY CHARACTERISTIC

Figure 14-2 D-PHY Signaling Levels

Figure 14-3 DDR Clock Definition

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 Table 14-5 : Clock Signal Specification

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 14.21 MIPI DPHY HS CHARACTERISTICS

Table 14-6 HS Transmitter DC Specifications

Table 14-7 HS Transmitter AC Specifications

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 Table 14-8 LP Transmitter DC Specifications

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 Table 14-9 LP Transmitter AC Specifications

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15 APPLICATION REFERENCE

15.1 Controlling and Programming

In SSD2832, command 0xB0 to 0xFF are used for local registers. APB peripherals which have the
registers accessed via command 0xE0. See the table below.

User can program local registers in one of the following ways:

1) MCU interface through MCU-0 interface only
2) SPI interface

Refer to the respective interfaces (RGB, SPI or MCU) for details on the use of these interfaces to
program local registers.

The table below shows the local register map summary in SSD2832.

Command Description
Some of the commands would have additional data
0xB0 – 0xDF
parameters added to support extension of certain register
fields. For example VBP (Vertical back porch) is an 8-bit
field. With the extension of the number of data parameters,
VBP can now become a 16-bit field. The original register
fields’ location would be maintained in the first 2 data
parameters for back-ward compatibility purpose. Only 2
data parameters would be added.
This is the command for APB peripheral access (e.g.
0xE0
GPIO)

If all 6 data parameters are given, SSD2832 would issue

APB write access with the APB_ADDR and APB_DATA.

If only 2 data parameters are given, SSD2832 would store

the APB_ADDR for read operation. Host can do a data read
to read back the APB_DATA.
Data Parameter Description
1 APB_ADDR[7:0]
2 APB_ADDR[15:8]
3 APB_DATA[7:0]
4 APB_DATA[15:8]
5 APB_DATA[23:16]
6 APB_DATA[31:24]
0xE1 – 0xFE Reserved
This is a special command which has 2 different usages
0xFF
depending on the interface through which the command is
received.

MCU or SPI Interface

This is the command to read back data returned by the
external MIPI slave.
The application processor can treat this register as an FIFO
and continuously read data from it. When the MCU
interface is 16-bit, the width of this field is 16-bit. When
the MCU interface is 8-bit, the width of this field is 8-bit.

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 The read of this register is only valid when the RDR bit is
1. In other words, only when the data returned by the MIPI
slave is received, the application processor can read this
register to get return data.

15.1.1 Access Local (non-APB) Registers

The legacy registers (16-bit accessed) are accessed in term of 2 bytes per cycle for all MCU
interfaces, except 8-bit format which requires 3 cycles to access (1 command, 2 data cycles)
In the first write cycle, only 8-bit data are written into the SSD2832, as the address can only be 8-bit.
No matter whether the interface is 8-bit, 16-bit, 24-bit or 48-bit, lower 8 bits are used. Please refer to
the table below.

Interface Data pins

types
D47-D24 D23-D16 D15-D8 D7-D0
48-bit,
24-bit,
Don’t care Don’t care Don’t care Address
16-bit,
8-bit
Table 15-1: MCU Interface Data Pin Mapping for Command Cycle for Legacy Registers

In the subsequent read or write cycle, the data width is only 16-bit or 2 bytes no matter the interface
width is selected, except for 8-bit format. Please refer to the table below.
If there are 4 bytes in the legacy registers due to data parameters extension, there will be additional
data cycles accordingly.

Interface Data pins

types Cycle Note
D47-D24 D23-D16 D15-D8 D7-D0
48-bit, 1st Don’t care Don’t care Data Byte 1 Data Byte 0 (1)
24-bit,
16-bit 2nd Don’t care Don’t care Data Byte 3 Data Byte 2 (2)

1st Don’t care Don’t care Don’t care Data Byte 0 (1)
2nd Don’t care Don’t care Don’t care Data Byte 1 (2)
8-bit
3rd Don’t care Don’t care Don’t care Data Byte 2 (3)
4th Don’t care Don’t care Don’t care Data Byte 3
Table 15-2: MCU Interface Data Pin Mapping for Legacy Register

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Note:
(1) If the local registers have 4 bytes of data, host can either write 2 bytes or 4 bytes of
data.
(2) If the local registers have only 2-bytes of data, any extra write will be ignored
(3) For 8-bit interface, all writes must be in multiple of 2 cycles

15.1.2 Access Local (APB) Registers for Write

The APB peripheral’s registers are accessed indirectly through command 0xE0. The data content of
0xE0 are 6 bytes and arranged in the order of {addr low, addr high, data0, data1, data2, data3}, where
addr low is sent first.
In the first write cycle, only 8-bit data are written into the SSD2832, as the address can only be 8-bit.
No matter whether the interface is 8-bit, 16-bit, 24-bit or 48-bit, lower 8 bits are used. Please refer to
the table below.

Interface Data pins

types
D47-D24 D23-D16 D15-D8 D7-D0
48-bit,
24-bit,
Don’t care Don’t care Don’t care 0xE0
16-bit,
8-bit
Table 15-3: MCU Interface Data Pin Mapping for Command Cycle for Extended Registers Write

In the sub-sequent write cycle, the data width is only 16-bit or 2 bytes, no matter the interface width is
selected, excepted for 8-bit format. Please refer to the table below.

Interface Data pins

types Cycle
D47-D24 D23-D16 D15-D8 D7-D0
1st Don’t care Don’t care Addr High Addr Low
48-bit,
24-bit, 2nd Don’t care Don’t care Data Byte 1 Data Byte 0
16-bit
3rd Don’t care Don’t care Data Byte 3 Data Byte 2
1st Don’t care Don’t care Don’t care Addr Low
2nd Don’t care Don’t care Don’t care Addr High
3rd Don’t care Don’t care Don’t care Data Byte 0
8-bit
4th Don’t care Don’t care Don’t care Data Byte 1
5th Don’t care Don’t care Don’t care Data Byte 2
6th Don’t care Don’t care Don’t care Data Byte 3
Table 15-4: MCU Interface Data Pin Mapping for Extended Registers Write

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SSD2832 Rev 1.5 151/178 Aug. 2020 Solomon Systech
15.1.3 Access Local (APB) Registers for Read
The APB peripheral’s registers are accessed by 0xE0. The content of 0xE0 are 2 bytes and arranged in
the order of {addr low, addr high}, where addr low is sent first.

In the first write cycle, only 8-bit data are written into the SSD2832, as the address can only be 8-bit.
No matter whether the interface is 8-bit, 16-bit, 24-bit or 48-bit, lower 8 bits are used. Please refer to
the table below.
Interface Data pins
types
D47-D24 D23-D16 D15-D8 D7-D0
48-bit,
24-bit,
Don’t care Don’t care Don’t care 0xE0
16-bit,
8-bit
Table 15-5: MCU Interface Data Pin Mapping for Extended Registers Address Set 1
In the sub-sequent write cycles, the data width is only 16-bit or 2 bytes no matter what interface width
is selected, excepted for 8-bit format. Please refer to the table below.
Interface Data pins
types Cycle
D47-D24 D23-D16 D15-D8 D7-D0
48-bit,
24-bit, 1st Don’t care Don’t care Addr High Addr Low
16-bit
1st Don’t care Don’t care Don’t care Addr Low
8-bit
2nd Don’t care Don’t care Don’t care Addr High
Table 15-6: MCU Interface Data Pin Mapping for Extended Registers Address Set 2

In the read cycles, the host read the data from 0xE1 register in 16-bit or 2 bytes format no matter what
interface width is selected, except for 8-bit format. Please refer to the table below.
Interface Data pins
types
D47-D24 D23-D16 D15-D8 D7-D0
48-bit,
24-bit,
Don’t care Don’t care Don’t care 0xE1
16-bit,
8-bit
Table 15-7: MCU Interface Data Pin Mapping for Extended Registers Data Read 1

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 Interface Data pins
types Cycle
D47-D24 D23-D16 D15-D8 D7-D0
48-bit, 1st Don’t care Don’t care Read Data 1 Read Data 0
24-bit,
16-bit 2nd Don’t care Don’t care Read Data 3 Read Data 2
1st Don’t care Don’t care Don’t care Read Data 0
2nd Don’t care Don’t care Don’t care Read Data 1
8-bit
3rd Don’t care Don’t care Don’t care Read Data 2
4th Don’t care Don’t care Don’t care Read Data 3
Table 15-8: MCU Interface Data Pin Mapping for Extended Registers Data Read 2

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 15.2 Video Mode Use Cases

For this mode, the user must set IF_SEL0 to “0” to select the interface as a combination of RGB and
SPI interface. The video data come from the RGB interface and the chip configuration is done
through the SPI interface.

The video timing parameter for MIPI DSI outputs are programmed at command 0xB1 to 0xB6.

The table below shows the minimum requirements for RGB parallel input and chip configuration,
with respect to the video timing parameter for MIPI DSI output. The units are pixel for horizontal
parameters and line for vertical parameters.

RGB Parallel Input Video Timing Output Video Timing Parameter (Per output DSI)
Parameter - Programmed at 0xB1 to 0xB6 commands
Single DSI Output:
Video Mode = 1 or 2:
HBP = (Panel HBP + Panel HSW)
Input HBP = Panel HBP /(Data_Width/24
Video Mode = 0:
HBP = (Panel HBP)
Horizontal Back Porch Video Mode = 1 or 2: Minimum of 20,
(HBP) Multiple of 2
Dual DSI Output:
Video Mode = 0: Minimum of 18, Multiple of
Video Mode = 1 or 2:
2
HBP = (Panel HBP + Panel HSW) / 2
Video Mode = 0:
HBP = (Panel HBP) / 2

Single DSI Output:

HSW configuration for (Video Mode = 0)
= Panel HSW
Horizontal Sync Width Input HSW = Panel HSW / 2
(HSW) Minimum of 2, Multiple of 2
Dual DSI Output:
HSW configuration for (Video Mode = 0)
= Panel HSW / 2

Input HACT = Panel HACT / 2

SDR mode: Multiple of 2

DDR mode: Multiple of 4 Single DSI Output:
HACT configuration = Panel HACT
Horizontal Actual
Note:
(HACT) For the following cases, input HACT needs Dual DSI Output:
to be at least multiple of 4 HACT configuration = Panel HACT / 2
- Dual-pixel input (either SDR or DDR
mode) and split to dual DSI output
- 18bpp or 30bpp pixel format

Single DSI Output:

HFP configuration
Input HFP = Panel HFP / 2 + 16 = Panel HFP
Horizontal Front Porch
(HFP) Minimum of 20, Multiple of 2 Dual DSI Output:
HFP configuration
= Panel HFP / 2

Vertical Back Porch Minimum of 2

Vertical Sync Width Minimum of 1
Vertical Actual Minimum of 2
Vertical Front Porch Minimum of 2

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The possible video paths (and non-video command paths) supported in this mode are shown below.
The SPI interface can be used to program local registers or transmit command packets during video
blanking to MIPI output.

RGB Interface Input, Single MIPI Video Output

RGB Interface 0 MIPI CPHY or DPHY TX 0

SSD2832

Local registers
SPI Interface

RGB Interface Input, Dual MIPI Video Output

This is either a split use case or a broadcast use case. For split use case, it can
be either odd/even pixel split, or left/right image split

RGB Interface 0 MIPI CPHY or DPHY TX 0

SSD2832
MIPI CPHY or DPHY TX 1

SPI Interface Local registers

The user, firstly, needs to configure the MIPI TX timing parameters through registers programming.
Then, the user can turn on the RGB interface and enable the SSD2832 to start transmission. All three
video mode sequence defined in the MIPI DSI specification are supported.

The PLL multiplication factor should be set such that the serial link data rate is faster than the
incoming data rate. Please refer to the table below for the PLL settings.

Below is the diagram to illustrate the definition of all the fields.

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 HSA
Hsync

DEN
HBP HACT HFP

Pclk

MIPI_Data[23:0]

VSA
Vsync

VBP VACT VFP

Hsync

Figure 15-1: Illustration of RGB Interface Parameters for Non-burst Mode with Sync Pulses

Hsync

DEN
HBP HACT HFP

Pclk

MIPI_Data[23:0]

Vsync

VBP VACT VFP

Hsync

Figure 15-2: Illustration of RGB Interface Parameters for Non-burst Mode with Sync Events and Burst Mode

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15.2.1 Interleaving Non-Video Packets with Video Packets

Non-video data can be transmitted during the vertical blanking of the video frames, or when nvb (in 0xB6
register) is set, during any BLLP period (including those in the horizontal blanking). It is recommended to send
non-video data during vertical blanking.

The nvd and bllp field (in 0xB6 command) determines how the non-video data is sent. See below table for
illustration.

NVD BLLP Non-burst mode Burst mode

0 0 If there is no non-video data to send, the If there is no non-video data to send, the serial
serial link will send blanking packet in HS link will enter LP mode during BLLP period.
mode during BLLP period.
If there is non-video data to send, non-video
If there is non-video data to send, the non- data will be sent in HS mode. Afterwards, the
video data will be sent in HS mode. serial link will enter LP mode for the
Afterwards, the serial link will send blanking remaining period of BLLP period.
packet in HS mode for the remaining period
of BLLP period.
0 1 If there is no non-video data to send, the Same as non-burst mode.
serial link will enter LP mode during BLLP
period.
If there is non-video data to send, non-video
data will be sent in HS mode. Afterwards,
the serial link will enter LP mode for the
remaining period of BLLP period.
1 x The serial link will enter LP mode for BLLP Same as non-burst mode.
mode. If there is non-video data to send, the
data will be sent in LP mode at the beginning
of BLLP period.

The number of non-video data packets that would be sent out is determined by the pnb field (in 0xD6
command). If there are more non-video data packets to be sent than pnb, it would be sent in the next available
vertical blanking line, or when nvd field (in 0xB6 command) is set, it would be sent in the next horizontal
blanking time.

vbn and vfn fields (in 0xDD command) are used to prohibit non-video packets from being sent out after vbn
lines before the first vertical active line, and before vfn lines after the last vertical active line.

Please refer to section Write Operation and Read Operation for more details on transmission of the non-video
data packets.

15.2.2 Video Bandwidth Consideration (RGB Parallel Interface)

For RGB input, the main thing to consider is the input bitrate must be lesser than or equal to the
output bit rate.

Calculation of input bitrate

Bitrate input = PCLK_freq * number_of_pixels input (dual or quad-pixel interface) * bits_per_pixel

(bpp)

E.g. if dual-pixel interface is used with PCLK = 150MHz, and 24bpp, then
Bitrate input = 150MHz * 2 * 24bits = 7.2Gbps

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Calculation of output bitrate (Refer to Clock Programming)

DPHY output:
Bitrate output = Total number of DPHY lanes * bitrate per lane

E.g. if there are 6 lanes @ 1Gbps each,

Bitrate output = 6 * 1Gbps = 6Gbps

CPHY output:
Bitrate output = Total number of CPHY lanes * symbol rate per lane * 2.28

E.g. if there are 6 lanes @ 1Gsps each,

Bitrate output = 6 * 1Gsps * 2.28 = 13.68Gbps

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 15.3 Command Mode Use Cases

MCU interface supports 48-bit, 24-bit data, 16-bit and 8-bit data bus. To support different bus width,
the following data pins of MCU interface are used.
 data[47:0] for 48-Bit interface
 data[23:0] for 24-bit interface
 data[15:0] for 16-bit interface
 data[7:0] for 8-bit interface

In SSD2832, MCU interface is up to 48-bit data interface. The following command mode use cases
are possible:

MCU Input, Command/Video Output

To select MCU(s) input, IF_SEL0 needs to “1”.

MCU-0 MIPI CPHY or DPHY TX 0

SSD2832
Local registers

MCU Input, Dual MIPI Command Output

This is a broadcast use case. To select MCU(s) input, IF_SEL0 needs to “1”.

MCU-0 MIPI CPHY or DPHY TX 0

SSD2832
MIPI CPHY or DPHY TX 1

Local registers

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15.3.1 Programming Sequence

SSD2832 can send image data to downstream display module using command mode using DCS
Write Memory Command 2Ch/3Ch. The sequence below is recommended when host intend to
use command mode:

1. Prior to start video data transmission for each frame, host shall send a LP NOP Packet
(Command 00h) to put MIPI-TX MIPI lanes into LP-11 state. This is to ensure TX lane does
not remain in HS for too long and eventually causes HS TX Timer (htt) timeout.
2. Host shall then send HS NOP Packet (Command 00h) to put TX link into HS state as
preparation for incoming 2C/3C command. Due internal latency, it is recommended to poll
for CBE status set to ensure the HS command has been sent out to TX.
3. Now TX link is in HS state, host can send DCS Write Memory Command starting from 2Ch
command and subsequently 3Ch commands.
4. If MCU interface is used, before start of transmission for next 3Ch command, host shall poll
for MLA status set to ensure there is buffer available for next in-coming command. If
Partition Mode is enabled (TDC>PST), host shall poll for MLE status instead. Host can also
wait for interrupt or wait for a fixed delay instead if it does not poll for interrupt status.
5. If 2Ch or 3Ch command data size is more than maximum data size, Partition Mode is
automatically enabled to split in-coming packet to multiple output packets.

Input Mode Maximum Data Size

MCU Input TDC <= 8192 bytes
Table 15-15: Maximum Data Size without using Partition Mode

6. For start of each new frame, step 1-3 shall be repeated.

CBE status set MLA status set MLA status set

DCS Command DCS Command DCS Command DCS Command

Image LP HS Image Image Image
8'h3C 8'h2C 8'h3C … 8'h3C
Data Pkt Pkt Data Data Data
Last Packet Dummy NOP First Packet Last Packet
Command

Single Frame Duration

Figure 15-3: Command use case Sequence with TDC < PST

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 Figure 15-4: Command use case Sequence with TDC > PST

15.3.2 Partition Mode

For DCS Write Packet, partition is supported for 0x2C or 0x3C DCS command. This is because
the DCS command 0x2C and 0x3C are to write display data into the LCD panel display memory.
The payload will be partitioned into several packets where the payload of each packet is
determined by the Partition register (PST). The first byte is the DCS command and the following
bytes are the payload. Only the last packet might contain less payload, as the total payload might
not be integer multiple of partition size. If the incoming DCS command is 0x2C, the DCS
command for the first packet is 0x2C and the DCS command for all other packets is 0x3C. If the
incoming DCS command is 0x3C, the DCS command of all the packets is 0x3C.
For example, if the byte size field is 200 and partition field is 80, 3 packets will be sent. The first
two have 80 bytes of payload. The last packet has 40 bytes of payload.

To use Partition Mode, the following steps shall be performed:

1. Configure Packet Size Threshold (PST) by writing to Packet Size Control Register 3 (0xBE).
PST has the following requirement:
PST < 8192 Bytes
PST < TDC (if MCU interface)
PST must be multiple of 12 bytes

2. Perform the normal steps of sending 2Ch/3Ch to display module. SSD2832 will automatically
split packet in to multiple 2C/3Ch packets with word count = PST, with last packet word
count < PST if there is remainders.

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15.4 Video to Command Mode

The MIPI TX output of SSD2832 can convert video packets to command mode packets (i.e. 0x2C
command for the first video line, and 0x3C commands for the subsequent video lines).

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15.4.1 Example of switching sequence

Note:
For this feature, it is important to note that once Video-to-Command mode is turned on, the MIPI
would be in HS link when there is active video input. It would remain in HS link until the mode is
turned off. Since there is a HS timeout built-in SSD2832, user is recommended to switch off Video-
to-command mode periodically (e.g. after a 2-3 frames of conversion)

15.5 MIPI Packet Control

2832 is able to perform MIPI read write by using either the SPI interface or the MCU interface.

The SPI interface is used together with the parallel RGB interface for control and command. At the IC
initialization stage, options for handling the non-video data should be set at the RGB Interface Control
Register 6 (0xB6).

For each read/write operation, control and packet registers should be set up accordingly to match
properties of different MIPI packets.

Configuration Register (0xB7) controls the format and structure of the MIPI packets. DCS, Generic,
PPS or Compression Mode packet, SP/LP, EOT or not, ECC or not. These settings should be changed
if the MIPI packet is different from the last used. It is recommended to confirm the settings every time
before a MIPI packet sent.

Virtual Channel Control (0xB8) controls the virtual channel of the packets.

Packet Size Control (0xBC to 0xBE) controls the length of the packet to be sent. TDC could affect the
packet type in the following MIPI packet transmission. Partition mode is offered when PST is set
lower than TDC for transmitting 0x2C/3C DCS packets.

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15.5.1 Write Operation

Setup DCS and TDC for

the command to be sent

Address from range Y Write the command to Packet

0xB0 to 0xFF Drop register (0xBF) of 2832

Directly write the command

to 2832

The SSD2832 can issue four kinds of packets for write operation, which are Generic Short Write
Packet, Generic Long Write Packet, DCS Short Write Packet and DCS Long Write Packet. The VC
ID of the outgoing packets can also be programmed through registers.

The SSD2832 needs to know the payload size of the outgoing packets. Hence, the user needs to
program the corresponding control registers prior to sending the MIPI data.

To send a DCS or Generic Write Packet in address 0xB0 to 0xFF, the user needs to write the
command/header and the payload to the Packet Data Drop register (0xBF). If the size field is no more
than 2 for Generic packet and 1 for DCS packet, the SSD2832 will send out DCS or Generic Short
Write Packet with the correct type. Otherwise, DCS or Generic Long Write Packet will be sent out.

After performing a write operation, the user can optionally make a BTA to let the MIPI slave report
its status. The SSD2832 will automatically make a BTA after each write operation.

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15.5.2 Read Operation

Setup DCS, TDC and Max Return

Size for the command to be read

DCS read packet? Y Address from range

0xB0 to 0xFF

N Y

Directly send read packet Use Packet Drop (0xBF)

register to send command

Check 0xC6, BTAR N

and RDR = 1

Check Return Data

Count (0xC2)

Read out the returned

data from 0xFF

The SSD2832 can issue two kinds of packets for read operation, which are Generic Read Packet, and
DCS Read Packet. The bit DCS controls whether Generic Read Packet or DCS Read Packet will be
sent out. The VC ID of the outgoing packets can also be programmed through registers.

Before the read packet is sent out, the SSD2832 will always send out the Set Maximum Return Size
Packet. This is to limit the Read Response Packet sent by the MIPI slave such that there is no over
flow. Two factors determine the maximum size. One is the limit of the SSD2832 and the other is the
limit of the application processor. The user should choose the smaller one among these two limits to
use as the maximum return size.

The parameter in the Set Maximum Return Size Packet is taken from local register. The user could
program the Set Maximum Return Size Register before every read so that the correct value is sent
through Set Maximum Return Size Packet. If the value is already the desired value, the user can
choose not to program it. SSD2832 will still automatically send out Set Maximum Return Size Packet
before the every Read Packet.

To send a DCS Read or Generic Read Packet, the user just needs to write the DCS (as there is no
parameter for DCS read) or Generic command, or write to Packet Drop Data register when the address
is from 0xB0 to 0xFF.

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Similar to the write operation, the Total Data Count register field is used to determine the payload size
of the outgoing packet. For DCS Read Packet, the payload is just the DCS command. There is no
parameter associated. For Generic Read Packet, the SSD2832 will send out the correct packet type
according to the Total Data Count value.

After sending out the read packet, the SSD2832 will automatically perform a BTA to wait for the
Read Response Packet from the MIPI slave. After seeing read valid status bit (0xC6) been set to 1, the
user should first check the number of bytes returned by the MIPI slave. By using this information, the
user will know how many data should be read out from data register (0xFF). After all the return data
are read out, the read valid status bit will be set to 0 by the SSD2832.

Even the read valid status bit is set to 1, the user can choose not to read the data out from data register.
The user can continue performing another operation. Once the user does so, the read valid status bit
will be set to 0 by the SSD2832.

There might be Acknowledge and Error Report Packet sent by the MIPI slave at the same time.

Under certain circumstance, the MIPI slave might only send back Acknowledge and Error Report
Packet without any data and the read valid status bit will not be set. Therefore, it is recommended that
the user check the bus turnaround bit first. The bus turnaround bit is to indicate whether the MIPI
slave has passed the bus authority back to the SSD2832 or not. Only when the bus turnaround is 1,
there might be return data. If there is no returned data, the user should follow Acknowledgement
Operation.

15.5.3 Internal Buffer Status

There are 2 types of buffers inside the SSD2832, which are MCU interface line buffer (ML) and
MCU/SPI command interface buffer (CB).

The ML buffers are used to store the data (DCS command 0x2C and 0x3C) written through MCU
interface when the if_sel is ‘01’. They are also used to store the video data written through RGB
interface when the if_sel is ‘00’.

For CB buffers, all command packets will be stored into them. They can store multiple packets, up to
4096 bytes in total. Below is a list of possible packets
 Generic Short Write Packet
 Generic Read Packet
 DCS Short Write Packet
 DCS Read Packet
 Generic Long Write Packet
 DCS Long Write Packet

In case of automatic partitioning, the packet length is determined by the PST field. It is not
recommended to make the PST field so small.

When the if_sel is “00”, the user can write the data through SPI interface. All packets will be written
into the CB buffers. Hence, the user needs to check the corresponding interrupts. The usage of the
interrupts is listed below.

CBE

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To indicate that the Command buffer is empty.

CBA

To indicate that the Command buffer can hold at least 1 more packet. The user can write 1 such
packet into CB buffer.

MLE

To indicate that MCU Long buffer is empty. Since the ML buffer can hold 2 packets, the user can
write up to 2 such packets into ML buffer without needing to look at the interrupt status.

MLA

To indicate that the MCU Long buffer can hold at least 1 more packet. The user can write 1 such
packet into ML buffer.

The interrupts mentioned here can be used as flow control between the application processor and the
SSD2832. However, it requires the user to know the buffer operation well. The PO interrupt is a
combination of the eight. It makes decision according to the parameters provided by the user for the
next packet to be written. Hence, the user does not need to know which buffer is going to be used and
how the buffer status is.

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 15.6 Interrupt Operation

An interrupt signal int has been provided to interrupt the application processor so that it does not need
to poll the status all the time. This will save the processing time of the application processor. int can
be programmed to active high or active low, when the event has happened.

There are many sources that can be mapped to the interrupt signal. The user can select different
source to perform different task. If more than 1 source is selected, the int signal will be asserted when
the event for 1 of the sources has happened. In this case, the user needs to read the register ISR to
determine what event has happened. The different sources can be enabled/disabled through register
ICR. Below is the list of available interrupt sources and their usage.

RDR

To indicate that return data from one of the MIPI slave is available for read.

BTAR

To indicate whether the SSD2832 has the bus authority or not. It can be used after SSD2832 makes a
BTA. If the MIPI slave has returned the bus authority back to SSD2832, the interrupt will be set to
indicate so. Please note that, on power up, the bus authority is already on the SSD2832. Hence, the
SSD2832 will show that it has the bus authority.

ARR

To indicate whether the SSD2832 has received the acknowledge response from the MIPI slave. The
acknowledge response can either report error or not error. This is to be determined by the ATR bit.

The above three interrupts are provided to the user to handle reading data from the MIPI slave or
getting acknowledgement response from the MIPI slave.

PLS

To indicate whether the PLL has been locked or not. If the PLL is not locked, the programming speed
at the external interface must be slow. After changing the PLL setting or changing the reference clock
source, the user also needs to use this interrupt to determine the PLL status.

On power up, only PLS interrupt is enabled. This is to let the user determine the programming speed
before configuring the SSD2832.

LPTO

To indicate that there is LP RX time out.

HSTO

To indicate that there is HS TX time out.

The above two interrupts are provided to the user for error handling.

CBE, CBA, MLE, MLA

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All these interrupts (CBE = command buffer empty, CBA = command buffer available, MLE = MCU
line buffer empty, MLA = MCU line buffer available) are provided to indicate the status of the
internal data buffers. They are used if the user is familiar with the buffer management of the
SSD2832. Otherwise, it is recommended to use the PO interrupt.

One important thing to note is the interrupt latency. The output interrupt signal does not change
immediately after an operation. This is due to the internal processing of the SSD2832. For example,
after changing the interrupt source from one to another, the output int level will remain at the old level
for a short period after the programming is done. Another example is that after programming the
TDC field, the interrupt will take a short period to reflect the correct PO status on int. There is
always a delay between the actual event and the interrupt.

In order to guarantee that the user can get the correct interrupt, it is recommended that the user
performs a read of any SSD2832 local register before taking in the interrupt signal or polling the
interrupt status bits. The read operation will cover the interrupt latency period. Alternatively, the user
can wait for certain amount of time to make sure the interrupt reflects the true status. Below is a
diagram for illustration.

Start of read Interrupt reflects

operation true status End of read
operation
Event
happens

int

Time

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 15.7 State machine operation
The state machine controls the sending and receiving of the data packet over the serial link. It is
triggered by an event from the application processor or the received data. Once a complete packet is
written into the SSD2832 buffer, it will send it out through the serial link. The user can write 1 to bit
COP (cancel-operation) at any time to cancel all the current operations.
When the SSD2832 is in high speed mode, the serial link is mainly used to send display data. If there
is no data to send, it will send null packet to maintain the serial link timing. If the application
processor does not have display data to send in a long period, it can turn the serial link into low power
mode by setting the register bit HS to 0.
When the SSD2832 is in low power mode, the serial link is mainly used to send command and
configuration data. If there are no data to be sent, the SSD2832 will be idle in LP TX stop mode.
The user can also enter sleep mode by writing 1 to SLP bit. Once the SLP bit is set to 1, the
SSD2832 will automatically enter LP mode. If the HS bit is 1, the SSD2832 will clear the HS bit to 0
and switch from HS to LP mode. Afterwards, the SSD2832 will issue ULPS trigger message to the
MIPI slave to enter Ultra Low Power State. During this state, the clock to SSD2832 can be switched
off such that the SSD2832 only consumes leakage current. This will save the overall system power
consumption. When exiting from the ULPS, the user can write 0 to SLP bit. However, the user
should be aware that the time to exit from ULPS is relatively long (please refer to MIPI DPHY
specification). Hence, the user cannot perform any data transmission before the system exits from
ULPS.
During reception, the state machine will disassemble the incoming data packet and put the received
register content into the internal buffer for reading out. Once all the data are put into the buffers, it
will set the register bit RDY to 1 to indicate that the SSD2832 is ready for read. The total number of
received bytes will also be stored in RDCR.
After the reception is completed, the SSD2832 will perform a bus turn around to enter the
transmission mode. It will always come back to the LP TX stop mode before it enters any other
mode.

15.8 Acknowledgement Operation

The SSD2832 can perform a BTA to give the bus authority to the MIPI slave and let it report its
status. The BTA can be enabled by setting FBW bit to 1 and performing a write operation, or just
performing a read operation. After the MIPI slave passes the bus authority back, the SDD2832 will
set bit BTAR to 1.
If there is no error on the slave side, the MIPI slave will return ACK trigger message, if the packet
before BTA is a write packet. The MIPI slave will return Read Response Packet, if the packet before
BTA is a read packet. In this case, after receiving the response from the MIPI slave, SSD2832 will
set bit ARR and ATR bits to 1. ARR indicates that response has been received from MIPI slave.
ATR indicates that the MIPI slave has reported no error with ACK trigger message. Consequently,
the register ARSR will be cleared to 0.
If there is error on the slave side, the MIPI slave will return Acknowledge and Error Report packet, if
the packet before BTA is a write packet. The MIPI slave will return Read Response Packet
(depending on the error type) and Acknowledge and Error Report Packet, if the packet before BTA is
a read packet. In this case, after receiving the response from the MIPI slave, SSD2832 will set bit
ARR bit to 1 and ATR bits to 0. ARR indicates that response has been received from MIPI slave.
ATR indicates that the MIPI slave has sent Acknowledge and Error Report Packet instead of ACK
trigger message. Therefore, the MIPI slave has reported error. The error reported by the MIPI slave
will be stored in register ARSR. The user can read this register to see what error the MIPI slave has
encountered.

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For the detailed description of each error bit, please refer to MIPI DSI specification. Below are the
flow charts of handling the MIPI slave acknowledgement. They are just for reference.

N
BTAR == 1?

Y
N Error!
ARR == 1?
No Acknowledgement
Y
N Handle Slave Error
ATR == 1?
Report

Slave has no error.

Proceed

N
BTAR == 1?

Y
N Error!
ARR == 1?
No Acknowledgement
Y
Slave has no error. Y N Handle Slave Error
Proceed ATR == 1?
Report

N Y
RDR == 1? Correctable?

Y N
Y
RDR == 1?

Read return data and Error! Error! Proceed

Proceed No return data Extra return data

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 15.9 Tearing Effect (TE) Operation

15.9.1 Using IO Pins

SSD2832 takes in TE_in pin, reshape and output TE_out pin. The programmable parameters are the
pulse width, polarity, and delay.

TE_out Pulse
TE_in
Modifier
Application Display Driver
Processor SSD2832

15.9.2 Using MIPI Escape Mode

The TE operation is to perform a BTA following the previous BTA without transmitting anything in between.
The bus is handed to the MIPI slave for providing TE information. After getting the TE event from display
driver, the MIPI slave will pass the bus authority back to the SSD2832 by using BTA trigger message.

The TE operation can be enabled by setting bit FBT and FBW to 1 before writing the last command to the MIPI
slave. Afterwards, the application processor can instruct the SSD2832 to send out the last command in a write
packet. Since FBW is 1, the SSD2832 will automatically perform a BTA after the write operation. The MIPI
slave will response and pass the bus authority back. Since FBT is 1, the SSD2832 will perform another BTA
without sending any data. This makes the MIPI slave enter TE mode.

The MIPI slave will send a TE trigger message back when it gets the TE event. After getting the trigger
message, the SSD2832 will set the TE pin to 1 to indicate that TE event has been received. At the same time,
bit TER will be set to 1. The application processor can write 1 to this bit to clear it. As the TE trigger message
only determines when the TE pin will be set to 1, a counter is used to determine when to set the TE pin to 0.
The TE pin will be set to 0, once the counter reaches the value in TEC. The counter uses the reference clock to
do counting.

If the MIPI slave does not send back the TE trigger message but just perform a BTA to pass the bus back, the
SSD2832 will automatically perform another BTA to pass the bus to the MIPI slave again. It will continue do
so until the MIPI slave respond with the TE trigger message, or the FBT bit is set to 0, or the LP RX timer
expires.

If the MIPI slave does not send back the TE trigger message and still holds the bus, the user can set the bit FBC
to 1 to force a bus contention. After bus contention is resolved, the slave will pass the bus back to SSD2832.

SSD2832 supports dual MIPI TX port. Hence there would be 2 TE outputs accordingly.

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15.10 Video BIST

SSD2832 supports the following pattern generations for video BIST.

Note: The minimum HTOTAL (HBP + HSW + HACT + HFP) needs to be at least 1200.

The following tables describe the various Video BIST mode in detail. Please also refer to Video BIST
Register Descriptions for the related registers descriptions.

MODE 0x0 Offset / Parameter Usage

Solid color loop in sequential order of 16 pre-defined color of ({0x3FF, 0x000, Number of frames pause between
vb_repeat_cnt
0x000}, {0x000, 0x3FF, 0x000}, {0x000, 0x000, 0x3FF}, {0x000, 0x3FF, 0x3FF}, different colors
{0x3FF, 0x000, 0x3FF}, {0x3FF, 0x3FF , 0x000}, {0x3FF, 0x3FF, 0x3FF}, vb_color_1 Not used
{0x37F, 0x37F, 0x37F}, {0x2FF, 0x2FF, 0x2FF}, {0x27F, 0x27F, 0x27F}, {0x1FF, vb_color_2 Not used
0x1FF, 0x1FF}, {0x17F, 0x17F, 0x17F}, {0x0FF, 0x0FF, 0x0FF}, {0x07F, 0x07F,
vb_x_start Not used
0x07F}, {0x03F, 0x03F, 0x03F}, {0x000, 0x000, 0x000})
vb_x_end Not used
vb_y_start Not used
vb_y_end Not used
1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

Table 15-9 Video BIST Mode 0

MODE 0x1, 0x2 Offset / Parameter Usage
Vertical (mode 0x1) / Horizontal (mode 0x2) repeating 16 colors bars with Color bar width in pixels (MODE 0x1
configurable bar width. Color repeating order are ({0x3FF, 0x000, 0x000}, {0x000, vb_repeat_cnt only : Must be multiple of four
0x3FF, 0x000}, {0x000, 0x000, 0x3FF}, {0x000, 0x3FF, 0x3FF}, {0x3FF, 0x000, number)
0x3FF}, {0x3FF, 0x3FF , 0x000}, {0x3FF, 0x3FF, 0x3FF}, {0x37F, 0x37F, vb_color_1 Not used
0x37F}, {0x2FF, 0x2FF, 0x2FF}, {0x27F, 0x27F, 0x27F}, {0x1FF, 0x1FF, vb_color_2 Not used
0x1FF}, {0x17F, 0x17F, 0x17F}, {0x0FF, 0x0FF, 0x0FF}, {0x07F, 0x07F, 0x07F},
vb_x_start Not used
{0x03F, 0x03F, 0x03F}, {0x000, 0x000, 0x000})
vb_x_end Not used
vb_y_start Not used
vb_y_end Not used
Note: For mode 1 & odd/even setting, vb_repeat_cnt must be
multiple of eight.

Table 15-10 Video BIST Mode 1 & 2

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MODE 0x3 Offset / Parameter Usage
Checker box with configurable width (>= 4) and color. Box width (>=4, must be multiple of
vb_repeat_cnt
four number)
vb_color_1 Color 1 RGB value
vb_color_2 Color 2 RGB value
vb_x_start Not used
vb_x_end Not used
vb_y_start Not used
vb_y_end Not used
Note: For odd/even setting, vb_repeat_cnt must be multiple
of eight.

Table 15-11 Video BIST Mode 3

MODE 0x4, 0x5 Offset / Parameter Usage
Horizontal (0x4) or vertical (0x5) gradient ramp with programmable line width and For Mode 0x4 - # of pixels for each
color increment value. color step. NOTE: It must be multiple
of four number.
0 – 4 pixel.
256 px repeat_cnt
4 – 4 pixels.
8 – 8 pixels.
…
vb_repeat_cnt
For Mode 0x5 - # of lines for each
color step.
0 – 1 line.
1 – 1 line.
2 – 2 lines.
…
r1,g1,b1 = (0,0,0) r1,g1,b1 = (0,0,0) Start color (common for mode 0x4,
r2,g2,b2 = (1,1,1) r2,g2,b2 = (63,0,0) vb_color_1
0x5)
repeat_cnt = 1
Color increment value for each step
vb_color_2
MODE 0x4 MODE 0x5 (common for mode 0x4, 0x5)
vb_x_start Not used
vb_x_end Not used
vb_y_start Not used
vb_y_end Not used
Note: For mode 4 & odd/even setting, vb_repeat_cnt must be
multiple of eight.

Table 15-12 Video BIST Mode 4 & 5

MODE 0x6 Offset / Parameter Usage
Solid filled rectangle with configurable position, size and foreground / background vb_repeat_cnt Not used
color vb_color_1 Foreground color
vb_color_2 Background color
Rectangle’s left boundary (Must be
vb_x_start
multiple of four number)
Rectangle’s right boundary (Must be
vb_x_end
multiple of four number)
vb_y_start Rectangle’s top boundary
vb_y_end Rectangle’s bottom boundary
Note: Start & end are inclusive.
vb_x_start = 4, vb_x_end = 4 means 4 pixels width vb_x_start =
4, vb_x_end = 8 means 8 pixels width
vb_x_start = 4, vb_x_end = 12 means 12 pixels width
vb_y_start = 1, vb_y_end = 1 means 1 line height
vb_y_start = 1, vb_y_end = 2 means 2 line height
vb_y_start = 1, vb_y_end = 3 means 3 line height
Note: For odd/even setting, vb_x_start & vb_x_end must be
multiple of eight.

Table 15-13 Video BIST Mode 6

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MODE 0x7 Offset / Parameter Usage
Single pixel width full size rectangle with two 45° cross touching screen corners. 0x0 : Original Box + Cross
Or single 45° diagonal line drawn from top left / top right / bottom right / bottom 0x1 : Line from (0,0) - (W,W)
left corner. Or rectangle border/frame. Foreground and background color are 0x2 : Line from (0,W) - (W,0)
vb_repeat_cnt
configurable. 0x3 : Line from (0,H) - (W,H-W)
0x4 : Line from (0,H-W) - (W,H)
0x5 : Box
vb_color_1 Foreground color RGB value
vb_color_2 Background color RGB value
vb_x_start Not used
vb_x_end Not used
vb_y_start Not used
vb_y_end Not used

0x0 0x1 0x2

0x3 0x4 0x5

Table 15-14 Video BIST Mode 7

MODE 0x8, 0x9 Offset / Parameter Usage
Vertical (0x8) or Horizontal (0x9) repeating color bars with width of 1 pixel per vb_repeat_cnt_h Not used
color. Color repeating order is [C1, !C2, !C1, C2] vb_color_1 Color 1 RGB value
vb_color_2 Color 2 RGB value
vb_x_start Not used
vb_x_end Not used
vb_y_start Not used
vb_y_end Not used

Table 15-15 Video BIST Mode 8 & 9

MODE 0xA Offset / Parameter Usage
Single pixel width vertical and horizontal line with configurable foreground and vb_repeat_cnt No used
background color vb_color_1 Foreground color RGB value
x_start vb_color_2 Background color RGB value
vb_x_start x-coordinate of the vertical line
vb_x_end Not used
y_start
vb_y_start y-coordinate of the horizontal line
vb_y_end Not used

Table 15-16 Video BIST Mode A

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MODE 0xB Offset / Parameter Usage
This mode is not used. Not used

Table 15-17 Video BIST Mode B

MODE 0xC Offset / Parameter Usage
Check box with configurable color, vertical offset and vertical repeat count. Vertical repeat in rows.
(Original single pixel checkbox can be obtained by setting offset=0 & repeat=0) 0: 1 line.
vb_repeat_cnt
1: 2 lines.
…
Vertical Offset = 1
Color 1 RGB value (second color of
vb_color_1
the first segment)
Vertical Repeat = 2 Color 2 RGB value (first color of the
vb_color_2
first segment)
vb_x_start Not used
Vertical Repeat = 2 vb_x_end Not used
Vertical Offset in rows. (The first
segment at the top. Must be <=
Vertical Repeat = 2 Vertical repeat)
vb_y_start
0: 1 line.
1: 2 lines.
…
vb_y_end Not used

Table 15-18 Video BIST Mode C

MODE 0xD, 0xE Offset / Parameter Usage
Vertical (0xD) or Horizontal (0xE) moving bar with configurable speed, width, step Number of frames pause between
vb_repeat_cnt
(with direction) and foreground / background color. steps
vb_color_1 Foreground color RGB value
vb_color_2 Background color RGB value
Move step (For mode 0xD, must be
vb_x_start
multiple of four number, singed)
Bar width (For mode 0xD, must be
multiple of four number)
vb_x_end 0 – 4 pixels
4 – 8 pixels
8 – 12 pixels
vb_y_start Move step (For mode 0xE, singed)
Bar width (For mode 0xE)
0 – 1 line
vb_y_end
1 – 2 lines
2 – 3 lines
Note: For odd/even setting, vb_x_start & vb_x_end must be
multiple of eight.

Table 15-19 Video BIST Mode D & E

MODE 0xF Offset / Parameter Usage
Full screen solid fill with configurable color. vb_repeat_cnt Not used
vb_color_1 Solid fill color RGB value
vb_co;or_2 Not used
vb_x_start Not used
vb_x_end Not used
vb_y_start Not used
vb_y_end Not used

Table 15-20 Video BIST Mode F

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16 PACKAGE INFORMATION

16.1 373 BALLS TFBGA

Figure 16-1: Package Information

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 Solomon Systech reserves the right to make changes without notice to any products herein. Solomon Systech makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any, and all, liability, including without limitation
consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including
“Typical” must be validated for each customer application by the customer’s technical experts. Solomon Systech does not convey any license
under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase
or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and
its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use,
even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part.

The product(s) listed in this datasheet comply with Directive (EU) 2015/863 of 31 March 2015 amending Annex II to Directive
2011/65/EU of the European Parliament and of the Council as regards the list of restricted substances and People’s Republic of
China Electronic Industry Standard GB/T 26572-2011 “Requirements for concentration limits for certain hazardous substances in
electronic information products (电子电器产品中限用物質的限用要求)”. Hazardous Substances test report is available upon request.

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