The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE

140 Design of Logic Systems I

Experiment 14 Finite State Machine Divisibility by 3

Amal Al Katrib
TA: Olivier Serres

Objective of the experiment The objectives of the lab are summarized as following: Design a circuit that checks if a number is divisible or not by 3 At every clock cycle, input one bit of the number to test, starting by the most-significant bit. Keep track of the rest of the division by 3. Sketch state machine with all its transitions. Program in Verilog and implement on FLEX FPGA.

Background Information: Finite State Machine A finite state machine (FSM) is a model of behavior composed of a finite number of states, transitions between those states, and actions. It could also be referred to as sequential circuits, a general class of circuits in which the outputs depend on the past behavior of the circuit, as well as on the present values of inputs. In most cases, a clock signal is used to control the operation of a sequential circuit; such circuit is called a synchronous sequential circuit. The alternative, in which no clock signal is used, is called an asynchronous sequential circuit. Synchronous circuits are easier to design and are used in a vast majority of practical applications. Synchronous sequential circuits are realized using combinational logic and one or more flip-flops. The circuit has a set of primary inputs, W, and produces a set of outputs, Z. Under control of the clock signal, the flip-flop outputs change their state as determined by the combinational logic that feeds the inputs of these flip-flops. Thus the circuit moves from one state to another, where changes in state depend on both the present state and the values of the primary inputs. Sequential circuits whose outputs depend only on the state of the circuit are of Moore type, while those whose outputs depend on both the state and the primary inputs are of Mealy type. Moore State Machine: A Moore machine is a finite state automaton where the outputs are determined by the current state alone (and do not depend directly on the input). The state diagram for a Moore machine will include an output signal for each state. Most digital electronic systems are designed as clocked sequential systems. Clocked sequential systems are a restricted form of Moore machine where the state changes only when the global clock signal changes. Typically the current state is stored in flipflops, and a global clock signal is connected to the "clock" input of the flip-flops. A typical electronic Moore machine includes a combinatorial logic chain to decode the current state into the outputs (lambda). The instant the current state changes, those changes ripple through that chain, and almost instantaneously the outputs change (or don't change).

Mealy State Machine:

a Mealy machine is a finite state machine (and more accurately, a finite state transducer) that generates an output based on its current state and an input. This means that the state diagram will include both an input and output signal for each transition edge.

Resources used in implementing the experiment Altera UP1 Board Max+Plus II Software ByteBlaster parallel port download cable Procedures to implement the experiment, results obtained, and analysis of data: Moore Finite State Machine: First, we sketch a finite state machine to keep track of the division of a number by 3, with its transitions, starting with the most significant bit. The state diagram for the circuit is created as seen below:
Reset

b=0

State A/ Z=1
b=1 b=1

b=1

State C/ Z=0

b=0 b=0

State B/ Z=0

Where at State A we obtain 3k+0, at State B we obtain 3k+1, and at State C we obtain 3k+2. To verify the correctness of the state diagram above, we use the following form: At State A For b=0

When we have an even number, 2n, where n=3k+0 (for State A), we obtain 6k or 3(2k). If we take 2k=k, then we get 3k or 3k+0 State A If we are at State A and we have b=0, the system will stay in State A For b=1 When we have an odd number, 2n+1, where n=3k+0 (for State A), we obtain 6k+1 or 3(2k)+1 If we take 2k=k, then we get 3k+1 State B If we are at State A and we have b=1, the system will move to State B At State B For b=0 When we have an even number, 2n, where n is now 3k+1(for State B), we obtain 6k+2 or 3(2k)+2 If we take 2k=k, then we get 3k+2 State C If we are at State B and we have b=0, the system will move to State C For b=1 When we have an odd number, 2n+1, where n is now 3k+1(for State B), we obtain 6k+3 or 3(2k+1) If we take 2k+1=k, then we get 3k State A If we are at State B and we have b=1, the system will go back to State A At State C For b=0 When we have an even number, 2n, where n is now 3k+2 (for State C), we obtain 6k+4 or 3(2k+1)+1 If we take 2k+1=k, then we get 3k+1 State B If we are at State C and we have b=0, the system will go back to State B For b=1 When we have an odd number, 2n+1, where n is now 3k+2 (for State C), we obtain 6k+5 or 3(2k+1)+2 If we take 2k+1=k, then we get 3k+2 State C If we are State C and we have b=1, the system will stay in State C This could also be tested by using different binary inputs and following the state diagram to see if the path is correct. Combinational Logic Circuit Design

To describe the combinational logic above, the following table is filled out: States A B C S1t 0 0 0 0 1 1 S0t 0 0 1 1 0 0 bin 0 1 0 1 0 1 S1t+1 0 0 1 0 0 1 S0t+1 0 1 0 0 1 0

This could also be written as below to show present and next states and account for the output: States PS S1t S0 t A B C (dont care) 00 01 10 11 b=0 S1t+1 S0t+1 00 10 01 dd NS b=1 S1t+1 S0t+1 01 00 10 dd Output Z 1 0 0 d

To obtain reduced equations for

, we use Karnaughs maps:

00 0 0

01 1 0

11 10 d d 0 1

0 1

00 0 1

01 0 0

11 10 d d 1 0

0 1

The corresponding logic circuit diagram for the reduced equations is as following:
S1t b S1t+1

S0 t

S0t+1

Output: (obtained from truth table this corresponds to a NOR gate) Another combinational logic block is used to generate the final output of the state machine, where out(divisible)=1 if and only if the number is divisible by 3. The output equation requires a NOR gate whose inputs are taken from the Q outputs of the 2 D flip-flops to be used. The following logic circuit is obtained:

1 3 2 2 Inbit 3 2 1 1 3 2 1

1 3 Q 5 6 3 1 2 3 4 2 2 1

2 3

CLK Q
1 10

CLR

PRE

2 1 Q 9 8 3 Outbit

12 Clock
CLK

CLK Q
13

Verilog Version of the FSM A verilog code for the FSM is created using a case statement. A reset signal is added to set the state to r=0. Max+Plus II Software is opened. We go File, New, Text, and then enter the code below:

module moore(Clock, Reset, Inbit, Outbit); input Clock, Reset, Inbit; output Outbit; reg Outbit; reg [1:0] state; parameter [1:0] A=0, B=1, C=2; always @(posedge Clock) begin if(Reset) state = A; else case (state) A: begin if(Inbit) state = B; else state = A; end B: begin if(Inbit) state = A; else state = C;

CLR

11

PRE

end C: begin if(Inbit) state = C; else state = B; end endcase if (state == A) Outbit = 1; else Outbit = 0; end endmodule
The file is saved as .v. We go to Compiler and hit start. Next we go to File, Edit Window, select nodes for simulation, End Time, add clock signal, and then Simulator. Now, the code is simulated in in

Max+Plus II.

Implementation on the FLEX FPGA

In order to test the circuit on the UP1 board, a module is designed to feed input bits to the Moore FSM. The module always resets the FSM and provides at each clock cycle one bit of the number. The result of divisibility by 3 is displayed by an LED. Below is the module testbench created: module testbench(Bits, Clock, DivThree); input Clock, Bits; wire[0:7] Bits; output DivThree; reg DivThree; reg[8:0] count; reg abit; reg reset; wire outfsm; always @(posedge Clock) begin if(count == 9)

count = 0; else count = count+1; case(count) 0: begin reset = 0; abit = Bits[0]; end 1: abit = Bits[1]; 2: abit = Bits[2]; 3: abit = Bits[3]; 4: abit = Bits[4]; 5: abit = Bits[5]; 6: abit = Bits[6]; 7: abit = Bits[7]; 9: begin reset = 1; DivThree = outfsm; end endcase end moore moor2(Clock, reset, abit, outfsm); endmodule Simulation of the FSM with the feed module is now run.

Figure 1: Timing diagram of testbench module

The device in hand is chosen. Next, we assign the pins appropriately:

Dip switch inputs are: 0 33 1 34 2 35 3 36 4 38 5 39 6 40 7 41 Clock pin assignment is 91 LED pin assignment is 14 The code is programmed to the FPGA. The code is tested by choosing different inputs on the Dip switch and observing the outputs on LED (dot of the 7-segment display). Huge Numbers and Speed The current design can test 25.7 million bits/sec if the state machine were to test a huge number having millions of bits. Since large numbers can be divided into smaller ones, testing 50 million bits/sec can be established through parallel computing that carries many instructions simultaneously. Additionally, by testing for more than 1 bit at a time, it is possible to test 10 numbers having 10 million bits/sec.

Conclusion
The experiment was conducted successfully and with no apparent errors. To verify the accuracy of the code, various inputs were applied using the dip switch and the outputs were observed on the 7segment display dot. The dot lit up when an input not divisible by 3 was applied, which is indicates a success in finishing the experiment. The objectives were full met as the student got familiarized with Moore Finite State Machines and creating Verilog codes that could implement such state machine on an FPGA.

References: Brown, Stephen and Zvonko Vranesic. Fundamentals of Digital Logic with VERILOG Design, 2006 http://blackboard.gwu.edu/webapps/portal/frameset.jsp?tab=courses&url=/bin/common/course .pl?course_id=_103922_1 http://en.wikipedia.org/wiki/Mealy_machine http://en.wikipedia.org/wiki/Moore_machine