FACULTY OF APPLIED SCIEINCES

UNIVERSITI TEKNOLOGI MARA

LABORATORY MANUAL
PHY548
 Handout

Data Sheet
 VCC
14 13 12 11 10 9 8
http://onsemi.com

LOW
POWER
1 2 3 4 5 6 7
SCHOTTKY
GND

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V 14
TA Operating Ambient 0 25 70 °C
1
Temperature Range
PLASTIC
IOH Output Current – High – 0.4 mA N SUFFIX
IOL Output Current – Low 8.0 mA CASE 646

14
1

SOIC
D SUFFIX
CASE 751A

ORDERING INFORMATION

Device Package Shipping

SN74LS08N 14 Pin DIP 2000 Units/Box

SN74LS08D 14 Pin 2500/Tape & Reel

© Semiconductor Components Industries, LLC, 1999 1 Publication Order Number:

December, 1999 – Rev. 6 SN74LS08/D
 VCC
14 13 12 11 10 9 8
http://onsemi.com

LOW
POWER
1 2 3 4 5 6 7
SCHOTTKY
GND

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V 14
TA Operating Ambient 0 25 70 °C
1
Temperature Range
PLASTIC
IOH Output Current – High – 0.4 mA N SUFFIX
IOL Output Current – Low 8.0 mA CASE 646

14
1

SOIC
D SUFFIX
CASE 751A

ORDERING INFORMATION

Device Package Shipping

SN74LS32N 14 Pin DIP 2000 Units/Box

SN74LS32D 14 Pin 2500/Tape & Reel

© Semiconductor Components Industries, LLC, 1999 1 Publication Order Number:

December, 1999 – Rev. 6 SN74LS32/D
 VCC
14 13 12 11 10 9 8
http://onsemi.com

LOW
POWER
1 2 3 4 5 6 7 SCHOTTKY
GND

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 4.75 5.0 5.25 V 14
TA Operating Ambient 0 25 70 °C
1
Temperature Range
PLASTIC
IOH Output Current – High – 0.4 mA N SUFFIX
IOL Output Current – Low 8.0 mA CASE 646

14
1

SOIC
D SUFFIX
CASE 751A

ORDERING INFORMATION

Device Package Shipping

SN74LS04N 14 Pin DIP 2000 Units/Box

SN74LS04D 14 Pin 2500/Tape & Reel

© Semiconductor Components Industries, LLC, 1999 1 Publication Order Number:

December, 1999 – Rev. 6 SN74LS04/D
 CD4081BM/CD4081BC Quad 2-Input AND Buffered B Series Gate
CD4071BM/CD4071BC Quad 2-Input OR Buffered B Series Gate
February 1988

CD4071BM/CD4071BC
Quad 2-Input OR Buffered B Series Gate
CD4081BM/CD4081BC
Quad 2-Input AND Buffered B Series Gate
General Description Features
These quad gates are monolithic complementary MOS Y Low power TTL Fan out of 2 driving 74L
(CMOS) integrated circuits constructed with N- and P-chan- compatibility or 1 driving 74LS
nel enhancement mode transistors. They have equal source Y 5V – 10V – 15V parametric ratings
and sink current capabilities and conform to standard B se- Y Symmetrical output characteristics
ries output drive. The devices also have buffered outputs Y Maximum input leakage 1 mA at 15V over full tempera-
which improve transfer characteristics by providing very ture range
high gain.
All inputs protected against static discharge with diodes to
VDD and VSS.

Connection Diagrams
CD4071B Dual-In-Line Package

TL/F/5977 – 3
Top View

CD4081B Dual-In-Line Package

TL/F/5977 – 6
Top View

Order Number CD4071B or CD4081B

C1995 National Semiconductor Corporation TL/F/5977 RRD-B30M105/Printed in U. S. A.

 ® 2N3904

SMALL SIGNAL NPN TRANSISTOR

PRELIMINARY DATA

Ordering Code Marking Package / Shipment

2N3904 2N3904 TO-92 / Bulk
2N3904-AP 2N3904 TO-92 / Ammopack

■ SILICON EPITAXIAL PLANAR NPN

TRANSISTOR
■ TO-92 PACKAGE SUITABLE FOR
THROUGH-HOLE PCB ASSEMBLY
■ THE PNP COMPLEMENTARY TYPE IS
2N3906
TO-92 TO-92
APPLICATIONS Bulk Ammopack
■ WELL SUITABLE FOR TV AND HOME

APPLIANCE EQUIPMENT
■ SMALL LOAD SWITCH TRANSISTOR WITH

HIGH GAIN AND LOW SATURATION

VOLTAGE
INTERNAL SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
V CBO Collector-Base Voltage (I E = 0) 60 V
V CEO Collector-Emitter Voltage (I B = 0) 40 V
V EBO Emitter-Base Voltage (I C = 0) 6 V
IC Collector Current 200 mA
o
P tot Total Dissipation at T C = 25 C 625 mW
o
T stg Storage Temperature -65 to 150 C
o
Tj Max. Operating Junction Temperature 150 C

February 2003 1/5

 Order this document
SEMICONDUCTOR TECHNICAL DATA by 2N3905/D

PNP Silicon

*Motorola Preferred Device

COLLECTOR
3

2
BASE

1
EMITTER
1
MAXIMUM RATINGS 2
3
Rating Symbol Value Unit
CASE 29–04, STYLE 1
Collector – Emitter Voltage VCEO 40 Vdc TO–92 (TO–226AA)
Collector – Base Voltage VCBO 40 Vdc
Emitter – Base Voltage VEBO 5.0 Vdc
Collector Current — Continuous IC 200 mAdc
Total Device Dissipation @ TA = 25°C PD 625 mW
Derate above 25°C 5.0 mW/°C
Total Power Dissipation @ TA = 60°C PD 250 mW
Total Device Dissipation @ TC = 25°C PD 1.5 Watts
Derate above 25°C 12 mW/°C
Operating and Storage Junction TJ, Tstg – 55 to +150 °C
Temperature Range

THERMAL CHARACTERISTICS(1)
Characteristic Symbol Max Unit
Thermal Resistance, Junction to R JA 200 °C/W
Ambient
Thermal Resistance, Junction to Case R JC 83.3 °C/W

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

Characteristic Symbol Min Max Unit

OFF CHARACTERISTICS
Collector – Emitter Breakdown Voltage (2) V(BR)CEO 40 — Vdc
(IC = 1.0 mAdc, IB = 0)
Collector – Base Breakdown Voltage V(BR)CBO 40 — Vdc
(IC = 10 Adc, IE = 0)
Emitter – Base Breakdown Voltage V(BR)EBO 5.0 — Vdc
(IE = 10 Adc, IC = 0)
Base Cutoff Current IBL — 50 nAdc
(VCE = 30 Vdc, VEB = 3.0 Vdc)
Collector Cutoff Current ICEX — 50 nAdc
(VCE = 30 Vdc, VEB = 3.0 Vdc)

1. Indicates Data in addition to JEDEC Requirements.

2. Pulse Test: Pulse Width 300 s; Duty Cycle 2.0%.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

Motorola Small–Signal Transistors, FETs and Diodes Device Data 1

© Motorola, Inc. 1996
 SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988

PRODUCTION DATA information is current as of publication date. Copyright © 1988, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

 SN5446A, ’47A, ’48, SN54LS47, ’LS48, ’LS49
SN7446A, ’47A, ’48, SN74LS47, ’LS48, ’LS49
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
SDLS111 – MARCH 1974 – REVISED MARCH 1988

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

 DM7446A, DM7447A BCD to 7-Segment Decoders/Drivers
September 1986
Revised July 2001

DM7446A, DM7447A
BCD to 7-Segment Decoders/Drivers
General Description Features
The DM7446A and DM7447A feature active-LOW outputs ■ All circuit types feature lamp intensity modulation
designed for driving common-anode LEDs or incandescent capability
indicators directly. All of the circuits have full ripple-blank- ■ Open-collector outputs drive indicators directly
ing input/output controls and a lamp test input. Segment
■ Lamp-test provision
identification and resultant displays are shown on a follow-
ing page. Display patterns for BCD input counts above nine ■ Leading/trailing zero suppression
are unique symbols to authenticate input conditions.
All of the circuits incorporate automatic leading and/or trail-
ing-edge, zero-blanking control (RBI and RBO). Lamp test
(LT) of these devices may be performed at any time when
the BI/RBO node is at a HIGH logic level. All types contain
an overriding blanking input (BI) which can be used to con-
trol the lamp intensity (by pulsing) or to inhibit the outputs.

Ordering Code:
Order Number Package Number Package Description
DM7446AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
DM7447AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Connection Diagram

© 2001 Fairchild Semiconductor Corporation DS006518 www.fairchildsemi.com

DM7446A, DM7447A
Function Table
Decimal or Inputs BI/RBO Outputs
Note
Function LT RBI D C B A (Note 1) a b c d e f g
0 H H L L L L H L L L L L L H
1 H X L L L H H H L L H H H H
2 H X L L H L H L L H L L H L
3 H X L L H H H L L L L H H L
4 H X L H L L H H L L H H L L
5 H X L H L H H L H L L H L L
6 H X L H H L H H H L L L L L
7 H X L H H H H L L L H H H H (Note 2)
8 H X H L L L H L L L L L L L
9 H X H L L H H L L L H H L L
10 H X H L H L H H H H L L H L
11 H X H L H H H H H L L H H L
12 H X H H L L H H L H H H L L
13 H X H H L H H L H H L H L L
14 H X H H H L H H H H L L L L
15 H X H H H H H H H H H H H H
BI X X X X X X L H H H H H H H (Note 3)
RBI H L L L L L L H H H H H H H (Note 4)
LT L X X X X X H L L L L L L L (Note 5)
H = HIGH level, L = LOW level, X = Don’t Care
Note 1: BI/RBO is a wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO).
Note 2: The blanking input (BI) must be OPEN or held at a HIGH logic level when output functions 0 through 15 are desired. The ripple-blanking input (RBI)
must be OPEN or HIGH if blanking of a decimal zero is not desired.
Note 3: When a LOW logic level is applied directly to the blanking input (BI), all segment outputs are HIGH regardless of the level of any other input.
Note 4: When ripple-blanking input (RBI) and inputs A, B, C, and D are at a LOW level with the lamp test input HIGH, all segment outputs go H and the rip-
ple-blanking output (RBO) goes to a LOW level (response condition).
Note 5: When the blanking input/ripple-blanking output (BI/RBO) is OPEN or held HIGH and a LOW is applied to the lamp-test input, all segment outputs are
L.

Logic Diagram

www.fairchildsemi.com 2
 ADC0802, ADC0803
ADC0804
8-Bit, Microprocessor-
August 1997 Compatible, A/D Converters

Features Description
• 80C48 and 80C80/85 Bus Compatible - No Interfacing The ADC0802 family are CMOS 8-Bit, successive-approxi-
Logic Required mation A/D converters which use a modified potentiometric
• Conversion Time < 100µs ladder and are designed to operate with the 8080A control
bus via three-state outputs. These converters appear to the
• Easy Interface to Most Microprocessors processor as memory locations or I/O ports, and hence no
• Will Operate in a “Stand Alone” Mode interfacing logic is required.
• Differential Analog Voltage Inputs The differential analog voltage input has good common-
• Works with Bandgap Voltage References mode-rejection and permits offsetting the analog zero-input-
voltage value. In addition, the voltage reference input can be
• TTL Compatible Inputs and Outputs adjusted to allow encoding any smaller analog voltage span
• On-Chip Clock Generator to the full 8 bits of resolution.
• 0V to 5V Analog Voltage Input Range (Single + 5V Supply)
• No Zero-Adjust Required

Ordering Information
PART NUMBER ERROR EXTERNAL CONDITIONS TEMP. RANGE (oC) PACKAGE PKG. NO

ADC0802LCN ±1/2 LSB VREF/2 = 2.500VDC (No Adjustments) 0 to 70 20 Ld PDIP E20.3

ADC0802LCD ±3/4 LSB -40 to 85 20 Ld CERDIP F20.3

ADC0802LD ±1 LSB -55 to 125 20 Ld CERDIP F20.3

ADC0803LCN ±1/2 LSB VREF/2 Adjusted for Correct Full Scale 0 to 70 20 Ld PDIP E20.3
Reading
ADC0803LCD ±3/4 LSB -40 to 85 20 Ld CERDIP F20.3

ADC0803LCWM ±1 LSB -40 to 85 20 Ld SOIC M20.3

ADC0803LD ±1 LSB -55 to 125 20 Ld CERDIP F20.3

ADC0804LCN ±1 LSB VREF/2 = 2.500VDC (No Adjustments) 0 to 70 20 Ld PDIP E20.3

ADC0804LCD ±1 LSB -40 to 85 20 Ld CERDIP F20.3

ADC0804LCWM ±1 LSB -40 to 85 20 Ld SOIC M20.3

Pinout Typical Application Schematic

ADC0802, ADC0803, ADC0804
(PDIP, CERDIP) 1 CS V+ 20 +5V 150pF
TOP VIEW 2 RD CLK R 19
3 WR CLK IN 4 10K
CS 1 20 V+ OR VREF 5 INTR
RD 2 19 CLK R 11 DB7
µP BUS

12 DB6
WR 3 18 DB0 (LSB) ANY
µPROCESSOR 13 DB5
CLK IN 4 17 DB1 8-BIT RESOLUTION
14 DB4 VIN (+) 6 OVER ANY
INTR 5 16 DB2 DIFF
15 7 DESIRED
DB3 VIN (-) INPUTS
VIN (+) ANALOG INPUT
6 15 DB3 16 DB2 AGND 8 VOLTAGE RANGE
VIN (-) 7 14 DB4 17 DB1 VREF/2 9 VREF/2
8 13 DB5 18 DB0 DGND 10
AGND
VREF/2 9 12 DB6
DGND 10 11 DB7 (MSB)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. File Number 3094.1
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
6-5
 ADC0802, ADC0803, ADC0804

Functional Diagram

2 READ
RD

1 “1” = RESET SHIFT REGISTER

CS SET Q “0” = BUSY AND RESET STATE RESET
3
WR

CLK R INPUT PROTECTION

FOR ALL LOGIC INPUTS
19
INPUT CLK
TO INTERNAL
CLK A CIRCUITS
G1
RESET
CLK IN D
CLK BV = 30V
4 GEN CLKS DFF1
CLK OSC START F/F Q
10
DGND
START
CLK B
CONVERSION
MSB D
V+ 20
(VREF)
LADDER SUCCESSIVE 8-BIT
AND APPROX. SHIFT
DECODER REGISTER REGISTER
AND LATCH IF RESET = “0”
9
VREF/2 R

RESET INTR F/F

DAC Q
LSB
AGND 8 VOUT

CLK A
V+
D

COMP DFF2
6 + - Q
VIN (+) ∑ +
- Q

THREE-STATE XFER SET

G2
7 OUTPUT LATCHES
VIN (-)
5
MSB LSB
CONV. COMPL. INTR

11 12 13 14 15 16 17 18
8 X 1/f
DIGITAL OUTPUTS
THREE-STATE CONTROL
“1” = OUTPUT ENABLE

6-6