CAPGEMINI

1) Explain ASIC Flow

2) Inputs to PD Flow
3) Sanity checks of Floor plan
4) Macros placement guidelines
5) What ate physical cells and difference between Physical and Logical cells?
6) What will you do in placement?
7) What will you do in CTS and Routing?
8) What are signoff checks?
9) What is LVS, DRC?
10) Explain few DRC rules
11) What is Antenna rule and how to fix?
12) How to fix setup & hold violations
13) What is setup & hold time?
14) What is skew?
15) What is SI, Noise, xtalk and how to fix?

1) Tell me about yourself

2) Explain me about the project
3) Antenna effect
4) Physical cells you used in project, purpose of tap & tie cells
5) What is DRC & what will we do
6) What is crosstalk & what are its remedies
7) Why metal layers are in horizontal & vertical fashion.

1) Goals of CTS
2) Post routing
3) Hold and setup fixes

1) Self-introduction
2) ASIC flow
3) Inputs to PD flow
4) Sanity checks at Floorplan
5) Each stage summary
6) Challenges for each stage
7) What are physical only cells
8) What is placement blockages and type
9) What is routing
10) How to fix setup and hold violations
11) What are DRC violations
12) What is LVS checks
13) What is metal density
14) What is skew
15) What is library setup and hold time
16) What is antenna effect, methods to fix antenna

1) Tell me about yourself

2) Explain me about the project
3) Antennna effect
4) Physical cells you used in project, purpose of tap & tie cells
5) What is DRC & what will we do
6) What is crosstalk & what are it's remedies
7) Why metal layers are in horizontal & vertical fashion.

1) Tell me about your self

2) Explain PD design flow each and every stage
3) What are the inputs for PD
4) What are checks will do before PD (sanity checks)
5) What are the output files of PD
6) Some of the commands in PD
7) Why do we are doing hold after CTS.
8) What you do in physical verification
9) What about LVS and DRC
10) What commands used in DRC
11) Which tool used for DRC
12) What is STA in which tool you did STA
13) What are the commands for setup check in STA
14) What is setup and hold & why you are checking setup?
15) What is skew and positive & negative skew
16) What is OCV &derate
17) CMOS Fabrication steps & Power dessipation concept
18) How many macros used in your design & how do you placed
19) what are timing exceptions(false path, multi cycle path, half cycle path)& commands
for exceptions
20) Where setup and hold check for half cycle path...consider 10ns time period.
21) Output file after synthesis.

1) Tell me about yourself

2) what are the inputs to PD
3) Stages of PD flow
4) Challenges faced in PD flow
5) what we do in physical verification(PV)
6) explain PV flow
7) About DRC,LVS,ERC
8) fabrication process
9) what do you know about MOSFET
10) what is Antenna effect and why does it affect only some nets

1) Self intro
2) PD flow brief explain
3) PV flow
4) LVS

1) Self-introduction
2) Brief explanation of PD flow
3) Physical verification
4) LVS
5) Antenna effect
6) Fixes of antenna effect
7) About capacitance

1) Introduction
2) CMOS basics working
3) Inputs to PD
4) PD flow
5) Physical verification
6) Floorplan in depth
7) Crosstalk
8) Antenna effects and fixes in depth
9) Why MOSFET not used much in industry

1) Introduce yourself
2) Brief about your project.
3) Detailed explanation of PD flow and how u performed all these in tools.
4) Basics of CMOS and logic gates using CMOS.
5) About LVT, SVT, HVT.
6) Some of the commands used in UNIX system.
7) Problems on STA
8) What is Setup and hold time
9) TCL programming

1) self introduction
2) Pd flow
3) Project summary
4) About the Unix commands
5) How we get setup nd hold violations
6) Fixing of setup nd hold violations
7) Pv

1) self introduction
2) PD inputs
3) what will do in floor plan
4) placement inputs
5) How will fix the congestion
6) Is there any timing violations in placement stage...
7) set and hold time and fixes
8) cross talk
9) some STA problems
10) unix commands
11) tcl scripting
12) why need to CMOS

1) Asic flow in detail explanation

2) Synthesis inputs&outputs, tools for synthesis
3) floorplan in detail
4) how the macros gets placed and what is the file for macros
5) y we use halos
6) placement stages, how only few std cells can be placed/how to place selected std
cells in core
7) what happens in CTS? What happens if we change frequency? Why we need set up
and hold?what happens if we don't check?
What is latency?
8) what is routing?what happens in routing?
9) tcl scripting commands
10) unix commands
11) gvim commands
12) diff b/w BJT and Mosfet
13) What is the use of digital in PD? Y we are going for digital

1) physical design flow

2) inputs pd
3) synthesis inputs and outputs which tool.
4) pnr flow stages what you know.
5) floor plan and placement inputs.
6) CTS and what pre and post CTS.
7) Routing resources
8) Physical verification detail.
9) Without drc if manufacturing chip.
10) physical only cells.
11) Tap, endcap, metalfill, decap.
12) Sta analysis.
13) Setup and hold.
14) Without setup and hold.
15) Digital.
16) CMOS.
17) Unix commands in detail.
18) Tcl commands.
19) Flip flops, clocks.
20) Drc tool, sta tool.

1) Pd Flow
2) Inputs pd
3) Floorplan detailed
4) Placement Detailed
5) CTS Detailed
6) routing Detailed
7) Setup and Hold
8) insertion Delay
9) Congetion
10) CMOS
11) TCL Commands
12) Physical only Cells and what is purpose
13) Digital and Vlsi what is The link
14) What's is Synthasis and Inputs oupts
15) Post CTS
16) Why your Using Buffers
17) What is Filler cells
18) PV Flow
19) What is LVS,DRC and Inputs of LVS
20) What is STA
21) project Summary
22) What purpuse Of M7,M5 metal layers
23) What Is EM
24) What is Setup And Hold Time equations
25) Unix commands
26) TCL Commands

1) Introduction
2) Pd flow
3) Explain each stage of pd flow
4) Setup n hold fixing
5) Antenna effects
6) Cmos
7) Project summary
8) SPEF
9) TCL command
10) Lvt hvt
11) Vth
12) Drc n sta tools
13) Xtalk

1) Introduction
2) Pd flow
3) Explain each stage of pd flow
4) Setup n hold fixing
5) Antenna effects
6) Cmos (implementation s)
7) Project summary
8) SPEF
9) Sdc command
10) Lvt hvt
11) Vth
12) Drc n sta tools
13) Xtalk
14) Metal layers
15) Cts cells
16) Ocv and Aocv
17) multi cycle path
18) NDR rules
19) setup n hold formulas
20) Cell delay parameters
21) abt physical cells(in detail)
22) congestion fixings
23) inputs of pd flow
24) what are tools used
25) LVS
26) temperature inversion
27) CRPR
28) spare cells
29) global routing n detailed routing
30) synthesis stages
31) diff btw ff n latch
32) propagation delay parameters
1) Intro.
2) Info abt training
3) Asic & PD flow with inputs
4) Antenna violation & fix
5) CMOS
6) Latchup
7) TCL
8) W/L resistance and capacitance
9) PV, LVS, drc

1) Synthesis inputs nd outputs

2) why we use synthesis even we have RTL
3) pnr flow
4) floorplan
5) without macros u can do floorplan what is the use
6) Powerplan why we use different metal layers what is the use
7) CTS
8) lvs,DRC,
9) setup ,hold,skew,latency

1) Introduce yourself
2) Explain about project
3) what are the challenge faced on your projects
4) explain Pd flow in Detail
5) what is Threshold voltage
6) what is Sub threshold voltage
7) what is functions of mux and demux
8) setup slack equation and hold slack equation
9) what NDR?
10) physical verification checks(lvs, drc, formality)
11) what are the power dissipation and types explain in Detail
12) If width of the metal layer increases means what happen to RC
13) fanout , max Tran
14) what are the guidelines to place macros

1) SD
2) PD flow
3) tool commands
4) synthesis steps
5) wt the DEF,SPEC,SPEF &.lef file contains
6) how to fix setup without lvt and upsizing
7) DRC, DRV, NDR
8) cmos working
9) Wt are the issues/challenges facing during project
10) Congestion
11) Physical cells ,Antenna effects
12) some practical questions related PD work
13) setup & hold violations,fixes
14) CRPR

1) SD
2) PD flow
3) tool commands
4) NDR Rule
5) wt the DEF,SPEC,SPEF &.lef file contains
6) how to fix setup without lvt and upsizing
7) DRC, DRV, NDR
8) cmos working
9) Wt are the issues/challenges facing during project
10) Congestion
11) Physical cells ,Antenna effects
12) some practical questions related PD work
13) setup & hold violations,fixes
14) CRPR
15) problem in setup and hold
16) signoff issues check
17) Full details of the project I did tell them
18) All Clock information in project
19) Violations

1) PD inputa
2) pd inputs contains
3) pd flow
4) fix setup and hold
5) setup slack and it's formula
6) hold slack and it's formula
7) ocv
8) derates explain
9) xtalk and noise difference
10) fix xtalk and noise
11) setup formula after ocv
12) PVT conditions for setup and hold

1) Pd flow
2) Lvs
3) DRC
4) Setup and hold
5) Timing paths
6) Floor planning
7) Pla
8) Cement
9) CTS
10) Signoff
11) Scripting
12) Linux Commands

1) Pd flow
2) Lvs
3) DRC
4) Setup and hold
5) Timing paths
6) Floor planning
7) Placement
8) CTS
9) Cmos
10) Skew
11) Physical cells ,Antenna effects, congestion,cell density, pindensity,commands for
keepout margin
12) All Clock information in project, DRC, DRV, Timing Exceptions

1) Introduce yourself
2) What is ndr
3) What is skew
4) Explain about pd flow
5) What is local skew and global skew
6) What is setup and hold time
7) What is antenna effect
8) Some qns on project
9) What is cmos,mofect,bjt
10) What is verilog
11) Unix commands
12) Differents between lunch and flip-flop
13) What is timing closure in vlsi
14) What is spef
15) What is congestion
16) Lef file is logical or physical give the Explain
17) What is look up table
18) What commands used for scan chain commands
19) Drv,skew
20) How to fix setup and hold
21) Cmos working
22) Violation
23) Ir violation

1) Self intro
2) Drv
3) Setup hold slack
4) pd flow
5) synthesis
6) sanity checks
7) floorplan
8) physical only cells
9) which frequency used in the project.
10) power dissipation
11) ndr
12) MOSFET
13) skew,local and global skew.
14) Timing constraints
15) False path multi path
16) Mux demux
17) Congestion
18) Some of the commands used
19) lib file, tlu files
20) Threshold,subthreshold.

1) Self intro
2) DRV, DRC, LVS
3) Power planning
4) PD flow
5) Sanity check
6) PD inputs and it contains
7) Congestion and how to avoid congestion
8) Crosstalk and how avoid the crosstalk
9) How to find crosstalk
10) Explain your project
11) Floorplan and placement goals
12) Some tool commands

1) Self intro
2) Inputs to pnr tool
3) Hw to place the macros
4) Pd flow
5) Timing exceptions
6) Some questions on sdc file
7) Setup time
8) Cts
9) Routing
10) More questions based on tool

1) Self intro
2) Pnr flow
3) Inputs to PnR
4) Why do we fix setup before placement .
5) Timing exceptions
6) Diff bw global vs detailed routing
7) Macro guidelines
8) Setup & hold
9) How to fix timing path violations
10) Challenges faced in diff stages

1) Self Intro
2) Inputs to PNR
3) Cross talk and Noise
4) Goals of Placement
5) OCV and PVT conditions
6) Setup and Hold formulas
7) Ways to fix transition time
8) Challenges faces during PNR .
9) Timing constraints
10) Clock constraints
11) Commands used in ICC tool

1) Self intro
2) Inputs for pnr and placements
3) CTS,SDC
4) Setup violations
5) Tool commands
6) Routing types and inputs
7) Setup equation
8) More questions on tool

1) Self intro
2) Inputs for pnr
3) Guidelines for macro placement
4) What Sdc, technology and def file contains
5) More questions on tool

1) What are inputs to pnr

2) What is esd
3) What is em
4) Antenna affect
5) Lvs drc format
6) Stick diagram of inverter
7) About project
8) Fabrication steps
9) ASIC flow
10) Norton theorem

1) cmos
2) diode nd characteristics
3) npn transistor
4) cmos inverter
5) bjt ,
6) finfet
7) difference between combinational nd sequential
8) conductors, semiconductor and insulators
9) extrinsic semiconductor nd intrinsic semiconductor
10) differnce between n type nd ptype
11) Latchup antenna effect electrostatic discharge,electro migration,ir drop
12) how we can find standard cells height.where we can use it
13) asic flow
14) layout tool commands
15) schematic diagram of inverter
16) some examples she has given to me to explain in aptitude
17) analog and digital difference
18) differnce between mosfet ,fet finfet
19) why pmos is pull up nd nmos pull down
20) ion implantation
21) Fabrication steps
22) layout steps
23) schematic definition
24) current matching and voltage matching difference
25) resistors, capacitor,voltage definition
26) types of resistors
27) ohmslaw not definition..why it is use of it nd formula explanation
28) Moore's law
29) gds ,pdk
30) twin tub process
31) cmos advantages and disadvantage
32) band gap theory
33) why nd what is the use of vlsi.
34) how many transistor we r using in a chip
35) she has given 1 square box with 4 rows nd 4 colums..and 8 dots which is not
intersected each other
36) AAAA BBBBB CCCCCC
WE CAN make equal this

1) self intro
2) Endcap cells
3) Why do we use end cap cells
4) Stages of pd ( floorplan and placement in detail)
5) Outcomes of placement stage
6) what is setup , and equation of setup time
7) How do we fix set up violations
8) What is hold , how do we fix ,
9) Where do we insert buffer to fix hold violations
10) What is ocv modelling
11) About course duration and start and end months of course.
12) What do u mean by congestion , how to overcome congestion.
13) What is cross talk , and cases of crosstalk in victim and aggressor
14) what is latch up , what is done to avoid latch up
15) What are tap cells , where do we place them

1) Self intro
2) Input file
3) Floorplan
4) Guidelines to macro
5) Physical cells
6) Taps cells
7) Latchup effect
8) Placement
9) Output reports of placement
10) What is setup and hold
11) How to overcome setup violations

1) Self introduction
2) Pd flow
3) Congestion
4) Cross talk
5) Set and hold checks
6) Sign off
7) Linux commands
8) About project
9) More questions on tool
10) Level shifters
11) Antenna violations
12) Clock gating

1) Self introduction
2) PD flow
3) Linux command
4) TCL command
5) Sign off
6) About project full explanation each stage of PD flow

1) Antenna violations
2) More questions on tool
3) Setup time and hold time
4) CTS stage
5) CMOS inverter
6) Threshold voltage

1) Self introduction
2) Overall what you learned in your course
3) What is course duration
4) Pd flow
5) Fixing steps for congestion
6) Setup and hold ,in detail
7) Setup and hold voilations fixes
8) Tool commands used
9) Unix commands-asked commands about,how to open a file
10) Lvt,hvt,,derive setup and time with eqution and waveform,slew,latency,what is
upsizing cell and down sizing cell
11) Draw the diagram of floor plan

1) Self introduction
2) What you learned in you course
3) What is course duration
4) PD flow
5) Setup and hold time
6) Ask to draw setup and hold wave forms
7) What is Synthesis
8) What we do in routing
9) Brief is cts
10) Project
11) Marcos in project
12) How macros placed in Floor plan
13) Objective of Floor plan

1) physical design flow

2) mosfet
3) crosstalk glitch
4) antena effect and how to overcome it
5) flip-flops ckt,tt
6) types
7) difference between flip flops and latches
8) floorplan
9) placement
10) IR drop

1) Briefly explain about pd flow

2) What are the inputs of pd
3) Which tool are used in your project and briefly explain about the tool which you
used in your project

1) explain about project

2) power planning inputs
3) after power plan any checks....
4) set up and hold time and fixing it
5) types of cells in project
6) end cap cells
7) pd flow
8) lvs
9) filler and decap cells
10) wt is diode and transistor
11) wt is the capacitor
12) wt is resistor
13) xor gate from nand gate
14) antenna effect
15) voltage drop
16) isolations cells
17) draw latch up phenomenon
18) how u placed macros in placement stage in the project
19) scripting
20) 5-10 commands in Linux

1) SD
2) LVS,DRC,antenna effect
3) length x,width y ,if increase length 2x what about resistance, capacitance
1) Electromigration
2) Signal integrity
3) Some Linux commands
4) Fanout increase, what about delay
5) What is meshm
6) Etching
7) Antenna violation, how to overcome it?
8) What is echo?
9) LVS concept
10) DRC violations
11) About PL51
12) Voltage drivers
13) Cross talk glitch
14) About project
15) floor plan inputs
16) Sanity checks
17) Macro guide lines

1) self introduction
2) explain about asic flow and pd flow briefly.
3) explain about pd project
4) what is mosfet.
5) explain favorite subject for 8 th semester

1) Asic flow
2) PD flow
3) IR drop
4) EM
5) Antenna Effect
6) Why we use Mos?
7) Electronics Means
8) Power Gating
9) DRVs
10) Latches and flipflop
11) Endcap cells
12) Tap cells
13) Power planning
14) Which Tool we r used in project.
15) If Resistance increases, then time will b
16) Scripting languages
17) TCL
18) Applications of buffer

1) self intro
2) sanity checks
3) complete pnr flow with each stage brief explanation.
4) lvs check
5) LEC check
6) ERC check
7) channel length purpose
8) what is routing

1) Project description
2) Pd flow
3) Floorplan
4) Macro Guidelines
5) What are the verifications
6) DRC
7) CMOS
8) Antenna effect
9) OR gate
10) LINUX command
11) CTS
12) Resistor and capacitor

1) Self introduction
2) Summery of project
3) About physical verification
4) Pd flow
5) inputs to pd flow
6) sanity checks
7) LVS, DRC
8) What is Em
9) What is antenna affect
10) How you will fix setup and hold violations
11) What is crosstalk
12) How the IR drop occures
13) Ocvs and aocvs

1) Pd flow
2) Physical verification
3) Sanity checks
4) Electromigration
5) Antenna effect
6) How to overcome antenna violations
7) Drc and lvs violation
8) Crosstalk
9) Congestion
10) Mosfets realisation
11) Basic digital concepts
12) Power planning
1) physical design flow
2) mosfet
3) crosstalk glitch
4) antena effect and how to overcome it
5) flip-flops ckt,tt
6) types
7) difference between flip flops and latches
8) floorplan
9) placement
10) IR drop
11) physical verification
12) routing
13) Xor gate

1) EM violation
2) About project
3) how you places macros
4) antena violation and how we fix it
5) wire load module
6) what is setup and hold time
7) what are the timing violation
8) DRC and LVS
9) what you will check in DRC
10) what are the timing violation
11) placement command

1) self intro
2) explain ASIC flow and input s
3) explain input files
4) what is tlu file
5) explain PD flow
6) sanity checks why it is required. What is the regions
7) how do fix the setup and hold
8) when you up size when you inside the buffer
9) DRV in Tran violation and hold violation which one do first
10) How good are in drv fixing?

1) Self introduction
2) Asic flow
3) pd flow
4) Antenna
5) CMOS
6) Drc
7) Lvs
8) Diode, Transistor
9) Placement issues
10) Congestion

1) Self introduction
2) LVS
3) pd flow
4) about diode and uses
5) project
6) transistor

1) Self introduction
2) LVS
3) pd flow
4) about diode and uses
5) project
6) transistor

1) Explain about pd flow

2) Pd inputs
3) Project tool name and how many macros are used in your project
4) Explain briefly your project

1) And gate
2) Xor gate
3) Latch and flipflop difference
4) Mux and demux
5) Combinational and sequential difference
6) MOSFET and BJT
7) Why vlsi is most important and example
8) Pd flow
9) Antenna effect
10) Lvs and Drc
11) Tcl command

1) DRC
2) LVS
3) Antenna effect

1) PD Inputs
2) Explanation of Stages of PD
3) DRC
4) DRVS

1) Xor gate truth table and symbol

2) DRC
3) LVS
4) Antenna effect
 5) BJT
6) MOSFET

1) Lvs
2) Drc
3) antenna effect
4) metal wire resistance and capacitance
5) Sd

CYIENT

1) Tell me about yourself

2) What all you learnt in your physical design training
3) What made you choose Physical design only in VLSI having other analog layout and
circuit design?
4) Tool used in the project
5) What is synthesis and inputs of it
6) What are sanity checks
7) What do you do in Floorplan?
8) How do u calculate the spacing between macros
9) What is STA , setup and hold
10) How do you calculate setup and hold time

1) Tell me about yourself

2) why u choose physical design, why not analog layout and circuit
3) Tool used in project
4) Inputs of PD
5) Each stage explanation.
6) What are the checks after each stage
7) Signal integrity
8) timing path groups
9) Fixes of violations and order.
10) Scan chain reordering.
11) CTS spec file

1) Self-introduction
2) Project specifications
3) About synthesis
4) Inputs for PD
5) Sanity checks
6) Each stage explanation and checks after one
7) setup and hold time checks
 8) Crosstalk
9) antenna effect
10) EM
11) How to fix timing after placement
12) Physical only cells
13) How to fix timing violations after synthesis and routing
14) command to find the diver cell of a known buffer
15) Command for path grouping
16) About Positive skew
17) What are the extra setting we will give for routing stage
18) How to fix shorts and spacing violations in routing stage

WIPRO

1) Introduction
2) Which tool you used for designing
3) Inputs of PNR
4) PNR flow
5) What are constraints, urf, DEF
6) Which voltage are used in design
7) What are inputs floorplan, placement
8) Guidelines of macros

1) Telephonic call
2) introduction
3) tools used in project
4) have you completed your project
5) inputs of PNR
6) SDC filles contents
7) PNR flow
8) floorplan inputs files
9) Placement
10) Routing
11) CTS
12) sanity check
13) what are the command used in sanity check
14) DEF files contents and use
15) UPF files contents and use
16) they also asked have you used Prime Time during your training

1) PD flow
2) Input for PD
3) Content for SDC,DEF
4) About project
 5) Practically how to do pd flow each stage
6) Prime time during training

1) Pd flow
2) Inputs for pd
3) Content of inputs
4) About project
5) Steps done while doing PNR
6) Sanity checks
7) Commands used in tool during PNR

1) PNR FLOW
2) tools used in project
3) have you completed your project
4) inputs of PNR
5) SDC filles contents
6) floorplan inputs files
7) Placement
8) Routing
9) CTS
10) sanity check
11) what are the command used in sanity check
12) DEF files contents and use

P2F SEMI

1) self intro
2) Input files
3) PD flow with explanation
4) Synthesis flow with explanation
5) ASIC flow

1) self-introduction
2) PD flow
3) Synthesis flow
4) what are the stages in PD flow
5) What are the stage in synthesis
6) define in PD flow
7) define in synthesis flow
8) Input files
 1) PD flow with explanation
2) Synthesis flow with explanation
3) Self Intro
4) Input files

1) *Introduction
2) *Setup and hold time & formulas
3) *Synthesis flow
4) *PD flow
5) *Uncertainty and jitter
6) *Goals of CTS
7) *Guidelines of macros placement
8) *inputs of PD

MEYVN SYSTEMS

1) self-introduction
2) explain pnr flow
3) setup and hold timing analysis
4) DNR
5) types of routing
6) OCV
7) CTS
8) setup and hold time related problems
9) why that particular technology used in project
10) what are the inputs required to pd flow
11) sanity checks
12) endcap cells and well tap cells

1) Tell me about your self

2) PD flow
3) Set up and hold time
4) Skew, latency, insertion delay definitions
5) Input files for PD

1) Self intro
2) Pd flow
3) Cts in detail
4) Setup and hold
5) Skew, latency

1) Self intro
2) pd flow each and every stages
3) input files of PD

1) Self-introduction
2) PD flow
3) Each stage in PD flow what are the startageis we used to place macros
4) Input files of PD
5) Detail about cts
6) PD verification
7) Explain drc
8) CTS goals
9) Setup and hold time
10) Skew and clock skew

1) Intro
2) PD flow in detail
3) Setup and Hold time
4) Why CTS is done for
5) Inputs of PD

1) Self introduction
2) PD flow
3) Setup and hold time
4) Inputs for pd
5) Congestion

1) self introduction
2) pd flow
3) setup an hold
4) input for pd
5) congestion
6) goals of cts

1) Self intro
2) Set up and hold
3) Congestion
 4) How to resolve the congestion
5) PD flow in detail

1) Self intro
2) Pd flow
3) Congestion
4) Setup and hold time
5) Setup check and hold check

1) Explain detailly about your project.

2) Explain PD flow.
3) Inputs of PD flow, what info does these files contain.
4) Checks before floor plan
5) What are the sanity checks for logical library input file.
6) What does color by hierarchy mean?
7) Who performs the fixing of location for IO ports.
8) Parametric OCV
9) PV
10) scan chain
11) Will you perform hold 13.check at placement stage? If not? Why?
12) Why CTS exactly needed & what you'll do under that?
13) How latency target affect your timing path.

1) complete pd flow before routing

2) what is setup and hold
3) what do we do in floorplan
4) What do we do in placement details

JUNTRAN TECHNOLOGY:

1) Difference between encoder and decoder, latch and flip flop

2) Congestion
3) Setup and hold time
4) Macros
5) Input for Placement, floor plan
6) CMOS inverter operation
7) Verilog code for full adder
8) Short channel effect

1) What are pd inputs

 2) What is skew and types
3) What is antenna affect
4) What is electromigration
5) What is multicycle path
6) What is check legalization
7) What is qor
8) Challenges in cts
9) Congestion

INFINERA:

1) Flipflop
2) Latch
3) Level and edge triggering
4) PD flow full explanation
5) Qtns from each stage including power planning
6) Macro placement
7) I/O port placement
8) Area estimation
9) Input files- sdc n tlu+ files
10) Setup check and hold check
11) Language other than tcl
12) Experience in physical verification
13) Power estimation
14) Dynamic power calculation
15) Temperature inversion
16) Timing Checks for clock

FIRST SILICA:

1) self introduction
2) ASIC flow
3) PD inputs
4) SDC Contains
5) IR Drop
6) Sanity check before PD
7) What is PVT.

1) Self introduction
2) ASIC flow
3) PD flow
4) Input for each stage of PD flow
5) Skew, latency
6) Set and hold optimization techniques

1) Asic flow
2) Sanity checks and reports
3) Inputs of pd
4) Guidelines of macro placement
5) physical only cells
6) placement stage full explanation wt we r doing.wt r the reports we have to check after
placement.
7) setup nd hold definition nd fixes of setup nd hold violation
8) Ir drop
9) check SDC explanation.
1) Self introduction
2) Sanity check
3) Input of pd
4) Guidlines of macro placement
5) Physical cells
6) Congestion
7) Skew
8) Setup and hold fixes
9) Tapcell,end cap cell,d cap cell
10) Explain Sign off

1) self intro
2) synthesis inputs nd outputs
3) sdc,tf
4) difference between lef nd def
5) Timing exceptions( multicyclepath false path with examples)
6) skew, insertion delay,sourcelatency
7) floorplan full explanation
8) placement full explanation
9) ctsfull explanation
10) Latchup,ocv,aocv, crosstalk,antennaeffect
11) Sta inputs
12) sanity checks before pnr in detail

1) Self intro
2) Synthesis input and output
3) Sdc
4) Synthesis flow
 5) Difference between def&lef
6) Sanity checks
7) Physical cell
8) Challenges phase in placement
9) Guidelines of macros placement

SIGN OFF SEMI:

1) Why we preferred cmos in making chip
Transistor function
2) About Gates logic
3) Pd flow
4) Macro placement
5) Latchup issue
6) Setup and hold violation and how to fix
7) CMOS logic
8) About our project
9) Issue faced in project

1) explain pd flow
2) what is physical cells
3) what is tap cells and end cap cells
4) what is skew
5) what is placement blockage which type of blockage we add

1) Introduction yourself
2) PNR flow
3) Inputs of pd flow
4) Skew, insertion deley and types
5) Setup and hold time
6) Sanity checks
7) Floorplan, macros guidelines
8) Channel length equation
9) Setup n hold violation fixes
10) Usefull skew
11) What is Skew, types of skew
12) Input of CTS, what need to fixes in CTS
13) Lvs and drc check
14) Synthesis flow
15) What is Logical synthesis and physical synthesis

AIML SERVICES:
1) What is skew
2) What is uncertainty
3) Guidelines of placement
4) What is bounds
5) How is timing violation
6) What is congestion
7) What is endcap cell
8) Commands of get cells
9) Physical only cell

1) .Explain PD flow
2) Why higher metal layers used fr powerplanning,
3) Guidelines of macro
4) Command fr keepout margin
5) Issues in placement
6) Why cell density arises
7) Setup, hold
8) Decap cells
9) What is IR drop
10) How to get instances name from ref name?
11) Inputs of PD flow.

1) Inputs to PD flow
2) UPF file
3) SDC file
4) Guidelines to place macro
5) Channel length spacing eqn
6) Skew
7) Uncertainity
8) Create clock command
9) Fixing congestion
10) Set up fixes in placement stage
11) Types of Logical bounds
12) Keepout margin and blockages

1) Difference between clock buffers and normal buffers

2) Macros placements
3) Ports placements
4) Input to pd
5) Uncertainty
6) Useful skew
7) Setup and hold
8) Setup fixes
9) Pd flow in detail
1) Explain PD flow
2) Uncertainty
3) Input in PD
4) Physical cells
5) Setup and hold
6) Setup and hold fix
7) Project summary
8) Virtual clock

1) PD flow
2) Different timing violations
3) Difference between STA and dynamic analysis
4) Setup and hold
5) Input to pd

1) PD flow in detail
2) setup and hold violation
3) uncertainty
4) Macros placements
5) input to pd
6) skew
7) where we will check setup & hold
8) commands of IC Compiler

1) PD flow in detail
2) setup and hold
3) Macros placements
4) inputs to pd
5) 10 commands of IC Compiler
6) Parameters used in setup and hold checks

1) Explain Floorplan in detail

2) Placement detail
3) What is congestion
4) Any 10 ICC commands
5) Guidelines of Macros placement
6) which timing violation we check in placement

1) what are the inputs in PD

2) self introduction
 3) timing exception
4) max Tran and max capacitance
5) PD flow
6) Pnr tool
7) Any two icc tool explain
8) def explain, def full observation
9) upf observation

1) Pd flow
2) Set-up time
3) Input for pd
4) Skew
5) Logic Library
6) Upf file
7) How to fix setup
8) Optimization techniques

1) Pnr inputs
2) Floorplanning in detail
3) Placement in detail
4) Icc commands project
5) Sdc commands

1) PNR inputs
2) floorplanning
3) skew
4) latency
5) SDC

1) Latchup remedies and its circuit diagram

2) Short channel effects
3) Second order effects
4) About projects done

i. Pd input
ii. Pnr flow
iii. Floorplan explain
iv. Placement explain
v. How to place Macros

MILIEUDIGITAL:
 1) Floorplan input
2) Cross talk
3) Skew
4) Floorplan output
5) Global routing types
6) CMP
7) PD flow
8) Input for PD

1) Self introduction
2) Which tool used
3) Course completion duration
4) About orcatop

1) Self introduction
2) Which tool is used in Pv
3) About DRC
4) setup and hold violation

1) Self intro
2) They ask abt which tools r using in each stage
3) Physical verification
4) Abt project

INSEMI:
1) write verilog code for full adder and explain the code
2) write verilog code for d f/f explains code
3) differences b/w $finish and $stop
4) explaine $display, $monitor, $stobe
5) difference between blocking and non blocking assignments

1) Self-introduction
2) Why you choose semiconductor profile
3) What’s the inspiration to choose semiconductors?
4) What are the strengths and weaknesses?
5) Which one you prefer among PD & Physical verification

1) Tell me about yourself

2) Explain me about the project
3) Antennna effect
4) Physical cells you used in project, purpose of tap & tie cells
5) What is DRC & what will we do
6) What is crosstalk & what are it's remedies
7) Why metal layers are are in horizontal & vertical fashion.

1) Self introduction
2) ASIC flow
3) Inputs to PD flow
4) Sanity checks at floorplan
5) Each stage summary
6) Challenges for each stage
7) What are physical only cells
8) What is placement blockages and type
9) What is routing
10) How to fix setup and hold violations
11) What are DRC violations
12) What is LVS checks
13) What is metal density
14) What is skew
15) What is library setup and hold time
16) What is antenna effect, methods to fix antenna

1) Tell me about your self

2) Explain PD design flow each and evry stage
3) what are the inputs for PD
4) what are checks will do before PD (sanity checks)
5) what are the output files of PD
6) some of the commands in PD
7) why do we are doing hold after CTS.
8) what you do in physical verification
9) what about LVS and DRC
10) what commands used in DRC
11) which tool used for DRC
12) what is STA in which tool you did STA
13) what are the comands for setup check in STA
14) what is setup and hold & why you are checking setup.
15) what is skew and positive & negative skew
16) what is OCV &derate
17) CMOS Fabrication steps & Power dessipation concept
18) How many macros used in your design & how do you placed
19) what are timing exceptions(false path, multi cycle path, half cycle path)& commands
for exceptions
20) where setup and hold check for half cycle path...consider 10ns time period.
21) output file after synthesis.
1) Tell me about yourself
2) what are the inputs to PD
3) Stages of PD flow
4) challenges faced in PD flow
5) what we do in physical verification(PV)
6) explain PV flow
7) About DRC,LVS,ERC
8) fabrication process
9) what do you know about MOSFET
10) what is Antenna effect and why does it affect only some nets

1) Self introduction
2) Breif explanation of PD flow
3) Physical verification
4) LVS
5) Antenna effect
6) Fixes of antenna effect
7) About capacitance
1) Intro
2) Cmos basics working
3) Inputs to PD
4) Pd flow
5) Physical verification
6) Floorplan in depth
7) Crosstalk
8) Antenna effects and fixes in depth
9) Why mosfet not used much in industry

1) Introduce urself.
2) Brief about your project.
3) Detailed explanation of pd flow and how u performed all these in tools.
4) Basics of CMOS and logic gates using CMOS.
5) About LVT, SVT, HVT.
6) Some of the commands used in UNIX system.
7) Problems on STA

1) self introduction
2) Pd flow
3) Project summary
4) About the Unix commands
5) How we get setup nd hold violations
6) Fixing of setup nd hold violations
7) Pv

1) self introduction
2) PD inputs
3) what will do in floor plan
4) placement inputs
5) How will fix the congestion
6) is there any timing violations in placement stage...
7) set and hold time and fixes
8) cross talk
9) some STA problems
10) unix commands
11) tcl scripting

1) Asic flow in detail explanation

2) Synthesis inputs&outputs, tools for synthesis
3) floorplan in detail
4) how the macros gets placed and what is the file for macros
5) y we use halos
6) placement stages, how only few std cells can be placed/how to place selected std
cells in core
7) 7.what happens in CTS? What happens if we change frequency? Why we need set up
and hold?what happens if we don't check?
8) What is latency?
9) what is routing?what happens in routing?
10) tcl scripting commands
11) unix commands
12) gvim commands
13) diff b/w BJT and Mosfet

1) physical design flow

2) inputs pd
3) synthesis inputs and outputs which tool.
4) pnr flow stages what you know.
5) floor plan and placement inputs.
6) CTS and what pre and post CTS.
7) Routing resources
8) Physical verification detail.
9) Without drc if manufacturing chip.
10) physical only cells.
11) Tap, endcap, metalfill, decap.
12) Sta analysis.
13) Setup and hold.
14) Without setup and hold.
15) Digital.
16) CMOS.
17) Unix commands in detail.
18) Tcl commands.
19) Flip flops, clocks.
20) Drc tool, sta tool.

1) Pd Flow
2) Inputs pd
3) Floorplan detailed
4) Placement Detailed
5) CTS Detailed
6) routing Detailed
7) Setup and Hold
8) insertion Delay
9) Congetion
10) CMOS
11) TCL Commands
12) Physical only Cells and what is purpuse
13) Digital and Vlsi what is The link
14) What's is Synthasis and Inputs oupts
15) Post CTS
16) Why your Using Buffers
17) What is Filler cells
18) PV Flow
19) What is LVS,DRC and Inputs of LVS
20) What is STA
21) project Summary
22) What purpuse Of M7,M5 metal layers
23) What Is EM
24) What is Setup And Hold Time equations
25) Unix commands
26) TCL Commands

1) Introduction
2) Pd flow
3) Explain each stage of pd flow
4) Setup n hold fixing
5) Antenna effects
6) Cmos
7) Project summary
8) SPEF
9) TCL command
10) Lvt hvt
11) Vth
12) Drc n sta tools
13) Xtalk

1) Introduction
2) Pd flow
3) Explain each stage of pd flow
4) Setup n hold fixing
5) Antenna effects
6) Cmos (implementation s)
7) Project summary
8) SPEF
9) Sdc command
10) Lvt hvt
11) Vth
12) Drc n sta tools
13) Xtalk
14) Metal layers
15) Cts cells
16) Ocv and Aocv
17) multi cycle path
18) NDR rules
19) setup n hold formulas
20) Cell delay parameters
21) abt physical cells(in detail)
22) congestion fixings
23) inputs of pd flow
24) what are tools used
25) LVS
26) temperature inversion
27) CRPR
28) spare cells
29) global routing n detailed routing
30) synthesis stages
31) diff btw ff n latch
32) propagation delay parameters

1) Intro.
2) Info abt training
3) Asic & PD flow with inputs
4) Antenna violation & fix
5) CMOS
 6) Latchup
7) TCL
8) W/L resistance and capacitance
9) PV, LVS, drc

1) Explain detailly about your project.

2) Explain PD flow.
3) Inputs of PD flow, what info does these files contain.
4) Checks before floor plan
5) What are the sanity checks for logical library input file.
6) What does color by hierarchy mean?
7) Who performs the fixing of location for IO ports.
8) OCV
9) Parametric OCV
10) PV
11) scan chain
12) Will you perform hold
13) Check at placement stage? If not? Why?
14) Why CTS exactly needed & what you'll do under that?
15) Goals of CTS
16) How latency target affect your timing path.

NUMATO LABS
1) Self Introduction
2) Explain digital electronics
3) BTECH Project explain
4) Explain with the Multiplexer
5) Can you explain basic gate
6) Explain AND GATE
7) Explain sta
8) Difference between sta and dynamic
9) Explain DRC
10) What is Floorplan and explain
11) Power Planning explain

1) Asked about final year project

2) Basic digital communication questions
3) Asked about Verilog

1) Tell me about yourself

2) Tell me engineering project
3) Difference between combinational and sequential
 4) What type of feedback in sequential circuits
5) Explain encoder
6) JK flip flops
7) Explain Floorplan
8) What is Static Timing Analysis
9) Setup and hold

DPIIND
1) Fixing setup and hold
2) PNR flow
3) Macro placement
4) DRC and DRV

MOSLOGI
1) DRC verification
2) Fabrication technics of CMOS
3) Optimization techniques
4) Project info

EXIGER
1) Physical Design flow?
2) CRPR?
3) How will fix the congestion by understanding of GRC Maps?
4) How you will practically worked on fixing the timing violation during placement and
CTS ?
5) What is Setup?
6) How you will fix setup and hold?
7) How you will upsize the driver strength & how you will upsize for CMOS inverter?
8) Why tool placing standard cells why not manually?

MODERNIZE CHIP
1) Good Knowledge on Fundamental of Eletronic Devices
2) VLSI
3) Digital Design knowledge on Latchup Antenna and Second Order Effects
4) Experience in Blocks like LDO,BGR,PLL,DAC and ADC
5) Experience in fixing verifications like DRC,LVS,ANTENNA & ERC.
SMART DV
1) All digital electronics basis
2) What is CMOS?
3) Requirements in designing layout
4) What is FET?
5) What is transistor?
6) SR flip-flop
7) Race around conditions? How to prevent it?
8) Difference between Combinational and Sequential Circuits

1) Amplitude and Frequency modulation

2) Oscillator
3) Bridge rectifiers
4) Combinational and Sequential circuits
5) Universal gates
6) Why they are called universal gates
7) Why it is named as 555ic
8) Why we use positive feedback in oscillator
9) About PLL

1) Verilog basis
2) Combinational and sequential circuits difference
3) Which signals mainly used in digital electronics
4) Tell me about digital electronics
5) Wire, reg data types
6) About Training during projects
7) Digital blocks design, Universal gated

ULKASEMI
1) Self introduction
2) About project
3) Explain each stage in detail from import design to routing
4) What is def
5) What contains in SDC file
6) What is LVS

1) Inputs to PD
2) Explain each stage in detail from import design to routing
 3) LVS
4) SDC
5) Outputs to PD

SYNAPSE DESIGN
1) Self-introduction
2) 2 PD flow explain
3) 3 how set keep out margin either core area or standard cell
4) 4.what are the goals of routing stage
5) drc and PD flow

1) Self introduction
2) About projects Done
3) About macros placement and guidelines required for placement.
4) What happen if we place macro at center ?
5) about STA
6) diff between latch and ff
7) Diff between pba and gba
8) About congestion and methods to reduce
9) Setup and hold violation methods
10) Uncertainty,skew,jitter, crosstalk
11) About script

1) self introduction
2) macros placement and guidelines
3) inputs to physical design, explain each input in detail
4) setup check,hold check, uncertainty,skew, latency
5) how to fix setup and hold violations, explain them in detail
6) what are the methods to reduce skew and latency
7) antenna effect and how to reduce it
8) difference between global routing and detailed routing
9) commands of floorplanning, placement,CTS, routing
10) commands to fix congestion
11) about TCL commands in detail
12) sanity checks at each and every stage
13) which sanity we redo at placement stage
14) soft ,hard, partial blockages
15) soft,hard macros in detail
16) lvs,upf,drc rules
17) synthesis part explain in detail
18) lec, explain about physical cells
19) cell padding means
20) pearl scripting
DIGICOMM

1) Self-introduction
2) can you explain PD flow
3) how fix step and hold violations explain
4) explain routing congestion
5) how to increase in routing pin density, cell density congestion
6) explain DRC
7) explain sing off

1) CMOS operating mode

2) project
3) M.tech project
4) difference between sequential & combinationl ckt
5) counters
6) verilog
7) PD flow
8) CTS
9) channel length modulation
10) body effect

LEAD SOC
1) Self-introduction
2) explain PD
3) explain Floorplan
4) drc
5) lvs error explain short error command

EXCEL VLSI

1) Self introduction
2) Overall what you learned in your course
3) What is course duration
4) Pd flow
5) Fixing steps for congestion
6) Setup and hold ,in detail
7) Setup and hold voilations fixes
 8) Tool commands used
9) Unix commands-asked commands about,how to open a file
10) Lvt,hvt,,derive setup and time with eqution and waveform,slew,latency,what is
upsizing cell and down sizing cell
11) Draw the diagram of floor plan

APPOSE ENGINEERING

1) Tell me about yourself

2) Project details
3) Staup time and hold time slk and violation
4) Cmos inverter
5) Ocv
6) PD inputs
7) PD flow
8) Sanity checks
9) Skew
10) Positive and negative skew
11) Congestion
12) What are the physical cells
13) Explain in detail Placement
14) How to place in clocks in cts

KEENS HEAD
1) definitiin on flip flop and latches
2) what is CTS
3) logic gates truth table
4) cmos implementation
5) what is CTS and why we do that
6) if we won't do CTS what will happen

1) difference between flop and latch

2) about project
3) copy & remove command
4) latch issue
5) CMOS operating
6) M.tech project
7) pd input
8) type of cells
 1) Self-introduction
2) asic design flow
3) explain .Lib present in information
4) how do you deside the Floorplan with and height
5) can you tell about the cts
6) what is skew
7) can you write truth table for AND gate and exor gate
8) flip flops explain
9) can you tell me mux 2*1
10) AND GATE 2*1 mux convert
11) what is DRC
12) what are the setps in the routing

APPEX SEMICONDUCTOR

1) what is clock skew

2) what is derate
3) what is clock tree synthesis
4) in which path we insert buffer

CHIPVIDIA
1) What is congestion
2) How to resolve congestion
3) Setup n hold formula
4) About Floorplan
5) Inputs for Pd
6) About.lef file

1) Explain about inputs to pd flow

2) What are the contents of check_design
3) Check_library
4) Check_timing
5) Explain about floor planning
6) Guidelines of floorplanning
7) Command for number of pins
8) What we do after floorplanning,what are commands for power planning
9) Command for upsizing cell in setup fix
10) Setup voilations fixes
11) Hold voilations fixes
12) Equation of channel length
13) Command to fix the macros
14) What is the congestion
15) How do we know there is a congestion
16) What is the command for congestion
17) What is cell density and pin density,how do we know there is cell density and pin
density
18) If congestion occur what you will do and what are the commands used
19) How CTS is done
20) What is skew, latency, uncertainty
21) What are the equations for setup and hold check

1) Tell me about yourself

2) Inputs of pd
3) Contents of technology file ,.lib
4) explain floor plan
5) What are sanity checks
6) What do we check in check_design, check_timing,check_library
7) Floorplan guidelines
8) How do you provide space between macros
9) Command to get the spacing
10) How do you get channel length (equation)
11) What do we do after placing macros
12) What are physical cells placed
13) Why do we use well tap cells and end cap cells
14) What do we do in placement
15) What is the command to place STD cells
16) what are checks u do after placement
17) what is congestion , how do you check congestion (command )
18) ways to reduce congestion
19) What are other issues in placement
20) What do we do in power plan , how do you do powerplan.
21) setup equation
22) What is skew ,types of skew how it affects setup and hold
23) what do we do in CTS

1) Tell me about your self

2) Congestion
3) Types of congestion
4) How to avoid congestion
5) What command you give when congestion happen, how can you identify
6) What command you give a at cts
7) Sanity check
8) How to fix congestion
9) Setup fix
10) What method you use to fix the skew
 11) Check design
12) Check_ timing
13) Floor plan process
14) Macros placement
15) Sign off checks
16) What we do in placement
17) Simple problems on spacing between the macros
18) Types of skews
19) Placement types
20) Setup equation
21) How does skew effects the set up and hold violation
22) Is this Skew it happen in before cts also?

1) IR drop fixes
2) DRV? What Analysis have u done in the design
3) Max cap Max Tran Max fan out have u faced?
4) Commands to solve congestion
5) Routing tracks
6) Power planning
7) Rt equation
8) At equation
9) What to do if the cells are illegal?
10) Group paths command
11) diff between halos and blockages
12) CTS? What checks do u do in CTS?
13) How do u take decisions uf u have violation in placement stage?
14) Sanity checks and commands explain commands
15) Pd input files ellobaorate all files
16) Types of LEF files
17) Physical only cells and usage
18) Timing report
19) Macros placement guidelines
20) Setup and hold fixes

1) Self introduction
2) Congestion and ways to resolve it
3) Setup n hold in depth
4) floorplan macros and std cells
5) Inputs for Pd
6) lef classification
7) Project
8) Mtech project

TRUE CHIP
1) Introduction
2) About academic projects
3) Difference between combinational and sequential circuits.
4) What are basic cells of combinational circuits
5) Design and gate and exit gate from mux using one mux.
6) What happens if we add inverter in series with nand and nor gates.
7) What are universal gates?
8) Can we call mux as universal cells
9) What is meant by coincidental cells, what is it give reason?

1) Introduction
2) What do you learn in your training
3) About PD flow
4) What happens in each stage of PD flow

1) self-introduction
2) Complete pd flow
3) What is Electromigration
4) Insertion delay
5) What is ocv and why it is considered
6) Setup slack violation
7) DFM
8) About routing

1) Introduction
2) Pd flow
3) Insertion delay
4) Difference between full adder and half adder
5) about sta
6) seup and hold time
7) setup and hold slack problems
8) ring and johnson counter
9) cell delay
10) implement mux using gates

1) 1 Self introduction
2) PD flow
3) What Tool used in project and titel of project
4) Inputs fro floor planning
5) About Routing
6) Lvs and Dfm
7) Setup and hold time
8) About Macros
9) What is launch and capture time
10) Insertion delay

1) Introduction
2) About project done in btech and training institute project
3) Macro placement and guidelines for placement
4) Combination and sequential ckts
5) About floorplanning and inputs for floorplanning
6) About upf

1) Self intro
2) what r soft macro hard macro
3) about your projects
4) what is set up & hold time
5) explain placement & CTS
6) what is congestion & how to fix it
7) what r level shifters
8) upf file

1) Self introduction
2) registers and latch difference
3) pd flow
4) What is the input and output for placement
5) Inputs for CTS
6) Draw a full adder and HA and it's difference, and related problems
7) how could be the power consumption in between near registers and in between
longer distance reg
8) Draw a H.A using Mux
9) About STA and setup slk formula
10) Calculate the clk frequency for given circuit
11) Cell delay, latency, propagation delay

1) self Introduction
2) Complete Pd flow
3) inputs to floor planning
4) Floor planning
5) What is Clock Tree Synthesis
6) about STA
7) setup and hold time
8) setup and hold slack problems
9) cell delay depends on
10) Half adder and full adder and problems
11) Mealy and moore machine
12) State machine
13) How do we give power to macros
14) information in TLU File?
15) Why we use full adder instead of using half adders

1) self intro
2) what is ASIC flow?
3) what are the steps involved in synthesis?
4) is the same gate level netlist is used for every technology nodes?
5) what are pd inputs?
6) what will be information mainly specifed in technology file?
7) draw CMOS inverter stick diagram and out of that which metal info is present in
.lef file?
8) what are the inputs to floorplan?
9) How can you say it is better floorplan?
10) when you place the macro in the core area how will you avoid congestion?
11) What are the physical cells and thier uses?
12) What are the steps to avoid congestion?
13) what is the difference between half adder and full adder?
14) problem on HA AND FA.
15) Implement FA using mux
16) implement and gate using mux
17) implement latch using mux
18) What are the inputs to CTS?
19) Difference between clock buffer and normal buffer
20) Problem on setup and hold check. To on which condition circuit may work!!

1) Self Introduction
2) About sta topics
3) About CMOS
4) What are and explain Logical gates
5) Input of pd
6) Complete Pd flow
7) What did you do CTS
8) TCL questions
9) What are check after routing
10) What congestion and fixing congestion
11) What is crosstalk and fixes

1) Questions about sta

2) Setup hold fixes
3) Flipflops
4) Draw rs flip flops
5) Multiplexers
6) And gate using 2x1 multiplexer
7) Both flows
8) MOSFET etc

1) Questions from STA

2) Explain any one combinational circuit
3) ASIC Flow
4) CMOS
5) About the project
6) Various stages in PD
7) Number system conversion question

1) Asic flow
2) Questions from STA
3) Full adder using 4x1 mux
4) CMOS inverter
5) Ring counter
6) Johnson counter
7) About the project
8) Inputs for PD
9) Sanity checks

1) PD flow
2) Inputs for PD
3) Logical questions from placement like difference between keep out margin and
placement blockages
4) Macros placement guidelines
5) What are halo cells
6) Sanity checks
7) Clock exceptions
8) STA questions how the setup and hold violations can be avoided
9) Before placement what we need to do
10) What are the reports generated after placement and what is contains
11) Half adder design
12) Frequency divider
13) One logical question from digital circuits

1) Pd flow
2) Ring counter
3) Meley n Moore
4) Full adder using mux
5) Sta
6) Sanitychk
7) Inputs for cts n floorplan
8) No conversion

1) Pd flow
2) Pd inputs
 3) Macros placement guidelines
4) Sanity checks
5) Checks after floorplan , after placement , after CTS
6) Physical cells
7) Latch up issue and fix
8) Antenna issue and fix
9) Timing exceptions
10) Timing definitions
11) Setup and hold defn
12) Setup and hold fix
13) Setup and hold problem
14) Diff btw latch and flipflop
15) Draw d f/f using logic gates

SMART SOC:
1) Self-introduction
2) define CMOS
3) Why complementary used in mos
4) Define half, full adder
5) Define mux
6) draw 8*1 mux to 2*1 mux
7) Convert decimal into binary (721)
8) Design AND gate using 2*1 mux
9) Difference between latch and filp flop
10) Draw the clock period in 20 ns
11) Define time period

PROXELERA PVT. LTD.

1) Intro
2) Sta problems
3) Cmos nand logic
4) Implement exor gate using nand gates
5) pnr flow
6) Latch up issue
7) Difference between latch and edge
8) pvt conditions
9) What are sanity checks
10) Wt is nm?
11) Synchronous and asynchronous clks? Problem also
12) Technology and tlu+?
13) Difficulty s faced in pnr?
14) If 10 clks are synchronis and 15 are asynchronous what will be the problem?
15) Skew problem?
 16) Master and generated clks?
17) Routing difficulties?
18) Project?
19) Can u draw how metal layers are connected and difficulties?
20) What are the metal layers and how u are connected draw and wt are the difficultys
faced?

1) Where we will use flops and where we will use latches?

2) What are clock tree exceptions?
3) What is the information available in spec file?
4) How you will deal with noise?
5) From where u will get the aggressor net and victim net info?
6) List out the timing models!!!
7) How will the delay values u will get in the .lib file?
8) What is STA
9) What is DTA
10) What is the difference between them?
11) Is half cycle path a timing exceptions?
12) Half cycle is critical to clear setup or hold?
13) Difference between NLDM and CCS
14) Why hold is calculated at 0ns? Difference between latch and flops?
15) What is min pulse width violation?

BIT SILICA

1) Self introduction
2) I/p files to PD
3) Explain each and every input file with the command
4) Diff bet constraints and logical libraries
5) Def file in detail and its use in tool
6) Is tlu+ file used only for pre- layout STA?
7) What does tlu+ file contain
8) What are the cells used in FP?
9) How do you perform powerplanning on tool?
10) Placement
11) How are the standard cells placed in the placement stage?
12) Why are macros placed from the origin?
13) Can the macros be placed elsewhere?
14) Macro guidelines
15) What is channel length spacing?
16) Formula for channel length
17) Problem on channel length(no of pins= 100, pitch=0.5)
18) What is Aspect Ratio? Explain in details
19) How do you fix DRCs on tool?
 20) Evaluation of timing constraints on tool
21) Have you done routing?
22) Boundary cells
23) CTS
24) How did you use CTS on tool?
25) Major goals in CTS
26) Skew
27) Setup and hold violation
28) How did you fixed the violation in your project?

GAAFET SEMICONDUCTOR

1) I/ps to PD flow
2) Pd flow
3) Sanity checks after floorplan
4) Inputs to CTS
5) Sanity checks after routing
6) Challenges faced during placement
7) Powerplanning
8) Macros placement guidelines
9) Why Macros are not placed at the centre?
10) Goals of CTS
11) What is skew and latency?

AMBIT SEMICONDUCTOR PVT. LTD.

1) Self introduction and family background
2) M. Tech project in depth
3) CMOS characteristics
4) Define Threshold voltage
5) what is the operating voltage for Silicon?
6) Difference between STA and DTA
7) What is latchup and how to fix it?
8) What is the function of Filler cells and which stage is it added?
9) Why are filler cells added after routing?
10) What is Antenna Effect?
11) Difference between BJT and FET.
12) Difference between HVT and LVT.
13) Signoff checks
14) What do you do in CONORMAL tool?
15) What is LEC?
16) What is the difference between golden netlist and optimised netlist?
17) How is the golden netlist provided by the RTL team verified?
 1) Self introduction
2) Academic project
3) Based on the project few questions
4) Setup and hold time
5) What is EMI
6) Truth table of xor gate

KRISH SEMICONDUCTOR

1) Self-Introduction
2) About PD course
3) PD flow & explain each stage
4) Overall about PD