M93Cx6-A125

Automotive 16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit

(8-bit or 16-bit wide) MICROWIRE™ serial EEPROM
Datasheet - production data

Features
• Industry standard MICROWIRE™ bus
• Memory array: 1 Kb, 2 Kb, 4 Kb, 8 Kb or 16 Kb
• Dual organization: by word (x16) or byte (x8)
• Write
SO8 (MN)
150 mil width
– Byte within 4 ms
– Word within 4 ms
• READY/BUSY signal during programming
• 2 MHz clock rate
• Sequential read operation
• Single supply voltage: 1.8 V to 5.5 V
TSSOP8 (DW)
169 mil width • Operating temperature range: -40 °C up to
125 °C
• Enhanced ESD protection
• Write cycle endurance
– 4 million Write cycles at 25 °C
– 1.2 million Write cycles at 85 °C
WFDFPN8 (MF)
2 x 3 mm – 600 k Write cycles at 125 °C
• Data retention
– 50 years at 125 °C
– more than 100 years at 25 °C
• Packages
– RoHS-compliant and Halogen-free
(ECOPACK2®)

Table 1. Device summary

Reference Part number

M93C46-A125
M93C56-A125
M93Cx6-A125 M93C66-A125
M93C76-A125
M93C86-A125

January 2015 DocID024752 Rev 5 1/31

This is information on a product in full production. www.st.com
Contents M93Cx6-A125

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Connecting to the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.3 Power-up and device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1 Read Data from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2 Erase and Write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.1 Write Enable and Write Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.2 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.3 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2.4 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 15
5.2.5 Erase Byte or Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2.6 Erase All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 READY/BUSY status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8 Common I/O operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

9 Clock pulse counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

10 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

11 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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M93Cx6-A125 Contents

12 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

13 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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List of tables M93Cx6-A125

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Memory size versus organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Instruction set for the M93Cx6-A125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Instruction set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Instruction set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. Instruction set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 9. Operating conditions (M93Cx6-A125) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Input and output capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 12. Cycling performance by byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 16. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 26
Table 17. WFDFPN8 (MLP8) – 8-lead very thin fine pitch dual flat package no lead
2 x 3 mm, 0.5 mm pitch, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 18. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 19. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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M93Cx6-A125 List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Bus master and memory devices on the serial bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. M93Cx6-A125 ORG input connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. READ, WRITE, WEN, WDS sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. WRAL sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. ERASE, ERAL sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Write sequence with one clock glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. AC testing input output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10. Synchronous timing (Start and op-code input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. Synchronous timing (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Synchronous timing (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. WFDFPN8 (MLP8) – 8-lead very thin fine pitch dual flat package no lead
2 x 3 mm, 0.5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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5
Description M93Cx6-A125

1 Description

The M93C46 (1 Kbit), M93C56 (2 Kbit), M93C66 (4 Kbit), M93C76 (8 Kbit) and M93C86
(16 Kbit) are Electrically Erasable PROgrammable Memory (EEPROM) devices accessed
through the MICROWIRE™ bus protocol. The memory array can be configured either in
bytes (x8b) or in words (x16b).
The M93Cx6-A125 devices operate within a voltage supply range from 1.8 V to 5.5 V
The M93Cx6-A125 devices are guaranteed over the -40 °C/+125 °C temperature range and
are compliant with the Automotive standard AEC-Q100 Grade 1.

Table 2. Memory size versus organization

Device Number of bits Number of 8-bit bytes Number of 16-bit words

M93C86 16384 2048 1024

M93C76 8192 1024 512
M93C66 4096 512 256
M93C56 2048 256 128
M93C46 1024 128 64

Figure 1. Logic diagram

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Table 3. Signal names

Signal name Function Direction

S Chip Select Input

D Serial Data input Input
Q Serial Data output Output
C Serial Clock Input
ORG Organization Select Input
VCC Supply voltage -
VSS Ground -

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M93Cx6-A125 Description

The M93Cx6-A125 is accessed by a set of instructions, as summarized in Table 4, and in

more detail in Table 5: Instruction set for the M93C46 to Table 7: Instruction set for the
M93C76 and M93C86).

Table 4. Instruction set for the M93Cx6-A125

Instruction Description Data

READ Read Data from Memory Byte or Word

WRITE Write Data to Memory Byte or Word
WEN Write Enable -
WDS Write Disable -
ERASE Erase Byte or Word Byte or Word
ERAL Erase All Memory -
WRAL Write All Memory with same Data -

A Read Data from Memory (READ) instruction loads the address of the first byte or word to
be read in an internal address register. The data at this address is then clocked out serially.
The address register is automatically incremented after the data is output and, if Chip Select
Input (S) is held High, the M93Cx6-A125 can output a sequential stream of data bytes or
words. In this way, the memory can be read as a data stream from eight to 16384 bits long
(in the case of the M93C86), or continuously (the address counter automatically rolls over to
00h when the highest address is reached).
Programming is internally self-timed (the external clock signal on Serial Clock (C) may be
stopped or left running after the start of a Write cycle) and does not require an Erase cycle
prior to the Write instruction. The Write instruction writes 8 or 16 bits at a time into one of the
byte or word locations of the M93Cx6-A125. After the start of the programming cycle, a
Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is
driven High. An internal Power-on Data Protection mechanism in the M93Cx6-A125 inhibits
the device when the supply is too low.

Figure 2. 8-pin package connections (top view)

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3   6##
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1. See Section 12: Package mechanical data for package dimensions, and how to identify pin-1.
2. DU = Don’t Use. The DU (do not use) pin does not contribute to the normal operation of the device. It is
reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be
connected to VCC or VSS.

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30
Connecting to the serial bus M93Cx6-A125

2 Connecting to the serial bus

Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus.
Only one device is selected at a time, so only one device drives the Serial Data output (Q)
line at a time, the other devices are high impedance.
The pull-down resistor R (represented in Figure 3) ensures that no device is selected if the
bus master leaves the S line in the high impedance state.
In applications where the bus master may be in a state where all inputs/outputs are high
impedance at the same time (for example, if the bus master is reset during the transmission
of an instruction), the clock line (C) must be connected to an external pull-down resistor so
that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is
pulled low): this ensures that C does not become high at the same time as S goes low, and
so, that the tSLCH requirement is met. The typical value of R is 100 kΩ.

Figure 3. Bus master and memory devices on the serial bus

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M93Cx6-A125 Operating features

3 Operating features

3.1 Supply voltage (VCC)

3.1.1 Operating supply voltage (VCC)

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied. In order to secure a stable
DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor
(usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).

3.1.2 Power-up conditions

When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip
Select (S) line is not allowed to float and should be driven to VSS, it is therefore
recommended to connect the S line to VSS via a suitable pull-down resistor.

3.1.3 Power-up and device reset

In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of VCC), the device does not respond to any
instruction until VCC has reached the power on reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Operating conditions, in
Section 11: DC and AC parameters).
When VCC passes the POR threshold, the device is reset and is in the following state:
• Standby Power mode
• deselected (assuming that there is a pull-down resistor on the S line)

3.1.4 Power-down
At power-down (continuous decrease in VCC), as soon as VCC drops from the normal
operating voltage to below the power on reset threshold voltage, the device stops
responding to any instruction sent to it.
During power-down, the device must be deselected and in the Standby Power mode (that is,
there should be no internal Write cycle in progress).

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30
Memory organization M93Cx6-A125

4 Memory organization

The M93Cx6-A125 memory is organized either as bytes (x8) or as words (x16). If

Organization Select (ORG) is left unconnected (or connected to VCC) the x16 organization is
selected; when Organization Select (ORG) is connected to Ground (VSS) the x8
organization is selected. When the M93Cx6-A125 is in Standby mode, Organization Select
(ORG) should be set either to VSS or VCC to reach the device minimum power consumption
(as any voltage between VSS and VCC applied to ORG input may increase the device
Standby current).

Figure 4. M93Cx6-A125 ORG input connection

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M93Cx6-A125 Instructions

5 Instructions

The instruction set of the M93Cx6-A125 devices contains seven instructions, as

summarized in Table 5 to Table 7. Each instruction consists of the following parts, as shown
in Figure 5: READ, WRITE, WEN, WDS sequences:
• Each instruction is preceded by a rising edge on Chip Select Input (S) with Serial Clock
(C) being held low.
• A start bit, which is the first ‘1’ read on Serial Data Input (D) during the rising edge of
Serial Clock (C).
• Two op-code bits, read on Serial Data Input (D) during the rising edge of Serial Clock
(C). (Some instructions also use the first two bits of the address to define the op-code).
• The address bits of the byte or word that is to be accessed. For the M93C46, the
address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization
(see Table 5). For the M93C56 and M93C66, the address is made up of 8 bits for the
x16 organization or 9 bits for the x8 organization (see Table 6). For the M93C76 and
M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8
organization (see Table 7).
The M93Cx6-A125 devices are fabricated in CMOS technology and are therefore able to
run as slow as 0 Hz (static input signals) or as fast as the maximum ratings specified in “AC
characteristics” tables, in Section 11: DC and AC parameters.

Table 5. Instruction set for the M93C46

x8 origination (ORG = 0) x16 origination (ORG = 1)
Start Op-
Instruction Description Required Required
bit code Address Address
(1) Data clock (1) Data clock
cycles cycles

Read Data from

READ 1 10 A6-A0 Q7-Q0 - A5-A0 Q15-Q0 -
Memory
Write Data to
WRITE 1 01 A6-A0 D7-D0 18 A5-A0 D15-D0 25
Memory
WEN Write Enable 1 00 11X XXXX - 10 11 XXXX - 9
00X
WDS Write Disable 1 00 - 10 00 XXXX - 9
XXXX
Erase Byte or
ERASE 1 11 A6-A0 - 10 A5-A0 - 9
Word
10X
ERAL Erase All Memory 1 00 - 10 10 XXXX - 9
XXXX
Write All Memory 01X
WRAL 1 00 D7-D0 18 01 XXXX D15-D0 25
with same Data XXXX
1. X = Don't Care bit.

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30
Instructions M93Cx6-A125

Table 6. Instruction set for the M93C56 and M93C66

x8 origination (ORG = 0) x16 origination (ORG = 1)
Op-
Start
Instruction Description cod Required Required
bit Address Address
e (1) (2) Data clock (1) (3) Data clock
cycles cycles

Q7- Q15-
READ Read Data from Memory 1 10 A8-A0 - A7-A0 -
Q0 Q0
D7-
WRITE Write Data to Memory 1 01 A8-A0 20 A7-A0 D15-D0 27
D0
1 1XXX 11XX
WEN Write Enable 1 00 - 12 - 11
XXXX XXXX
0 0XXX 00XX
WDS Write Disable 1 00 - 12 - 11
XXXX XXXX
ERASE Erase Byte or Word 1 11 A8-A0 - 12 A7-A0 - 11
1 0XXX 10XX
ERAL Erase All Memory 1 00 - 12 - 11
XXXX XXXX
Write All Memory with 0 1XXX D7- 01XX
WRAL 1 00 20 D15-D0 27
same Data XXXX D0 XXXX
1. X = Don't Care bit.
2. Address bit A8 is not decoded by the M93C56.
3. Address bit A7 is not decoded by the M93C56.

Table 7. Instruction set for the M93C76 and M93C86

x8 Origination (ORG = 0) x16 Origination (ORG = 1)
Start Op-
Instruction Description Required Required
bit code Address Address
(1)(2) Data clock (1) (3) Data clock
cycles cycles

Read Data from

READ 1 10 A10-A0 Q7-Q0 - A9-A0 Q15-Q0 -
Memory
Write Data to
WRITE 1 01 A10-A0 D7-D0 22 A9-A0 D15-D0 29
Memory
11X XXXX 11 XXXX
WEN Write Enable 1 00 - 14 - 13
XXXX XXXX
00X XXXX 00 XXXX
WDS Write Disable 1 00 - 14 - 13
XXXX XXXX
ERASE Erase Byte or Word 1 11 A10-A0 - 14 A9-A0 - 13
10X XXXX 10 XXXX
ERAL Erase All Memory 1 00 - 14 - 13
XXXX XXXX
Write All Memory 01X XXXX 01 XXXX
WRAL 1 00 D7-D0 22 D15-D0 29
with same Data XXXX XXXX
1. X = Don't Care bit.
2. Address bit A10 is not decoded by the M93C76.
3. Address bit A9 is not decoded by the M93C76.

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M93Cx6-A125 Instructions

5.1 Read Data from Memory

The Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q).
When the instruction is received, the op-code and address are decoded, and the data from
the memory is transferred to an output shift register. A dummy 0 bit is output first, followed
by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are
triggered by the rising edge of Serial Clock (C). The M93Cx6-A125 automatically increments
the internal address register and clocks out the next byte (or word) as long as the Chip
Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or
words) and a continuous stream of data can be read (the address counter automatically rolls
over to 00h when the highest address is reached).

5.2 Erase and Write data

5.2.1 Write Enable and Write Disable

The Write Enable (WEN) instruction enables the future execution of erase or write
instructions, and the Write Disable (WDS) instruction disables it. When power is first
applied, the M93Cx6-A125 initializes itself so that erase and write instructions are disabled.
After a Write Enable (WEN) instruction has been executed, erasing and writing remains
enabled until a Write Disable (WDS) instruction is executed, or until VCC falls below the
power-on reset threshold voltage. To protect the memory contents from accidental
corruption, it is advisable to issue the Write Disable (WDS) instruction after every write
cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable
(WEN) or Write Disable (WDS) instructions.

5.2.2 Write
For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and
address bits. These form the byte or word that is to be written. As with the other bits, Serial
Data Input (D) is sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken low before
the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought low before or after
this specific time frame, the self-timed programming cycle will not be started, and the
addressed location will not be programmed. The completion of the cycle can be detected by
monitoring the READY/BUSY line, as described later in this document.
Once the Write cycle has been started, it is internally self-timed (the external clock signal on
Serial Clock (C) may be stopped or left running after the start of a Write cycle). The Write
cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an
explicit erase instruction before a Write Data to Memory (WRITE) instruction.

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30
Instructions M93Cx6-A125

Figure 5. READ, WRITE, WEN, WDS sequences

2EAD 3

$    !N !

1 1N 1

!$$2 $!4! /54

/0
#/$%

7RITE 3

#(%#+
34!453
$    !N ! $N $

!$$2 $!4! ). "539 2%!$9

/0
#/$%

7RITE 3 7RITE 3
%NABLE $ISABLE

$      8N 8 $      8N 8

/0 /0
#/$% #/$%
!)D

1. For the meanings of An, Xn, Qn and Dn, see Table 5, Table 6 and Table 7.

14/31 DocID024752 Rev 5

M93Cx6-A125 Instructions

5.2.3 Write All

As with the Erase All Memory (ERAL) instruction, the format of the Write All Memory with
same Data (WRAL) instruction requires that a dummy address be provided. As with the
Write Data to Memory (WRITE) instruction, the format of the Write All Memory with same
Data (WRAL) instruction requires that an 8-bit data byte, or 16-bit data word, be provided.
This value is written to all the addresses of the memory device. The completion of the cycle
can be detected by monitoring the READY/BUSY line, as described next.

Figure 6. WRAL sequence

72)4% 3
!,,
#(%#+
34!453
$      8N 8 $N $

!$$2 $!4! ). "539 2%!$9

/0
#/$%
!)#

1. For the meanings of Xn and Dn, please see Table 5, Table 6 and Table 7.

5.2.4 ECC (Error Correction Code) and Write cycling

The devices identified with the Process letter “K” embed an Error Correction Code (ECC)
internal logic function which is transparent for the Microwire communication protocol.
The ECC logic is implemented on each byte.

DocID024752 Rev 5 15/31

30
Instructions M93Cx6-A125

5.2.5 Erase Byte or Word

The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or
word) to 1. Once the address has been correctly decoded, the falling edge of the Chip
Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be
detected by monitoring the READY/BUSY line, as described in Section 6: READY/BUSY
status.

Figure 7. ERASE, ERAL sequences

%2!3% 3
#(%#+
34!453
$    !N !

!$$2 "539 2%!$9

/0
#/$%

%2!3% 3
!,,
#(%#+
34!453
$      8N 8

!$$2 "539 2%!$9

/0
#/$%
!)"

1. For the meanings of An and Xn, please see Table 5, Table 6 and Table 7.

5.2.6 Erase All

The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set
to 1). The format of the instruction requires that a dummy address be provided. The Erase
cycle is conducted in the same way as the Erase instruction (ERASE). The completion of
the cycle can be detected by monitoring the READY/BUSY line, as described in Section 6:
READY/BUSY status.

16/31 DocID024752 Rev 5

M93Cx6-A125 READY/BUSY status

6 READY/BUSY status

While the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL
instruction, the Busy signal (Q=0) is returned whenever Chip Select input (S) is driven high.
(Please note, though, that there is an initial delay, of tSLSH, before this status information
becomes available). In this state, the M93Cx6-A125 ignores any data on the bus. When the
Write cycle is completed, and Chip Select Input (S) is driven high, the Ready signal (Q=1)
indicates that the M93Cx6-A125 is ready to receive the next instruction. Serial Data Output
(Q) remains set to 1 until the Chip Select Input (S) is brought low or until a new start bit is
decoded.

7 Initial delivery state

The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).

8 Common I/O operation

Serial Data Output (Q) and Serial Data Input (D) can be connected together, through a
current limiting resistor, to form a common, single-wire data bus. Some precautions must be
taken when operating the memory in this way, mostly to prevent a short circuit current from
flowing when the last address bit (A0) clashes with the first data bit on Serial Data Output
(Q). Please see the application note AN394 for details.

DocID024752 Rev 5 17/31

30
Clock pulse counter M93Cx6-A125

9 Clock pulse counter

In a noisy environment, the number of pulses received on Serial Clock (C) may be greater
than the number delivered by the master (the microcontroller). This can lead to a
misalignment of the instruction of one or more bits (as shown in Figure 8) and may lead to
the writing of erroneous data at an erroneous address.
To avoid this problem, the M93Cx6-A125 has an on-chip counter that counts the clock
pulses from the start bit until the falling edge of the Chip Select Input (S). If the number of
clock pulses received is not the number expected, the WRITE, ERASE, ERAL or WRAL
instruction is aborted, and the contents of the memory are not modified.
The number of clock cycles expected for each instruction, and for each member of the
M93Cx6-A125 family, are summarized in Table 5: Instruction set for the M93C46 to Table 7:
Instruction set for the M93C76 and M93C86. For example, a Write Data to Memory (WRITE)
instruction on the M93C56 (or M93C66) expects 20 clock cycles (for the x8 organization)
from the start bit to the falling edge of Chip Select Input (S). That is:
1 Start bit
+ 2 Op-code bits
+ 9 Address bits
+ 8 Data bits

Figure 8. Write sequence with one clock glitch

!N !N  !N 

34!24   'LITCH $

!$$2%33 !.$ $!4!

72)4% !2% 3()&4%$ "9 /.% ")4
!)

18/31 DocID024752 Rev 5

M93Cx6-A125 Maximum ratings

10 Maximum ratings

Stressing the device outside the ratings listed in the Absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these, or any other conditions outside those indicated in the operating sections of
this specification, is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Table 8. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

Ambient operating temperature –40 130 °C

TSTG Storage temperature –65 150 °C
TLEAD (1)
Lead temperature during soldering See note °C
VOUT Output range (Q = VOH or Hi-Z) –0.50 VCC+0.5 V
VIN Input range –0.50 VCC+1 V
VCC Supply voltage –0.50 6.5 V
VESD Electrostatic discharge voltage (human body model)(2) - 4000 V
1. Compliant with JEDEC standard J-STD-020D (for small-body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS
directive 2011/65/EU of July 2011).
2. Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant with
ANSI/ESDA/JEDEC JS-001-2012), C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).

DocID024752 Rev 5 19/31

30
DC and AC parameters M93Cx6-A125

11 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device.

Table 9. Operating conditions (M93Cx6-A125)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 1.8 5.5 V

TA Ambient operating temperature –40 125 °C

Table 10. AC measurement conditions

Symbol Parameter Min. Max. Unit

CL Load capacitance 100 pF

- Input rise and fall times - 50 ns
- Input voltage levels 0.2 VCC to 0.8 VCC V
- Input timing reference voltages 0.3 VCC to 0.7 VCC V
- Output timing reference voltages 0.3 VCC to 0.7 VCC V

Figure 9. AC testing input output waveforms

-#88
9&&
9&&
)NPUT AND OUTPUT
)NPUT VOLTAGE LEVELS
TIMING REFERENCE LEVELS
9&&
9&&

-36

Table 11. Input and output capacitance

Symbol Parameter Test condition(1) Min Max Unit

COUT Output capacitance VOUT = 0V - 8 pF

CIN Input capacitance VIN = 0V - 6 pF
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 1 MHz.

Table 12. Cycling performance by byte

Symbol Parameter Test condition Min. Max. Unit

TA ≤ 25 °C, 1.8 V < VCC < 5.5 V - 4,000,000

Write cycle Write
Ncycle TA = 85 °C, 1.8 V < VCC < 5.5 V - 1,200,000
endurance cycle(1)
TA = 125 °C, 1.8 V < VCC < 5.5 V - 600,000
1. A Write cycle is executed when either a Write, a Write All, an Erase or an Erase All instruction is decoded.

20/31 DocID024752 Rev 5

M93Cx6-A125 DC and AC parameters

Table 13. DC characteristics

Test conditions
Symbol Parameter (in addition to conditions specified Min. Max. Unit
in Table 9)

ILI Input leakage current VIN = VSS or VCC - 2

µA
ILO Output leakage current S = VCC, VOUT = VSS or VCC - 2
VCC = 1.8 V, C = 0.1 VCC/0.9 VCC,
- 1
Q = open, fC = 2 MHz
VCC = 2.5 V, C = 0.1 VCC/0.9 VCC,
ICC Supply current (Read) - 1 mA
Q = open, fC = 2 MHz
VCC = 5.5 V, fC = 2 MHz
- 1.5
C = 0.1 VCC/0.9 VCC, Q = open
1.8 V ≤ VCC < 5.5 V during tW,
ICC0(1) Supply current (Write) - 1.5 mA
S = VCC
t° = 85 °C, VCC = 1.8 V,
- 1
S = VCC, VIN = VSS or VCC
t° = 85 °C, VCC = 2.5 V,
- 2
S = VCC, VIN = VSS or VCC
t° = 85 °C, VCC = 5.5 V,
- 3
S = VCC, VIN = VSS or VCC
ICC1 Supply current (Standby mode) µA
t° = 125 °C, VCC = 1.8 V,
- 15
S = VCC, VIN = VSS or VCC
t° = 125 °C, VCC = 2.5 V,
- 15
S = VCC, VIN = VSS or VCC
t° = 125 °C, VCC = 5.5 V,
- 15
S = VCC, VIN = VSS or VCC
1.8 V ≤ VCC < 2.5 V –0.45 0.25 VCC
VIL Input low voltage (D, C, S) V
2.5 V ≤ VCC < 5.5 V –0.45 0.3 VCC
1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC+1
VIH Input high voltage (D, C, S) V
2.5 V ≤ VCC < 5.5 V 0.7 VCC VCC+1
VCC = 1.8 V, IOL = 1 mA - 0.3
VOL Output low voltage V
VCC ≥ 2.5 V, IOL = 2.1 mA - 0.4
VCC = 1.8 V, IOH = 1 mA 0.8 VCC -
VOH Output high voltage V
VCC ≥ 2.5 V, IOH = -2.1 mA 0.8 VCC -
VRES Internal reset threshold voltage - 0.5 1.5 V
1. Average value during the Write cycle (tW)

DocID024752 Rev 5 21/31

30
DC and AC parameters M93Cx6-A125

Table 14. AC characteristics

Test conditions specified in Table 9 and Table 10

Symbol Alt. Parameter Min. Max. Unit

fC fSK Clock frequency D.C. 2 MHz

tSLCH Chip Select low to Clock high 50 - ns
tSHCH tCSS Chip Select set-up time 50 - ns
tSLSH(1) tCS Chip Select low to Chip Select high 200 - ns
(2)
tCHCL tSKH Clock high time 200 - ns
(2)
tCLCH tSKL Clock low time 200 - ns
tDVCH tDIS Data in set-up time 50 - ns
tCHDX tDIH Data in hold time 50 - ns
tCLSH tSKS Clock set-up time (relative to S) 50 - ns
tCLSL tCSH Chip Select hold time 0 - ns
tSHQV tSV Chip Select to READY/BUSY status - 200 ns
Chip Select low to output Hi-Z (VCC>2.5 V) - 100 ns
tSLQZ(3) tDF
Chip Select low to output Hi-Z (VCC<2.5 V) - 200 ns
tCHQL tPD0 Delay to output low - 200 ns
tCHQV tPD1 Delay to output valid - 200 ns
tW tWP Erase or Write cycle time - 4 ms
1. Chip Select Input (S) must be brought low for a minimum of tSLSH between consecutive instruction cycles.
2. tCHCL + tCLCH ≥ 1 / fC.
3. Value defined from characterization, not tested in production.

22/31 DocID024752 Rev 5

M93Cx6-A125 DC and AC parameters

Figure 10. Synchronous timing (Start and op-code input)

W&/6+ W&+&/

W6+&+ W&/&+

W'9&+ W&+';

$ 67$57 23&2'( 23&2'(

67$57 23&2'(,1387
AI

Figure 11. Synchronous timing (Read)

&

W&/6/

W'9&+ W&+'; W&+49 W6/6+

' $Q $

W&+4/ W6/4=
+L=
4 44 4

$''5(66,1387 '$7$287387

$,&

Figure 12. Synchronous timing (Write)

W6/&+

W&/6/

W'9&+ W&+'; W6/6+

$ $Q $'

W6+49 W6/4=
+L=
1 %86< 5($'<

W:

$''5(66'$7$,1387 :5,7(&<&/(
AI

DocID024752 Rev 5 23/31

30
Package mechanical data M93Cx6-A125

12 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

24/31 DocID024752 Rev 5

M93Cx6-A125 Package mechanical data

Figure 13. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package outline

K[Û

$ $
F
FFF
E
H

PP
' *$8*(3/$1(

N


( (
 /
$
/
62$B9

1. Drawing is not to scale.

Table 15. SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package data
millimeters inches(1)
Symbol
Typ Min Max Typ Min Max

A - - 1.75 - - 0.0689
A1 - 0.1 0.25 - 0.0039 0.0098
A2 - 1.25 - - 0.0492 -
b - 0.28 0.48 - 0.011 0.0189
c - 0.17 0.23 - 0.0067 0.0091
ccc - - 0.1 - - 0.0039
D 4.9 4.8 5 0.1929 0.189 0.1969
E 6 5.8 6.2 0.2362 0.2283 0.2441
E1 3.9 3.8 4 0.1535 0.1496 0.1575
e 1.27 - - 0.05 - -
h - 0.25 0.5 - 0.0098 0.0197
k - 0° 8° - 0° 8°
L - 0.4 1.27 - 0.0157 0.05
L1 1.04 - - 0.0409 - -
1. Values in inches are converted from mm and rounded to 4 decimal digits.

DocID024752 Rev 5 25/31

30
Package mechanical data M93Cx6-A125

Figure 14. TSSOP8 – 8 lead thin shrink small outline, package outline


ϴ ϱ
Đ

ϭ 

ϭ ϰ

ϭ >
 Ϯ
W >ϭ

ď Ğ
76623$0B9

1. Drawing is not to scale.

Table 16. TSSOP8 – 8-lead thin shrink small outline, package mechanical data
millimeters inches(1)
Symbol
Typ Min Max Typ Min Max

A - - 1.200 - - 0.0472
A1 - 0.050 0.150 - 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b - 0.190 0.300 - 0.0075 0.0118
c - 0.090 0.200 - 0.0035 0.0079
CP - - 0.100 - - 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 - - 0.0256 - -
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 - - 0.0394 - -
α - 0° 8° - 0° 8°
N 8 8
1. Values in inches are converted from mm and rounded to four decimal digits.

26/31 DocID024752 Rev 5

M93Cx6-A125 Package mechanical data

Figure 15. WFDFPN8 (MLP8) – 8-lead very thin fine pitch dual flat package no lead
2 x 3 mm, 0.5 mm, package outline
'
'
'DWXP<
$ % H
'
3LQ,'PDUNLQJ
3LQ

( (
(
6HH=
'HWDLO

[ DDD # .

1;E EEE - & $ %

[ DDD # 1' [H GGG - &
7RSYLHZ %RWWRPYLHZ

'DWXP<
 FFF #
&
HHH # $
6HDWLQJSODQH $
/ /

H
/ 6LGHYLHZ
H 7HUPLQDOWLS

'HWDLO³=´ $<B0(B9

1. Drawing is not to scale.

2. The central pad (the area E2 by D2 in the above illustration) must be either connected to Vss or left floating
(not connected) in the end application.

DocID024752 Rev 5 27/31

30
Package mechanical data M93Cx6-A125

Table 17. WFDFPN8 (MLP8) – 8-lead very thin fine pitch dual flat package no lead
2 x 3 mm, 0.5 mm pitch, mechanical data
millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.

A 0.700 0.750 0.800 0.0276 0.0295 0.0315

A1 0.025 0.045 0.065 0.0010 0.0018 0.0026
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
D 1.900 2.000 2.100 0.0748 0.0787 0.0827
E 2.900 3.000 3.100 0.1142 0.1181 0.1220
e - 0.500 - - 0.0197 -
L1 - - 0.150 - - 0.0059
L3 0.300 - - 0.0118 - -
D2 1.050 - 1.650 0.0413 - 0.0650
E2 1.050 - 1.450 0.0413 - 0.0571
K 0.400 - - 0.0157 - -
L 0.300 - 0.500 0.0118 - 0.0197
(2)
NX 8
(3)
ND 4
aaa 0.150 0.0059
bbb 0.100 0.0039
ccc 0.100 0.0039
ddd 0.050 0.0020
eee(4) 0.080 0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. NX is the number of terminals.
3. ND is the number of terminals on “D” sides.
4. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from mea-
suring.

28/31 DocID024752 Rev 5

M93Cx6-A125 Part numbering

13 Part numbering

Table 18. Ordering information scheme

Example: M93C 86 R MN 3 T P /K

Device type

M93 = MICROWIRE serial EEPROM

Device function

86 = 16 Kbit (2048 x 8)

76 = 8 Kbit (1024 x 8)

66 = 4 Kbit (512 x 8)

56 = 2 Kbit (256 x 8)

46 = 1 Kbit (128 x 8)
Operating voltage

R = VCC = 1.8 to 5.5 V

Package(1)

MN = SO8 (150 mils width)

DW = TSSOP8 (169 mils width)

MF = WFDFPN8 (2 x 3 mm)

Device grade

3 = Device tested with high reliability certified flow(2)

Automotive temperature range (–40 to 125 °C)

Packing

T = tape and reel packing

blank = tube packing

Plating technology

P or G = ECOPACK2®

Process

/K = Manufacturing technology code

1. All packages are ECOPACK2® (RoHS compliant and free of brominated, chlorinated and antimony-oxide
flame retardants).
2. The high reliability certified flow (HRCF) is described in quality note QNEE9801. Please ask your nearest
ST sales office for a copy.

Engineering samples
Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are
not yet qualified and therefore not yet ready to be used in production and any consequences
deriving from such usage will not be at ST charge. In no event, ST will be liable for any
customer usage of these engineering samples in production. ST Quality has to be contacted
prior to any decision to use these Engineering samples to run qualification activity.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.

DocID024752 Rev 5 29/31

30
Revision history M93Cx6-A125

14 Revision history

Table 19. Document revision history

Date Revision Changes

07-Aug-2013 1 Initial release

Document status changed from “Preliminary data” to “Production
data”.
Updated:
– Features: “data retention” bullet
– Table 9: Operating conditions (M93Cx6-A125)
– “TSLQZ” row in Table 14: AC characteristics
02-Dec-2013 2
– Note (1) under Table 8: Absolute maximum ratings
– Table 13: DC characteristics
– Figure 15: WFDFPN8 (MLP8) – 8-lead very thin fine pitch dual flat
package no lead 2 x 3 mm, 0.5 mm, package outline.
Renamed Figure 11: Synchronous timing (Read) and Figure 12:
Synchronous timing (Write).
Delete sentence: “The VCC rise time must not vary faster than 1
13-Aug-2014 3 V/μs.” inside Section 3.1.2
Updated packing inside Chapter Table 18.
Updated ECOPACK® to ECOPACK2®
Updated VIH value inside Table 13: DC characteristics.
02-Sept-2014 4
Added note 2. in Figure 15.
Updated Table 18: Ordering information scheme
Updated note 2. in Table 8: Absolute maximum ratings
Updated Figure 15: WFDFPN8 (MLP8) – 8-lead very thin fine pitch
dual flat package no lead 2 x 3 mm, 0.5 mm, package outline
16-Jan-2015 5
Updated Table 17: WFDFPN8 (MLP8) – 8-lead very thin fine pitch
dual flat package no lead 2 x 3 mm, 0.5 mm pitch, mechanical data
Added paragraph: Engineering samples on page 29

30/31 DocID024752 Rev 5

M93Cx6-A125

IMPORTANT NOTICE – PLEASE READ CAREFULLY

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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2015 STMicroelectronics – All rights reserved

DocID024752 Rev 5 31/31

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