CONTENTS

S.No DATE EXPERIMENT NAME PAGE No. GRADE SIGNATURE

1. 29/01/2024 Various logic gates in verilog 2-7

using structural & data-flow
modelling
2. 29/01/2024 Half adder & full adder in verilog 8 - 11
using structural & data flow
modelling
3. 05/02/2024 Binary 4-bit parallel adder 12 - 14
4. 12/02/2024 Half subtractor & full subtractor 15 – 18
in verilog using structural & data
flow modelling
5. 05/02/2024 Binary multiplier in verilog using 19 - 20
structural & data flow modelling
6. 11/03/2024 Multiplexer (2:1, 4:1, 8:1) 21 – 25
7. 11/03/2024 Demultiplexer(1:2, 1:4, 1:8) 26 – 30
8. 11/03/2024 Comparator 31 – 32
9. 18/03/2024 Encoder (2:1, 4:2, 8:3) 33 – 35
10. 18/03/2024 Decoder (1:2, 2:4, 3:8) 36 – 39
11. 18/03/2024 Priority encoder 40 – 43
12. 18/03/2024 BCD to 7 segment display 44 – 46
13. 25/03/2024 Latches & flip flops 47 - 54
14. 25/03/2024 Shift registers 55 – 61
15. 08/04/2024 Counters 62 – 66
16. 08/04/2024 PRBS generator 67 - 68

1|Page
 LAB 1
VARIOUS LOGIC GATES IN VERILOG USING
STRUCTURAL & DATA-FLOW MODELLING
AIM :
Basic logic gates are fundamental building blocks of digital circuits that perform basic logical operations. Now
develop all the gates in the Xilinx Vivado using structural and dataflow models.

SOFTWARE USED :
XILINX VIVADO

1. AND Gate:
THEORY:
- Outputs a high (logic 1) signal only when all its inputs are high.

TRUTH TABLE:

A B Y
0 0 0
0 1 0
1 0 0
1 1 1

DATAFLOW MODELLING : SCHEMATIC :

module and_1(
input a,
input b,
output x
);
assign x = a&b;
endmodule

TEST BENCH : OUTPUT :

module and_tb();
wire x;
reg a,b;
and_1 and_3(.a(a), .b(b), .x(x));
initial
begin
a=1'b0; b=1'b0;
#5 a=1'b1; b=1'b0;
#5 a=1'b0; b=1'b1;
#5 a=1'b1; b=1'b1;
end
endmodule

2|Page
2. OR Gate:
THEORY:
- Outputs a high (logic 1) signal when any of its inputs are high.

TRUTH TABLE:

A B Y
0 0 0
0 1 1
1 0 1
1 1 1

DATAFLOW MODELLING : SCHEMATIC :

module or_1(
input a,
input b,
output x
);
assign x = a|b;
endmodule

TEST BENCH : OUTPUT :

module or_tb();
wire x;
reg a,b;
or_1 or_3(.a(a), .b(b), .x(x));
initial
begin
a=1'b0; b=1'b0;
#5 a=1'b1; b=1'b0;
#5 a=1'b0; b=1'b1;
#5 a=1'b1; b=1'b1;
end
endmodule

3. NOT Gate (INVERTER):

THEORY:
-Outputs the opposite of its input signal.

TRUTH TABLE:

A Y
0 1
0 0

3|Page
DATAFLOW MODELLING : SCHEMATIC :
module not_1(
input a,
output x
);
assign x = ~a;
endmodule

TEST BENCH : OUTPUT :

module not_tb();
wire x;
reg a;
not_1 not_3(.a(a), .x(x));
initial
begin
a=1'b0;
#5 a=1'b1;
end
endmodule

4. XOR Gate:
THEORY:
- Outputs a high (logic 1) signal when the number of high inputs is odd.

TRUTH TABLE:

A B Y
0 0 0
0 1 1
1 0 1
1 1 0

DATAFLOW MODELLING : SCHEMATIC :

module xor_1(
input a,
input b,
output x
);
assign x = a^b;
endmodule

TEST BENCH : OUTPUT :

module xor_tb();
wire x,c;
reg a,b;
xor_1 xor_3(.a(a), .b(b), .x(x));
initial
begin
a=1'b0; b=1'b0;
#5 a=1'b1; b=1'b0;
#5 a=1'b0; b=1'b1;

4|Page
 #5 a=1'b1; b=1'b1;
end
endmodule

5. X-NOR Gate:
THEORY:
- the output is high (1) when both inputs are equal (either both 0s or both 1s), and low (0) when the inputs are
different (0 and 1, or 1 and 0).

TRUTH TABLE:

A B Y
0 0 1
0 1 0
1 0 0
1 1 1

DATAFLOW MODELLING : SCHEMATIC :

module xnor_1(
input a,
input b,
output x
);
assign x = (~(a^b));
endmodule

STRUCTURAL MODELLING :
module xnor_2(
input a,
input b,
output x
);
wire z;
xor_1 y1(a,b,z);
not_1 y2(z,x);
endmodule

TEST BENCH : OUTPUT :

module xnor_tb();
wire x;
reg a,b;
xnor_1 xnor_3(.a(a), .b(b), .x(x));
initial
begin
a=1'b0; b=1'b0;
#5 a=1'b1; b=1'b0;
#5 a=1'b0; b=1'b1;
#5 a=1'b1; b=1'b1;
end
endmodule

5|Page
6. NAND Gate:
THEORY:
- Outputs a low (logic 0) signal only when all its inputs are high.

TRUTH TABLE:

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

DATAFLOW MODELLING : SCHEMATIC :

module nand_1(
input a,
input b,
output c
);
assign c = (~(a&b));
endmodule

STRUCTURAL MODELLING :
module nand_2(
input a,
input b,
output c
);
wire z;
and_1 y1(a,b,z);
not_1 y2(z,c);
endmodule

TEST BENCH : OUTPUT :

module nand_tb();
wire c;
reg a,b;
nand_1 nand_3(.a(a), .b(b), .c(c));
initial
begin
a=1'b0; b=1'b0;
#5 a=1'b1; b=1'b0;
#5 a=1'b0; b=1'b1;
#5 a=1'b1; b=1'b1;
end
endmodule

6|Page
7. NOR Gate:
THEORY:
- Outputs a low (logic 0) signal when any of its inputs are high.

TRUTH TABLE:

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

DATAFLOW MODELLING : SCHEMATIC :

module nor_1(
input a,
input b,
output c
);
assign c = (~(a|b));
endmodule

STRUCTURAL MODELLING :
module nand_2(
input a,
input b,
output c
);
wire z;
or_1 y1(a,b,z);
not_1 y2(z,c);
endmodule

TEST BENCH : OUTPUT :

module nor_tb();
wire c;
reg a,b;
nor_1 nor_3(.a(a), .b(b), .c(c));
initial
begin
a=1'b0; b=1'b0;
#5 a=1'b1; b=1'b0;
#5 a=1'b0; b=1'b1;
#5 a=1'b1; b=1'b1;
end
endmodule

CONCLUSION :
All the basic gates have been successfully verified and compiled on the Xilinx verilog

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

7|Page
 LAB 2
HALF ADDER & FULL ADDER IN VERILOG USING
STRUCTURAL & DATA FLOW MODELLING
AIM :
Developing a half adder & full adder in Xilinx Vivado using structural model, data flow model and test bench
and plot the output and schematic corresponding to it.

SOFTWARE USED :
XILINX VIVADO

1. HALF ADDER:
THEORY:
-A half adder is a basic digital circuit designed to add two single binary digits. It consists of two inputs,
representing the bits to be added, and two outputs: the sum (S) and the carry (C). The sum output is the result of
an XOR operation on the inputs, while the carry output is the result of an AND operation. This simple circuit
forms the foundation of more complex arithmetic circuits and is essential in digital systems and processors for
performing binary addition operations.

TRUTH TABLE:

A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 1 1

DATAFLOW MODELLING : SCHEMATIC :

module dataflow_ha(
input a,
input b,
output c,
output d
);
assign c = a^b;
assign d = a&b;
endmodule

STRUCTURAL MODELLING :
module ha_2(
input a,
input b,
output c,
output d
);
exor_ha(a,b,c);
and_ha(a,b,d);
endmodule
//EX-OR GATE

8|Page
module exor_ha(
input a,
input b,
output x
);
assign x = a^b;
endmodule
//AND GATE
module and_ha(
input a,
input b,
output y
);
assign y = a&b;
endmodule

TEST BENCH : OUTPUT :

module ha_tb();
wire c,d;
reg a,b;
ha_1 ha_3(.a(a), .b(b), .c(c), .d(d));
initial
begin
a=1'b0; b=1'b0;
#5 a=1'b1; b=1'b0;
#5 a=1'b0; b=1'b1;
#5 a=1'b1; b=1'b1;
end
endmodule

1. FULL ADDER:
THEORY:
-A full adder is a key digital circuit used for adding three binary digits: two inputs (A and B) representing the
bits to be added, and a carry input (Cin) representing any carry from a previous addition. It produces two
outputs: the sum (S) and a carry (Cout) representing any carry generated from the addition. The sum output is
the result of an XOR operation on the inputs and the carry input, while the carry output is determined through a
combination of AND and OR operations. Full adders are essential components in complex arithmetic circuits
and are integral to digital systems and processors for performing multi-bit binary addition operations.

TRUTH TABLE:

A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

9|Page
DATAFLOW MODELLING :
module fa_1(
input a,
input b,
input cin,
output s,
output cout
);
assign s = a^b^cin;
assign cout = (a&b)|(b&cin)|(cin&a);
endmodule

STRUCTURAL MODELLING :
module fa_3(
input a,
input b,
input cin,
output s,
output cout
);
wire x1,x2,x3;
fa_ha1 y1(a,b,x1,x2);
fa_ha1 y2(x1,cin,s,x3);
fa_or y3(x3,x2,cout);
endmodule
//HALF ADDER
module fa_ha1(
input s,
input r,
input en,
output q,
output q0
);
wire x,y;
assign x = ~((s)&(en));
assign y = ~((r)&(en));
assign q = ~((x)&(q0));
assign q0 = ~((y)&(q));
endmodule
// OR GATE
module fa_or(
input a,
input b,
output z
);
assign z = a|b;
endmodule

10 | P a g e
TEST BENCH :
module fa_tb();
wire s,cout;
reg a,b,cin;
fa_1 fa_2(.a(a),.b(b),.cin(cin),.s(s),.cout(cout));
initial
begin
a=1'b0;b=1'b0;cin=1'b0;
#5 a=1'b0;b=1'b0;cin=1'b1;
#5 a=1'b0;b=1'b1;cin=1'b0;
#5 a=1'b0;b=1'b1;cin=1'b1;
#5 a=1'b1;b=1'b0;cin=1'b0;
#5 a=1'b1;b=1'b0;cin=1'b1;
#5 a=1'b1;b=1'b1;cin=1'b0;
#5 a=1'b1;b=1'b1;cin=1'b1;
end
endmodule

SCHEMATIC :

OUTPUT :

CONCLUSION :
All half adder & full adder in verilog using structural & data flow modelling have been successfully
implemented and executed in Xilinx Verilog.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

11 | P a g e
 LAB 3
BINARY 4 BIT PARALLEL ADDER

AIM :
Developing a 4-bit binary parallel adder in Xilinx Vivado using structural model and test bench and plot the
output and schematic corresponding to it.

SOFTWARE USED :
XILINX VIVADO

1. 4 BIT ADDER:
THEORY :
A 4-bit binary parallel adder is a digital circuit that adds two 4-bit binary numbers simultaneously, generating a
4-bit sum and a carry-out bit. It operates by adding corresponding bits from the input numbers along with any
carry from the previous addition, making it a fundamental component in digital systems for arithmetic
operations.

Example :

1 0 1 1 (A)
+ 1 1 0 1 (B)
---------
Carry (1) - 1 0 0 0 (Sum)

STRUCTURAL MODEL :
module bfpa_1(
output [3:0]sum,
output cout ,
input [3:0]a,b);

wire c1,c2,c3,c4;

full_3 ad0( .a(a[0]), .b(b[0]),.cin(0), .s(sum[0]), .cout(c1));

full_3 ad1( .a(a[1]), .b(b[1]),.cin(c1), .s(sum[1]), .cout(c2));
full_3 ad2( .a(a[2]), .b(b[2]),.cin(c2), .s(sum[2]), .cout(c3));
full_3 ad3( .a(a[3]), .b(b[3]),.cin(c3), .s(sum[3]), .cout(c4));
assign cout= c4;
endmodule

module full_3(a,b,cin,s,cout);
input a,b,cin;
output s, cout;
assign s=a^b^cin;
assign cout = (a&b) | (b&cin) | (cin&a);
endmodule

12 | P a g e
SCHEMATIC :

TEST BENCH :
module bfpa_tb();

reg [3:0] a = 4'b0000;

reg [3:0] b = 4'b0000;
reg cin = 1'b0;

wire [3:0] sum;

wire cout;

bfpa_1 bfpa_2(
.a(a),
.b(b),
.sum(sum),
.cout(cout)
);

initial
begin
a = 4'b0000; b = 4'b0000; #5;
a = 4'b0001; b = 4'b0001; #5;
a = 4'b0010; b = 4'b0010; #5;
a = 4'b0011; b = 4'b0011; #5;
a = 4'b0100; b = 4'b0100; #5;
a = 4'b0101; b = 4'b0101; #5;
a = 4'b0110; b = 4'b0110; #5;
a = 4'b0111; b = 4'b0111; #5;
a = 4'b1000; b = 4'b1000; #5;
a = 4'b1001; b = 4'b1001; #5;
a = 4'b1010; b = 4'b1010; #5;
a = 4'b1011; b = 4'b1011; #5;
a = 4'b1100; b = 4'b1100; #5;

13 | P a g e
 a = 4'b1101; b = 4'b1101; #5;
a = 4'b1110; b = 4'b1110; #5;
a = 4'b1111; b = 4'b1111; #5;
end
endmodule

OUTPUT :

CONCLUSION :
We have successfully completed the 4-bit binary full adder using Verilog structural and dataflow modeling in
Xilinx Verilog, demonstrating effective implementation and execution.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

14 | P a g e
 LAB 4
HALF SUBTRACTOR & FULL SUBTRACTOR IN VERILOG
USING STRUCTURAL & DATA FLOW MODELLING

AIM :
We will now create the half and full subtractors, crucial for binary subtraction. Employing structural and
dataflow models in Xilinx Vivado, we will implement these subtractors efficiently.

SOFTWARE USED :
XILINX VIVADO

1. HALF SUBTRACTOR:
THEORY:
- A Half Subtractor is a simple digital circuit used for binary subtraction. It consists of an XOR gate for
computing the difference and an AND gate for generating the borrow output. This circuit is crucial for
subtracting single-digit binary numbers and serves as a foundational element for more complex subtraction
operations.

TRUTH TABLE:

A B Diff Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

DATAFLOW MODELLING : SCHEMATIC :

module dataflow_hs(
input a,
input b,
output c,
output d
);
assign c = a^b;
assign d = ~a&b;
endmodule

STRUCTURAL MODELLING :
module hs_1(
input a,
input b,
output c,
output d
);
wire x;
exor_hs(a,b,c);
not_hs(a,x);

15 | P a g e
 and_hs(x,b,d);

endmodule
//EX-OR GATE
module exor_hs(
input a,
input b,
output x
);
assign x = a^b;
endmodule
//NOT GATE
module not_hs(
input a,
output z
);
assign z = ~a;
endmodule
//AND GATE
module and_ha(
input a,
input b,
output y
);
assign y = a&b;
endmodule

TEST BENCH : OUTPUT :

module hs_tb();
wire c1,d1;
reg a,b;
hs_2 hs_3(.a(a), .b(b), .c(c), .d(d));
initial
begin
a=1'b0; b=1'b0;
#5 a=1'b1; b=1'b0;
#5 a=1'b0; b=1'b1;
#5 a=1'b1; b=1'b1;
end
endmodule

2. FULL SUBTRACTOR:
THEORY:
-A Full Subtractor is a vital digital circuit used for binary subtraction. It includes three inputs: minuend (A),
subtrahend (B), and borrow-in (Bin), and two outputs: difference (D) and borrow-out (Bout). The Full
Subtractor efficiently computes the binary difference while considering a borrow input, crucial for cascading
multiple subtractors in multi-digit subtraction operations.

16 | P a g e
TRUTH TABLE:

A B Bin Diff Dout

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 1
1 1 1 1 1

DATAFLOW MODELLING :
module dataflow_fs(
input a,
input b,
input c,
output d,
output cout
);
assign cout = a^b^c;
assign d = ~a&b|~a&c|b&c;
endmodule

STRUCTURAL MODELLING :
module fs_1(
input a,
input b,
input bin,
output d,
output cout
);
wire x1,x2,x3;
hs_1 m1(a,b,x1,x2);
hs_1 m2(x1,bin,d,x3);
or_1 (x3,x2,cout);
endmodule
//HALF ADDER
module hs_1(
input a,
input b,
output c,
output d
);
assign c = a^b;
assign d = ~a&b;
endmodule
// OR GATE
module or_1(
input a,b,
output z
);

17 | P a g e
 assign z=a|b;
endmodule

TEST BENCH :
module fa_tb();
wire s1,cout1;
reg a,b,cin;
fa_1 fa_2(.a(a),.b(b),.cin(cin),.s(s),.cout(cout));
initial
begin
a=1'b0;b=1'b0;cin=1'b0;
#5 a=1'b0;b=1'b0;cin=1'b1;
#5 a=1'b0;b=1'b1;cin=1'b0;
#5 a=1'b0;b=1'b1;cin=1'b1;
#5 a=1'b1;b=1'b0;cin=1'b0;
#5 a=1'b1;b=1'b0;cin=1'b1;
#5 a=1'b1;b=1'b1;cin=1'b0;
#5 a=1'b1;b=1'b1;cin=1'b1;
end
endmodule

SCHEMATIC :

OUTPUT :

CONCLUSION :
All half subtractor & full subtractor in verilog using structural & data flow modelling have been successfully
implemented and executed in Xilinx Verilog.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065
18 | P a g e
 LAB 5
BINARY MULTIPLIER IN VERILOG USING STRUCTURAL &
DATA FLOW MODELLING
AIM :
Developing a binary multiplier in Xilinx Vivado using structural model and test bench and plot the output and
schematic corresponding to it.

SOFTWARE USED :
XILINX VIVADO

1. BINARY MULTIPLIER :
THEORY :
A 4-bit multiplier is a digital circuit that takes two 4-bit binary numbers as inputs and produces an 8-bit binary
number as output, representing their product. The multiplication process involves performing a series of binary
addition and shifting operations, like manual multiplication. Each bit of one input number is multiplied by each
bit of the other input number, and the results are added together to obtain the final product. For example, let's
consider multiplying two 4-bit binary numbers: (A = 1010) and (B = 0011). To compute their product, we
perform the following steps:
1. Multiply each bit of (A) by each bit of (B) using binary multiplication rules:

1 0 1 0 *
0 0 1 1
---------------------
0 0 1 1
0 0 0 0 0
1 0 1 0 0 1
------------------------
1 0 0 1 1 0 1 0
2. Add the intermediate results together to obtain the final product: (10011010)2.
Thus, the product of (1010)2 and (0011)2 is (10011010)2 in binary, which is (154)10 in decimal. This exemplifies
the functionality of a 4-bit multiplier circuit.

DATAFLOW MODEL :
module bm(
input [3:0] A,
input [3:0] B,
output [7:0] Product
);

// Intermediate wires for partial products

wire [3:0] PP0, PP1, PP2, PP3;

// Generate partial products

assign PP0 = A & {4{B[0]}};
assign PP1 = A & {4{B[1]}};
assign PP2 = A & {4{B[2]}};
assign PP3 = A & {4{B[3]}};

// Summation of partial products (with shifting)

assign Product = (PP0 + (PP1 << 1) + (PP2 << 2) + (PP3 << 3));
endmodule

19 | P a g e
SCHEMATIC :

TEST BENCH :
module bm_tb();
reg [3:0] A, B;
wire [7:0] Product;

bm uut (.A(A), .B(B), .Product(Product));

initial begin
$monitor("Time: %t, A = %b, B = %b, Product = %b", $time, A, B, Product);
A = 0; B = 0;
#10 A = 4'b0110; B = 4'b1011; // 6 * 11 = 66
#10 A = 4'b1111; B = 4'b1111; // 15 * 15 = 225
#10;
end
endmodule
OUTPUT :

CONCLUSION :
We have successfully completed the 4-bit binary full adder using Verilog structural and dataflow modeling in
Xilinx Verilog, demonstrating effective implementation and execution.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

20 | P a g e
 LAB 6
MULTIPLEXER (2:1, 4:1, 8:1)
AIM :
We will now create 2:1, 4:1, 8:1 MUX. Employing dataflow models in Xilinx Vivado, we will implement these
multiplexers efficiently.

SOFTWARE USED :
XILINX VIVADO

MULTIPLEXER (MUX) :

THEORY:
- A multiplexer (MUX) selects one input from multiple sources based on control signals, directing it to a
single output. Used in digital systems for data routing, it simplifies circuitry and optimizes resource utilization
in applications like digital communication and networking.

1. 2:1 MUX :
THEORY:
- A 2:1 multiplexer (MUX) is a basic digital circuit that selects between two input signals based on a control
input, transmitting the selected input to a single output.

TRUTH TABLE:

Its truth table illustrates the output corresponding to each input combination and control signal:

Control Input Data input 1 Data input 2 Output (Y)

0 X X D1
1 X X D2

In this table, "X" represents "don't care" values, and the output (Y) is determined by the control input (C): when
C is 0, the output is D0, and when C is 1, the output is D1.

DATAFLOW MODELLING : SCHEMATIC :

module mux_1(
input p,
input q,
input s,
output w
);
assign w = ((~s&p)|(s&q));
endmodule

21 | P a g e
TEST BENCH : OUTPUT :
module mux21_tb();
wire w;
reg p,q,s;
mux_1 mux_3(.p(p), .q(q), .s(s), .w(w));
initial
begin
p=1'b0;q=1'b0;s=1'b0;
#5 p=1'b0;q=1'b0;s=1'b1;
#5 p=1'b0;q=1'b1;s=1'b0;
#5 p=1'b0;q=1'b1;s=1'b1;
#5 p=1'b1;q=1'b0;s=1'b0;
#5 p=1'b1;q=1'b0;s=1'b1;
#5 p=1'b1;q=1'b1;s=1'b0;
#5 p=1'b1;q=1'b1;s=1'b1;
end
endmodule

2. 4:1 MUX :
THEORY:
- A 4:1 multiplexer (MUX) is a basic digital circuit that selects between four input signals based on a control
input, transmitting the selected input to a single output.

TRUTH TABLE:

Its truth table illustrates the output corresponding to each input combination and control signal:

Control Control Data Data Data Data Output (Y)

Input (S0) Input (S1) input 1 input 2 input 3 input 4
(D1) (D2) (D3) (D4)
0 0 X X X X D1
1 1 X X X X D2
1 0 X X X X D3
1 1 X X X X D4

In this table, "X" represents "don't care" values, and the output (Y) is determined by the control input (C): when
C is 00, the output is D0, and when C is 01, the output is D1.

DATAFLOW MODELLING : SCHEMATIC :

module mux_2(
input a,
input b,
input c,
input d,
input s1,
input s2,
output y
);
assign y = ((~s1&~s2&a)|(~s1&s2&b)|(s1&~s2&c)|(s1&s2&d));
endmodule

22 | P a g e
TEST BENCH : OUTPUT :
module mux41_tb();
wire y;
reg a,b,c,d,s1,s2;
mux_2 mux_4(.a(a), .b(b), .c(c),
.d(d),.s1(s1),.s2(s2),.y(y));
initial
begin
a=1'b0;b=1'b0;c=1'b0;s1=1’b0;s2=1’b0;
#5 a=1'b0;b=1'b0;c=1'b1;s1=1’b0;s2=1’b1;
#5 a=1'b0;b=1'b1;c=1'b0;s1=1’b1;s2=1’b0;
#5 a=1'b0;b=1'b1;c=1'b1;s1=1’b1;s2=1’b1;
#5 a=1'b1;b=1'b0;c=1'b0;s1=1’b0;s2=1’b1;
#5 a=1'b1;b=1'b0;c=1'b1;s1=1’b1;s2=1’b0;
#5 a=1'b1;b=1'b1;c=1'b0;s1=1’b1;s2=1’b1;
#5 a=1'b1;b=1'b1;c=1'b1;s1=1’b0;s2=1’b0;
end
endmodule

3. 8:1 MUX :
THEORY:
- A 8:1 multiplexer (MUX) is a basic digital circuit that selects between eight input signals based on a control
input, transmitting the selected input to a single output.

TRUTH TABLE:

Its truth table illustrates the output corresponding to each input combination and control signal:

Control Control Control Data Data Data Data Data Data Data Data Output
Input Input Input input input input input input input input input (Y)
(S0) (S1) (S2) 1 2 3 4 5 6 7 8
(D1) (D2) (D3) (D4) (D5) (D6) (D7) (D8)
0 0 0 X X X X X X X X D1
0 0 1 X X X X X X X X D2
0 1 0 X X X X X X X X D3
0 1 1 X X X X X X X X D4
1 0 0 X X X X X X X X D5
1 0 1 X X X X X X X X D6
1 1 0 X X X X X X X X D7
1 1 1 X X X X X X X X D8

In this table, "X" represents "don't care" values, and the output (Y) is determined by the control inputs (C): when
C is 000, the output is D0, and when C is 001, the output is D1.

23 | P a g e
DATAFLOW MODELLING :
module mux_2(
input a, b, c, d, e, f, g, h,
input s1, s2, s3,
output y
);
assign y
=((~s1&~s2&~s3&a)|(~s1&~s2&s3&b)|(~s1&s2&~s3&c)|(~s1&s2&s3&d)|(s1&~s2&~s3&e)|(s1&~s2&s3&f)|(
s1&s2&~s3&g)|(s1&s2&s3&h));
endmodule

STRUCTURAL MODELLING :
module mux_3(
input i1,i2,i3,i4,i5,i6,i7,i8,
input d1,d2,d3,
output z
);
wire x1,x2;
mux_2 m1(.a(i1),.b(i2),.c(i3),.d(i4),.s1(d1),.s2(d2),.y(x1));
mux_2 m2(.a(i5),.b(i6),.c(i7),.d(i8),.s1(d1),.s2(d2),.y(x2));
mux_1 m3(.p(x1),.q(x2),.s(d3),.w(z));
endmodule

SCHEMATIC :

24 | P a g e
TEST BENCH : OUTPUT :
module mux81_tb();
wire y;
reg i1,i2,i3,i4,i5,i6,i7,i8,d1,d2,d3;
mux_6 mux_8(
.i1(i1), .i2(i2), .i3(i3), .i4(i4),
.i5(i5), .i6(i6), .i7(i7), .i8(i8),
.d1(d1), .d2(d2), .d3(d3),
.y(y)
);
initial
begin
i1 = 1'b1; i2 = 1'b0; i3 = 1'b0; i4 = 1'b0;
i5 = 1'b0; i6 = 1'b0; i7 = 1'b0; i8 = 1'b0;
d1 = 1'b0; d2 = 1'b0; d3 = 1'b0;

#5; i1 = 1'b0; i2 = 1'b1; i3 = 1'b0; i4 = 1'b0;

i5 = 1'b0; i6 = 1'b0; i7 = 1'b0; i8 = 1'b0;
d1 = 1'b0; d2 = 1'b0; d3 = 1'b1;

#5; i1 = 1'b0; i2 = 1'b0; i3 = 1'b1; i4 = 1'b0;

i5 = 1'b0; i6 = 1'b0; i7 = 1'b0; i8 = 1'b0;
d1 = 1'b0; d2 = 1'b1; d3 = 1'b0;

#5; i1 = 1'b0; i2 = 1'b0; i3 = 1'b0; i4 = 1'b1;

i5 = 1'b0; i6 = 1'b0; i7 = 1'b0; i8 = 1'b0;
d1 = 1'b0; d2 = 1'b1; d3 = 1'b1;
// Add more test cases as needed

end
endmodule

CONCLUSION :
All types of MUX(2:1, 4:1, 8:1) in verilog using structural & data flow modelling respectively have been
successfully implemented and executed in Xilinx Verilog.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

25 | P a g e
 LAB 7
DE-MULTIPLEXER (1:2, 1:4, 1:8)
AIM :
We will now create 1:2, 1:4, 1:8 MUX. Employing dataflow models in Xilinx Vivado, we will implement these
multiplexers efficiently.

SOFTWARE USED :
XILINX VIVADO

DE-MULTIPLEXER (DE-MUX) :

THEORY:
- A demultiplexer, or demux, is a fundamental digital circuit component that takes a single input and routes it to
one of several possible output lines based on the value of its control inputs. Conceptually, it acts as a reverse of a
multiplexer, enabling the distribution of data from one source to multiple destinations.

1. 1:2 DEMUX :
THEORY:
- For a 1:2 demux, there are two output lines, typically labeled Y0 and Y1, and one input line, typically labeled
D. A single control input, typically labeled S, determines which output line receives the input data.

TRUTH TABLE:

Its truth table illustrates the output corresponding to each input combination and control signal:

Control Input (S) Data input (D) Output (Y1) Output (Y2)
0 X D 0
1 X 0 D

In this table, "X" represents "don't care" values, and the output (Y) is determined by the control input (C): when
C is 0, the output is D0, and when C is 1, the output is D1.

BEHAVIOURAL MODELLING : SCHEMATIC :

module dmux_21(
input a,
input s,
output y0,
output y1
);
reg y0,y1;
always@(a,s)
begin
y0=(~s&a);
y1=(s&a);
end
endmodule

26 | P a g e
TEST BENCH : OUTPUT :
module dmux12_tb();
wire y0,y1;
reg a,s;
dmux_21 dmux_3(.a(a), .s(s), .y0(y0), .y1(y1));
initial
begin
a=1'b0;s=1'b0;
#5 a=1'b0;s=1'b1;
#5 a=1'b1;s=1'b0;
#5 a=1'b1;s=1'b1;
end
endmodule

2. 1:4 DEMUX :
THEORY:
- For a 1:4 demux, there are four output lines, Y0 through Y3, and one input line, D. Two control inputs,
typically labeled S0 and S1, determine which output line receives the input data.

TRUTH TABLE:

Its truth table illustrates the output corresponding to each input combination and control signal:

Control Control Data input Output Output Output Output

Input (S0) Input (S1) (D) (Y0) (Y1) (Y2) (Y3)
0 0 X D 0 0 0
0 1 X 0 D 0 0
1 0 X 0 0 D 0
1 1 X 0 0 0 D

In this table, "X" represents "don't care" values, and the output (Y) is determined by the control input (C): when
C is 00, the output is D0, and when C is 01, the output is D1.

DATAFLOW MODELLING : SCHEMATIC :

module dmux_14(
input a,
input s0,
input s1,
output y0,y1,y2,y3
);
assign y0 = (~s0&~s1&a);
assign y1 = (~s0&s1&a);
assign y2 = (s0&~s1&a);
assign y3 = (s0&s1&a);
endmodule

27 | P a g e
TEST BENCH : OUTPUT :
module dmux14_tb();
wire y0,y1,y2,y3;
reg a,s0,s1;
dmux_14 dmux_6(.a(a), .s0(s0), .s1(s1),
.y0(y0), .y1(y1), .y2(y2), .y3(y3));
initial
begin
a=1'b0;s0=1'b0;s1=1'b0;
#5 a=1'b0;s0=1'b0;s1=1'b1;
#5 a=1'b0;s0=1'b1;s1=1'b0;
#5 a=1'b0;s0=1'b1;s1=1'b1;
#5 a=1'b1;s0=1'b0;s1=1'b0;
#5 a=1'b1;s0=1'b0;s1=1'b1;
#5 a=1'b1;s0=1'b1;s1=1'b0;
#5 a=1'b1;s0=1'b1;s1=1'b1;
end
endmodule

3. 1:8 DEMUX :
THEORY:
- For a 1:8 demux, there are eight output lines, and three control inputs, typically labeled S0, S1, and S2. The
truth table for a 1:8 demux follows the same pattern as the 1:4 demux, with additional rows to accommodate the
increased number of output lines.

TRUTH TABLE:

Its truth table illustrates the output corresponding to each input combination and control signal:

Control Control Control Data Output Output Output Output Output Output Output Output
Input Input Input input (Y0) (Y1) (Y2) (Y3) (Y4) (Y5) (Y6) (Y7)
(S0) (S1) (S2) (D)
0 0 0 X D 0 0 0 0 0 0 0
0 0 1 X 0 D 0 0 0 0 0 0
0 1 0 X 0 0 D 0 0 0 0 0
0 1 1 X 0 0 0 D 0 0 0 0
1 0 0 X 0 0 0 0 D 0 0 0
1 0 1 X 0 0 0 0 0 D 0 0
1 1 0 X 0 0 0 0 0 0 D 0
1 1 1 X 0 0 0 0 0 0 0 D

In this table, "X" represents "don't care" values, and the output (Y) is determined by the control inputs (C): when
C is 000, the output is D0, and when C is 001, the output is D1.

28 | P a g e
STRUCTURAL MODELLING :
module dmux_18(
input a,s0,s1,s2,
output y0,y1,y2,y3,y4,y5,y6,y7
);
wire x1,x2,x3,x4,x5,x6;
dmux_21 m1(a,s2,x1,x2);
dmux_21 m2(x1,s1,x3,x4);
dmux_21 m3(x2,s1,x5,x6);
dmux_21 m4(x3,s0,y0,y1);
dmux_21 m5(x4,s0,y2,y3);
dmux_21 m6(x5,s0,y4,y5);
dmux_21 m7(x6,s0,y6,y7);
endmodule
//1:2 DE-MUX
module dmux_21(
input a,
input s,
output y0,
output y1
);
reg y0,y1;
always@(a,s)
begin
y0=(~s&a);
y1=(s&a);
end
endmodule

SCHEMATIC :

29 | P a g e
TEST BENCH :
module dmux18_tb();
wire y0,y1,y2,y3,y4,y5,y6,y7;
reg a,s0,s1,s2;
dmux_18 dmux_7(.a(a), .s0(s0), .s1(s1), .s2(s2), .y0(y0), .y1(y1), .y2(y2), .y3(y3), .y4(y4), .y5(y5), .y6(y6),
.y7(y7));
initial
begin
a=1'b0;s0=1'b0;s1=1'b0;s2=1'b0;
#5 a=1'b0;s0=1'b0;s1=1'b0;s2=1'b1;
#5 a=1'b0;s0=1'b0;s1=1'b1;s2=1'b0;
#5 a=1'b0;s0=1'b0;s1=1'b1;s2=1'b1;
#5 a=1'b0;s0=1'b1;s1=1'b0;s2=1'b0;
#5 a=1'b0;s0=1'b1;s1=1'b0;s2=1'b1;
#5 a=1'b0;s0=1'b1;s1=1'b1;s2=1'b0;
#5 a=1'b0;s0=1'b1;s1=1'b1;s2=1'b1;
#5 a=1'b1;s0=1'b0;s1=1'b0;s2=1'b0;
#5 a=1'b1;s0=1'b0;s1=1'b0;s2=1'b1;
#5 a=1'b1;s0=1'b0;s1=1'b1;s2=1'b0;
#5 a=1'b1;s0=1'b0;s1=1'b1;s2=1'b1;
#5 a=1'b1;s0=1'b1;s1=1'b0;s2=1'b0;
#5 a=1'b1;s0=1'b1;s1=1'b0;s2=1'b1;
#5 a=1'b1;s0=1'b1;s1=1'b1;s2=1'b0;
#5 a=1'b1;s0=1'b1;s1=1'b1;s2=1'b1;
end
endmodule

OUTPUT :

CONCLUSION :
All types of DEMUX(1:2, 1:4, 1:8) in verilog using structural, behavioral, dataflow & data flow modelling
respectively have been successfully implemented and executed in Xilinx Verilog.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

30 | P a g e
 LAB 8
COMPARATOR

AIM :
Developing a Comparator in Xilinx Vivado using structural model and test bench and plot the output and
schematic corresponding to it.

SOFTWARE USED :
XILINX VIVADO

1. COMPARATOR:
THEORY :
A comparator is a fundamental electronic component used to compare the magnitudes of two input signals. Its
primary function is to determine whether one input signal is greater than, equal to, or less than the other.
Typically found in analog circuits, comparators produce a digital output based on this comparison, often
represented by logic levels such as high (1) or low (0).

BEHAVIORAL MODEL :
module comp2_1(input [1:0]a, [1:0]b, output g, e, s);
reg g, e, s;

always @(*) begin

if(a == b) begin
g = 1'b0;
e = 1'b1;
s = 1'b0;
end
else if(a > b) begin
g = 1'b1;
e = 1'b0;
s = 1'b0;
end
else begin // a < b
g = 1'b0;
e = 1'b0;
s = 1'b1;
end
end
endmodule

31 | P a g e
SCHEMATIC :

TEST BENCH :
module comp2_1_tb;
reg [1:0] a, b;
wire g, e, s;
comp2_1 comp_3 (.a(a),.b(b),.g(g),.e(e),.s(s));
initial begin
a = 2;b = 2;#10;
a = 3;b = 1;#10;
a = 0;b = 3;#10;
end
endmodule

OUTPUT :

CONCLUSION :
We have successfully completed the Comparator using Verilog behavioral modeling in Xilinx Verilog,
demonstrating effective implementation and execution.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

32 | P a g e
 LAB 9
ENCODER (2:1, 4:2, 8:3)
AIM :
We will now create encoder (2:1, 4:2, 8:3). Employing dataflow models in Xilinx Vivado, we will implement
these encoders efficiently.

SOFTWARE USED :
XILINX VIVADO

ENCODER :
THEORY:
- Encoders are digital circuits that compress multiple input signals into a reduced set of output signals, usually
in binary form. They serve to streamline data representation, prioritizing efficiency in communication and
control systems. By encoding information from various sources, encoders facilitate tasks like data transmission,
address decoding, and sensor interfacing, optimizing information processing.

1. 2:1 ENCODER :
THEORY:
- 2:1 Encoder: Converts 2 input lines into 1 output line, with priority given to the highest numbered input.

TRUTH TABLE:
Its truth table illustrates the output corresponding to each input combination and control signal:

A B Y
0 1 1
1 0 2

For the 2:1 encoder, the output is a single line representing the highest numbered active input.

BEHAVIOURAL MODELLING : SCHEMATIC :

module encoder_21(
input a,b,
output y
);
assign y = a|b;
endmodule

2. 4:2 ENCODER :
THEORY:
- 4:2 Encoder: Converts 4 input lines into 2 output lines, encoding the highest numbered active input.
TRUTH TABLE:
Its truth table illustrates the output corresponding to each input combination and control signal:

A B C D Y1 Y0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

33 | P a g e
For the 4:2 encoder, there are two output lines representing the two highest numbered active inputs.

DATAFLOW MODELLING : SCHEMATIC :

module encoder_42(
input a,b,c,d,
output x,y,z
);
assign x = c|d;
assign y = d|(b&(~c));
assign z = a|b|c|d;
endmodule

3. 8:3 ENCODER :
THEORY:
- 8:3 Encoder: Converts 8 input lines into 3 output lines, with priority given to the highest numbered active
input.

TRUTH TABLE:

Its truth table illustrates the output corresponding to each input combination and control signal:

A B C D E F G H Y2 Y1 Y0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

For the 8:3 encoder, there are three output lines representing the three highest numbered active inputs.

STRUCTURAL MODELLING : SCHEMATIC :

module encoder_83_1(
input d0,
input d1,
input d2,
input d3,
input d4,
input d5,
input d6,
input d7,
output q0,
output q1,
output q2
);
or (q0,d1,d3,d5,d7),(q1,d2,d3,d6,d7),(q2,d4,d5,d6,d7);
endmodule

34 | P a g e
TEST BENCH :
module encoder_83_tb();
wire q0,q1,q2;
reg d0,d1,d2,d3,d4,d5,d6,d7;
encoder_83_1 encoder_7(.d0(d0), .d1(d1), .d2(d2), .d3(d3), .d4(d4), .d5(d5), .d6(d6), .d7(d7), q0(q0), .q1(q1),
.q2(q2));

initial
begin
d0 = 1;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 0;
#10 d0 = 0;d1 = 1;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 0;
#10 d0 = 0;d1 = 0;d2 = 1;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 0;
#10 d0 = 0;d1 = 0;d2 = 0;d3 = 1;d4 = 0;d5 = 0;d6 = 0;d7 = 0;
#10 d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 1;d5 = 0;d6 = 0;d7 = 0;
#10 d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 1;d6 = 0;d7 = 0;
#10 d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 1;d7 = 0;
#10 d0 = 0;d1 = 0;d2 = 0;d3 = 0;d4 = 0;d5 = 0;d6 = 0;d7 = 1;
end
endmodule

OUTPUT :

CONCLUSION :
All types of ENCODERS (2:1, 4:2, 8:3) in verilog using structural, behavioral, dataflow & data flow modelling
respectively have been successfully implemented and executed in Xilinx Verilog.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

35 | P a g e
 LAB 10
DECODER (1:2, 2:4, 3:8)
AIM :
We will now create Decoder (1:2, 2:4, 3:8). Employing dataflow models in Xilinx Vivado, we will implement
these encoders efficiently.

SOFTWARE USED :
XILINX VIVADO

DECODER :
THEORY:
- A decoder is a combinational logic circuit that converts coded inputs into a set of output signals. Specifically,
in digital electronics, a decoder takes an n-bit input and selects one of 2^n output lines, depending on the input
code. The most common type of decoder is the binary decoder, which has 2^n output lines and n input lines.
Each output line corresponds to a specific binary code input. When a particular binary input is applied, the
corresponding output line is activated (set to logic high), while all other output lines remain inactive (set to logic
low).

1. 1:2 DECODER :
THEORY:
- A 1:2 decoder is a digital circuit that takes a single input line and selects one of two output lines based on the
input signal.

TRUTH TABLE:
Its truth table illustrates the output corresponding to each input combination and control signal:

A Y1 Y0
0 0 1
1 1 0

DATAFLOW MODELLING : SCHEMATIC :

module decoder_12 (
input in,
output [1:0] out
);
// Priority decoder
assign out[0] = ~in;
assign out[1] = in;
endmodule

2. 2:4 DECODER :
THEORY:
- A 2:4 decoder is a digital circuit that takes two input lines and selects one of four output lines based on the
input signal combination.

36 | P a g e
TRUTH TABLE:
Its truth table illustrates the output corresponding to each input combination and control signal:

A B Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

DATAFLOW MODELLING : SCHEMATIC :

module decoder_24(
input a,b,en,
output d0,d1,d2,d3
);
assign d0 = ~((~a)&(~b)&(~en));
assign d1 = ~((~a)&(b)&(~en));
assign d2 = ~((a)&(~b)&(~en));
assign d3 = ~((a)&(b)&(~en));
endmodule

3. 3:8 DECODER :
THEORY:
- A 3:8 decoder is a digital circuit that takes three input lines and selects one of eight output lines based on the
input signal combination.

TRUTH TABLE:

Its truth table illustrates the output corresponding to each input combination and control signal:

A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0

37 | P a g e
STRUCTURAL MODELLING :
module decoder_38(
input [2:0] in,
output reg [7:0] out
);
wire [1:0] temp1, temp2, temp3;
// First 1:2 decoder
decoder_12 decoder1 (
.in(in[0]),
.out(temp1)
);
// Second 1:2 decoder
decoder_12 decoder2 (
.in(in[1]),
.out(temp2)
);
// Third 1:2 decoder
decoder_12 decoder3 (
.in(in[2]),
.out(temp3)
);
// Output logic
always @* begin
out[0] = temp1[0] & temp2[0] & temp3[0];
out[1] = temp1[0] & temp2[0] & temp3[1];
out[2] = temp1[0] & temp2[1] & temp3[0];
out[3] = temp1[0] & temp2[1] & temp3[1];
out[4] = temp1[1] & temp2[0] & temp3[0];
out[5] = temp1[1] & temp2[0] & temp3[1];
out[6] = temp1[1] & temp2[1] & temp3[0];
out[7] = temp1[1] & temp2[1] & temp3[1];
end
endmodule
module decoder_12 (
input in,
output [1:0] out
);
// Priority decoder
assign out[0] = ~in;
assign out[1] = in;
endmodule

SCHEMATIC :

38 | P a g e
TEST BENCH :
module decoder_38_tb();
reg [2:0] in;
wire [7:0] out;
decoder_38 deccoder_3(
.in(in),
.out(out)
);
initial
begin
in = 3'b000;
#10 in = 3'b001;
#10 in = 3'b010;
#10 in = 3'b011;
#10 in = 3'b100;
#10 in = 3'b101;
#10 in = 3'b110;
#10 in = 3'b111;
end
endmodule

OUTPUT :

CONCLUSION :
All types of DECODERS (1:2, 2:4, 3:8) in verilog using structural, behavioral, dataflow & data flow modelling
respectively have been successfully implemented and executed in Xilinx Verilog.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

39 | P a g e
 LAB 11
PRIORITY ENCODER

AIM :
Developing a priority encoder in Xilinx Vivado using structural model and test bench and plot the output and
schematic corresponding to it.

SOFTWARE USED :
XILINX VIVADO

1. PRIORITY ENCODER:
THEORY :
A priority encoder is a digital circuit that converts multiple input lines into a binary representation of the
highest-priority active input. The output of a priority encoder is determined by the highest-order active input.
For instance, in a 4-input priority encoder, if multiple inputs are active simultaneously, the encoder will
prioritize the input with the highest index (e.g., I3 has higher priority than I2, which has higher priority than I1,
and so on).

TRUTH TABLE :
A3 A2 A1 A0 Y1 Y0 V
0 0 0 0 0 0 0
0 0 0 1 0 1 1
0 0 1 0 0 1 1
0 0 1 1 0 1 1
0 1 X X 1 1 1
1 X X X 1 1 1

BEHAVIORAL MODEL :
module penc_1(
input a0,
input a1,
input a2,
input a3,
output y0,
output y1,
output v
);
assign y0= a3|a2;
assign y1=a3|(~a2&a1);
assign v=a3|a2|a1|a0;
endmodule

40 | P a g e
SCHEMATIC :

TEST BENCH :
module penc_tb();
reg a0, a1, a2, a3;
wire y0, y1, v;
penc_1 penc_2 (.a0(a0), .a1(a1), .a2(a2), .a3(a3), .y0(y0), .y1(y1), .v(v));
initial
begin
for (integer i = 0; i < 16; i = i + 1) begin
{a3, a2, a1, a0} = i;
#10;
end
end
initial begin
$monitor("Time = %t, Inputs = %b, Outputs = %b%b, v = %b", $time, {a3, a2, a1, a0}, y1, y0, v);
end
endmodule

OUTPUT :

CONCLUSION :
We have successfully completed the Priority encoder using Verilog behavioral modeling in Xilinx Verilog,
demonstrating effective implementation and execution.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

41 | P a g e
 LAB 12
ARITHMATIC & LOGICAL UNIT (ALU)

AIM :
Developing a ALU in Xilinx Vivado using structural model and test bench and plot the output and schematic
corresponding to it.

SOFTWARE USED :
XILINX VIVADO

1. ALU:
THEORY :
The 1-bit Arithmetic Logic Unit (ALU) is a fundamental component of digital circuits used in computers and
other digital systems. Its purpose is to perform arithmetic and logic operations on binary numbers. In a 1-bit
ALU, the operations are performed on individual bits of binary numbers.
The basic operations typically supported by a 1-bit ALU include:
Addition: Adding two binary digits (bits) along with a carry-in bit to produce a sum bit and a carry-out bit.
Subtraction: Subtracting one binary digit from another along with a borrow-in bit to produce a difference bit and
a borrow-out bit.
Logical AND: Performing a logical AND operation on two input bits to produce an output bit.
Logical OR: Performing a logical OR operation on two input bits to produce an output bit.
Logical XOR: Performing a logical XOR (exclusive OR) operation on two input bits to produce an output bit.
Logical NOT: Performing a logical NOT (negation) operation on a single input bit to produce an output bit.
These operations are typically implemented using basic digital logic gates such as AND gates, OR gates, XOR
gates, and inverters (NOT gates). The inputs to the ALU are the two binary numbers to be operated on, along
with control signals that specify which operation to perform. The output of the ALU is the result of the specified
operation.

BEHAVIORAL MODEL :
module alu_1bit(input a, b, input [2:0] mode, output reg result);
always @(*) begin
case(mode)
3'b000: result = a & b; // Logical AND & Mul
3'b001: result = a | b; // Logical OR
3'b010: result = a ^ b; // Logical XOR & Add & Sub
3'b011: result = ~(a & b); // Logical NAND
3'b100: result = ~(a | b); // Logical NOR
3'b101: result = ~(a ^ b); // Logical XNOR
default: result = 1'b0; // Default to 0 for unknown mode
endcase
end
endmodule

42 | P a g e
SCHEMATIC :

TEST BENCH :
module alu1_tb();
reg a, b;
reg [2:0] mode;
wire result;
alu_1bit alu_4 (a, b, mode, result);
initial begin
$monitor("time=%3d, a=%b, b=%b, mode=%b, result=%b", $time, a, b, mode, result);
for (integer i = 0; i < 8; i = i + 1) begin
mode = i;
for (integer j = 0; j < 4; j = j + 1) begin
{a, b} = j;
#10;
end
end
end
endmodule

OUTPUT :

CONCLUSION :
We have successfully completed the ALU using Verilog behavioral modeling in Xilinx Verilog, demonstrating
effective implementation and execution.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

43 | P a g e
 LAB 12
BCD TO 7 SEGMENT DISPLAY

AIM :
Developing a BCD to 7 segment display in Xilinx Vivado using structural model and test bench and plot the
output and schematic corresponding to it.

SOFTWARE USED :
XILINX VIVADO

1. ALU:
THEORY :
1. BCD Encoding

BCD encoding represents each decimal digit from 0 to 9 using a 4-bit binary code. For example:

Decimal 0 is represented as 0000

Decimal 1 is represented as 0001
Decimal 2 is represented as 0010
...
Decimal 9 is represented as 1001
2. 7-Segment Display

A 7-segment display is a form of electronic display device for displaying decimal numerals. It consists of seven
LED segments arranged in a rectangular pattern. Each segment is either on or off, controlled by an input signal.
The arrangement of segments allows the display of decimal digits 0 through 9 and some alphabetic characters
(A-F for hexadecimal display).

3. BCD to 7-Segment Conversion

The BCD to 7-Segment conversion requires mapping each BCD input to the corresponding pattern of segments
to display the decimal digit. This mapping is typically done using a truth table or logic equations.

BEHAVIORAL MODEL :
module bcd_1(
input [3:0] bcd,
output reg [6:0] seg
);

always @* begin
case (bcd)
4'b0000: seg = 7'b1000000; // 0
4'b0001: seg = 7'b1111001; // 1
4'b0010: seg = 7'b0100100; // 2
4'b0011: seg = 7'b0110000; // 3
4'b0100: seg = 7'b0011001; // 4
4'b0101: seg = 7'b0010010; // 5
4'b0110: seg = 7'b0000010; // 6
4'b0111: seg = 7'b1111000; // 7
4'b1000: seg = 7'b0000000; // 8
4'b1001: seg = 7'b0010000; // 9
default: seg = 7'b1111111; // default to all segments off
endcase

44 | P a g e
end

endmodule

SCHEMATIC :

TEST BENCH :
module alu1_tb();
reg a, b;
reg [2:0] mode;
wire result;
alu_1bit alu_4 (a, b, mode, result);
initial begin
$monitor("time=%3d, a=%b, b=%b, mode=%b, result=%b", $time, a, b, mode, result);
for (integer i = 0; i < 8; i = i + 1) begin
mode = i;
for (integer j = 0; j < 4; j = j + 1) begin
{a, b} = j;
#10;
end
end
end
endmodule

HARDWARE IMPLEMENTATION (CONSTRAINT FILE):

# Switches
set_property PACKAGE_PIN V17 [get_ports {bcd[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {bcd[0]}]
set_property PACKAGE_PIN V16 [get_ports {bcd[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {bcd[1]}]
set_property PACKAGE_PIN W16 [get_ports {bcd[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {bcd[2]}]
set_property PACKAGE_PIN W17 [get_ports {bcd[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {bcd[3]}]

#7 segment display
set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]

45 | P a g e
 set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]

set_property PACKAGE_PIN V7 [get_ports dp]

set_property IOSTANDARD LVCMOS33 [get_ports dp]

set_property PACKAGE_PIN U2 [get_ports {an[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]

OUTPUT :

CONCLUSION :
We have successfully completed the BCD to 7 SEGMENT using Verilog behavioral modeling in Xilinx Verilog,
demonstrating effective implementation and execution.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

46 | P a g e
 LAB 13
LATCHES & FLIP FLOPS
AIM :
Basic Latches and flip flops in the Xilinx Vivado using structural, dataflow models.

SOFTWARE USED :
XILINX VIVADO

1. SR LATCH:
THEORY:
The SR (Set-Reset) Latch is a basic type of latch circuit that can store one bit of data. It has two inputs, labeled
S (Set) and R (Reset), and two outputs, Q and Q' (Q-bar, the complement of Q). The SR latch is built using two
cross-coupled NOR or NAND gates. It is a fundamental building block for flip-flops and more complex memory
circuits.
NOR-based SR Latch: Setting S to 1 and R to 0 sets the latch, making Q = 1 and Q' = 0. Resetting occurs when
S = 0 and R = 1, making Q = 0 and Q' = 1. When both inputs are 0, the output state is maintained. An invalid
state occurs when both inputs are 1.
NAND-based SR Latch: Operates similarly but with opposite input conditions. The latch is set with S = 0 and R
= 1, reset with S = 1 and R = 0, holds with S = R = 1, and enters an invalid state with S = R = 0.

TRUTH TABLE:

S R Q(NEXT) Q’(NEXT)
0 0 Q Q’
0 1 0 1
1 0 1 0
1 1 Invalid Invalid

DATAFLOW MODELLING : SCHEMATIC :

module latchsr_1(
input s,
input r,
input en,
output q,
output q0
);
wire x,y;
assign x = ~((s)&(en));
assign y = ~((r)&(en));
assign q = ~((x)&(q0));
assign q0 = ~((y)&(q));
endmodule

47 | P a g e
TEST BENCH : OUTPUT :
module srlatch_tb();
reg s, r, en;
wire q, q0;
latchsr_1 latchsr_2 (s, r, en, q, q0);
initial begin
s = 0; r = 0; en = 0;
#10 en = 1; // Enable the latch
#10 s = 1; r = 0; // Set Q
#10 s = 0; r = 0; // Hold state
#10 s = 0; r = 1; // Reset Q
#10 s = 0; r = 0; // Hold state
#10 s = 1; r = 1; // (Potentially undefined condition)
#10 en = 0; // Disable the latch
#10 s = 1; r = 0; // Inputs should have no effect
#10; // End simulation
end
endmodule

2. SR FLIP FLOP:
THEORY:
- The SR Flip-Flop is a clocked version of the SR latch. It includes a control signal known as the "clock"
which determines when the flip-flop can change states. The clock signal allows the flip-flop to synchronize with
a system clock, making it suitable for edge-triggered operations in digital circuits.

TRUTH TABLE:

S R Q(NEXT) Q’(NEXT)
0 0 Q Q’
0 1 0 1
1 0 1 0
1 1 Invalid Invalid

DATAFLOW MODELLING :
module srff_1(
input wire clk,
input wire reset,
input wire s,
input wire r,
output reg q,
output reg q_bar
);
always @(posedge clk or posedge reset) begin
if (reset) begin
q <= 1'b0; // Reset state
q_bar <= 1'b1; // Reset state (inverted output)
end
else begin
if (s & ~r) begin // Set condition: S=1, R=0
q <= 1'b1;
q_bar <= 1'b0;
end
else if (~s & r) begin // Reset condition: S=0, R=1

48 | P a g e
 q <= 1'b0;
q_bar <= 1'b1;
end
// If both S and R are 0, maintain the current state
end
end
endmodule

SCHEMATIC :

TEST BENCH :
module srff_tb();
reg clk, reset, s, r;
wire q, q_bar;
srff_1 srff_2 (clk, reset, s, r, q, q_bar);
// Generate a clock signal
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
reset = 1; s = 0; r = 0;
#10 reset = 0; // Release reset
#10 s = 1; r = 0;
#20 s = 0; r = 0; // Hold state
#10 s = 0; r = 1;
#20 s = 0; r = 0; // Hold state
// Invalid (S=R=1) - should ideally be avoided
#10 s = 1; r = 1;
#10;
end
endmodule

49 | P a g e
OUTPUT :

3. D-FLIP FLOP:
THEORY:
-The D (Data) Flip-Flop has a single data input along with a clock input. The main feature of the D flip-flop is
that it captures the value at the data input at a rising or falling clock edge and outputs this value stably until the
next clock edge. It essentially serves as a 1-bit memory cell.

TRUTH TABLE:

D Q(NEXT)
0 0
1 1

DATAFLOW MODELLING : SCHEMATIC :

module d_flip_flop(
input wire clk,
input wire reset,
input wire d,
output reg q
);
always @(posedge clk or posedge reset)
begin
if (reset)
q <= 1'b0; // Reset state
else
q <= d; // D input state
end
endmodule

TEST BENCH : OUTPUT :

module dff_tb();
reg clk, reset, d;
wire q;
d_flip_flop dff_2 (clk, reset, d, q);
initial begin
clk = 0;
forever #5 clk = ~clk;
end

initial
begin

50 | P a g e
 reset = 1; d = 0;
#10 reset = 0;
#10 d = 1;
#20 d = 0;
#10 d = 1;
#20;
end
endmodule

4. T-FLIP FLOP:
THEORY:
- The T (Toggle) Flip-Flop is a modified version of the D flip-flop. It has a T input and toggles its output on
each clock edge when T is high. When T is low, the output does not change. The T flip-flop is useful for
counting applications as it divides the input clock frequency by two.

TRUTH TABLE:

T Q(Previous) Q(Next)
0 0 0
0 1 1
1 0 1
1 1 0

DATAFLOW MODELLING :
module tff_1(
input wire clk,
input wire reset,
input wire t,
output reg q
);
reg q_next;
always @(posedge clk or posedge reset) begin
if (reset)
q <= 1'b0; // Reset state
else begin
if (t) // T input is 1
q_next <= ~q; // Toggle q
else // T input is 0
q_next <= q; // Maintain q
end
end
always @* begin
q = q_next; // Update q asynchronously
end
endmodule

51 | P a g e
SCHEMATIC :

TEST BENCH :
module tff_tb();
reg clk, reset, t;
wire q;
tff_1 tff_2 (clk, reset, t, q);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial
begin
reset = 1; t = 0;
#10 reset = 0; // Release reset
// Toggle the flip-flop several times
#10 t = 1;
#10 t = 0;
#10 t = 1;
#20 t = 0;
#20;
end
endmodule

OUTPUT :

5. JK FLIP FLOP:
THEORY:
- The JK Flip-Flop combines features of the SR and T flip-flops. It has two inputs, J and K, which behave like
the S and R inputs of an SR flip-flop. However, the JK flip-flop does not have an invalid state. If both J and K
are high, the flip-flop toggles its state. This versatility makes the JK flip-flop suitable for a wider range of
applications than the SR flip-flop.

52 | P a g e
TRUTH TABLE:

J K Q(Previous) Q(Next)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

DATAFLOW MODELLING :
module jkff_1(
input wire clk,
input wire reset,
input wire j,
input wire k,
output reg q
);
reg q_next;
always @(posedge clk or posedge reset) begin
if (reset)
q <= 1'b0; // Reset state
else begin
if (j & ~k) // J=1, K=0
q_next = 1'b1; // Set
else if (~j & k) // J=0, K=1
q_next = 1'b0; // Reset
else if (j & k) // J=1, K=1
q_next = ~q; // Toggle
else // J=0, K=0
q_next = q; // Hold
end
end
always @* begin
q = q_next; // Update q asynchronously
end
endmodule

SCHEMATIC :

53 | P a g e
TEST BENCH :
module jkff_tb();
reg clk, reset, j, k;
wire q;
jkff_1 jkff_2 (clk, reset, j, k, q);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
reset = 1; j = 0; k = 0;
#10 reset = 0;
#10 j = 1; k = 0;
#20 j = 0; k = 0; // Hold state
#10 j = 0; k = 1;
#20 j = 0; k = 0; // Hold state
// Test Toggle condition
#10 j = 1; k = 1;
#10 j = 1; k = 1; // Continue Toggling
#20;
end
endmodule

OUTPUT :

CONCLUSION :

All the flip flops & SR latch have been successfully verified and compiled on the Xilinx verilog.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

54 | P a g e
 LAB 14
SHIFT REGISTERS
AIM :
Develop Shift Registers in the Xilinx Vivado using structural, dataflow models.

SOFTWARE USED :
XILINX VIVADO

SHIFT REGISTERS:
Shift registers are a type of sequential logic circuit, primarily used for the storage and movement of digital data.
They are used in various applications including data processing, data storage, and data transfer in VLSI systems.
A shift register mainly consists of a series of flip-flops, where each flip-flop can store a single bit of data. The
data in a shift register can be shifted left or right based on the control signals and can be used in various
configurations such as Serial-In Serial-Out (SISO), Serial-In Parallel-Out (SIPO), Parallel-In Serial-Out (PISO),
and Parallel-In Parallel-Out (PIPO). These configurations are defined by the method in which data is inputted
and outputted from the register.

1. SISO (SERIAL-IN SERIAL-OUT):

THEORY:
A Serial-In Serial-Out shift register is the simplest type of shift register. In a SISO shift register, data enters at
one end (serial input) and is shifted right or left through each flip-flop in the register one bit at a time per clock
cycle. The data exits at the opposite end from the input (serial output).
Operation:
Input: Data is input serially at one end.
Process: With each clock pulse, each bit in the register is shifted to the adjacent flip-flop.
Output: Data is output serially from the opposite end.

DATAFLOW MODELLING :
module siso_1(
input wire clk,
input wire reset,
input wire x,
output q
);
wire q0,q1,q2,q3;
d_flip_flop ad0(clk, reset, x, q0); // D input state
d_flip_flop ad1(clk, reset, q0, q1); // D input state
d_flip_flop ad2(clk, reset, q1, q2); // D input state
d_flip_flop ad3(clk, reset, q2, q3); // D input state
assign q=q3;
endmodule
module d_flip_flop(
input wire clk,
input wire reset,
input wire d,
output reg q
);
always @(posedge clk or posedge reset) begin
if (reset)
q <= 1'b0; // Reset state

55 | P a g e
 else
q <= d; // D input state
end
endmodule

SCHEMATIC :

TEST BENCH : OUTPUT :

module siso_tb();
reg clk = 0;
reg reset = 1;
reg x = 0;
wire q;
siso_b1
siso_2(.clk(clk),.reset(reset),.x(x),.q(q));
always #5 clk = ~clk;
initial begin
#5 reset = 0; // Release reset after 5 time
units
#10 x = 1; // Apply input '1' after 10 time units
#10 x = 0; // Apply input '0' after 10 time units
#50; // End simulation after 100 time units
end
endmodule

2. SIPO (SERIAL IN PARALLEL OUT):

THEORY:
- A Serial-In Parallel-Out shift register allows input data to be entered serially and output data to be retrieved
in parallel. This configuration is useful when converting serial data to parallel data, often needed in interfacing
and data handling applications.
Operation:
Input: Data is input serially at one end.
Process: Each bit is shifted through the flip-flops sequentially with each clock pulse.
Output: Each bit is available simultaneously at the output pins after being shifted through the register.

56 | P a g e
DATAFLOW MODELLING : SCHEMATIC :

module sipo_b1(
input wire clk, // Clock input
input wire reset, // Reset input
input wire serial_in, // Serial input
output reg [3:0] parallel_out // Parallel output
);
// Internal signals
reg q0;
reg q1;
reg q2;
reg q3; // Individual flip-flop outputs
// Flip-flop logic
always @(posedge clk or posedge reset) begin
if (reset) begin
q0 <= 1'b0; // Reset state
q1 <= 1'b0;
q2 <= 1'b0;
q3 <= 1'b0;
end
else begin
q0 <= serial_in; // D input state
q1 <= q0;
q2 <= q1;
q3 <= q2;
end
end
// Assign output
always @* begin
parallel_out = {q3, q2, q1, q0}; // Output connected to the individual flip-flop outputs
end
endmodule

TEST BENCH :
module sipo_tb();
reg clk = 0;
reg reset = 1;
reg serial_in = 0;
wire [3:0] parallel_out;
sipo_b1 sipo_2 (.clk(clk), .reset(reset), .serial_in(serial_in), .parallel_out(parallel_out));
// Clock generation
always #5 clk = ~clk;
initial begin
clk = 0;
reset = 1;
serial_in = 0;
#10 reset = 0; // Release reset after 10 time units
end
initial begin
// Apply serial input sequence
#10 serial_in = 1;
#10 serial_in = 0;
#40 ;
end
always #1 $display("Time=%t, parallel_out=%b", $time, parallel_out);
endmodule

57 | P a g e
OUTPUT :

3. PIPO (PARALLEL IN PARALLEL OUT):

THEORY:
- A Parallel-In Parallel-Out shift register allows parallel data to be loaded simultaneously and to be outputted
simultaneously. This type of shift register is useful in applications where data needs to be stored temporarily and
retrieved without modification of the order.
Operation:
Input: All bits are loaded in parallel into the register.
Process: Data is stored without shifting; the register acts as a buffer.
Output: Data is output in parallel, reflecting the input data exactly.

DATAFLOW MODELLING : SCHEMATIC :

module pipo_b1(
input wire clk, // Clock input
input wire reset, // Reset input
input wire [3:0]parallel_in, //
Parallel input
output reg [3:0] parallel_out //
Parallel output
);
// Internal signals
reg [3:0] reg_data; // Data register
// Register logic
always @(posedge clk or posedge reset) begin
if (reset) begin
reg_data <= 4'b0000; // Reset state
end
else begin
reg_data <= parallel_in; // Load parallel input on clock edge
end
end
// Assign parallel output
always @* begin
parallel_out = reg_data; // Output parallel input on parallel output
end
endmodule

58 | P a g e
TEST BENCH : OUTPUT :
module pipo_tb();
reg clk = 0;
reg reset = 1;
reg [3:0] parallel_in = 4'b0000;
wire [3:0] parallel_out;
pipo_b1 pipo_1 (
.clk(clk),
.reset(reset),
.parallel_in(parallel_in),
.parallel_out(parallel_out)
);
always #5 clk = ~clk;
initial begin
clk = 0;
reset = 1;
parallel_in = 4'b0000;
#10 reset = 0;
end
initial begin
#10 parallel_in = 4'b1010;
#10 parallel_in = 4'b0110;
#10 parallel_in = 4'b1100;
#60;
end
always #1 $display("Time=%t, parallel_out=%b", $time, parallel_out);
endmodule

4. PISO (PARALLEL IN SERIAL OUT) :

THEORY:
- Parallel-In Serial-Out shift registers are used to convert parallel data to serial data. This is useful for data
transmission over a single line communication channel or reducing the number of data lines.
Operation:
Input: Data is loaded into the register simultaneously into all flip-flops.
Process: The loaded data is then shifted out serially through a single output line.
Output: Data exits the register serially.

DATAFLOW MODELLING :
module piso_1(
input clk,
input pi,
input [3:0] data,
output [3:0] q
);
wire x1,x2,x3,x4,x5,x6,x7;
wire d1,d2,d3;
assign d1=((q[0]&pi)|(~pi&data[1]));
assign d2=((q[1]&pi)|(~pi&data[2]));
assign d3=((q[2]&pi)|(~pi&data[3]));
d_ff DFF1(clk,data[0],q[0]);
d_ff DFF2(clk,d1,q[1]);
d_ff DFF3(clk,d2,q[2]);
d_ff DFF4(clk,d3,q[3]);

59 | P a g e
endmodule
module d_ff(input clk,d,output reg q);
always@(posedge clk)
begin
q<=d;
end
endmodule

SCHEMATIC :

TEST BENCH :
module piso_tb();
reg [3:0]data;
reg clk,pi;
wire [3:0]q;
piso_1 piso_2(clk,pi,data,q);
initial begin
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
pi=0;data=4'b0101;
#20 pi=1;
#20 pi=1;
#10 pi=0;
#10 pi=0;
end
endmodule

60 | P a g e
OUTPUT :

CONCLUSION :

All the shift registers have been successfully verified and compiled on the Xilinx verilog.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

61 | P a g e
 LAB 15
COUNTERS
AIM :
Develop Counters in the Xilinx Vivado using structural, dataflow models.

SOFTWARE USED :
XILINX VIVADO

COUNTERS:
Synchronous Counters for VLSI

In digital electronics, counters are essential components used for counting purposes, which include counting
specific events, dividing frequencies, and measuring frequency and time. Synchronous counters are a type of
counter where the clock input is connected to all flip-flops simultaneously. This ensures that the output changes
synchronously with the clock signal, providing more stable and predictable output compared to asynchronous
counters. There are two primary types of synchronous counters: the synchronous up counter and the
synchronous down counter, each having distinct counting sequences.

1. SYNCHRONOUS UP COUNTER :
THEORY:
A synchronous up counter counts upwards, incrementing the count with each clock pulse from zero up to a
maximum value, which depends on the number of flip-flops used.
Structure and Operation
Configuration: Typically consists of a series of flip-flops (JK or D type), each representing a single bit. The
number of flip-flops determines the count range of the counter (e.g., a 4-bit counter can count from 0 to 15).
Counting Mechanism: Each flip-flop is triggered by the clock pulse, causing the counter to increment its value.
Output: The output is taken from the states of the flip-flops, which represent a binary count.
Features
Synchronous Operation: All flip-flops receive the clock signal simultaneously, ensuring precise and predictable
output transitions.
Reset Input: Most designs include a reset input that sets all outputs to zero when activated.
Carry Out: An output that indicates when the counter has reached its maximum count and resets to zero on the
next clock pulse.

DATAFLOW MODELLING :
module upc_1(
input clk,
input rst,output [3:0]counter);
reg [3:0]counter_up;
always@(clk or rst)
begin
if(rst)
counter_up<=4'd0;
else
counter_up<=counter_up+4'd1;
end
assign counter=counter_up;
endmodule

62 | P a g e
SCHEMATIC :

TEST BENCH :
module sync_up_tb();
reg clk,rst;
wire [3:0]counter;
sync_up uut(clk,rst,counter);
initial begin
clk=0;
forever #50 clk=~clk;
end
initial begin
rst=1;
#50 rst=0;
end
endmodule

OUTPUT :

2. SYNCHRONOUS DOWN COUNTER :

THEORY:
- A synchronous down counter counts downwards, decrementing the count with each clock pulse from a set
value down to zero.

Structure and Operation

Configuration: Similar to the up counter, it uses a series of flip-flops connected in a manner that allows the
count to decrement.
Counting Mechanism: The flip-flops are triggered in such a way that each clock pulse causes the binary number
represented by the flip-flops to decrease by one.
Output: The binary number from the flip-flops is outputted as the count.
Features
Directional Count: Specifically designed to count in reverse.
Synchronous Operation: Ensures all parts of the counter count down in unison at each clock pulse.

63 | P a g e
Reset and Load Capability: Typically includes the ability to load a specific starting count value and to reset the
count to this value when needed.

DATAFLOW MODELLING :
module sync_down(
input clk,
input rst,
output [3:0]counter
);
reg [3:0]counter_down;
always@(clk or rst)
begin
if(rst)
counter_down<=4'hf;
else
counter_down<=counter_down - 4'd0;
end
assign counter=counter_down;
endmodule
SCHEMATIC :

TEST BENCH :
module sync_down_tb();
reg clk,rst;
wire [3:0]counter;
sync_down uut(.clk(clk),.rst(rst),.counter(counter));
initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
rst=1;
#50;
rst=0;
end
endmodule

64 | P a g e
OUTPUT :

3. . SYNCHRONOUS UP-DOWN COUNTER:

THEORY:
- A Parallel-In Parallel-Out shift register allows parallel data to be loaded simultaneously and to be outputted
simultaneously. This type of shift register is useful in applications where data needs to be stored temporarily and
retrieved without modification of the order.
Operation:
Input: All bits are loaded in parallel into the register.
Process: Data is stored without shifting; the register acts as a buffer.
Output: Data is output in parallel, reflecting the input data exactly.

DATAFLOW MODELLING :
module sync_updown(
input clk,
input rst,
input up_down,
output [3:0] counter
);
reg [3:0]counter_up_down;
always@(clk or rst)
begin
if(rst)
counter_up_down<=4'h0;
else if(~up_down)
counter_up_down<=counter_up_down + 4'd1;
else
counter_up_down<=counter_up_down - 4'd1;
end
assign counter=counter_up_down;
endmodule

SCHEMATIC :

65 | P a g e
TEST BENCH :
module counter_up_down_tb();
reg clk,rst,up_down;
wire [3:0]counter;

sync_updown uut(clk,rst,up_down,counter);
initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
rst=1;
up_down=0;
#50 rst=0;
#50 up_down=1;
end
endmodule

OUTPUT :

CONCLUSION :

All the COUNTERS have been successfully verified and compiled on the Xilinx verilog.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

66 | P a g e
 LAB 16
PRBS GENERATOR

AIM :
Developing a PRBS Generator in Xilinx Vivado using structural model and test bench and plot the output and
schematic corresponding to it.

SOFTWARE USED :
XILINX VIVADO

1. PRBS GENERATOR:
THEORY :
A Pseudo-Random Binary Sequence (PRBS) generator is a circuit used in digital communications, testing, and
system validation to produce a sequence of binary numbers that appears random but is actually deterministic and
repeatable. PRBS generators are widely utilized in VLSI design to simulate and test the behavior of digital
circuits under various data patterns. They play a crucial role in stress testing, bit error rate (BER) testing, and
modeling of communication channels.
Basic Concept
PRBS is generated using linear feedback shift registers (LFSRs), which are a type of shift register with
feedback. The feedback is typically implemented by using exclusive-or (XOR) gates, and the feedback
configuration determines the sequence's properties, including its length and randomness.
Structure and Operation
Linear Feedback Shift Register (LFSR):
Structure: An LFSR consists of a series of flip-flops connected in a chain, with the output of one flip-flop being
the input of the next. The final output is fed back to the input through a combination of XOR gates.
Feedback Taps: The positions where the feedback is tapped are critical and depend on polynomial coefficients,
defining the characteristics of the PRBS. Commonly used polynomials for feedback taps are based on primitive
polynomials over the binary field, which ensure maximum length sequences.
Sequence Generation:
Initialization: The LFSR must be loaded with a non-zero initial value, often referred to as the seed. This seed
affects the sequence of outputs but not the properties such as length or randomness.
Clocking: With each clock pulse, the contents of the shift register are shifted, and the feedback mechanism
calculates the new bit to be fed into the register.
Output: The output of the LFSR is taken from one of the flip-flops or the XOR output, and it represents the
PRBS.
Characteristics of PRBS:
Maximum Length Sequence: Also known as m-sequences, these are generated when the length of the sequence
before it repeats is 2n −1, where n is the number of flip-flops in the LFSR.
Randomness: The sequences exhibit properties similar to those of truly random sequences, such as balanced
number of ones and zeros, balanced run lengths of ones and zeros, and autocorrelation properties.

BEHAVIORAL MODEL :

module prbs(input clk, input reset, output Out);

reg [7:0] shift_reg;
wire feedback = (shift_reg[7]^shift_reg[6]);
always @(posedge clk or posedge reset) begin
if (reset) begin
shift_reg <= 8'b00000001;
end
else begin
shift_reg <= {shift_reg[6:0], feedback};
end

67 | P a g e
 end
assign Out = shift_reg[0];
endmodule

SCHEMATIC :

TEST BENCH :
module prbs_tb();
reg clk, reset;
wire Out ;
prbs prbs_1(.clk(clk), .reset(reset), .Out(Out));
initial
begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
reset = 1;
#10 reset = 0;
#1000;
end
endmodule

OUTPUT :

CONCLUSION :
We have successfully completed the PRBS GENERATOR using Verilog behavioral modeling in Xilinx Verilog,
demonstrating effective implementation and execution.

Name : V SAI CHARAN GUPTA

Branch : ETC Id : B221065

68 | P a g e