1. What is VHDL?

ANS: VHDL stands for very high-speed integrated circuit hardware description language. Which is one
of the programming languages used to model a digital system by dataflow, behavioral and structural style of
modeling.

2. What is library in VHDL?

Ans: Library is the collection of compile VHDL design units i.e. entity, architecture, configuration
package and package.

Use statement can access different component inside the library

Syntax of use statement

Use library_name.package_name.item_name;

Eg. Use ieee.std_logic_1164.all;

3. What are the basic elements of VHDL language?

Any vhdl code is a combination of design units, objects, type & operators linked together in a logical
manner to produce the desired output.

In VHDL an entity is used to describe a hardware module.

An entity can be described using,

1. Entity declaration.

2. Architecture.

3. Configuration

4. Package declaration.

5. Package body.

4. What is entity declaration in VHDL?

Entity declaration:It defines the names, input output signals and modes of a hardware module. It describe the
interface of the design to its external environment. It can be use as a component in other entity after being
compile into a default library work

Syntax: entity entity_name is

Port declaration;

end entity_name;

Ex: entity andGate is

port(A : in std_logic;
B : in std_logic;
Y : out std_logic);

end andGate;
 5. what is port in VHDL?
⚫ Ports are interface through which an entity can communicates with its
environments.
⚫ Port declaration defines the name, type, direction and possible defaults value forthe signal. Each
port has a type i.e. bit_type, std_logic type.
⚫ Each port has a direction i.e. IN, OUT, INOUT,BUFFER
IN — Input: It indicates the input port whose values can read but cannot assignany values i.e. c <= a
OUT — Output : It indicates the output port to which value can only be assignbut not read.

INOUT – It indicate bidirectional port whose value can be read and also assign
BUFFER – It is an output port with read capability. It is not a bidirectional port i.e. port can be read and
write. It has only one source.

For ex. For AND gate

Library ieee;
Use ieee.std_logic_1164.all;

Entity and_2 is

Port ( a,b:in std_logic;

Z : out std_logic);

End and_2;
6. What is architecture in VHDL?how to write an architecture in vhdl?
Architecture body contains the internal description of the entity. It describes the functioning and the
structure of the circuit. Architecture always present with an entity i.e. without entity architecture is
not possible. Single entity can have
multiple architecture. Architecture can be used to described a design at different level of abstraction
like gate level or behavioral level
Architecture contains only concurrent statement. Process is only
concurrent statement that contains sequential statement inside it.
Architecture can be describe using structural, data flow, behavioral or mixedstyle

⚫ Syntax:
⚫ Architecture architecture_name of entity_name is
⚫ [ declaration ]
⚫ Begin
◦ [ statements ] End
architecture_name;
There are 4 different modeling style use in architecture body
1. As a set of interconnection ports ( to represent the structure)
2. As a set of concurrent assignment statements ( to represents data flow)
3. As a set of sequential statements ( to represents behavioral )
4. as the combination of above three ( mixed style)For ex.
Library ieee;
Use ieee.std_logic_1164.all;Entity
and_2 is
 Port ( a,b : in std_logic;z :
out std_logic);
End and_2;
Architecture Df of and_2 isBegin
Z <= a and b;
End DF;
7. what is Configuration in VHDL? how to write it in VHDL?
⚫ If an entity contains many architectures and any one of the possible architecture
binding with its entity is done using configuration. It is used to bind the architecture body to its
entity and a component with an entity.
⚫ Syntax:
🞄 Configuration configuration_name of entity_name is
🞄 For architecture_name
🞄 End for;
🞄 End configuration_name;
For example
Configuration DEC_CONFIG of DECODER 2x4 isFor
DEC_DATA FLOW
End for;
End DEC_CONFIG;
8. What is package in VHDL?

⚫ Package is a collection of commonly used sub-program, data types, constant,function and

procedure
⚫ Syntax:
◦ Package package_name is
◦ Declaration; End
package_name;Package
Body
It contain the implementation details of either function or a sub-program. Package body cannot be
written without a package. It is used to store private declaration that should not be visible.
Syntax:
Package body package_name is
Declaration
Sub program body; End
package_name;

9. what are Different modeling style in VHDL:

The internal working of an entity can be defined using different modeling styles inside architecture
body. They are

Behavioral modeling
Data flow modeling

Structural modeling

Mixed Style

10. what is behavioral modeling in VHDL?

Behavioral Style:
No structure
Sometime called high level description
Set of assignment statement to represent a behavior.
It consists of sequential statement of VHDL under the process statement.
For Ex.: NAND Gate
library ieee;
Use ieee.std_logic_1164.all;Entity
nand_2 is
Port ( a,b : in std_logic; y : out std_logic);end
nand_2;
Architecture beh of nand_2 isBegin
Process (a,b)
Begin
If (a = ‘1’ and b =‘1’) then
Y <= ‘0’;
Else
Y <= ‘1’;
End if;
End process;
End beh;

11. what is data flow style in VHDL?

Data Flow Style:

All data paths shown plus all control signal
Data flow architecture is executed using concurrent statement rather than process & sequential
statement. The order of concurrent statement does not matter because concurrent statement are
executed concurrently or simultaneously.
For Ex: half Adder
library ieee;
Use ieee.std_logic _1164.all;Entity
HA is
 Port ( ai, bi : in std_logic;S,C :
out std_logic);
End HA;
Architecture DF of HA isBegin
S <= ai XOR bi;

C <= ai and bi;

End DF;

12. what is structural style in VHDL?

Interconnection of already designed components

Structural architecture is executed using concurrent statement like component declaration and component
installation.
13. what is Port map?
Port map is a interconnection with current entity port & componentdeclaration port. It is used in
structural modeling style.
There are two types of port map
i) Positional port map
ii) Name port map
Positional Port map : In positional port map actual parameters are associated sequentially i.e.
actual1, actual2 ...................................................... , actualn.
Name port map : In name port map we have to specify association between each pair of formal &
actual parameter. i.e. formal1 => actual1, formal2=> actual2, formal n => actual n

14. what is data object in VHDL?

An object contains a value of specified type i.e. it stores information. Each object has a type and class
E.g. signal A : std_logic;
There are four data objects used in VHDL
a. Constant
b. Variable
c. Signal
d. File

15. what is constant?

An object of constant class can hold a single value of particular type.

Value can assign to constant before a simulation start and value can not bechange during the
course of simulation.
Constant can assign a value once in a program, the value remains costant till theend of program.
Syntax:
Constant constant_name: constant_type:= value;For Ex.;
Constant Pi : real := 3.14;
Constant RISE_TIME: TIME: = 10ns;
16. what is variable?

An object of variable class can hold a single value of given type. The different values can be assigned
to variable at different time using variable assignment statement. Variable assignment is done using
symbol “:=”.
Syntax:
Variable variable_name: variable_type (range):= [initial value]For Ex:
Variable count: std_logic_vector (3 downto 0):= “0000”;

17. what is Signal (Set of values) in VHDL?

An object belongs to the signal class can hold a list of values which include current value of a signal
and set of possible feature value that will be appeared on a signal. The feature can be assigned to a
signal using signal assignment symbol
i.e. “<=”.
Syntax:
Signal signal_name: signal_type (range):= [initial value] For Ex:
Signal a : std_logic_vector (3 downto 0):= “0000”;
18. what is File (Sequence of value)?
An object belong to class file contain a sequence of value of a specified type. Value can be read or
write in the file using read operation or write operation respectively.
Syntax:
File file_name: file_type_name;For ex:
File PAT1, PAT2: std_logic_file;

19.what is data type in VHDL?

VHDL data types are groups into four major categories
Scalar Type: values belonging to this type appear in sequential order. i.e. valuesof this type are
ordered & relational operation can used on them.
There are four different kind of scalar type
A) Enumeration type
B) Integer type
C) Floating type or (Real Type)
D) Physical type
Enumeration Type: enumeration type declaration defines a type that has a set ofuser defined values
consisting of identifiers and character literals.
Syntax: type type_name is (IDENTIFIER LIST);
Ex: i) type STATE_TABLE is (Reset, S0, S1, S2, FINAL);
ii) type colour is (violet,red,blue,green);
Integer Type:
It contain mathematical integer. An integer type defines a type whose set ofvalues falls with in
a specified integer range –(231 -1) to +(231-1)
Type index is range 0 to 15;
For Ex.: 3,1,-2,6E2,0,56342,98_71_28…..
It defines a value with real number. They can be either positive or negativewhich contain a
decimal point.
Example
Type real_data is range 0.0 to 31.9;
 For Ex: 3.23,-1.7859, 4.76E20, 0.0, 0.0002

Physical Type:

It represents physical quantities such as distance, time, length, voltage, current etc. a physical data
type provides for a base unit & successive units are definedin terms of unit.

Composite Type:

A composite type represent collection of values. There are two types-Array Type:- It
contain many elements of same type
Record Type:- It contain many elements of different type Array are
further two types-
Undimensional or one dimensional array:
type array_name is array (index range) of element type;For Ex: type
byte is array ( 7 downto 0) of std_logic; Multidimensional array:-
type array_name is array (index range1, index range2) of element type;For Ex:
type memory is array ( 3 downto 0, 7 downto 0) of std_logic;
Access Type:

Value belonging to access type are pointers to a dynamic allocated object ofsome other type.
They are similar to pointers in pascal & C-language.
Example:
Type ptr is access module;
In this example declares ptr of access type whose values are addresses of module
File Type:
Object of file type represents files in the host environment. They provide amechanism by
which a VHDL design communicates with the host environment. Examples
Type vector is file of BIT_VECTOR;Type
tom is file of BIT_VECTOR;

20. what is different statement in VHDL?

There are two types of statements

Concurrent statement
Sequential statement
Concurrent statement:
They are present in architecture are executed simultaneously or concurrently. In concurrent statement
there order of writing is not important. They can used for data flow, behavioral & structural
architecture.
🞄 Process is only concurrent statement which can contain sequential statement. If architecture contain
more than one
 Process, then all process is executed simultaneously by simulator.There are two
types of concurrent statement.
When-else Statement and With Select Statement
WHEN-ELSE (Conditional signal assignment statement):
⚫ Syntax:
⚫ Signal_name <= expression 1 when condition 1 else
expression 2 when condition 2 else
.
.
expression n;
This statement has assignment in architecture to one target for multiple condition or expression. This
statement has assign a value to output port based on priority of condition.
Conditional signal assignment statement select different values based on specified possibly different
condition. It is like an “IF’ statement in sequential statement.
WITH-SELECT (Selected signal assignment statement):
⚫ Syntax:
⚫ With expression select
⚫ Out_signal <= expression 1 when choice 1,
expression 2 when choice 2,
.
.
expression n when others;
In this statement the no. of choices or conditions are limited whereas when-else statement the choices
or conditions are unlimited. It is similar to case statement in sequential statement.
Selected signal assignment statement select different values for output signal based on the value of
select expression.
Examples
Write VHDL code for 4:1 mux using when-else statement library ieee;
Use ieee.std_logic_1164.all;Entity
mux_4_1 is
Port(I: in std_logic_vector(3 downto 0);S : in
std_logoc_vector(1 downto 0);
Z : out std_logic);end
mux_4_1;
Architecture beh of mux_4_1 isBegin
Z <= I(0) when S = “00” else
 I(1) when S = “01” else I(2)
when S = “10” else I(3);
End beh;
Examples
Write VHDL code for 4:1 mux using with-select statement library ieee;
Use ieee.std_logic_1164.all;Entity
mux_4_1 is
Port(I: in std_logic_vector(3 downto 0);S : in
std_logoc_vector(1 downto 0);
Z : out std_logic);end
mux_4_1;
Architecture beh of mux_4_1 isBegin
With S select
Z <= I(0) when “00”,
I(1) when “01” ,
I(2) when “10” , I(3)
when others;
End beh;
Sequential Statements:
A set of VHDL statement that executes in sequence is called sequentialstatements.
Sequential statements can appear only inside the process and subprogram. Morethan one process can
be include in the architecture.
As the process statement is concurrent statement, all the process inside thearchitecture are executed
concurrently.
Process Statement:
Process is the heart of behavioral or sequential category. Process statementappear inside an
architecture body & it enclose with other statements within it
i.e. if statement, case statement, loop statement etc appear inside a process.Syntax:
[label] : Process [(sensitivity list)]
[variable declaration]
Begin
Sequential statements i.e. Signal
assignment statement Variable
assignment statementWait statement
Case statement
Loop statement End
process [label];If
Statement:

Syntax:
if condition then
sequential statement;elsif
condition then sequential
statement;else
sequential statement;end
if;
If statement select sequential statement for execution based on the value ofcondition.
It is similar to when-else statement in the concurrent statement. If statement is executed by checking
each condition sequentially untill the first true condition is found, then set of sequential statement
associated with this condition is executed.Case Statement:
Syntax:
Case expression is
When choice => sequential statement;….branch1 When choice
=> sequential statement;….branch2
.
.
When others => sequential statement;….last branch
The expression value may be discrete type or one dimensional array type. The choices may be express
as a single value, as a range of value or by using other clause (when others)
The others clause can be used as a choice to catch all values. And if present it must be last branch in
the case statement.