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Microprocess Architecture Real Mode Addressing

The document discusses real mode memory addressing in 8086 and later microprocessors. Real mode allows addressing the first 1MB of memory using segment registers and offsets. Segment registers define starting addresses for 64KB segments, and offsets select locations within segments.

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4 views

Microprocess Architecture Real Mode Addressing

The document discusses real mode memory addressing in 8086 and later microprocessors. Real mode allows addressing the first 1MB of memory using segment registers and offsets. Segment registers define starting addresses for 64KB segments, and offsets select locations within segments.

Uploaded by

delasernastebojan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Real Mode Memory Addressing

Engr. Feln Lily F. Canonigo, MEP

1
Programming Model

Programming Model of the 8086 through P4 is considered


program visible.

Program visible – Registers are used during application


programming and are specified in the instructions.

2
8 bit
names
32 BIT 16 bit
NAMES names
EAX AH AX AL ACCUMULATOR

EBX BH BX BL BASE INDEX

ECX CH CX CL COUNT

EDX DH DX DL DATA

ESP SP STACK POINTER

EBP BP BASE POINTER

EDI DI DESTINATION INDEX

ESI SI SOURCE INDEX

3
EIP IP ACCUMULATOR

EFLAGS FLAGS FLAGS

CS CODE
DS DATA
ES EXTRA
SS STACK
FS
GS

• The shaded boxes exist only from 80386 through P4


• FS and GS registers have no special names.
4
Multipurpose Registers
EAX (ACCUMULATOR)
EBX (BASE INDEX)
ECX (count)
EDX (data)
EBP(Base Pointer)
EDI (Destination index)
ESI (Source index)
EIP (Instruction Pointer)

5
Special – Purpose Registers
EIP (Instruction Pointer)
ESP (Stack Pointer)
EFLAGS

6
FLAGS
C (Carry) RF(resume)
P (Parity) NT (nested task)
A (Auxiliary carry) VM (virtual mode)
Z (Zero) AC (alignment check)
S (Sign) VIF (Virtual Interrupt flag)
T (Trap) ID (identification)
I (Interrupt)
D (Direction)
O (overflow)
IOPL (I/O Privilege level)
7
Segment Register
CS (Code)
DS (Data)
ES (extra)
SS (Stack)
FS and GS

8
Real Mode Memory Addressing
80286 and above operate in either the read or protected mode.
Only the 8086 and 8088 operate exclusively in the real mode.

Real mode operation allows the microprocessor to address


only the first 1Mbyte of memory space called either real
memory or conventional memory. 00000H-FFFFFH

9
Segment and Offsets
Combination of a segment address and an offset address
access a memory location in the real mode.
The segment address located within one segment register
defines the beginning address of any 64K-byte memory
segment.
The offset address is also held in a register and selects any
location within the 64K byte memory segment.

10
FFFFF

1FFFF

1F000 Offset = F000

Segment Register
10000 1000

Offset is also sometimes referred to as


00000 displacement 11
The segment register in the previous example contained
1000H yet it addresses a segment starting at location 10000H.

In real mode every value in the segment register is appended


with a 0H on its rightmost end.

Because of the append, real mode segments can begin only at


16-byte boundary in the memory system. This 16-byte
boundary is called a paragraph.

The ending address is found by adding FFFFH.

12
Example
What is the ending address of the segment, whose address
is defined as 3000H in the segment register?
Solution:
30000H starting/first address (appended 0)
+ FFFFH
3FFFFH ending address

13
Example
If the segment address is 1000H and the offset address
2000H, what is the address of the memory location?
Solution:
10000H starting/first address (appended 0)
+ 2000H offset address
12000H memory location address

NOTE: the problem above can be written as 1000:2000

14
Example
What is the actual memory location of 1234:300?

Solution:
12340H starting/first address (appended 0)
+ 300H offset address
12640H memory location address

15
Segment and Offset Address
Combinations (for 16-bit)
Segment Offset
CS IP
SS SP or BP
DS BX, DI, SI
ES DI

NOTE: Offset register should not be more


than FFFFH, cause system to halt and
indicate an addressing error.
16
Segment and Offset Address
Combinations (for 32-bit)
Segment Offset
CS EIP
SS ESP or EBP
DS EAX, EBX, ECX, EDX, ESI, EDI
ES EDI
FS No default
GS No default

17
Boardwork: (3 problems)

Find the memory address of the next


instruction executed by the microprocessor,
when operated in the real mode.

1. 2300H:1A00H
2. SI = 1002H and DS = 2000H
3. SP = 3A00H and SS = 2900H

18

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