8086 Microprocessor

Architecture of 8086
Memory segmentation,
Signal Description,
Addressing modes,
MODULE I
⚫ Architecture of 8086

⚫ Memory segmentation
⚫ Signal description

⚫ Addressing modes
MODULE 1

MICROPROCESSOR
⚫A single chip computer
⚫ Device which has data processing capability
⚫ Program controlled semiconductor device (IC)
which fetches (from memory), decodes and
executes instructions.
⚫ It is used as CPU (Central Processing Unit) in
computers.
⚫ Microcontroller???
◦ P + RAM + RO M + I/O ports + Timer
◦ Less bulkier than P
MODULE 1
Fifth Generation Pentium
32-bit P
GENERATION Superscalar architecture

Fourth Generation
Third Generation During 1980s
During 1978 Low power version of HMOS technology
HMOS technology  Faster speed, Higher (HCMOS)
packing density 32 bit processors
16 bit processors  40/ 48/ 64 pins Physical memory space 224 bytes = 16 Mb
Easier to program Virtual memory space 240 bytes = 1 Tb
Dynamically relatable programs Floating point hardware
Processor has multiply/ divide arithmetic Supports increased number of addressing
hardware modes
More powerful interrupt handling
capabilities Intel 80386, 80486
Flexible I/O port addressing Second Generation
During 1973
Intel 8086 (16 bit processor) NMOS technology  Faster speed, Higher
density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors  16 pins nesting
8 and 16 bit processors  40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are
multiplexed Intel 8085 (8 bit processor)
MODULE 1

8086- Overview
⚫ First 16-bit processor released by INTEL
in 1978
⚫ Powerful instruction set
⚫ 20-bit addressing capability
⚫ Powerful set of registers- general purpose
and special purpose registers
HOMEW ORK
⚫ DRAWTHE INTERNAL BLOCK
DIAGRAM OF 8086 (detailed)
◦ Refer Lyla B Das., The X86 Microprocessors
Architecture,Programming and Interfacing
MODULE 1

8086 A R C H ITECTURE
MODULE 1

ARCHITECTURE
MODULE 1

EXECUTION UNIT
EU decodes and executes
instructions.

A decoder in the EU control

system translates
instructions.
16-bit ALU for
performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
MODULE 1

EXECUTION UNIT

Accumulator Register (AX)

Consists of two 8-bit registers AL and AH, which can

be combined together and used as a 16-bit registerA X .

AL in this case contains the low order byte of the

word, andAH contains the high-order byte.

The I/O instructions use the A X or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

Multiplication and Division instructions also use the A X

or AL as implicit register for one of the operands.
MODULE 1

EXECUTION UNIT

Base Register (BX)

Consists of two 8-bit registers BL and BH, which can be

combined together and used as a 16-bit register BX.

BL in this case contains the low-order byte of the word, and

BH contains the high-order byte.

This is the only general purpose register whose contents

can be used for addressing the 8086 memory.

All memory references utilizing this register content for

addressing use DS as the default segment register.
MODULE 1

EXECUTION UNIT

Counter Register (CX)

Consists of two 8-bit registers CL and CH, which

can be combined together and used as a 16-bit
register CX.

When combined, CL register contains the low

order byte of the word, and CH contains the high-
order byte.

Instructions such as SHIFT, ROTATE and LOOP use

the contents of C X as a counter.
MODULE 1

EXECUTION UNIT

Data Register (DX)

Consists of two 8-bit registers DL and DH, which

can be combined together and used as a 16-bit
register DX.

When combined, DL register contains the low

order byte of the word, and D H contains the high-
order byte.

Used to hold the high 16-bit result (data) in 16 X

16 multiplication or the high 16-bit dividend (data)
before a 32 ÷ 16 division and the 16-bit remainder
after division.
MODULE 1

EXECUTION UNIT

Stack Pointer (SP) and Base Pointer (BP)

SP and BP are used to access data in the stack segment.
SP always points to the top of the stack
SP contents are automatically updated (incremented/
decremented) due to execution of a POP or PUSH
instruction.

BP can point to any location in the stack

MODULE 1

EXECUTION UNIT

Source Index (SI) and Destination Index (DI)

Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in
order to distinguish between the source and
destination addresses.
MODULE 1

EXECUTION UNIT
Carry Flag
Flag Register Auxiliary Carry Flag This flag is set, when there is a
This is set, if there is a carry from the carry out of MSB in case of
lowest nibble,i.e,bit B3 during addition,or addition or a borrow in case
Sign Flag borrow for the lowest nibble i.e., B3 of subtraction.
This flag is set, when the during subtraction.. Parity Flag
result of computation is This flag is set to 1,if the lower
negative Zero flag byte of the result contains even
This flag is set, when the result number of 1’s ;for odd number
of computation is zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Over flow Flag Trap Flag

This flag is set,if an overflow occurs, i.e,if the result of a If this flag is set,the processor
signed operation is large enough to accommodate in a enters the single step execution
destination register.The result isDirection Flag7-bits in size in
of more than ode by generating internal
ca This is used by string manipulation instructions. If this flag bit is ‘0’,them errupts after the execution of
string
c se of 8-bitissigned
processed beginning
operation and from
morethe lowest
than address
15-bits in the highestint
in sizeto Interrupt Flag
each instruction
ase of address, i.e.,auto
16-bit sign incrementing
operations, then themode. Otherwise,
overflow the string is
will be set. auses the 8086 to recognize
processed from the highest address towards the lowest address, i.e., Cernal mask interrupts;clearing
auto decrementing mode. ext
MODULE 1

BUS INTERFACE UNIT

Dedicated Adder to generate

20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

DEPARTMENT OSeFgm
EeCnEt ,Registers >>
ARYANET INSTITUTE O FTECHN O LOGY
MODULE 1

BUS INTERFACE UNIT

ADDRESS GENERATION:
◦ 20-bit address of a byte is called its physical address
◦ It is specified as a logical address which is in the form of
two 16-bit numbers in the format base address:offset
◦ Segment register contains 16-bit base(segment) address
◦ Pointer register or index register contains offset address
◦ Segment address left-shifted 4 times + offset address=
physical address
MODULE 1

BUS INTERFACE UNIT

ADDRESS GENERATION
⚫ Eg:physical address=155A5h (20 bit)
⚫ Segment address=1005h (16 bit)
0001 0000 0000 0101
⚫ Offset=5555h (16 bit) Segment addr left
shifted with
0001 0000 0000 0101 0000 appended zeros

0101 0101 0101 0101 Offset

0001 0101 0101 1010 0101

1 5 5 A 5 Physical address
MODULE 1

ADDRESS GENERATION

O ffset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)

MODULE 1

BUS INTERFACE UNIT

MEMORY SEGMENTATION
⚫ 8086 has 20-bit address bus
⚫ Can access 220 address locations=1 MB
⚫ Physical memory address ranging from 00000h to FFFFFh
⚫ Total memory size divided into 16 segments of 64KB each-
segmentation
⚫ 4 types of segments- data,code, extra & stack segments
⚫ Data is stored in data segment
⚫ Program code in code segment
⚫ Extra segment is another type of data segment used in a
special way
⚫ Stack segment is an area of memory which functions and is
accessed differently from the other 3 segments
MODULE 1

BUS INTERFACE UNIT

MEMORY SEGMENTATION
⚫ General concerns:
◦ Segment addresses are divisible by 16
◦ Segments can be overlapping- more than 1 logical address for the
same physical address
◦ There can be many segments with same base address but the offsets
within the segment will have to be taken care of to prevent
overwriting of data.
◦ A segment can have a maximum size of 64KB
◦ A program need not have all 4 segments, but it will have at least the
code segment
◦ The address used in instructions are called logical addresses and are
translated by the BIU to physical address
MODULE 1

BUS INTERFACE UNIT

MEMORY SEGMENTATION

⚫ Advantages
◦ It allows address registers to have the same size
as the data registers while allowing the use of 20-
bit physical address
◦ All addresses in memory are re-locatable
◦ Allows placing of code, data and stack portions of
the same program in different parts(segments) of
memory, for data and code protection
MODULE 1

BUS INTERFACE UNIT

Code Segment Register
16-bit
CS contains the base or start of the current code
segment; IP contains the distance or offset from this

address to the next instruction byte to be fetched.

BIU computes the 20-bit physical address by logically
shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.

This 20-bit address is then placed on the address bus and

the instruction byte is fetched.
Thus the logical address for an instruction byte is of the
form CS:IP
MODULE 1

BUS INTERFACE UNIT

Data Segment Register

16-bit
DS points to the current data segment; operands
for most instructions are fetched from this segment.
The 16-bit contents of the Source Index (SI) or
Destination Index (DI) or a 16-bit displacement are
used as offset for computing the 20-bit physical
address.
MODULE 1

BUS INTERFACE UNIT

Stack Segment Register
Stack in 8086 is LIFO stack
16-bit stack pointer(SP) points to the top of the
stack
Base address(16 bit) is available in stack segment
register(SS)
Logical address of a stack can be of the form SS:SP
or SS:BP
BIU computes the 20-bit physical address by
logically shifting the contents of SS 4-bits to the left
and then adding the 16-bit contents of SP.
MODULE 1

BUS INTERFACE UNIT

Extra Segment Register

16-bit

Points to the extra segment in which data (in excess

of 64K pointed to by the DS) is stored.
String instructions use the ES and DI to determine
the 20-bit physical address for the destination.
MODULE 1

BUS INTERFACE UNIT

Instruction Pointer
16-bit

Always points to the next instruction to be

executed within the currently executing code
segment.
So, this register contains the 16-bit offset address
pointing to the next instruction code within the
64Kb of the code segment area.

Its content is automatically incremented as the

execution of the next instruction takes place.
MODULE 1

BUS INTERFACE UNIT

Instruction queue

A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction code
are pre fetched from the
memory ahead of time.

This is done in order to

speed up the execution by
overlapping instruction
fetch with execution.

This mechanism is known

as pipelining.
ASSIGNMENT 1
⚫ INSTRUCTION SET OF 8086
◦ Data transfer instructions
◦ Branch instructions
◦ Arithmetic instructions
◦ Logical instructions
◦ Shift and rotate instructions
◦ String instructions
HOMEW ORK
⚫ Draw the pin diagram of 8086
MODULE 1

HARDWARE
SPECIFICAT I O N
 PINS A N D SIGNALS
C O M M O N SIGNALS
AD 0 -AD 15 (Bidirectional)
Address/Data bus

Low order address bus; these are multiplexed

with data.

When A D lines are used to transmit memory

address the symbol A is used instead of AD, for
exampleA 0-A 15.

When data are transmitted over A D lines the

symbol D is used in place of AD, for example D0-
D 7,D 8-D 15 or D 0-D 15.

A 16/S3,A 17/S4,A 18/S5,A 19/S6

High order address bus. These are multiplexed

with status signals
 PINS A N D SIGNALS
C O M M O N SIGNALS B H E (Active Low)/S7 (Output)
Bus High Enable/Status
It is used to enable data onto the most
significant half of data bus, D8-D15. 8-bit
device connected to upper half of the data
bus use BHE (Active Low) signal. It is
multiplexed with status signal S7.

MN/ M X
MINIMUM /MAXIMUM
This pin signal indicates what mode the
processor is to operate in.

R D (Read) (Active Low)

The signal is used for read operation.
It is an output signal.
It is active when low.
 PINS A N D SIGNALS
C O M M O N SIGNALS TEST
TEST Input is tested by the ‘WAIT’ instruction.

8086 will enter a wait state after execution of the

WAIT instruction and will resume execution only
when the TEST is made low by an active
hardware.

This is used to synchronize an external activity to

the processor internal operation.

READY
This is the acknowledgement from the slow
device or memory that they have completed the
data transfer.

The signal made available by the devices is

synchronized by the 8284A clock generator to
provide ready input to the 8086.

The signal is active high.

 PINS A N D SIGNALS
C O M M O N SIGNALS RESET (Input)

Causes the processor to immediately terminate

its present activity.

The signal must be active HIGH for at least four

clock cycles.
CLK(Clock)

The clock input provides the basic timing for

processor operation and bus control activity. Its
an asymmetric square wave with 33% duty cycle.
INTR( Interrupt Request)

This is a triggered input. Used by an external

device to interrupt 8086, which responds only if IF
flag is 1.
NMI(Non Maskable Interrupt)
High priority interrupt. Request is accepted no
matter what IF is.
MODULE 1

PINS A N D SIGNALS
MIN/MAX MODE SIGNALS The 8086 microprocessor can work in two modes
of operations :Minimum mode and Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any co-
processors and can not be used for multiprocessor
systems.

In the maximum mode the 8086 can work in multi-

processor or co-processor configuration.

Minimum or maximum mode operations are

decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in minimum

mode otherwise it operates in Maximum mode.
MODULE 1

PINS A N D SIGNALS
MINIMUM MODE SIGNALS
PINS 24 TO 31

DT/R (Data Transmit/ Receive) Output signal from the

processor to control the direction of data
flow through the data transceivers

DEN (Data Enable) Output signal from the processor used

as output enable for the transceivers
ALE (Address Latch Enable) Used to demultiplex the
address and data lines using external latches
M/IO Used to differentiate memory access and I/O
access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.

WR Write control signal;asserted low Whenever

processor writes data to memory or I/O port

INTA (Interrupt Acknowledge)When the interrupt request

is accepted by the processor, the output is low
on this line.
MODULE 1

PINS A N D SIGNALS
MINIMUM MODE SIGNALS
PINS 24 TO 31

HOLD Input signal to the processor from the bus

masters
as a request to grant the control of the bus.

Usually used by the DMA controller to get

the control of the bus.
HLDA (Hold Acknowledge) Acknowledge signal by the
processor to the bus master requesting the control
of the bus through HOLD.

The acknowledge is asserted high,

when the processor accepts HOLD.
MODULE 1

PINS A N D SIGNALS
MAXIMUM MODE SIGNALS
PINS 24 TO 31 REASSIGNED

𝑆0 , 𝑆1 , 𝑆2 Status signals; used by the 8086 bus

controller to generate bus timing and control
signals.These are decoded as shown.
MODULE 1

PINS A N D SIGNALS
MAXIMUM MODE SIGNALS
PINS 24 TO 31 REASSIGNED

𝑄𝑆0 , 𝑄𝑆1 (Queue Status) The processor provides the status of

queue in these lines.

The queue status can be used by external device to

track the internal status of the queue in 8086.

The output on QS 0 and QS 1 can be interpreted as

shown in the table.
MODULE 1

PINS A N D SIGNALS
MAXIMUM MODE SIGNALS
PINS 24 TO 31 REASSIGNED

RQ/ (Bus Request/ Bus Grant) These requests are used by

GT0, other local bus masters to force the processor to
RQ/ GT1 release the local bus at the end of the processor’s
current bus cycle.

These pins are bidirectional.

The request on GT0 will have higher priority than

GT1

LOCK An output signal activatedby the LOCK

prefix instruction.

Remains active until the completion of

the instruction prefixed by LOCK.

The 8086 output low on the LOCK pin

while executing an instruction prefixed
by LOCK to
prevent other bus masters from gaining control of
MODULE 1

ADDRESSING MODES
 ADDRESSING MODES
Every instruction of a program has to operate on a data.
The different ways in which a source operand is denoted
in an instruction are known as addressing modes.

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Indexed Addressing

6. Based Indexed Addressing

7. Relative based indexed Addressing

8. Implied Addressing
 ADDRESSING MODES
The instruction will specify the name of the
1. Register Addressing register which holds the data to be operated by
the instruction.
2. Immediate Addressing
Example:
3. Direct Addressing
MOV CL, DH
4. Register Indirect Addressing
The content of 8-bit register DH is moved to
5. Indexed Addressing another 8-bit register CL

6. Based Indexed Addressing (CL)  (DH)

7. Relative based indexed Addressing

8. Implied Addressing
 ADDRESSING MODES

In immediate addressing mode, an 8-bit or 16-bit

data is specified as part of the instruction
1. Register Addressing
Example:
2. Immediate Addressing
MOV DL, 08H
3. Direct Addressing
The 8-bit data (08H) given in the instruction is
4. Register Indirect Addressing moved to DL

5. Indexed Addressing (DL)  08H

6. Based Indexed Addressing

MOV AX, 0A9FH
7. Relative based indexed Addressing
The 16-bit data (0A9FH) given in the instruction is
8. Implied Addressing moved to AX register

(AX)  0A9FH
 ADDRESSING MODES

Here, the effective address of the memory

1. Register Addressing location at which the data operand is stored is
given in the instruction.
2. Immediate Addressing
The effective address is just a 16-bit number
3. Direct Addressing written directly in the instruction.

4. Register Indirect Addressing Example:

5. Indexed Addressing MOV BX, [1354H]

MOV BL, [0400H]
6. Based Indexed Addressing
The square brackets around the 1354H denotes
7. Relative based indexed the contents of the memory location. When
Addressing executed, this instruction will copy the contents of
the memory location into BX register.
8. Implied Addressing
This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.
 ADDRESSING MODES
In Register indirect addressing, name of the
register which holds the effective address (EA)
will be specified in the instruction.
1. Register Addressing
Registers used to hold EA are any of the following
2. Immediate Addressing
registers:
3. Direct Addressing
BX, BP, DI and SI.
4. Register Indirect Addressing
Content of the DS register is used for base
address calculation.
5. Indexed Addressing
Example:
6. Based Indexed Addressing
Note : Register/ memory
MOV CX, [BX] enclosed in brackets refer to
7. Relative based indexed content of register/ memory
Addressing
Operations:
8. Implied Addressing
EA = (BX)
BA = (DS) x 1610
MA = BA + EA

(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA +1)
 ADDRESSING MODES
SI or DI register is used to hold an index value for
memory.

1. Register Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.
2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Indexed Addressing Example:

6. Based Indexed Addressing MOV CX, [SI]

7. Relative based indexed Addressing Operations:

8. Implied Addressing offset = (SI)

BA = (DS) x 1610
MA = BA + offset

(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA + 1)
 ADDRESSING MODES
In Based Index Addressing, the effective address
is computed from the sum of a base register (BX
or BP) and an index register (SI or DI).

1. Register Addressing Example:

2. Immediate Addressing
MOV DX, [BX + SI]
3. Direct Addressing
Operations:
4. Register Indirect Addressing
000AH  0AH (Sign extended)
5. Indexed Addressing
EA = (BX) + (SI)
6. Based Indexed Addressing BA = (DS) x 1610
MA = BA + EA
7. Relative based indexed Addressing
(DX)  (MA) or,
8. Implied Addressing
(DL)  (MA)
(DH)  (MA + 1)
 ADDRESSING MODES
In relative based Indexed Addressing, the
effective address is computed from the sum of a
base register (BX or BP), an index register (SI or
1. Register Addressing DI) and a displacement.

2. Immediate Addressing Example:

3. Direct Addressing MOV DX, [BX + SI + 0AH]

4. Register Indirect Addressing Operations:

5. Indexed Addressing 000AH  0AH (Sign extended)

6. Based Indexed Addressing EA = (BX) + (SI) + 000AH

BA = (DS) x 1610
7. Relative based indexed Addressing MA = BA + EA

8. Implied Addressing (DX)  (MA) or,

(DL)  (MA)
(DH)  (MA + 1)
 ADDRESSING MODES

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

Instructions using this mode have no
5. Indexed Addressing operands. The instruction itself will specify
the data to be operated by the instruction.
6. Based Indexed Addressing
Example: CLC
7. Relative based indexed Addressing
This clears the carry flag to zero.
8. Implied Addressing