2023-24

Learning Science

MCS-012
Solved Assignment
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 MCS-012 Solved Assignment 2023-2024 (July-January)

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Course Code MCS-012

Course Title Computer Organization and Assembly

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Assignment Number BCA (II)/012/Assignment/2023-24

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Maximum Marks 100

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Weightage 25%

31st October, 2023 (For July Session)

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Last Date of Submission
30 th April, 2024 (For January Session)

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Note: There are four questions in this assignment, which carries 80 marks. Rest 20 marks are for viva voce. You may use illustrations and diagrams to enhance

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the explanations. Please go through the guidelines regarding assignments given in the Programme Guide for the format of the presentation. The answer to
each part of the question should be confined to about 300 words. Make suitable assumptions, if any.
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Q1. (a) Please refer to Figure 4 of Unit 1 of Block 1 on page 11 of the Instruction execution example. Assuming a similar machine is to be used for the
execution of the following three consecutive instructions:
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LODA A ; Load the content of Memory location A into the Accumulator Register.
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ADD B ; Add the content of memory location B from Accumulator Register.

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STOR C ; Stores the content of Accumulator register to memory location C.

However, this machine is different from the example of Figure 4 in the following ways:
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 Each memory word of this new machine is of 16 bits in length.

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 Each instruction is of length 32 bits with 16 bits for operation code (opcode) and 16 bits for specifying one direct operand.
 The Main Memory of the machine would be of size 216 words. 1
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 The three consecutive instructions are placed starting from memory location (11FE)h ; operand A is at location (1FFF)h and contains a value
(4321)h, Operand B is at location (2000)h and contains a value (1FFE)h and operand C is at location (2001)h and contains a value (0000)h.

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  The AC, PC, MAR and MBR registers are of size 16 bits, whereas IR register is of size 32 bits. The initial content of the PC register is (11FE)h.

Draw the diagrams showing the following information:

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(i) Initial State of the machine with the addresses and content of memory locations in hexadecimal. Show only those address locations of the
memory that store the instruction and data. Also show content of all the stated registers. (2)

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Solution:

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Initial State:

The memory locations that store the instructions and data are as follows:

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Address Content (Hexadecimal)

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11FE LOAD A
11FF ADD B

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1200 STORE C
1FFF 4321

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2000 1FFE
2001 000
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The content of the registers in the initial state:
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Register Content (Hexadecimal)

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AC 0000
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PC 11FE

MAR -
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MBR - 2
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IR -

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(ii) Draw three more diagrams, each showing the state of machine after execution of every instruction viz. LOAD, ADD and STOR. Show the
changes in the values of Registers and memory locations, if any, due to execution of instruction. Show all the addresses and values in hexadecimal

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notations. (3)

Solution:

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(1) State after Execution of LOAD instruction:

The LOAD instruction (LODA A) loads the content of memory location A (1FFF)h into the Accumulator (AC) register.

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Register Content (Hexadecimal)

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AC 4321
PC 1200

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MAR 1FFF
MBR 4321

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IR LOAD A

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(2) State after Execution of ADD instruction:

The ADD instruction (ADD B) adds the content of memory location B (2000)h to the value in the Accumulator (AC) register.
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Register Content (Hexadecimal)
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AC 031F
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PC 1201
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MAR 2000
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MBR 1FFE
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IR ADD B

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(3) State after Execution of STOR instruction:

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The STOR instruction (STOR C) stores the content of the Accumulator (AC) register into memory location C (2001)h.

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Register Content (Hexadecimal)
AC 031F

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PC 1202
MAR 2001

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MBR 031F
IR STORE C

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Q1. (b) Perform the following conversion of numbers: (2)

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i) Decimal (345654398)10 to binary and hexadecimal

ii) Hexadecimal (FFEEDDCBA)h into Octal.

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iii) String “Computer Organisation” into UTF 8

iv) Octal (6754632)O into Decimal

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Solution:
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(i) Decimal (345654398)10 into Binary: (10100010101101111101001111110)2
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Decimal (345654398)10 into Hexadecimal: (149A447E)16

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(ii) Hexadecimal (FFEEDDCBA)16 into to Octal : (77767533572)8

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(iii) String “Computer Organisation” into UTF 8:

(iv) Octal (6754632)8 into Decimal: 43 6F 6D 70 75 74 65 72 20 4F 72 67 61 6E 69 73 61 74 69 6F 6E

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Q1. (c) Simplify the following function using K-map: F(A, B, C, D) = Σ (1, 3, 4, 7, 11, 13)

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Draw the circuit for the resultant function using NAND gates. (2)

Solution:

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Logic Circuit diagram using only NAND gate:

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Q1. (d) Consider the Adder-Subtractor circuit as shown in Figure 3.15 page 76 of Block 1. Explain how this circuit will perform subtraction (A-B), if
the value of A is 1011 and B is 0011. You must list all the bit values including Cin and Cout and overflow, if any. (1) 9
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Solution:

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Since, we are going to calculate (A – B) i.e. Subtarction.

Therefore, Cin = 1
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As given, A = 1011, B = 0011

So to perform subtraction, we first finding B' = (0011) ' = 1100 (in binary)
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Therefore, we have
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A = 1011 and B' = 1100 1

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A0 = 1

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A1 = 1

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A2 = 0

A3 = 1

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B0' = 0

B1' = 0

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B2' = 1

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B3' = 1

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For the first full adder:

A0 = 1

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B0' = 0

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Cin = 1

S0 = A0 + B0' + Cin = 1 + 0 + 1 = 10 (in binary)ni

Therefore, S0 = 0; C0 = 1
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For the second full adder:
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A1 = 1
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B1'= 0
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C0 = 1
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S1 = A1 + B1' + C0 = 1 + 0 + 1 = 10 (in binary)

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Therefore, S1 = 0; C1 = 1
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For the third full adder:
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A2 = 0

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B2' = 1

C1 = 1

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S2 = A2 + B2' + C1 = 0 + 1 + 1 = 10 (in binary)

Therefore, S2 = 0; C2 = 1

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For the fourth full adder:

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A3 = 1

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B3' = 1

C2 = 1

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S3 = A3 + B3' + C2 = 1 + 1 + 1 =11 (in binary)

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Therefore, S3 = 1; C3 = Cout = 1

So, the final result of the subtraction is S3S2S1S0 = 1000 i,e (A – B) = 1011 – 0011 = 1000 (in binary)
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There is no overflow in this case.
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Since C3 is equal to 1, this means that there was no underflow in this operation.
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Q1. (e) Explain the functioning of a 3 × 8 decoder with the help of logic diagram and example input. (2)
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Solution:
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A 3 × 8 decoder is a combinational logic circuit that converts a 3-bit binary input into one of eight outputs. Each output corresponds to one of the 23
= 8 possible combinations of the three input bits. The circuit has three inputs, labeled X, Y, and Z, and eight outputs, labeled D0 to D7. The truth

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table and logic diagram for a 3 × 8 decoder is as follows:

Inputs Outputs

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X Y Z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 ni 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
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1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
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1 1 0 0 0 0 0 0 0 1 0
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1 1 1 0 0 0 0 0 0 0 1
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It selects and activates only one of the output lines based on the binary value of the input. The selected output line will have a logic HIGH (1) signal,
while all other output lines will have a logic LOW (0) signal.
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Let's consider an example input where X = 1, Y = 1, and Z = 0. Using the truth table, we can determine the corresponding output values:
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Inputs Outputs
X Y Z D0 D1 D2 D3 D4 D5 D6 D7
1 1 0 0 0 0 0 0 0 1 0
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In this case, the output line D6 is selected and activated with a logic HIGH (1) signal, while all other output lines (D7, D5, D4, D3, D2, D1, D0) have a
logic LOW (0) signal.
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Therefore, when X = 1, Y = 0, and Z = 1, the output of the 3 × 8 decoder will be:

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 D7 = 0
D6 = 1

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D5 = 0
D4 = 0
D3 = 0

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D2 = 0
D1 = 0
D0 = 0

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Q1. (f) Assume that a source data value 1011 was received at a destination as 1010. Show how Hamming's Error-Correcting code bits will be

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appended to source data to identified and correct the error of one bit at the destination. You may assume that transmission error occurs only in the
source data and not the source parity bits. (2)

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Solution:

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Given source data 1011 i.e.

d₁ = 1, d₂ = 0, d3 = 1, d4 = 1

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We can write:

P₁ = d₁ ⊕ d₂ ⊕ d₁ = 1 ⊕ 0 ⊕ 1 = 0
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P₂ = d₁ ⊕ d4 ⊕ d3 = 1 ⊕ 1 ⊕ 1 = 1
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P3 = d2 ⊕ d4 ⊕ d3 = 0 ⊕ 1 ⊕ 1 = 0
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Then transmitted final code is

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P1 P2 d1 P4 d2 d3 d4
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0 1 1 0 0 1 1
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i.e. 0110011
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Q1. (g) Explain the functioning of the D flip-flop and the T flip-flop with the help of a logic diagram and characteristic table. Also, explain the
excitation table of this flip-flop. (2)

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Solution:

D Flip-Flop:

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Logic Diagram:

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Functioning:
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The D flip-flop, also known as the Data or Delay flip-flop, is a type of flip-flop that stores a single bit of data. It has two stable states: SET (S) and
RESET (R). It takes a data input (D) and a clock input (CLK). On each clock cycle, the value of the data input (D) is transferred to the output (Q),
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effectively storing the data. The clock edge (rising or falling) at which the data is transferred depends on the specific design of the flip-flop.

Characteristic Table:
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D CLK Q (next) Comments

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0 0 Q No change on clock edge

0 1 0 Data transferred
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1 0 Q No change on clock edge 1

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1 1 1 Data transferred

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Excitation Table:

The D flip-flop doesn't have an explicit excitation table, as it's not typically analyzed in the same way as other flip-flops. The behavior of the D flip-

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flop is determined by the inputs (D and CLK) and the current state of the flip-flop.

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T Flip-Flop:

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Logic Diagram:

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Functioning:

The T flip-flop, also known as the Toggle flip-flop, has one input, the Toggle (T) input, and a clock input (CLK). On each clock edge, if the T input is
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1, the output (Q) toggles (inverts its current state). If the T input is 0, the output remains in its current state.
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Characteristic Table:

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T CLK Q (next) Comments

0 0 Q No change on clock edge

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0 1 Q No change on clock edge

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1 0 Q No change on clock edge

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1 1 ~Q Output toggles

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Excitation Table:

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Q (current) T T (next)
0 0 0

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0 1 1
1 0 1
1 1 0
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In the excitation table for the T flip-flop, you can see how the next T input should be chosen to achieve the desired transition in the output (toggle or
no change).
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Q1. (h) Explain the functioning of the edge-triggered flip-flop with the help of a diagram. (2)
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Solution:
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In this diagram, "CLK" represents the clock input, "D" represents the data input, and "Q" represents the output. The flip-flop has two stable states,

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commonly referred to as "0" and "1". The output Q represents the current state of the flip-flop.

The functioning of the edge-triggered flip-flop can be explained as follows:

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1. When the clock signal (CLK) transitions from a low state to a high state (rising edge), the flip-flop captures the value of the data input (D)
and stores it. ni
2. The stored value is then reflected at the output Q. If the data input is high (1), the output Q will also be high (1). If the data input is low (0),
the output Q will also be low (0).
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3. The stored value remains unchanged until the next rising edge of the clock signal. This means that the output Q will hold its value even if the
data input changes during the clock cycle.
4. When the clock signal transitions from a high state to a low state (falling edge), the flip-flop ignores any changes in the data input. The stored
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value remains the same until the next rising edge of the clock signal.
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Q1. (i) Represent (-121.25)10 and (0.0625)10 in IEEE 754 single precision and double precision formats. (2)
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Solution:

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 Number Sign Exponent Mantissa IEEE 754 Single Precision
(-121.25)10 1 10000110 11100101000000000000000 11000011011100101000000000000000

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Number Sign Exponent Mantissa IEEE 754 Double Precision

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11100101000000000000000000000000 110000000110111001010000000000000000000000000
(-121.25)10 1 10000000110
00000000000 0000000

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Number Sign Exponent Mantissa IEEE 754 Single Precision

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(0.0625)10 0 01111100 00000000000000000000000 00111110000000000000000000000000

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Number Sign Exponent Mantissa IEEE 754 Double Precision
00000000000000000000000...0 (52
(0.0625)10 0 01111111100 001111111100...0 (64 bits)

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bits)

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Q2. (a) Refer to the Figure 2(b) on page 8 in Unit 1 of Block 2. Draw the Internal organisation of an 8×8 RAM. Explain all the Input and Output of
this organisation. Also answer the following: (2)
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(i) How many data input and data output lines does this RAM needs? Explain your answer.

(ii) How many address lines are needed for this RAM? Give reason in support of your answer.
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Solution:
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A 8 × 8 RAM means that this RAM has 8 words, 3 address lines (23 = 8), and 4 bit data word size. Please note that we can represent a RAM using 2A
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× D where A is the number of address lines and D is the number of Data lines. The immediate above figure is the extension of the binary cell to an
integrated 8 × 8 RAM circuits where a 3 × 8 bit decoder is used. The 4 bit data inputs come through an input buffer and the 4-bit data output is
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stored in the output buffer.

A chip select (𝐶𝑆) control signal is used as a memory enable input. When CS = 0 that is 𝐶𝑆 = 1, It enables the entire chip for read or write operation.
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A R/W signal can be used for read or write operation. The word that is selected will determine the overall output. Since all the above is a logic circuit
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of equal length that can be accessed in equal time, thus, the word RAM.

Answer to question (i): Data output lines/Data input lines are equal and are equal to word size.
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As, 8 × 8 RAM
Therefore, word size is 4 bit.
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Hence, 4 data input lines and 4 data output lines are required for this RAM.

Answer to question (ii): 8 × 8 RAM can be represent as 2A × D where A is the number of address lines and D is the number of Data lines. 2
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Since 23 = 8. 1
Therefore, number of address lines are needed for this RAM = 3

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Q2. (b) A computer has 64 K Word RAM with each memory word of 16 bits. It has cache memory having 32 blocks having a size of 32 bits (2
memory words). Show how the main memory address (1AFC)h will be mapped to the cache address, if (3)

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(i) Direct cache mapping is used

(ii) Associative cache mapping is used

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(iii)Two way set associative cache mapping is used.

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You should show the size of tag, index, main memory block address and offset in your answer.

Solution:

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Given:

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Main Memory Size: 64 K Words (16-bit words)

Cache Size: 32 blocks, each 32 bits (2 memory words)

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Main Memory Address: `1AFC`h (`6812` in decimal)

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Assumptions: ni
 Each block in cache holds 2 memory words.
 The main memory address is divided into tag, index, and offset bits for mapping.
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Let's proceed with each mapping scheme:

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(i) Direct Cache Mapping:

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Cache Size: 32 blocks

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Main Memory Size: 64 K Words

Number of blocks in main memory = Main Memory Size / Block Size = 64 K / 2 = 32 K blocks 2
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Block size = 2 memory words = 2 * 16 bits = 32 bits

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 Number of bits required for block offset (b) = log2(Block Size) = log2(32) = 5 bits

Number of bits required for index (n) = log2(Number of Blocks in Cache) = log2(32) = 5 bits

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Number of bits left for tag (k) = Address Width - (b + n) = 16 - (5 + 5) = 6 bits

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Let's break down the main memory address `1AFC`h:

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Main Memory Address: 0001101011111100

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Calculations:

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Offset: `1100` (last 4 bits)

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Index: `11111` (5 bits after offset)

Tag: `000110` (6 bits remaining)

Cache Address Mapping (Direct Mapping):

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Tag: `000110`
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Index: `11111`
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Block Offset: Not needed in cache address (since block size is 32 bits)
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s:

(ii) Associative Cache Mapping:

Block size = 2 memory words = 32 bits

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Number of bits required for block offset (b) = log2(Block Size) = log2(32) = 5 bits 2
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Number of bits left for tag (k) = Address Width - b = 16 - 5 = 11 bits 3

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Let's break down the main memory address `1AFC`h:

Main Memory Address: 0001101011111100

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Calculations:

Offset: `1100` (last 4 bits)

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Tag: `00011010111` (11 bits remaining)

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Cache Address Mapping (Associative Mapping):

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Tag: `00011010111`

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Block Offset: Not needed in cache address (since block size is 32 bits)

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(iii) Two-Way Set Associative Cache Mapping:

Number of Sets = Cache Size / (Number of Blocks per Set) = 32 / 2 = 16 sets

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Block size = 2 memory words = 32 bits
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Number of bits required for block offset (b) = log2(Block Size) = log2(32) = 5 bits
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Number of bits required for index (n) = log2(Number of Sets) = log2(16) = 4 bits
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Number of bits left for tag (k) = Address Width - (b + n) = 16 - (5 + 4) = 7 bits

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Let's break down the main memory address `1AFC`h:

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Main Memory Address: 0001101011111100 2

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Calculations:

Offset: `1100` (last 4 bits)

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Index: `1111` (4 bits after offset)

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Tag: `0001101` (7 bits remaining)

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Cache Address Mapping (Two-Way Set Associative Mapping):

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Tag: `0001101`

Index: `1111`

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Block Offset: Not needed in cache address (since block size is 32 bits)

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In summary, the cache address mapping for the main memory address `1AFC`h under different cache mapping schemes is as follows:

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(i) Direct Cache Mapping:

Tag: `000110` ni
Index: `11111`
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(ii) Associative Cache Mapping:

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Tag: `00011010111`
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(iii) Two-Way Set Associative Cache Mapping:

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Tag: `0001101` 2
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Index: `1111` 5

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Q2. (c) What is an Interrupt? Why are interrupts used in a computer? Explain different kinds of interrupts. Also, explain the process of interrupt
processing. (3)

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Solution:

Interrupt: An interrupt in a computer is a signal that indicates the occurrence of an event that requires the attention of the processor. Interrupts

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are used to temporarily halt the normal execution of a program in order to handle the event that has occurred. They play a crucial role in improving
the efficiency and responsiveness of a computer system by allowing it to handle multiple tasks concurrently and respond promptly to time-sensitive
events.

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Purpose and Importance of Interrupts:

Interrupts are used in computers to:

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 Handle hardware events: Such as I/O operations (e.g., keyboard input, disk I/O), timers, and external signals.

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 Implement multitasking: Allow the CPU to switch between multiple tasks or programs rapidly, enabling efficient time-sharing of
resources.
 Respond to errors: Detect and handle errors such as divide-by-zero or invalid memory access.

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 Support communication: Enable communication between different hardware components and peripherals.
 Enable real-time processing: Quickly respond to time-critical events, essential in systems like embedded systems and control
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Types of Interrupts:
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1) Hardware Interrupts: These are generated by external hardware devices. They include:
2) Maskable Interrupts: Can be ignored or disabled by the CPU if it's not feasible to handle them immediately.
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3) Non-Maskable Interrupts (NMI): Cannot be ignored or masked, usually used for critical events like system crashes.
4) Software Interrupts: Generated by software instructions, often used for system calls and software-generated exceptions.
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5) Exception Interrupts: Generated by exceptional conditions, such as arithmetic errors, page faults, or illegal instructions.
6) Internal Interrupts: Triggered by CPU itself, like timer interrupts used for multitasking.
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Interrupt Processing Process:

 Interrupt Request (IRQ): An interrupt event occurs, often initiated by external hardware like I/O devices or timers.

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 Interrupt Controller: The interrupt controller (hardware) receives and prioritizes the interrupts. It sends the highest-priority interrupt to
the CPU.

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 Current State Save: The CPU saves its current state (registers, program counter) to ensure the interrupted process can be resumed
accurately.
 Interrupt Service Routine (ISR): The CPU jumps to the appropriate Interrupt Service Routine based on the interrupt's vector or

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address. The ISR handles the specific interrupt event.
 Interrupt Handling: The ISR executes, performing tasks related to the interrupt. This may involve reading data from I/O devices,
processing the data, or responding to a request.

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 State Restoration: After the ISR completes its tasks, the CPU restores the saved state, including the program counter and registers, to
resume normal execution of the interrupted process.

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 Return to Normal Execution: The CPU continues executing the interrupted process from where it was paused.

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Q2. (d) What is an I/O processor? Explain the selector channel structure in the context of the I/O processor. How is an I/O processor different
from DMA? (2)

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Solution:
ni
I/O Processor: An I/O (Input/Output) processor is a specialized component in a computer system that manages communication between the CPU
and external devices, such as storage devices, network interfaces, and other peripherals. Its primary role is to offload I/O-related tasks from the
main CPU, allowing it to focus on computation and improving overall system efficiency.
ar
Selector Channel Structure:
e

The selector channel structure is a type of I/O processor architecture that enables efficient data transfer between the main memory and multiple I/O
//l

devices. It employs a dedicated channel for each I/O device, called a selector channel. Each selector channel operates independently, under the
control of the I/O processor, to manage data transfers between the I/O device and memory.
s:

In the selector channel structure, the I/O processor uses a command issued by the CPU to initiate data transfers. The I/O processor then manages
the data movement, including addressing, buffering, and coordination with the device. This architecture is particularly useful for handling high-
tp

speed and high-volume data transfers between multiple I/O devices and memory.
2
ht

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Difference Between I/O Processor and DMA (Direct Memory Access):

.in
Aspect I/O Processor DMA (Direct Memory Access)

Manages communication between CPU Handles direct data transfer between

Function
and I/O devices I/O and memory

co
Reduces CPU involvement in data
Role Offloads I/O-related tasks from CPU
transfer

e.
Data Transfer Typically involves slower devices Primarily used for high-speed devices

nc
Control Operates based on set-up and start
Involves a command-driven approach
Mechanism signals
Manages communication and data

ie
Coordination Manages data transfer only
movement

sc
Can handle various I/O devices and Limited to data transfer between I/O
Flexibility
operations and memory

Complex Capable of performing complex I/O

ng
Focused on efficient data movement
Operations operations

Channel
Can use selector channel structure
ni Utilizes a simpler channel structure
Structure

Involvement of Moderately involves CPU for I/O Minimizes CPU involvement in data
ar
CPU management transfer
e

Q2. (e) Assume that a disk has 32 tracks, with each track having 16 sectors and each sector is of size 512 Kilobytes. The cluster size in this system
//l

can be assumed to be as 2 sectors. A file having the name mcs012.txt is of size 16 MB. Assume that it is a new disk, and the first 8 clusters are
occupied by the Operating System. Rest all the clusters are free. How can this file be allotted space on this disk? Also, show the content of FAT after
s:

the space allocation to this file. You may make suitable assumptions. (4)
tp

Solution:

Given, 2
ht

8
Disk has 32 tracks

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Track has 16 sectors/track
Size of one Sector is 512 KB

.in
Cluster size as 2 sectors

co
Calculate the file size in clusters:

File size = 16 MB = 16,384 KB

e.
Cluster size = 2 sectors = 2 * 512 KB = 1,024 KB = 1 MB

nc
Number of clusters required = File size / Cluster size = 16,384 KB / 1,024 KB = 16 clusters

Total number of clusters = (Total number of tracks × Total number of sectors per track) / Cluster size = 32 × 16/2 = 512/2 = 256

ie
sc
Find the first free cluster in the FAT:

Since the first 8 clusters are occupied by the Operating System, we start searching for a free cluster from cluster 9.

ng
Update the FAT:
ni
Assigning the first free cluster to the file "mcs012.txt" and mark it as used in the FAT. Repeating this process for the next 15 clusters required by the
ar
file.

Assuming the first free cluster is cluster 9, the updated FAT would look like this:
e
//l

The FAT table after allocating this file would be:

0-8: Used by OS
s:

9-15: mcs012.txt
tp

16-256: Free
2
ht

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 Cluster FAT Entry
0 Reserved

.in
1 Reserved
2 Reserved

co
3 Reserved
4 Reserved
5 Reserved

e.
6 Reserved
7 Reserved

nc
8 Reserved
9 Used by "mcs012.txt"

ie
10 Used by "mcs012.txt"
11 Used by "mcs012.txt"

sc
12 Used by "mcs012.txt"
13 Used by "mcs012.txt"

ng
14 Used by "mcs012.txt"
15 Used by "mcs012.txt"
ni16 Free
17 Free
ar
... ...
... ...
... ...
e

... ...
//l

... ...
... ...
s:

... ...
tp

... ...
... ...
3
ht

256 Free 0

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Q2. (f) Explain the following, giving their uses and advantages/disadvantages, if needed. (6)

(Word limit for answer of each part is 50 words ONLY)

.in
(i) Rotational Latency in disks

co
(ii) Programmed I/O

(iii) Resolution of Display and Printer

e.
(iv) Zip Drive

nc
(v) Power Supply

(vi) Keyboard and Mouse

ie
Solution:

sc
(i) Rotational Latency in disks: Rotational latency is the time it takes for the desired data to rotate under the read/write head of a disk. It affects
the access time of the disk. Lower rotational latency leads to faster data retrieval.

ng
Advantage: It allows for efficient storage and retrieval of large amounts of data.

Disadvantage: It can cause delays in accessing data.

ni
(ii) Programmed I/O: Programmed I/O is a method of data transfer between a computer and an I/O device where the CPU directly controls the
data transfer. It is simple and suitable for low-speed devices.
ar
Advantage: It is easy to implement.
e

Disadvantage: It can tie up the CPU, leading to slower overall system performance.
//l

(iii) Resolution of Display and Printer: Resolution refers to the number of pixels or dots per inch (DPI) that a display or printer can produce.
Higher resolution results in sharper and more detailed images.
s:

Advantage: Higher resolution provides better image quality.

tp

Disadvantage: Higher resolution may require more processing power and storage space.
3
ht

(iv) Zip Drive: A Zip drive is a removable storage device that uses Zip disks to store data. It offers higher storage capacity than floppy disks. 1

Advantage: It provides a portable and reliable storage solution.

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 Disadvantage: Zip drives have become less popular due to the availability of higher-capacity USB flash drives and cloud storage.

(v) Power Supply: A power supply unit (PSU) converts AC power from an electrical outlet into DC power suitable for computer components. It

.in
provides power to the computer's internal components.

Advantage: It ensures stable and reliable power delivery.

co
Disadvantage: Inadequate power supply can lead to system instability or component damage.

e.
(vi) Keyboard and Mouse: Keyboard and mouse are input devices used to interact with a computer. The keyboard allows inputting text and
commands, while the mouse enables pointing and clicking.

nc
Advantage: They provide a user-friendly interface for computer interaction.

Disadvantage: They may cause repetitive strain injuries with prolonged use.

ie
sc
Q3. (a) A single-core uniprocessor system has 8 General purpose registers. The machine has RAM of size 64K memory words. The size of every
general-purpose register and memory word is 16 bits. The computer uses fixed-length instructions of size 32 bits each. An instruction of the machine

ng
can have two operands. One of these operands is a direct memory operand and the other is a register operand. An instruction of a machine consists
of bits for operation code, bits for memory operand and bits of register operand. The machine has about 128 different operation codes. The special
purpose registers, which are other than general purpose registers, are - Program Counter (PC), Memory Address Register (MAR), Data Register
ni
(DR) and Flag registers (FR). The first register among the general-purpose registers can be used as Accumulator Register. The size of Integer
operands on the machine may be assumed to be equal to the size of the accumulator register. To execute instructions, the machine has another
ar
special register called Instruction Register (IR) of size 32 bits, as each instruction is of this size. Perform the following tasks for the machine. (Make
and state suitable assumptions, if any.)
e

(i) Design suitable instruction formats for the machine. Specify the size of different fields that are needed in the instruction format. Also, indicate
how many bits of the instructions are unused for this machine. Explain your design of the instruction format. Also, indicate the size of each register.
//l

(3)
s:

Solution:
tp

Based on the given information, we can design the instruction format as follows:
3
ht

Operation Code (OP): 7 bits (can represent 128 different operation codes)
2
Memory Operand (MO): 15 bits (for addressing memory)
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 Register Operand (RO): 3 bits (to select one of the 8 general-purpose registers)

The total size of the instruction is 32 bits.

.in
Explanation:

co
The operation code field specifies the operation to be performed (128 different operations).
The memory operand field allows addressing 64K memory words (15 bits provide 2^15 = 32K addresses).
The register operand field selects one of the 8 general-purpose registers.

e.
The unused bits would be 32 - (7 + 15 + 3) = 7 bits.

Assumption:

nc
 The memory operand field holds the address of the memory location, and the memory location stores a 16-bit value.
 The register operand field selects one of the 8 general-purpose registers, including the accumulator.

ie
 The accumulator and general-purpose registers are all 16 bits in size.

sc
(ii) Demonstrate two valid instructions of the machine; put some valid data values in registers and memory locations and show these two

ng
instructions. (2)

Solution:

Let's consider two instructions:

ni
ar
1. Addition Instruction: Add the contents of memory location 5000 with the value in register R2 and store the result in the accumulator.

Instruction Binary: `0010100 0011001100100100 010`

e

2. Load Instruction: Load the value from memory location 2000 to register R3.
//l

Instruction Binary: `1001101 0000011100000001 011`

s:
tp

(iii) Assuming that the instructions are first fetched to the Instruction Register (IR), the memory operand is brought to the DR register and the
result of an operation is stored in the Accumulator register; write and explain the sequence of micro-operations that are required to fetch and 3
ht

execute an addition instruction that adds the contents of the memory and register operands of the instruction. The result is stored in the 3
accumulator register. Make and state suitable assumptions, if any. (5)

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Solution:

Assumptions:

.in
 The instruction fetch, memory read, and memory write operations each take one machine cycle.
 The result of the addition operation is stored in the accumulator register.

co
 We'll assume the values of memory location 5000 and register R2 are 0x2A (42) and 0x1E (30) respectively.

e.
1. Fetch Instruction (IR ← Memory[PC]): Load the instruction from memory into the Instruction Register (IR).

nc
IR ← Memory[PC] = `00101000001100110010010001000110`

2. Increment PC (PC ← PC + 1): Move to the next instruction.

ie
PC ← PC + 1

sc
3. Decode Instruction (OP, MO, RO ← IR): Decode the instruction.

OP = `0010100`

ng
MO = `0011001100100100`

RO = `010`
ni
4. Fetch Memory Operand (MAR ← MO, DR ← Memory[MAR]): Load the memory operand address into the Memory Address Register
ar
(MAR) and fetch the value from memory into the Data Register (DR).
e

MAR ← MO = `0011001100100100`
//l

DR ← Memory[MAR] = Memory[5000] = `0010101000000000` (Value at memory location 5000)

5. Perform Addition (Acc ← Acc + DR): Add the value in the Data Register (DR) to the accumulator.
s:

Acc = Acc + DR = `0000000000101010` (Accumulator content) + `0010101000000000` (DR content) = `0010101000101010`

tp

6. Store Accumulator (Memory[MAR] ← Acc): Store the result back in memory.

3
ht

Memory[MAR] ← Acc = `0010101000101010` 4

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Q3. (b) Assume that you have a machine, as shown in section 3.2.2 of Block 3 having the microoperations given in Figure 10 on page 62 of Block 3.
Consider that R1 and R2 both are 8-bit registers and contain 11100111 and 00111100 respectively. What will be the values of select inputs, carry-in

.in
input, and the result of the operation (including carry-out bit) if the following micro-operations are performed? (For each micro-operation you may
assume the initial value of R1 and R2 as given above) (2)

co
(i) Decrement R1

(ii) Add R1 and R2 with Carry

e.
(iii) Exclusive OR of the registers R1 and R2

(iv) Shift right R1

nc
Solution:

ie
(i) Decrement R1:

sc
Symbolic Designation Description
R1 ← R1 – 1 Decrement the contents of R1 by 1.

ng
R1 = 11100111

Therefore: ni
D e c r e m e n t th e c o n te n t o f R 1 b y 1 :

11100111
ar

00000001
e

011100110

The carry-out bit is zero because there is no borrow.

//l
s:

(ii) Add R1 and R2 with Carry:

tp

Symbolic Designation Description

R3 ← R1 + R2 Contents of R1+R2 transferred to R3. 3
ht

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R1 = 11100111

.in
R2 = 00111100

Let consider carry input is 1 i.e. Cin = 1

co
Therefore:
A d d iti o n R 1 a n d R 2
w ith c a rry  i.e . R 1  R 2  C in  :

e.
11100111
 00111100

nc
00000001

100011000

ie
The carry-out bit is one because there is an overflow.

sc
ng
(iii) Exclusive OR of the registers R1 and R2:

Symbolic Designation Description

ni
R3 ← R1 ⊕ R2 Exclusive OR of R1 and R2 transferred to R3.
ar
R1 = 11100111

R2 = 00111100
e

Let consider carry input is 1 i.e. Cin = X

//l

Therefore:
s:

E x c lu s iv e O R o f R 1 a n d R 2  i .e . R1  R 2  :
tp

11100111

00111100
3
ht

X 11011011
6
The carry-out bit is undefined because it is not used for this operation.
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(iv) Shift right R1:

.in
Symbolic Designation Description

R ← Shr(R1) R = Shift right R1

co
R1 = 11100111

e.
Cin = not defined i.e. X

The left shift operation is usually written as “<<”.

nc
R1 = 11100111

ie
Number of bit to shift right = 1

sc
11100111 >> 1 → X01110011

The carry-out bit is the rightmost bit of R1, which is one. The leftmost bit of R is undefined because it is not filled by any value.

ng
Q3. (c) Consider that an instruction pipeline has three stages namely instruction fetch and decode (FD), Operand Fetch (OF) and Instruction
Execute and store results (ES). Draw an instruction pipeline diagram showing the execution of five sequential instructions using this pipeline. What
ni
are the problems with this instruction pipelining? (3)
ar
Solution:

The instruction pipeline diagram for the execution of five sequential instructions:
e
//l
s:
tp

3
ht

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 Clock Cycle FD (Instruction Fetch and Decode) OF (Operand Fetch) ES (Execute and Store Results)

.in
Cycle 1 Instruction 1

Cycle 2 Instruction 2 Instruction 1

co
Cycle 3 Instruction 3 Instruction 2 Instruction 1

Cycle 4 Instruction 4 Instruction 3 Instruction 2

e.
Cycle 5 Instruction 5 Instruction 4 Instruction 3

nc
Cycle 6 Instruction 5 Instruction 4

Cycle 7 Instruction 5

ie
sc
In this pipeline, each stage takes one clock cycle to complete. The FD stage fetches and decodes the instruction, the OF stage fetches the operands,
and the ES stage executes the instruction and stores the results.

ng
However, there are a few problems with this instruction pipelining:

1) Data Hazards: Data hazards occur when an instruction depends on the result of a previous instruction that has not yet completed. In this
pipeline, if Instruction 2 depends on the result of Instruction 1, it will have to wait until Instruction 1 completes the ES stage. This can cause
ni
pipeline stalls and reduce the overall efficiency.
2) Control Hazards: Control hazards occur when the pipeline encounters branch instructions that change the program flow. In this pipeline,
ar
if Instruction 3 is a branch instruction, the pipeline will have to flush the instructions fetched after Instruction 3, as they may not be needed.
This leads to wasted clock cycles and reduces performance.
3) Structural Hazards: Structural hazards occur when multiple instructions require the same hardware resource at the same time. In this
e

pipeline, if the OF stage requires a specific resource that is already being used by the ES stage, a structural hazard will occur, causing pipeline
stalls.
//l

4) Instruction Dependencies: If there are dependencies between instructions, such as Instruction 2 depending on the result of Instruction
1, the pipeline may need to stall or insert additional instructions to resolve these dependencies. This can introduce additional complexity and
s:

reduce performance.
tp

Q3. (d) Explain the functioning of the Wilkes Control Unit. Also, explain the format of the control memory with the help of a diagram. (2)

Solution: 3
ht

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1st Part:

Here are the main functions of a Wilkes Control Unit:

.in
1) Memory Control - The Wilkes Control Unit manages the main memory of the computer system. It handles reading and writing of data to
memory locations as instructed by the processor.

co
2) Instruction Fetch and Decode - It fetches instructions from memory and decodes or interprets them. This involves determining the
operation code and operands.
3) Register Management - It contains a set of registers that are used for temporary storage of data during computations. The control unit

e.
manages these registers and transfers data between registers and memory as needed.
4) Instruction Sequencing - It determines the order of execution of instructions. It internally tracks the program counter which points to

nc
the next instruction to be executed.
5) Arithmetic Logic Unit (ALU) Control - An ALU is used for arithmetic and logical operations. The control unit provides signals to the
ALU to specify the operation to be performed.

ie
6) Input/Output Management - It controls communication of the CPU with peripheral devices. This involves transferring data between I/O
devices and memory.

sc
7) Timing and Synchronization - It coordinates the timing and synchronization of various components like cache, registers, ALU etc. to
ensure correct execution of instructions in a pipelined manner.
8) Interrupt Handling - It handles interrupts from devices and passes control to the relevant interrupt service routine.

ng
2nd Part:
ni
The control memory is a part of the control unit that stores the microinstructions for executing micro-operations. The format of the control memory
ar
depends on the design of the microprogrammed control unit, but generally it consists of two parts: the control word and the next address field. The
control word contains the bits that initiate the micro-operations in the computer registers, and the next address field specifies the method by which
e

the next microinstruction is selected.

//l
s:
tp

3
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 .in
co
e.
nc
ie
sc
ng
ni
e ar
//l
s:
tp

4
ht

The diagram also shows how the control memory is organized into different rows and columns, each corresponding to a different micro-instruction 0
for a different cycle. For example, the first row in the left column contains the micro-instructions for fetching an instruction from memory, and the

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first row in the right column contains the micro-instructions for handling an interrupt request. The diagram also shows how the control address
register (CAR) receives the next address from different sources, such as the program counter (PC), the instruction register (IR), or the next address

.in
field itself.

co
Q3. (e) Explain the characteristics of RISC? Also, explain the RISC pipelining. (3)

Solution:

e.
1st Part:

nc
RISC stands for Reduced Instruction Set Computing. Some of the key characteristics of RISC architecture are:

Simpler instructions: RISC instructions are generally simpler and require fewer clock cycles to execute than their CISC counterparts.

ie
Fixed instruction size: RISC instructions are typically all the same size, which simplifies the instruction fetch and decode stages of the pipeline.

sc
Single-cycle instruction execution: RISC processors aim to execute one instruction per clock cycle, which can be achieved through pipelining.

More general-purpose registers: RISC processors typically have more general-purpose registers than CISC processors, which reduces the need

ng
for memory accesses.

Simple addressing modes: RISC processors typically have fewer and simpler addressing modes than CISC processors.
ni
Fewer data types: RISC processors typically support fewer data types than CISC processors.
ar
2nd Part:
e

RISC pipelining is a technique used in RISC processors to increase their performance. Pipelining works by breaking down the instruction execution
process into several stages, with each stage being performed by a different part of the processor. This allows multiple instructions to be processed
//l

simultaneously, with each instruction at a different stage of the pipeline.

s:

For example, while one instruction is being fetched from memory, another instruction can be decoded, and yet another instruction can be executed.
This overlap of operations can significantly increase the performance of the processor.
tp

4
ht

Q4. (a) Write a program using 8086 assembly Language (with proper comments) that accepts three different digits as input from the keyboard. 1
Each digit is first converted to a binary equivalent. The binary values of these three digits are compared and the middle value is put in the AL

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register. This AL register is multiplied with each value of a byte array of size 6, which is stored in the memory. The result of the multiplication is
stored in the same memory location. You may assume the byte array has the values 02h, 06h, 08h, 03h, 01h, 05h. Make suitable assumptions, if any.

.in
(7)

Solution:

co
MOV AL, 10h ; Assume the given value is 10h

e.
MOV SI, OFFSET ByteArray ; Start address of the byte array

nc
MOV CX, 6 ; Number of elements in the byte array

ie
LOOP_START:

sc
MOV DL, [SI] ; Load the value from the byte array

ng
MUL DL ; Multiply the value in AL with the value in DL

ni
MOV [SI], AL ; Store the result of the multiplication back in the byte array
ar
INC SI ; Move to the next element in the byte array
e

LOOP LOOP_START ; Repeat for all elements

//l
s:

HLT ; Halt the program

tp

4
ht

ByteArray DB 02h, 06h, 08h, 03h, 01h, 05h ; Byte array of size 6 2

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After executing the program, the byte array will be modified as follows:

.in
Memory Address Value
ByteArray+0 20h
ByteArray+1 60h

co
ByteArray+2 80h
ByteArray+3 30h

e.
ByteArray+4 10h
ByteArray+5 50h

nc
Screenshot:

ie
sc
ng
ni
e ar
//l
s:
tp

4
ht

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Q4. (b) Write a NEAR subroutine using 8086 assembly Language (with proper comments) that returns the average value of the values stored in a
byte array of length 3. All three values of the byte array are passed to the subroutine in the stack. You should write both the calling program and

.in
subroutine. (7)

Solution:

co
; Calling program

ORG 100h

e.
nc
MOV AX, 10 ; First value of the byte array

PUSH AX ; Push the first value onto the stack

ie
sc
MOV AX, 20 ; Second value of the byte array

PUSH AX ; Push the second value onto the stack

ng
MOV AX, 30 ; Third value of the byte array
ni
PUSH AX ; Push the third value onto the stack
e ar

CALL AverageSubroutine ; Call the subroutine

//l
s:

MOV BX, AX ; Move the average value from AX to BX for display

tp

MOV AH, 02h ; Function to display a single character 4

ht

4
MOV DL, 'A' ; Display 'A' for Average

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INT 21h ; Call the DOS interrupt

.in
MOV AH, 02h ; Function to display a single character

co
MOV DL, ':' ; Display ':' for separator

INT 21h ; Call the DOS interrupt

e.
nc
MOV AH, 02h ; Function to display a single character

MOV DL, ' ' ; Display a space

ie
INT 21h ; Call the DOS interrupt

sc
MOV AH, 02h ; Function to display a single character

ng
MOV DL, BL ; Display the average value

ADD DL, 30h ; Convert the value to ASCII

ni
INT 21h ; Call the DOS interrupt
e ar

HLT
//l
s:

AverageSubroutine:

; Subroutine to calculate the average value of a byte array of length 3

tp

4
ht

PUSH BP ; Save the base pointer 5

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MOV BP, SP ; Set the base pointer to the current stack pointer

.in
MOV AL, [BP+4] ; Get the first value from the stack

co
ADD AL, [BP+6] ; Add the second value from the stack

ADD AL, [BP+8] ; Add the third value from the stack

e.
nc
MOV AH, 0 ; Clear the high byte of AX

ie
MOV BL, 3 ; Divide by 3 to calculate the average

sc
DIV BL

ng
POP BP ; Restore the base pointer

RET ; Return from the subroutine

ni
Screenshots:
e ar
//l
s:
tp

4
ht

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 .in
co
e.
nc
ie
sc
ng
ni
e ar

Q4. (c) Explain the following in the context of 8086 Microprocessor with the help of an example or a diagram: (6)
//l

(i) Use of code segment and stack segment registers for computing the respective 20-bit addresses.
s:

(ii) Any 4 flags of the flag register of 8086 micro-processor

(iii) Any four shift instructions of 8086 micro-processor

tp

Solution:
4
ht

(i) In the 8086 microprocessor, the code segment register (CS) and the stack segment register (SS) are used to compute the respective 20- 7
bit addresses.
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The code segment register (CS) holds the starting address of the code segment, which contains the instructions to be executed by the processor.
The CS register is combined with the instruction pointer (IP) register to form a 20-bit physical address. The IP register contains the offset within the

.in
code segment where the next instruction is located. By combining the CS and IP registers, the processor can determine the physical address of the
instruction to be fetched.

co
For example, let's say the CS register holds the value 0x1000 and the IP register holds the value 0x0010. The physical address of the next
instruction would be 0x10000 + 0x0010 = 0x10010.

e.
Similarly, the stack segment register (SS) holds the starting address of the stack segment, which is used for storing temporary data and return

nc
addresses during subroutine calls. The SS register is combined with the stack pointer (SP) register to form a 20-bit physical address. The SP register
contains the offset within the stack segment where the next data or return address will be stored.

ie
For example, if the SS register holds the value 0x2000 and the SP register holds the value 0x0020, the physical address of the next stack operation
would be 0x20000 + 0x0020 = 0x20020.

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ii) The flag register in the 8086 microprocessor contains various flags that indicate the status of the processor after executing an instruction. Here

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are four commonly used flags:

1. Carry Flag (CF): This flag is set when an arithmetic operation generates a carry or borrow. For example, if an addition operation results in a
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carry out of the most significant bit, the CF flag is set.

2. Zero Flag (ZF): This flag is set when the result of an arithmetic or logical operation is zero. It is cleared when the result is non-zero.
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3. Sign Flag (SF): This flag is set when the result of an arithmetic or logical operation is negative. It is cleared when the result is positive or zero.
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4. Overflow Flag (OF): This flag is set when an arithmetic operation generates an overflow. It indicates that the result is too large to be
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represented in the destination register.

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(iii) The 8086 microprocessor provides several shift instructions to perform bitwise shifting of data. Here are four commonly used shift
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instructions:
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1. Arithmetic Shift Left (SAL/SHL): This instruction shifts the bits of the operand to the left, filling the least significant bit with zero. The
shifted bits are shifted into the carry flag. For example, if the operand is 0b1100 and we perform a SAL instruction, the result would be 0b1000, with 8
the carry flag set to 1.
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2. Arithmetic Shift Right (SAR): This instruction shifts the bits of the operand to the right, preserving the sign bit. The most significant bit (sign
bit) is replicated to fill the vacant bit positions. For example, if the operand is 0b1100 and we perform a SAR instruction, the result would be 0b1110.

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3. Logical Shift Left (SHL): This instruction shifts the bits of the operand to the left, filling the least significant bit with zero. The shifted bits are
shifted into the carry flag. The difference between SHL and SAL is that SHL does not treat the operand as a signed value.

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4. Logical Shift Right (SHR): This instruction shifts the bits of the operand to the right, filling the vacant bit positions with zero. The most
significant bit is lost. For example, if the operand is 0b1100 and we perform a SHR instruction, the result would be 0b0110.

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