ARM® NEON™ Intrinsics

Reference
Document number: IHI 0073B
Date of Issue: 24/03/2016

Abstract
This draft document is a reference for the Advanced SIMD Architecture Extension (NEON) Intrinsics for ARMv7
and ARMv8 architectures.

Keywords
ACLE, NEON

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Contents

1 ABOUT THIS DOCUMENT 4

1.1 Change control 4

1.1.1 Current status and anticipated changes 4
1.1.2 Change history 4

1.2 References 4

1.3 Terms and abbreviations 4

2 SCOPE 5

3 LIST OF INTRINSICS 6

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1 ABOUT THIS DOCUMENT
1.1 Change control
1.1.1 Current status and anticipated changes
This document is the first release of the ARM NEON Intrinsics reference.

1.1.2 Change history

Issue Date By Change
A 09/05/2014 TB First release
B 24/03/2016 TB Add intrinsics for new NEON Instructions in ARMv8.1.

1.1.3 Changes in the current release

 Adds intrinsics for the SQRDMLAH and SQRDMLSH Advanced SIMD instructions newly added in
ARMv8.1 [ACLE-124].
 Adds missing vmov<q>_n_p64 intrinsics [ACLE-125].
 Fixes typographical errors [ACLE-121, ACLE-123].

1.2 References
This document refers to the following documents.
Ref Doc No Author(s) Title
ARMARMv8 ARM DDI0487A.B ARM ARMv8-A Reference Manual (Issue A.b)
ARMARMv81 http://community.arm.com/gro ARM ARMv8.1 Extension
ups/processors/blog/2014/12/
02/the-armv8-a-architecture-
and-its-ongoing-development
ACLE2 IHI 0053C ARM ARM C Language extensions, Release 2.0.
ACLE21 IHI 0053D ARM ARM C Language extensions, Release 2.1.

1.3 Terms and abbreviations

This document uses the following terms and abbreviations.
Term Meaning
ARMv7, ARMv8 Legacy intrinsics common to ARMv7(A&R profiles) & ARMv8, all instruction sets

ARMv8 Intrinsics introduced in ARMv8, all instruction sets

ARMv8(AArch64) Intrinsics introduced in ARMv8, AArch64 state only

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2 SCOPE
This document serves as a look-up reference for all ARMv7 and ARMv8 NEON Intrinsics. The formal specification
for NEON Intrinsics is available in [ACLE2]. The table in section 3 has the following format:

Instruction operand ARMv8 AArch64 Result location List of architectures

Intrinsic Prototype to argument Instruction(s) the with respect to the intrinsic is
mapping intrinsic maps to instruction. supported in.

The AArch64 instruction mapping is shown here as an example implementation. Their meaning and semantics are
specified in [ACLE2]. For accurate specification of the vector and scalar data types used in this document, refer
[ACLE2] – this document does not specify them.
This document does not describe the assembly operation of instructions – see [ARMARMv8].

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3 LIST OF INTRINSICS

Argument Supported
Intrinsic A64 Instruction Result
Preparation Architectures

int8x8_t vadd_s8
(int8x8_t a, a → Vn.8B ADD Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int8x16_t vaddq_s8
(int8x16_t a, a → Vn.16B ADD Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vadd_s16
(int16x4_t a, a → Vn.4H ADD Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int16x8_t vaddq_s16
(int16x8_t a, a → Vn.8H ADD Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vadd_s32
(int32x2_t a, a → Vn.2S ADD Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

int32x4_t vaddq_s32
(int32x4_t a, a → Vn.4S ADD Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

int64x1_t vadd_s64
(int64x1_t a, a → Dn ADD Dd,Dn,Dm Dd ARMv7, ARMv8
int64x1_t b) b → Dm

int64x2_t vaddq_s64
(int64x2_t a, a → Vn.2D ADD Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
int64x2_t b) b → Vm.2D

uint8x8_t vadd_u8
(uint8x8_t a, a → Vn.8B ADD Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vaddq_u8
(uint8x16_t a, a → Vn.16B ADD Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vadd_u16
(uint16x4_t a, a → Vn.4H ADD Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

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uint16x8_t vaddq_u16
(uint16x8_t a, a → Vn.8H ADD Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vadd_u32
(uint32x2_t a, a → Vn.2S ADD Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

uint32x4_t vaddq_u32
(uint32x4_t a, a → Vn.4S ADD Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

uint64x1_t vadd_u64
(uint64x1_t a, a → Dn ADD Dd,Dn,Dm Dd ARMv7, ARMv8
uint64x1_t b) b → Dm

uint64x2_t vaddq_u64
(uint64x2_t a, a → Vn.2D ADD Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
uint64x2_t b) b → Vm.2D

float32x2_t vadd_f32
(float32x2_t a, a → Vn.2S FADD Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

float32x4_t vaddq_f32
(float32x4_t a, a → Vn.4S FADD Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

float64x1_t vadd_f64
(float64x1_t a, a → Dn FADD Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

float64x2_t vaddq_f64
(float64x2_t a, a → Vn.2D FADD Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

int64_t vaddd_s64
(int64_t a, a → Dn ADD Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

uint64_t vaddd_u64
(uint64_t a, a → Dn ADD Dd,Dn,Dm Dd ARMv8(AArch64)
uint64_t b) b → Dm

int16x8_t vaddl_s8
(int8x8_t a, a → Vn.8B SADDL Vd.8H,Vn.8B,Vm.8B Vd.8H ARMv7, ARMv8
int8x8_t b) b → Vm.8B

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int32x4_t vaddl_s16
(int16x4_t a, a → Vn.4H SADDL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int64x2_t vaddl_s32
(int32x2_t a, a → Vn.2S SADDL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint16x8_t vaddl_u8
(uint8x8_t a, a → Vn.8B UADDL Vd.8H,Vn.8B,Vm.8B Vd.8H ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint32x4_t vaddl_u16
(uint16x4_t a, a → Vn.4H UADDL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint64x2_t vaddl_u32
(uint32x2_t a, a → Vn.2S UADDL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

int16x8_t vaddl_high_s8
(int8x16_t a, a → Vn.16B SADDL2 Vd.8H,Vn.16B,Vm.16B Vd.8H ARMv8(AArch64)
int8x16_t b) b → Vm.16B

int32x4_t vaddl_high_s16
(int16x8_t a, a → Vn.8H SADDL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int64x2_t vaddl_high_s32
(int32x4_t a, a → Vn.4S SADDL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
int32x4_t b) b → Vm.4S

uint16x8_t vaddl_high_u8
(uint8x16_t a, a → Vn.16B UADDL2 Vd.8H,Vn.16B,Vm.16B Vd.8H ARMv8(AArch64)
uint8x16_t b) b → Vm.16B

uint32x4_t vaddl_high_u16
(uint16x8_t a, a → Vn.8H UADDL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
uint16x8_t b) b → Vm.8H

uint64x2_t vaddl_high_u32
(uint32x4_t a, a → Vn.4S UADDL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
uint32x4_t b) b → Vm.4S

int16x8_t vaddw_s8
(int16x8_t a, a → Vn.8H SADDW Vd.8H,Vn.8H,Vm.8B Vd.8H ARMv7, ARMv8
int8x8_t b) b → Vm.8B

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int32x4_t vaddw_s16
(int32x4_t a, a → Vn.4S SADDW Vd.4S,Vn.4S,Vm.4H Vd.4S ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int64x2_t vaddw_s32
(int64x2_t a, a → Vn.2D SADDW Vd.2D,Vn.2D,Vm.2S Vd.2D ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint16x8_t vaddw_u8
(uint16x8_t a, a → Vn.8H UADDW Vd.8H,Vn.8H,Vm.8B Vd.8H ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint32x4_t vaddw_u16
(uint32x4_t a, a → Vn.4S UADDW Vd.4S,Vn.4S,Vm.4H Vd.4S ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint64x2_t vaddw_u32
(uint64x2_t a, a → Vn.2D UADDW Vd.2D,Vn.2D,Vm.2S Vd.2D ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

int16x8_t vaddw_high_s8
(int16x8_t a, a → Vn.8H SADDW2 Vd.8H,Vn.8H,Vm.16B Vd.8H ARMv8(AArch64)
int8x16_t b) b → Vm.16B

int32x4_t vaddw_high_s16
(int32x4_t a, a → Vn.4S SADDW2 Vd.4S,Vn.4S,Vm.8H Vd.4S ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int64x2_t vaddw_high_s32
(int64x2_t a, a → Vn.2D SADDW2 Vd.2D,Vn.2D,Vm.4S Vd.2D ARMv8(AArch64)
int32x4_t b) b → Vm.4S

uint16x8_t vaddw_high_u8
(uint16x8_t a, a → Vn.8H UADDW2 Vd.8H,Vn.8H,Vm.16B Vd.8H ARMv8(AArch64)
uint8x16_t b) b → Vm.16B

uint32x4_t vaddw_high_u16
(uint32x4_t a, a → Vn.4S UADDW2 Vd.4S,Vn.4S,Vm.8H Vd.4S ARMv8(AArch64)
uint16x8_t b) b → Vm.8H

uint64x2_t vaddw_high_u32
(uint64x2_t a, a → Vn.2D UADDW2 Vd.2D,Vn.2D,Vm.4S Vd.2D ARMv8(AArch64)
uint32x4_t b) b → Vm.4S

int8x8_t vhadd_s8
(int8x8_t a, a → Vn.8B SHADD Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

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int8x16_t vhaddq_s8
(int8x16_t a, a → Vn.16B SHADD Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vhadd_s16
(int16x4_t a, a → Vn.4H SHADD Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int16x8_t vhaddq_s16
(int16x8_t a, a → Vn.8H SHADD Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vhadd_s32
(int32x2_t a, a → Vn.2S SHADD Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

int32x4_t vhaddq_s32
(int32x4_t a, a → Vn.4S SHADD Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint8x8_t vhadd_u8
(uint8x8_t a, a → Vn.8B UHADD Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vhaddq_u8
(uint8x16_t a, a → Vn.16B UHADD Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vhadd_u16
(uint16x4_t a, a → Vn.4H UHADD Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vhaddq_u16
(uint16x8_t a, a → Vn.8H UHADD Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vhadd_u32
(uint32x2_t a, a → Vn.2S UHADD Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

uint32x4_t vhaddq_u32
(uint32x4_t a, a → Vn.4S UHADD Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

int8x8_t vrhadd_s8
(int8x8_t a, a → Vn.8B SRHADD Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

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int8x16_t vrhaddq_s8
(int8x16_t a, a → Vn.16B SRHADD Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vrhadd_s16
(int16x4_t a, a → Vn.4H SRHADD Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int16x8_t vrhaddq_s16
(int16x8_t a, a → Vn.8H SRHADD Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vrhadd_s32
(int32x2_t a, a → Vn.2S SRHADD Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

int32x4_t vrhaddq_s32
(int32x4_t a, a → Vn.4S SRHADD Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint8x8_t vrhadd_u8
(uint8x8_t a, a → Vn.8B URHADD Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vrhaddq_u8
(uint8x16_t a, a → Vn.16B URHADD Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vrhadd_u16
(uint16x4_t a, a → Vn.4H URHADD Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vrhaddq_u16
(uint16x8_t a, a → Vn.8H URHADD Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vrhadd_u32
(uint32x2_t a, a → Vn.2S URHADD Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

uint32x4_t vrhaddq_u32
(uint32x4_t a, a → Vn.4S URHADD Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

int8x8_t vqadd_s8
(int8x8_t a, a → Vn.8B SQADD Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

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int8x16_t vqaddq_s8
(int8x16_t a, a → Vn.16B SQADD Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vqadd_s16
(int16x4_t a, a → Vn.4H SQADD Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int16x8_t vqaddq_s16
(int16x8_t a, a → Vn.8H SQADD Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vqadd_s32
(int32x2_t a, a → Vn.2S SQADD Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

int32x4_t vqaddq_s32
(int32x4_t a, a → Vn.4S SQADD Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

int64x1_t vqadd_s64
(int64x1_t a, a → Dn SQADD Dd,Dn,Dm Dd ARMv7, ARMv8
int64x1_t b) b → Dm

int64x2_t vqaddq_s64
(int64x2_t a, a → Vn.2D SQADD Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
int64x2_t b) b → Vm.2D

uint8x8_t vqadd_u8
(uint8x8_t a, a → Vn.8B UQADD Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vqaddq_u8
(uint8x16_t a, a → Vn.16B UQADD Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vqadd_u16
(uint16x4_t a, a → Vn.4H UQADD Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vqaddq_u16
(uint16x8_t a, a → Vn.8H UQADD Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vqadd_u32
(uint32x2_t a, a → Vn.2S UQADD Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

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uint32x4_t vqaddq_u32
(uint32x4_t a, a → Vn.4S UQADD Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

uint64x1_t vqadd_u64
(uint64x1_t a, a → Dn UQADD Dd,Dn,Dm Dd ARMv7, ARMv8
uint64x1_t b) b → Dm

uint64x2_t vqaddq_u64
(uint64x2_t a, a → Vn.2D UQADD Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
uint64x2_t b) b → Vm.2D

int8_t vqaddb_s8
(int8_t a, a → Bn SQADD Bd,Bn,Bm Bd ARMv8(AArch64)
int8_t b) b → Bm

int16_t vqaddh_s16
(int16_t a, a → Hn SQADD Hd,Hn,Hm Hd ARMv8(AArch64)
int16_t b) b → Hm

int32_t vqadds_s32
(int32_t a, a → Sn SQADD Sd,Sn,Sm Sd ARMv8(AArch64)
int32_t b) b → Sm

int64_t vqaddd_s64
(int64_t a, a → Dn SQADD Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

uint8_t vqaddb_u8
(uint8_t a, a → Bn UQADD Bd,Bn,Bm Bd ARMv8(AArch64)
uint8_t b) b → Bm

uint16_t vqaddh_u16
(uint16_t a, a → Hn UQADD Hd,Hn,Hm Hd ARMv8(AArch64)
uint16_t b) b → Hm

uint32_t vqadds_u32
(uint32_t a, a → Sn UQADD Sd,Sn,Sm Sd ARMv8(AArch64)
uint32_t b) b → Sm

uint64_t vqaddd_u64
(uint64_t a, a → Dn UQADD Dd,Dn,Dm Dd ARMv8(AArch64)
uint64_t b) b → Dm

int8x8_t vuqadd_s8
(int8x8_t a, a → Vd.8B SUQADD Vd.8B,Vn.8B Vd.8B ARMv8(AArch64)
uint8x8_t b) b → Vn.8B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 13 of 348
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int8x16_t vuqaddq_s8
(int8x16_t a, a → Vd.16B SUQADD Vd.16B,Vn.16B Vd.16B ARMv8(AArch64)
uint8x16_t b) b → Vn.16B

int16x4_t vuqadd_s16
(int16x4_t a, a → Vd.4H SUQADD Vd.4H,Vn.4H Vd.4H ARMv8(AArch64)
uint16x4_t b) b → Vn.4H

int16x8_t vuqaddq_s16
(int16x8_t a, a → Vd.8H SUQADD Vd.8H,Vn.8H Vd.8H ARMv8(AArch64)
uint16x8_t b) b → Vn.8H

int32x2_t vuqadd_s32
(int32x2_t a, a → Vd.2S SUQADD Vd.2S,Vn.2S Vd.2S ARMv8(AArch64)
uint32x2_t b) b → Vn.2S

int32x4_t vuqaddq_s32
(int32x4_t a, a → Vd.4S SUQADD Vd.4S,Vn.4S Vd.4S ARMv8(AArch64)
uint32x4_t b) b → Vn.4S

int64x1_t vuqadd_s64
(int64x1_t a, a → Dd SUQADD Dd,Dn Dd ARMv8(AArch64)
uint64x1_t b) b → Dn

int64x2_t vuqaddq_s64
(int64x2_t a, a → Vd.2D SUQADD Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
uint64x2_t b) b → Vn.2D

int8_t vuqaddb_s8
(int8_t a, a → Bd SUQADD Bd,Bn Bd ARMv8(AArch64)
uint8_t b) b → Bn

int16_t vuqaddh_s16
(int16_t a, a → Hd SUQADD Hd,Hn Hd ARMv8(AArch64)
uint16_t b) b → Hn

int32_t vuqadds_s32
(int32_t a, a → Sd SUQADD Sd,Sn Sd ARMv8(AArch64)
uint32_t b) b → Sn

int64_t vuqaddd_s64
(int64_t a, a → Dd SUQADD Dd,Dn Dd ARMv8(AArch64)
uint64_t b) b → Dn

uint8x8_t vsqadd_u8
(uint8x8_t a, a → Vd.8B USQADD Vd.8B,Vn.8B Vd.8B ARMv8(AArch64)
int8x8_t b) b → Vn.8B

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uint8x16_t vsqaddq_u8
(uint8x16_t a, a → Vd.16B USQADD Vd.16B,Vn.16B Vd.16B ARMv8(AArch64)
int8x16_t b) b → Vn.16B

uint16x4_t vsqadd_u16
(uint16x4_t a, a → Vd.4H USQADD Vd.4H,Vn.4H Vd.4H ARMv8(AArch64)
int16x4_t b) b → Vn.4H

uint16x8_t vsqaddq_u16
(uint16x8_t a, a → Vd.8H USQADD Vd.8H,Vn.8H Vd.8H ARMv8(AArch64)
int16x8_t b) b → Vn.8H

uint32x2_t vsqadd_u32
(uint32x2_t a, a → Vd.2S USQADD Vd.2S,Vn.2S Vd.2S ARMv8(AArch64)
int32x2_t b) b → Vn.2S

uint32x4_t vsqaddq_u32
(uint32x4_t a, a → Vd.4S USQADD Vd.4S,Vn.4S Vd.4S ARMv8(AArch64)
int32x4_t b) b → Vn.4S

uint64x1_t vsqadd_u64
(uint64x1_t a, a → Dd USQADD Dd,Dn Dd ARMv8(AArch64)
int64x1_t b) b → Dn

uint64x2_t vsqaddq_u64
(uint64x2_t a, a → Vd.2D USQADD Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
int64x2_t b) b → Vn.2D

uint8_t vsqaddb_u8
(uint8_t a, a → Bd USQADD Bd,Bn Bd ARMv8(AArch64)
int8_t b) b → Bn

uint16_t vsqaddh_u16
(uint16_t a, a → Hd USQADD Hd,Hn Hd ARMv8(AArch64)
int16_t b) b → Hn

uint32_t vsqadds_u32
(uint32_t a, a → Sd USQADD Sd,Sn Sd ARMv8(AArch64)
int32_t b) b → Sn

uint64_t vsqaddd_u64
(uint64_t a, a → Dd USQADD Dd,Dn Dd ARMv8(AArch64)
int64_t b) b → Dn

int8x8_t vaddhn_s16
(int16x8_t a, a → Vn.8H ADDHN Vd.8B,Vn.8H,Vm.8H Vd.8B ARMv7, ARMv8
int16x8_t b) b → Vm.8H

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 15 of 348
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int16x4_t vaddhn_s32
(int32x4_t a, a → Vn.4S ADDHN Vd.4H,Vn.4S,Vm.4S Vd.4H ARMv7, ARMv8
int32x4_t b) b → Vm.4S

int32x2_t vaddhn_s64
(int64x2_t a, a → Vn.2D ADDHN Vd.2S,Vn.2D,Vm.2D Vd.2S ARMv7, ARMv8
int64x2_t b) b → Vm.2D

uint8x8_t vaddhn_u16
(uint16x8_t a, a → Vn.8H ADDHN Vd.8B,Vn.8H,Vm.8H Vd.8B ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint16x4_t vaddhn_u32
(uint32x4_t a, a → Vn.4S ADDHN Vd.4H,Vn.4S,Vm.4S Vd.4H ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

uint32x2_t vaddhn_u64
(uint64x2_t a, a → Vn.2D ADDHN Vd.2S,Vn.2D,Vm.2D Vd.2S ARMv7, ARMv8
uint64x2_t b) b → Vm.2D

int8x16_t vaddhn_high_s16
(int8x8_t r, r → Vd.8B
ADDHN2 Vd.16B,Vn.8H,Vm.8H Vd.16B ARMv8(AArch64)
int16x8_t a, a → Vn.8H
int16x8_t b) b → Vm.8H

int16x8_t vaddhn_high_s32
(int16x4_t r, r → Vd.4H
ADDHN2 Vd.8H,Vn.4S,Vm.4S Vd.8H ARMv8(AArch64)
int32x4_t a, a → Vn.4S
int32x4_t b) b → Vm.4S

int32x4_t vaddhn_high_s64
(int32x2_t r, r → Vd.2S
ADDHN2 Vd.4S,Vn.2D,Vm.2D Vd.4S ARMv8(AArch64)
int64x2_t a, a → Vn.2D
int64x2_t b) b → Vm.2D

uint8x16_t vaddhn_high_u16
(uint8x8_t r, r → Vd.8B
ADDHN2 Vd.16B,Vn.8H,Vm.8H Vd.16B ARMv8(AArch64)
uint16x8_t a, a → Vn.8H
uint16x8_t b) b → Vm.8H

uint16x8_t vaddhn_high_u32
(uint16x4_t r, r → Vd.4H
ADDHN2 Vd.8H,Vn.4S,Vm.4S Vd.8H ARMv8(AArch64)
uint32x4_t a, a → Vn.4S
uint32x4_t b) b → Vm.4S

uint32x4_t vaddhn_high_u64
(uint32x2_t r, r → Vd.2S
ADDHN2 Vd.4S,Vn.2D,Vm.2D Vd.4S ARMv8(AArch64)
uint64x2_t a, a → Vn.2D
uint64x2_t b) b → Vm.2D

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int8x8_t vraddhn_s16
(int16x8_t a, a → Vn.8H RADDHN Vd.8B,Vn.8H,Vm.8H Vd.8B ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int16x4_t vraddhn_s32
(int32x4_t a, a → Vn.4S RADDHN Vd.4H,Vn.4S,Vm.4S Vd.4H ARMv7, ARMv8
int32x4_t b) b → Vm.4S

int32x2_t vraddhn_s64
(int64x2_t a, a → Vn.2D RADDHN Vd.2S,Vn.2D,Vm.2D Vd.2S ARMv7, ARMv8
int64x2_t b) b → Vm.2D

uint8x8_t vraddhn_u16
(uint16x8_t a, a → Vn.8H RADDHN Vd.8B,Vn.8H,Vm.8H Vd.8B ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint16x4_t vraddhn_u32
(uint32x4_t a, a → Vn.4S RADDHN Vd.4H,Vn.4S,Vm.4S Vd.4H ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

uint32x2_t vraddhn_u64
(uint64x2_t a, a → Vn.2D RADDHN Vd.2S,Vn.2D,Vm.2D Vd.2S ARMv7, ARMv8
uint64x2_t b) b → Vm.2D

int8x16_t vraddhn_high_s16
(int8x8_t r, r → Vd.8B
RADDHN2 Vd.16B,Vn.8H,Vm.8H Vd.16B ARMv8(AArch64)
int16x8_t a, a → Vn.8H
int16x8_t b) b → Vm.8H

int16x8_t vraddhn_high_s32
(int16x4_t r, r → Vd.4H
RADDHN2 Vd.8H,Vn.4S,Vm.4S Vd.8H ARMv8(AArch64)
int32x4_t a, a → Vn.4S
int32x4_t b) b → Vm.4S

int32x4_t vraddhn_high_s64
(int32x2_t r, r → Vd.2S
RADDHN2 Vd.4S,Vn.2D,Vm.2D Vd.4S ARMv8(AArch64)
int64x2_t a, a → Vn.2D
int64x2_t b) b → Vm.2D

uint8x16_t vraddhn_high_u16
(uint8x8_t r, r → Vd.8B
RADDHN2 Vd.16B,Vn.8H,Vm.8H Vd.16B ARMv8(AArch64)
uint16x8_t a, a → Vn.8H
uint16x8_t b) b → Vm.8H

uint16x8_t vraddhn_high_u32
(uint16x4_t r, r → Vd.4H
RADDHN2 Vd.8H,Vn.4S,Vm.4S Vd.8H ARMv8(AArch64)
uint32x4_t a, a → Vn.4S
uint32x4_t b) b → Vm.4S

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Non-Confidential
uint32x4_t vraddhn_high_u64
(uint32x2_t r, r → Vd.2S
RADDHN2 Vd.4S,Vn.2D,Vm.2D Vd.4S ARMv8(AArch64)
uint64x2_t a, a → Vn.2D
uint64x2_t b) b → Vm.2D

int8x8_t vmul_s8
(int8x8_t a, a → Vn.8B MUL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int8x16_t vmulq_s8
(int8x16_t a, a → Vn.16B MUL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vmul_s16
(int16x4_t a, a → Vn.4H MUL Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int16x8_t vmulq_s16
(int16x8_t a, a → Vn.8H MUL Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vmul_s32
(int32x2_t a, a → Vn.2S MUL Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

int32x4_t vmulq_s32
(int32x4_t a, a → Vn.4S MUL Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint8x8_t vmul_u8
(uint8x8_t a, a → Vn.8B MUL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vmulq_u8
(uint8x16_t a, a → Vn.16B MUL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vmul_u16
(uint16x4_t a, a → Vn.4H MUL Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vmulq_u16
(uint16x8_t a, a → Vn.8H MUL Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vmul_u32
(uint32x2_t a, a → Vn.2S MUL Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 18 of 348
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uint32x4_t vmulq_u32
(uint32x4_t a, a → Vn.4S MUL Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

float32x2_t vmul_f32
(float32x2_t a, a → Vn.2S FMUL Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

float32x4_t vmulq_f32
(float32x4_t a, a → Vn.4S FMUL Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

poly8x8_t vmul_p8
(poly8x8_t a, a → Vn.8B PMUL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
poly8x8_t b) b → Vm.8B

poly8x16_t vmulq_p8
(poly8x16_t a, a → Vn.16B PMUL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
poly8x16_t b) b → Vm.16B

float64x1_t vmul_f64
(float64x1_t a, a → Dn FMUL Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

float64x2_t vmulq_f64
(float64x2_t a, a → Vn.2D FMUL Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

float32x2_t vmulx_f32
(float32x2_t a, a → Vn.2S FMULX Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
float32x2_t b) b → Vm.2S

float32x4_t vmulxq_f32
(float32x4_t a, a → Vn.4S FMULX Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
float32x4_t b) b → Vm.4S

float64x1_t vmulx_f64
(float64x1_t a, a → Dn FMULX Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

float64x2_t vmulxq_f64
(float64x2_t a, a → Vn.2D FMULX Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

float32_t vmulxs_f32
(float32_t a, a → Sn FMULX Sd,Sn,Sm Sd ARMv8(AArch64)
float32_t b) b → Sm

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 19 of 348
Non-Confidential
float64_t vmulxd_f64
(float64_t a, a → Dn FMULX Dd,Dn,Dm Dd ARMv8(AArch64)
float64_t b) b → Dm

float32x2_t vmulx_lane_f32
(float32x2_t a, a → Vn.2S
FMULX Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv8(AArch64)
float32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

float32x4_t vmulxq_lane_f32
(float32x4_t a, a → Vn.4S
FMULX Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv8(AArch64)
float32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

float64x1_t vmulx_lane_f64
(float64x1_t a, a → Dn
FMULX Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x1_t v, v → Vm.1D
const int lane) lane == 0

float64x2_t vmulxq_lane_f64
(float64x2_t a, a → Vn.2D
FMULX Vd.2D,Vn.2D,Vm.D[lane] Vd.2D ARMv8(AArch64)
float64x1_t v, v → Vm.1D
const int lane) lane == 0

float32_t vmulxs_lane_f32
(float32_t a, a → Sn
FMULX Sd,Sn,Vm.S[lane] Sd ARMv8(AArch64)
float32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

float64_t vmulxd_lane_f64
(float64_t a, a → Dn
FMULX Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x1_t v, v → Vm.1D
const int lane) lane == 0

float32x2_t vmulx_laneq_f32
(float32x2_t a, a → Vn.2S
FMULX Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv8(AArch64)
float32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

float32x4_t vmulxq_laneq_f32
(float32x4_t a, a → Vn.4S
FMULX Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv8(AArch64)
float32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

float64x1_t vmulx_laneq_f64
(float64x1_t a, a → Dn
FMULX Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x2_t v, v → Vm.2D
const int lane) 0 <= lane <= 1

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 20 of 348
Non-Confidential
float64x2_t vmulxq_laneq_f64
(float64x2_t a, a → Vn.2D
FMULX Vd.2D,Vn.2D,Vm.D[lane] Vd.2D ARMv8(AArch64)
float64x2_t v, v → Vm.2D
const int lane) 0 <= lane <= 1

float32_t vmulxs_laneq_f32
(float32_t a, a → Sn
FMULX Sd,Sn,Vm.S[lane] Sd ARMv8(AArch64)
float32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

float64_t vmulxd_laneq_f64
(float64_t a, a → Dn
FMULX Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x2_t v, v → Vm.2D
const int lane) 0 <= lane <= 1

float32x2_t vdiv_f32
(float32x2_t a, a → Vn.2S FDIV Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
float32x2_t b) b → Vm.2S

float32x4_t vdivq_f32
(float32x4_t a, a → Vn.4S FDIV Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
float32x4_t b) b → Vm.4S

float64x1_t vdiv_f64
(float64x1_t a, a → Dn FDIV Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

float64x2_t vdivq_f64
(float64x2_t a, a → Vn.2D FDIV Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

int8x8_t vmla_s8
(int8x8_t a, a → Vd.8B
MLA Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b, b → Vn.8B
int8x8_t c) c → Vm.8B

int8x16_t vmlaq_s8
(int8x16_t a, a → Vd.16B
MLA Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b, b → Vn.16B
int8x16_t c) c → Vm.16B

int16x4_t vmla_s16
(int16x4_t a, a → Vd.4H
MLA Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b, b → Vn.4H
int16x4_t c) c → Vm.4H

int16x8_t vmlaq_s16
(int16x8_t a, a → Vd.8H
MLA Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b, b → Vn.8H
int16x8_t c) c → Vm.8H

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int32x2_t vmla_s32
(int32x2_t a, a → Vd.2S
MLA Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b, b → Vn.2S
int32x2_t c) c → Vm.2S

int32x4_t vmlaq_s32
(int32x4_t a, a → Vd.4S
MLA Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b, b → Vn.4S
int32x4_t c) c → Vm.4S

uint8x8_t vmla_u8
(uint8x8_t a, a → Vd.8B
MLA Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b, b → Vn.8B
uint8x8_t c) c → Vm.8B

uint8x16_t vmlaq_u8
(uint8x16_t a, a → Vd.16B
MLA Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b, b → Vn.16B
uint8x16_t c) c → Vm.16B

uint16x4_t vmla_u16
(uint16x4_t a, a → Vd.4H
MLA Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b, b → Vn.4H
uint16x4_t c) c → Vm.4H

uint16x8_t vmlaq_u16
(uint16x8_t a, a → Vd.8H
MLA Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b, b → Vn.8H
uint16x8_t c) c → Vm.8H

uint32x2_t vmla_u32
(uint32x2_t a, a → Vd.2S
MLA Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b, b → Vn.2S
uint32x2_t c) c → Vm.2S

uint32x4_t vmlaq_u32
(uint32x4_t a, a → Vd.4S
MLA Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b, b → Vn.4S
uint32x4_t c) c → Vm.4S

float32x2_t vmla_f32
(float32x2_t a, a → N/A RESULT[I] = a[i] + (b[i] * c[i]) for i = 0
N/A ARMv7, ARMv8
float32x2_t b, b → N/A to 1
float32x2_t c) c → N/A

float32x4_t vmlaq_f32
(float32x4_t a, a → N/A RESULT[I] = a[i] + (b[i] * c[i]) for i = 0
N/A ARMv7, ARMv8
float32x4_t b, b → N/A to 3
float32x4_t c) c → N/A

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float64x1_t vmla_f64
(float64x1_t a, a → N/A
RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 N/A ARMv8(AArch64)
float64x1_t b, b → N/A
float64x1_t c) c → N/A

float64x2_t vmlaq_f64
(float64x2_t a, a → N/A RESULT[I] = a[i] + (b[i] * c[i]) for i = 0
N/A ARMv8(AArch64)
float64x2_t b, b → N/A to 1
float64x2_t c) c → N/A

int16x8_t vmlal_s8
(int16x8_t a, a → Vd.8H
SMLAL Vd.8H,Vn.8B,Vm.8B Vd.8H ARMv7, ARMv8
int8x8_t b, b → Vn.8B
int8x8_t c) c → Vm.8B

int32x4_t vmlal_s16
(int32x4_t a, a → Vd.4S
SMLAL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
int16x4_t b, b → Vn.4H
int16x4_t c) c → Vm.4H

int64x2_t vmlal_s32
(int64x2_t a, a → Vd.2D
SMLAL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
int32x2_t b, b → Vn.2S
int32x2_t c) c → Vm.2S

uint16x8_t vmlal_u8
(uint16x8_t a, a → Vd.8H
UMLAL Vd.8H,Vn.8B,Vm.8B Vd.8H ARMv7, ARMv8
uint8x8_t b, b → Vn.8B
uint8x8_t c) c → Vm.8B

uint32x4_t vmlal_u16
(uint32x4_t a, a → Vd.4S
UMLAL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
uint16x4_t b, b → Vn.4H
uint16x4_t c) c → Vm.4H

uint64x2_t vmlal_u32
(uint64x2_t a, a → Vd.2D
UMLAL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
uint32x2_t b, b → Vn.2S
uint32x2_t c) c → Vm.2S

int16x8_t vmlal_high_s8
(int16x8_t a, a → Vd.8H
SMLAL2 Vd.8H,Vn.16B,Vm.16B Vd.8H ARMv8(AArch64)
int8x16_t b, b → Vn.16B
int8x16_t c) c → Vm.16B

int32x4_t vmlal_high_s16
(int32x4_t a, a → Vd.4S
SMLAL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
int16x8_t b, b → Vn.8H
int16x8_t c) c → Vm.8H

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int64x2_t vmlal_high_s32
(int64x2_t a, a → Vd.2D
SMLAL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
int32x4_t b, b → Vn.4S
int32x4_t c) c → Vm.4S

uint16x8_t vmlal_high_u8
(uint16x8_t a, a → Vd.8H
UMLAL2 Vd.8H,Vn.16B,Vm.16B Vd.8H ARMv8(AArch64)
uint8x16_t b, b → Vn.16B
uint8x16_t c) c → Vm.16B

uint32x4_t vmlal_high_u16
(uint32x4_t a, a → Vd.4S
UMLAL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
uint16x8_t b, b → Vn.8H
uint16x8_t c) c → Vm.8H

uint64x2_t vmlal_high_u32
(uint64x2_t a, a → Vd.2D
UMLAL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
uint32x4_t b, b → Vn.4S
uint32x4_t c) c → Vm.4S

int8x8_t vmls_s8
(int8x8_t a, a → Vd.8B
MLS Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b, b → Vn.8B
int8x8_t c) c → Vm.8B

int8x16_t vmlsq_s8
(int8x16_t a, a → Vd.16B
MLS Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b, b → Vn.16B
int8x16_t c) c → Vm.16B

int16x4_t vmls_s16
(int16x4_t a, a → Vd.4H
MLS Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b, b → Vn.4H
int16x4_t c) c → Vm.4H

int16x8_t vmlsq_s16
(int16x8_t a, a → Vd.8H
MLS Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b, b → Vn.8H
int16x8_t c) c → Vm.8H

int32x2_t vmls_s32
(int32x2_t a, a → Vd.2S
MLS Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b, b → Vn.2S
int32x2_t c) c → Vm.2S

int32x4_t vmlsq_s32
(int32x4_t a, a → Vd.4S
MLS Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b, b → Vn.4S
int32x4_t c) c → Vm.4S

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uint8x8_t vmls_u8
(uint8x8_t a, a → Vd.8B
MLS Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b, b → Vn.8B
uint8x8_t c) c → Vm.8B

uint8x16_t vmlsq_u8
(uint8x16_t a, a → Vd.16B
MLS Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b, b → Vn.16B
uint8x16_t c) c → Vm.16B

uint16x4_t vmls_u16
(uint16x4_t a, a → Vd.4H
MLS Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b, b → Vn.4H
uint16x4_t c) c → Vm.4H

uint16x8_t vmlsq_u16
(uint16x8_t a, a → Vd.8H
MLS Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b, b → Vn.8H
uint16x8_t c) c → Vm.8H

uint32x2_t vmls_u32
(uint32x2_t a, a → Vd.2S
MLS Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b, b → Vn.2S
uint32x2_t c) c → Vm.2S

uint32x4_t vmlsq_u32
(uint32x4_t a, a → Vd.4S
MLS Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b, b → Vn.4S
uint32x4_t c) c → Vm.4S

float32x2_t vmls_f32
(float32x2_t a, a → N/A RESULT[I] = a[i] - (b[i] * c[i]) for i = 0
N/A ARMv7, ARMv8
float32x2_t b, b → N/A to 1
float32x2_t c) c → N/A

float32x4_t vmlsq_f32
(float32x4_t a, a → N/A RESULT[I] = a[i] - (b[i] * c[i]) for i = 0
N/A ARMv7, ARMv8
float32x4_t b, b → N/A to 3
float32x4_t c) c → N/A

float64x1_t vmls_f64
(float64x1_t a, a → N/A
RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 N/A ARMv8(AArch64)
float64x1_t b, b → N/A
float64x1_t c) c → N/A

float64x2_t vmlsq_f64
(float64x2_t a, a → N/A RESULT[I] = a[i] - (b[i] * c[i]) for i = 0
N/A ARMv8(AArch64)
float64x2_t b, b → N/A to 1
float64x2_t c) c → N/A

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int16x8_t vmlsl_s8
(int16x8_t a, a → Vd.8H
SMLSL Vd.8H,Vn.8B,Vm.8B Vd.8H ARMv7, ARMv8
int8x8_t b, b → Vn.8B
int8x8_t c) c → Vm.8B

int32x4_t vmlsl_s16
(int32x4_t a, a → Vd.4S
SMLSL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
int16x4_t b, b → Vn.4H
int16x4_t c) c → Vm.4H

int64x2_t vmlsl_s32
(int64x2_t a, a → Vd.2D
SMLSL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
int32x2_t b, b → Vn.2S
int32x2_t c) c → Vm.2S

uint16x8_t vmlsl_u8
(uint16x8_t a, a → Vd.8H
UMLSL Vd.8H,Vn.8B,Vm.8B Vd.8H ARMv7, ARMv8
uint8x8_t b, b → Vn.8B
uint8x8_t c) c → Vm.8B

uint32x4_t vmlsl_u16
(uint32x4_t a, a → Vd.4S
UMLSL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
uint16x4_t b, b → Vn.4H
uint16x4_t c) c → Vm.4H

uint64x2_t vmlsl_u32
(uint64x2_t a, a → Vd.2D
UMLSL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
uint32x2_t b, b → Vn.2S
uint32x2_t c) c → Vm.2S

int16x8_t vmlsl_high_s8
(int16x8_t a, a → Vd.8H
SMLSL2 Vd.8H,Vn.16B,Vm.16B Vd.8H ARMv8(AArch64)
int8x16_t b, b → Vn.16B
int8x16_t c) c → Vm.16B

int32x4_t vmlsl_high_s16
(int32x4_t a, a → Vd.4S
SMLSL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
int16x8_t b, b → Vn.8H
int16x8_t c) c → Vm.8H

int64x2_t vmlsl_high_s32
(int64x2_t a, a → Vd.2D
SMLSL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
int32x4_t b, b → Vn.4S
int32x4_t c) c → Vm.4S

uint16x8_t vmlsl_high_u8
(uint16x8_t a, a → Vd.8H
UMLSL2 Vd.8H,Vn.16B,Vm.16B Vd.8H ARMv8(AArch64)
uint8x16_t b, b → Vn.16B
uint8x16_t c) c → Vm.16B

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uint32x4_t vmlsl_high_u16
(uint32x4_t a, a → Vd.4S
UMLSL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
uint16x8_t b, b → Vn.8H
uint16x8_t c) c → Vm.8H

uint64x2_t vmlsl_high_u32
(uint64x2_t a, a → Vd.2D
UMLSL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
uint32x4_t b, b → Vn.4S
uint32x4_t c) c → Vm.4S

float32x2_t vfma_f32
(float32x2_t a, a → Vd.2S
FMLA Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b, b → Vn.2S
float32x2_t c) c → Vm.2S

float32x4_t vfmaq_f32
(float32x4_t a, a → Vd.4S
FMLA Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
float32x4_t b, b → Vn.4S
float32x4_t c) c → Vm.4S

float64x1_t vfma_f64
(float64x1_t a, a → Da
FMADD Dd,Dn,Dm,Da Dd ARMv8(AArch64)
float64x1_t b, b → Dn
float64x1_t c) c → Dm

float64x2_t vfmaq_f64
(float64x2_t a, a → Vd.2D
FMLA Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b, b → Vn.2D
float64x2_t c) c → Vm.2D

float32x2_t vfma_lane_f32
(float32x2_t a, a → Vd.2S
float32x2_t b, b → Vn.2S FMLA Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv8(AArch64)
float32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

float32x4_t vfmaq_lane_f32
(float32x4_t a, a → Vd.4S
float32x4_t b, b → Vn.4S FMLA Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv8(AArch64)
float32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

float64x1_t vfma_lane_f64
(float64x1_t a, a → Dd
float64x1_t b, b → Dn FMLA Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x1_t v, v → Vm.1D
const int lane) lane == 0

float64x2_t vfmaq_lane_f64
(float64x2_t a, a → Vd.2D
float64x2_t b, b → Vn.2D FMLA Vd.2D,Vn.2D,Vm.D[lane] Vd.2D ARMv8(AArch64)
float64x1_t v, v → Vm.1D
const int lane) lane == 0

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float32_t vfmas_lane_f32
(float32_t a, a → Sd
float32_t b, b → Sn FMLA Sd,Sn,Vm.S[lane] Sd ARMv8(AArch64)
float32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

float64_t vfmad_lane_f64
(float64_t a, a → Dd
float64_t b, b → Dn FMLA Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x1_t v, v → Vm.1D
const int lane) lane == 0

float32x2_t vfma_laneq_f32
(float32x2_t a, a → Vd.2S
float32x2_t b, b → Vn.2S FMLA Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv8(AArch64)
float32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

float32x4_t vfmaq_laneq_f32
(float32x4_t a, a → Vd.4S
float32x4_t b, b → Vn.4S FMLA Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv8(AArch64)
float32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

float64x1_t vfma_laneq_f64
(float64x1_t a, a → Dd
float64x1_t b, b → Dn FMLA Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x2_t v, v → Vm.2D
const int lane) 0 <= lane <= 1

float64x2_t vfmaq_laneq_f64
(float64x2_t a, a → Vd.2D
float64x2_t b, b → Vn.2D FMLA Vd.2D,Vn.2D,Vm.D[lane] Vd.2D ARMv8(AArch64)
float64x2_t v, v → Vm.2D
const int lane) 0 <= lane <= 1

float32_t vfmas_laneq_f32
(float32_t a, a → Sd
float32_t b, b → Sn FMLA Sd,Sn,Vm.S[lane] Sd ARMv8(AArch64)
float32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

float64_t vfmad_laneq_f64
(float64_t a, a → Dd
float64_t b, b → Dn FMLA Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x2_t v, v → Vm.2D
const int lane) 0 <= lane <= 1

float32x2_t vfms_f32
(float32x2_t a, a → Vd.2S
FMLS Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b, b → Vn.2S
float32x2_t c) c → Vm.2S

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float32x4_t vfmsq_f32
(float32x4_t a, a → Vd.4S
FMLS Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
float32x4_t b, b → Vn.4S
float32x4_t c) c → Vm.4S

float64x1_t vfms_f64
(float64x1_t a, a → Da
FMSUB Dd,Dn,Dm,Da Dd ARMv8(AArch64)
float64x1_t b, b → Dn
float64x1_t c) c → Dm

float64x2_t vfmsq_f64
(float64x2_t a, a → Vd.2D
FMLS Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b, b → Vn.2D
float64x2_t c) c → Vm.2D

float32x2_t vfms_lane_f32
(float32x2_t a, a → Vd.2S
float32x2_t b, b → Vn.2S FMLS Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv8(AArch64)
float32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

float32x4_t vfmsq_lane_f32
(float32x4_t a, a → Vd.4S
float32x4_t b, b → Vn.4S FMLS Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv8(AArch64)
float32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

float64x1_t vfms_lane_f64
(float64x1_t a, a → Dd
float64x1_t b, b → Dn FMLS Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x1_t v, v → Vm.1D
const int lane) lane == 0

float64x2_t vfmsq_lane_f64
(float64x2_t a, a → Vd.2D
float64x2_t b, b → Vn.2D FMLS Vd.2D,Vn.2D,Vm.D[lane] Vd.2D ARMv8(AArch64)
float64x1_t v, v → Vm.1D
const int lane) lane == 0

float32_t vfmss_lane_f32
(float32_t a, a → Sd
float32_t b, b → Sn FMLS Sd,Sn,Vm.S[lane] Sd ARMv8(AArch64)
float32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

float64_t vfmsd_lane_f64
(float64_t a, a → Dd
float64_t b, b → Dn FMLS Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x1_t v, v → Vm.1D
const int lane) lane == 0

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float32x2_t vfms_laneq_f32
(float32x2_t a, a → Vd.2S
float32x2_t b, b → Vn.2S FMLS Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv8(AArch64)
float32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

float32x4_t vfmsq_laneq_f32
(float32x4_t a, a → Vd.4S
float32x4_t b, b → Vn.4S FMLS Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv8(AArch64)
float32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

float64x1_t vfms_laneq_f64
(float64x1_t a, a → Dd
float64x1_t b, b → Dn FMLS Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x2_t v, v → Vm.2D
const int lane) 0 <= lane <= 1

float64x2_t vfmsq_laneq_f64
(float64x2_t a, a → Vd.2D
float64x2_t b, b → Vn.2D FMLS Vd.2D,Vn.2D,Vm.D[lane] Vd.2D ARMv8(AArch64)
float64x2_t v, v → Vm.2D
const int lane) 0 <= lane <= 1

float32_t vfmss_laneq_f32
(float32_t a, a → Sd
float32_t b, b → Sn FMLS Sd,Sn,Vm.S[lane] Sd ARMv8(AArch64)
float32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

float64_t vfmsd_laneq_f64
(float64_t a, a → Dd
float64_t b, b → Dn FMLS Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x2_t v, v → Vm.2D
const int lane) 0 <= lane <= 1

int16x4_t vqdmulh_s16
(int16x4_t a, a → Vn.4H SQDMULH Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int16x8_t vqdmulhq_s16
(int16x8_t a, a → Vn.8H SQDMULH Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vqdmulh_s32
(int32x2_t a, a → Vn.2S SQDMULH Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

int32x4_t vqdmulhq_s32
(int32x4_t a, a → Vn.4S SQDMULH Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

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int16_t vqdmulhh_s16
(int16_t a, a → Hn SQDMULH Hd,Hn,Hm Hd ARMv8(AArch64)
int16_t b) b → Hm

int32_t vqdmulhs_s32
(int32_t a, a → Sn SQDMULH Sd,Sn,Sm Sd ARMv8(AArch64)
int32_t b) b → Sm

int16x4_t vqrdmulh_s16
(int16x4_t a, a → Vn.4H SQRDMULH Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int16x8_t vqrdmulhq_s16
(int16x8_t a, a → Vn.8H SQRDMULH Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vqrdmulh_s32
(int32x2_t a, a → Vn.2S SQRDMULH Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

int32x4_t vqrdmulhq_s32
(int32x4_t a, a → Vn.4S SQRDMULH Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

int16_t vqrdmulhh_s16
(int16_t a, a → Hn SQRDMULH Hd,Hn,Hm Hd ARMv8(AArch64)
int16_t b) b → Hm

int32_t vqrdmulhs_s32
(int32_t a, a → Sn SQRDMULH Sd,Sn,Sm Sd ARMv8(AArch64)
int32_t b) b → Sm

int16x4_t vqrdmlah_s16
(int16x4_t a, a → Vd.4H
int16x4_t b, b → Vn.4H SQRDMLAH Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8
int16x4_t c) c → Vm.4H

int16x8_t vqrdmlahq_s16
(int16x8_t a, a → Vd.8H
int16x8_t b, b → Vn.8H SQRDMLAH Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8
int16x8_t c) c → Vm.8H

int32x2_t vqrdmlah_s32
(int32x2_t a, a → Vd.2S
int32x2_t b, b → Vn.2S SQRDMLAH Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8
int32x2_t c) c → Vm.2S

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int32x4_t vqrdmlahq_s32
(int32x4_t a, a → Vd.4S
int32x4_t b, b → Vn.4S SQRDMLAH Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8
int32x4_t c) c → Vm.4S

int16_t vqrdmlahh_s16
(int16_t a, a → Hd
int16_t b, b → Hn SQRDMLAH Hd,Hn,Hm Hd ARMv8(AArch64)
int16_t c) c → Hm

int32_t vqrdmlahs_s32
(int32_t a, a → Sd
int32_t b, b → Sn SQRDMLAH Sd,Sn,Sm Sd ARMv8(AArch64)
int32_t c) c → Sm

int16x4_t vqrdmlsh_s16
(int16x4_t a, a → Vd.4H
int16x4_t b, b → Vn.4H SQRDMLSH Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8
int16x4_t c) c → Vm.4H

int16x8_t vqrdmlshq_s16
(int16x8_t a, a → Vd.8H
int16x8_t b, b → Vn.8H SQRDMLSH Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8
int16x8_t c) c → Vm.8H

int32x2_t vqrdmlsh_s32
(int32x2_t a, a → Vd.2S
int32x2_t b, b → Vn.2S SQRDMLSH Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8
int32x2_t c) c → Vm.2S

int32x4_t vqrdmlshq_s32
(int32x4_t a, a → Vd.4S
int32x4_t b, b → Vn.4S SQRDMLSH Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8
int32x4_t c) c → Vm.4S

int16_t vqrdmlshh_s16
(int16_t a, a → Hd
int16_t b, b → Hn SQRDMLSH Hd,Hn,Hm Hd ARMv8(AArch64)
int16_t c) c → Hm

int32_t vqrdmlshs_s32
(int32_t a, a → Sd
int32_t b, b → Sn SQRDMLSH Sd,Sn,Sm Sd ARMv8(AArch64)
int32_t c) c → Sm

int32x4_t vqdmlal_s16
(int32x4_t a, a → Vd.4S
SQDMLAL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
int16x4_t b, b → Vn.4H
int16x4_t c) c → Vm.4H

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int64x2_t vqdmlal_s32
(int64x2_t a, a → Vd.2D
SQDMLAL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
int32x2_t b, b → Vn.2S
int32x2_t c) c → Vm.2S

int32_t vqdmlalh_s16
(int32_t a, a → Sd
SQDMLAL Sd,Hn,Hm Sd ARMv8(AArch64)
int16_t b, b → Hn
int16_t c) c → Hm

int64_t vqdmlals_s32
(int64_t a, a → Dd
SQDMLAL Dd,Sn,Sm Dd ARMv8(AArch64)
int32_t b, b → Sn
int32_t c) c → Sm

int32x4_t vqdmlal_high_s16
(int32x4_t a, a → Vd.4S
SQDMLAL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
int16x8_t b, b → Vn.8H
int16x8_t c) c → Vm.8H

int64x2_t vqdmlal_high_s32
(int64x2_t a, a → Vd.2D
SQDMLAL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
int32x4_t b, b → Vn.4S
int32x4_t c) c → Vm.4S

int32x4_t vqdmlsl_s16
(int32x4_t a, a → Vd.4S
SQDMLSL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
int16x4_t b, b → Vn.4H
int16x4_t c) c → Vm.4H

int64x2_t vqdmlsl_s32
(int64x2_t a, a → Vd.2D
SQDMLSL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
int32x2_t b, b → Vn.2S
int32x2_t c) c → Vm.2S

int32_t vqdmlslh_s16
(int32_t a, a → Sd
SQDMLSL Sd,Hn,Hm Sd ARMv8(AArch64)
int16_t b, b → Hn
int16_t c) c → Hm

int64_t vqdmlsls_s32
(int64_t a, a → Dd
SQDMLSL Dd,Sn,Sm Dd ARMv8(AArch64)
int32_t b, b → Sn
int32_t c) c → Sm

int32x4_t vqdmlsl_high_s16
(int32x4_t a, a → Vd.4S
SQDMLSL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
int16x8_t b, b → Vn.8H
int16x8_t c) c → Vm.8H

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int64x2_t vqdmlsl_high_s32
(int64x2_t a, a → Vd.2D
SQDMLSL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
int32x4_t b, b → Vn.4S
int32x4_t c) c → Vm.4S

int16x8_t vmull_s8
(int8x8_t a, a → Vn.8B SMULL Vd.8H,Vn.8B,Vm.8B Vd.8H ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int32x4_t vmull_s16
(int16x4_t a, a → Vn.4H SMULL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int64x2_t vmull_s32
(int32x2_t a, a → Vn.2S SMULL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint16x8_t vmull_u8
(uint8x8_t a, a → Vn.8B UMULL Vd.8H,Vn.8B,Vm.8B Vd.8H ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint32x4_t vmull_u16
(uint16x4_t a, a → Vn.4H UMULL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint64x2_t vmull_u32
(uint32x2_t a, a → Vn.2S UMULL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

poly16x8_t vmull_p8
(poly8x8_t a, a → Vn.8B PMULL Vd.8H,Vn.8B,Vm.8B Vd.8H ARMv7, ARMv8
poly8x8_t b) b → Vm.8B

int16x8_t vmull_high_s8
(int8x16_t a, a → Vn.16B SMULL2 Vd.8H,Vn.16B,Vm.16B Vd.8H ARMv8(AArch64)
int8x16_t b) b → Vm.16B

int32x4_t vmull_high_s16
(int16x8_t a, a → Vn.8H SMULL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int64x2_t vmull_high_s32
(int32x4_t a, a → Vn.4S SMULL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
int32x4_t b) b → Vm.4S

uint16x8_t vmull_high_u8
(uint8x16_t a, a → Vn.16B UMULL2 Vd.8H,Vn.16B,Vm.16B Vd.8H ARMv8(AArch64)
uint8x16_t b) b → Vm.16B

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uint32x4_t vmull_high_u16
(uint16x8_t a, a → Vn.8H UMULL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
uint16x8_t b) b → Vm.8H

uint64x2_t vmull_high_u32
(uint32x4_t a, a → Vn.4S UMULL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
uint32x4_t b) b → Vm.4S

poly16x8_t vmull_high_p8
(poly8x16_t a, a → Vn.16B PMULL2 Vd.8H,Vn.16B,Vm.16B Vd.8H ARMv8(AArch64)
poly8x16_t b) b → Vm.16B

int32x4_t vqdmull_s16
(int16x4_t a, a → Vn.4H SQDMULL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int64x2_t vqdmull_s32
(int32x2_t a, a → Vn.2S SQDMULL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
int32x2_t b) b → Vm.2S

int32_t vqdmullh_s16
(int16_t a, a → Hn SQDMULL Sd,Hn,Hm Sd ARMv8(AArch64)
int16_t b) b → Hm

int64_t vqdmulls_s32
(int32_t a, a → Sn SQDMULL Dd,Sn,Sm Dd ARMv8(AArch64)
int32_t b) b → Sm

int32x4_t vqdmull_high_s16
(int16x8_t a, a → Vn.8H SQDMULL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int64x2_t vqdmull_high_s32
(int32x4_t a, a → Vn.4S SQDMULL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
int32x4_t b) b → Vm.4S

int8x8_t vsub_s8
(int8x8_t a, a → Vn.8B SUB Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int8x16_t vsubq_s8
(int8x16_t a, a → Vn.16B SUB Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vsub_s16
(int16x4_t a, a → Vn.4H SUB Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

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int16x8_t vsubq_s16
(int16x8_t a, a → Vn.8H SUB Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vsub_s32
(int32x2_t a, a → Vn.2S SUB Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

int32x4_t vsubq_s32
(int32x4_t a, a → Vn.4S SUB Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

int64x1_t vsub_s64
(int64x1_t a, a → Dn SUB Dd,Dn,Dm Dd ARMv7, ARMv8
int64x1_t b) b → Dm

int64x2_t vsubq_s64
(int64x2_t a, a → Vn.2D SUB Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
int64x2_t b) b → Vm.2D

uint8x8_t vsub_u8
(uint8x8_t a, a → Vn.8B SUB Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vsubq_u8
(uint8x16_t a, a → Vn.16B SUB Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vsub_u16
(uint16x4_t a, a → Vn.4H SUB Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vsubq_u16
(uint16x8_t a, a → Vn.8H SUB Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vsub_u32
(uint32x2_t a, a → Vn.2S SUB Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

uint32x4_t vsubq_u32
(uint32x4_t a, a → Vn.4S SUB Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

uint64x1_t vsub_u64
(uint64x1_t a, a → Dn SUB Dd,Dn,Dm Dd ARMv7, ARMv8
uint64x1_t b) b → Dm

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uint64x2_t vsubq_u64
(uint64x2_t a, a → Vn.2D SUB Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
uint64x2_t b) b → Vm.2D

float32x2_t vsub_f32
(float32x2_t a, a → Vn.2S FSUB Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

float32x4_t vsubq_f32
(float32x4_t a, a → Vn.4S FSUB Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

float64x1_t vsub_f64
(float64x1_t a, a → Dn FSUB Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

float64x2_t vsubq_f64
(float64x2_t a, a → Vn.2D FSUB Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

int64_t vsubd_s64
(int64_t a, a → Dn SUB Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

uint64_t vsubd_u64
(uint64_t a, a → Dn SUB Dd,Dn,Dm Dd ARMv8(AArch64)
uint64_t b) b → Dm

int16x8_t vsubl_s8
(int8x8_t a, a → Vn.8B SSUBL Vd.8H,Vn.8B,Vm.8B Vd.8H ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int32x4_t vsubl_s16
(int16x4_t a, a → Vn.4H SSUBL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int64x2_t vsubl_s32
(int32x2_t a, a → Vn.2S SSUBL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint16x8_t vsubl_u8
(uint8x8_t a, a → Vn.8B USUBL Vd.8H,Vn.8B,Vm.8B Vd.8H ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint32x4_t vsubl_u16
(uint16x4_t a, a → Vn.4H USUBL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

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uint64x2_t vsubl_u32
(uint32x2_t a, a → Vn.2S USUBL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

int16x8_t vsubl_high_s8
(int8x16_t a, a → Vn.16B SSUBL2 Vd.8H,Vn.16B,Vm.16B Vd.8H ARMv8(AArch64)
int8x16_t b) b → Vm.16B

int32x4_t vsubl_high_s16
(int16x8_t a, a → Vn.8H SSUBL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int64x2_t vsubl_high_s32
(int32x4_t a, a → Vn.4S SSUBL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
int32x4_t b) b → Vm.4S

uint16x8_t vsubl_high_u8
(uint8x16_t a, a → Vn.16B USUBL2 Vd.8H,Vn.16B,Vm.16B Vd.8H ARMv8(AArch64)
uint8x16_t b) b → Vm.16B

uint32x4_t vsubl_high_u16
(uint16x8_t a, a → Vn.8H USUBL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
uint16x8_t b) b → Vm.8H

uint64x2_t vsubl_high_u32
(uint32x4_t a, a → Vn.4S USUBL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
uint32x4_t b) b → Vm.4S

int16x8_t vsubw_s8
(int16x8_t a, a → Vn.8H SSUBW Vd.8H,Vn.8H,Vm.8B Vd.8H ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int32x4_t vsubw_s16
(int32x4_t a, a → Vn.4S SSUBW Vd.4S,Vn.4S,Vm.4H Vd.4S ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int64x2_t vsubw_s32
(int64x2_t a, a → Vn.2D SSUBW Vd.2D,Vn.2D,Vm.2S Vd.2D ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint16x8_t vsubw_u8
(uint16x8_t a, a → Vn.8H USUBW Vd.8H,Vn.8H,Vm.8B Vd.8H ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint32x4_t vsubw_u16
(uint32x4_t a, a → Vn.4S USUBW Vd.4S,Vn.4S,Vm.4H Vd.4S ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 38 of 348
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uint64x2_t vsubw_u32
(uint64x2_t a, a → Vn.2D USUBW Vd.2D,Vn.2D,Vm.2S Vd.2D ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

int16x8_t vsubw_high_s8
(int16x8_t a, a → Vn.8H SSUBW2 Vd.8H,Vn.8H,Vm.16B Vd.8H ARMv8(AArch64)
int8x16_t b) b → Vm.16B

int32x4_t vsubw_high_s16
(int32x4_t a, a → Vn.4S SSUBW2 Vd.4S,Vn.4S,Vm.8H Vd.4S ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int64x2_t vsubw_high_s32
(int64x2_t a, a → Vn.2D SSUBW2 Vd.2D,Vn.2D,Vm.4S Vd.2D ARMv8(AArch64)
int32x4_t b) b → Vm.4S

uint16x8_t vsubw_high_u8
(uint16x8_t a, a → Vn.8H USUBW2 Vd.8H,Vn.8H,Vm.16B Vd.8H ARMv8(AArch64)
uint8x16_t b) b → Vm.16B

uint32x4_t vsubw_high_u16
(uint32x4_t a, a → Vn.4S USUBW2 Vd.4S,Vn.4S,Vm.8H Vd.4S ARMv8(AArch64)
uint16x8_t b) b → Vm.8H

uint64x2_t vsubw_high_u32
(uint64x2_t a, a → Vn.2D USUBW2 Vd.2D,Vn.2D,Vm.4S Vd.2D ARMv8(AArch64)
uint32x4_t b) b → Vm.4S

int8x8_t vhsub_s8
(int8x8_t a, a → Vn.8B SHSUB Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int8x16_t vhsubq_s8
(int8x16_t a, a → Vn.16B SHSUB Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vhsub_s16
(int16x4_t a, a → Vn.4H SHSUB Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int16x8_t vhsubq_s16
(int16x8_t a, a → Vn.8H SHSUB Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vhsub_s32
(int32x2_t a, a → Vn.2S SHSUB Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

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int32x4_t vhsubq_s32
(int32x4_t a, a → Vn.4S SHSUB Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint8x8_t vhsub_u8
(uint8x8_t a, a → Vn.8B UHSUB Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vhsubq_u8
(uint8x16_t a, a → Vn.16B UHSUB Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vhsub_u16
(uint16x4_t a, a → Vn.4H UHSUB Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vhsubq_u16
(uint16x8_t a, a → Vn.8H UHSUB Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vhsub_u32
(uint32x2_t a, a → Vn.2S UHSUB Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

uint32x4_t vhsubq_u32
(uint32x4_t a, a → Vn.4S UHSUB Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

int8x8_t vqsub_s8
(int8x8_t a, a → Vn.8B SQSUB Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int8x16_t vqsubq_s8
(int8x16_t a, a → Vn.16B SQSUB Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vqsub_s16
(int16x4_t a, a → Vn.4H SQSUB Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int16x8_t vqsubq_s16
(int16x8_t a, a → Vn.8H SQSUB Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vqsub_s32
(int32x2_t a, a → Vn.2S SQSUB Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 40 of 348
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int32x4_t vqsubq_s32
(int32x4_t a, a → Vn.4S SQSUB Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

int64x1_t vqsub_s64
(int64x1_t a, a → Dn SQSUB Dd,Dn,Dm Dd ARMv7, ARMv8
int64x1_t b) b → Dm

int64x2_t vqsubq_s64
(int64x2_t a, a → Vn.2D SQSUB Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
int64x2_t b) b → Vm.2D

uint8x8_t vqsub_u8
(uint8x8_t a, a → Vn.8B UQSUB Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vqsubq_u8
(uint8x16_t a, a → Vn.16B UQSUB Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vqsub_u16
(uint16x4_t a, a → Vn.4H UQSUB Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vqsubq_u16
(uint16x8_t a, a → Vn.8H UQSUB Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vqsub_u32
(uint32x2_t a, a → Vn.2S UQSUB Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

uint32x4_t vqsubq_u32
(uint32x4_t a, a → Vn.4S UQSUB Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

uint64x1_t vqsub_u64
(uint64x1_t a, a → Dn UQSUB Dd,Dn,Dm Dd ARMv7, ARMv8
uint64x1_t b) b → Dm

uint64x2_t vqsubq_u64
(uint64x2_t a, a → Vn.2D UQSUB Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
uint64x2_t b) b → Vm.2D

int8_t vqsubb_s8
(int8_t a, a → Bn SQSUB Bd,Bn,Bm Bd ARMv8(AArch64)
int8_t b) b → Bm

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 41 of 348
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int16_t vqsubh_s16
(int16_t a, a → Hn SQSUB Hd,Hn,Hm Hd ARMv8(AArch64)
int16_t b) b → Hm

int32_t vqsubs_s32
(int32_t a, a → Sn SQSUB Sd,Sn,Sm Sd ARMv8(AArch64)
int32_t b) b → Sm

int64_t vqsubd_s64
(int64_t a, a → Dn SQSUB Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

uint8_t vqsubb_u8
(uint8_t a, a → Bn UQSUB Bd,Bn,Bm Bd ARMv8(AArch64)
uint8_t b) b → Bm

uint16_t vqsubh_u16
(uint16_t a, a → Hn UQSUB Hd,Hn,Hm Hd ARMv8(AArch64)
uint16_t b) b → Hm

uint32_t vqsubs_u32
(uint32_t a, a → Sn UQSUB Sd,Sn,Sm Sd ARMv8(AArch64)
uint32_t b) b → Sm

uint64_t vqsubd_u64
(uint64_t a, a → Dn UQSUB Dd,Dn,Dm Dd ARMv8(AArch64)
uint64_t b) b → Dm

int8x8_t vsubhn_s16
(int16x8_t a, a → Vn.8H SUBHN Vd.8B,Vn.8H,Vm.8H Vd.8B ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int16x4_t vsubhn_s32
(int32x4_t a, a → Vn.4S SUBHN Vd.4H,Vn.4S,Vm.4S Vd.4H ARMv7, ARMv8
int32x4_t b) b → Vm.4S

int32x2_t vsubhn_s64
(int64x2_t a, a → Vn.2D SUBHN Vd.2S,Vn.2D,Vm.2D Vd.2S ARMv7, ARMv8
int64x2_t b) b → Vm.2D

uint8x8_t vsubhn_u16
(uint16x8_t a, a → Vn.8H SUBHN Vd.8B,Vn.8H,Vm.8H Vd.8B ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint16x4_t vsubhn_u32
(uint32x4_t a, a → Vn.4S SUBHN Vd.4H,Vn.4S,Vm.4S Vd.4H ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 42 of 348
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uint32x2_t vsubhn_u64
(uint64x2_t a, a → Vn.2D SUBHN Vd.2S,Vn.2D,Vm.2D Vd.2S ARMv7, ARMv8
uint64x2_t b) b → Vm.2D

int8x16_t vsubhn_high_s16
(int8x8_t r, r → Vd.8B
SUBHN2 Vd.16B,Vn.8H,Vm.8H Vd.16B ARMv8(AArch64)
int16x8_t a, a → Vn.8H
int16x8_t b) b → Vm.8H

int16x8_t vsubhn_high_s32
(int16x4_t r, r → Vd.4H
SUBHN2 Vd.8H,Vn.4S,Vm.4S Vd.8H ARMv8(AArch64)
int32x4_t a, a → Vn.4S
int32x4_t b) b → Vm.4S

int32x4_t vsubhn_high_s64
(int32x2_t r, r → Vd.2S
SUBHN2 Vd.4S,Vn.2D,Vm.2D Vd.4S ARMv8(AArch64)
int64x2_t a, a → Vn.2D
int64x2_t b) b → Vm.2D

uint8x16_t vsubhn_high_u16
(uint8x8_t r, r → Vd.8B
SUBHN2 Vd.16B,Vn.8H,Vm.8H Vd.16B ARMv8(AArch64)
uint16x8_t a, a → Vn.8H
uint16x8_t b) b → Vm.8H

uint16x8_t vsubhn_high_u32
(uint16x4_t r, r → Vd.4H
SUBHN2 Vd.8H,Vn.4S,Vm.4S Vd.8H ARMv8(AArch64)
uint32x4_t a, a → Vn.4S
uint32x4_t b) b → Vm.4S

uint32x4_t vsubhn_high_u64
(uint32x2_t r, r → Vd.2S
SUBHN2 Vd.4S,Vn.2D,Vm.2D Vd.4S ARMv8(AArch64)
uint64x2_t a, a → Vn.2D
uint64x2_t b) b → Vm.2D

int8x8_t vrsubhn_s16
(int16x8_t a, a → Vn.8H RSUBHN Vd.8B,Vn.8H,Vm.8H Vd.8B ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int16x4_t vrsubhn_s32
(int32x4_t a, a → Vn.4S RSUBHN Vd.4H,Vn.4S,Vm.4S Vd.4H ARMv7, ARMv8
int32x4_t b) b → Vm.4S

int32x2_t vrsubhn_s64
(int64x2_t a, a → Vn.2D RSUBHN Vd.2S,Vn.2D,Vm.2D Vd.2S ARMv7, ARMv8
int64x2_t b) b → Vm.2D

uint8x8_t vrsubhn_u16
(uint16x8_t a, a → Vn.8H RSUBHN Vd.8B,Vn.8H,Vm.8H Vd.8B ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 43 of 348
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uint16x4_t vrsubhn_u32
(uint32x4_t a, a → Vn.4S RSUBHN Vd.4H,Vn.4S,Vm.4S Vd.4H ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

uint32x2_t vrsubhn_u64
(uint64x2_t a, a → Vn.2D RSUBHN Vd.2S,Vn.2D,Vm.2D Vd.2S ARMv7, ARMv8
uint64x2_t b) b → Vm.2D

int8x16_t vrsubhn_high_s16
(int8x8_t r, r → Vd.8B
RSUBHN2 Vd.16B,Vn.8H,Vm.8H Vd.16B ARMv8(AArch64)
int16x8_t a, a → Vn.8H
int16x8_t b) b → Vm.8H

int16x8_t vrsubhn_high_s32
(int16x4_t r, r → Vd.4H
RSUBHN2 Vd.8H,Vn.4S,Vm.4S Vd.8H ARMv8(AArch64)
int32x4_t a, a → Vn.4S
int32x4_t b) b → Vm.4S

int32x4_t vrsubhn_high_s64
(int32x2_t r, r → Vd.2S
RSUBHN2 Vd.4S,Vn.2D,Vm.2D Vd.4S ARMv8(AArch64)
int64x2_t a, a → Vn.2D
int64x2_t b) b → Vm.2D

uint8x16_t vrsubhn_high_u16
(uint8x8_t r, r → Vd.8B
RSUBHN2 Vd.16B,Vn.8H,Vm.8H Vd.16B ARMv8(AArch64)
uint16x8_t a, a → Vn.8H
uint16x8_t b) b → Vm.8H

uint16x8_t vrsubhn_high_u32
(uint16x4_t r, r → Vd.4H
RSUBHN2 Vd.8H,Vn.4S,Vm.4S Vd.8H ARMv8(AArch64)
uint32x4_t a, a → Vn.4S
uint32x4_t b) b → Vm.4S

uint32x4_t vrsubhn_high_u64
(uint32x2_t r, r → Vd.2S
RSUBHN2 Vd.4S,Vn.2D,Vm.2D Vd.4S ARMv8(AArch64)
uint64x2_t a, a → Vn.2D
uint64x2_t b) b → Vm.2D

uint8x8_t vceq_s8
(int8x8_t a, a → Vn.8B CMEQ Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

uint8x16_t vceqq_s8
(int8x16_t a, a → Vn.16B CMEQ Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

uint16x4_t vceq_s16
(int16x4_t a, a → Vn.4H CMEQ Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

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uint16x8_t vceqq_s16
(int16x8_t a, a → Vn.8H CMEQ Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

uint32x2_t vceq_s32
(int32x2_t a, a → Vn.2S CMEQ Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint32x4_t vceqq_s32
(int32x4_t a, a → Vn.4S CMEQ Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint8x8_t vceq_u8
(uint8x8_t a, a → Vn.8B CMEQ Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vceqq_u8
(uint8x16_t a, a → Vn.16B CMEQ Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vceq_u16
(uint16x4_t a, a → Vn.4H CMEQ Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vceqq_u16
(uint16x8_t a, a → Vn.8H CMEQ Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vceq_u32
(uint32x2_t a, a → Vn.2S CMEQ Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

uint32x4_t vceqq_u32
(uint32x4_t a, a → Vn.4S CMEQ Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

uint32x2_t vceq_f32
(float32x2_t a, a → Vn.2S FCMEQ Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

uint32x4_t vceqq_f32
(float32x4_t a, a → Vn.4S FCMEQ Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

uint8x8_t vceq_p8
(poly8x8_t a, a → Vn.8B CMEQ Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
poly8x8_t b) b → Vm.8B

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uint8x16_t vceqq_p8
(poly8x16_t a, a → Vn.16B CMEQ Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
poly8x16_t b) b → Vm.16B

uint64x1_t vceq_s64
(int64x1_t a, a → Dn CMEQ Dd,Dn,Dm Dd ARMv8(AArch64)
int64x1_t b) b → Dm

uint64x2_t vceqq_s64
(int64x2_t a, a → Vn.2D CMEQ Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
int64x2_t b) b → Vm.2D

uint64x1_t vceq_u64
(uint64x1_t a, a → Dn CMEQ Dd,Dn,Dm Dd ARMv8(AArch64)
uint64x1_t b) b → Dm

uint64x2_t vceqq_u64
(uint64x2_t a, a → Vn.2D CMEQ Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
uint64x2_t b) b → Vm.2D

uint64x1_t vceq_p64
(poly64x1_t a, a → Dn CMEQ Dd,Dn,Dm Dd ARMv8
poly64x1_t b) b → Dm

uint64x2_t vceqq_p64
(poly64x2_t a, a → Vn.2D CMEQ Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8
poly64x2_t b) b → Vm.2D

uint64x1_t vceq_f64
(float64x1_t a, a → Dn FCMEQ Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

uint64x2_t vceqq_f64
(float64x2_t a, a → Vn.2D FCMEQ Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

uint64_t vceqd_s64
(int64_t a, a → Dn CMEQ Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

uint64_t vceqd_u64
(uint64_t a, a → Dn CMEQ Dd,Dn,Dm Dd ARMv8(AArch64)
uint64_t b) b → Dm

uint32_t vceqs_f32
(float32_t a, a → Sn FCMEQ Sd,Sn,Sm Sd ARMv8(AArch64)
float32_t b) b → Sm

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uint64_t vceqd_f64
(float64_t a, a → Dn FCMEQ Dd,Dn,Dm Dd ARMv8(AArch64)
float64_t b) b → Dm

uint8x8_t vceqz_s8
CMEQ Vd.8B,Vn.8B,#0 Vd.8B ARMv8(AArch64)
(int8x8_t a) a → Vn.8B

uint8x16_t vceqzq_s8
CMEQ Vd.16B,Vn.16B,#0 Vd.16B ARMv8(AArch64)
(int8x16_t a) a → Vn.16B

uint16x4_t vceqz_s16
CMEQ Vd.4H,Vn.4H,#0 Vd.4H ARMv8(AArch64)
(int16x4_t a) a → Vn.4H

uint16x8_t vceqzq_s16
CMEQ Vd.8H,Vn.8H,#0 Vd.8H ARMv8(AArch64)
(int16x8_t a) a → Vn.8H

uint32x2_t vceqz_s32
CMEQ Vd.2S,Vn.2S,#0 Vd.2S ARMv8(AArch64)
(int32x2_t a) a → Vn.2S

uint32x4_t vceqzq_s32
CMEQ Vd.4S,Vn.4S,#0 Vd.4S ARMv8(AArch64)
(int32x4_t a) a → Vn.4S

uint8x8_t vceqz_u8
CMEQ Vd.8B,Vn.8B,#0 Vd.8B ARMv8(AArch64)
(uint8x8_t a) a → Vn.8B

uint8x16_t vceqzq_u8
CMEQ Vd.16B,Vn.16B,#0 Vd.16B ARMv8(AArch64)
(uint8x16_t a) a → Vn.16B

uint16x4_t vceqz_u16
CMEQ Vd.4H,Vn.4H,#0 Vd.4H ARMv8(AArch64)
(uint16x4_t a) a → Vn.4H

uint16x8_t vceqzq_u16
CMEQ Vd.8H,Vn.8H,#0 Vd.8H ARMv8(AArch64)
(uint16x8_t a) a → Vn.8H

uint32x2_t vceqz_u32
CMEQ Vd.2S,Vn.2S,#0 Vd.2S ARMv8(AArch64)
(uint32x2_t a) a → Vn.2S

uint32x4_t vceqzq_u32
CMEQ Vd.4S,Vn.4S,#0 Vd.4S ARMv8(AArch64)
(uint32x4_t a) a → Vn.4S

uint32x2_t vceqz_f32
FCMEQ Vd.2S,Vn.2S,#0 Vd.2S ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

uint32x4_t vceqzq_f32
FCMEQ Vd.4S,Vn.4S,#0 Vd.4S ARMv8(AArch64)
(float32x4_t a) a → Vn.4S

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uint8x8_t vceqz_p8
CMEQ Vd.8B,Vn.8B,#0 Vd.8B ARMv8(AArch64)
(poly8x8_t a) a → Vn.8B

uint8x16_t vceqzq_p8
CMEQ Vd.16B,Vn.16B,#0 Vd.16B ARMv8(AArch64)
(poly8x16_t a) a → Vn.16B

uint64x1_t vceqz_s64
CMEQ Dd,Dn,#0 Dd ARMv8(AArch64)
(int64x1_t a) a → Dn

uint64x2_t vceqzq_s64
CMEQ Vd.2D,Vn.2D,#0 Vd.2D ARMv8(AArch64)
(int64x2_t a) a → Vn.2D

uint64x1_t vceqz_u64
CMEQ Dd,Dn,#0 Dd ARMv8(AArch64)
(uint64x1_t a) a → Dn

uint64x2_t vceqzq_u64
CMEQ Vd.2D,Vn.2D,#0 Vd.2D ARMv8(AArch64)
(uint64x2_t a) a → Vn.2D

uint64x1_t vceqz_p64
CMEQ Dd,Dn,#0 Dd ARMv8
(poly64x1_t a) a → Dn

uint64x2_t vceqzq_p64
CMEQ Vd.2D,Vn.2D,#0 Vd.2D ARMv8
(poly64x2_t a) a → Vn.2D

uint64x1_t vceqz_f64
FCMEQ Dd,Dn,#0 Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

uint64x2_t vceqzq_f64
FCMEQ Vd.2D,Vn.2D,#0 Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

uint64_t vceqzd_s64
CMEQ Dd,Dn,#0 Dd ARMv8(AArch64)
(int64_t a) a → Dn

uint64_t vceqzd_u64
CMEQ Dd,Dn,#0 Dd ARMv8(AArch64)
(uint64_t a) a → Dn

uint32_t vceqzs_f32
FCMEQ Sd,Sn,#0 Sd ARMv8(AArch64)
(float32_t a) a → Sn

uint64_t vceqzd_f64
FCMEQ Dd,Dn,#0 Dd ARMv8(AArch64)
(float64_t a) a → Dn

uint8x8_t vcge_s8
(int8x8_t a, a → Vn.8B CMGE Vd.8B,Vm.8B,Vn.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

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uint8x16_t vcgeq_s8
(int8x16_t a, a → Vn.16B CMGE Vd.16B,Vm.16B,Vn.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

uint16x4_t vcge_s16
(int16x4_t a, a → Vn.4H CMGE Vd.4H,Vm.4H,Vn.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

uint16x8_t vcgeq_s16
(int16x8_t a, a → Vn.8H CMGE Vd.8H,Vm.8H,Vn.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

uint32x2_t vcge_s32
(int32x2_t a, a → Vn.2S CMGE Vd.2S,Vm.2S,Vn.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint32x4_t vcgeq_s32
(int32x4_t a, a → Vn.4S CMGE Vd.4S,Vm.4S,Vn.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint8x8_t vcge_u8
(uint8x8_t a, a → Vn.8B CMHS Vd.8B,Vm.8B,Vn.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vcgeq_u8
(uint8x16_t a, a → Vn.16B CMHS Vd.16B,Vm.16B,Vn.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vcge_u16
(uint16x4_t a, a → Vn.4H CMHS Vd.4H,Vm.4H,Vn.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vcgeq_u16
(uint16x8_t a, a → Vn.8H CMHS Vd.8H,Vm.8H,Vn.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vcge_u32
(uint32x2_t a, a → Vn.2S CMHS Vd.2S,Vm.2S,Vn.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

uint32x4_t vcgeq_u32
(uint32x4_t a, a → Vn.4S CMHS Vd.4S,Vm.4S,Vn.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

uint32x2_t vcge_f32
(float32x2_t a, a → Vn.2S FCMGE Vd.2S,Vm.2S,Vn.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

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uint32x4_t vcgeq_f32
(float32x4_t a, a → Vn.4S FCMGE Vd.4S,Vm.4S,Vn.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

uint64x1_t vcge_s64
(int64x1_t a, a → Dn CMGE Dd,Dn,Dm Dd ARMv8(AArch64)
int64x1_t b) b → Dm

uint64x2_t vcgeq_s64
(int64x2_t a, a → Vn.2D CMGE Vd.2D,Vm.2D,Vn.2D Vd.2D ARMv8(AArch64)
int64x2_t b) b → Vm.2D

uint64x1_t vcge_u64
(uint64x1_t a, a → Dn CMHS Dd,Dn,Dm Dd ARMv8(AArch64)
uint64x1_t b) b → Dm

uint64x2_t vcgeq_u64
(uint64x2_t a, a → Vn.2D CMHS Vd.2D,Vm.2D,Vn.2D Vd.2D ARMv8(AArch64)
uint64x2_t b) b → Vm.2D

uint64x1_t vcge_f64
(float64x1_t a, a → Dn FCMGE Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

uint64x2_t vcgeq_f64
(float64x2_t a, a → Vn.2D FCMGE Vd.2D,Vm.2D,Vn.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

uint64_t vcged_s64
(int64_t a, a → Dn CMGE Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

uint64_t vcged_u64
(uint64_t a, a → Dn CMHS Dd,Dn,Dm Dd ARMv8(AArch64)
uint64_t b) b → Dm

uint32_t vcges_f32
(float32_t a, a → Sn FCMGE Sd,Sn,Sm Sd ARMv8(AArch64)
float32_t b) b → Sm

uint64_t vcged_f64
(float64_t a, a → Dn FCMGE Dd,Dn,Dm Dd ARMv8(AArch64)
float64_t b) b → Dm

uint8x8_t vcgez_s8
CMGE Vd.8B,Vn.8B,#0 Vd.8B ARMv8(AArch64)
(int8x8_t a) a → Vn.8B

uint8x16_t vcgezq_s8
CMGE Vd.16B,Vn.16B,#0 Vd.16B ARMv8(AArch64)
(int8x16_t a) a → Vn.16B

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uint16x4_t vcgez_s16
CMGE Vd.4H,Vn.4H,#0 Vd.4H ARMv8(AArch64)
(int16x4_t a) a → Vn.4H

uint16x8_t vcgezq_s16
CMGE Vd.8H,Vn.8H,#0 Vd.8H ARMv8(AArch64)
(int16x8_t a) a → Vn.8H

uint32x2_t vcgez_s32
CMGE Vd.2S,Vn.2S,#0 Vd.2S ARMv8(AArch64)
(int32x2_t a) a → Vn.2S

uint32x4_t vcgezq_s32
CMGE Vd.4S,Vn.4S,#0 Vd.4S ARMv8(AArch64)
(int32x4_t a) a → Vn.4S

uint64x1_t vcgez_s64
CMGE Dd,Dn,#0 Dd ARMv8(AArch64)
(int64x1_t a) a → Dn

uint64x2_t vcgezq_s64
CMGE Vd.2D,Vn.2D,#0 Vd.2D ARMv8(AArch64)
(int64x2_t a) a → Vn.2D

uint32x2_t vcgez_f32
FCMGE Vd.2S,Vn.2S,#0 Vd.2S ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

uint32x4_t vcgezq_f32
FCMGE Vd.4S,Vn.4S,#0 Vd.4S ARMv8(AArch64)
(float32x4_t a) a → Vn.4S

uint64x1_t vcgez_f64
FCMGE Dd,Dn,#0 Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

uint64x2_t vcgezq_f64
FCMGE Vd.2D,Vn.2D,#0 Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

uint64_t vcgezd_s64
CMGE Dd,Dn,#0 Dd ARMv8(AArch64)
(int64_t a) a → Dn

uint32_t vcgezs_f32
FCMGE Sd,Sn,#0 Sd ARMv8(AArch64)
(float32_t a) a → Sn

uint64_t vcgezd_f64
FCMGE Dd,Dn,#0 Dd ARMv8(AArch64)
(float64_t a) a → Dn

uint8x8_t vcle_s8
(int8x8_t a, a → Vn.8B CMGE Vd.8B,Vm.8B,Vn.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

uint8x16_t vcleq_s8
(int8x16_t a, a → Vn.16B CMGE Vd.16B,Vm.16B,Vn.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

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uint16x4_t vcle_s16
(int16x4_t a, a → Vn.4H CMGE Vd.4H,Vm.4H,Vn.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

uint16x8_t vcleq_s16
(int16x8_t a, a → Vn.8H CMGE Vd.8H,Vm.8H,Vn.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

uint32x2_t vcle_s32
(int32x2_t a, a → Vn.2S CMGE Vd.2S,Vm.2S,Vn.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint32x4_t vcleq_s32
(int32x4_t a, a → Vn.4S CMGE Vd.4S,Vm.4S,Vn.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint8x8_t vcle_u8
(uint8x8_t a, a → Vn.8B CMHS Vd.8B,Vm.8B,Vn.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vcleq_u8
(uint8x16_t a, a → Vn.16B CMHS Vd.16B,Vm.16B,Vn.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vcle_u16
(uint16x4_t a, a → Vn.4H CMHS Vd.4H,Vm.4H,Vn.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vcleq_u16
(uint16x8_t a, a → Vn.8H CMHS Vd.8H,Vm.8H,Vn.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vcle_u32
(uint32x2_t a, a → Vn.2S CMHS Vd.2S,Vm.2S,Vn.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

uint32x4_t vcleq_u32
(uint32x4_t a, a → Vn.4S CMHS Vd.4S,Vm.4S,Vn.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

uint32x2_t vcle_f32
(float32x2_t a, a → Vn.2S FCMGE Vd.2S,Vm.2S,Vn.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

uint32x4_t vcleq_f32
(float32x4_t a, a → Vn.4S FCMGE Vd.4S,Vm.4S,Vn.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

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uint64x1_t vcle_s64
(int64x1_t a, a → Dn CMGE Dd,Dm,Dn Dd ARMv8(AArch64)
int64x1_t b) b → Dm

uint64x2_t vcleq_s64
(int64x2_t a, a → Vn.2D CMGE Vd.2D,Vm.2D,Vn.2D Vd.2D ARMv8(AArch64)
int64x2_t b) b → Vm.2D

uint64x1_t vcle_u64
(uint64x1_t a, a → Dn CMHS Dd,Dm,Dn Dd ARMv8(AArch64)
uint64x1_t b) b → Dm

uint64x2_t vcleq_u64
(uint64x2_t a, a → Vn.2D CMHS Vd.2D,Vm.2D,Vn.2D Vd.2D ARMv8(AArch64)
uint64x2_t b) b → Vm.2D

uint64x1_t vcle_f64
(float64x1_t a, a → Dn FCMGE Dd,Dm,Dn Dd ARMv8(AArch64)
float64x1_t b) b → Dm

uint64x2_t vcleq_f64
(float64x2_t a, a → Vn.2D FCMGE Vd.2D,Vm.2D,Vn.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

uint64_t vcled_s64
(int64_t a, a → Dn CMGE Dd,Dm,Dn Dd ARMv8(AArch64)
int64_t b) b → Dm

uint64_t vcled_u64
(uint64_t a, a → Dn CMHS Dd,Dm,Dn Dd ARMv8(AArch64)
uint64_t b) b → Dm

uint32_t vcles_f32
(float32_t a, a → Sn FCMGE Sd,Sm,Sn Sd ARMv8(AArch64)
float32_t b) b → Sm

uint64_t vcled_f64
(float64_t a, a → Dn FCMGE Dd,Dm,Dn Dd ARMv8(AArch64)
float64_t b) b → Dm

uint8x8_t vclez_s8
CMLE Vd.8B,Vn.8B,#0 Vd.8B ARMv8(AArch64)
(int8x8_t a) a → Vn.8B

uint8x16_t vclezq_s8
CMLE Vd.16B,Vn.16B,#0 Vd.16B ARMv8(AArch64)
(int8x16_t a) a → Vn.16B

uint16x4_t vclez_s16
CMLE Vd.4H,Vn.4H,#0 Vd.4H ARMv8(AArch64)
(int16x4_t a) a → Vn.4H

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uint16x8_t vclezq_s16
CMLE Vd.8H,Vn.8H,#0 Vd.8H ARMv8(AArch64)
(int16x8_t a) a → Vn.8H

uint32x2_t vclez_s32
CMLE Vd.2S,Vn.2S,#0 Vd.2S ARMv8(AArch64)
(int32x2_t a) a → Vn.2S

uint32x4_t vclezq_s32
CMLE Vd.4S,Vn.4S,#0 Vd.4S ARMv8(AArch64)
(int32x4_t a) a → Vn.4S

uint64x1_t vclez_s64
CMLE Dd,Dn,#0 Dd ARMv8(AArch64)
(int64x1_t a) a → Dn

uint64x2_t vclezq_s64
CMLE Vd.2D,Vn.2D,#0 Vd.2D ARMv8(AArch64)
(int64x2_t a) a → Vn.2D

uint32x2_t vclez_f32
CMLE Vd.2S,Vn.2S,#0 Vd.2S ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

uint32x4_t vclezq_f32
FCMLE Vd.4S,Vn.4S,#0 Vd.4S ARMv8(AArch64)
(float32x4_t a) a → Vn.4S

uint64x1_t vclez_f64
FCMLE Dd,Dn,#0 Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

uint64x2_t vclezq_f64
FCMLE Vd.2D,Vn.2D,#0 Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

uint64_t vclezd_s64
CMLE Dd,Dn,#0 Dd ARMv8(AArch64)
(int64_t a) a → Dn

uint32_t vclezs_f32
FCMLE Sd,Sn,#0 Sd ARMv8(AArch64)
(float32_t a) a → Sn

uint64_t vclezd_f64
FCMLE Dd,Dn,#0 Dd ARMv8(AArch64)
(float64_t a) a → Dn

uint8x8_t vcgt_s8
(int8x8_t a, a → Vn.8B CMGT Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

uint8x16_t vcgtq_s8
(int8x16_t a, a → Vn.16B CMGT Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

uint16x4_t vcgt_s16
(int16x4_t a, a → Vn.4H CMGT Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

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uint16x8_t vcgtq_s16
(int16x8_t a, a → Vn.8H CMGT Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

uint32x2_t vcgt_s32
(int32x2_t a, a → Vn.2S CMGT Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint32x4_t vcgtq_s32
(int32x4_t a, a → Vn.4S CMGT Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint8x8_t vcgt_u8
(uint8x8_t a, a → Vn.8B CMHI Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vcgtq_u8
(uint8x16_t a, a → Vn.16B CMHI Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vcgt_u16
(uint16x4_t a, a → Vn.4H CMHI Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vcgtq_u16
(uint16x8_t a, a → Vn.8H CMHI Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vcgt_u32
(uint32x2_t a, a → Vn.2S CMHI Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

uint32x4_t vcgtq_u32
(uint32x4_t a, a → Vn.4S CMHI Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

uint32x2_t vcgt_f32
(float32x2_t a, a → Vn.2S FCMGT Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

uint32x4_t vcgtq_f32
(float32x4_t a, a → Vn.4S FCMGT Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

uint64x1_t vcgt_s64
(int64x1_t a, a → Dn CMGT Dd,Dn,Dm Dd ARMv8(AArch64)
int64x1_t b) b → Dm

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uint64x2_t vcgtq_s64
(int64x2_t a, a → Vn.2D CMGT Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
int64x2_t b) b → Vm.2D

uint64x1_t vcgt_u64
(uint64x1_t a, a → Dn CMHI Dd,Dn,Dm Dd ARMv8(AArch64)
uint64x1_t b) b → Dm

uint64x2_t vcgtq_u64
(uint64x2_t a, a → Vn.2D CMHI Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
uint64x2_t b) b → Vm.2D

uint64x1_t vcgt_f64
(float64x1_t a, a → Dn FCMGT Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

uint64x2_t vcgtq_f64
(float64x2_t a, a → Vn.2D FCMGT Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

uint64_t vcgtd_s64
(int64_t a, a → Dn CMGT Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

uint64_t vcgtd_u64
(uint64_t a, a → Dn CMHI Dd,Dn,Dm Dd ARMv8(AArch64)
uint64_t b) b → Dm

uint32_t vcgts_f32
(float32_t a, a → Sn FCMGT Sd,Sn,Sm Sd ARMv8(AArch64)
float32_t b) b → Sm

uint64_t vcgtd_f64
(float64_t a, a → Dn FCMGT Dd,Dn,Dm Dd ARMv8(AArch64)
float64_t b) b → Dm

uint8x8_t vcgtz_s8
CMGT Vd.8B,Vn.8B,#0 Vd.8B ARMv8(AArch64)
(int8x8_t a) a → Vn.8B

uint8x16_t vcgtzq_s8
CMGT Vd.16B,Vn.16B,#0 Vd.16B ARMv8(AArch64)
(int8x16_t a) a → Vn.16B

uint16x4_t vcgtz_s16
CMGT Vd.4H,Vn.4H,#0 Vd.4H ARMv8(AArch64)
(int16x4_t a) a → Vn.4H

uint16x8_t vcgtzq_s16
CMGT Vd.8H,Vn.8H,#0 Vd.8H ARMv8(AArch64)
(int16x8_t a) a → Vn.8H

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uint32x2_t vcgtz_s32
CMGT Vd.2S,Vn.2S,#0 Vd.2S ARMv8(AArch64)
(int32x2_t a) a → Vn.2S

uint32x4_t vcgtzq_s32
CMGT Vd.4S,Vn.4S,#0 Vd.4S ARMv8(AArch64)
(int32x4_t a) a → Vn.4S

uint64x1_t vcgtz_s64
CMGT Dd,Dn,#0 Dd ARMv8(AArch64)
(int64x1_t a) a → Dn

uint64x2_t vcgtzq_s64
CMGT Vd.2D,Vn.2D,#0 Vd.2D ARMv8(AArch64)
(int64x2_t a) a → Vn.2D

uint32x2_t vcgtz_f32
FCMGT Vd.2S,Vn.2S,#0 Vd.2S ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

uint32x4_t vcgtzq_f32
FCMGT Vd.4S,Vn.4S,#0 Vd.4S ARMv8(AArch64)
(float32x4_t a) a → Vn.4S

uint64x1_t vcgtz_f64
FCMGT Dd,Dn,#0 Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

uint64x2_t vcgtzq_f64
FCMGT Vd.2D,Vn.2D,#0 Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

uint64_t vcgtzd_s64
CMGT Dd,Dn,#0 Dd ARMv8(AArch64)
(int64_t a) a → Dn

uint32_t vcgtzs_f32
FCMGT Sd,Sn,#0 Sd ARMv8(AArch64)
(float32_t a) a → Sn

uint64_t vcgtzd_f64
FCMGT Dd,Dn,#0 Dd ARMv8(AArch64)
(float64_t a) a → Dn

uint8x8_t vclt_s8
(int8x8_t a, a → Vn.8B CMGT Vd.8B,Vm.8B,Vn.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

uint8x16_t vcltq_s8
(int8x16_t a, a → Vn.16B CMGT Vd.16B,Vm.16B,Vn.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

uint16x4_t vclt_s16
(int16x4_t a, a → Vn.4H CMGT Vd.4H,Vm.4H,Vn.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

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uint16x8_t vcltq_s16
(int16x8_t a, a → Vn.8H CMGT Vd.8H,Vm.8H,Vn.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

uint32x2_t vclt_s32
(int32x2_t a, a → Vn.2S CMGT Vd.2S,Vm.2S,Vn.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint32x4_t vcltq_s32
(int32x4_t a, a → Vn.4S CMGT Vd.4S,Vm.4S,Vn.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint8x8_t vclt_u8
(uint8x8_t a, a → Vn.8B CMHI Vd.8B,Vm.8B,Vn.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vcltq_u8
(uint8x16_t a, a → Vn.16B CMHI Vd.16B,Vm.16B,Vn.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vclt_u16
(uint16x4_t a, a → Vn.4H CMHI Vd.4H,Vm.4H,Vn.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vcltq_u16
(uint16x8_t a, a → Vn.8H CMHI Vd.8H,Vm.8H,Vn.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vclt_u32
(uint32x2_t a, a → Vn.2S CMHI Vd.2S,Vm.2S,Vn.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

uint32x4_t vcltq_u32
(uint32x4_t a, a → Vn.4S CMHI Vd.4S,Vm.4S,Vn.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

uint32x2_t vclt_f32
(float32x2_t a, a → Vn.2S FCMGT Vd.2S,Vm.2S,Vn.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

uint32x4_t vcltq_f32
(float32x4_t a, a → Vn.4S FCMGT Vd.4S,Vm.4S,Vn.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

uint64x1_t vclt_s64
(int64x1_t a, a → Dn CMGT Dd,Dm,Dn Dd ARMv8(AArch64)
int64x1_t b) b → Dm

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uint64x2_t vcltq_s64
(int64x2_t a, a → Vn.2D CMGT Vd.2D,Vm.2D,Vn.2D Vd.2D ARMv8(AArch64)
int64x2_t b) b → Vm.2D

uint64x1_t vclt_u64
(uint64x1_t a, a → Dn CMHI Dd,Dm,Dn Dd ARMv8(AArch64)
uint64x1_t b) b → Dm

uint64x2_t vcltq_u64
(uint64x2_t a, a → Vn.2D CMHI Vd.2D,Vm.2D,Vn.2D Vd.2D ARMv8(AArch64)
uint64x2_t b) b → Vm.2D

uint64x1_t vclt_f64
(float64x1_t a, a → Dn FCMGT Dd,Dm,Dn Dd ARMv8(AArch64)
float64x1_t b) b → Dm

uint64x2_t vcltq_f64
(float64x2_t a, a → Vn.2D FCMGT Vd.2D,Vm.2D,Vn.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

uint64_t vcltd_s64
(int64_t a, a → Dn CMGT Dd,Dm,Dn Dd ARMv8(AArch64)
int64_t b) b → Dm

uint64_t vcltd_u64
(uint64_t a, a → Dn CMHI Dd,Dm,Dn Dd ARMv8(AArch64)
uint64_t b) b → Dm

uint32_t vclts_f32
(float32_t a, a → Sn FCMGT Sd,Sm,Sn Sd ARMv8(AArch64)
float32_t b) b → Sm

uint64_t vcltd_f64
(float64_t a, a → Dn FCMGT Dd,Dm,Dn Dd ARMv8(AArch64)
float64_t b) b → Dm

uint8x8_t vcltz_s8
CMLT Vd.8B,Vn.8B,#0 Vd.8B ARMv8(AArch64)
(int8x8_t a) a → Vn.8B

uint8x16_t vcltzq_s8
CMLT Vd.16B,Vn.16B,#0 Vd.16B ARMv8(AArch64)
(int8x16_t a) a → Vn.16B

uint16x4_t vcltz_s16
CMLT Vd.4H,Vn.4H,#0 Vd.4H ARMv8(AArch64)
(int16x4_t a) a → Vn.4H

uint16x8_t vcltzq_s16
CMLT Vd.8H,Vn.8H,#0 Vd.8H ARMv8(AArch64)
(int16x8_t a) a → Vn.8H

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uint32x2_t vcltz_s32
CMLT Vd.2S,Vn.2S,#0 Vd.2S ARMv8(AArch64)
(int32x2_t a) a → Vn.2S

uint32x4_t vcltzq_s32
CMLT Vd.4S,Vn.4S,#0 Vd.4S ARMv8(AArch64)
(int32x4_t a) a → Vn.4S

uint64x1_t vcltz_s64
CMLT Dd,Dn,#0 Dd ARMv8(AArch64)
(int64x1_t a) a → Dn

uint64x2_t vcltzq_s64
CMLT Vd.2D,Vn.2D,#0 Vd.2D ARMv8(AArch64)
(int64x2_t a) a → Vn.2D

uint32x2_t vcltz_f32
FCMLT Vd.2S,Vn.2S,#0 Vd.2S ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

uint32x4_t vcltzq_f32
FCMLT Vd.4S,Vn.4S,#0 Vd.4S ARMv8(AArch64)
(float32x4_t a) a → Vn.4S

uint64x1_t vcltz_f64
FCMLT Dd,Dn,#0 Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

uint64x2_t vcltzq_f64
FCMLT Vd.2D,Vn.2D,#0 Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

uint64_t vcltzd_s64
CMLT Dd,Dn,#0 Dd ARMv8(AArch64)
(int64_t a) a → Dn

uint32_t vcltzs_f32
FCMLT Sd,Sn,#0 Sd ARMv8(AArch64)
(float32_t a) a → Sn

uint64_t vcltzd_f64
FCMLT Dd,Dn,#0 Dd ARMv8(AArch64)
(float64_t a) a → Dn

uint32x2_t vcage_f32
(float32x2_t a, a → Vn.2S FACGE Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

uint32x4_t vcageq_f32
(float32x4_t a, a → Vn.4S FACGE Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

uint64x1_t vcage_f64
(float64x1_t a, a → Dn FACGE Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

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uint64x2_t vcageq_f64
(float64x2_t a, a → Vn.2D FACGE Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

uint32_t vcages_f32
(float32_t a, a → Sn FACGE Sd,Sn,Sm Sd ARMv8(AArch64)
float32_t b) b → Sm

uint64_t vcaged_f64
(float64_t a, a → Dn FACGE Dd,Dn,Dm Dd ARMv8(AArch64)
float64_t b) b → Dm

uint32x2_t vcale_f32
(float32x2_t a, a → Vn.2S FACGE Vd.2S,Vm.2S,Vn.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

uint32x4_t vcaleq_f32
(float32x4_t a, a → Vn.4S FACGE Vd.4S,Vm.4S,Vn.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

uint64x1_t vcale_f64
(float64x1_t a, a → Dn FACGE Dd,Dm,Dn Dd ARMv8(AArch64)
float64x1_t b) b → Dm

uint64x2_t vcaleq_f64
(float64x2_t a, a → Vn.2D FACGE Vd.2D,Vm.2D,Vn.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

uint32_t vcales_f32
(float32_t a, a → Sn FACGE Sd,Sm,Sn Sd ARMv8(AArch64)
float32_t b) b → Sm

uint64_t vcaled_f64
(float64_t a, a → Dn FACGE Dd,Dm,Dn Dd ARMv8(AArch64)
float64_t b) b → Dm

uint32x2_t vcagt_f32
(float32x2_t a, a → Vn.2S FACGT Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

uint32x4_t vcagtq_f32
(float32x4_t a, a → Vn.4S FACGT Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

uint64x1_t vcagt_f64
(float64x1_t a, a → Dn FACGT Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

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uint64x2_t vcagtq_f64
(float64x2_t a, a → Vn.2D FACGT Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

uint32_t vcagts_f32
(float32_t a, a → Sn FACGT Sd,Sn,Sm Sd ARMv8(AArch64)
float32_t b) b → Sm

uint64_t vcagtd_f64
(float64_t a, a → Dn FACGT Dd,Dn,Dm Dd ARMv8(AArch64)
float64_t b) b → Dm

uint32x2_t vcalt_f32
(float32x2_t a, a → Vn.2S FACGT Vd.2S,Vm.2S,Vn.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

uint32x4_t vcaltq_f32
(float32x4_t a, a → Vn.4S FACGT Vd.4S,Vm.4S,Vn.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

uint64x1_t vcalt_f64
(float64x1_t a, a → Dn FACGT Dd,Dm,Dn Dd ARMv8(AArch64)
float64x1_t b) b → Dm

uint64x2_t vcaltq_f64
(float64x2_t a, a → Vn.2D FACGT Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

uint32_t vcalts_f32
(float32_t a, a → Sn FACGT Sd,Sm,Sn Sd ARMv8(AArch64)
float32_t b) b → Sm

uint64_t vcaltd_f64
(float64_t a, a → Dn FACGT Dd,Dm,Dn Dd ARMv8(AArch64)
float64_t b) b → Dm

uint8x8_t vtst_s8
(int8x8_t a, a → Vn.8B CMTST Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

uint8x16_t vtstq_s8
(int8x16_t a, a → Vn.16B CMTST Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

uint16x4_t vtst_s16
(int16x4_t a, a → Vn.4H CMTST Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

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uint16x8_t vtstq_s16
(int16x8_t a, a → Vn.8H CMTST Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

uint32x2_t vtst_s32
(int32x2_t a, a → Vn.2S CMTST Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint32x4_t vtstq_s32
(int32x4_t a, a → Vn.4S CMTST Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint8x8_t vtst_u8
(uint8x8_t a, a → Vn.8B CMTST Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vtstq_u8
(uint8x16_t a, a → Vn.16B CMTST Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vtst_u16
(uint16x4_t a, a → Vn.4H CMTST Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vtstq_u16
(uint16x8_t a, a → Vn.8H CMTST Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vtst_u32
(uint32x2_t a, a → Vn.2S CMTST Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

uint32x4_t vtstq_u32
(uint32x4_t a, a → Vn.4S CMTST Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

uint8x8_t vtst_p8
(poly8x8_t a, a → Vn.8B CMTST Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
poly8x8_t b) b → Vm.8B

uint8x16_t vtstq_p8
(poly8x16_t a, a → Vn.16B CMTST Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
poly8x16_t b) b → Vm.16B

uint16x4_t vtst_p16
(poly16x4_t a, a → Vn.4H CMTST Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
poly16x4_t b) b → Vm.4H

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uint16x8_t vtstq_p16
(poly16x8_t a, a → Vn.8H CMTST Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
poly16x8_t b) b → Vm.8H

uint64x1_t vtst_s64
(int64x1_t a, a → Dn CMTST Dd,Dn,Dm Dd ARMv8(AArch64)
int64x1_t b) b → Dm

uint64x2_t vtstq_s64
(int64x2_t a, a → Vn.2D CMTST Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
int64x2_t b) b → Vm.2D

uint64x1_t vtst_u64
(uint64x1_t a, a → Dn CMTST Dd,Dn,Dm Dd ARMv8(AArch64)
uint64x1_t b) b → Dm

uint64x2_t vtstq_u64
(uint64x2_t a, a → Vn.2D CMTST Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
uint64x2_t b) b → Vm.2D

uint64x1_t vtst_p64
(poly64x1_t a, a → Dn CMTST Dd,Dn,Dm Dd ARMv8
poly64x1_t b) b → Dm

uint64x2_t vtstq_p64
(poly64x2_t a, a → Vn.2D CMTST Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8
poly64x2_t b) b → Vm.2D

uint64_t vtstd_s64
(int64_t a, a → Dn CMTST Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

uint64_t vtstd_u64
(uint64_t a, a → Dn CMTST Dd,Dn,Dm Dd ARMv8(AArch64)
uint64_t b) b → Dm

int8x8_t vabd_s8
(int8x8_t a, a → Vn.8B SABD Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int8x16_t vabdq_s8
(int8x16_t a, a → Vn.16B SABD Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vabd_s16
(int16x4_t a, a → Vn.4H SABD Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

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int16x8_t vabdq_s16
(int16x8_t a, a → Vn.8H SABD Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vabd_s32
(int32x2_t a, a → Vn.2S SABD Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

int32x4_t vabdq_s32
(int32x4_t a, a → Vn.4S SABD Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint8x8_t vabd_u8
(uint8x8_t a, a → Vn.8B UABD Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vabdq_u8
(uint8x16_t a, a → Vn.16B UABD Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vabd_u16
(uint16x4_t a, a → Vn.4H UABD Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vabdq_u16
(uint16x8_t a, a → Vn.8H UABD Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vabd_u32
(uint32x2_t a, a → Vn.2S UABD Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

uint32x4_t vabdq_u32
(uint32x4_t a, a → Vn.4S UABD Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

float32x2_t vabd_f32
(float32x2_t a, a → Vn.2S FABD Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

float32x4_t vabdq_f32
(float32x4_t a, a → Vn.4S FABD Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

float64x1_t vabd_f64
(float64x1_t a, a → Dn FABD Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

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float64x2_t vabdq_f64
(float64x2_t a, a → Vn.2D FABD Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

float32_t vabds_f32
(float32_t a, a → Sn FABD Sd,Sn,Sm Sd ARMv8(AArch64)
float32_t b) b → Sm

float64_t vabdd_f64
(float64_t a, a → Dn FABD Dd,Dn,Dm Dd ARMv8(AArch64)
float64_t b) b → Dm

int16x8_t vabdl_s8
(int8x8_t a, a → Vn.8B SABDL Vd.8H,Vn.8B,Vm.8B Vd.8H ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int32x4_t vabdl_s16
(int16x4_t a, a → Vn.4H SABDL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int64x2_t vabdl_s32
(int32x2_t a, a → Vn.2S SABDL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint16x8_t vabdl_u8
(uint8x8_t a, a → Vn.8B UABDL Vd.8H,Vn.8B,Vm.8B Vd.8H ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint32x4_t vabdl_u16
(uint16x4_t a, a → Vn.4H UABDL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint64x2_t vabdl_u32
(uint32x2_t a, a → Vn.2S UABDL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

int16x8_t vabdl_high_s8
(int8x16_t a, a → Vn.16B SABDL2 Vd.8H,Vn.16B,Vm.16B Vd.8H ARMv8(AArch64)
int8x16_t b) b → Vm.16B

int32x4_t vabdl_high_s16
(int16x8_t a, a → Vn.8H SABDL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int64x2_t vabdl_high_s32
(int32x4_t a, a → Vn.4S SABDL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
int32x4_t b) b → Vm.4S

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uint16x8_t vabdl_high_u8
(uint8x16_t a, a → Vn.16B UABDL2 Vd.8H,Vn.16B,Vm.16B Vd.8H ARMv8(AArch64)
uint8x16_t b) b → Vm.16B

uint32x4_t vabdl_high_u16
(uint16x8_t a, a → Vn.8H UABDL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
uint16x8_t b) b → Vm.8H

uint64x2_t vabdl_high_u32
(uint32x4_t a, a → Vn.4S UABDL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
uint32x4_t b) b → Vm.4S

int8x8_t vaba_s8
(int8x8_t a, a → Vd.8B
SABA Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b, b → Vn.8B
int8x8_t c) c → Vm.8B

int8x16_t vabaq_s8
(int8x16_t a, a → Vd.16B
SABA Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b, b → Vn.16B
int8x16_t c) c → Vm.16B

int16x4_t vaba_s16
(int16x4_t a, a → Vd.4H
SABA Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b, b → Vn.4H
int16x4_t c) c → Vm.4H

int16x8_t vabaq_s16
(int16x8_t a, a → Vd.8H
SABA Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b, b → Vn.8H
int16x8_t c) c → Vm.8H

int32x2_t vaba_s32
(int32x2_t a, a → Vd.2S
SABA Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b, b → Vn.2S
int32x2_t c) c → Vm.2S

int32x4_t vabaq_s32
(int32x4_t a, a → Vd.4S
SABA Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b, b → Vn.4S
int32x4_t c) c → Vm.4S

uint8x8_t vaba_u8
(uint8x8_t a, a → Vd.8B
UABA Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b, b → Vn.8B
uint8x8_t c) c → Vm.8B

uint8x16_t vabaq_u8
(uint8x16_t a, a → Vd.16B
UABA Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b, b → Vn.16B
uint8x16_t c) c → Vm.16B

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uint16x4_t vaba_u16
(uint16x4_t a, a → Vd.4H
UABA Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b, b → Vn.4H
uint16x4_t c) c → Vm.4H

uint16x8_t vabaq_u16
(uint16x8_t a, a → Vd.8H
UABA Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b, b → Vn.8H
uint16x8_t c) c → Vm.8H

uint32x2_t vaba_u32
(uint32x2_t a, a → Vd.2S
UABA Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b, b → Vn.2S
uint32x2_t c) c → Vm.2S

uint32x4_t vabaq_u32
(uint32x4_t a, a → Vd.4S
UABA Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b, b → Vn.4S
uint32x4_t c) c → Vm.4S

int16x8_t vabal_s8
(int16x8_t a, a → Vd.8H
SABAL Vd.8H,Vn.8B,Vm.8B Vd.8H ARMv7, ARMv8
int8x8_t b, b → Vn.8B
int8x8_t c) c → Vm.8B

int32x4_t vabal_s16
(int32x4_t a, a → Vd.4S
SABAL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
int16x4_t b, b → Vn.4H
int16x4_t c) c → Vm.4H

int64x2_t vabal_s32
(int64x2_t a, a → Vd.2D
SABAL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
int32x2_t b, b → Vn.2S
int32x2_t c) c → Vm.2S

uint16x8_t vabal_u8
(uint16x8_t a, a → Vd.8H
UABAL Vd.8H,Vn.8B,Vm.8B Vd.8H ARMv7, ARMv8
uint8x8_t b, b → Vn.8B
uint8x8_t c) c → Vm.8B

uint32x4_t vabal_u16
(uint32x4_t a, a → Vd.4S
UABAL Vd.4S,Vn.4H,Vm.4H Vd.4S ARMv7, ARMv8
uint16x4_t b, b → Vn.4H
uint16x4_t c) c → Vm.4H

uint64x2_t vabal_u32
(uint64x2_t a, a → Vd.2D
UABAL Vd.2D,Vn.2S,Vm.2S Vd.2D ARMv7, ARMv8
uint32x2_t b, b → Vn.2S
uint32x2_t c) c → Vm.2S

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int16x8_t vabal_high_s8
(int16x8_t a, a → Vd.8H
SABAL2 Vd.8H,Vn.16B,Vm.16B Vd.8H ARMv8(AArch64)
int8x16_t b, b → Vn.16B
int8x16_t c) c → Vm.16B

int32x4_t vabal_high_s16
(int32x4_t a, a → Vd.4S
SABAL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
int16x8_t b, b → Vn.8H
int16x8_t c) c → Vm.8H

int64x2_t vabal_high_s32
(int64x2_t a, a → Vd.2D
SABAL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
int32x4_t b, b → Vn.4S
int32x4_t c) c → Vm.4S

uint16x8_t vabal_high_u8
(uint16x8_t a, a → Vd.8H
UABAL2 Vd.8H,Vn.16B,Vm.16B Vd.8H ARMv8(AArch64)
uint8x16_t b, b → Vn.16B
uint8x16_t c) c → Vm.16B

uint32x4_t vabal_high_u16
(uint32x4_t a, a → Vd.4S
UABAL2 Vd.4S,Vn.8H,Vm.8H Vd.4S ARMv8(AArch64)
uint16x8_t b, b → Vn.8H
uint16x8_t c) c → Vm.8H

uint64x2_t vabal_high_u32
(uint64x2_t a, a → Vd.2D
UABAL2 Vd.2D,Vn.4S,Vm.4S Vd.2D ARMv8(AArch64)
uint32x4_t b, b → Vn.4S
uint32x4_t c) c → Vm.4S

int8x8_t vmax_s8
(int8x8_t a, a → Vn.8B SMAX Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int8x16_t vmaxq_s8
(int8x16_t a, a → Vn.16B SMAX Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vmax_s16
(int16x4_t a, a → Vn.4H SMAX Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int16x8_t vmaxq_s16
(int16x8_t a, a → Vn.8H SMAX Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vmax_s32
(int32x2_t a, a → Vn.2S SMAX Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

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int32x4_t vmaxq_s32
(int32x4_t a, a → Vn.4S SMAX Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint8x8_t vmax_u8
(uint8x8_t a, a → Vn.8B UMAX Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vmaxq_u8
(uint8x16_t a, a → Vn.16B UMAX Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vmax_u16
(uint16x4_t a, a → Vn.4H UMAX Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vmaxq_u16
(uint16x8_t a, a → Vn.8H UMAX Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vmax_u32
(uint32x2_t a, a → Vn.2S UMAX Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

uint32x4_t vmaxq_u32
(uint32x4_t a, a → Vn.4S UMAX Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

float32x2_t vmax_f32
(float32x2_t a, a → Vn.2S FMAX Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

float32x4_t vmaxq_f32
(float32x4_t a, a → Vn.4S FMAX Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

float64x1_t vmax_f64
(float64x1_t a, a → Dn FMAX Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

float64x2_t vmaxq_f64
(float64x2_t a, a → Vn.2D FMAX Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

int8x8_t vmin_s8
(int8x8_t a, a → Vn.8B SMIN Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

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int8x16_t vminq_s8
(int8x16_t a, a → Vn.16B SMIN Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vmin_s16
(int16x4_t a, a → Vn.4H SMIN Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int16x8_t vminq_s16
(int16x8_t a, a → Vn.8H SMIN Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vmin_s32
(int32x2_t a, a → Vn.2S SMIN Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

int32x4_t vminq_s32
(int32x4_t a, a → Vn.4S SMIN Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint8x8_t vmin_u8
(uint8x8_t a, a → Vn.8B UMIN Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vminq_u8
(uint8x16_t a, a → Vn.16B UMIN Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vmin_u16
(uint16x4_t a, a → Vn.4H UMIN Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint16x8_t vminq_u16
(uint16x8_t a, a → Vn.8H UMIN Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
uint16x8_t b) b → Vm.8H

uint32x2_t vmin_u32
(uint32x2_t a, a → Vn.2S UMIN Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

uint32x4_t vminq_u32
(uint32x4_t a, a → Vn.4S UMIN Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
uint32x4_t b) b → Vm.4S

float32x2_t vmin_f32
(float32x2_t a, a → Vn.2S FMIN Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

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float32x4_t vminq_f32
(float32x4_t a, a → Vn.4S FMIN Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

float64x1_t vmin_f64
(float64x1_t a, a → Dn FMIN Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

float64x2_t vminq_f64
(float64x2_t a, a → Vn.2D FMIN Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

float32x2_t vmaxnm_f32
(float32x2_t a, a → Vn.2S FMAXNM Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8
float32x2_t b) b → Vm.2S

float32x4_t vmaxnmq_f32
(float32x4_t a, a → Vn.4S FMAXNM Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8
float32x4_t b) b → Vm.4S

float64x1_t vmaxnm_f64
(float64x1_t a, a → Dn FMAXNM Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

float64x2_t vmaxnmq_f64
(float64x2_t a, a → Vn.2D FMAXNM Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

float32x2_t vminnm_f32
(float32x2_t a, a → Vn.2S FMINNM Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8
float32x2_t b) b → Vm.2S

float32x4_t vminnmq_f32
(float32x4_t a, a → Vn.4S FMINNM Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8
float32x4_t b) b → Vm.4S

float64x1_t vminnm_f64
(float64x1_t a, a → Dn FMINNM Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

float64x2_t vminnmq_f64
(float64x2_t a, a → Vn.2D FMINNM Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

int8x8_t vshl_s8
(int8x8_t a, a → Vn.8B SSHL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

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int8x16_t vshlq_s8
(int8x16_t a, a → Vn.16B SSHL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vshl_s16
(int16x4_t a, a → Vn.4H SSHL Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int16x8_t vshlq_s16
(int16x8_t a, a → Vn.8H SSHL Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vshl_s32
(int32x2_t a, a → Vn.2S SSHL Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

int32x4_t vshlq_s32
(int32x4_t a, a → Vn.4S SSHL Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

int64x1_t vshl_s64
(int64x1_t a, a → Dn SSHL Dd,Dn,Dm Dd ARMv7, ARMv8
int64x1_t b) b → Dm

int64x2_t vshlq_s64
(int64x2_t a, a → Vn.2D SSHL Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
int64x2_t b) b → Vm.2D

uint8x8_t vshl_u8
(uint8x8_t a, a → Vn.8B USHL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

uint8x16_t vshlq_u8
(uint8x16_t a, a → Vn.16B USHL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

uint16x4_t vshl_u16
(uint16x4_t a, a → Vn.4H USHL Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

uint16x8_t vshlq_u16
(uint16x8_t a, a → Vn.8H USHL Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

uint32x2_t vshl_u32
(uint32x2_t a, a → Vn.2S USHL Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

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uint32x4_t vshlq_u32
(uint32x4_t a, a → Vn.4S USHL Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint64x1_t vshl_u64
(uint64x1_t a, a → Dn USHL Dd,Dn,Dm Dd ARMv7, ARMv8
int64x1_t b) b → Dm

uint64x2_t vshlq_u64
(uint64x2_t a, a → Vn.2D USHL Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
int64x2_t b) b → Vm.2D

int64_t vshld_s64
(int64_t a, a → Dn SSHL Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

uint64_t vshld_u64
(uint64_t a, a → Dn USHL Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

int8x8_t vqshl_s8
(int8x8_t a, a → Vn.8B SQSHL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int8x16_t vqshlq_s8
(int8x16_t a, a → Vn.16B SQSHL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vqshl_s16
(int16x4_t a, a → Vn.4H SQSHL Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int16x8_t vqshlq_s16
(int16x8_t a, a → Vn.8H SQSHL Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vqshl_s32
(int32x2_t a, a → Vn.2S SQSHL Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

int32x4_t vqshlq_s32
(int32x4_t a, a → Vn.4S SQSHL Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

int64x1_t vqshl_s64
(int64x1_t a, a → Dn SQSHL Dd,Dn,Dm Dd ARMv7, ARMv8
int64x1_t b) b → Dm

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int64x2_t vqshlq_s64
(int64x2_t a, a → Vn.2D SQSHL Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
int64x2_t b) b → Vm.2D

uint8x8_t vqshl_u8
(uint8x8_t a, a → Vn.8B UQSHL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

uint8x16_t vqshlq_u8
(uint8x16_t a, a → Vn.16B UQSHL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

uint16x4_t vqshl_u16
(uint16x4_t a, a → Vn.4H UQSHL Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

uint16x8_t vqshlq_u16
(uint16x8_t a, a → Vn.8H UQSHL Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

uint32x2_t vqshl_u32
(uint32x2_t a, a → Vn.2S UQSHL Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint32x4_t vqshlq_u32
(uint32x4_t a, a → Vn.4S UQSHL Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint64x1_t vqshl_u64
(uint64x1_t a, a → Dn UQSHL Dd,Dn,Dm Dd ARMv7, ARMv8
int64x1_t b) b → Dm

uint64x2_t vqshlq_u64
(uint64x2_t a, a → Vn.2D UQSHL Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
int64x2_t b) b → Vm.2D

int8_t vqshlb_s8
(int8_t a, a → Bn SQSHL Bd,Bn,Bm Bd ARMv8(AArch64)
int8_t b) b → Bm

int16_t vqshlh_s16
(int16_t a, a → Hn SQSHL Hd,Hn,Hm Hd ARMv8(AArch64)
int16_t b) b → Hm

int32_t vqshls_s32
(int32_t a, a → Sn SQSHL Sd,Sn,Sm Sd ARMv8(AArch64)
int32_t b) b → Sm

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int64_t vqshld_s64
(int64_t a, a → Dn SQSHL Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

uint8_t vqshlb_u8
(uint8_t a, a → Bn UQSHL Bd,Bn,Bm Bd ARMv8(AArch64)
int8_t b) b → Bm

uint16_t vqshlh_u16
(uint16_t a, a → Hn UQSHL Hd,Hn,Hm Hd ARMv8(AArch64)
int16_t b) b → Hm

uint32_t vqshls_u32
(uint32_t a, a → Sn UQSHL Sd,Sn,Sm Sd ARMv8(AArch64)
int32_t b) b → Sm

uint64_t vqshld_u64
(uint64_t a, a → Dn UQSHL Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

int8x8_t vrshl_s8
(int8x8_t a, a → Vn.8B SRSHL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int8x16_t vrshlq_s8
(int8x16_t a, a → Vn.16B SRSHL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vrshl_s16
(int16x4_t a, a → Vn.4H SRSHL Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int16x8_t vrshlq_s16
(int16x8_t a, a → Vn.8H SRSHL Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vrshl_s32
(int32x2_t a, a → Vn.2S SRSHL Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

int32x4_t vrshlq_s32
(int32x4_t a, a → Vn.4S SRSHL Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

int64x1_t vrshl_s64
(int64x1_t a, a → Dn SRSHL Dd,Dn,Dm Dd ARMv7, ARMv8
int64x1_t b) b → Dm

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int64x2_t vrshlq_s64
(int64x2_t a, a → Vn.2D SRSHL Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
int64x2_t b) b → Vm.2D

uint8x8_t vrshl_u8
(uint8x8_t a, a → Vn.8B URSHL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

uint8x16_t vrshlq_u8
(uint8x16_t a, a → Vn.16B URSHL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

uint16x4_t vrshl_u16
(uint16x4_t a, a → Vn.4H URSHL Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

uint16x8_t vrshlq_u16
(uint16x8_t a, a → Vn.8H URSHL Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

uint32x2_t vrshl_u32
(uint32x2_t a, a → Vn.2S URSHL Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint32x4_t vrshlq_u32
(uint32x4_t a, a → Vn.4S URSHL Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint64x1_t vrshl_u64
(uint64x1_t a, a → Dn URSHL Dd,Dn,Dm Dd ARMv7, ARMv8
int64x1_t b) b → Dm

uint64x2_t vrshlq_u64
(uint64x2_t a, a → Vn.2D URSHL Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
int64x2_t b) b → Vm.2D

int64_t vrshld_s64
(int64_t a, a → Dn SRSHL Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

uint64_t vrshld_u64
(uint64_t a, a → Dn URSHL Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

int8x8_t vqrshl_s8
(int8x8_t a, a → Vn.8B SQRSHL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

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int8x16_t vqrshlq_s8
(int8x16_t a, a → Vn.16B SQRSHL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vqrshl_s16
(int16x4_t a, a → Vn.4H SQRSHL Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int16x8_t vqrshlq_s16
(int16x8_t a, a → Vn.8H SQRSHL Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

int32x2_t vqrshl_s32
(int32x2_t a, a → Vn.2S SQRSHL Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

int32x4_t vqrshlq_s32
(int32x4_t a, a → Vn.4S SQRSHL Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

int64x1_t vqrshl_s64
(int64x1_t a, a → Dn SQRSHL Dd,Dn,Dm Dd ARMv7, ARMv8
int64x1_t b) b → Dm

int64x2_t vqrshlq_s64
(int64x2_t a, a → Vn.2D SQRSHL Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
int64x2_t b) b → Vm.2D

uint8x8_t vqrshl_u8
(uint8x8_t a, a → Vn.8B UQRSHL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

uint8x16_t vqrshlq_u8
(uint8x16_t a, a → Vn.16B UQRSHL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

uint16x4_t vqrshl_u16
(uint16x4_t a, a → Vn.4H UQRSHL Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

uint16x8_t vqrshlq_u16
(uint16x8_t a, a → Vn.8H UQRSHL Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv7, ARMv8
int16x8_t b) b → Vm.8H

uint32x2_t vqrshl_u32
(uint32x2_t a, a → Vn.2S UQRSHL Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

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uint32x4_t vqrshlq_u32
(uint32x4_t a, a → Vn.4S UQRSHL Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
int32x4_t b) b → Vm.4S

uint64x1_t vqrshl_u64
(uint64x1_t a, a → Dn UQRSHL Dd,Dn,Dm Dd ARMv7, ARMv8
int64x1_t b) b → Dm

uint64x2_t vqrshlq_u64
(uint64x2_t a, a → Vn.2D UQRSHL Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv7, ARMv8
int64x2_t b) b → Vm.2D

int8_t vqrshlb_s8
(int8_t a, a → Bn SQRSHL Bd,Bn,Bm Bd ARMv8(AArch64)
int8_t b) b → Bm

int16_t vqrshlh_s16
(int16_t a, a → Hn SQRSHL Hd,Hn,Hm Hd ARMv8(AArch64)
int16_t b) b → Hm

int32_t vqrshls_s32
(int32_t a, a → Sn SQRSHL Sd,Sn,Sm Sd ARMv8(AArch64)
int32_t b) b → Sm

int64_t vqrshld_s64
(int64_t a, a → Dn SQRSHL Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

uint8_t vqrshlb_u8
(uint8_t a, a → Bn UQRSHL Bd,Bn,Bm Bd ARMv8(AArch64)
int8_t b) b → Bm

uint16_t vqrshlh_u16
(uint16_t a, a → Hn UQRSHL Hd,Hn,Hm Hd ARMv8(AArch64)
int16_t b) b → Hm

uint32_t vqrshls_u32
(uint32_t a, a → Sn UQRSHL Sd,Sn,Sm Sd ARMv8(AArch64)
int32_t b) b → Sm

uint64_t vqrshld_u64
(uint64_t a, a → Dn UQRSHL Dd,Dn,Dm Dd ARMv8(AArch64)
int64_t b) b → Dm

int8x8_t vshr_n_s8
(int8x8_t a, a → Vn.8B SSHR Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
const int n) 1 <= n <= 8

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int8x16_t vshrq_n_s8
(int8x16_t a, a → Vn.16B SSHR Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
const int n) 1 <= n <= 8

int16x4_t vshr_n_s16
(int16x4_t a, a → Vn.4H SSHR Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
const int n) 1 <= n <= 16

int16x8_t vshrq_n_s16
(int16x8_t a, a → Vn.8H SSHR Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
const int n) 1 <= n <= 16

int32x2_t vshr_n_s32
(int32x2_t a, a → Vn.2S SSHR Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

int32x4_t vshrq_n_s32
(int32x4_t a, a → Vn.4S SSHR Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
const int n) 1 <= n <= 32

int64x1_t vshr_n_s64
(int64x1_t a, a → Dn SSHR Dd,Dn,#n Dd ARMv7, ARMv8
const int n) 1 <= n <= 64

int64x2_t vshrq_n_s64
(int64x2_t a, a → Vn.2D SSHR Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
const int n) 1 <= n <= 64

uint8x8_t vshr_n_u8
(uint8x8_t a, a → Vn.8B USHR Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
const int n) 1 <= n <= 8

uint8x16_t vshrq_n_u8
(uint8x16_t a, a → Vn.16B USHR Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
const int n) 1 <= n <= 8

uint16x4_t vshr_n_u16
(uint16x4_t a, a → Vn.4H USHR Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
const int n) 1 <= n <= 16

uint16x8_t vshrq_n_u16
(uint16x8_t a, a → Vn.8H USHR Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
const int n) 1 <= n <= 16

uint32x2_t vshr_n_u32
(uint32x2_t a, a → Vn.2S USHR Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 80 of 348
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uint32x4_t vshrq_n_u32
(uint32x4_t a, a → Vn.4S USHR Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
const int n) 1 <= n <= 32

uint64x1_t vshr_n_u64
(uint64x1_t a, a → Dn USHR Dd,Dn,#n Dd ARMv7, ARMv8
const int n) 1 <= n <= 64

uint64x2_t vshrq_n_u64
(uint64x2_t a, a → Vn.2D USHR Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
const int n) 1 <= n <= 64

int64_t vshrd_n_s64
(int64_t a, a → Dn SSHR Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 1 <= n <= 64

uint64_t vshrd_n_u64
(uint64_t a, a → Dn USHR Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 1 <= n <= 64

int8x8_t vshl_n_s8
(int8x8_t a, a → Vn.8B SHL Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
const int n) 0 <= n <= 7

int8x16_t vshlq_n_s8
(int8x16_t a, a → Vn.16B SHL Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
const int n) 0 <= n <= 7

int16x4_t vshl_n_s16
(int16x4_t a, a → Vn.4H SHL Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
const int n) 0 <= n <= 15

int16x8_t vshlq_n_s16
(int16x8_t a, a → Vn.8H SHL Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
const int n) 0 <= n <= 15

int32x2_t vshl_n_s32
(int32x2_t a, a → Vn.2S SHL Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
const int n) 0 <= n <= 31

int32x4_t vshlq_n_s32
(int32x4_t a, a → Vn.4S SHL Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
const int n) 0 <= n <= 31

int64x1_t vshl_n_s64
(int64x1_t a, a → Dn SHL Dd,Dn,#n Dd ARMv7, ARMv8
const int n) 0 <= n <= 63

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int64x2_t vshlq_n_s64
(int64x2_t a, a → Vn.2D SHL Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
const int n) 0 <= n <= 63

uint8x8_t vshl_n_u8
(uint8x8_t a, a → Vn.8B SHL Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
const int n) 0 <= n <= 7

uint8x16_t vshlq_n_u8
(uint8x16_t a, a → Vn.16B SHL Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
const int n) 0 <= n <= 7

uint16x4_t vshl_n_u16
(uint16x4_t a, a → Vn.4H SHL Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
const int n) 0 <= n <= 15

uint16x8_t vshlq_n_u16
(uint16x8_t a, a → Vn.8H SHL Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
const int n) 0 <= n <= 15

uint32x2_t vshl_n_u32
(uint32x2_t a, a → Vn.2S SHL Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
const int n) 0 <= n <= 31

uint32x4_t vshlq_n_u32
(uint32x4_t a, a → Vn.4S SHL Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
const int n) 0 <= n <= 31

uint64x1_t vshl_n_u64
(uint64x1_t a, a → Dn SHL Dd,Dn,#n Dd ARMv7, ARMv8
const int n) 0 <= n <= 63

uint64x2_t vshlq_n_u64
(uint64x2_t a, a → Vn.2D SHL Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
const int n) 0 <= n <= 63

int64_t vshld_n_s64
(int64_t a, a → Dn SHL Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 0 <= n <= 63

uint64_t vshld_n_u64
(uint64_t a, a → Dn SHL Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 0 <= n <= 63

int8x8_t vrshr_n_s8
(int8x8_t a, a → Vn.8B SRSHR Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
const int n) 1 <= n <= 8

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 82 of 348
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int8x16_t vrshrq_n_s8
(int8x16_t a, a → Vn.16B SRSHR Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
const int n) 1 <= n <= 8

int16x4_t vrshr_n_s16
(int16x4_t a, a → Vn.4H SRSHR Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
const int n) 1 <= n <= 16

int16x8_t vrshrq_n_s16
(int16x8_t a, a → Vn.8H SRSHR Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
const int n) 1 <= n <= 16

int32x2_t vrshr_n_s32
(int32x2_t a, a → Vn.2S SRSHR Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

int32x4_t vrshrq_n_s32
(int32x4_t a, a → Vn.4S SRSHR Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
const int n) 1 <= n <= 32

int64x1_t vrshr_n_s64
(int64x1_t a, a → Dn SRSHR Dd,Dn,#n Dd ARMv7, ARMv8
const int n) 1 <= n <= 64

int64x2_t vrshrq_n_s64
(int64x2_t a, a → Vn.2D SRSHR Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
const int n) 1 <= n <= 64

uint8x8_t vrshr_n_u8
(uint8x8_t a, a → Vn.8B URSHR Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
const int n) 1 <= n <= 8

uint8x16_t vrshrq_n_u8
(uint8x16_t a, a → Vn.16B URSHR Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
const int n) 1 <= n <= 8

uint16x4_t vrshr_n_u16
(uint16x4_t a, a → Vn.4H URSHR Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
const int n) 1 <= n <= 16

uint16x8_t vrshrq_n_u16
(uint16x8_t a, a → Vn.8H URSHR Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
const int n) 1 <= n <= 16

uint32x2_t vrshr_n_u32
(uint32x2_t a, a → Vn.2S URSHR Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 83 of 348
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uint32x4_t vrshrq_n_u32
(uint32x4_t a, a → Vn.4S URSHR Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
const int n) 1 <= n <= 32

uint64x1_t vrshr_n_u64
(uint64x1_t a, a → Dn URSHR Dd,Dn,#n Dd ARMv7, ARMv8
const int n) 1 <= n <= 64

uint64x2_t vrshrq_n_u64
(uint64x2_t a, a → Vn.2D URSHR Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
const int n) 1 <= n <= 64

int64_t vrshrd_n_s64
(int64_t a, a → Dn SRSHR Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 1 <= n <= 64

uint64_t vrshrd_n_u64
(uint64_t a, a → Dn URSHR Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 1 <= n <= 64

int8x8_t vsra_n_s8
(int8x8_t a, a → Vd.8B
SSRA Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
int8x8_t b, b → Vn.8B
const int n) 1 <= n <= 8

int8x16_t vsraq_n_s8
(int8x16_t a, a → Vd.16B
SSRA Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
int8x16_t b, b → Vn.16B
const int n) 1 <= n <= 8

int16x4_t vsra_n_s16
(int16x4_t a, a → Vd.4H
SSRA Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
int16x4_t b, b → Vn.4H
const int n) 1 <= n <= 16

int16x8_t vsraq_n_s16
(int16x8_t a, a → Vd.8H
SSRA Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
int16x8_t b, b → Vn.8H
const int n) 1 <= n <= 16

int32x2_t vsra_n_s32
(int32x2_t a, a → Vd.2S
SSRA Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
int32x2_t b, b → Vn.2S
const int n) 1 <= n <= 32

int32x4_t vsraq_n_s32
(int32x4_t a, a → Vd.4S
SSRA Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
int32x4_t b, b → Vn.4S
const int n) 1 <= n <= 32

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 84 of 348
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int64x1_t vsra_n_s64
(int64x1_t a, a → Dd
SSRA Dd,Dn,#n Dd ARMv7, ARMv8
int64x1_t b, b → Dn
const int n) 1 <= n <= 64

int64x2_t vsraq_n_s64
(int64x2_t a, a → Vd.2D
SSRA Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
int64x2_t b, b → Vn.2D
const int n) 1 <= n <= 64

uint8x8_t vsra_n_u8
(uint8x8_t a, a → Vd.8B
USRA Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
uint8x8_t b, b → Vn.8B
const int n) 1 <= n <= 8

uint8x16_t vsraq_n_u8
(uint8x16_t a, a → Vd.16B
USRA Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
uint8x16_t b, b → Vn.16B
const int n) 1 <= n <= 8

uint16x4_t vsra_n_u16
(uint16x4_t a, a → Vd.4H
USRA Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
uint16x4_t b, b → Vn.4H
const int n) 1 <= n <= 16

uint16x8_t vsraq_n_u16
(uint16x8_t a, a → Vd.8H
USRA Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
uint16x8_t b, b → Vn.8H
const int n) 1 <= n <= 16

uint32x2_t vsra_n_u32
(uint32x2_t a, a → Vd.2S
USRA Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
uint32x2_t b, b → Vn.2S
const int n) 1 <= n <= 32

uint32x4_t vsraq_n_u32
(uint32x4_t a, a → Vd.4S
USRA Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
uint32x4_t b, b → Vn.4S
const int n) 1 <= n <= 32

uint64x1_t vsra_n_u64
(uint64x1_t a, a → Dd
USRA Dd,Dn,#n Dd ARMv7, ARMv8
uint64x1_t b, b → Dn
const int n) 1 <= n <= 64

uint64x2_t vsraq_n_u64
(uint64x2_t a, a → Vd.2D
USRA Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
uint64x2_t b, b → Vn.2D
const int n) 1 <= n <= 64

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 85 of 348
Non-Confidential
int64_t vsrad_n_s64
(int64_t a, a → Dd
SSRA Dd,Dn,#n Dd ARMv8(AArch64)
int64_t b, b → Dn
const int n) 1 <= n <= 64

uint64_t vsrad_n_u64
(uint64_t a, a → Dd
USRA Dd,Dn,#n Dd ARMv8(AArch64)
uint64_t b, b → Dn
const int n) 1 <= n <= 64

int8x8_t vrsra_n_s8
(int8x8_t a, a → Vd.8B
SRSRA Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
int8x8_t b, b → Vn.8B
const int n) 1 <= n <= 8

int8x16_t vrsraq_n_s8
(int8x16_t a, a → Vd.16B
SRSRA Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
int8x16_t b, b → Vn.16B
const int n) 1 <= n <= 8

int16x4_t vrsra_n_s16
(int16x4_t a, a → Vd.4H
SRSRA Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
int16x4_t b, b → Vn.4H
const int n) 1 <= n <= 16

int16x8_t vrsraq_n_s16
(int16x8_t a, a → Vd.8H
SRSRA Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
int16x8_t b, b → Vn.8H
const int n) 1 <= n <= 16

int32x2_t vrsra_n_s32
(int32x2_t a, a → Vd.2S
SRSRA Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
int32x2_t b, b → Vn.2S
const int n) 1 <= n <= 32

int32x4_t vrsraq_n_s32
(int32x4_t a, a → Vd.4S
SRSRA Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
int32x4_t b, b → Vn.4S
const int n) 1 <= n <= 32

int64x1_t vrsra_n_s64
(int64x1_t a, a → Dd
SRSRA Dd,Dn,#n Dd ARMv7, ARMv8
int64x1_t b, b → Dn
const int n) 1 <= n <= 64

int64x2_t vrsraq_n_s64
(int64x2_t a, a → Vd.2D
SRSRA Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
int64x2_t b, b → Vn.2D
const int n) 1 <= n <= 64

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 86 of 348
Non-Confidential
uint8x8_t vrsra_n_u8
(uint8x8_t a, a → Vd.8B
URSRA Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
uint8x8_t b, b → Vn.8B
const int n) 1 <= n <= 8

uint8x16_t vrsraq_n_u8
(uint8x16_t a, a → Vd.16B
URSRA Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
uint8x16_t b, b → Vn.16B
const int n) 1 <= n <= 8

uint16x4_t vrsra_n_u16
(uint16x4_t a, a → Vd.4H
URSRA Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
uint16x4_t b, b → Vn.4H
const int n) 1 <= n <= 16

uint16x8_t vrsraq_n_u16
(uint16x8_t a, a → Vd.8H
URSRA Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
uint16x8_t b, b → Vn.8H
const int n) 1 <= n <= 16

uint32x2_t vrsra_n_u32
(uint32x2_t a, a → Vd.2S
URSRA Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
uint32x2_t b, b → Vn.2S
const int n) 1 <= n <= 32

uint32x4_t vrsraq_n_u32
(uint32x4_t a, a → Vd.4S
URSRA Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
uint32x4_t b, b → Vn.4S
const int n) 1 <= n <= 32

uint64x1_t vrsra_n_u64
(uint64x1_t a, a → Dd
URSRA Dd,Dn,#n Dd ARMv7, ARMv8
uint64x1_t b, b → Dn
const int n) 1 <= n <= 64

uint64x2_t vrsraq_n_u64
(uint64x2_t a, a → Vd.2D
URSRA Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
uint64x2_t b, b → Vn.2D
const int n) 1 <= n <= 64

int64_t vrsrad_n_s64
(int64_t a, a → Dd
SRSRA Dd,Dn,#n Dd ARMv8(AArch64)
int64_t b, b → Dn
const int n) 1 <= n <= 64

uint64_t vrsrad_n_u64
(uint64_t a, a → Dd
URSRA Dd,Dn,#n Dd ARMv8(AArch64)
uint64_t b, b → Dn
const int n) 1 <= n <= 64

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 87 of 348
Non-Confidential
int8x8_t vqshl_n_s8
(int8x8_t a, a → Vn.8B SQSHL Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
const int n) 0 <= n <= 7

int8x16_t vqshlq_n_s8
(int8x16_t a, a → Vn.16B SQSHL Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
const int n) 0 <= n <= 7

int16x4_t vqshl_n_s16
(int16x4_t a, a → Vn.4H SQSHL Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
const int n) 0 <= n <= 15

int16x8_t vqshlq_n_s16
(int16x8_t a, a → Vn.8H SQSHL Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
const int n) 0 <= n <= 15

int32x2_t vqshl_n_s32
(int32x2_t a, a → Vn.2S SQSHL Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
const int n) 0 <= n <= 31

int32x4_t vqshlq_n_s32
(int32x4_t a, a → Vn.4S SQSHL Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
const int n) 0 <= n <= 31

int64x1_t vqshl_n_s64
(int64x1_t a, a → Dn SQSHL Dd,Dn,#n Dd ARMv7, ARMv8
const int n) 0 <= n <= 63

int64x2_t vqshlq_n_s64
(int64x2_t a, a → Vn.2D SQSHL Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
const int n) 0 <= n <= 63

uint8x8_t vqshl_n_u8
(uint8x8_t a, a → Vn.8B UQSHL Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
const int n) 0 <= n <= 7

uint8x16_t vqshlq_n_u8
(uint8x16_t a, a → Vn.16B UQSHL Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
const int n) 0 <= n <= 7

uint16x4_t vqshl_n_u16
(uint16x4_t a, a → Vn.4H UQSHL Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
const int n) 0 <= n <= 15

uint16x8_t vqshlq_n_u16
(uint16x8_t a, a → Vn.8H UQSHL Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
const int n) 0 <= n <= 15

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 88 of 348
Non-Confidential
uint32x2_t vqshl_n_u32
(uint32x2_t a, a → Vn.2S UQSHL Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
const int n) 0 <= n <= 31

uint32x4_t vqshlq_n_u32
(uint32x4_t a, a → Vn.4S UQSHL Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
const int n) 0 <= n <= 31

uint64x1_t vqshl_n_u64
(uint64x1_t a, a → Dn UQSHL Dd,Dn,#n Dd ARMv7, ARMv8
const int n) 0 <= n <= 63

uint64x2_t vqshlq_n_u64
(uint64x2_t a, a → Vn.2D UQSHL Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
const int n) 0 <= n <= 63

int8_t vqshlb_n_s8
(int8_t a, a → Bn SQSHL Bd,Bn,#n Bd ARMv8(AArch64)
const int n) 0 <= n <= 7

int16_t vqshlh_n_s16
(int16_t a, a → Hn SQSHL Hd,Hn,#n Hd ARMv8(AArch64)
const int n) 0 <= n <= 15

int32_t vqshls_n_s32
(int32_t a, a → Sn SQSHL Sd,Sn,#n Sd ARMv8(AArch64)
const int n) 0 <= n <= 31

int64_t vqshld_n_s64
(int64_t a, a → Dn SQSHL Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 0 <= n <= 63

uint8_t vqshlb_n_u8
(uint8_t a, a → Bn UQSHL Bd,Bn,#n Bd ARMv8(AArch64)
const int n) 0 <= n <= 7

uint16_t vqshlh_n_u16
(uint16_t a, a → Hn UQSHL Hd,Hn,#n Hd ARMv8(AArch64)
const int n) 0 <= n <= 15

uint32_t vqshls_n_u32
(uint32_t a, a → Sn UQSHL Sd,Sn,#n Sd ARMv8(AArch64)
const int n) 0 <= n <= 31

uint64_t vqshld_n_u64
(uint64_t a, a → Dn UQSHL Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 0 <= n <= 63

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 89 of 348
Non-Confidential
uint8x8_t vqshlu_n_s8
(int8x8_t a, a → Vn.8B SQSHLU Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
const int n) 0 <= n <= 7

uint8x16_t vqshluq_n_s8
(int8x16_t a, a → Vn.16B SQSHLU Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
const int n) 0 <= n <= 7

uint16x4_t vqshlu_n_s16
(int16x4_t a, a → Vn.4H SQSHLU Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
const int n) 0 <= n <= 15

uint16x8_t vqshluq_n_s16
(int16x8_t a, a → Vn.8H SQSHLU Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
const int n) 0 <= n <= 15

uint32x2_t vqshlu_n_s32
(int32x2_t a, a → Vn.2S SQSHLU Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
const int n) 0 <= n <= 31

uint32x4_t vqshluq_n_s32
(int32x4_t a, a → Vn.4S SQSHLU Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
const int n) 0 <= n <= 31

uint64x1_t vqshlu_n_s64
(int64x1_t a, a → Dn SQSHLU Dd,Dn,#n Dd ARMv7, ARMv8
const int n) 0 <= n <= 63

uint64x2_t vqshluq_n_s64
(int64x2_t a, a → Vn.2D SQSHLU Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
const int n) 0 <= n <= 63

uint8_t vqshlub_n_s8
(int8_t a, a → Bn SQSHLU Bd,Bn,#n Bd ARMv8(AArch64)
const int n) 0 <= n <= 7

uint16_t vqshluh_n_s16
(int16_t a, a → Hn SQSHLU Hd,Hn,#n Hd ARMv8(AArch64)
const int n) 0 <= n <= 15

uint32_t vqshlus_n_s32
(int32_t a, a → Sn SQSHLU Sd,Sn,#n Sd ARMv8(AArch64)
const int n) 0 <= n <= 31

uint64_t vqshlud_n_s64
(int64_t a, a → Dn SQSHLU Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 0 <= n <= 63

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 90 of 348
Non-Confidential
int8x8_t vshrn_n_s16
(int16x8_t a, a → Vn.8H SHRN Vd.8B,Vn.8H,#n Vd.8B ARMv7, ARMv8
const int n) 1 <= n <= 8

int16x4_t vshrn_n_s32
(int32x4_t a, a → Vn.4S SHRN Vd.4H,Vn.4S,#n Vd.4H ARMv7, ARMv8
const int n) 1 <= n <= 16

int32x2_t vshrn_n_s64
(int64x2_t a, a → Vn.2D SHRN Vd.2S,Vn.2D,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

uint8x8_t vshrn_n_u16
(uint16x8_t a, a → Vn.8H SHRN Vd.8B,Vn.8H,#n Vd.8B ARMv7, ARMv8
const int n) 1 <= n <= 8

uint16x4_t vshrn_n_u32
(uint32x4_t a, a → Vn.4S SHRN Vd.4H,Vn.4S,#n Vd.4H ARMv7, ARMv8
const int n) 1 <= n <= 16

uint32x2_t vshrn_n_u64
(uint64x2_t a, a → Vn.2D SHRN Vd.2S,Vn.2D,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

int8x16_t vshrn_high_n_s16
(int8x8_t r, r → Vd.8B
SHRN2 Vd.16B,Vn.8H,#n Vd.16B ARMv8(AArch64)
int16x8_t a, a → Vn.8H
const int n) 1 <= n <= 8

int16x8_t vshrn_high_n_s32
(int16x4_t r, r → Vd.4H
SHRN2 Vd.8H,Vn.4S,#n Vd.8H ARMv8(AArch64)
int32x4_t a, a → Vn.4S
const int n) 1 <= n <= 16

int32x4_t vshrn_high_n_s64
(int32x2_t r, r → Vd.2S
SHRN2 Vd.4S,Vn.2D,#n Vd.4S ARMv8(AArch64)
int64x2_t a, a → Vn.2D
const int n) 1 <= n <= 32

uint8x16_t vshrn_high_n_u16
(uint8x8_t r, r → Vd.8B
SHRN2 Vd.16B,Vn.8H,#n Vd.16B ARMv8(AArch64)
uint16x8_t a, a → Vn.8H
const int n) 1 <= n <= 8

uint16x8_t vshrn_high_n_u32
(uint16x4_t r, r → Vd.4H
SHRN2 Vd.8H,Vn.4S,#n Vd.8H ARMv8(AArch64)
uint32x4_t a, a → Vn.4S
const int n) 1 <= n <= 16

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 91 of 348
Non-Confidential
uint32x4_t vshrn_high_n_u64
(uint32x2_t r, r → Vd.2S
SHRN2 Vd.4S,Vn.2D,#n Vd.4S ARMv8(AArch64)
uint64x2_t a, a → Vn.2D
const int n) 1 <= n <= 32

uint8x8_t vqshrun_n_s16
(int16x8_t a, a → Vn.8H SQSHRUN Vd.8B,Vn.8H,#n Vd.8B ARMv7, ARMv8
const int n) 1 <= n <= 8

uint16x4_t vqshrun_n_s32
(int32x4_t a, a → Vn.4S SQSHRUN Vd.4H,Vn.4S,#n Vd.4H ARMv7, ARMv8
const int n) 1 <= n <= 16

uint32x2_t vqshrun_n_s64
(int64x2_t a, a → Vn.2D SQSHRUN Vd.2S,Vn.2D,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

uint8_t vqshrunh_n_s16
(int16_t a, a → Hn SQSHRUN Bd,Hn,#n Bd ARMv8(AArch64)
const int n) 1 <= n <= 8

uint16_t vqshruns_n_s32
(int32_t a, a → Sn SQSHRUN Hd,Sn,#n Hd ARMv8(AArch64)
const int n) 1 <= n <= 16

uint32_t vqshrund_n_s64
(int64_t a, a → Dn SQSHRUN Sd,Dn,#n Sd ARMv8(AArch64)
const int n) 1 <= n <= 32

uint8x16_t vqshrun_high_n_s16
(uint8x8_t r, r → Vd.8B
SQSHRUN2 Vd.16B,Vn.8H,#n Vd.16B ARMv8(AArch64)
int16x8_t a, a → Vn.8H
const int n) 1 <= n <= 8

uint16x8_t vqshrun_high_n_s32
(uint16x4_t r, r → Vd.4H
SQSHRUN2 Vd.8H,Vn.4S,#n Vd.8H ARMv8(AArch64)
int32x4_t a, a → Vn.4S
const int n) 1 <= n <= 16

uint32x4_t vqshrun_high_n_s64
(uint32x2_t r, r → Vd.2S
SQSHRUN2 Vd.4S,Vn.2D,#n Vd.4S ARMv8(AArch64)
int64x2_t a, a → Vn.2D
const int n) 1 <= n <= 32

uint8x8_t vqrshrun_n_s16
(int16x8_t a, a → Vn.8H SQRSHRUN Vd.8B,Vn.8H,#n Vd.8B ARMv7, ARMv8
const int n) 1 <= n <= 8

uint16x4_t vqrshrun_n_s32
(int32x4_t a, a → Vn.4S SQRSHRUN Vd.4H,Vn.4S,#n Vd.4H ARMv7, ARMv8
const int n) 1 <= n <= 16

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 92 of 348
Non-Confidential
uint32x2_t vqrshrun_n_s64
(int64x2_t a, a → Vn.2D SQRSHRUN Vd.2S,Vn.2D,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

uint8_t vqrshrunh_n_s16
(int16_t a, a → Hn SQRSHRUN Bd,Hn,#n Bd ARMv8(AArch64)
const int n) 1 <= n <= 8

uint16_t vqrshruns_n_s32
(int32_t a, a → Sn SQRSHRUN Hd,Sn,#n Hd ARMv8(AArch64)
const int n) 1 <= n <= 16

uint32_t vqrshrund_n_s64
(int64_t a, a → Dn SQRSHRUN Sd,Dn,#n Sd ARMv8(AArch64)
const int n) 1 <= n <= 32

uint8x16_t vqrshrun_high_n_s16
(uint8x8_t r, r → Vd.8B
SQRSHRUN2 Vd.16B,Vn.8H,#n Vd.16B ARMv8(AArch64)
int16x8_t a, a → Vn.8H
const int n) 1 <= n <= 8

uint16x8_t vqrshrun_high_n_s32
(uint16x4_t r, r → Vd.4H
SQRSHRUN2 Vd.8H,Vn.4S,#n Vd.8H ARMv8(AArch64)
int32x4_t a, a → Vn.4S
const int n) 1 <= n <= 16

uint32x4_t vqrshrun_high_n_s64
(uint32x2_t r, r → Vd.2S
SQRSHRUN2 Vd.4S,Vn.2D,#n Vd.4S ARMv8(AArch64)
int64x2_t a, a → Vn.2D
const int n) 1 <= n <= 32

int8x8_t vqshrn_n_s16
(int16x8_t a, a → Vn.8H SQSHRN Vd.8B,Vn.8H,#n Vd.8B ARMv7, ARMv8
const int n) 1 <= n <= 8

int16x4_t vqshrn_n_s32
(int32x4_t a, a → Vn.4S SQSHRN Vd.4H,Vn.4S,#n Vd.4H ARMv7, ARMv8
const int n) 1 <= n <= 16

int32x2_t vqshrn_n_s64
(int64x2_t a, a → Vn.2D SQSHRN Vd.2S,Vn.2D,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

uint8x8_t vqshrn_n_u16
(uint16x8_t a, a → Vn.8H UQSHRN Vd.8B,Vn.8H,#n Vd.8B ARMv7, ARMv8
const int n) 1 <= n <= 8

uint16x4_t vqshrn_n_u32
(uint32x4_t a, a → Vn.4S UQSHRN Vd.4H,Vn.4S,#n Vd.4H ARMv7, ARMv8
const int n) 1 <= n <= 16

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 93 of 348
Non-Confidential
uint32x2_t vqshrn_n_u64
(uint64x2_t a, a → Vn.2D UQSHRN Vd.2S,Vn.2D,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

int8_t vqshrnh_n_s16
(int16_t a, a → Hn SQSHRN Bd,Hn,#n Bd ARMv8(AArch64)
const int n) 1 <= n <= 8

int16_t vqshrns_n_s32
(int32_t a, a → Sn SQSHRN Hd,Sn,#n Hd ARMv8(AArch64)
const int n) 1 <= n <= 16

int32_t vqshrnd_n_s64
(int64_t a, a → Dn SQSHRN Sd,Dn,#n Sd ARMv8(AArch64)
const int n) 1 <= n <= 32

uint8_t vqshrnh_n_u16
(uint16_t a, a → Hn UQSHRN Bd,Hn,#n Bd ARMv8(AArch64)
const int n) 1 <= n <= 8

uint16_t vqshrns_n_u32
(uint32_t a, a → Sn UQSHRN Hd,Sn,#n Hd ARMv8(AArch64)
const int n) 1 <= n <= 16

uint32_t vqshrnd_n_u64
(uint64_t a, a → Dn UQSHRN Sd,Dn,#n Sd ARMv8(AArch64)
const int n) 1 <= n <= 32

int8x16_t vqshrn_high_n_s16
(int8x8_t r, r → Vd.8B
SQSHRN2 Vd.16B,Vn.8H,#n Vd.16B ARMv8(AArch64)
int16x8_t a, a → Vn.8H
const int n) 1 <= n <= 8

int16x8_t vqshrn_high_n_s32
(int16x4_t r, r → Vd.4H
SQSHRN2 Vd.8H,Vn.4S,#n Vd.8H ARMv8(AArch64)
int32x4_t a, a → Vn.4S
const int n) 1 <= n <= 16

int32x4_t vqshrn_high_n_s64
(int32x2_t r, r → Vd.2S
SQSHRN2 Vd.4S,Vn.2D,#n Vd.4S ARMv8(AArch64)
int64x2_t a, a → Vn.2D
const int n) 1 <= n <= 32

uint8x16_t vqshrn_high_n_u16
(uint8x8_t r, r → Vd.8B
UQSHRN2 Vd.16B,Vn.8H,#n Vd.16B ARMv8(AArch64)
uint16x8_t a, a → Vn.8H
const int n) 1 <= n <= 8

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 94 of 348
Non-Confidential
uint16x8_t vqshrn_high_n_u32
(uint16x4_t r, r → Vd.4H
UQSHRN2 Vd.8H,Vn.4S,#n Vd.8H ARMv8(AArch64)
uint32x4_t a, a → Vn.4S
const int n) 1 <= n <= 16

uint32x4_t vqshrn_high_n_u64
(uint32x2_t r, r → Vd.2S
UQSHRN2 Vd.4S,Vn.2D,#n Vd.4S ARMv8(AArch64)
uint64x2_t a, a → Vn.2D
const int n) 1 <= n <= 32

int8x8_t vrshrn_n_s16
(int16x8_t a, a → Vn.8H RSHRN Vd.8B,Vn.8H,#n Vd.8B ARMv7, ARMv8
const int n) 1 <= n <= 8

int16x4_t vrshrn_n_s32
(int32x4_t a, a → Vn.4S RSHRN Vd.4H,Vn.4S,#n Vd.4H ARMv7, ARMv8
const int n) 1 <= n <= 16

int32x2_t vrshrn_n_s64
(int64x2_t a, a → Vn.2D RSHRN Vd.2S,Vn.2D,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

uint8x8_t vrshrn_n_u16
(uint16x8_t a, a → Vn.8H RSHRN Vd.8B,Vn.8H,#n Vd.8B ARMv7, ARMv8
const int n) 1 <= n <= 8

uint16x4_t vrshrn_n_u32
(uint32x4_t a, a → Vn.4S RSHRN Vd.4H,Vn.4S,#n Vd.4H ARMv7, ARMv8
const int n) 1 <= n <= 16

uint32x2_t vrshrn_n_u64
(uint64x2_t a, a → Vn.2D RSHRN Vd.2S,Vn.2D,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

int8x16_t vrshrn_high_n_s16
(int8x8_t r, r → Vd.8B
RSHRN2 Vd.16B,Vn.8H,#n Vd.16B ARMv8(AArch64)
int16x8_t a, a → Vn.8H
const int n) 1 <= n <= 8

int16x8_t vrshrn_high_n_s32
(int16x4_t r, r → Vd.4H
RSHRN2 Vd.8H,Vn.4S,#n Vd.8H ARMv8(AArch64)
int32x4_t a, a → Vn.4S
const int n) 1 <= n <= 16

int32x4_t vrshrn_high_n_s64
(int32x2_t r, r → Vd.2S
RSHRN2 Vd.4S,Vn.2D,#n Vd.4S ARMv8(AArch64)
int64x2_t a, a → Vn.2D
const int n) 1 <= n <= 32

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 95 of 348
Non-Confidential
uint8x16_t vrshrn_high_n_u16
(uint8x8_t r, r → Vd.8B
RSHRN2 Vd.16B,Vn.8H,#n Vd.16B ARMv8(AArch64)
uint16x8_t a, a → Vn.8H
const int n) 1 <= n <= 8

uint16x8_t vrshrn_high_n_u32
(uint16x4_t r, r → Vd.4H
RSHRN2 Vd.8H,Vn.4S,#n Vd.8H ARMv8(AArch64)
uint32x4_t a, a → Vn.4S
const int n) 1 <= n <= 16

uint32x4_t vrshrn_high_n_u64
(uint32x2_t r, r → 32(Vd)
RSHRN2 Vd.4S,Vn.2D,#n Vd.4S ARMv8(AArch64)
uint64x2_t a, a → Vn.2D
const int n) 1 <= n <= 32

int8x8_t vqrshrn_n_s16
(int16x8_t a, a → Vn.8H SQRSHRN Vd.8B,Vn.8H,#n Vd.8B ARMv7, ARMv8
const int n) 1 <= n <= 8

int16x4_t vqrshrn_n_s32
(int32x4_t a, a → Vn.4S SQRSHRN Vd.4H,Vn.4S,#n Vd.4H ARMv7, ARMv8
const int n) 1 <= n <= 16

int32x2_t vqrshrn_n_s64
(int64x2_t a, a → Vn.2D SQRSHRN Vd.2S,Vn.2D,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

uint8x8_t vqrshrn_n_u16
(uint16x8_t a, a → Vn.8H UQRSHRN Vd.8B,Vn.8H,#n Vd.8B ARMv7, ARMv8
const int n) 1 <= n <= 8

uint16x4_t vqrshrn_n_u32
(uint32x4_t a, a → Vn.4S UQRSHRN Vd.4H,Vn.4S,#n Vd.4H ARMv7, ARMv8
const int n) 1 <= n <= 16

uint32x2_t vqrshrn_n_u64
(uint64x2_t a, a → Vn.2D UQRSHRN Vd.2S,Vn.2D,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

int8_t vqrshrnh_n_s16
(int16_t a, a → Hn SQRSHRN Bd,Hn,#n Bd ARMv8(AArch64)
const int n) 1 <= n <= 8

int16_t vqrshrns_n_s32
(int32_t a, a → Sn SQRSHRN Hd,Sn,#n Hd ARMv8(AArch64)
const int n) 1 <= n <= 16

int32_t vqrshrnd_n_s64
(int64_t a, a → Dn SQRSHRN Sd,Dn,#n Sd ARMv8(AArch64)
const int n) 1 <= n <= 32

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 96 of 348
Non-Confidential
uint8_t vqrshrnh_n_u16
(uint16_t a, a → Hn UQRSHRN Bd,Hn,#n Bd ARMv8(AArch64)
const int n) 1 <= n <= 8

uint16_t vqrshrns_n_u32
(uint32_t a, a → Sn UQRSHRN Hd,Sn,#n Hd ARMv8(AArch64)
const int n) 1 <= n <= 16

uint32_t vqrshrnd_n_u64
(uint64_t a, a → Dn UQRSHRN Sd,Dn,#n Sd ARMv8(AArch64)
const int n) 1 <= n <= 32

int8x16_t vqrshrn_high_n_s16
(int8x8_t r, r → Vd.8B
SQRSHRN2 Vd.16B,Vn.8H,#n Vd.16B ARMv8(AArch64)
int16x8_t a, a → Vn.8H
const int n) 1 <= n <= 8

int16x8_t vqrshrn_high_n_s32
(int16x4_t r, r → Vd.4H
SQRSHRN2 Vd.8H,Vn.4S,#n Vd.8H ARMv8(AArch64)
int32x4_t a, a → Vn.4S
const int n) 1 <= n <= 16

int32x4_t vqrshrn_high_n_s64
(int32x2_t r, r → Vd.2S
SQRSHRN2 Vd.4S,Vn.2D,#n Vd.4S ARMv8(AArch64)
int64x2_t a, a → Vn.2D
const int n) 1 <= n <= 32

uint8x16_t vqrshrn_high_n_u16
(uint8x8_t r, r → Vd.8B
UQRSHRN2 Vd.16B,Vn.8H,#n Vd.16B ARMv8(AArch64)
uint16x8_t a, a → Vn.8H
const int n) 1 <= n <= 8

uint16x8_t vqrshrn_high_n_u32
(uint16x4_t r, r → Vd.4H
UQRSHRN2 Vd.8H,Vn.4S,#n Vd.8H ARMv8(AArch64)
uint32x4_t a, a → Vn.4S
const int n) 1 <= n <= 16

uint32x4_t vqrshrn_high_n_u64
(uint32x2_t r, r → Vd.2S
UQRSHRN2 Vd.4S,Vn.2D,#n Vd.4S ARMv8(AArch64)
uint64x2_t a, a → Vn.2D
const int n) 1 <= n <= 32

int16x8_t vshll_n_s8
(int8x8_t a, a → Vn.8B SSHLL Vd.8H,Vn.8B,#n Vd.8H ARMv7, ARMv8
const int n) 0 <= n <= 7

int32x4_t vshll_n_s16
(int16x4_t a, a → Vn.4H SSHLL Vd.4S,Vn.4H,#n Vd.4S ARMv7, ARMv8
const int n) 0 <= n <= 15

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int64x2_t vshll_n_s32
(int32x2_t a, a → Vn.2S SSHLL Vd.2D,Vn.2S,#n Vd.2D ARMv7, ARMv8
const int n) 0 <= n <= 31

uint16x8_t vshll_n_u8
(uint8x8_t a, a → Vn.8B USHLL Vd.8H,Vn.8B,#n Vd.8H ARMv7, ARMv8
const int n) 0 <= n <= 7

uint32x4_t vshll_n_u16
(uint16x4_t a, a → Vn.4H USHLL Vd.4S,Vn.4H,#n Vd.4S ARMv7, ARMv8
const int n) 0 <= n <= 15

uint64x2_t vshll_n_u32
(uint32x2_t a, a → Vn.2S USHLL Vd.2D,Vn.2S,#n Vd.2D ARMv7, ARMv8
const int n) 0 <= n <= 31

int16x8_t vshll_high_n_s8
(int8x16_t a, a → Vn.16B SSHLL2 Vd.8H,Vn.16B,#n Vd.8H ARMv8(AArch64)
const int n) 0 <= n <= 7

int32x4_t vshll_high_n_s16
(int16x8_t a, a → Vn.8H SSHLL2 Vd.4S,Vn.8H,#n Vd.4S ARMv8(AArch64)
const int n) 0 <= n <= 15

int64x2_t vshll_high_n_s32
(int32x4_t a, a → Vn.4S SSHLL2 Vd.2D,Vn.4S,#n Vd.2D ARMv8(AArch64)
const int n) 0 <= n <= 31

uint16x8_t vshll_high_n_u8
(uint8x16_t a, a → Vn.16B USHLL2 Vd.8H,Vn.16B,#n Vd.8H ARMv8(AArch64)
const int n) 0 <= n <= 7

uint32x4_t vshll_high_n_u16
(uint16x8_t a, a → Vn.8H USHLL2 Vd.4S,Vn.8H,#n Vd.4S ARMv8(AArch64)
const int n) 0 <= n <= 15

uint64x2_t vshll_high_n_u32
(uint32x4_t a, a → Vn.4S USHLL2 Vd.2D,Vn.4S,#n Vd.2D ARMv8(AArch64)
const int n) 0 <= n <= 31

int16x8_t vshll_n_s8
(int8x8_t a, a → Vn.8B SHLL Vd.8H,Vn.8B,#n Vd.8H ARMv7, ARMv8
const int n) n == 8

int32x4_t vshll_n_s16
(int16x4_t a, a → Vn.4H SHLL Vd.4S,Vn.4H,#n Vd.4S ARMv7, ARMv8
const int n) n == 16

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 98 of 348
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int64x2_t vshll_n_s32
(int32x2_t a, a → Vn.2S SHLL Vd.2D,Vn.2S,#n Vd.2D ARMv7, ARMv8
const int n) n == 32

uint16x8_t vshll_n_u8
(uint8x8_t a, a → Vn.8B SHLL Vd.8H,Vn.8B,#n Vd.8H ARMv7, ARMv8
const int n) n == 8

uint32x4_t vshll_n_u16
(uint16x4_t a, a → Vn.4H SHLL Vd.4S,Vn.4H,#n Vd.4S ARMv7, ARMv8
const int n) n == 16

uint64x2_t vshll_n_u32
(uint32x2_t a, a → Vn.2S SHLL Vd.2D,Vn.2S,#n Vd.2D ARMv7, ARMv8
const int n) n == 32

int16x8_t vshll_high_n_s8
(int8x16_t a, a → Vn.16B SHLL2 Vd.8H,Vn.16B,#n Vd.8H ARMv8(AArch64)
const int n) n == 8

int32x4_t vshll_high_n_s16
(int16x8_t a, a → Vn.8H SHLL2 Vd.4S,Vn.8H,#n Vd.4S ARMv8(AArch64)
const int n) n == 16

int64x2_t vshll_high_n_s32
(int32x4_t a, a → Vn.4S SHLL2 Vd.2D,Vn.4S,#n Vd.2D ARMv8(AArch64)
const int n) n == 32

uint16x8_t vshll_high_n_u8
(uint8x16_t a, a → Vn.16B SHLL2 Vd.8H,Vn.16B,#n Vd.8H ARMv8(AArch64)
const int n) n == 8

uint32x4_t vshll_high_n_u16
(uint16x8_t a, a → Vn.8H SHLL2 Vd.4S,Vn.8H,#n Vd.4S ARMv8(AArch64)
const int n) n == 16

uint64x2_t vshll_high_n_u32
(uint32x4_t a, a → Vn.4S SHLL2 Vd.2D,Vn.4S,#n Vd.2D ARMv8(AArch64)
const int n) n == 32

int8x8_t vsri_n_s8
(int8x8_t a, a → Vd.8B
SRI Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
int8x8_t b, b → Vn.8B
const int n) 1 <= n <= 8

int8x16_t vsriq_n_s8
(int8x16_t a, a → Vd.16B
SRI Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
int8x16_t b, b → Vn.16B
const int n) 1 <= n <= 8

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Non-Confidential
int16x4_t vsri_n_s16
(int16x4_t a, a → Vd.4H
SRI Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
int16x4_t b, b → Vn.4H
const int n) 1 <= n <= 16

int16x8_t vsriq_n_s16
(int16x8_t a, a → Vd.8H
SRI Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
int16x8_t b, b → Vn.8H
const int n) 1 <= n <= 16

int32x2_t vsri_n_s32
(int32x2_t a, a → Vd.2S
SRI Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
int32x2_t b, b → Vn.2S
const int n) 1 <= n <= 32

int32x4_t vsriq_n_s32
(int32x4_t a, a → Vd.4S
SRI Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
int32x4_t b, b → Vn.4S
const int n) 1 <= n <= 32

int64x1_t vsri_n_s64
(int64x1_t a, a → Dd
SRI Dd,Dn,#n Dd ARMv7, ARMv8
int64x1_t b, b → Dn
const int n) 1 <= n <= 64

int64x2_t vsriq_n_s64
(int64x2_t a, a → Vd.2D
SRI Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
int64x2_t b, b → Vn.2D
const int n) 1 <= n <= 64

uint8x8_t vsri_n_u8
(uint8x8_t a, a → Vd.8B
SRI Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
uint8x8_t b, b → Vn.8B
const int n) 1 <= n <= 8

uint8x16_t vsriq_n_u8
(uint8x16_t a, a → Vd.16B
SRI Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
uint8x16_t b, b → Vn.16B
const int n) 1 <= n <= 8

uint16x4_t vsri_n_u16
(uint16x4_t a, a → Vd.4H
SRI Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
uint16x4_t b, b → Vn.4H
const int n) 1 <= n <= 16

uint16x8_t vsriq_n_u16
(uint16x8_t a, a → Vd.8H
SRI Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
uint16x8_t b, b → Vn.8H
const int n) 1 <= n <= 16

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uint32x2_t vsri_n_u32
(uint32x2_t a, a → Vd.2S
SRI Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
uint32x2_t b, b → Vn.2S
const int n) 1 <= n <= 32

uint32x4_t vsriq_n_u32
(uint32x4_t a, a → Vd.4S
SRI Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
uint32x4_t b, b → Vn.4S
const int n) 1 <= n <= 32

uint64x1_t vsri_n_u64
(uint64x1_t a, a → Dd
SRI Dd,Dn,#n Dd ARMv7, ARMv8
uint64x1_t b, b → Dn
const int n) 1 <= n <= 64

uint64x2_t vsriq_n_u64
(uint64x2_t a, a → Vd.2D
SRI Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
uint64x2_t b, b → Vn.2D
const int n) 1 <= n <= 64

poly64x1_t vsri_n_p64
(poly64x1_t a, a → Dd
SRI Dd,Dn,#n Dd ARMv8
poly64x1_t b, b → Dn
const int n) 1 <= n <= 64

poly64x2_t vsriq_n_p64
(poly64x2_t a, a → Vd.2D
SRI Vd.2D,Vn.2D,#n Vd.2D ARMv8
poly64x2_t b, b → Vn.2D
const int n) 1 <= n <= 64

poly8x8_t vsri_n_p8
(poly8x8_t a, a → Vd.8B
SRI Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
poly8x8_t b, b → Vn.8B
const int n) 1 <= n <= 8

poly8x16_t vsriq_n_p8
(poly8x16_t a, a → Vd.16B
SRI Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
poly8x16_t b, b → Vn.16B
const int n) 1 <= n <= 8

poly16x4_t vsri_n_p16
(poly16x4_t a, a → Vd.4H
SRI Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
poly16x4_t b, b → Vn.4H
const int n) 1 <= n <= 16

poly16x8_t vsriq_n_p16
(poly16x8_t a, a → Vd.8H
SRI Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
poly16x8_t b, b → Vn.8H
const int n) 1 <= n <= 16

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 101 of 348
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int64_t vsrid_n_s64
(int64_t a, a → Dd
SRI Dd,Dn,#n Dd ARMv8(AArch64)
int64_t b, b → Dn
const int n) 1 <= n <= 64

uint64_t vsrid_n_u64
(uint64_t a, a → Dd
SRI Dd,Dn,#n Dd ARMv8(AArch64)
uint64_t b, b → Dn
const int n) 1 <= n <= 64

int8x8_t vsli_n_s8
(int8x8_t a, a → Vd.8B
SLI Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
int8x8_t b, b → Vn.8B
const int n) 0 <= n <= 7

int8x16_t vsliq_n_s8
(int8x16_t a, a → Vd.16B
SLI Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
int8x16_t b, b → Vn.16B
const int n) 0 <= n <= 7

int16x4_t vsli_n_s16
(int16x4_t a, a → Vd.4H
SLI Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
int16x4_t b, b → Vn.4H
const int n) 0 <= n <= 15

int16x8_t vsliq_n_s16
(int16x8_t a, a → Vd.8H
SLI Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
int16x8_t b, b → Vn.8H
const int n) 0 <= n <= 15

int32x2_t vsli_n_s32
(int32x2_t a, a → Vd.2S
SLI Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
int32x2_t b, b → Vn.2S
const int n) 0 <= n <= 31

int32x4_t vsliq_n_s32
(int32x4_t a, a → Vd.4S
SLI Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
int32x4_t b, b → Vn.4S
const int n) 0 <= n <= 31

int64x1_t vsli_n_s64
(int64x1_t a, a → Dd
SLI Dd,Dn,#n Dd ARMv7, ARMv8
int64x1_t b, b → Dn
const int n) 0 <= n <= 63

int64x2_t vsliq_n_s64
(int64x2_t a, a → Vd.2D
SLI Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
int64x2_t b, b → Vn.2D
const int n) 0 <= n <= 63

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uint8x8_t vsli_n_u8
(uint8x8_t a, a → Vd.8B
SLI Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
uint8x8_t b, b → Vn.8B
const int n) 0 <= n <= 7

uint8x16_t vsliq_n_u8
(uint8x16_t a, a → Vd.16B
SLI Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
uint8x16_t b, b → Vn.16B
const int n) 0 <= n <= 7

uint16x4_t vsli_n_u16
(uint16x4_t a, a → Vd.4H
SLI Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
uint16x4_t b, b → Vn.4H
const int n) 0 <= n <= 15

uint16x8_t vsliq_n_u16
(uint16x8_t a, a → Vd.8H
SLI Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
uint16x8_t b, b → Vn.8H
const int n) 0 <= n <= 15

uint32x2_t vsli_n_u32
(uint32x2_t a, a → Vd.2S
SLI Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
uint32x2_t b, b → Vn.2S
const int n) 0 <= n <= 31

uint32x4_t vsliq_n_u32
(uint32x4_t a, a → Vd.4S
SLI Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
uint32x4_t b, b → Vn.4S
const int n) 0 <= n <= 31

uint64x1_t vsli_n_u64
(uint64x1_t a, a → Dd
SLI Dd,Dn,#n Dd ARMv7, ARMv8
uint64x1_t b, b → Dn
const int n) 0 <= n <= 63

uint64x2_t vsliq_n_u64
(uint64x2_t a, a → Vd.2D
SLI Vd.2D,Vn.2D,#n Vd.2D ARMv7, ARMv8
uint64x2_t b, b → Vn.2D
const int n) 0 <= n <= 63

poly64x1_t vsli_n_p64
(poly64x1_t a, a → Dd
SLI Dd,Dn,#n Dd ARMv8
poly64x1_t b, b → Dn
const int n) 0 <= n <= 63

poly64x2_t vsliq_n_p64
(poly64x2_t a, a → Vd.2D
SLI Vd.2D,Vn.2D,#n Vd.2D ARMv8
poly64x2_t b, b → Vn.2D
const int n) 0 <= n <= 63

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 103 of 348
Non-Confidential
poly8x8_t vsli_n_p8
(poly8x8_t a, a → Vd.8B
SLI Vd.8B,Vn.8B,#n Vd.8B ARMv7, ARMv8
poly8x8_t b, b → Vn.8B
const int n) 0 <= n <= 7

poly8x16_t vsliq_n_p8
(poly8x16_t a, a → Vd.16B
SLI Vd.16B,Vn.16B,#n Vd.16B ARMv7, ARMv8
poly8x16_t b, b → Vn.16B
const int n) 0 <= n <= 7

poly16x4_t vsli_n_p16
(poly16x4_t a, a → Vd.4H
SLI Vd.4H,Vn.4H,#n Vd.4H ARMv7, ARMv8
poly16x4_t b, b → Vn.4H
const int n) 0 <= n <= 15

poly16x8_t vsliq_n_p16
(poly16x8_t a, a → Vd.8H
SLI Vd.8H,Vn.8H,#n Vd.8H ARMv7, ARMv8
poly16x8_t b, b → Vn.8H
const int n) 0 <= n <= 15

int64_t vslid_n_s64
(int64_t a, a → Dd
SLI Dd,Dn,#n Dd ARMv8(AArch64)
int64_t b, b → Dn
const int n) 0 <= n <= 63

uint64_t vslid_n_u64
(uint64_t a, a → Dd
SLI Dd,Dn,#n Dd ARMv8(AArch64)
uint64_t b, b → Dn
const int n) 0 <= n <= 63

int32x2_t vcvt_s32_f32
FCVTZS Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(float32x2_t a) a → Vn.2S

int32x4_t vcvtq_s32_f32
FCVTZS Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(float32x4_t a) a → Vn.4S

uint32x2_t vcvt_u32_f32
FCVTZU Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(float32x2_t a) a → Vn.2S

uint32x4_t vcvtq_u32_f32
FCVTZU Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(float32x4_t a) a → Vn.4S

int32x2_t vcvtn_s32_f32
FCVTNS Vd.2S,Vn.2S Vd.2S ARMv8
(float32x2_t a) a → Vn.2S

int32x4_t vcvtnq_s32_f32
FCVTNS Vd.4S,Vn.4S Vd.4S ARMv8
(float32x4_t a) a → Vn.4S

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 104 of 348
Non-Confidential
uint32x2_t vcvtn_u32_f32
FCVTNU Vd.2S,Vn.2S Vd.2S ARMv8
(float32x2_t a) a → Vn.2S

uint32x4_t vcvtnq_u32_f32
FCVTNU Vd.4S,Vn.4S Vd.4S ARMv8
(float32x4_t a) a → Vn.4S

int32x2_t vcvtm_s32_f32
FCVTMS Vd.2S,Vn.2S Vd.2S ARMv8
(float32x2_t a) a → Vn.2S

int32x4_t vcvtmq_s32_f32
FCVTMS Vd.4S,Vn.4S Vd.4S ARMv8
(float32x4_t a) a → Vn.4S

uint32x2_t vcvtm_u32_f32
FCVTMU Vd.2S,Vn.2S Vd.2S ARMv8
(float32x2_t a) a → Vn.2S

uint32x4_t vcvtmq_u32_f32
FCVTMU Vd.4S,Vn.4S Vd.4S ARMv8
(float32x4_t a) a → Vn.4S

int32x2_t vcvtp_s32_f32
FCVTPS Vd.2S,Vn.2S Vd.2S ARMv8
(float32x2_t a) a → Vn.2S

int32x4_t vcvtpq_s32_f32
FCVTPS Vd.4S,Vn.4S Vd.4S ARMv8
(float32x4_t a) a → Vn.4S

uint32x2_t vcvtp_u32_f32
FCVTPU Vd.2S,Vn.2S Vd.2S ARMv8
(float32x2_t a) a → Vn.2S

uint32x4_t vcvtpq_u32_f32
FCVTPU Vd.4S,Vn.4S Vd.4S ARMv8
(float32x4_t a) a → Vn.4S

int32x2_t vcvta_s32_f32
FCVTAS Vd.2S,Vn.2S Vd.2S ARMv8
(float32x2_t a) a → Vn.2S

int32x4_t vcvtaq_s32_f32
FCVTAS Vd.4S,Vn.4S Vd.4S ARMv8
(float32x4_t a) a → Vn.4S

uint32x2_t vcvta_u32_f32
FCVTAU Vd.2S,Vn.2S Vd.2S ARMv8
(float32x2_t a) a → Vn.2S

uint32x4_t vcvtaq_u32_f32
FCVTAU Vd.4S,Vn.4S Vd.4S ARMv8
(float32x4_t a) a → Vn.4S

int32_t vcvts_s32_f32
FCVTZS Sd,Sn Sd ARMv8(AArch64)
(float32_t a) a → Sn

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uint32_t vcvts_u32_f32
FCVTZU Sd,Sn Sd ARMv8(AArch64)
(float32_t a) a → Sn

int32_t vcvtns_s32_f32
FCVTNS Sd,Sn Sd ARMv8(AArch64)
(float32_t a) a → Sn

uint32_t vcvtns_u32_f32
FCVTNU Sd,Sn Sd ARMv8(AArch64)
(float32_t a) a → Sn

int32_t vcvtms_s32_f32
FCVTMS Sd,Sn Sd ARMv8(AArch64)
(float32_t a) a → Sn

uint32_t vcvtms_u32_f32
FCVTMU Sd,Sn Sd ARMv8(AArch64)
(float32_t a) a → Sn

int32_t vcvtps_s32_f32
FCVTPS Sd,Sn Sd ARMv8(AArch64)
(float32_t a) a → Sn

uint32_t vcvtps_u32_f32
FCVTPU Sd,Sn Sd ARMv8(AArch64)
(float32_t a) a → Sn

int32_t vcvtas_s32_f32
FCVTAS Sd,Sn Sd ARMv8(AArch64)
(float32_t a) a → Sn

uint32_t vcvtas_u32_f32
FCVTAU Sd,Sn Sd ARMv8(AArch64)
(float32_t a) a → Sn

int64x1_t vcvt_s64_f64
FCVTZS Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

int64x2_t vcvtq_s64_f64
FCVTZS Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

uint64x1_t vcvt_u64_f64
FCVTZU Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

uint64x2_t vcvtq_u64_f64
FCVTZU Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

int64x1_t vcvtn_s64_f64
FCVTNS Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

int64x2_t vcvtnq_s64_f64
FCVTNS Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

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uint64x1_t vcvtn_u64_f64
FCVTNU Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

uint64x2_t vcvtnq_u64_f64
FCVTNU Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

int64x1_t vcvtm_s64_f64
FCVTMS Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

int64x2_t vcvtmq_s64_f64
FCVTMS Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

uint64x1_t vcvtm_u64_f64
FCVTMU Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

uint64x2_t vcvtmq_u64_f64
FCVTMU Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

int64x1_t vcvtp_s64_f64
FCVTPS Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

int64x2_t vcvtpq_s64_f64
FCVTPS Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

uint64x1_t vcvtp_u64_f64
FCVTPU Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

uint64x2_t vcvtpq_u64_f64
FCVTPU Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

int64x1_t vcvta_s64_f64
FCVTAS Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

int64x2_t vcvtaq_s64_f64
FCVTAS Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

uint64x1_t vcvta_u64_f64
FCVTAU Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

uint64x2_t vcvtaq_u64_f64
FCVTAU Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

int64_t vcvtd_s64_f64
FCVTZS Dd,Dn Dd ARMv8(AArch64)
(float64_t a) a → Dn

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uint64_t vcvtd_u64_f64
FCVTZU Dd,Dn Dd ARMv8(AArch64)
(float64_t a) a → Dn

int64_t vcvtnd_s64_f64
FCVTNS Dd,Dn Dd ARMv8(AArch64)
(float64_t a) a → Dn

uint64_t vcvtnd_u64_f64
FCVTNU Dd,Dn Dd ARMv8(AArch64)
(float64_t a) a → Dn

int64_t vcvtmd_s64_f64
FCVTMS Dd,Dn Dd ARMv8(AArch64)
(float64_t a) a → Dn

uint64_t vcvtmd_u64_f64
FCVTMU Dd,Dn Dd ARMv8(AArch64)
(float64_t a) a → Dn

int64_t vcvtpd_s64_f64
FCVTPS Dd,Dn Dd ARMv8(AArch64)
(float64_t a) a → Dn

uint64_t vcvtpd_u64_f64
FCVTPU Dd,Dn Dd ARMv8(AArch64)
(float64_t a) a → Dn

int64_t vcvtad_s64_f64
FCVTAS Dd,Dn Dd ARMv8(AArch64)
(float64_t a) a → Dn

uint64_t vcvtad_u64_f64
FCVTAU Dd,Dn Dd ARMv8(AArch64)
(float64_t a) a → Dn

int32x2_t vcvt_n_s32_f32
(float32x2_t a, a → Vn.2S FCVTZS Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

int32x4_t vcvtq_n_s32_f32
(float32x4_t a, a → Vn.4S FCVTZS Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
const int n) 1 <= n <= 32

uint32x2_t vcvt_n_u32_f32
(float32x2_t a, a → Vn.2S FCVTZU Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

uint32x4_t vcvtq_n_u32_f32
(float32x4_t a, a → Vn.4S FCVTZU Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
const int n) 1 <= n <= 32

int32_t vcvts_n_s32_f32
(float32_t a, a → Sn FCVTZS Sd,Sn,#n Sd ARMv8(AArch64)
const int n) 1 <= n <= 32

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uint32_t vcvts_n_u32_f32
(float32_t a, a → Sn FCVTZU Sd,Sn,#n Sd ARMv8(AArch64)
const int n) 1 <= n <= 32

int64x1_t vcvt_n_s64_f64
(float64x1_t a, a → Dn FCVTZS Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 1 <= n <= 64

int64x2_t vcvtq_n_s64_f64
(float64x2_t a, a → Vn.2D FCVTZS Vd.2D,Vn.2D,#n Vd.2D ARMv8(AArch64)
const int n) 1 <= n <= 64

uint64x1_t vcvt_n_u64_f64
(float64x1_t a, a → Dn FCVTZU Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 1 <= n <= 64

uint64x2_t vcvtq_n_u64_f64
(float64x2_t a, a → Vn.2D FCVTZU Vd.2D,Vn.2D,#n Vd.2D ARMv8(AArch64)
const int n) 1 <= n <= 64

int64_t vcvtd_n_s64_f64
(float64_t a, a → Dn FCVTZS Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 1 <= n <= 64

uint64_t vcvtd_n_u64_f64
(float64_t a, a → Dn FCVTZU Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 1 <= n <= 64

float32x2_t vcvt_f32_s32
SCVTF Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(int32x2_t a) a → Vn.2S

float32x4_t vcvtq_f32_s32
SCVTF Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(int32x4_t a) a → Vn.4S

float32x2_t vcvt_f32_u32
UCVTF Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(uint32x2_t a) a → Vn.2S

float32x4_t vcvtq_f32_u32
UCVTF Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(uint32x4_t a) a → Vn.4S

float32_t vcvts_f32_s32
SCVTF Sd,Sn Sd ARMv8(AArch64)
(int32_t a) a → Sn

float32_t vcvts_f32_u32
UCVTF Sd,Sn Sd ARMv8(AArch64)
(uint32_t a) a → Sn

float64x1_t vcvt_f64_s64
SCVTF Dd,Dn Dd ARMv8(AArch64)
(int64x1_t a) a → Dn

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float64x2_t vcvtq_f64_s64
SCVTF Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(int64x2_t a) a → Vn.2D

float64x1_t vcvt_f64_u64
UCVTF Dd,Dn Dd ARMv8(AArch64)
(uint64x1_t a) a → Dn

float64x2_t vcvtq_f64_u64
UCVTF Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(uint64x2_t a) a → Vn.2D

float64_t vcvtd_f64_s64
SCVTF Dd,Dn Dd ARMv8(AArch64)
(int64_t a) a → Dn

float64_t vcvtd_f64_u64
UCVTF Dd,Dn Dd ARMv8(AArch64)
(uint64_t a) a → Dn

float32x2_t vcvt_n_f32_s32
(int32x2_t a, a → Vn.2S SCVTF Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

float32x4_t vcvtq_n_f32_s32
(int32x4_t a, a → Vn.4S SCVTF Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
const int n) 1 <= n <= 32

float32x2_t vcvt_n_f32_u32
(uint32x2_t a, a → Vn.2S UCVTF Vd.2S,Vn.2S,#n Vd.2S ARMv7, ARMv8
const int n) 1 <= n <= 32

float32x4_t vcvtq_n_f32_u32
(uint32x4_t a, a → Vn.4S UCVTF Vd.4S,Vn.4S,#n Vd.4S ARMv7, ARMv8
const int n) 1 <= n <= 32

float32_t vcvts_n_f32_s32
(int32_t a, a → Sn SCVTF Sd,Sn,#n Sd ARMv8(AArch64)
const int n) 1 <= n <= 32

float32_t vcvts_n_f32_u32
(uint32_t a, a → Sn UCVTF Sd,Sn,#n Sd ARMv8(AArch64)
const int n) 1 <= n <= 32

float64x1_t vcvt_n_f64_s64
(int64x1_t a, a → Dn SCVTF Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 1 <= n <= 64

float64x2_t vcvtq_n_f64_s64
(int64x2_t a, a → Vn.2D SCVTF Vd.2D,Vn.2D,#n Vd.2D ARMv8(AArch64)
const int n) 1 <= n <= 64

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float64x1_t vcvt_n_f64_u64
(uint64x1_t a, a → Dn UCVTF Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 1 <= n <= 64

float64x2_t vcvtq_n_f64_u64
(uint64x2_t a, a → Vn.2D UCVTF Vd.2D,Vn.2D,#n Vd.2D ARMv8(AArch64)
const int n) 1 <= n <= 64

float64_t vcvtd_n_f64_s64
(int64_t a, a → Dn SCVTF Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 1 <= n <= 64

float64_t vcvtd_n_f64_u64
(uint64_t a, a → Dn UCVTF Dd,Dn,#n Dd ARMv8(AArch64)
const int n) 1 <= n <= 64

float16x4_t vcvt_f16_f32
FCVTN Vd.4H,Vn.4S Vd.4H ARMv7, ARMv8
(float32x4_t a) a → Vn.4S

float16x8_t vcvt_high_f16_f32
(float16x4_t r, r → Vd.4H FCVTN2 Vd.8H,Vn.4S Vd.8H ARMv8(AArch64)
float32x4_t a) a → Vn.4S

float32x2_t vcvt_f32_f64
FCVTN Vd.2S,Vn.2D Vd.2S ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

float32x4_t vcvt_high_f32_f64
(float32x2_t r, r → Vd.2S FCVTN2 Vd.4S,Vn.2D Vd.4S ARMv8(AArch64)
float64x2_t a) a → Vn.2D

float32x4_t vcvt_f32_f16
FCVTL Vd.4S,Vn.4H Vd.4S ARMv7, ARMv8
(float16x4_t a) a → Vn.4H

float32x4_t vcvt_high_f32_f16
FCVTL2 Vd.4S,Vn.8H Vd.4S ARMv8(AArch64)
(float16x8_t a) a → Vn.8H

float64x2_t vcvt_f64_f32
FCVTL Vd.2D,Vn.2S Vd.2D ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

float64x2_t vcvt_high_f64_f32
FCVTL2 Vd.2D,Vn.4S Vd.2D ARMv8(AArch64)
(float32x4_t a) a → Vn.4S

float32x2_t vcvtx_f32_f64
FCVTXN Vd.2S,Vn.2D Vd.2S ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

float32_t vcvtxd_f32_f64
FCVTXN Sd,Dn Sd ARMv8(AArch64)
(float64_t a) a → Dn

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float32x4_t vcvtx_high_f32_f64
(float32x2_t r, r → Vd.2S FCVTXN2 Vd.4S,Vn.2D Vd.4S ARMv8(AArch64)
float64x2_t a) a → Vn.2D

float32x2_t vrnd_f32
FRINTZ Vd.2S,Vn.2S Vd.2S ARMv8
(float32x2_t a) a → Vn.2S

float32x4_t vrndq_f32
FRINTZ Vd.4S,Vn.4S Vd.4S ARMv8
(float32x4_t a) a → Vn.4S

float64x1_t vrnd_f64
FRINTZ Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

float64x2_t vrndq_f64
FRINTZ Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

float32x2_t vrndn_f32
FRINTN Vd.2S,Vn.2S Vd.2S ARMv8
(float32x2_t a) a → Vn.2S

float32x4_t vrndnq_f32
FRINTN Vd.4S,Vn.4S Vd.4S ARMv8
(float32x4_t a) a → Vn.4S

float64x1_t vrndn_f64
FRINTN Dd,Dn Dd ARMv8
(float64x1_t a) a → Dn

float64x2_t vrndnq_f64
FRINTN Vd.2D,Vn.2D Vd.2D ARMv8
(float64x2_t a) a → Vn.2D

float32_t vrndns_f32
FRINTN Sd,Sn Sd ARMv8
(float32_t a) a → Sn

float32x2_t vrndm_f32
FRINTM Vd.2S,Vn.2S Vd.2S ARMv8
(float32x2_t a) a → Vn.2S

float32x4_t vrndmq_f32
FRINTM Vd.4S,Vn.4S Vd.4S ARMv8
(float32x4_t a) a → Vn.4S

float64x1_t vrndm_f64
FRINTM Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

float64x2_t vrndmq_f64
FRINTM Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

float32x2_t vrndp_f32
FRINTP Vd.2S,Vn.2S Vd.2S ARMv8
(float32x2_t a) a → Vn.2S

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float32x4_t vrndpq_f32
FRINTP Vd.4S,Vn.4S Vd.4S ARMv8
(float32x4_t a) a → Vn.4S

float64x1_t vrndp_f64
FRINTP Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

float64x2_t vrndpq_f64
FRINTP Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

float32x2_t vrnda_f32
FRINTA Vd.2S,Vn.2S Vd.2S ARMv8
(float32x2_t a) a → Vn.2S

float32x4_t vrndaq_f32
FRINTA Vd.4S,Vn.4S Vd.4S ARMv8
(float32x4_t a) a → Vn.4S

float64x1_t vrnda_f64
FRINTA Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

float64x2_t vrndaq_f64
FRINTA Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

float32x2_t vrndi_f32
FRINTI Vd.2S,Vn.2S Vd.2S ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

float32x4_t vrndiq_f32
FRINTI Vd.4S,Vn.4S Vd.4S ARMv8(AArch64)
(float32x4_t a) a → Vn.4S

float64x1_t vrndi_f64
FRINTI Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

float64x2_t vrndiq_f64
FRINTI Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

float32x2_t vrndx_f32
FRINTX Vd.2S,Vn.2S Vd.2S ARMv8
(float32x2_t a) a → Vn.2S

float32x4_t vrndxq_f32
FRINTX Vd.4S,Vn.4S Vd.4S ARMv8
(float32x4_t a) a → Vn.4S

float64x1_t vrndx_f64
FRINTX Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

float64x2_t vrndxq_f64
FRINTX Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

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int8x8_t vmovn_s16
XTN Vd.8B,Vn.8H Vd.8B ARMv7, ARMv8
(int16x8_t a) a → Vn.8H

int16x4_t vmovn_s32
XTN Vd.4H,Vn.4S Vd.4H ARMv7, ARMv8
(int32x4_t a) a → Vn.4S

int32x2_t vmovn_s64
XTN Vd.2S,Vn.2D Vd.2S ARMv7, ARMv8
(int64x2_t a) a → Vn.2D

uint8x8_t vmovn_u16
XTN Vd.8B,Vn.8H Vd.8B ARMv7, ARMv8
(uint16x8_t a) a → Vn.8H

uint16x4_t vmovn_u32
XTN Vd.4H,Vn.4S Vd.4H ARMv7, ARMv8
(uint32x4_t a) a → Vn.4S

uint32x2_t vmovn_u64
XTN Vd.2S,Vn.2D Vd.2S ARMv7, ARMv8
(uint64x2_t a) a → Vn.2D

int8x16_t vmovn_high_s16
(int8x8_t r, r → Vd.8B XTN2 Vd.16B,Vn.8H Vd.16B ARMv8(AArch64)
int16x8_t a) a → Vn.8H

int16x8_t vmovn_high_s32
(int16x4_t r, r → Vd.4H XTN2 Vd.8H,Vn.4S Vd.8H ARMv8(AArch64)
int32x4_t a) a → Vn.4S

int32x4_t vmovn_high_s64
(int32x2_t r, r → Vd.2S XTN2 Vd.4S,Vn.2D Vd.4S ARMv8(AArch64)
int64x2_t a) a → Vn.2D

uint8x16_t vmovn_high_u16
(uint8x8_t r, r → Vd.8B XTN2 Vd.16B,Vn.8H Vd.16B ARMv8(AArch64)
uint16x8_t a) a → Vn.8H

uint16x8_t vmovn_high_u32
(uint16x4_t r, r → Vd.4H XTN2 Vd.8H,Vn.4S Vd.8H ARMv8(AArch64)
uint32x4_t a) a → Vn.4S

uint32x4_t vmovn_high_u64
(uint32x2_t r, r → Vd.2S XTN2 Vd.4S,Vn.2D Vd.4S ARMv8(AArch64)
uint64x2_t a) a → Vn.2D

int16x8_t vmovl_s8
SSHLL Vd.8H,Vn.8B,#0 Vd.8H ARMv7, ARMv8
(int8x8_t a) a → Vn.8B

int32x4_t vmovl_s16
SSHLL Vd.4S,Vn.4H,#0 Vd.4S ARMv7, ARMv8
(int16x4_t a) a → Vn.4H

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int64x2_t vmovl_s32
SSHLL Vd.2D,Vn.2S,#0 Vd.2D ARMv7, ARMv8
(int32x2_t a) a → Vn.2S

uint16x8_t vmovl_u8
USHLL Vd.8H,Vn.8B,#0 Vd.8H ARMv7, ARMv8
(uint8x8_t a) a → Vn.8B

uint32x4_t vmovl_u16
USHLL Vd.4S,Vn.4H,#0 Vd.4S ARMv7, ARMv8
(uint16x4_t a) a → Vn.4H

uint64x2_t vmovl_u32
USHLL Vd.2D,Vn.2S,#0 Vd.2D ARMv7, ARMv8
(uint32x2_t a) a → Vn.2S

int16x8_t vmovl_high_s8
SSHLL2 Vd.8H,Vn.16B,#0 Vd.8H ARMv8(AArch64)
(int8x16_t a) a → Vn.16B

int32x4_t vmovl_high_s16
SSHLL2 Vd.4S,Vn.8H,#0 Vd.4S ARMv8(AArch64)
(int16x8_t a) a → Vn.8H

int64x2_t vmovl_high_s32
SSHLL2 Vd.2D,Vn.4S,#0 Vd.2D ARMv8(AArch64)
(int32x4_t a) a → Vn.4S

uint16x8_t vmovl_high_u8
USHLL2 Vd.8H,Vn.16B,#0 Vd.8H ARMv8(AArch64)
(uint8x16_t a) a → Vn.16B

uint32x4_t vmovl_high_u16
USHLL2 Vd.4S,Vn.8H,#0 Vd.4S ARMv8(AArch64)
(uint16x8_t a) a → Vn.8H

uint64x2_t vmovl_high_u32
USHLL2 Vd.2D,Vn.4S,#0 Vd.2D ARMv8(AArch64)
(uint32x4_t a) a → Vn.4S

int8x8_t vqmovn_s16
SQXTN Vd.8B,Vn.8H Vd.8B ARMv7, ARMv8
(int16x8_t a) a → Vn.8H

int16x4_t vqmovn_s32
SQXTN Vd.4H,Vn.4S Vd.4H ARMv7, ARMv8
(int32x4_t a) a → Vn.4S

int32x2_t vqmovn_s64
SQXTN Vd.2S,Vn.2D Vd.2S ARMv7, ARMv8
(int64x2_t a) a → Vn.2D

uint8x8_t vqmovn_u16
UQXTN Vd.8B,Vn.8H Vd.8B ARMv7, ARMv8
(uint16x8_t a) a → Vn.8H

uint16x4_t vqmovn_u32
UQXTN Vd.4H,Vn.4S Vd.4H ARMv7, ARMv8
(uint32x4_t a) a → Vn.4S

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uint32x2_t vqmovn_u64
UQXTN Vd.2S,Vn.2D Vd.2S ARMv7, ARMv8
(uint64x2_t a) a → Vn.2D

int8_t vqmovnh_s16
SQXTN Bd,Hn Bd ARMv8(AArch64)
(int16_t a) a → Hn

int16_t vqmovns_s32
SQXTN Hd,Sn Hd ARMv8(AArch64)
(int32_t a) a → Sn

int32_t vqmovnd_s64
SQXTN Sd,Dn Sd ARMv8(AArch64)
(int64_t a) a → Dn

uint8_t vqmovnh_u16
UQXTN Bd,Hn Bd ARMv8(AArch64)
(uint16_t a) a → Hn

uint16_t vqmovns_u32
UQXTN Hd,Sn Hd ARMv8(AArch64)
(uint32_t a) a → Sn

uint32_t vqmovnd_u64
UQXTN Sd,Dn Sd ARMv8(AArch64)
(uint64_t a) a → Dn

int8x16_t vqmovn_high_s16
(int8x8_t r, r → Vd.8B SQXTN2 Vd.16B,Vn.8H Vd.16B ARMv8(AArch64)
int16x8_t a) a → Vn.8H

int16x8_t vqmovn_high_s32
(int16x4_t r, r → Vd.4H SQXTN2 Vd.8H,Vn.4S Vd.8H ARMv8(AArch64)
int32x4_t a) a → Vn.4S

int32x4_t vqmovn_high_s64
(int32x2_t r, r → Vd.2S SQXTN2 Vd.4S,Vn.2D Vd.4S ARMv8(AArch64)
int64x2_t a) a → Vn.2D

uint8x16_t vqmovn_high_u16
(uint8x8_t r, r → Vd.8B UQXTN2 Vd.16B,Vn.8H Vd.16B ARMv8(AArch64)
uint16x8_t a) a → Vn.8H

uint16x8_t vqmovn_high_u32
(uint16x4_t r, r → Vd.4H UQXTN2 Vd.8H,Vn.4S Vd.8H ARMv8(AArch64)
uint32x4_t a) a → Vn.4S

uint32x4_t vqmovn_high_u64
(uint32x2_t r, r → Vd.2S UQXTN2 Vd.4S,Vn.2D Vd.4S ARMv8(AArch64)
uint64x2_t a) a → Vn.2D

uint8x8_t vqmovun_s16
SQXTUN Vd.8B,Vn.8H Vd.8B ARMv7, ARMv8
(int16x8_t a) a → Vn.8H

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Non-Confidential
uint16x4_t vqmovun_s32
SQXTUN Vd.4H,Vn.4S Vd.4H ARMv7, ARMv8
(int32x4_t a) a → Vn.4S

uint32x2_t vqmovun_s64
SQXTUN Vd.2S,Vn.2D Vd.2S ARMv7, ARMv8
(int64x2_t a) a → Vn.2D

uint8_t vqmovunh_s16
SQXTUN Bd,Hn Bd ARMv8(AArch64)
(int16_t a) a → Hn

uint16_t vqmovuns_s32
SQXTUN Hd,Sn Hd ARMv8(AArch64)
(int32_t a) a → Sn

uint32_t vqmovund_s64
SQXTUN Sd,Dn Sd ARMv8(AArch64)
(int64_t a) a → Dn

uint8x16_t vqmovun_high_s16
(uint8x8_t r, r → Vd.8B SQXTUN2 Vd.16B,Vn.8H Vd.16B ARMv8(AArch64)
int16x8_t a) a → Vn.8H

uint16x8_t vqmovun_high_s32
(uint16x4_t r, r → Vd.4H SQXTUN2 Vd.8H,Vn.4S Vd.8H ARMv8(AArch64)
int32x4_t a) a → Vn.4S

uint32x4_t vqmovun_high_s64
(uint32x2_t r, r → Vd.2S SQXTUN2 Vd.4S,Vn.2D Vd.4S ARMv8(AArch64)
int64x2_t a) a → Vn.2D

int16x4_t vmla_lane_s16
(int16x4_t a, a → Vd.4H
int16x4_t b, b → Vn.4H MLA Vd.4H,Vn.4H,Vm.H[lane] Vd.4H ARMv7, ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int16x8_t vmlaq_lane_s16
(int16x8_t a, a → Vd.8H
int16x8_t b, b → Vn.8H MLA Vd.8H,Vn.8H,Vm.H[lane] Vd.8H ARMv7, ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int32x2_t vmla_lane_s32
(int32x2_t a, a → Vd.2S
int32x2_t b, b → Vn.2S MLA Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv7, ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32x4_t vmlaq_lane_s32
(int32x4_t a, a → Vd.4S
int32x4_t b, b → Vn.4S MLA Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv7, ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

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uint16x4_t vmla_lane_u16
(uint16x4_t a, a → Vd.4H
uint16x4_t b, b → Vn.4H MLA Vd.4H,Vn.4H,Vm.H[lane] Vd.4H ARMv7, ARMv8
uint16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

uint16x8_t vmlaq_lane_u16
(uint16x8_t a, a → Vd.8H
uint16x8_t b, b → Vn.8H MLA Vd.8H,Vn.8H,Vm.H[lane] Vd.8H ARMv7, ARMv8
uint16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

uint32x2_t vmla_lane_u32
(uint32x2_t a, a → Vd.2S
uint32x2_t b, b → Vn.2S MLA Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv7, ARMv8
uint32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

uint32x4_t vmlaq_lane_u32
(uint32x4_t a, a → Vd.4S
uint32x4_t b, b → Vn.4S MLA Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv7, ARMv8
uint32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

float32x2_t vmla_lane_f32
(float32x2_t a,
RESULT[I] = a[i] + (b[i] * v[lane]) for i
float32x2_t b, N/A ARMv7, ARMv8
= 0 to 1
float32x2_t v,
const int lane) 0 <= lane <= 1

float32x4_t vmlaq_lane_f32
(float32x4_t a,
RESULT[I] = a[i] + (b[i] * v[lane]) for i
float32x4_t b, N/A ARMv7, ARMv8
= 0 to 3
float32x2_t v,
const int lane) 0 <= lane <= 1

int16x4_t vmla_laneq_s16
(int16x4_t a, a → Vd.4H
int16x4_t b, b → Vn.4H MLA Vd.4H,Vn.4H,Vm.H[lane] Vd.4H ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int16x8_t vmlaq_laneq_s16
(int16x8_t a, a → Vd.8H
int16x8_t b, b → Vn.8H MLA Vd.8H,Vn.8H,Vm.H[lane] Vd.8H ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int32x2_t vmla_laneq_s32
(int32x2_t a, a → Vd.2S
int32x2_t b, b → Vn.2S MLA Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

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int32x4_t vmlaq_laneq_s32
(int32x4_t a, a → Vd.4S
int32x4_t b, b → Vn.4S MLA Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

uint16x4_t vmla_laneq_u16
(uint16x4_t a, a → Vd.4H
uint16x4_t b, b → Vn.4H MLA Vd.4H,Vn.4H,Vm.H[lane] Vd.4H ARMv8(AArch64)
uint16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

uint16x8_t vmlaq_laneq_u16
(uint16x8_t a, a → Vd.8H
uint16x8_t b, b → Vn.8H MLA Vd.8H,Vn.8H,Vm.H[lane] Vd.8H ARMv8(AArch64)
uint16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

uint32x2_t vmla_laneq_u32
(uint32x2_t a, a → Vd.2S
uint32x2_t b, b → Vn.2S MLA Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv8(AArch64)
uint32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

uint32x4_t vmlaq_laneq_u32
(uint32x4_t a, a → Vd.4S
uint32x4_t b, b → Vn.4S MLA Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv8(AArch64)
uint32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

float32x2_t vmla_laneq_f32
(float32x2_t a,
RESULT[I] = a[i] + (b[i] * v[lane]) for i
float32x2_t b, N/A ARMv8(AArch64)
= 0 to 1
float32x4_t v,
const int lane) 0 <= lane <= 3

float32x4_t vmlaq_laneq_f32
(float32x4_t a,
RESULT[I] = a[i] + (b[i] * v[lane]) for i
float32x4_t b, N/A ARMv8(AArch64)
= 0 to 3
float32x4_t v,
const int lane) 0 <= lane <= 3

int32x4_t vmlal_lane_s16
(int32x4_t a, a → Vd.4S
int16x4_t b, b → Vn.4H SMLAL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv7, ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int64x2_t vmlal_lane_s32
(int64x2_t a, a → Vd.2D
int32x2_t b, b → Vn.2S SMLAL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv7, ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

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uint32x4_t vmlal_lane_u16
(uint32x4_t a, a → Vd.4S
uint16x4_t b, b → Vn.4H UMLAL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv7, ARMv8
uint16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

uint64x2_t vmlal_lane_u32
(uint64x2_t a, a → Vd.2D
uint32x2_t b, b → Vn.2S UMLAL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv7, ARMv8
uint32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32x4_t vmlal_high_lane_s16
(int32x4_t a, a → Vd.4S
int16x8_t b, b → Vn.8H SMLAL2 Vd.4S,Vn.8H,Vm.H[lane] Vd.4S ARMv8(AArch64)
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int64x2_t vmlal_high_lane_s32
(int64x2_t a, a → Vd.2D
int32x4_t b, b → Vn.4S SMLAL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

uint32x4_t vmlal_high_lane_u16
(uint32x4_t a, a → Vd.4S
uint16x8_t b, b → Vn.8H UMLAL2 Vd.4S,Vn.8H,Vm.H[lane] Vd.4S ARMv8(AArch64)
uint16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

uint64x2_t vmlal_high_lane_u32
(uint64x2_t a, a → Vd.2D
uint32x4_t b, b → Vn.4S UMLAL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
uint32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32x4_t vmlal_laneq_s16
(int32x4_t a, a → Vd.4S
int16x4_t b, b → Vn.4H SMLAL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int64x2_t vmlal_laneq_s32
(int64x2_t a, a → Vd.2D
int32x2_t b, b → Vn.2S SMLAL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

uint32x4_t vmlal_laneq_u16
(uint32x4_t a, a → Vd.4S
uint16x4_t b, b → Vn.4H UMLAL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv8(AArch64)
uint16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

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uint64x2_t vmlal_laneq_u32
(uint64x2_t a, a → Vd.2D
uint32x2_t b, b → Vn.2S UMLAL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv8(AArch64)
uint32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32x4_t vmlal_high_laneq_s16
(int32x4_t a, a → Vd.4S
int16x8_t b, b → Vn.8H SMLAL2 Vd.4S,Vn.8H,Vm.H[lane] Vd.4S ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int64x2_t vmlal_high_laneq_s32
(int64x2_t a, a → Vd.2D
int32x4_t b, b → Vn.4S SMLAL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

uint32x4_t vmlal_high_laneq_u16
(uint32x4_t a, a → Vd.4S
uint16x8_t b, b → Vn.8H UMLAL2 Vd.4S,Vn.8H,Vm.H[lane] Vd.4S ARMv8(AArch64)
uint16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

uint64x2_t vmlal_high_laneq_u32
(uint64x2_t a, a → Vd.2D
uint32x4_t b, b → Vn.4S UMLAL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
uint32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32x4_t vqdmlal_lane_s16
(int32x4_t a, a → Vd.4S
int16x4_t b, b → Vn.4H SQDMLAL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv7, ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int64x2_t vqdmlal_lane_s32
(int64x2_t a, a → Vd.2D
int32x2_t b, b → Vn.2S SQDMLAL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv7, ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32_t vqdmlalh_lane_s16
(int32_t a, a → Sd
int16_t b, b → Hn SQDMLAL Sd,Hn,Vm.H[lane] Sd ARMv8(AArch64)
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int64_t vqdmlals_lane_s32
(int64_t a, a → Dd
int32_t b, b → Sn SQDMLAL Dd,Sn,Vm.S[lane] Dd ARMv8(AArch64)
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

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int32x4_t vqdmlal_high_lane_s16
(int32x4_t a, a → Vd.4S
SQDMLAL2
int16x8_t b, b → Vn.8H Vd.4S ARMv8(AArch64)
Vd.4S,Vn.8H,Vm.H[lane]
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int64x2_t vqdmlal_high_lane_s32
(int64x2_t a, a → Vd.2D
int32x4_t b, b → Vn.4S SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32x4_t vqdmlal_laneq_s16
(int32x4_t a, a → Vd.4S
int16x4_t b, b → Vn.4H SQDMLAL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int64x2_t vqdmlal_laneq_s32
(int64x2_t a, a → Vd.2D
int32x2_t b, b → Vn.2S SQDMLAL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32_t vqdmlalh_laneq_s16
(int32_t a, a → Sd
int16_t b, b → Hn SQDMLAL Sd,Hn,Vm.H[lane] Sd ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int64_t vqdmlals_laneq_s32
(int64_t a, a → Dd
int32_t b, b → Sn SQDMLAL Dd,Sn,Vm.S[lane] Dd ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32x4_t vqdmlal_high_laneq_s16
(int32x4_t a, a → Vd.4S
SQDMLAL2
int16x8_t b, b → Vn.8H Vd.4S ARMv8(AArch64)
Vd.4S,Vn.8H,Vm.H[lane]
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int64x2_t vqdmlal_high_laneq_s32
(int64x2_t a, a → Vd.2D
int32x4_t b, b → Vn.4S SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int16x4_t vmls_lane_s16
(int16x4_t a, a → Vd.4H
int16x4_t b, b → Vn.4H MLS Vd.4H,Vn.4H,Vm.H[lane] Vd.4H ARMv7, ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

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int16x8_t vmlsq_lane_s16
(int16x8_t a, a → Vd.8H
int16x8_t b, b → Vn.8H MLS Vd.8H,Vn.8H,Vm.H[lane] Vd.8H ARMv7, ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int32x2_t vmls_lane_s32
(int32x2_t a, a → Vd.2S
int32x2_t b, b → Vn.2S MLS Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv7, ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32x4_t vmlsq_lane_s32
(int32x4_t a, a → Vd.4S
int32x4_t b, b → Vn.4S MLS Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv7, ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

uint16x4_t vmls_lane_u16
(uint16x4_t a, a → Vd.4H
uint16x4_t b, b → Vn.4H MLS Vd.4H,Vn.4H,Vm.H[lane] Vd.4H ARMv7, ARMv8
uint16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

uint16x8_t vmlsq_lane_u16
(uint16x8_t a, a → Vd.8H
uint16x8_t b, b → Vn.8H MLS Vd.8H,Vn.8H,Vm.H[lane] Vd.8H ARMv7, ARMv8
uint16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

uint32x2_t vmls_lane_u32
(uint32x2_t a, a → Vd.2S
uint32x2_t b, b → Vn.2S MLS Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv7, ARMv8
uint32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

uint32x4_t vmlsq_lane_u32
(uint32x4_t a, a → Vd.4S
uint32x4_t b, b → Vn.4S MLS Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv7, ARMv8
uint32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

float32x2_t vmls_lane_f32
(float32x2_t a,
RESULT[I] = a[i] - (b[i] * v[lane]) for i
float32x2_t b, N/A ARMv7, ARMv8
= 0 to 1
float32x2_t v,
const int lane) 0 <= lane <= 1

float32x4_t vmlsq_lane_f32
(float32x4_t a,
RESULT[I] = a[i] - (b[i] * v[lane]) for i
float32x4_t b, N/A ARMv7, ARMv8
= 0 to 3
float32x2_t v,
const int lane) 0 <= lane <= 1

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int16x4_t vmls_laneq_s16
(int16x4_t a, a → Vd.4H
int16x4_t b, b → Vn.4H MLS Vd.4H,Vn.4H,Vm.H[lane] Vd.4H ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int16x8_t vmlsq_laneq_s16
(int16x8_t a, a → Vd.8H
int16x8_t b, b → Vn.8H MLS Vd.8H,Vn.8H,Vm.H[lane] Vd.8H ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int32x2_t vmls_laneq_s32
(int32x2_t a, a → Vd.2S
int32x2_t b, b → Vn.2S MLS Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32x4_t vmlsq_laneq_s32
(int32x4_t a, a → Vd.4S
int32x4_t b, b → Vn.4S MLS Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

uint16x4_t vmls_laneq_u16
(uint16x4_t a, a → Vd.4H
uint16x4_t b, b → Vn.4H MLS Vd.4H,Vn.4H,Vm.H[lane] Vd.4H ARMv8(AArch64)
uint16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

uint16x8_t vmlsq_laneq_u16
(uint16x8_t a, a → Vd.8H
uint16x8_t b, b → Vn.8H MLS Vd.8H,Vn.8H,Vm.H[lane] Vd.8H ARMv8(AArch64)
uint16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

uint32x2_t vmls_laneq_u32
(uint32x2_t a, a → Vd.2S
uint32x2_t b, b → Vn.2S MLS Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv8(AArch64)
uint32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

uint32x4_t vmlsq_laneq_u32
(uint32x4_t a, a → Vd.4S
uint32x4_t b, b → Vn.4S MLS Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv8(AArch64)
uint32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

float32x2_t vmls_laneq_f32
(float32x2_t a,
RESULT[I] = a[i] - (b[i] * v[lane]) for i
float32x2_t b, N/A ARMv8(AArch64)
= 0 to 1
float32x4_t v,
const int lane) 0 <= lane <= 3

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 124 of 348
Non-Confidential
float32x4_t vmlsq_laneq_f32
(float32x4_t a,
RESULT[I] = a[i] - (b[i] * v[lane]) for i
float32x4_t b, N/A ARMv8(AArch64)
= 0 to 3
float32x4_t v,
const int lane) 0 <= lane <= 3

int32x4_t vmlsl_lane_s16
(int32x4_t a, a → Vd.4S
int16x4_t b, b → Vn.4H SMLSL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv7, ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int64x2_t vmlsl_lane_s32
(int64x2_t a, a → Vd.2D
int32x2_t b, b → Vn.2S SMLSL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv7, ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

uint32x4_t vmlsl_lane_u16
(uint32x4_t a, a → Vd.4S
uint16x4_t b, b → Vn.4H UMLSL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv7, ARMv8
uint16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

uint64x2_t vmlsl_lane_u32
(uint64x2_t a, a → Vd.2D
uint32x2_t b, b → Vn.2S UMLSL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv7, ARMv8
uint32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32x4_t vmlsl_high_lane_s16
(int32x4_t a, a → Vd.4S
int16x8_t b, b → Vn.8H SMLSL2 Vd.4S,Vn.8H,Vm.H[lane] Vd.4S ARMv8(AArch64)
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int64x2_t vmlsl_high_lane_s32
(int64x2_t a, a → Vd.2D
int32x4_t b, b → Vn.4S SMLSL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

uint32x4_t vmlsl_high_lane_u16
(uint32x4_t a, a → Vd.4S
uint16x8_t b, b → Vn.8H UMLSL2 Vd.4S,Vn.8H,Vm.H[lane] Vd.4S ARMv8(AArch64)
uint16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

uint64x2_t vmlsl_high_lane_u32
(uint64x2_t a, a → Vd.2D
uint32x4_t b, b → Vn.4S UMLSL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
uint32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

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int32x4_t vmlsl_laneq_s16
(int32x4_t a, a → Vd.4S
int16x4_t b, b → Vn.4H SMLSL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int64x2_t vmlsl_laneq_s32
(int64x2_t a, a → Vd.2D
int32x2_t b, b → Vn.2S SMLSL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

uint32x4_t vmlsl_laneq_u16
(uint32x4_t a, a → Vd.4S
uint16x4_t b, b → Vn.4H UMLSL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv8(AArch64)
uint16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

uint64x2_t vmlsl_laneq_u32
(uint64x2_t a, a → Vd.2D
uint32x2_t b, b → Vn.2S UMLSL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv8(AArch64)
uint32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32x4_t vmlsl_high_laneq_s16
(int32x4_t a, a → Vd.4S
int16x8_t b, b → Vn.8H SMLSL2 Vd.4S,Vn.8H,Vm.H[lane] Vd.4S ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int64x2_t vmlsl_high_laneq_s32
(int64x2_t a, a → Vd.2D
int32x4_t b, b → Vn.4S SMLSL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

uint32x4_t vmlsl_high_laneq_u16
(uint32x4_t a, a → Vd.4S
uint16x8_t b, b → Vn.8H UMLSL2 Vd.4S,Vn.8H,Vm.H[lane] Vd.4S ARMv8(AArch64)
uint16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

uint64x2_t vmlsl_high_laneq_u32
(uint64x2_t a, a → Vd.2D
uint32x4_t b, b → Vn.4S UMLSL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
uint32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32x4_t vqdmlsl_lane_s16
(int32x4_t a, a → Vd.4S
int16x4_t b, b → Vn.4H SQDMLSL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv7, ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

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int64x2_t vqdmlsl_lane_s32
(int64x2_t a, a → Vd.2D
int32x2_t b, b → Vn.2S SQDMLSL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv7, ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32_t vqdmlslh_lane_s16
(int32_t a, a → Sd
int16_t b, b → Hn SQDMLSL Sd,Hn,Vm.H[lane] Sd ARMv8(AArch64)
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int64_t vqdmlsls_lane_s32
(int64_t a, a → Dd
int32_t b, b → Sn SQDMLSL Dd,Sn,Vm.S[lane] Dd ARMv8(AArch64)
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32x4_t vqdmlsl_high_lane_s16
(int32x4_t a, a → Vd.4S
SQDMLSL2
int16x8_t b, b → Vn.8H Vd.4S ARMv8(AArch64)
Vd.4S,Vn.8H,Vm.H[lane]
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int64x2_t vqdmlsl_high_lane_s32
(int64x2_t a, a → Vd.2D
int32x4_t b, b → Vn.4S SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32x4_t vqdmlsl_laneq_s16
(int32x4_t a, a → Vd.4S
int16x4_t b, b → Vn.4H SQDMLSL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int64x2_t vqdmlsl_laneq_s32
(int64x2_t a, a → Vd.2D
int32x2_t b, b → Vn.2S SQDMLSL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32_t vqdmlslh_laneq_s16
(int32_t a, a → Sd
int16_t b, b → Hn SQDMLSL Sd,Hn,Vm.H[lane] Sd ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int64_t vqdmlsls_laneq_s32
(int64_t a, a → Dd
int32_t b, b → Sn SQDMLSL Dd,Sn,Vm.S[lane] Dd ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

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Non-Confidential
int32x4_t vqdmlsl_high_laneq_s16
(int32x4_t a, a → Vd.4S
SQDMLSL2
int16x8_t b, b → Vn.8H Vd.4S ARMv8(AArch64)
Vd.4S,Vn.8H,Vm.H[lane]
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int64x2_t vqdmlsl_high_laneq_s32
(int64x2_t a, a → Vd.2D
int32x4_t b, b → Vn.4S SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int16x4_t vmul_n_s16
(int16x4_t a, a → Vn.4H MUL Vd.4H,Vn.4H,Vm.H[0] Vd.4H ARMv7, ARMv8
int16_t b) b → Vm.H[0]

int16x8_t vmulq_n_s16
(int16x8_t a, a → Vn.8H MUL Vd.8H,Vn.8H,Vm.H[0] Vd.8H ARMv7, ARMv8
int16_t b) b → Vm.H[0]

int32x2_t vmul_n_s32
(int32x2_t a, a → Vn.2S MUL Vd.2S,Vn.2S,Vm.S[0] Vd.2S ARMv7, ARMv8
int32_t b) b → Vm.S[0]

int32x4_t vmulq_n_s32
(int32x4_t a, a → Vn.4S MUL Vd.4S,Vn.4S,Vm.S[0] Vd.4S ARMv7, ARMv8
int32_t b) b → Vm.S[0]

uint16x4_t vmul_n_u16
(uint16x4_t a, a → Vn.4H MUL Vd.4H,Vn.4H,Vm.H[0] Vd.4H ARMv7, ARMv8
uint16_t b) b → Vm.H[0]

uint16x8_t vmulq_n_u16
(uint16x8_t a, a → Vn.8H MUL Vd.8H,Vn.8H,Vm.H[0] Vd.8H ARMv7, ARMv8
uint16_t b) b → Vm.H[0]

uint32x2_t vmul_n_u32
(uint32x2_t a, a → Vn.2S MUL Vd.2S,Vn.2S,Vm.S[0] Vd.2S ARMv7, ARMv8
uint32_t b) b → Vm.S[0]

uint32x4_t vmulq_n_u32
(uint32x4_t a, a → Vn.4S MUL Vd.4S,Vn.4S,Vm.S[0] Vd.4S ARMv7, ARMv8
uint32_t b) b → Vm.S[0]

float32x2_t vmul_n_f32
(float32x2_t a, a → Vn.2S FMUL Vd.2S,Vn.2S,Vm.S[0] Vd.2S ARMv7, ARMv8
float32_t b) b → Vm.S[0]

float32x4_t vmulq_n_f32
(float32x4_t a, a → Vn.4S FMUL Vd.4S,Vn.4S,Vm.S[0] Vd.4S ARMv7, ARMv8
float32_t b) b → Vm.S[0]

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float64x1_t vmul_n_f64
(float64x1_t a, a → Dn FMUL Dd,Dn,Vm.D[0] Dd ARMv8(AArch64)
float64_t b) b → Vm.D[0]

float64x2_t vmulq_n_f64
(float64x2_t a, a → Vn.2D FMUL Vd.2D,Vn.2D,Vm.D[0] Vd.2D ARMv8(AArch64)
float64_t b) b → Vm.D[0]

int16x4_t vmul_lane_s16
(int16x4_t a, a → Vn.4H
MUL Vd.4H,Vn.4H,Vm.H[lane] Vd.4H ARMv7, ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int16x8_t vmulq_lane_s16
(int16x8_t a, a → Vn.8H
MUL Vd.8H,Vn.8H,Vm.H[lane] Vd.8H ARMv7, ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int32x2_t vmul_lane_s32
(int32x2_t a, a → Vn.2S
MUL Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv7, ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32x4_t vmulq_lane_s32
(int32x4_t a, a → Vn.4S
MUL Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv7, ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

uint16x4_t vmul_lane_u16
(uint16x4_t a, a → Vn.4H
MUL Vd.4H,Vn.4H,Vm.H[lane] Vd.4H ARMv7, ARMv8
uint16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

uint16x8_t vmulq_lane_u16
(uint16x8_t a, a → Vn.8H
MUL Vd.8H,Vn.8H,Vm.H[lane] Vd.8H ARMv7, ARMv8
uint16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

uint32x2_t vmul_lane_u32
(uint32x2_t a, a → Vn.2S
MUL Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv7, ARMv8
uint32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

uint32x4_t vmulq_lane_u32
(uint32x4_t a, a → Vn.4S
MUL Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv7, ARMv8
uint32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

float32x2_t vmul_lane_f32
(float32x2_t a, a → Vn.2S
FMUL Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv7, ARMv8
float32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

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Non-Confidential
float32x4_t vmulq_lane_f32
(float32x4_t a, a → Vn.4S
FMUL Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv7, ARMv8
float32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

float64x1_t vmul_lane_f64
(float64x1_t a, a → Dn
FMUL Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x1_t v, v → Vm.1D
const int lane) lane == 0

float64x2_t vmulq_lane_f64
(float64x2_t a, a → Vn.2D
FMUL Vd.2D,Vn.2D,Vm.D[lane] Vd.2D ARMv8(AArch64)
float64x1_t v, v → Vm.1D
const int lane) lane == 0

float32_t vmuls_lane_f32
(float32_t a, a → Sn
FMUL Sd,Sn,Vm.S[lane] Sd ARMv8(AArch64)
float32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

float64_t vmuld_lane_f64
(float64_t a, a → Dn
FMUL Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x1_t v, v → Vm.1D
const int lane) lane == 0

int16x4_t vmul_laneq_s16
(int16x4_t a, a → Vn.4H
MUL Vd.4H,Vn.4H,Vm.H[lane] Vd.4H ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int16x8_t vmulq_laneq_s16
(int16x8_t a, a → Vn.8H
MUL Vd.8H,Vn.8H,Vm.H[lane] Vd.8H ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int32x2_t vmul_laneq_s32
(int32x2_t a, a → Vn.2S
MUL Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32x4_t vmulq_laneq_s32
(int32x4_t a, a → Vn.4S
MUL Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

uint16x4_t vmul_laneq_u16
(uint16x4_t a, a → Vn.4H
MUL Vd.4H,Vn.4H,Vm.H[lane] Vd.4H ARMv8(AArch64)
uint16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

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uint16x8_t vmulq_laneq_u16
(uint16x8_t a, a → Vn.8H
MUL Vd.8H,Vn.8H,Vm.H[lane] Vd.8H ARMv8(AArch64)
uint16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

uint32x2_t vmul_laneq_u32
(uint32x2_t a, a → Vn.2S
MUL Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv8(AArch64)
uint32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

uint32x4_t vmulq_laneq_u32
(uint32x4_t a, a → Vn.4S
MUL Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv8(AArch64)
uint32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

float32x2_t vmul_laneq_f32
(float32x2_t a, a → Vn.2S
FMUL Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv8(AArch64)
float32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

float32x4_t vmulq_laneq_f32
(float32x4_t a, a → Vn.4S
FMUL Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv8(AArch64)
float32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

float64x1_t vmul_laneq_f64
(float64x1_t a, a → Dn
FMUL Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x2_t v, v → Vm.2D
const int lane) 0 <= lane <= 1

float64x2_t vmulq_laneq_f64
(float64x2_t a, a → Vn.2D
FMUL Vd.2D,Vn.2D,Vm.D[lane] Vd.2D ARMv8(AArch64)
float64x2_t v, v → Vm.2D
const int lane) 0 <= lane <= 1

float32_t vmuls_laneq_f32
(float32_t a, a → Sn
FMUL Sd,Sn,Vm.S[lane] Sd ARMv8(AArch64)
float32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

float64_t vmuld_laneq_f64
(float64_t a, a → Dn
FMUL Dd,Dn,Vm.D[lane] Dd ARMv8(AArch64)
float64x2_t v, v → Vm.2D
const int lane) 0 <= lane <= 1

int32x4_t vmull_n_s16
(int16x4_t a, a → Vn.4H SMULL Vd.4S,Vn.4H,Vm.H[0] Vd.4S ARMv7, ARMv8
int16_t b) b → Vm.H[0]

int64x2_t vmull_n_s32
(int32x2_t a, a → Vn.2S SMULL Vd.2D,Vn.2S,Vm.S[0] Vd.2D ARMv7, ARMv8
int32_t b) b → Vm.S[0]

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uint32x4_t vmull_n_u16
(uint16x4_t a, a → Vn.4H UMULL Vd.4S,Vn.4H,Vm.H[0] Vd.4S ARMv7, ARMv8
uint16_t b) b → Vm.H[0]

uint64x2_t vmull_n_u32
(uint32x2_t a, a → Vn.2S UMULL Vd.2D,Vn.2S,Vm.S[0] Vd.2D ARMv7, ARMv8
uint32_t b) b → Vm.S[0]

int32x4_t vmull_high_n_s16
(int16x8_t a, a → Vn.8H SMULL2 Vd.4S,Vn.8H,Vm.H[0] Vd.4S ARMv8(AArch64)
int16_t b) b → Vm.H[0]

int64x2_t vmull_high_n_s32
(int32x4_t a, a → Vn.4S SMULL2 Vd.2D,Vn.4S,Vm.S[0] Vd.2D ARMv8(AArch64)
int32_t b) b → Vm.S[0]

uint32x4_t vmull_high_n_u16
(uint16x8_t a, a → Vn.8H UMULL2 Vd.4S,Vn.8H,Vm.H[0] Vd.4S ARMv8(AArch64)
uint16_t b) b → Vm.H[0]

uint64x2_t vmull_high_n_u32
(uint32x4_t a, a → Vn.4S UMULL2 Vd.2D,Vn.4S,Vm.S[0] Vd.2D ARMv8(AArch64)
uint32_t b) b → Vm.S[0]

int32x4_t vmull_lane_s16
(int16x4_t a, a → Vn.4H
SMULL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv7, ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int64x2_t vmull_lane_s32
(int32x2_t a, a → Vn.2S
SMULL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv7, ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

uint32x4_t vmull_lane_u16
(uint16x4_t a, a → Vn.4H
UMULL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv7, ARMv8
uint16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

uint64x2_t vmull_lane_u32
(uint32x2_t a, a → Vn.2S
UMULL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv7, ARMv8
uint32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32x4_t vmull_high_lane_s16
(int16x8_t a, a → Vn.8H
SMULL2 Vd.4S,Vn.8H,Vm.H[lane] Vd.4S ARMv8(AArch64)
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

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int64x2_t vmull_high_lane_s32
(int32x4_t a, a → Vn.4S
SMULL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

uint32x4_t vmull_high_lane_u16
(uint16x8_t a, a → Vn.8H
UMULL2 Vd.4S,Vn.8H,Vm.H[lane] Vd.4S ARMv8(AArch64)
uint16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

uint64x2_t vmull_high_lane_u32
(uint32x4_t a, a → Vn.4S
UMULL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
uint32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32x4_t vmull_laneq_s16
(int16x4_t a, a → Vn.4H
SMULL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int64x2_t vmull_laneq_s32
(int32x2_t a, a → Vn.2S
SMULL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

uint32x4_t vmull_laneq_u16
(uint16x4_t a, a → Vn.4H
UMULL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv8(AArch64)
uint16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

uint64x2_t vmull_laneq_u32
(uint32x2_t a, a → Vn.2S
UMULL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv8(AArch64)
uint32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32x4_t vmull_high_laneq_s16
(int16x8_t a, a → Vn.8H
SMULL2 Vd.4S,Vn.8H,Vm.H[lane] Vd.4S ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int64x2_t vmull_high_laneq_s32
(int32x4_t a, a → Vn.4S
SMULL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

uint32x4_t vmull_high_laneq_u16
(uint16x8_t a, a → Vn.8H
UMULL2 Vd.4S,Vn.8H,Vm.H[lane] Vd.4S ARMv8(AArch64)
uint16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

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uint64x2_t vmull_high_laneq_u32
(uint32x4_t a, a → Vn.4S
UMULL2 Vd.2D,Vn.4S,Vm.S[lane] Vd.2D ARMv8(AArch64)
uint32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32x4_t vqdmull_n_s16
(int16x4_t a, a → Vn.4H SQDMULL Vd.4S,Vn.4H,Vm.H[0] Vd.4S ARMv7, ARMv8
int16_t b) b → Vm.H[0]

int64x2_t vqdmull_n_s32
(int32x2_t a, a → Vn.2S SQDMULL Vd.2D,Vn.2S,Vm.S[0] Vd.2D ARMv7, ARMv8
int32_t b) b → Vm.S[0]

int32x4_t vqdmull_high_n_s16
(int16x8_t a, a → Vn.8H SQDMULL2 Vd.4S,Vn.8H,Vm.H[0] Vd.4S ARMv8(AArch64)
int16_t b) b → Vm.H[0]

int64x2_t vqdmull_high_n_s32
(int32x4_t a, a → Vn.4S SQDMULL2 Vd.2D,Vn.4S,Vm.S[0] Vd.2D ARMv8(AArch64)
int32_t b) b → Vm.S[0]

int32x4_t vqdmull_lane_s16
(int16x4_t a, a → Vn.4H
SQDMULL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv7, ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int64x2_t vqdmull_lane_s32
(int32x2_t a, a → Vn.2S
SQDMULL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv7, ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32_t vqdmullh_lane_s16
(int16_t a, a → Hn
SQDMULL Sd,Hn,Vm.H[lane] Sd ARMv8(AArch64)
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int64_t vqdmulls_lane_s32
(int32_t a, a → Sn
SQDMULL Dd,Sn,Vm.S[lane] Dd ARMv8(AArch64)
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32x4_t vqdmull_high_lane_s16
(int16x8_t a, a → Vn.8H SQDMULL2
Vd.4S ARMv8(AArch64)
int16x4_t v, v → Vm.4H Vd.4S,Vn.8H,Vm.H[lane]
const int lane) 0 <= lane <= 3

int64x2_t vqdmull_high_lane_s32
(int32x4_t a, a → Vn.4S SQDMULL2
Vd.2D ARMv8(AArch64)
int32x2_t v, v → Vm.2S Vd.2D,Vn.4S,Vm.S[lane]
const int lane) 0 <= lane <= 1

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int32x4_t vqdmull_laneq_s16
(int16x4_t a, a → Vn.4H
SQDMULL Vd.4S,Vn.4H,Vm.H[lane] Vd.4S ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int64x2_t vqdmull_laneq_s32
(int32x2_t a, a → Vn.2S
SQDMULL Vd.2D,Vn.2S,Vm.S[lane] Vd.2D ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32_t vqdmullh_laneq_s16
(int16_t a, a → Hn
SQDMULL Sd,Hn,Vm.H[lane] Sd ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int64_t vqdmulls_laneq_s32
(int32_t a, a → Sn
SQDMULL Dd,Sn,Vm.S[lane] Dd ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32x4_t vqdmull_high_laneq_s16
(int16x8_t a, a → Vn.8H SQDMULL2
Vd.4S ARMv8(AArch64)
int16x8_t v, v → Vm.8H Vd.4S,Vn.8H,Vm.H[lane]
const int lane) 0 <= lane <= 7

int64x2_t vqdmull_high_laneq_s32
(int32x4_t a, a → Vn.4S SQDMULL2
Vd.2D ARMv8(AArch64)
int32x4_t v, v → Vm.4S Vd.2D,Vn.4S,Vm.S[lane]
const int lane) 0 <= lane <= 3

int16x4_t vqdmulh_n_s16
(int16x4_t a, a → Vn.4H SQDMULH Vd.4H,Vn.4H,Vm.H[0] Vd.4H ARMv7, ARMv8
int16_t b) b → Vm.H[0]

int16x8_t vqdmulhq_n_s16
(int16x8_t a, a → Vn.8H SQDMULH Vd.8H,Vn.8H,Vm.H[0] Vd.8H ARMv7, ARMv8
int16_t b) b → Vm.H[0]

int32x2_t vqdmulh_n_s32
(int32x2_t a, a → Vn.2S SQDMULH Vd.2S,Vn.2S,Vm.S[0] Vd.2S ARMv7, ARMv8
int32_t b) b → Vm.S[0]

int32x4_t vqdmulhq_n_s32
(int32x4_t a, a → Vn.4S SQDMULH Vd.4S,Vn.4S,Vm.S[0] Vd.4S ARMv7, ARMv8
int32_t b) b → Vm.S[0]

int16x4_t vqdmlah_n_s16
(int16x4_t a, a → Vd.4H
SQDMLAH Vd.4H,Vn.4H,Vm.H[0] Vd.4H ARMv8
int16x4_t b, b → Vn.4H
int16_t c) c → Vm.H[0]

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int16x8_t vqdmlahq_n_s16
(int16x8_t a, a → Vd.8H
SQDMLAH Vd.8H,Vn.8H,Vm.H[0] Vd.8H ARMv8
int16x8_t b, b → Vn.8H
int16_t c) c → Vm.H[0]

int32x2_t vqdmlah_n_s32
(int32x2_t a, a → Vn.2S
SQDMLAH Vd.2S,Vn.2S,Vm.S[0] Vd.2S ARMv8
int32x2_t b, b → Vn.2S
int32_t c) c → Vm.S[0]

int32x4_t vqdmlahq_n_s32
(int32x4_t a, a → Vd.4S
SQDMLAH Vd.4S,Vn.4S,Vm.S[0] Vd.4S ARMv8
int32x4_t b, b → Vn.4S
int32_t c) c → Vm.S[0]

int16x4_t vqdmlsh_n_s16
(int16x4_t a, a → Vd.4H
SQDMLSH Vd.4H,Vn.4H,Vm.H[0] Vd.4H ARMv8
int16x4_t b, b → Vn.4H
int16_t c) c → Vm.H[0]

int16x8_t vqdmlshq_n_s16
(int16x8_t a, a → Vd.8H
SQDMLSH Vd.8H,Vn.8H,Vm.H[0] Vd.8H ARMv8
int16x8_t b, b → Vn.8H
int16_t c) c → Vm.H[0]

int32x2_t vqdmlsh_n_s32
(int32x2_t a, a → Vn.2S
SQDMLSH Vd.2S,Vn.2S,Vm.S[0] Vd.2S ARMv8
int32x2_t b, b → Vn.2S
int32_t c) c → Vm.S[0]

int32x4_t vqdmlshq_n_s32
(int32x4_t a, a → Vd.4S
SQDMLSH Vd.4S,Vn.4S,Vm.S[0] Vd.4S ARMv8
int32x4_t b, b → Vn.4S
int32_t c) c → Vm.S[0]

int16x4_t vqdmulh_lane_s16
(int16x4_t a, a → Vn.4H
SQDMULH Vd.4H,Vn.4H,Vm.H[lane] Vd.4H ARMv7, ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int16x8_t vqdmulhq_lane_s16
(int16x8_t a, a → Vn.8H
SQDMULH Vd.8H,Vn.8H,Vm.H[lane] Vd.8H ARMv7, ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int32x2_t vqdmulh_lane_s32
(int32x2_t a, a → Vn.2S
SQDMULH Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv7, ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

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int32x4_t vqdmulhq_lane_s32
(int32x4_t a, a → Vn.4S
SQDMULH Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv7, ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int16_t vqdmulhh_lane_s16
(int16_t a, a → Hn
SQDMULH Hd,Hn,Vm.H[lane] Hd ARMv8(AArch64)
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int32_t vqdmulhs_lane_s32
(int32_t a, a → Sn
SQDMULH Sd,Sn,Vm.H[lane] Sd ARMv8(AArch64)
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int16x4_t vqdmulh_laneq_s16
(int16x4_t a, a → Vn.4H
SQDMULH Vd.4H,Vn.4H,Vm.H[lane] Vd.4H ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int16x8_t vqdmulhq_laneq_s16
(int16x8_t a, a → Vn.8H
SQDMULH Vd.8H,Vn.8H,Vm.H[lane] Vd.8H ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int32x2_t vqdmulh_laneq_s32
(int32x2_t a, a → Vn.2S
SQDMULH Vd.2S,Vn.2S,Vm.S[lane] Vd.2S ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32x4_t vqdmulhq_laneq_s32
(int32x4_t a, a → Vn.4S
SQDMULH Vd.4S,Vn.4S,Vm.S[lane] Vd.4S ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int16_t vqdmulhh_laneq_s16
(int16_t a, a → Hn
SQDMULH Hd,Hn,Vm.H[lane] Hd ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int32_t vqdmulhs_laneq_s32
(int32_t a, a → Sn
SQDMULH Sd,Sn,Vm.S[lane] Sd ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int16x4_t vqrdmulh_n_s16
(int16x4_t a, a → Vn.4H SQRDMULH Vd.4H,Vn.4H,Vm.H[0] Vd.4H ARMv7, ARMv8
int16_t b) b → Vm.H[0]

int16x8_t vqrdmulhq_n_s16
(int16x8_t a, a → Vn.8H SQRDMULH Vd.8H,Vn.8H,Vm.H[0] Vd.8H ARMv7, ARMv8
int16_t b) b → Vm.H[0]

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int32x2_t vqrdmulh_n_s32
(int32x2_t a, a → Vn.2S SQRDMULH Vd.2S,Vn.2S,Vm.S[0] Vd.2S ARMv7, ARMv8
int32_t b) b → Vm.S[0]

int32x4_t vqrdmulhq_n_s32
(int32x4_t a, a → Vn.4S SQRDMULH Vd.4S,Vn.4S,Vm.S[0] Vd.4S ARMv7, ARMv8
int32_t b) b → Vm.S[0]

int16x4_t vqrdmulh_lane_s16
(int16x4_t a, a → Vn.4H SQRDMULH
Vd.4H ARMv7, ARMv8
int16x4_t v, v → Vm.4H Vd.4H,Vn.4H,Vm.H[lane]
const int lane) 0 <= lane <= 3

int16x8_t vqrdmulhq_lane_s16
(int16x8_t a, a → Vn.8H SQRDMULH
Vd.8H ARMv7, ARMv8
int16x4_t v, v → Vm.4H Vd.8H,Vn.8H,Vm.H[lane]
const int lane) 0 <= lane <= 3

int32x2_t vqrdmulh_lane_s32
(int32x2_t a, a → Vn.2S SQRDMULH
Vd.2S ARMv7, ARMv8
int32x2_t v, v → Vm.2S Vd.2S,Vn.2S,Vm.S[lane]
const int lane) 0 <= lane <= 1

int32x4_t vqrdmulhq_lane_s32
(int32x4_t a, a → Vn.4S SQRDMULH
Vd.4S ARMv7, ARMv8
int32x2_t v, v → Vm.2S Vd.4S,Vn.4S,Vm.S[lane]
const int lane) 0 <= lane <= 1

int16_t vqrdmulhh_lane_s16
(int16_t a, a → Hn
SQRDMULH Hd,Hn,Vm.H[lane] Hd ARMv8(AArch64)
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int32_t vqrdmulhs_lane_s32
(int32_t a, a → Sn
SQRDMULH Sd,Sn,Vm.S[lane] Sd ARMv8(AArch64)
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int16x4_t vqrdmulh_laneq_s16
(int16x4_t a, a → Vn.4H SQRDMULH
Vd.4H ARMv8(AArch64)
int16x8_t v, v → Vm.8H Vd.4H,Vn.4H,Vm.H[lane]
const int lane) 0 <= lane <= 7

int16x8_t vqrdmulhq_laneq_s16
(int16x8_t a, a → Vn.8H SQRDMULH
Vd.8H ARMv8(AArch64)
int16x8_t v, v → Vm.8H Vd.8H,Vn.8H,Vm.H[lane]
const int lane) 0 <= lane <= 7

int32x2_t vqrdmulh_laneq_s32
(int32x2_t a, a → Vn.2S SQRDMULH
Vd.2S ARMv8(AArch64)
int32x4_t v, v → Vm.4S Vd.2S,Vn.2S,Vm.S[lane]
const int lane) 0 <= lane <= 3

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Non-Confidential
int32x4_t vqrdmulhq_laneq_s32
(int32x4_t a, a → Vn.4S SQRDMULH
Vd.4S ARMv8(AArch64)
int32x4_t v, v → Vm.4S Vd.4S,Vn.4S,Vm.S[lane]
const int lane) 0 <= lane <= 3

int16_t vqrdmulhh_laneq_s16
(int16_t a, a → Hn
SQRDMULH Hd,Hn,Vm.H[lane] Hd ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int32_t vqrdmulhs_laneq_s32
(int32_t a, a → Sn
SQRDMULH Sd,Sn,Vm.S[lane] Sd ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int16x4_t vqrdmlah_lane_s16
(int16x4_t a, a → Vd.4H
SQRDMLAH
int16x4_t b, b → Vn.4H Vd.4H,Vn.4H,Vm.H[lane]
Vd.4H ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int16x8_t vqrdmlahq_lane_s16
(int16x8_t a, a → Vd.8H
SQRDMLAH
int16x8_t b, b → Vn.8H Vd.8H,Vn.8H,Vm.H[lane]
Vd.8H ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int32x2_t vqrdmulh_lane_s32
(int32x2_t a, a → Vd.2S
SQRDMLAH
int32x2_t b, b → Vn.2S Vd.2S,Vn.2S,Vm.S[lane]
Vd.2S ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int32x4_t vqrdmlahq_lane_s32
(int32x4_t a, a → Vd.4S
SQRDMLAH
int32x4_t b, b → Vn.4S Vd.4S,Vn.4S,Vm.S[lane]
Vd.4S ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int16_t vqrdmlahh_lane_s16
(int16_t a, a → Hd
int16_t b, b → Hn SQRDMLAH Hd,Hn,Vm.H[lane] Hd ARMv8(AArch64)
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int32_t vqrdmlahs_lane_s32
(int32_t a, a → Sd
int32_t b, b → Sn SQRDMLAH Sd,Sn,Vm.S[lane] Sd ARMv8(AArch64)
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

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int16x4_t vqrdmlah_laneq_s16
(int16x4_t a, a → Vd.4H
SQRDMLAH
int16x4_t b, b → Vn.4H Vd.4H,Vn.4H,Vm.H[lane]
Vd.4H ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int16x8_t vqrdmlahq_laneq_s16
(int16x8_t a, a → Vd.8H
SQRDMLAH
int16x8_t b, b → Vn.8H Vd.8H,Vn.8H,Vm.H[lane]
Vd.8H ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int32x2_t vqrdmlah_laneq_s32
(int32x2_t a, a → Vd.2S
SQRDMLAH
int32x2_t b, b → Vn.2S Vd.2S,Vn.2S,Vm.S[lane]
Vd.2S ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32x4_t vqrdmlahq_laneq_s32
(int32x4_t a, a → Vd.4S
SQRDMLAH
int32x4_t b, b → Vn.4S Vd.4S,Vn.4S,Vm.S[lane]
Vd.4S ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int16_t vqrdmlahh_laneq_s16
(int16_t a, a → Hd
int16_t b, b → Hn SQRDMLAH Hd,Hn,Vm.H[lane] Hd ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int32_t vqrdmlahs_laneq_s32
(int32_t a, a → Sd
int32_t b, b → Sn SQRDMLAH Sd,Sn,Vm.S[lane] Sd ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int16x4_t vqrdmlsh_lane_s16
(int16x4_t a, a → Vd.4H
SQRDMLSH
int16x4_t b, b → Vn.4H Vd.4H,Vn.4H,Vm.H[lane]
Vd.4H ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int16x8_t vqrdmlshq_lane_s16
(int16x8_t a, a → Vd.8H
SQRDMLSH
int16x8_t b, b → Vn.8H Vd.8H,Vn.8H,Vm.H[lane]
Vd.8H ARMv8
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int32x2_t vqrdmlsh_lane_s32
(int32x2_t a, a → Vd.2S
SQRDMLSH
int32x2_t b, b → Vn.2S Vd.2S,Vn.2S,Vm.S[lane]
Vd.2S ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 140 of 348
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int32x4_t vqrdmlshq_lane_s32
(int32x4_t a, a → Vd.4S
SQRDMLSH
int32x4_t b, b → Vn.4S Vd.4S,Vn.4S,Vm.S[lane]
Vd.4S ARMv8
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int16_t vqrdmlshh_lane_s16
(int16_t a, a → Hd
int16_t b, b → Hn SQRDMLSH Hd,Hn,Vm.H[lane] Hd ARMv8(AArch64)
int16x4_t v, v → Vm.4H
const int lane) 0 <= lane <= 3

int32_t vqrdmlshs_lane_s32
(int32_t a, a → Sd
int32_t b, b → Sn SQRDMLSH Sd,Sn,Vm.S[lane] Sd ARMv8(AArch64)
int32x2_t v, v → Vm.2S
const int lane) 0 <= lane <= 1

int16x4_t vqrdmlsh_laneq_s16
(int16x4_t a, a → Vd.4H
SQRDMLSH
int16x4_t b, b → Vn.4H Vd.4H,Vn.4H,Vm.H[lane]
Vd.4H ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int16x8_t vqrdmlshq_laneq_s16
(int16x8_t a, a → Vd.8H
SQRDMLSH
int16x8_t b, b → Vn.8H Vd.8H,Vn.8H,Vm.H[lane]
Vd.8H ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int32x2_t vqrdmlsh_laneq_s32
(int32x2_t a, a → Vd.2S
SQRDMLSH
int32x2_t b, b → Vn.2S Vd.2S,Vn.2S,Vm.S[lane]
Vd.2S ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int32x4_t vqrdmlshq_laneq_s32
(int32x4_t a, a → Vd.4S
SQRDMLSH
int32x4_t b, b → Vn.4S Vd.4S,Vn.4S,Vm.S[lane]
Vd.4S ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

int16_t vqrdmlshh_laneq_s16
(int16_t a, a → Hd
int16_t b, b → Hn SQRDMLSH Hd,Hn,Vm.H[lane] Hd ARMv8(AArch64)
int16x8_t v, v → Vm.8H
const int lane) 0 <= lane <= 7

int32_t vqrdmlshs_laneq_s32
(int32_t a, a → Sd
int32_t b, b → Sn SQRDMLSH Sd,Sn,Vm.S[lane] Sd ARMv8(AArch64)
int32x4_t v, v → Vm.4S
const int lane) 0 <= lane <= 3

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int16x4_t vmla_n_s16
(int16x4_t a, a → Vd.4H
MLA Vd.4H,Vn.4H,Vm.H[0] Vd.4H ARMv7, ARMv8
int16x4_t b, b → Vn.4H
int16_t c) c → Vm.H[0]

int16x8_t vmlaq_n_s16
(int16x8_t a, a → Vd.8H
MLA Vd.8H,Vn.8H,Vm.H[0] Vd.8H ARMv7, ARMv8
int16x8_t b, b → Vn.8H
int16_t c) c → Vm.H[0]

int32x2_t vmla_n_s32
(int32x2_t a, a → Vd.2S
MLA Vd.2S,Vn.2S,Vm.S[0] Vd.2S ARMv7, ARMv8
int32x2_t b, b → Vn.2S
int32_t c) c → Vm.S[0]

int32x4_t vmlaq_n_s32
(int32x4_t a, a → Vd.4S
MLA Vd.4S,Vn.4S,Vm.S[0] Vd.4S ARMv7, ARMv8
int32x4_t b, b → Vn.4S
int32_t c) c → Vm.S[0]

uint16x4_t vmla_n_u16
(uint16x4_t a, a → Vd.4H
MLA Vd.4H,Vn.4H,Vm.H[0] Vd.4H ARMv7, ARMv8
uint16x4_t b, b → Vn.4H
uint16_t c) c → Vm.H[0]

uint16x8_t vmlaq_n_u16
(uint16x8_t a, a → Vd.8H
MLA Vd.8H,Vn.8H,Vm.H[0] Vd.8H ARMv7, ARMv8
uint16x8_t b, b → Vn.8H
uint16_t c) c → Vm.H[0]

uint32x2_t vmla_n_u32
(uint32x2_t a, a → Vd.2S
MLA Vd.2S,Vn.2S,Vm.S[0] Vd.2S ARMv7, ARMv8
uint32x2_t b, b → Vn.2S
uint32_t c) c → Vm.S[0]

uint32x4_t vmlaq_n_u32
(uint32x4_t a, a → Vd.4S
MLA Vd.4S,Vn.4S,Vm.S[0] Vd.4S ARMv7, ARMv8
uint32x4_t b, b → Vn.4S
uint32_t c) c → Vm.S[0]

float32x2_t vmla_n_f32
(float32x2_t a, a → N/A RESULT[I] = a[i] + (b[i] * c) for i = 0 to
N/A ARMv7, ARMv8
float32x2_t b, b → N/A 1
float32_t c) c → N/A

float32x4_t vmlaq_n_f32
(float32x4_t a, a → N/A RESULT[I] = a[i] + (b[i] * c) for i = 0 to
N/A ARMv7, ARMv8
float32x4_t b, b → N/A 3
float32_t c) c → N/A

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int32x4_t vmlal_n_s16
(int32x4_t a, a → Vd.4S
SMLAL Vd.4S,Vn.4H,Vm.H[0] Vd.4S ARMv7, ARMv8
int16x4_t b, b → Vn.4H
int16_t c) c → Vm.H[0]

int64x2_t vmlal_n_s32
(int64x2_t a, a → Vd.2D
SMLAL Vd.2D,Vn.2S,Vm.S[0] Vd.2D ARMv7, ARMv8
int32x2_t b, b → Vn.2S
int32_t c) c → Vm.S[0]

uint32x4_t vmlal_n_u16
(uint32x4_t a, a → Vd.4S
UMLAL Vd.4S,Vn.4H,Vm.H[0] Vd.4S ARMv7, ARMv8
uint16x4_t b, b → Vn.4H
uint16_t c) c → Vm.H[0]

uint64x2_t vmlal_n_u32
(uint64x2_t a, a → Vd.2D
UMLAL Vd.2D,Vn.2S,Vm.S[0] Vd.2D ARMv7, ARMv8
uint32x2_t b, b → Vn.2S
uint32_t c) c → Vm.S[0]

int32x4_t vmlal_high_n_s16
(int32x4_t a, a → Vd.4S
SMLAL2 Vd.4S,Vn.8H,Vm.H[0] Vd.4S ARMv8(AArch64)
int16x8_t b, b → Vn.8H
int16_t c) c → Vm.H[0]

int64x2_t vmlal_high_n_s32
(int64x2_t a, a → Vd.2D
SMLAL2 Vd.2D,Vn.4S,Vm.S[0] Vd.2D ARMv8(AArch64)
int32x4_t b, b → Vn.4S
int32_t c) c → Vm.S[0]

uint32x4_t vmlal_high_n_u16
(uint32x4_t a, a → Vd.4S
UMLAL2 Vd.4S,Vn.8H,Vm.H[0] Vd.4S ARMv8(AArch64)
uint16x8_t b, b → Vn.8H
uint16_t c) c → Vm.H[0]

uint64x2_t vmlal_high_n_u32
(uint64x2_t a, a → Vd.2D
UMLAL2 Vd.2D,Vn.4S,Vm.S[0] Vd.2D ARMv8(AArch64)
uint32x4_t b, b → Vn.4S
uint32_t c) c → Vm.S[0]

int32x4_t vqdmlal_n_s16
(int32x4_t a, a → Vd.4S
SQDMLAL Vd.4S,Vn.4H,Vm.H[0] Vd.4S ARMv7, ARMv8
int16x4_t b, b → Vn.4H
int16_t c) c → Vm.H[0]

int64x2_t vqdmlal_n_s32
(int64x2_t a, a → Vd.2D
SQDMLAL Vd.2D,Vn.2S,Vm.S[0] Vd.2D ARMv7, ARMv8
int32x2_t b, b → Vn.2S
int32_t c) c → Vm.S[0]

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int32x4_t vqdmlal_high_n_s16
(int32x4_t a, a → Vd.4S
SQDMLAL2 Vd.4S,Vn.8H,Vm.H[0] Vd.4S ARMv8(AArch64)
int16x8_t b, b → Vn.8H
int16_t c) c → Vm.H[0]

int64x2_t vqdmlal_high_n_s32
(int64x2_t a, a → Vd.2D
SQDMLAL2 Vd.2D,Vn.4S,Vm.S[0] Vd.2D ARMv8(AArch64)
int32x4_t b, b → Vn.4S
int32_t c) c → Vm.S[0]

int16x4_t vmls_n_s16
(int16x4_t a, a → Vd.4H
MLS Vd.4H,Vn.4H,Vm.H[0] Vd.4H ARMv7, ARMv8
int16x4_t b, b → Vn.4H
int16_t c) c → Vm.H[0]

int16x8_t vmlsq_n_s16
(int16x8_t a, a → Vd.8H
MLS Vd.8H,Vn.8H,Vm.H[0] Vd.8H ARMv7, ARMv8
int16x8_t b, b → Vn.8H
int16_t c) c → Vm.H[0]

int32x2_t vmls_n_s32
(int32x2_t a, a → Vd.2S
MLS Vd.2S,Vn.2S,Vm.S[0] Vd.2S ARMv7, ARMv8
int32x2_t b, b → Vn.2S
int32_t c) c → Vm.S[0]

int32x4_t vmlsq_n_s32
(int32x4_t a, a → Vd.4S
MLS Vd.4S,Vn.4S,Vm.S[0] Vd.4S ARMv7, ARMv8
int32x4_t b, b → Vn.4S
int32_t c) c → Vm.S[0]

uint16x4_t vmls_n_u16
(uint16x4_t a, a → Vd.4H
MLS Vd.4H,Vn.4H,Vm.H[0] Vd.4H ARMv7, ARMv8
uint16x4_t b, b → Vn.4H
uint16_t c) c → Vm.H[0]

uint16x8_t vmlsq_n_u16
(uint16x8_t a, a → Vd.8H
MLS Vd.8H,Vn.8H,Vm.H[0] Vd.8H ARMv7, ARMv8
uint16x8_t b, b → Vn.8H
uint16_t c) c → Vm.H[0]

uint32x2_t vmls_n_u32
(uint32x2_t a, a → Vd.2S
MLS Vd.2S,Vn.2S,Vm.S[0] Vd.2S ARMv7, ARMv8
uint32x2_t b, b → Vn.2S
uint32_t c) c → Vm.S[0]

uint32x4_t vmlsq_n_u32
(uint32x4_t a, a → Vd.4S
MLS Vd.4S,Vn.4S,Vm.S[0] Vd.4S ARMv7, ARMv8
uint32x4_t b, b → Vn.4S
uint32_t c) c → Vm.S[0]

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Non-Confidential
float32x2_t vmls_n_f32
(float32x2_t a, a → N/A RESULT[I] = a[i] - (b[i] * c) for i = 0 to
N/A ARMv7, ARMv8
float32x2_t b, b → N/A 1
float32_t c) c → N/A

float32x4_t vmlsq_n_f32
(float32x4_t a, a → N/A RESULT[I] = a[i] - (b[i] * c) for i = 0 to
N/A ARMv7, ARMv8
float32x4_t b, b → N/A 3
float32_t c) c → N/A

int32x4_t vmlsl_n_s16
(int32x4_t a, a → Vd.4S
SMLSL Vd.4S,Vn.4H,Vm.H[0] Vd.4S ARMv7, ARMv8
int16x4_t b, b → Vn.4H
int16_t c) c → Vm.H[0]

int64x2_t vmlsl_n_s32
(int64x2_t a, a → Vd.2D
SMLSL Vd.2D,Vn.2S,Vm.S[0] Vd.2D ARMv7, ARMv8
int32x2_t b, b → Vn.2S
int32_t c) c → Vm.S[0]

uint32x4_t vmlsl_n_u16
(uint32x4_t a, a → Vd.4S
UMLSL Vd.4S,Vn.4H,Vm.H[0] Vd.4S ARMv7, ARMv8
uint16x4_t b, b → Vn.4H
uint16_t c) c → Vm.H[0]

uint64x2_t vmlsl_n_u32
(uint64x2_t a, a → Vd.2D
UMLSL Vd.2D,Vn.2S,Vm.S[0] Vd.2D ARMv7, ARMv8
uint32x2_t b, b → Vn.2S
uint32_t c) c → Vm.S[0]

int32x4_t vmlsl_high_n_s16
(int32x4_t a, a → Vd.4S
SMLSL2 Vd.4S,Vn.8H,Vm.H[0] Vd.4S ARMv8(AArch64)
int16x8_t b, b → Vn.8H
int16_t c) c → Vm.H[0]

int64x2_t vmlsl_high_n_s32
(int64x2_t a, a → Vd.2D
SMLSL2 Vd.2D,Vn.4S,Vm.S[0] Vd.2D ARMv8(AArch64)
int32x4_t b, b → Vn.4S
int32_t c) c → Vm.S[0]

uint32x4_t vmlsl_high_n_u16
(uint32x4_t a, a → Vd.4S
UMLSL2 Vd.4S,Vn.8H,Vm.H[0] Vd.4S ARMv8(AArch64)
uint16x8_t b, b → Vn.8H
uint16_t c) c → Vm.H[0]

uint64x2_t vmlsl_high_n_u32
(uint64x2_t a, a → Vd.2D
UMLSL2 Vd.2D,Vn.4S,Vm.S[0] Vd.2D ARMv8(AArch64)
uint32x4_t b, b → Vn.4S
uint32_t c) c → Vm.S[0]

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Non-Confidential
int32x4_t vqdmlsl_n_s16
(int32x4_t a, a → Vd.4S
SQDMLSL Vd.4S,Vn.4H,Vm.H[0] Vd.4S ARMv7, ARMv8
int16x4_t b, b → Vn.4H
int16_t c) c → Vm.H[0]

int64x2_t vqdmlsl_n_s32
(int64x2_t a, a → Vd.2D
SQDMLSL Vd.2D,Vn.2S,Vm.S[0] Vd.2D ARMv7, ARMv8
int32x2_t b, b → Vn.2S
int32_t c) c → Vm.S[0]

int32x4_t vqdmlsl_high_n_s16
(int32x4_t a, a → Vd.4S
SQDMLSL2 Vd.4S,Vn.8H,Vm.H[0] Vd.4S ARMv8(AArch64)
int16x8_t b, b → Vn.8H
int16_t c) c → Vm.H[0]

int64x2_t vqdmlsl_high_n_s32
(int64x2_t a, a → Vd.2D
SQDMLSL2 Vd.2D,Vn.4S,Vm.S[0] Vd.2D ARMv8(AArch64)
int32x4_t b, b → Vn.4S
int32_t c) c → Vm.S[0]

int8x8_t vabs_s8
ABS Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(int8x8_t a) a → Vn.8B

int8x16_t vabsq_s8
ABS Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(int8x16_t a) a → Vn.16B

int16x4_t vabs_s16
ABS Vd.4H,Vn.4H Vd.4H ARMv7, ARMv8
(int16x4_t a) a → Vn.4H

int16x8_t vabsq_s16
ABS Vd.8H,Vn.8H Vd.8H ARMv7, ARMv8
(int16x8_t a) a → Vn.8H

int32x2_t vabs_s32
ABS Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(int32x2_t a) a → Vn.2S

int32x4_t vabsq_s32
ABS Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(int32x4_t a) a → Vn.4S

float32x2_t vabs_f32
FABS Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(float32x2_t a) a → Vn.2S

float32x4_t vabsq_f32
FABS Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(float32x4_t a) a → Vn.4S

int64x1_t vabs_s64
ABS Dd,Dn Dd ARMv8(AArch64)
(int64x1_t a) a → Dn

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 146 of 348
Non-Confidential
int64_t vabsd_s64
ABS Dd,Dn Dd ARMv8(AArch64)
(int64_t a) a → Dn

int64x2_t vabsq_s64
ABS Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(int64x2_t a) a → Vn.2D

float64x1_t vabs_f64
FABS Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

float64x2_t vabsq_f64
FABS Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

int8x8_t vqabs_s8
SQABS Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(int8x8_t a) a → Vn.8B

int8x16_t vqabsq_s8
SQABS Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(int8x16_t a) a → Vn.16B

int16x4_t vqabs_s16
SQABS Vd.4H,Vn.4H Vd.4H ARMv7, ARMv8
(int16x4_t a) a → Vn.4H

int16x8_t vqabsq_s16
SQABS Vd.8H,Vn.8H Vd.8H ARMv7, ARMv8
(int16x8_t a) a → Vn.8H

int32x2_t vqabs_s32
SQABS Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(int32x2_t a) a → Vn.2S

int32x4_t vqabsq_s32
SQABS Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(int32x4_t a) a → Vn.4S

int64x1_t vqabs_s64
SQABS Dd,Dn Dd ARMv8(AArch64)
(int64x1_t a) a → Dn

int64x2_t vqabsq_s64
SQABS Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(int64x2_t a) a → Vn.2D

int8_t vqabsb_s8
SQABS Bd,Bn Bd ARMv8(AArch64)
(int8_t a) a → Bn

int16_t vqabsh_s16
SQABS Hd,Hn Hd ARMv8(AArch64)
(int16_t a) a → Hn

int32_t vqabss_s32
SQABS Sd,Sn Sd ARMv8(AArch64)
(int32_t a) a → Sn

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int64_t vqabsd_s64
SQABS Dd,Dn Dd ARMv8(AArch64)
(int64_t a) a → Dn

int8x8_t vneg_s8
NEG Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(int8x8_t a) a → Vn.8B

int8x16_t vnegq_s8
NEG Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(int8x16_t a) a → Vn.16B

int16x4_t vneg_s16
NEG Vd.4H,Vn.4H Vd.4H ARMv7, ARMv8
(int16x4_t a) a → Vn.4H

int16x8_t vnegq_s16
NEG Vd.8H,Vn.8H Vd.8H ARMv7, ARMv8
(int16x8_t a) a → Vn.8H

int32x2_t vneg_s32
NEG Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(int32x2_t a) a → Vn.2S

int32x4_t vnegq_s32
NEG Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(int32x4_t a) a → Vn.4S

float32x2_t vneg_f32
FNEG Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(float32x2_t a) a → Vn.2S

float32x4_t vnegq_f32
FNEG Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(float32x4_t a) a → Vn.4S

int64x1_t vneg_s64
NEG Dd,Dn Dd ARMv8(AArch64)
(int64x1_t a) a → Dn

int64_t vnegd_s64
NEG Dd,Dn Dd ARMv8(AArch64)
(int64_t a) a → Dn

int64x2_t vnegq_s64
NEG Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(int64x2_t a) a → Vn.2D

float64x1_t vneg_f64
FNEG Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

float64x2_t vnegq_f64
FNEG Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

int8x8_t vqneg_s8
SQNEG Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(int8x8_t a) a → Vn.8B

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int8x16_t vqnegq_s8
SQNEG Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(int8x16_t a) a → Vn.16B

int16x4_t vqneg_s16
SQNEG Vd.4H,Vn.4H Vd.4H ARMv7, ARMv8
(int16x4_t a) a → Vn.4H

int16x8_t vqnegq_s16
SQNEG Vd.8H,Vn.8H Vd.8H ARMv7, ARMv8
(int16x8_t a) a → Vn.8H

int32x2_t vqneg_s32
SQNEG Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(int32x2_t a) a → Vn.2S

int32x4_t vqnegq_s32
SQNEG Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(int32x4_t a) a → Vn.4S

int64x1_t vqneg_s64
SQNEG Dd,Dn Dd ARMv8(AArch64)
(int64x1_t a) a → Dn

int64x2_t vqnegq_s64
SQNEG Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(int64x2_t a) a → Vn.2D

int8_t vqnegb_s8
SQNEG Bd,Bn Bd ARMv8(AArch64)
(int8_t a) a → Bn

int16_t vqnegh_s16
SQNEG Hd,Hn Hd ARMv8(AArch64)
(int16_t a) a → Hn

int32_t vqnegs_s32
SQNEG Sd,Sn Sd ARMv8(AArch64)
(int32_t a) a → Sn

int64_t vqnegd_s64
SQNEG Dd,Dn Dd ARMv8(AArch64)
(int64_t a) a → Dn

int8x8_t vcls_s8
CLS Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(int8x8_t a) a → Vn.8B

int8x16_t vclsq_s8
CLS Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(int8x16_t a) a → Vn.16B

int16x4_t vcls_s16
CLS Vd.4H,Vn.4H Vd.4H ARMv7, ARMv8
(int16x4_t a) a → Vn.4H

int16x8_t vclsq_s16
CLS Vd.8H,Vn.8H Vd.8H ARMv7, ARMv8
(int16x8_t a) a → Vn.8H

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int32x2_t vcls_s32
CLS Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(int32x2_t a) a → Vn.2S

int32x4_t vclsq_s32
CLS Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(int32x4_t a) a → Vn.4S

int8x8_t vclz_s8
CLZ Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(int8x8_t a) a → Vn.8B

int8x16_t vclzq_s8
CLZ Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(int8x16_t a) a → Vn.16B

int16x4_t vclz_s16
CLZ Vd.4H,Vn.4H Vd.4H ARMv7, ARMv8
(int16x4_t a) a → Vn.4H

int16x8_t vclzq_s16
CLZ Vd.8H,Vn.8H Vd.8H ARMv7, ARMv8
(int16x8_t a) a → Vn.8H

int32x2_t vclz_s32
CLZ Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(int32x2_t a) a → Vn.2S

int32x4_t vclzq_s32
CLZ Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(int32x4_t a) a → Vn.4S

uint8x8_t vclz_u8
CLZ Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(uint8x8_t a) a → Vn.8B

uint8x16_t vclzq_u8
CLZ Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(uint8x16_t a) a → Vn.16B

uint16x4_t vclz_u16
CLZ Vd.4H,Vn.4H Vd.4H ARMv7, ARMv8
(uint16x4_t a) a → Vn.4H

uint16x8_t vclzq_u16
CLZ Vd.8H,Vn.8H Vd.8H ARMv7, ARMv8
(uint16x8_t a) a → Vn.8H

uint32x2_t vclz_u32
CLZ Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(uint32x2_t a) a → Vn.2S

uint32x4_t vclzq_u32
CLZ Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(uint32x4_t a) a → Vn.4S

int8x8_t vcnt_s8
CNT Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(int8x8_t a) a → Vn.8B

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int8x16_t vcntq_s8
CNT Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(int8x16_t a) a → Vn.16B

uint8x8_t vcnt_u8
CNT Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(uint8x8_t a) a → Vn.8B

uint8x16_t vcntq_u8
CNT Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(uint8x16_t a) a → Vn.16B

poly8x8_t vcnt_p8
CNT Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(poly8x8_t a) a → Vn.8B

poly8x16_t vcntq_p8
CNT Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(poly8x16_t a) a → Vn.16B

uint32x2_t vrecpe_u32
URECPE Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(uint32x2_t a) a → Vn.2S

uint32x4_t vrecpeq_u32
URECPE Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(uint32x4_t a) a → Vn.4S

float32x2_t vrecpe_f32
FRECPE Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(float32x2_t a) a → Vn.2S

float32x4_t vrecpeq_f32
FRECPE Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(float32x4_t a) a → Vn.4S

float64x1_t vrecpe_f64
FRECPE Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

float64x2_t vrecpeq_f64
FRECPE Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

float32_t vrecpes_f32
FRECPE Sd,Sn Sd ARMv8(AArch64)
(float32_t a) a → Sn

float64_t vrecped_f64
FRECPE Dd,Dn Dd ARMv8(AArch64)
(float64_t a) a → Dn

float32x2_t vrecps_f32
(float32x2_t a, a → Vn.2S FRECPS Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

float32x4_t vrecpsq_f32
(float32x4_t a, a → Vn.4S FRECPS Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

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float64x1_t vrecps_f64
(float64x1_t a, a → Dn FRECPS Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

float64x2_t vrecpsq_f64
(float64x2_t a, a → Vn.2D FRECPS Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

float32_t vrecpss_f32
(float32_t a, a → Sn FRECPS Sd,Sn,Sm Sd ARMv8(AArch64)
float32_t b) b → Sm

float64_t vrecpsd_f64
(float64_t a, a → Dn FRECPS Dd,Dn,Dm Dd ARMv8(AArch64)
float64_t b) b → Dm

float32x2_t vsqrt_f32
FSQRT Vd.2S,Vn.2S Vd.2S ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

float32x4_t vsqrtq_f32
FSQRT Vd.4S,Vn.4S Vd.4S ARMv8(AArch64)
(float32x4_t a) a → Vn.4S

float64x1_t vsqrt_f64
FSQRT Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

float64x2_t vsqrtq_f64
FSQRT Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

uint32x2_t vrsqrte_u32
URSQRTE Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(uint32x2_t a) a → Vn.2S

uint32x4_t vrsqrteq_u32
URSQRTE Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(uint32x4_t a) a → Vn.4S

float32x2_t vrsqrte_f32
FRSQRTE Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(float32x2_t a) a → Vn.2S

float32x4_t vrsqrteq_f32
FRSQRTE Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(float32x4_t a) a → Vn.4S

float64x1_t vrsqrte_f64
FRSQRTE Dd,Dn Dd ARMv8(AArch64)
(float64x1_t a) a → Dn

float64x2_t vrsqrteq_f64
FRSQRTE Vd.2D,Vn.2D Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

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float32_t vrsqrtes_f32
FRSQRTE Sd,Sn Sd ARMv8(AArch64)
(float32_t a) a → Sn

float64_t vrsqrted_f64
FRSQRTE Dd,Dn Dd ARMv8(AArch64)
(float64_t a) a → Dn

float32x2_t vrsqrts_f32
(float32x2_t a, a → Vn.2S FRSQRTS Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

float32x4_t vrsqrtsq_f32
(float32x4_t a, a → Vn.4S FRSQRTS Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv7, ARMv8
float32x4_t b) b → Vm.4S

float64x1_t vrsqrts_f64
(float64x1_t a, a → Dn FRSQRTS Dd,Dn,Dm Dd ARMv8(AArch64)
float64x1_t b) b → Dm

float64x2_t vrsqrtsq_f64
(float64x2_t a, a → Vn.2D FRSQRTS Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

float32_t vrsqrtss_f32
(float32_t a, a → Sn FRSQRTS Sd,Sn,Sm Sd ARMv8(AArch64)
float32_t b) b → Sm

float64_t vrsqrtsd_f64
(float64_t a, a → Dn FRSQRTS Dd,Dn,Dm Dd ARMv8(AArch64)
float64_t b) b → Dm

int8x8_t vmvn_s8
MVN Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(int8x8_t a) a → Vn.8B

int8x16_t vmvnq_s8
MVN Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(int8x16_t a) a → Vn.16B

int16x4_t vmvn_s16
MVN Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(int16x4_t a) a → Vn.8B

int16x8_t vmvnq_s16
MVN Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(int16x8_t a) a → Vn.16B

int32x2_t vmvn_s32
MVN Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(int32x2_t a) a → Vn.8B

int32x4_t vmvnq_s32
MVN Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(int32x4_t a) a → Vn.16B

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uint8x8_t vmvn_u8
MVN Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(uint8x8_t a) a → Vn.8B

uint8x16_t vmvnq_u8
MVN Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(uint8x16_t a) a → Vn.16B

uint16x4_t vmvn_u16
MVN Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(uint16x4_t a) a → Vn.8B

uint16x8_t vmvnq_u16
MVN Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(uint16x8_t a) a → Vn.16B

uint32x2_t vmvn_u32
MVN Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(uint32x2_t a) a → Vn.8B

uint32x4_t vmvnq_u32
MVN Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(uint32x4_t a) a → Vn.16B

poly8x8_t vmvn_p8
MVN Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(poly8x8_t a) a → Vn.8B

poly8x16_t vmvnq_p8
MVN Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(poly8x16_t a) a → Vn.16B

int8x8_t vand_s8
(int8x8_t a, a → Vn.8B AND Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int8x16_t vandq_s8
(int8x16_t a, a → Vn.16B AND Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vand_s16
(int16x4_t a, a → Vn.8B AND Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int16x4_t b) b → Vm.8B

int16x8_t vandq_s16
(int16x8_t a, a → Vn.16B AND Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int16x8_t b) b → Vm.16B

int32x2_t vand_s32
(int32x2_t a, a → Vn.8B AND Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int32x2_t b) b → Vm.8B

int32x4_t vandq_s32
(int32x4_t a, a → Vn.16B AND Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int32x4_t b) b → Vm.16B

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int64x1_t vand_s64
(int64x1_t a, a → Dn AND Dd,Dn,Dm Dd ARMv7, ARMv8
int64x1_t b) b → Dm

int64x2_t vandq_s64
(int64x2_t a, a → Vn.16B AND Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int64x2_t b) b → Vm.16B

uint8x8_t vand_u8
(uint8x8_t a, a → Vn.8B AND Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vandq_u8
(uint8x16_t a, a → Vn.16B AND Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vand_u16
(uint16x4_t a, a → Vn.8B AND Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint16x4_t b) b → Vm.8B

uint16x8_t vandq_u16
(uint16x8_t a, a → Vn.16B AND Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint16x8_t b) b → Vm.16B

uint32x2_t vand_u32
(uint32x2_t a, a → Vn.8B AND Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint32x2_t b) b → Vm.8B

uint32x4_t vandq_u32
(uint32x4_t a, a → Vn.16B AND Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint32x4_t b) b → Vm.16B

uint64x1_t vand_u64
(uint64x1_t a, a → Vn.8B AND Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint64x1_t b) b → Vm.8B

uint64x2_t vandq_u64
(uint64x2_t a, a → Vn.16B AND Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint64x2_t b) b → Vm.16B

int8x8_t vorr_s8
(int8x8_t a, a → Vn.8B ORR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int8x16_t vorrq_s8
(int8x16_t a, a → Vn.16B ORR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 155 of 348
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int16x4_t vorr_s16
(int16x4_t a, a → Vn.8B ORR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int16x4_t b) b → Vm.8B

int16x8_t vorrq_s16
(int16x8_t a, a → Vn.16B ORR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int16x8_t b) b → Vm.16B

int32x2_t vorr_s32
(int32x2_t a, a → Vn.8B ORR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int32x2_t b) b → Vm.8B

int32x4_t vorrq_s32
(int32x4_t a, a → Vn.16B ORR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int32x4_t b) b → Vm.16B

int64x1_t vorr_s64
(int64x1_t a, a → Vn.8B ORR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int64x1_t b) b → Vm.8B

int64x2_t vorrq_s64
(int64x2_t a, a → Vn.16B ORR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int64x2_t b) b → Vm.16B

uint8x8_t vorr_u8
(uint8x8_t a, a → Vn.8B ORR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vorrq_u8
(uint8x16_t a, a → Vn.16B ORR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vorr_u16
(uint16x4_t a, a → Vn.8B ORR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint16x4_t b) b → Vm.8B

uint16x8_t vorrq_u16
(uint16x8_t a, a → Vn.16B ORR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint16x8_t b) b → Vm.16B

uint32x2_t vorr_u32
(uint32x2_t a, a → Vn.8B ORR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint32x2_t b) b → Vm.8B

uint32x4_t vorrq_u32
(uint32x4_t a, a → Vn.16B ORR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint32x4_t b) b → Vm.16B

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uint64x1_t vorr_u64
(uint64x1_t a, a → Vn.8B ORR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint64x1_t b) b → Vm.8B

uint64x2_t vorrq_u64
(uint64x2_t a, a → Vn.16B ORR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint64x2_t b) b → Vm.16B

int8x8_t veor_s8
(int8x8_t a, a → Vn.8B EOR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int8x16_t veorq_s8
(int8x16_t a, a → Vn.16B EOR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t veor_s16
(int16x4_t a, a → Vn.8B EOR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int16x4_t b) b → Vm.8B

int16x8_t veorq_s16
(int16x8_t a, a → Vn.16B EOR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int16x8_t b) b → Vm.16B

int32x2_t veor_s32
(int32x2_t a, a → Vn.8B EOR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int32x2_t b) b → Vm.8B

int32x4_t veorq_s32
(int32x4_t a, a → Vn.16B EOR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int32x4_t b) b → Vm.16B

int64x1_t veor_s64
(int64x1_t a, a → Vn.8B EOR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int64x1_t b) b → Vm.8B

int64x2_t veorq_s64
(int64x2_t a, a → Vn.16B EOR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int64x2_t b) b → Vm.16B

uint8x8_t veor_u8
(uint8x8_t a, a → Vn.8B EOR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t veorq_u8
(uint8x16_t a, a → Vn.16B EOR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

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uint16x4_t veor_u16
(uint16x4_t a, a → Vn.8B EOR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint16x4_t b) b → Vm.8B

uint16x8_t veorq_u16
(uint16x8_t a, a → Vn.16B EOR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint16x8_t b) b → Vm.16B

uint32x2_t veor_u32
(uint32x2_t a, a → Vn.8B EOR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint32x2_t b) b → Vm.8B

uint32x4_t veorq_u32
(uint32x4_t a, a → Vn.16B EOR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint32x4_t b) b → Vm.16B

uint64x1_t veor_u64
(uint64x1_t a, a → Vn.8B EOR Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint64x1_t b) b → Vm.8B

uint64x2_t veorq_u64
(uint64x2_t a, a → Vn.16B EOR Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint64x2_t b) b → Vm.16B

int8x8_t vbic_s8
(int8x8_t a, a → Vn.8B BIC Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int8x16_t vbicq_s8
(int8x16_t a, a → Vn.16B BIC Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

int16x4_t vbic_s16
(int16x4_t a, a → Vn.8B BIC Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int16x4_t b) b → Vm.8B

int16x8_t vbicq_s16
(int16x8_t a, a → Vn.16B BIC Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int16x8_t b) b → Vm.16B

int32x2_t vbic_s32
(int32x2_t a, a → Vn.8B BIC Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int32x2_t b) b → Vm.8B

int32x4_t vbicq_s32
(int32x4_t a, a → Vn.16B BIC Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int32x4_t b) b → Vm.16B

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int64x1_t vbic_s64
(int64x1_t a, a → Vn.8B BIC Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int64x1_t b) b → Vm.8B

int64x2_t vbicq_s64
(int64x2_t a, a → Vn.16B BIC Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int64x2_t b) b → Vm.16B

uint8x8_t vbic_u8
(uint8x8_t a, a → Vn.8B BIC Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vbicq_u8
(uint8x16_t a, a → Vn.16B BIC Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vbic_u16
(uint16x4_t a, a → Vn.8B BIC Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint16x4_t b) b → Vm.8B

uint16x8_t vbicq_u16
(uint16x8_t a, a → Vn.16B BIC Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint16x8_t b) b → Vm.16B

uint32x2_t vbic_u32
(uint32x2_t a, a → Vn.8B BIC Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint32x2_t b) b → Vm.8B

uint32x4_t vbicq_u32
(uint32x4_t a, a → Vn.16B BIC Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint32x4_t b) b → Vm.16B

uint64x1_t vbic_u64
(uint64x1_t a, a → Vn.8B BIC Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint64x1_t b) b → Vm.8B

uint64x2_t vbicq_u64
(uint64x2_t a, a → Vn.16B BIC Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint64x2_t b) b → Vm.16B

int8x8_t vorn_s8
(int8x8_t a, a → Vn.8B ORN Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int8x16_t vornq_s8
(int8x16_t a, a → Vn.16B ORN Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b) b → Vm.16B

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int16x4_t vorn_s16
(int16x4_t a, a → Vn.8B ORN Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int16x4_t b) b → Vm.8B

int16x8_t vornq_s16
(int16x8_t a, a → Vn.16B ORN Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int16x8_t b) b → Vm.16B

int32x2_t vorn_s32
(int32x2_t a, a → Vn.8B ORN Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int32x2_t b) b → Vm.8B

int32x4_t vornq_s32
(int32x4_t a, a → Vn.16B ORN Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int32x4_t b) b → Vm.16B

int64x1_t vorn_s64
(int64x1_t a, a → Vn.8B ORN Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int64x1_t b) b → Vm.8B

int64x2_t vornq_s64
(int64x2_t a, a → Vn.16B ORN Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int64x2_t b) b → Vm.16B

uint8x8_t vorn_u8
(uint8x8_t a, a → Vn.8B ORN Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint8x16_t vornq_u8
(uint8x16_t a, a → Vn.16B ORN Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b) b → Vm.16B

uint16x4_t vorn_u16
(uint16x4_t a, a → Vn.8B ORN Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint16x4_t b) b → Vm.8B

uint16x8_t vornq_u16
(uint16x8_t a, a → Vn.16B ORN Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint16x8_t b) b → Vm.16B

uint32x2_t vorn_u32
(uint32x2_t a, a → Vn.8B ORN Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint32x2_t b) b → Vm.8B

uint32x4_t vornq_u32
(uint32x4_t a, a → Vn.16B ORN Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint32x4_t b) b → Vm.16B

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uint64x1_t vorn_u64
(uint64x1_t a, a → Vn.8B ORN Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint64x1_t b) b → Vm.8B

uint64x2_t vornq_u64
(uint64x2_t a, a → Vn.16B ORN Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint64x2_t b) b → Vm.16B

int8x8_t vbsl_s8
(uint8x8_t a, a → Vd.8B
BSL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b, b → Vn.8B
int8x8_t c) c → Vm.8B

int8x16_t vbslq_s8
(uint8x16_t a, a → Vd.16B
BSL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int8x16_t b, b → Vn.16B
int8x16_t c) c → Vm.16B

int16x4_t vbsl_s16
(uint16x4_t a, a → Vd.8B
BSL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int16x4_t b, b → Vn.8B
int16x4_t c) c → Vm.8B

int16x8_t vbslq_s16
(uint16x8_t a, a → Vd.16B
BSL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int16x8_t b, b → Vn.16B
int16x8_t c) c → Vm.16B

int32x2_t vbsl_s32
(uint32x2_t a, a → Vd.8B
BSL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int32x2_t b, b → Vn.8B
int32x2_t c) c → Vm.8B

int32x4_t vbslq_s32
(uint32x4_t a, a → Vd.16B
BSL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int32x4_t b, b → Vn.16B
int32x4_t c) c → Vm.16B

int64x1_t vbsl_s64
(uint64x1_t a, a → Vd.8B
BSL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int64x1_t b, b → Vn.8B
int64x1_t c) c → Vm.8B

int64x2_t vbslq_s64
(uint64x2_t a, a → Vd.16B
BSL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
int64x2_t b, b → Vn.16B
int64x2_t c) c → Vm.16B

uint8x8_t vbsl_u8
(uint8x8_t a, a → Vd.8B
BSL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b, b → Vn.8B
uint8x8_t c) c → Vm.8B

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uint8x16_t vbslq_u8
(uint8x16_t a, a → Vd.16B
BSL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint8x16_t b, b → Vn.16B
uint8x16_t c) c → Vm.16B

uint16x4_t vbsl_u16
(uint16x4_t a, a → Vd.8B
BSL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint16x4_t b, b → Vn.8B
uint16x4_t c) c → Vm.8B

uint16x8_t vbslq_u16
(uint16x8_t a, a → Vd.16B
BSL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint16x8_t b, b → Vn.16B
uint16x8_t c) c → Vm.16B

uint32x2_t vbsl_u32
(uint32x2_t a, a → Vd.8B
BSL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint32x2_t b, b → Vn.8B
uint32x2_t c) c → Vm.8B

uint32x4_t vbslq_u32
(uint32x4_t a, a → Vd.16B
BSL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint32x4_t b, b → Vn.16B
uint32x4_t c) c → Vm.16B

uint64x1_t vbsl_u64
(uint64x1_t a, a → Vd.8B
BSL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint64x1_t b, b → Vn.8B
uint64x1_t c) c → Vm.8B

uint64x2_t vbslq_u64
(uint64x2_t a, a → Vd.16B
BSL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
uint64x2_t b, b → Vn.16B
uint64x2_t c) c → Vm.16B

poly64x1_t vbsl_p64
(poly64x1_t a, a → Vd.8B
BSL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8
poly64x1_t b, b → Vn.8B
poly64x1_t c) c → Vm.8B

poly64x2_t vbslq_p64
(poly64x2_t a, a → Vd.16B
BSL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8
poly64x2_t b, b → Vn.16B
poly64x2_t c) c → Vm.16B

float32x2_t vbsl_f32
(uint32x2_t a, a → Vd.8B
BSL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
float32x2_t b, b → Vn.8B
float32x2_t c) c → Vm.8B

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float32x4_t vbslq_f32
(uint32x4_t a, a → Vd.16B
BSL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
float32x4_t b, b → Vn.16B
float32x4_t c) c → Vm.16B

poly8x8_t vbsl_p8
(uint8x8_t a, a → Vd.8B
BSL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
poly8x8_t b, b → Vn.8B
poly8x8_t c) c → Vm.8B

poly8x16_t vbslq_p8
(uint8x16_t a, a → Vd.16B
BSL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
poly8x16_t b, b → Vn.16B
poly8x16_t c) c → Vm.16B

poly16x4_t vbsl_p16
(uint16x4_t a, a → Vd.8B
BSL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
poly16x4_t b, b → Vn.8B
poly16x4_t c) c → Vm.8B

poly16x8_t vbslq_p16
(uint16x8_t a, a → Vd.16B
BSL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv7, ARMv8
poly16x8_t b, b → Vn.16B
poly16x8_t c) c → Vm.16B

float64x1_t vbsl_f64
(uint64x1_t a, a → Vd.8B
BSL Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
float64x1_t b, b → Vn.8B
float64x1_t c) c → Vm.8B

float64x2_t vbslq_f64
(uint64x2_t a, a → Vd.16B
BSL Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
float64x2_t b, b → Vn.16B
float64x2_t c) c → Vm.16B

int8x8_t vcopy_lane_s8
(int8x8_t a, a → Vd.8B
const int lane1, 0 <= lane1 <= 7 INS Vd.B[lane1],Vn.B[lane2] Vd.8B ARMv8(AArch64)
int8x8_t b, b → Vn.8B
const int lane2) 0 <= lane2 <= 7

int8x16_t vcopyq_lane_s8
(int8x16_t a, a → Vd.16B
const int lane1, 0 <= lane1 <= 15 INS Vd.B[lane1],Vn.B[lane2] Vd.16B ARMv8(AArch64)
int8x8_t b, b → Vn.8B
const int lane2) 0 <= lane2 <= 7

int16x4_t vcopy_lane_s16
(int16x4_t a, a → Vd.4H
const int lane1, 0 <= lane1 <= 3 INS Vd.H[lane1],Vn.H[lane2] Vd.4H ARMv8(AArch64)
int16x4_t b, b → Vn.4H
const int lane2) 0 <= lane2 <= 3

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int16x8_t vcopyq_lane_s16
(int16x8_t a, a → Vd.8H
const int lane1, 0 <= lane1 <= 7 INS Vd.H[lane1],Vn.H[lane2] Vd.8H ARMv8(AArch64)
int16x4_t b, b → Vn.4H
const int lane2) 0 <= lane2 <= 3

int32x2_t vcopy_lane_s32
(int32x2_t a, a → Vd.2S
const int lane1, 0 <= lane1 <= 1 INS Vd.S[lane1],Vn.S[lane2] Vd.2S ARMv8(AArch64)
int32x2_t b, b → Vn.2S
const int lane2) 0 <= lane2 <= 1

int32x4_t vcopyq_lane_s32
(int32x4_t a, a → Vd.4S
const int lane1, 0 <= lane1 <= 3 INS Vd.S[lane1],Vn.S[lane2] Vd.4S ARMv8(AArch64)
int32x2_t b, b → Vn.2S
const int lane2) 0 <= lane2 <= 1

int64x1_t vcopy_lane_s64
(int64x1_t a, a → UNUSED
const int lane1, lane1 == 0 DUP Dd,Vn.D[lane2] Dd ARMv8(AArch64)
int64x1_t b, b → Vn.1D
const int lane2) lane2 == 0

int64x2_t vcopyq_lane_s64
(int64x2_t a, a → Vd.2D
const int lane1, 0 <= lane1 <= 1 INS Vd.D[lane1],Vn.D[lane2] Vd.2D ARMv8(AArch64)
int64x1_t b, b → Vn.1D
const int lane2) lane2 == 0

uint8x8_t vcopy_lane_u8
(uint8x8_t a, a → Vd.8B
const int lane1, 0 <= lane1 <= 7 INS Vd.B[lane1],Vn.B[lane2] Vd.8B ARMv8(AArch64)
uint8x8_t b, b → Vn.8B
const int lane2) 0 <= lane2 <= 7

uint8x16_t vcopyq_lane_u8
(uint8x16_t a, a → Vd.16B
const int lane1, 0 <= lane1 <= 15 INS Vd.B[lane1],Vn.B[lane2] Vd.16B ARMv8(AArch64)
uint8x8_t b, b → Vn.8B
const int lane2) 0 <= lane2 <= 7

uint16x4_t vcopy_lane_u16
(uint16x4_t a, a → Vd.4H
const int lane1, 0 <= lane1 <= 3 INS Vd.H[lane1],Vn.H[lane2] Vd.4H ARMv8(AArch64)
uint16x4_t b, b → Vn.4H
const int lane2) 0 <= lane2 <= 3

uint16x8_t vcopyq_lane_u16
(uint16x8_t a, a → Vd.8H
const int lane1, 0 <= lane1 <= 7 INS Vd.H[lane1],Vn.H[lane2] Vd.8H ARMv8(AArch64)
uint16x4_t b, b → Vn.4H
const int lane2) 0 <= lane2 <= 3

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 164 of 348
Non-Confidential
uint32x2_t vcopy_lane_u32
(uint32x2_t a, a → Vd.2S
const int lane1, 0 <= lane1 <= 1 INS Vd.S[lane1],Vn.S[lane2] Vd.2S ARMv8(AArch64)
uint32x2_t b, b → Vn.2S
const int lane2) 0 <= lane2 <= 1

uint32x4_t vcopyq_lane_u32
(uint32x4_t a, a → Vd.4S
const int lane1, 0 <= lane1 <= 3 INS Vd.S[lane1],Vn.S[lane2] Vd.4S ARMv8(AArch64)
uint32x2_t b, b → Vn.2S
const int lane2) 0 <= lane2 <= 1

uint64x1_t vcopy_lane_u64
(uint64x1_t a, a → UNUSED
const int lane1, lane1 == 0 DUP Dd,Vn.D[lane2] Dd ARMv8(AArch64)
uint64x1_t b, b → Vn.1D
const int lane2) lane2 == 0

uint64x2_t vcopyq_lane_u64
(uint64x2_t a, a → Vd.2D
const int lane1, 0 <= lane1 <= 1 INS Vd.D[lane1],Vn.D[lane2] Vd.2D ARMv8(AArch64)
uint64x1_t b, b → Vn.1D
const int lane2) lane2 == 0

poly64x1_t vcopy_lane_p64
(poly64x1_t a, a → UNUSED
const int lane1, lane1 == 0 DUP Dd,Vn.D[lane2] Dd ARMv8
poly64x1_t b, b → Vn.1D
const int lane2) lane2 == 0

poly64x2_t vcopyq_lane_p64
(poly64x2_t a, a → Vd.2D
const int lane1, 0 <= lane1 <= 1 INS Vd.D[lane1],Vn.D[lane2] Vd.2D ARMv8
poly64x1_t b, b → Vn.1D
const int lane2) lane2 == 0

float32x2_t vcopy_lane_f32
(float32x2_t a, a → Vd.2S
const int lane1, 0 <= lane1 <= 1 INS Vd.S[lane1],Vn.S[lane2] Vd.2S ARMv8(AArch64)
float32x2_t b, b → Vn.2S
const int lane2) 0 <= lane2 <= 1

float32x4_t vcopyq_lane_f32
(float32x4_t a, a → Vd.4S
const int lane1, 0 <= lane1 <= 3 INS Vd.S[lane1],Vn.S[lane2] Vd.4S ARMv8(AArch64)
float32x2_t b, b → Vn.2S
const int lane2) 0 <= lane2 <= 1

float64x1_t vcopy_lane_f64
(float64x1_t a, a → UNUSED
const int lane1, lane1 == 0 DUP Dd,Vn.D[lane2] Dd ARMv8(AArch64)
float64x1_t b, b → Vn.1D
const int lane2) lane2 == 0

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 165 of 348
Non-Confidential
float64x2_t vcopyq_lane_f64
(float64x2_t a, a → Vd.2D
const int lane1, 0 <= lane1 <= 1 INS Vd.D[lane1],Vn.D[lane2] Vd.2D ARMv8(AArch64)
float64x1_t b, b → Vn.1D
const int lane2) lane2 == 0

poly8x8_t vcopy_lane_p8
(poly8x8_t a, a → Vd.8B
const int lane1, 0 <= lane1 <= 7 INS Vd.B[lane1],Vn.B[lane2] Vd.8B ARMv8(AArch64)
poly8x8_t b, b → Vn.8B
const int lane2) 0 <= lane2 <= 7

poly8x16_t vcopyq_lane_p8
(poly8x16_t a, a → Vd.16B
const int lane1, 0 <= lane1 <= 15 INS Vd.B[lane1],Vn.B[lane2] Vd.16B ARMv8(AArch64)
poly8x8_t b, b → Vn.8B
const int lane2) 0 <= lane2 <= 7

poly16x4_t vcopy_lane_p16
(poly16x4_t a, a → Vd.4H
const int lane1, 0 <= lane1 <= 3 INS Vd.H[lane1],Vn.H[lane2] Vd.4H ARMv8(AArch64)
poly16x4_t b, b → Vn.4H
const int lane2) 0 <= lane2 <= 3

poly16x8_t vcopyq_lane_p16
(poly16x8_t a, a → Vd.8H
const int lane1, 0 <= lane1 <= 7 INS Vd.H[lane1],Vn.H[lane2] Vd.8H ARMv8(AArch64)
poly16x4_t b, b → Vn.4H
const int lane2) 0 <= lane2 <= 3

int8x8_t vcopy_laneq_s8
(int8x8_t a, a → Vd.8B
const int lane1, 0 <= lane1 <= 7 INS Vd.B[lane1],Vn.B[lane2] Vd.8B ARMv8(AArch64)
int8x16_t b, b → Vn.16B
const int lane2) 0 <= lane2 <= 15

int8x16_t vcopyq_laneq_s8
(int8x16_t a, a → Vd.16B
const int lane1, 0 <= lane1 <= 15 INS Vd.B[lane1],Vn.B[lane2] Vd.16B ARMv8(AArch64)
int8x16_t b, b → Vn.16B
const int lane2) 0 <= lane2 <= 15

int16x4_t vcopy_laneq_s16
(int16x4_t a, a → Vd.4H
const int lane1, 0 <= lane1 <= 3 INS Vd.H[lane1],Vn.H[lane2] Vd.4H ARMv8(AArch64)
int16x8_t b, b → Vn.8H
const int lane2) 0 <= lane2 <= 7

int16x8_t vcopyq_laneq_s16
(int16x8_t a, a → Vd.8H
const int lane1, 0 <= lane1 <= 7 INS Vd.H[lane1],Vn.H[lane2] Vd.8H ARMv8(AArch64)
int16x8_t b, b → Vn.8H
const int lane2) 0 <= lane2 <= 7

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 166 of 348
Non-Confidential
int32x2_t vcopy_laneq_s32
(int32x2_t a, a → Vd.2S
const int lane1, 0 <= lane1 <= 1 INS Vd.S[lane1],Vn.S[lane2] Vd.2S ARMv8(AArch64)
int32x4_t b, b → Vn.4S
const int lane2) 0 <= lane2 <= 3

int32x4_t vcopyq_laneq_s32
(int32x4_t a, a → Vd.4S
const int lane1, 0 <= lane1 <= 3 INS Vd.S[lane1],Vn.S[lane2] Vd.4S ARMv8(AArch64)
int32x4_t b, b → Vn.4S
const int lane2) 0 <= lane2 <= 3

int64x1_t vcopy_laneq_s64
(int64x1_t a, a → UNUSED
const int lane1, lane1 == 0 DUP Dd,Vn.D[lane2] Dd ARMv8(AArch64)
int64x2_t b, b → Vn.2D
const int lane2) 0 <= lane2 <= 1

int64x2_t vcopyq_laneq_s64
(int64x2_t a, a → Vd.2D
const int lane1, 0 <= lane1 <= 1 INS Vd.D[lane1],Vn.D[lane2] Vd.2D ARMv8(AArch64)
int64x2_t b, b → Vn.2D
const int lane2) 0 <= lane2 <= 1

uint8x8_t vcopy_laneq_u8
(uint8x8_t a, a → Vd.8B
const int lane1, 0 <= lane1 <= 7 INS Vd.B[lane1],Vn.B[lane2] Vd.8B ARMv8(AArch64)
uint8x16_t b, b → Vn.16B
const int lane2) 0 <= lane2 <= 15

uint8x16_t vcopyq_laneq_u8
(uint8x16_t a, a → Vd.16B
const int lane1, 0 <= lane1 <= 15 INS Vd.B[lane1],Vn.B[lane2] Vd.16B ARMv8(AArch64)
uint8x16_t b, b → Vn.16B
const int lane2) 0 <= lane2 <= 15

uint16x4_t vcopy_laneq_u16
(uint16x4_t a, a → Vd.4H
const int lane1, 0 <= lane1 <= 3 INS Vd.H[lane1],Vn.H[lane2] Vd.4H ARMv8(AArch64)
uint16x8_t b, b → Vn.8H
const int lane2) 0 <= lane2 <= 7

uint16x8_t vcopyq_laneq_u16
(uint16x8_t a, a → Vd.8H
const int lane1, 0 <= lane1 <= 7 INS Vd.H[lane1],Vn.H[lane2] Vd.8H ARMv8(AArch64)
uint16x8_t b, b → Vn.8H
const int lane2) 0 <= lane2 <= 7

uint32x2_t vcopy_laneq_u32
(uint32x2_t a, a → Vd.2S
const int lane1, 0 <= lane1 <= 1 INS Vd.S[lane1],Vn.S[lane2] Vd.2S ARMv8(AArch64)
uint32x4_t b, b → Vn.4S
const int lane2) 0 <= lane2 <= 3

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uint32x4_t vcopyq_laneq_u32
(uint32x4_t a, a → Vd.4S
const int lane1, 0 <= lane1 <= 3 INS Vd.S[lane1],Vn.S[lane2] Vd.4S ARMv8(AArch64)
uint32x4_t b, b → Vn.4S
const int lane2) 0 <= lane2 <= 3

uint64x1_t vcopy_laneq_u64
(uint64x1_t a, a → UNUSED
const int lane1, lane1 == 0 DUP Dd,Vn.D[lane2] Dd ARMv8(AArch64)
uint64x2_t b, b → Vn.2D
const int lane2) 0 <= lane2 <= 1

uint64x2_t vcopyq_laneq_u64
(uint64x2_t a, a → Vd.2D
const int lane1, 0 <= lane1 <= 1 INS Vd.D[lane1],Vn.D[lane2] Vd.2D ARMv8(AArch64)
uint64x2_t b, b → Vn.2D
const int lane2) 0 <= lane2 <= 1

poly64x1_t vcopy_laneq_p64
(poly64x1_t a, a → UNUSED
const int lane1, lane1 == 0 DUP Dd,Vn.D[lane2] Dd ARMv8
poly64x2_t b, b → Vn.2D
const int lane2) 0 <= lane2 <= 1

poly64x2_t vcopyq_laneq_p64
(poly64x2_t a, a → Vd.2D
const int lane1, 0 <= lane1 <= 1 INS Vd.D[lane1],Vn.D[lane2] Vd.2D ARMv8
poly64x2_t b, b → Vn.2D
const int lane2) 0 <= lane2 <= 1

float32x2_t vcopy_laneq_f32
(float32x2_t a, a → Vd.2S
const int lane1, 0 <= lane1 <= 1 INS Vd.S[lane1],Vn.S[lane2] Vd.2S ARMv8(AArch64)
float32x4_t b, b → Vn.4S
const int lane2) 0 <= lane2 <= 3

float32x4_t vcopyq_laneq_f32
(float32x4_t a, a → Vd.4S
const int lane1, 0 <= lane1 <= 3 INS Vd.S[lane1],Vn.S[lane2] Vd.4S ARMv8(AArch64)
float32x4_t b, b → Vn.4S
const int lane2) 0 <= lane2 <= 3

float64x1_t vcopy_laneq_f64
(float64x1_t a, a → UNUSED
const int lane1, lane1 == 0 DUP Dd,Vn.D[lane2] Dd ARMv8(AArch64)
float64x2_t b, b → Vn.2D
const int lane2) 0 <= lane2 <= 1

float64x2_t vcopyq_laneq_f64
(float64x2_t a, a → Vd.2D
const int lane1, 0 <= lane1 <= 1 INS Vd.D[lane1],Vn.D[lane2] Vd.2D ARMv8(AArch64)
float64x2_t b, b → Vn.2D
const int lane2) 0 <= lane2 <= 1

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 168 of 348
Non-Confidential
poly8x8_t vcopy_laneq_p8
(poly8x8_t a, a → Vd.8B
const int lane1, 0 <= lane1 <= 7 INS Vd.B[lane1],Vn.B[lane2] Vd.8B ARMv8(AArch64)
poly8x16_t b, b → Vn.16B
const int lane2) 0 <= lane2 <= 15

poly8x16_t vcopyq_laneq_p8
(poly8x16_t a, a → Vd.16B
const int lane1, 0 <= lane1 <= 15 INS Vd.B[lane1],Vn.B[lane2] Vd.16B ARMv8(AArch64)
poly8x16_t b, b → Vn.16B
const int lane2) 0 <= lane2 <= 15

poly16x4_t vcopy_laneq_p16
(poly16x4_t a, a → Vd.4H
const int lane1, 0 <= lane1 <= 3 INS Vd.H[lane1],Vn.H[lane2] Vd.4H ARMv8(AArch64)
poly16x8_t b, b → Vn.8H
const int lane2) 0 <= lane2 <= 7

poly16x8_t vcopyq_laneq_p16
(poly16x8_t a, a → Vd.8H
const int lane1, 0 <= lane1 <= 7 INS Vd.H[lane1],Vn.H[lane2] Vd.8H ARMv8(AArch64)
poly16x8_t b, b → Vn.8H
const int lane2) 0 <= lane2 <= 7

int8x8_t vrbit_s8
RBIT Vd.8B,Vn.8B Vd.8B ARMv8(AArch64)
(int8x8_t a) a → Vn.8B

int8x16_t vrbitq_s8
RBIT Vd.16B,Vn.16B Vd.16B ARMv8(AArch64)
(int8x16_t a) a → Vn.16B

uint8x8_t vrbit_u8
RBIT Vd.8B,Vn.8B Vd.8B ARMv8(AArch64)
(uint8x8_t a) a → Vn.8B

uint8x16_t vrbitq_u8
RBIT Vd.16B,Vn.16B Vd.16B ARMv8(AArch64)
(uint8x16_t a) a → Vn.16B

poly8x8_t vrbit_p8
RBIT Vd.8B,Vn.8B Vd.8B ARMv8(AArch64)
(poly8x8_t a) a → Vn.8B

poly8x16_t vrbitq_p8
RBIT Vd.16B,Vn.16B Vd.16B ARMv8(AArch64)
(poly8x16_t a) a → Vn.16B

int8x8_t vcreate_s8
INS Vd.D[0],Xn Vd.8B ARMv7, ARMv8
(uint64_t a) a → Xn

int16x4_t vcreate_s16
INS Vd.D[0],Xn Vd.4H ARMv7, ARMv8
(uint64_t a) a → Xn

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int32x2_t vcreate_s32
INS Vd.D[0],Xn Vd.2S ARMv7, ARMv8
(uint64_t a) a → Xn

int64x1_t vcreate_s64
INS Vd.D[0],Xn Vd.1D ARMv7, ARMv8
(uint64_t a) a → Xn

uint8x8_t vcreate_u8
INS Vd.D[0],Xn Vd.8B ARMv7, ARMv8
(uint64_t a) a → Xn

uint16x4_t vcreate_u16
INS Vd.D[0],Xn Vd.4H ARMv7, ARMv8
(uint64_t a) a → Xn

uint32x2_t vcreate_u32
INS Vd.D[0],Xn Vd.2S ARMv7, ARMv8
(uint64_t a) a → Xn

uint64x1_t vcreate_u64
INS Vd.D[0],Xn Vd.1D ARMv7, ARMv8
(uint64_t a) a → Xn

poly64x1_t vcreate_p64
INS Vd.D[0],Xn Vd.1D ARMv8
(uint64_t a) a → Xn

float16x4_t vcreate_f16
INS Vd.D[0],Xn Vd.4H ARMv7, ARMv8
(uint64_t a) a → Xn

float32x2_t vcreate_f32
INS Vd.D[0],Xn Vd.2S ARMv7, ARMv8
(uint64_t a) a → Xn

poly8x8_t vcreate_p8
INS Vd.D[0],Xn Vd.8B ARMv7, ARMv8
(uint64_t a) a → Xn

poly16x4_t vcreate_p16
INS Vd.D[0],Xn Vd.4H ARMv7, ARMv8
(uint64_t a) a → Xn

float64x1_t vcreate_f64
INS Vd.D[0],Xn Vd.1D ARMv8(AArch64)
(uint64_t a) a → Xn

int8x8_t vdup_n_s8
DUP Vd.8B,rn Vd.8B ARMv7, ARMv8
(int8_t value) value → rn

int8x16_t vdupq_n_s8
DUP Vd.16B,rn Vd.16B ARMv7, ARMv8
(int8_t value) value → rn

int16x4_t vdup_n_s16
DUP Vd.4H,rn Vd.4H ARMv7, ARMv8
(int16_t value) value → rn

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 170 of 348
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int16x8_t vdupq_n_s16
DUP Vd.8H,rn Vd.8H ARMv7, ARMv8
(int16_t value) value → rn

int32x2_t vdup_n_s32
DUP Vd.2S,rn Vd.2S ARMv7, ARMv8
(int32_t value) value → rn

int32x4_t vdupq_n_s32
DUP Vd.4S,rn Vd.4S ARMv7, ARMv8
(int32_t value) value → rn

int64x1_t vdup_n_s64
INS Dd.D[0],xn Vd.1D ARMv7, ARMv8
(int64_t value) value → rn

int64x2_t vdupq_n_s64
DUP Vd.2D,rn Vd.2D ARMv7, ARMv8
(int64_t value) value → rn

uint8x8_t vdup_n_u8
DUP Vd.8B,rn Vd.8B ARMv7, ARMv8
(uint8_t value) value → rn

uint8x16_t vdupq_n_u8
DUP Vd.16B,rn Vd.16B ARMv7, ARMv8
(uint8_t value) value → rn

uint16x4_t vdup_n_u16
DUP Vd.4H,rn Vd.4H ARMv7, ARMv8
(uint16_t value) value → rn

uint16x8_t vdupq_n_u16
DUP Vd.8H,rn Vd.8H ARMv7, ARMv8
(uint16_t value) value → rn

uint32x2_t vdup_n_u32
DUP Vd.2S,rn Vd.2S ARMv7, ARMv8
(uint32_t value) value → rn

uint32x4_t vdupq_n_u32
DUP Vd.4S,rn Vd.4S ARMv7, ARMv8
(uint32_t value) value → rn

uint64x1_t vdup_n_u64
INS Dd.D[0],xn Vd.1D ARMv7, ARMv8
(uint64_t value) value → rn

uint64x2_t vdupq_n_u64
DUP Vd.2D,rn Vd.2D ARMv7, ARMv8
(uint64_t value) value → rn

poly64x1_t vdup_n_p64
INS Dd.D[0],xn Vd.1D ARMv8
(poly64_t value) value → rn

poly64x2_t vdupq_n_p64
DUP Vd.2D,rn Vd.2D ARMv8
(poly64_t value) value → rn

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float32x2_t vdup_n_f32
DUP Vd.2S,rn Vd.2S ARMv7, ARMv8
(float32_t value) value → rn

float32x4_t vdupq_n_f32
DUP Vd.4S,rn Vd.4S ARMv7, ARMv8
(float32_t value) value → rn

poly8x8_t vdup_n_p8
DUP Vd.8B,rn Vd.8B ARMv7, ARMv8
(poly8_t value) value → rn

poly8x16_t vdupq_n_p8
DUP Vd.16B,rn Vd.16B ARMv7, ARMv8
(poly8_t value) value → rn

poly16x4_t vdup_n_p16
DUP Vd.4H,rn Vd.4H ARMv7, ARMv8
(poly16_t value) value → rn

poly16x8_t vdupq_n_p16
DUP Vd.8H,rn Vd.8H ARMv7, ARMv8
(poly16_t value) value → rn

float64x1_t vdup_n_f64
INS Dd.D[0],xn Vd.1D ARMv8(AArch64)
(float64_t value) value → rn

float64x2_t vdupq_n_f64
DUP Vd.2D,rn Vd.2D ARMv8(AArch64)
(float64_t value) value → rn

int8x8_t vmov_n_s8
DUP Vd.8B,rn Vd.8B ARMv7, ARMv8
(int8_t value) value → rn

int8x16_t vmovq_n_s8
DUP Vd.16B,rn Vd.16B ARMv7, ARMv8
(int8_t value) value → rn

int16x4_t vmov_n_s16
DUP Vd.4H,rn Vd.4H ARMv7, ARMv8
(int16_t value) value → rn

int16x8_t vmovq_n_s16
DUP Vd.8H,rn Vd.8H ARMv7, ARMv8
(int16_t value) value → rn

int32x2_t vmov_n_s32
DUP Vd.2S,rn Vd.2S ARMv7, ARMv8
(int32_t value) value → rn

int32x4_t vmovq_n_s32
DUP Vd.4S,rn Vd.4S ARMv7, ARMv8
(int32_t value) value → rn

int64x1_t vmov_n_s64
DUP Vd.1D,rn Vd.1D ARMv7, ARMv8
(int64_t value) value → rn

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 172 of 348
Non-Confidential
int64x2_t vmovq_n_s64
DUP Vd.2D,rn Vd.2D ARMv7, ARMv8
(int64_t value) value → rn

uint8x8_t vmov_n_u8
DUP Vd.8B,rn Vd.8B ARMv7, ARMv8
(uint8_t value) value → rn

uint8x16_t vmovq_n_u8
DUP Vd.16B,rn Vd.16B ARMv7, ARMv8
(uint8_t value) value → rn

uint16x4_t vmov_n_u16
DUP Vd.4H,rn Vd.4H ARMv7, ARMv8
(uint16_t value) value → rn

uint16x8_t vmovq_n_u16
DUP Vd.8H,rn Vd.8H ARMv7, ARMv8
(uint16_t value) value → rn

uint32x2_t vmov_n_u32
DUP Vd.2S,rn Vd.2S ARMv7, ARMv8
(uint32_t value) value → rn

uint32x4_t vmovq_n_u32
DUP Vd.4S,rn Vd.4S ARMv7, ARMv8
(uint32_t value) value → rn

uint64x1_t vmov_n_u64
DUP Vd.1D,rn Vd.1D ARMv7, ARMv8
(uint64_t value) value → rn

uint64x2_t vmovq_n_u64
DUP Vd.2D,rn Vd.2D ARMv7, ARMv8
(uint64_t value) value → rn

float32x2_t vmov_n_f32
DUP Vd.2S,rn Vd.2S ARMv7, ARMv8
(float32_t value) value → rn

float32x4_t vmovq_n_f32
DUP Vd.4S,rn Vd.4S ARMv7, ARMv8
(float32_t value) value → rn

poly8x8_t vmov_n_p8
DUP Vd.8B,rn Vd.8B ARMv7, ARMv8
(poly8_t value) value → rn

poly8x16_t vmovq_n_p8
DUP Vd.16B,rn Vd.16B ARMv7, ARMv8
(poly8_t value) value → rn

poly16x4_t vmov_n_p16
DUP Vd.4H,rn Vd.4H ARMv7, ARMv8
(poly16_t value) value → rn

poly16x8_t vmovq_n_p16
DUP Vd.8H,rn Vd.8H ARMv7, ARMv8
(poly16_t value) value → rn

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 173 of 348
Non-Confidential
poly64x1_t vmov_n_p64
INS Dd.D[0],xn Vd.1D ARMv8
(poly64_t value) value → rn

poly64x2_t vmovq_n_p64
DUP Vd.2D,rn Vd.2D ARMv8
(poly64_t value) value → rn

float64x1_t vmov_n_f64
DUP Vd.1D,rn Vd.1D ARMv8(AArch64)
(float64_t value) value → rn

float64x2_t vmovq_n_f64
DUP Vd.2D,rn Vd.2D ARMv8(AArch64)
(float64_t value) value → rn

int8x8_t vdup_lane_s8
(int8x8_t vec, vec → Vn.8B DUP Vd.8B,Vn.B[lane] Vd.8B ARMv7, ARMv8
const int lane) 0 <= lane <= 7

int8x16_t vdupq_lane_s8
(int8x8_t vec, vec → Vn.8B DUP Vd.16B,Vn.B[lane] Vd.16B ARMv7, ARMv8
const int lane) 0 <= lane <= 7

int16x4_t vdup_lane_s16
(int16x4_t vec, vec → Vn.4H DUP Vd.4H,Vn.H[lane] Vd.4H ARMv7, ARMv8
const int lane) 0 <= lane <= 3

int16x8_t vdupq_lane_s16
(int16x4_t vec, vec → Vn.4H DUP Vd.8H,Vn.H[lane] Vd.8H ARMv7, ARMv8
const int lane) 0 <= lane <= 3

int32x2_t vdup_lane_s32
(int32x2_t vec, vec → Vn.2S DUP Vd.2S,Vn.S[lane] Vd.2S ARMv7, ARMv8
const int lane) 0 <= lane <= 1

int32x4_t vdupq_lane_s32
(int32x2_t vec, vec → Vn.2S DUP Vd.4S,Vn.S[lane] Vd.4S ARMv7, ARMv8
const int lane) 0 <= lane <= 1

int64x1_t vdup_lane_s64
(int64x1_t vec, vec → Vn.1D DUP Dd,Vn.D[lane] Dd ARMv7, ARMv8
const int lane) lane == 0

int64x2_t vdupq_lane_s64
(int64x1_t vec, vec → Vn.1D DUP Vd.2D,Vn.D[lane] Vd.2D ARMv7, ARMv8
const int lane) lane == 0

uint8x8_t vdup_lane_u8
(uint8x8_t vec, vec → Vn.8B DUP Vd.8B,Vn.B[lane] Vd.8B ARMv7, ARMv8
const int lane) 0 <= lane <= 7

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 174 of 348
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uint8x16_t vdupq_lane_u8
(uint8x8_t vec, vec → Vn.8B DUP Vd.16B,Vn.B[lane] Vd.16B ARMv7, ARMv8
const int lane) 0 <= lane <= 7

uint16x4_t vdup_lane_u16
(uint16x4_t vec, vec → Vn.4H DUP Vd.4H,Vn.H[lane] Vd.4H ARMv7, ARMv8
const int lane) 0 <= lane <= 3

uint16x8_t vdupq_lane_u16
(uint16x4_t vec, vec → Vn.4H DUP Vd.8H,Vn.H[lane] Vd.8H ARMv7, ARMv8
const int lane) 0 <= lane <= 3

uint32x2_t vdup_lane_u32
(uint32x2_t vec, vec → Vn.2S DUP Vd.2S,Vn.S[lane] Vd.2S ARMv7, ARMv8
const int lane) 0 <= lane <= 1

uint32x4_t vdupq_lane_u32
(uint32x2_t vec, vec → Vn.2S DUP Vd.4S,Vn.S[lane] Vd.4S ARMv7, ARMv8
const int lane) 0 <= lane <= 1

uint64x1_t vdup_lane_u64
(uint64x1_t vec, vec → Vn.1D DUP Dd,Vn.D[lane] Dd ARMv7, ARMv8
const int lane) lane == 0

uint64x2_t vdupq_lane_u64
(uint64x1_t vec, vec → Vn.1D DUP Vd.2D,Vn.D[lane] Vd.2D ARMv7, ARMv8
const int lane) lane == 0

poly64x1_t vdup_lane_p64
(poly64x1_t vec, vec → Vn.1D DUP Dd,Vn.D[lane] Dd ARMv8
const int lane) lane == 0

poly64x2_t vdupq_lane_p64
(poly64x1_t vec, vec → Vn.1D DUP Vd.2D,Vn.D[lane] Vd.2D ARMv8
const int lane) lane == 0

float32x2_t vdup_lane_f32
(float32x2_t vec, vec → Vn.2S DUP Vd.2S,Vn.S[lane] Vd.2S ARMv7, ARMv8
const int lane) 0 <= lane <= 1

float32x4_t vdupq_lane_f32
(float32x2_t vec, vec → Vn.2S DUP Vd.4S,Vn.S[lane] Vd.4S ARMv7, ARMv8
const int lane) 0 <= lane <= 1

poly8x8_t vdup_lane_p8
(poly8x8_t vec, vec → Vn.8B DUP Vd.8B,Vn.B[lane] Vd.8B ARMv7, ARMv8
const int lane) 0 <= lane <= 7

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 175 of 348
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poly8x16_t vdupq_lane_p8
(poly8x8_t vec, vec → Vn.8B DUP Vd.16B,Vn.B[lane] Vd.16B ARMv7, ARMv8
const int lane) 0 <= lane <= 7

poly16x4_t vdup_lane_p16
(poly16x4_t vec, vec → Vn.4H DUP Vd.4H,Vn.H[lane] Vd.4H ARMv7, ARMv8
const int lane) 0 <= lane <= 3

poly16x8_t vdupq_lane_p16
(poly16x4_t vec, vec → Vn.4H DUP Vd.8H,Vn.H[lane] Vd.8H ARMv7, ARMv8
const int lane) 0 <= lane <= 3

float64x1_t vdup_lane_f64
(float64x1_t vec, vec → Vn.1D DUP Dd,Vn.D[lane] Dd ARMv8(AArch64)
const int lane) lane == 0

float64x2_t vdupq_lane_f64
(float64x1_t vec, vec → Vn.1D DUP Vd.2D,Vn.D[lane] Vd.2D ARMv8(AArch64)
const int lane) lane == 0

int8x8_t vdup_laneq_s8
(int8x16_t vec, vec → Vn.16B DUP Vd.8B,Vn.B[lane] Vd.8B ARMv8(AArch64)
const int lane) 0 <= lane <= 15

int8x16_t vdupq_laneq_s8
(int8x16_t vec, vec → Vn.16B DUP Vd.16B,Vn.B[lane] Vd.16B ARMv8(AArch64)
const int lane) 0 <= lane <= 15

int16x4_t vdup_laneq_s16
(int16x8_t vec, vec → Vn.8H DUP Vd.4H,Vn.H[lane] Vd.4H ARMv8(AArch64)
const int lane) 0 <= lane <= 7

int16x8_t vdupq_laneq_s16
(int16x8_t vec, vec → Vn.8H DUP Vd.8H,Vn.H[lane] Vd.8H ARMv8(AArch64)
const int lane) 0 <= lane <= 7

int32x2_t vdup_laneq_s32
(int32x4_t vec, vec → Vn.4S DUP Vd.2S,Vn.S[lane] Vd.2S ARMv8(AArch64)
const int lane) 0 <= lane <= 3

int32x4_t vdupq_laneq_s32
(int32x4_t vec, vec → Vn.4S DUP Vd.4S,Vn.S[lane] Vd.4S ARMv8(AArch64)
const int lane) 0 <= lane <= 3

int64x1_t vdup_laneq_s64
(int64x2_t vec, vec → Vn.2D DUP Dd,Vn.D[lane] Dd ARMv8(AArch64)
const int lane) 0 <= lane <= 1

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int64x2_t vdupq_laneq_s64
(int64x2_t vec, vec → Vn.2D DUP Vd.2D,Vn.D[lane] Vd.2D ARMv8(AArch64)
const int lane) 0 <= lane <= 1

uint8x8_t vdup_laneq_u8
(uint8x16_t vec, vec → Vn.16B DUP Vd.8B,Vn.B[lane] Vd.8B ARMv8(AArch64)
const int lane) 0 <= lane <= 15

uint8x16_t vdupq_laneq_u8
(uint8x16_t vec, vec → Vn.16B DUP Vd.16B,Vn.B[lane] Vd.16B ARMv8(AArch64)
const int lane) 0 <= lane <= 15

uint16x4_t vdup_laneq_u16
(uint16x8_t vec, vec → Vn.8H DUP Vd.4H,Vn.H[lane] Vd.4H ARMv8(AArch64)
const int lane) 0 <= lane <= 7

uint16x8_t vdupq_laneq_u16
(uint16x8_t vec, vec → Vn.8H DUP Vd.8H,Vn.H[lane] Vd.8H ARMv8(AArch64)
const int lane) 0 <= lane <= 7

uint32x2_t vdup_laneq_u32
(uint32x4_t vec, vec → Vn.4S DUP Vd.2S,Vn.S[lane] Vd.2S ARMv8(AArch64)
const int lane) 0 <= lane <= 3

uint32x4_t vdupq_laneq_u32
(uint32x4_t vec, vec → Vn.4S DUP Vd.4S,Vn.S[lane] Vd.4S ARMv8(AArch64)
const int lane) 0 <= lane <= 3

uint64x1_t vdup_laneq_u64
(uint64x2_t vec, vec → Vn.2D DUP Dd,Vn.D[lane] Dd ARMv8(AArch64)
const int lane) 0 <= lane <= 1

uint64x2_t vdupq_laneq_u64
(uint64x2_t vec, vec → Vn.2D DUP Vd.2D,Vn.D[lane] Vd.2D ARMv8(AArch64)
const int lane) 0 <= lane <= 1

poly64x1_t vdup_laneq_p64
(poly64x2_t vec, vec → Vn.2D DUP Dd,Vn.D[lane] Dd ARMv8
const int lane) 0 <= lane <= 1

poly64x2_t vdupq_laneq_p64
(poly64x2_t vec, vec → Vn.2D DUP Vd.2D,Vn.D[lane] Vd.2D ARMv8
const int lane) 0 <= lane <= 1

float32x2_t vdup_laneq_f32
(float32x4_t vec, vec → Vn.4S DUP Vd.2S,Vn.S[lane] Vd.2S ARMv8(AArch64)
const int lane) 0 <= lane <= 3

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 177 of 348
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float32x4_t vdupq_laneq_f32
(float32x4_t vec, vec → Vn.4S DUP Vd.4S,Vn.S[lane] Vd.4S ARMv8(AArch64)
const int lane) 0 <= lane <= 3

poly8x8_t vdup_laneq_p8
(poly8x16_t vec, vec → Vn.16B DUP Vd.8B,Vn.B[lane] Vd.8B ARMv8(AArch64)
const int lane) 0 <= lane <= 15

poly8x16_t vdupq_laneq_p8
(poly8x16_t vec, vec → Vn.16B DUP Vd.16B,Vn.B[lane] Vd.16B ARMv8(AArch64)
const int lane) 0 <= lane <= 15

poly16x4_t vdup_laneq_p16
(poly16x8_t vec, vec → Vn.8H DUP Vd.4H,Vn.H[lane] Vd.4H ARMv8(AArch64)
const int lane) 0 <= lane <= 7

poly16x8_t vdupq_laneq_p16
(poly16x8_t vec, vec → Vn.8H DUP Vd.8H,Vn.H[lane] Vd.8H ARMv8(AArch64)
const int lane) 0 <= lane <= 7

float64x1_t vdup_laneq_f64
(float64x2_t vec, vec → Vn.2D DUP Dd,Vn.D[lane] Dd ARMv8(AArch64)
const int lane) 0 <= lane <= 1

float64x2_t vdupq_laneq_f64
(float64x2_t vec, vec → Vn.2D DUP Vd.2D,Vn.D[lane] Vd.2D ARMv8(AArch64)
const int lane) 0 <= lane <= 1

int8x16_t vcombine_s8
DUP Vd.1D,Vn.D[0]
(int8x8_t low, low → Vn.8B Vd.16B ARMv7, ARMv8
INS Vd.D[1],Vm.D[0]
int8x8_t high) high → Vm.8B

int16x8_t vcombine_s16
DUP Vd.1D,Vn.D[0]
(int16x4_t low, low → Vn.4H Vd.8H ARMv7, ARMv8
INS Vd.D[1],Vm.D[0]
int16x4_t high) high → Vm.4H

int32x4_t vcombine_s32
DUP Vd.1D,Vn.D[0]
(int32x2_t low, low → Vn.2S Vd.4S ARMv7, ARMv8
INS Vd.D[1],Vm.D[0]
int32x2_t high) high → Vm.2S

int64x2_t vcombine_s64
DUP Vd.1D,Vn.D[0]
(int64x1_t low, low → Vn.1D Vd.2D ARMv7, ARMv8
INS Vd.D[1],Vm.D[0]
int64x1_t high) high → Vm.1D

uint8x16_t vcombine_u8
DUP Vd.1D,Vn.D[0]
(uint8x8_t low, low → Vn.8B Vd.16B ARMv7, ARMv8
INS Vd.D[1],Vm.D[0]
uint8x8_t high) high → Vm.8B

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uint16x8_t vcombine_u16
DUP Vd.1D,Vn.D[0]
(uint16x4_t low, low → Vn.4H Vd.8H ARMv7, ARMv8
INS Vd.D[1],Vm.D[0]
uint16x4_t high) high → Vm.4H

uint32x4_t vcombine_u32
DUP Vd.1D,Vn.D[0]
(uint32x2_t low, low → Vn.2S Vd.4S ARMv7, ARMv8
INS Vd.D[1],Vm.D[0]
uint32x2_t high) high → Vm.2S

uint64x2_t vcombine_u64
DUP Vd.1D,Vn.D[0]
(uint64x1_t low, low → Vn.1D Vd.2D ARMv7, ARMv8
INS Vd.D[1],Vm.D[0]
uint64x1_t high) high → Vm.1D

poly64x2_t vcombine_p64
DUP Vd.1D,Vn.D[0]
(poly64x1_t low, low → Vn.1D Vd.2D ARMv8
INS Vd.D[1],Vm.D[0]
poly64x1_t high) high → Vm.1D

float16x8_t vcombine_f16
DUP Vd.1D,Vn.D[0]
(float16x4_t low, low → Vn.4H Vd.8H ARMv7, ARMv8
INS Vd.D[1],Vm.D[0]
float16x4_t high) high → Vm.4H

float32x4_t vcombine_f32
DUP Vd.1D,Vn.D[0]
(float32x2_t low, low → Vn.2S Vd.4S ARMv7, ARMv8
INS Vd.D[1],Vm.D[0]
float32x2_t high) high → Vm.2S

poly8x16_t vcombine_p8
DUP Vd.1D,Vn.D[0]
(poly8x8_t low, low → Vn.8B Vd.16B ARMv7, ARMv8
INS Vd.D[1],Vm.D[0]
poly8x8_t high) high → Vm.8B

poly16x8_t vcombine_p16
DUP Vd.1D,Vn.D[0]
(poly16x4_t low, low → Vn.4H Vd.8H ARMv7, ARMv8
INS Vd.D[1],Vm.D[0]
poly16x4_t high) high → Vm.4H

float64x2_t vcombine_f64
DUP Vd.1D,Vn.D[0]
(float64x1_t low, low → Vn.1D Vd.2D ARMv8(AArch64)
INS Vd.D[1],Vm.D[0]
float64x1_t high) high → Vm.1D

int8x8_t vget_high_s8
DUP Vd.1D,Vn.D[1] Vd.8B ARMv7, ARMv8
(int8x16_t a) a → Vn.16B

int16x4_t vget_high_s16
DUP Vd.1D,Vn.D[1] Vd.4H ARMv7, ARMv8
(int16x8_t a) a → Vn.8H

int32x2_t vget_high_s32
DUP Vd.1D,Vn.D[1] Vd.2S ARMv7, ARMv8
(int32x4_t a) a → Vn.4S

int64x1_t vget_high_s64
DUP Vd.1D,Vn.D[1] Vd.1D ARMv7, ARMv8
(int64x2_t a) a → Vn.2D

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uint8x8_t vget_high_u8
DUP Vd.1D,Vn.D[1] Vd.8B ARMv7, ARMv8
(uint8x16_t a) a → Vn.16B

uint16x4_t vget_high_u16
DUP Vd.1D,Vn.D[1] Vd.4H ARMv7, ARMv8
(uint16x8_t a) a → Vn.8H

uint32x2_t vget_high_u32
DUP Vd.1D,Vn.D[1] Vd.2S ARMv7, ARMv8
(uint32x4_t a) a → Vn.4S

uint64x1_t vget_high_u64
DUP Vd.1D,Vn.D[1] Vd.1D ARMv7, ARMv8
(uint64x2_t a) a → Vn.2D

poly64x1_t vget_high_p64
DUP Vd.1D,Vn.D[1] Vd.1D ARMv8
(poly64x2_t a) a → Vn.2D

float16x4_t vget_high_f16
DUP Vd.1D,Vn.D[1] Vd.4H ARMv8(AArch64)
(float16x8_t a) a → Vn.8H

float32x2_t vget_high_f32
DUP Vd.1D,Vn.D[1] Vd.2S ARMv7, ARMv8
(float32x4_t a) a → Vn.4S

poly8x8_t vget_high_p8
DUP Vd.1D,Vn.D[1] Vd.8B ARMv7, ARMv8
(poly8x16_t a) a → Vn.16B

poly16x4_t vget_high_p16
DUP Vd.1D,Vn.D[1] Vd.4H ARMv7, ARMv8
(poly16x8_t a) a → Vn.8H

float64x1_t vget_high_f64
DUP Vd.1D,Vn.D[1] Vd.1D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

int8x8_t vget_low_s8
DUP Vd.1D,Vn.D[0] Vd.8B ARMv7, ARMv8
(int8x16_t a) a → Vn.16B

int16x4_t vget_low_s16
DUP Vd.1D,Vn.D[0] Vd.4H ARMv7, ARMv8
(int16x8_t a) a → Vn.8H

int32x2_t vget_low_s32
DUP Vd.1D,Vn.D[0] Vd.2S ARMv7, ARMv8
(int32x4_t a) a → Vn.4S

int64x1_t vget_low_s64
DUP Vd.1D,Vn.D[0] Vd.1D ARMv7, ARMv8
(int64x2_t a) a → Vn.2D

uint8x8_t vget_low_u8
DUP Vd.1D,Vn.D[0] Vd.8B ARMv7, ARMv8
(uint8x16_t a) a → Vn.16B

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uint16x4_t vget_low_u16
DUP Vd.1D,Vn.D[0] Vd.4H ARMv7, ARMv8
(uint16x8_t a) a → Vn.8H

uint32x2_t vget_low_u32
DUP Vd.1D,Vn.D[0] Vd.2S ARMv7, ARMv8
(uint32x4_t a) a → Vn.4S

uint64x1_t vget_low_u64
DUP Vd.1D,Vn.D[0] Vd.1D ARMv7, ARMv8
(uint64x2_t a) a → Vn.2D

poly64x1_t vget_low_p64
DUP Vd.1D,Vn.D[0] Vd.1D ARMv8
(poly64x2_t a) a → Vn.2D

float16x4_t vget_low_f16
DUP Vd.1D,Vn.D[0] Vd.4H ARMv8(AArch64)
(float16x8_t a) a → Vn.8H

float32x2_t vget_low_f32
DUP Vd.1D,Vn.D[0] Vd.2S ARMv7, ARMv8
(float32x4_t a) a → Vn.4S

poly8x8_t vget_low_p8
DUP Vd.1D,Vn.D[0] Vd.8B ARMv7, ARMv8
(poly8x16_t a) a → Vn.16B

poly16x4_t vget_low_p16
DUP Vd.1D,Vn.D[0] Vd.4H ARMv7, ARMv8
(poly16x8_t a) a → Vn.8H

float64x1_t vget_low_f64
DUP Vd.1D,Vn.D[0] Vd.1D ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

int8_t vdupb_lane_s8
(int8x8_t vec, vec → Vn.8B DUP Bd,Vn.B[lane] Bd ARMv8(AArch64)
const int lane) 0 <= lane <= 7

int16_t vduph_lane_s16
(int16x4_t vec, vec → Vn.4H DUP Hd,Vn.H[lane] Hd ARMv8(AArch64)
const int lane) 0 <= lane <= 3

int32_t vdups_lane_s32
(int32x2_t vec, vec → Vn.2S DUP Sd,Vn.S[lane] Sd ARMv8(AArch64)
const int lane) 0 <= lane <= 1

int64_t vdupd_lane_s64
(int64x1_t vec, vec → Vn.1D DUP Dd,Vn.D[lane] Dd ARMv8(AArch64)
const int lane) lane == 0

uint8_t vdupb_lane_u8
(uint8x8_t vec, vec → Vn.8B DUP Bd,Vn.B[lane] Bd ARMv8(AArch64)
const int lane) 0 <= lane <= 7

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uint16_t vduph_lane_u16
(uint16x4_t vec, vec → Vn.4H DUP Hd,Vn.H[lane] Hd ARMv8(AArch64)
const int lane) 0 <= lane <= 3

uint32_t vdups_lane_u32
(uint32x2_t vec, vec → Vn.2S DUP Sd,Vn.S[lane] Sd ARMv8(AArch64)
const int lane) 0 <= lane <= 1

uint64_t vdupd_lane_u64
(uint64x1_t vec, vec → Vn.1D DUP Dd,Vn.D[lane] Dd ARMv8(AArch64)
const int lane) lane == 0

float32_t vdups_lane_f32
(float32x2_t vec, vec → Vn.2S DUP Sd,Vn.S[lane] Sd ARMv8(AArch64)
const int lane) 0 <= lane <= 1

float64_t vdupd_lane_f64
(float64x1_t vec, vec → Vn.1D DUP Dd,Vn.D[lane] Dd ARMv8(AArch64)
const int lane) lane == 0

poly8_t vdupb_lane_p8
(poly8x8_t vec, vec → Vn.8B DUP Bd,Vn.B[lane] Bd ARMv8(AArch64)
const int lane) 0 <= lane <= 7

poly16_t vduph_lane_p16
(poly16x4_t vec, vec → Vn.4H DUP Hd,Vn.H[lane] Hd ARMv8(AArch64)
const int lane) 0 <= lane <= 3

int8_t vdupb_laneq_s8
(int8x16_t vec, vec → Vn.16B DUP Bd,Vn.B[lane] Bd ARMv8(AArch64)
const int lane) 0 <= lane <= 15

int16_t vduph_laneq_s16
(int16x8_t vec, vec → Vn.8H DUP Hd,Vn.H[lane] Hd ARMv8(AArch64)
const int lane) 0 <= lane <= 7

int32_t vdups_laneq_s32
(int32x4_t vec, vec → Vn.4S DUP Sd,Vn.S[lane] Sd ARMv8(AArch64)
const int lane) 0 <= lane <= 3

int64_t vdupd_laneq_s64
(int64x2_t vec, vec → Vn.2D DUP Dd,Vn.D[lane] Dd ARMv8(AArch64)
const int lane) 0 <= lane <= 1

uint8_t vdupb_laneq_u8
(uint8x16_t vec, vec → Vn.16B DUP Bd,Vn.B[lane] Bd ARMv8(AArch64)
const int lane) 0 <= lane <= 15

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uint16_t vduph_laneq_u16
(uint16x8_t vec, vec → Vn.8H DUP Hd,Vn.H[lane] Hd ARMv8(AArch64)
const int lane) 0 <= lane <= 7

uint32_t vdups_laneq_u32
(uint32x4_t vec, vec → Vn.4S DUP Sd,Vn.S[lane] Sd ARMv8(AArch64)
const int lane) 0 <= lane <= 3

uint64_t vdupd_laneq_u64
(uint64x2_t vec, vec → Vn.2D DUP Dd,Vn.D[lane] Dd ARMv8(AArch64)
const int lane) 0 <= lane <= 1

float32_t vdups_laneq_f32
(float32x4_t vec, vec → Vn.4S DUP Sd,Vn.S[lane] Sd ARMv8(AArch64)
const int lane) 0 <= lane <= 3

float64_t vdupd_laneq_f64
(float64x2_t vec, vec → Vn.2D DUP Dd,Vn.D[lane] Dd ARMv8(AArch64)
const int lane) 0 <= lane <= 1

poly8_t vdupb_laneq_p8
(poly8x16_t vec, vec → Vn.16B DUP Bd,Vn.B[lane] Bd ARMv8(AArch64)
const int lane) 0 <= lane <= 15

poly16_t vduph_laneq_p16
(poly16x8_t vec, vec → Vn.8H DUP Hd,Vn.H[lane] Hd ARMv8(AArch64)
const int lane) 0 <= lane <= 7

int8x8_t vld1_s8
LD1 {Vt.8B},[Xn] Vt.8B ARMv7, ARMv8
(int8_t const * ptr) ptr → Xn

int8x16_t vld1q_s8
LD1 {Vt.16B},[Xn] Vt.16B ARMv7, ARMv8
(int8_t const * ptr) ptr → Xn

int16x4_t vld1_s16
LD1 {Vt.4H},[Xn] Vt.4H ARMv7, ARMv8
(int16_t const * ptr) ptr → Xn

int16x8_t vld1q_s16
LD1 {Vt.8H},[Xn] Vt.8H ARMv7, ARMv8
(int16_t const * ptr) ptr → Xn

int32x2_t vld1_s32
LD1 {Vt.2S},[Xn] Vt.2S ARMv7, ARMv8
(int32_t const * ptr) ptr → Xn

int32x4_t vld1q_s32
LD1 {Vt.4S},[Xn] Vt.4S ARMv7, ARMv8
(int32_t const * ptr) ptr → Xn

int64x1_t vld1_s64
LD1 {Vt.1D},[Xn] Vt.1D ARMv7, ARMv8
(int64_t const * ptr) ptr → Xn

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int64x2_t vld1q_s64
LD1 {Vt.2D},[Xn] Vt.2D ARMv7, ARMv8
(int64_t const * ptr) ptr → Xn

uint8x8_t vld1_u8
LD1 {Vt.8B},[Xn] Vt.8B ARMv7, ARMv8
(uint8_t const * ptr) ptr → Xn

uint8x16_t vld1q_u8
LD1 {Vt.16B},[Xn] Vt.16B ARMv7, ARMv8
(uint8_t const * ptr) ptr → Xn

uint16x4_t vld1_u16
LD1 {Vt.4H},[Xn] Vt.4H ARMv7, ARMv8
(uint16_t const * ptr) ptr → Xn

uint16x8_t vld1q_u16
LD1 {Vt.8H},[Xn] Vt.8H ARMv7, ARMv8
(uint16_t const * ptr) ptr → Xn

uint32x2_t vld1_u32
LD1 {Vt.2S},[Xn] Vt.2S ARMv7, ARMv8
(uint32_t const * ptr) ptr → Xn

uint32x4_t vld1q_u32
LD1 {Vt.4S},[Xn] Vt.4S ARMv7, ARMv8
(uint32_t const * ptr) ptr → Xn

uint64x1_t vld1_u64
LD1 {Vt.1D},[Xn] Vt.1D ARMv7, ARMv8
(uint64_t const * ptr) ptr → Xn

uint64x2_t vld1q_u64
LD1 {Vt.2D},[Xn] Vt.2D ARMv7, ARMv8
(uint64_t const * ptr) ptr → Xn

poly64x1_t vld1_p64
LD1 {Vt.1D},[Xn] Vt.1D ARMv8
(poly64_t const * ptr) ptr → Xn

poly64x2_t vld1q_p64
LD1 {Vt.2D},[Xn] Vt.2D ARMv8
(poly64_t const * ptr) ptr → Xn

float16x4_t vld1_f16
LD1 {Vt.4H},[Xn] Vt.4H ARMv7, ARMv8
(float16_t const * ptr) ptr → Xn

float16x8_t vld1q_f16
LD1 {Vt.8H},[Xn] Vt.8H ARMv7, ARMv8
(float16_t const * ptr) ptr → Xn

float32x2_t vld1_f32
LD1 {Vt.2S},[Xn] Vt.2S ARMv7, ARMv8
(float32_t const * ptr) ptr → Xn

float32x4_t vld1q_f32
LD1 {Vt.4S},[Xn] Vt.4S ARMv7, ARMv8
(float32_t const * ptr) ptr → Xn

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poly8x8_t vld1_p8
LD1 {Vt.8B},[Xn] Vt.8B ARMv7, ARMv8
(poly8_t const * ptr) ptr → Xn

poly8x16_t vld1q_p8
LD1 {Vt.16B},[Xn] Vt.16B ARMv7, ARMv8
(poly8_t const * ptr) ptr → Xn

poly16x4_t vld1_p16
LD1 {Vt.4H},[Xn] Vt.4H ARMv7, ARMv8
(poly16_t const * ptr) ptr → Xn

poly16x8_t vld1q_p16
LD1 {Vt.8H},[Xn] Vt.8H ARMv7, ARMv8
(poly16_t const * ptr) ptr → Xn

float64x1_t vld1_f64
LD1 {Vt.1D},[Xn] Vt.1D ARMv8(AArch64)
(float64_t const * ptr) ptr → Xn

float64x2_t vld1q_f64
LD1 {Vt.2D},[Xn] Vt.2D ARMv8(AArch64)
(float64_t const * ptr) ptr → Xn

int8x8_t vld1_lane_s8
(int8_t const * ptr, ptr → Xn
LD1 {Vt.b}[lane],[Xn] Vt.8B ARMv7, ARMv8
int8x8_t src, src → Vt.8B
const int lane) 0 <= lane <= 7

int8x16_t vld1q_lane_s8
(int8_t const * ptr, ptr → Xn
LD1 {Vt.b}[lane],[Xn] Vt.16B ARMv7, ARMv8
int8x16_t src, src → Vt.16B
const int lane) 0 <= lane <= 15

int16x4_t vld1_lane_s16
(int16_t const * ptr, ptr → Xn
LD1 {Vt.H}[lane],[Xn] Vt.4H ARMv7, ARMv8
int16x4_t src, src → Vt.4H
const int lane) 0 <= lane <= 3

int16x8_t vld1q_lane_s16
(int16_t const * ptr, ptr → Xn
LD1 {Vt.H}[lane],[Xn] Vt.8H ARMv7, ARMv8
int16x8_t src, src → Vt.8H
const int lane) 0 <= lane <= 7

int32x2_t vld1_lane_s32
(int32_t const * ptr, ptr → Xn
LD1 {Vt.S}[lane],[Xn] Vt.2S ARMv7, ARMv8
int32x2_t src, src → Vt.2S
const int lane) 0 <= lane <= 1

int32x4_t vld1q_lane_s32
(int32_t const * ptr, ptr → Xn
LD1 {Vt.S}[lane],[Xn] Vt.4S ARMv7, ARMv8
int32x4_t src, src → Vt.4S
const int lane) 0 <= lane <= 3

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int64x1_t vld1_lane_s64
(int64_t const * ptr, ptr → Xn
LD1 {Vt.D}[lane],[Xn] Vt.1D ARMv7, ARMv8
int64x1_t src, src → Vt.1D
const int lane) lane == 0

int64x2_t vld1q_lane_s64
(int64_t const * ptr, ptr → Xn
LD1 {Vt.D}[lane],[Xn] Vt.2D ARMv7, ARMv8
int64x2_t src, src → Vt.2D
const int lane) 0 <= lane <= 1

uint8x8_t vld1_lane_u8
(uint8_t const * ptr, ptr → Xn
LD1 {Vt.B}[lane],[Xn] Vt.8B ARMv7, ARMv8
uint8x8_t src, src → Vt.8B
const int lane) 0 <= lane <= 7

uint8x16_t vld1q_lane_u8
(uint8_t const * ptr, ptr → Xn
LD1 {Vt.B}[lane],[Xn] Vt.16B ARMv7, ARMv8
uint8x16_t src, src → Vt.16B
const int lane) 0 <= lane <= 15

uint16x4_t vld1_lane_u16
(uint16_t const * ptr, ptr → Xn
LD1 {Vt.H}[lane],[Xn] Vt.4H ARMv7, ARMv8
uint16x4_t src, src → Vt.4H
const int lane) 0 <= lane <= 3

uint16x8_t vld1q_lane_u16
(uint16_t const * ptr, ptr → Xn
LD1 {Vt.H}[lane],[Xn] Vt.8H ARMv7, ARMv8
uint16x8_t src, src → Vt.8H
const int lane) 0 <= lane <= 7

uint32x2_t vld1_lane_u32
(uint32_t const * ptr, ptr → Xn
LD1 {Vt.S}[lane],[Xn] Vt.2S ARMv7, ARMv8
uint32x2_t src, src → Vt.2S
const int lane) 0 <= lane <= 1

uint32x4_t vld1q_lane_u32
(uint32_t const * ptr, ptr → Xn
LD1 {Vt.S}[lane],[Xn] Vt.4S ARMv7, ARMv8
uint32x4_t src, src → Vt.4S
const int lane) 0 <= lane <= 3

uint64x1_t vld1_lane_u64
(uint64_t const * ptr, ptr → Xn
LD1 {Vt.D}[lane],[Xn] Vt.1D ARMv7, ARMv8
uint64x1_t src, src → Vt.1D
const int lane) lane == 0

uint64x2_t vld1q_lane_u64
(uint64_t const * ptr, ptr → Xn
LD1 {Vt.D}[lane],[Xn] Vt.2D ARMv7, ARMv8
uint64x2_t src, src → Vt.2D
const int lane) 0 <= lane <= 1

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 186 of 348
Non-Confidential
poly64x1_t vld1_lane_p64
(poly64_t const * ptr, ptr → Xn
LD1 {Vt.D}[lane],[Xn] Vt.1D ARMv8
poly64x1_t src, src → Vt.1D
const int lane) lane == 0

poly64x2_t vld1q_lane_p64
(poly64_t const * ptr, ptr → Xn
LD1 {Vt.D}[lane],[Xn] Vt.2D ARMv8
poly64x2_t src, src → Vt.2D
const int lane) 0 <= lane <= 1

float16x4_t vld1_lane_f16
(float16_t const * ptr, ptr → Xn
LD1 {Vt.H}[lane],[Xn] Vt.4H ARMv7, ARMv8
float16x4_t src, src → Vt.4H
const int lane) 0 <= lane <= 3

float16x8_t vld1q_lane_f16
(float16_t const * ptr, ptr → Xn
LD1 {Vt.H}[lane],[Xn] Vt.8H ARMv7, ARMv8
float16x8_t src, src → Vt.8H
const int lane) 0 <= lane <= 7

float32x2_t vld1_lane_f32
(float32_t const * ptr, ptr → Xn
LD1 {Vt.S}[lane],[Xn] Vt.2S ARMv7, ARMv8
float32x2_t src, src → Vt.2S
const int lane) 0 <= lane <= 1

float32x4_t vld1q_lane_f32
(float32_t const * ptr, ptr → Xn
LD1 {Vt.S}[lane],[Xn] Vt.4S ARMv7, ARMv8
float32x4_t src, src → Vt.4S
const int lane) 0 <= lane <= 3

poly8x8_t vld1_lane_p8
(poly8_t const * ptr, ptr → Xn
LD1 {Vt.B}[lane],[Xn] Vt.8B ARMv7, ARMv8
poly8x8_t src, src → Vt.8B
const int lane) 0 <= lane <= 7

poly8x16_t vld1q_lane_p8
(poly8_t const * ptr, ptr → Xn
LD1 {Vt.B}[lane],[Xn] Vt.16B ARMv7, ARMv8
poly8x16_t src, src → Vt.16B
const int lane) 0 <= lane <= 15

poly16x4_t vld1_lane_p16
(poly16_t const * ptr, ptr → Xn
LD1 {Vt.H}[lane],[Xn] Vt.4H ARMv7, ARMv8
poly16x4_t src, src → Vt.4H
const int lane) 0 <= lane <= 3

poly16x8_t vld1q_lane_p16
(poly16_t const * ptr, ptr → Xn
LD1 {Vt.H}[lane],[Xn] Vt.8H ARMv7, ARMv8
poly16x8_t src, src → Vt.8H
const int lane) 0 <= lane <= 7

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Non-Confidential
float64x1_t vld1_lane_f64
(float64_t const * ptr, ptr → Xn
LD1 {Vt.D}[lane],[Xn] Vt.1D ARMv8(AArch64)
float64x1_t src, src → Vt.1D
const int lane) lane == 0

float64x2_t vld1q_lane_f64
(float64_t const * ptr, ptr → Xn
LD1 {Vt.D}[lane],[Xn] Vt.2D ARMv8(AArch64)
float64x2_t src, src → Vt.2D
const int lane) 0 <= lane <= 1

int8x8_t vld1_dup_s8
LD1R {Vt.8B},[Xn] Vt.8B ARMv7, ARMv8
(int8_t const * ptr) ptr → Xn

int8x16_t vld1q_dup_s8
LD1R {Vt.16B},[Xn] Vt.16B ARMv7, ARMv8
(int8_t const * ptr) ptr → Xn

int16x4_t vld1_dup_s16
LD1R {Vt.4H},[Xn] Vt.4H ARMv7, ARMv8
(int16_t const * ptr) ptr → Xn

int16x8_t vld1q_dup_s16
LD1R {Vt.8H},[Xn] Vt.8H ARMv7, ARMv8
(int16_t const * ptr) ptr → Xn

int32x2_t vld1_dup_s32
LD1R {Vt.2S},[Xn] Vt.2S ARMv7, ARMv8
(int32_t const * ptr) ptr → Xn

int32x4_t vld1q_dup_s32
LD1R {Vt.4S},[Xn] Vt.4S ARMv7, ARMv8
(int32_t const * ptr) ptr → Xn

int64x1_t vld1_dup_s64
LD1 {Vt.1D},[Xn] Vt.1D ARMv7, ARMv8
(int64_t const * ptr) ptr → Xn

int64x2_t vld1q_dup_s64
LD1R {Vt.2D},[Xn] Vt.2D ARMv7, ARMv8
(int64_t const * ptr) ptr → Xn

uint8x8_t vld1_dup_u8
LD1R {Vt.8B},[Xn] Vt.8B ARMv7, ARMv8
(uint8_t const * ptr) ptr → Xn

uint8x16_t vld1q_dup_u8
LD1R {Vt.16B},[Xn] Vt.16B ARMv7, ARMv8
(uint8_t const * ptr) ptr → Xn

uint16x4_t vld1_dup_u16
LD1R {Vt.4H},[Xn] Vt.4H ARMv7, ARMv8
(uint16_t const * ptr) ptr → Xn

uint16x8_t vld1q_dup_u16
LD1R {Vt.8H},[Xn] Vt.8H ARMv7, ARMv8
(uint16_t const * ptr) ptr → Xn

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Non-Confidential
uint32x2_t vld1_dup_u32
LD1R {Vt.2S},[Xn] Vt.2S ARMv7, ARMv8
(uint32_t const * ptr) ptr → Xn

uint32x4_t vld1q_dup_u32
LD1R {Vt.4S},[Xn] Vt.4S ARMv7, ARMv8
(uint32_t const * ptr) ptr → Xn

uint64x1_t vld1_dup_u64
LD1 {Vt.1D},[Xn] Vt.1D ARMv7, ARMv8
(uint64_t const * ptr) ptr → Xn

uint64x2_t vld1q_dup_u64
LD1R {Vt.2D},[Xn] Vt.2D ARMv7, ARMv8
(uint64_t const * ptr) ptr → Xn

poly64x1_t vld1_dup_p64
LD1 {Vt.1D},[Xn] Vt.1D ARMv8
(poly64_t const * ptr) ptr → Xn

poly64x2_t vld1q_dup_p64
LD1R {Vt.2D},[Xn] Vt.2D ARMv8
(poly64_t const * ptr) ptr → Xn

float16x4_t vld1_dup_f16
LD1R {Vt.4H},[Xn] Vt.4H ARMv7, ARMv8
(float16_t const * ptr) ptr → Xn

float16x8_t vld1q_dup_f16
LD1R {Vt.8H},[Xn] Vt.8H ARMv7, ARMv8
(float16_t const * ptr) ptr → Xn

float32x2_t vld1_dup_f32
LD1R {Vt.2S},[Xn] Vt.2S ARMv7, ARMv8
(float32_t const * ptr) ptr → Xn

float32x4_t vld1q_dup_f32
LD1R {Vt.4S},[Xn] Vt.4S ARMv7, ARMv8
(float32_t const * ptr) ptr → Xn

poly8x8_t vld1_dup_p8
LD1R {Vt.8B},[Xn] Vt.8B ARMv7, ARMv8
(poly8_t const * ptr) ptr → Xn

poly8x16_t vld1q_dup_p8
LD1R {Vt.16B},[Xn] Vt.16B ARMv7, ARMv8
(poly8_t const * ptr) ptr → Xn

poly16x4_t vld1_dup_p16
LD1R {Vt.4H},[Xn] Vt.4H ARMv7, ARMv8
(poly16_t const * ptr) ptr → Xn

poly16x8_t vld1q_dup_p16
LD1R {Vt.8H},[Xn] Vt.8H ARMv7, ARMv8
(poly16_t const * ptr) ptr → Xn

float64x1_t vld1_dup_f64
LD1 {Vt.1D},[Xn] Vt.1D ARMv8(AArch64)
(float64_t const * ptr) ptr → Xn

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float64x2_t vld1q_dup_f64
LD1R {Vt.2D},[Xn] Vt.2D ARMv8(AArch64)
(float64_t const * ptr) ptr → Xn

void vst1_s8
(int8_t * ptr, ptr → Xn ST1 {Vt.8B},[Xn] ARMv7, ARMv8
int8x8_t val) val → Vt.8B

void vst1q_s8
(int8_t * ptr, ptr → Xn ST1 {Vt.16B},[Xn] ARMv7, ARMv8
int8x16_t val) val → Vt.16B

void vst1_s16
(int16_t * ptr, ptr → Xn ST1 {Vt.4H},[Xn] ARMv7, ARMv8
int16x4_t val) val → Vt.4H

void vst1q_s16
(int16_t * ptr, ptr → Xn ST1 {Vt.8H},[Xn] ARMv7, ARMv8
int16x8_t val) val → Vt.8H

void vst1_s32
(int32_t * ptr, ptr → Xn ST1 {Vt.2S},[Xn] ARMv7, ARMv8
int32x2_t val) val → Vt.2S

void vst1q_s32
(int32_t * ptr, ptr → Xn ST1 {Vt.4S},[Xn] ARMv7, ARMv8
int32x4_t val) val → Vt.4S

void vst1_s64
(int64_t * ptr, ptr → Xn ST1 {Vt.1D},[Xn] ARMv7, ARMv8
int64x1_t val) val → Vt.1D

void vst1q_s64
(int64_t * ptr, ptr → Xn ST1 {Vt.2D},[Xn] ARMv7, ARMv8
int64x2_t val) val → Vt.2D

void vst1_u8
(uint8_t * ptr, ptr → Xn ST1 {Vt.8B},[Xn] ARMv7, ARMv8
uint8x8_t val) val → Vt.8B

void vst1q_u8
(uint8_t * ptr, ptr → Xn ST1 {Vt.16B},[Xn] ARMv7, ARMv8
uint8x16_t val) val → Vt.16B

void vst1_u16
(uint16_t * ptr, ptr → Xn ST1 {Vt.4H},[Xn] ARMv7, ARMv8
uint16x4_t val) val → Vt.4H

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 190 of 348
Non-Confidential
void vst1q_u16
(uint16_t * ptr, ptr → Xn ST1 {Vt.8H},[Xn] ARMv7, ARMv8
uint16x8_t val) val → Vt.8H

void vst1_u32
(uint32_t * ptr, ptr → Xn ST1 {Vt.2S},[Xn] ARMv7, ARMv8
uint32x2_t val) val → Vt.2S

void vst1q_u32
(uint32_t * ptr, ptr → Xn ST1 {Vt.4S},[Xn] ARMv7, ARMv8
uint32x4_t val) val → Vt.4S

void vst1_u64
(uint64_t * ptr, ptr → Xn ST1 {Vt.1D},[Xn] ARMv7, ARMv8
uint64x1_t val) val → Vt.1D

void vst1q_u64
(uint64_t * ptr, ptr → Xn ST1 {Vt.2D},[Xn] ARMv7, ARMv8
uint64x2_t val) val → Vt.2D

void vst1_p64
(poly64_t * ptr, ptr → Xn ST1 {Vt.1D},[Xn] ARMv8
poly64x1_t val) val → Vt.1D

void vst1q_p64
(poly64_t * ptr, ptr → Xn ST1 {Vt.2D},[Xn] ARMv8
poly64x2_t val) val → Vt.2D

void vst1_f16
(float16_t * ptr, ptr → Xn ST1 {Vt.4H},[Xn] ARMv7, ARMv8
float16x4_t val) val → Vt.4H

void vst1q_f16
(float16_t * ptr, ptr → Xn ST1 {Vt.8H},[Xn] ARMv7, ARMv8
float16x8_t val) val → Vt.8H

void vst1_f32
(float32_t * ptr, ptr → Xn ST1 {Vt.2S},[Xn] ARMv7, ARMv8
float32x2_t val) val → Vt.2S

void vst1q_f32
(float32_t * ptr, ptr → Xn ST1 {Vt.4S},[Xn] ARMv7, ARMv8
float32x4_t val) val → Vt.4S

void vst1_p8
(poly8_t * ptr, ptr → Xn ST1 {Vt.8B},[Xn] ARMv7, ARMv8
poly8x8_t val) val → Vt.8B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 191 of 348
Non-Confidential
void vst1q_p8
(poly8_t * ptr, ptr → Xn ST1 {Vt.16B},[Xn] ARMv7, ARMv8
poly8x16_t val) val → Vt.16B

void vst1_p16
(poly16_t * ptr, ptr → Xn ST1 {Vt.4H},[Xn] ARMv7, ARMv8
poly16x4_t val) val → Vt.4H

void vst1q_p16
(poly16_t * ptr, ptr → Xn ST1 {Vt.8H},[Xn] ARMv7, ARMv8
poly16x8_t val) val → Vt.8H

void vst1_f64
(float64_t * ptr, ptr → Xn ST1 {Vt.1D},[Xn] ARMv8(AArch64)
float64x1_t val) val → Vt.1D

void vst1q_f64
(float64_t * ptr, ptr → Xn ST1 {Vt.2D},[Xn] ARMv8(AArch64)
float64x2_t val) val → Vt.2D

void vst1_lane_s8
(int8_t * ptr, ptr → Xn
ST1 {Vt.b}[lane],[Xn] ARMv7, ARMv8
int8x8_t val, val → Vt.8B
const int lane) 0 <= lane <= 7

void vst1q_lane_s8
(int8_t * ptr, ptr → Xn
ST1 {Vt.b}[lane],[Xn] ARMv7, ARMv8
int8x16_t val, val → Vt.16B
const int lane) 0 <= lane <= 15

void vst1_lane_s16
(int16_t * ptr, ptr → Xn
ST1 {Vt.h}[lane],[Xn] ARMv7, ARMv8
int16x4_t val, val → Vt.4H
const int lane) 0 <= lane <= 3

void vst1q_lane_s16
(int16_t * ptr, ptr → Xn
ST1 {Vt.h}[lane],[Xn] ARMv7, ARMv8
int16x8_t val, val → Vt.8H
const int lane) 0 <= lane <= 7

void vst1_lane_s32
(int32_t * ptr, ptr → Xn
ST1 {Vt.s}[lane],[Xn] ARMv7, ARMv8
int32x2_t val, val → Vt.2S
const int lane) 0 <= lane <= 1

void vst1q_lane_s32
(int32_t * ptr, ptr → Xn
ST1 {Vt.s}[lane],[Xn] ARMv7, ARMv8
int32x4_t val, val → Vt.4S
const int lane) 0 <= lane <= 3

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 192 of 348
Non-Confidential
void vst1_lane_s64
(int64_t * ptr, ptr → Xn
ST1 {Vt.d}[lane],[Xn] ARMv7, ARMv8
int64x1_t val, val → Vt.1D
const int lane) lane == 0

void vst1q_lane_s64
(int64_t * ptr, ptr → Xn
ST1 {Vt.d}[lane],[Xn] ARMv7, ARMv8
int64x2_t val, val → Vt.2D
const int lane) 0 <= lane <= 1

void vst1_lane_u8
(uint8_t * ptr, ptr → Xn
ST1 {Vt.b}[lane],[Xn] ARMv7, ARMv8
uint8x8_t val, val → Vt.8B
const int lane) 0 <= lane <= 7

void vst1q_lane_u8
(uint8_t * ptr, ptr → Xn
ST1 {Vt.b}[lane],[Xn] ARMv7, ARMv8
uint8x16_t val, val → Vt.16B
const int lane) 0 <= lane <= 15

void vst1_lane_u16
(uint16_t * ptr, ptr → Xn
ST1 {Vt.h}[lane],[Xn] ARMv7, ARMv8
uint16x4_t val, val → Vt.4H
const int lane) 0 <= lane <= 3

void vst1q_lane_u16
(uint16_t * ptr, ptr → Xn
ST1 {Vt.h}[lane],[Xn] ARMv7, ARMv8
uint16x8_t val, val → Vt.8H
const int lane) 0 <= lane <= 7

void vst1_lane_u32
(uint32_t * ptr, ptr → Xn
ST1 {Vt.s}[lane],[Xn] ARMv7, ARMv8
uint32x2_t val, val → Vt.2S
const int lane) 0 <= lane <= 1

void vst1q_lane_u32
(uint32_t * ptr, ptr → Xn
ST1 {Vt.s}[lane],[Xn] ARMv7, ARMv8
uint32x4_t val, val → Vt.4S
const int lane) 0 <= lane <= 3

void vst1_lane_u64
(uint64_t * ptr, ptr → Xn
ST1 {Vt.d}[lane],[Xn] ARMv7, ARMv8
uint64x1_t val, val → Vt.1D
const int lane) lane == 0

void vst1q_lane_u64
(uint64_t * ptr, ptr → Xn
ST1 {Vt.d}[lane],[Xn] ARMv7, ARMv8
uint64x2_t val, val → Vt.2D
const int lane) 0 <= lane <= 1

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 193 of 348
Non-Confidential
void vst1_lane_p64
(poly64_t * ptr, ptr → Xn
ST1 {Vt.d}[lane],[Xn] ARMv8
poly64x1_t val, val → Vt.1D
const int lane) lane == 0

void vst1q_lane_p64
(poly64_t * ptr, ptr → Xn
ST1 {Vt.d}[lane],[Xn] ARMv8
poly64x2_t val, val → Vt.2D
const int lane) 0 <= lane <= 1

void vst1_lane_f16
(float16_t * ptr, ptr → Xn
ST1 {Vt.h}[lane],[Xn] ARMv7, ARMv8
float16x4_t val, val → Vt.4H
const int lane) 0 <= lane <= 3

void vst1q_lane_f16
(float16_t * ptr, ptr → Xn
ST1 {Vt.h}[lane],[Xn] ARMv7, ARMv8
float16x8_t val, val → Vt.8H
const int lane) 0 <= lane <= 7

void vst1_lane_f32
(float32_t * ptr, ptr → Xn
ST1 {Vt.s}[lane],[Xn] ARMv7, ARMv8
float32x2_t val, val → Vt.2S
const int lane) 0 <= lane <= 1

void vst1q_lane_f32
(float32_t * ptr, ptr → Xn
ST1 {Vt.s}[lane],[Xn] ARMv7, ARMv8
float32x4_t val, val → Vt.4S
const int lane) 0 <= lane <= 3

void vst1_lane_p8
(poly8_t * ptr, ptr → Xn
ST1 {Vt.b}[lane],[Xn] ARMv7, ARMv8
poly8x8_t val, val → Vt.8B
const int lane) 0 <= lane <= 7

void vst1q_lane_p8
(poly8_t * ptr, ptr → Xn
ST1 {Vt.b}[lane],[Xn] ARMv7, ARMv8
poly8x16_t val, val → Vt.16B
const int lane) 0 <= lane <= 15

void vst1_lane_p16
(poly16_t * ptr, ptr → Xn
ST1 {Vt.h}[lane],[Xn] ARMv7, ARMv8
poly16x4_t val, val → Vt.4H
const int lane) 0 <= lane <= 3

void vst1q_lane_p16
(poly16_t * ptr, ptr → Xn
ST1 {Vt.h}[lane],[Xn] ARMv7, ARMv8
poly16x8_t val, val → Vt.8H
const int lane) 0 <= lane <= 7

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 194 of 348
Non-Confidential
void vst1_lane_f64
(float64_t * ptr, ptr → Xn
ST1 {Vt.d}[lane],[Xn] ARMv8(AArch64)
float64x1_t val, val → Vt.1D
const int lane) lane == 0

void vst1q_lane_f64
(float64_t * ptr, ptr → Xn
ST1 {Vt.d}[lane],[Xn] ARMv8(AArch64)
float64x2_t val, val → Vt.2D
const int lane) 0 <= lane <= 1

Vt2.8B →
int8x8x2_t vld2_s8 result.val[1]
LD2 {Vt.8B - Vt2.8B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) Vt.8B →
ptr → Xn result.val[0]

Vt2.16B →
int8x16x2_t vld2q_s8 result.val[1]
LD2 {Vt.16B - Vt2.16B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) Vt.16B →
ptr → Xn result.val[0]

Vt2.4H →
int16x4x2_t vld2_s16 result.val[1]
LD2 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) Vt.4H →
ptr → Xn result.val[0]

Vt2.8H →
int16x8x2_t vld2q_s16 result.val[1]
LD2 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) Vt.8H →
ptr → Xn result.val[0]

Vt2.2S →
int32x2x2_t vld2_s32 result.val[1]
LD2 {Vt.2S - Vt2.2S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) Vt.2S →
ptr → Xn result.val[0]

Vt2.4S →
int32x4x2_t vld2q_s32 result.val[1]
LD2 {Vt.4S - Vt2.4S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) Vt.4S →
ptr → Xn result.val[0]

Vt2.8B →
uint8x8x2_t vld2_u8 result.val[1]
LD2 {Vt.8B - Vt2.8B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) Vt.8B →
ptr → Xn result.val[0]

Vt2.16B →
uint8x16x2_t vld2q_u8 result.val[1]
LD2 {Vt.16B - Vt2.16B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) Vt.16B →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 195 of 348
Non-Confidential
 Vt2.4H →
uint16x4x2_t vld2_u16 result.val[1]
LD2 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) Vt.4H →
ptr → Xn result.val[0]

Vt2.8H →
uint16x8x2_t vld2q_u16 result.val[1]
LD2 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) Vt.8H →
ptr → Xn result.val[0]

Vt2.2S →
uint32x2x2_t vld2_u32 result.val[1]
LD2 {Vt.2S - Vt2.2S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) Vt.2S →
ptr → Xn result.val[0]

Vt2.4S →
uint32x4x2_t vld2q_u32 result.val[1]
LD2 {Vt.4S - Vt2.4S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) Vt.4S →
ptr → Xn result.val[0]

Vt2.4H →
float16x4x2_t vld2_f16 result.val[1]
LD2 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) Vt.4H →
ptr → Xn result.val[0]

Vt2.8H →
float16x8x2_t vld2q_f16 result.val[1]
LD2 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) Vt.8H →
ptr → Xn result.val[0]

Vt2.2S →
float32x2x2_t vld2_f32 result.val[1]
LD2 {Vt.2S - Vt2.2S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) Vt.2S →
ptr → Xn result.val[0]

Vt2.4S →
float32x4x2_t vld2q_f32 result.val[1]
LD2 {Vt.4S - Vt2.4S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) Vt.4S →
ptr → Xn result.val[0]

Vt2.8B →
poly8x8x2_t vld2_p8 result.val[1]
LD2 {Vt.8B - Vt2.8B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) Vt.8B →
ptr → Xn result.val[0]

Vt2.16B →
poly8x16x2_t vld2q_p8 result.val[1]
LD2 {Vt.16B - Vt2.16B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) Vt.16B →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 196 of 348
Non-Confidential
 Vt2.4H →
poly16x4x2_t vld2_p16 result.val[1]
LD2 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) Vt.4H →
ptr → Xn result.val[0]

Vt2.8H →
poly16x8x2_t vld2q_p16 result.val[1]
LD2 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) Vt.8H →
ptr → Xn result.val[0]

Vt2.1D →
int64x1x2_t vld2_s64 result.val[1]
LD1 {Vt.1D - Vt2.1D},[Xn] ARMv7, ARMv8
(int64_t const * ptr) Vt.1D →
ptr → Xn result.val[0]

Vt2.1D →
uint64x1x2_t vld2_u64 result.val[1]
LD1 {Vt.1D - Vt2.1D},[Xn] ARMv7, ARMv8
(uint64_t const * ptr) Vt.1D →
ptr → Xn result.val[0]

Vt2.1D →
poly64x1x2_t vld2_p64 result.val[1]
LD1 {Vt.1D - Vt2.1D},[Xn] ARMv8
(poly64_t const * ptr) Vt.1D →
ptr → Xn result.val[0]

Vt2.2D →
int64x2x2_t vld2q_s64 result.val[1]
LD2 {Vt.2D - Vt2.2D},[Xn] ARMv8(AArch64)
(int64_t const * ptr) Vt.2D →
ptr → Xn result.val[0]

Vt2.2D →
uint64x2x2_t vld2q_u64 result.val[1]
LD2 {Vt.2D - Vt2.2D},[Xn] ARMv8(AArch64)
(uint64_t const * ptr) Vt.2D →
ptr → Xn result.val[0]

Vt2.2D →
poly64x2x2_t vld2q_p64 result.val[1]
LD2 {Vt.2D - Vt2.2D},[Xn] ARMv8(AArch64)
(poly64_t const * ptr) Vt.2D →
ptr → Xn result.val[0]

Vt2.1D →
float64x1x2_t vld2_f64 result.val[1]
LD1 {Vt.1D - Vt2.1D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) Vt.1D →
ptr → Xn result.val[0]

Vt2.2D →
float64x2x2_t vld2q_f64 result.val[1]
LD2 {Vt.2D - Vt2.2D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) Vt.2D →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 197 of 348
Non-Confidential
 Vt3.8B →
result.val[2]
int8x8x3_t vld3_s8 Vt2.8B →
LD3 {Vt.8B - Vt3.8B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) result.val[1]
Vt.8B →
ptr → Xn result.val[0]

Vt3.16B →
result.val[2]
int8x16x3_t vld3q_s8 Vt2.16B →
LD3 {Vt.16B - Vt3.16B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) result.val[1]
Vt.16B →
ptr → Xn result.val[0]

Vt3.4H →
result.val[2]
int16x4x3_t vld3_s16 Vt2.4H →
LD3 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt3.8H →
result.val[2]
int16x8x3_t vld3q_s16 Vt2.8H →
LD3 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt3.2S →
result.val[2]
int32x2x3_t vld3_s32 Vt2.2S →
LD3 {Vt.2S - Vt3.2S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt3.4S →
result.val[2]
int32x4x3_t vld3q_s32 Vt2.4S →
LD3 {Vt.4S - Vt3.4S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt3.8B →
result.val[2]
uint8x8x3_t vld3_u8 Vt2.8B →
LD3 {Vt.8B - Vt3.8B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) result.val[1]
Vt.8B →
ptr → Xn result.val[0]

Vt3.16B →
result.val[2]
uint8x16x3_t vld3q_u8 Vt2.16B →
LD3 {Vt.16B - Vt3.16B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) result.val[1]
Vt.16B →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 198 of 348
Non-Confidential
 Vt3.4H →
result.val[2]
uint16x4x3_t vld3_u16 Vt2.4H →
LD3 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt3.8H →
result.val[2]
uint16x8x3_t vld3q_u16 Vt2.8H →
LD3 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt3.2S →
result.val[2]
uint32x2x3_t vld3_u32 Vt2.2S →
LD3 {Vt.2S - Vt3.2S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt3.4S →
result.val[2]
uint32x4x3_t vld3q_u32 Vt2.4S →
LD3 {Vt.4S - Vt3.4S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt3.4H →
result.val[2]
float16x4x3_t vld3_f16 Vt2.4H →
LD3 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt3.8H →
result.val[2]
float16x8x3_t vld3q_f16 Vt2.8H →
LD3 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt3.2S →
result.val[2]
float32x2x3_t vld3_f32 Vt2.2S →
LD3 {Vt.2S - Vt3.2S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt3.4S →
result.val[2]
float32x4x3_t vld3q_f32 Vt2.4S →
LD3 {Vt.4S - Vt3.4S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) result.val[1]
Vt.4S →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 199 of 348
Non-Confidential
 Vt3.8B →
result.val[2]
poly8x8x3_t vld3_p8 Vt2.8B →
LD3 {Vt.8B - Vt3.8B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) result.val[1]
Vt.8B →
ptr → Xn result.val[0]

Vt3.16B →
result.val[2]
poly8x16x3_t vld3q_p8 Vt2.16B →
LD3 {Vt.16B - Vt3.16B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) result.val[1]
Vt.16B →
ptr → Xn result.val[0]

Vt3.4H →
result.val[2]
poly16x4x3_t vld3_p16 Vt2.4H →
LD3 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt3.8H →
result.val[2]
poly16x8x3_t vld3q_p16 Vt2.8H →
LD3 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt3.1D →
result.val[2]
int64x1x3_t vld3_s64 Vt2.1D →
LD1 {Vt.1D - Vt3.1D},[Xn] ARMv7, ARMv8
(int64_t const * ptr) result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt3.1D →
result.val[2]
uint64x1x3_t vld3_u64 Vt2.1D →
LD1 {Vt.1D - Vt3.1D},[Xn] ARMv7, ARMv8
(uint64_t const * ptr) result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt3.1D →
result.val[2]
poly64x1x3_t vld3_p64 Vt2.1D →
LD1 {Vt.1D - Vt3.1D},[Xn] ARMv8
(poly64_t const * ptr) result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt3.2D →
result.val[2]
int64x2x3_t vld3q_s64 Vt2.2D →
LD3 {Vt.2D - Vt3.2D},[Xn] ARMv8(AArch64)
(int64_t const * ptr) result.val[1]
Vt.2D →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 200 of 348
Non-Confidential
 Vt3.2D →
result.val[2]
uint64x2x3_t vld3q_u64 Vt2.2D →
LD3 {Vt.2D - Vt3.2D},[Xn] ARMv8(AArch64)
(uint64_t const * ptr) result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt3.2D →
result.val[2]
poly64x2x3_t vld3q_p64 Vt2.2D →
LD3 {Vt.2D - Vt3.2D},[Xn] ARMv8(AArch64)
(poly64_t const * ptr) result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt3.1D →
result.val[2]
float64x1x3_t vld3_f64 Vt2.1D →
LD1 {Vt.1D - Vt3.1D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt3.2D →
result.val[2]
float64x2x3_t vld3q_f64 Vt2.2D →
LD3 {Vt.2D - Vt3.2D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt4.8B →
result.val[3]
Vt3.8B →
int8x8x4_t vld4_s8 result.val[2]
LD4 {Vt.8B - Vt4.8B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) Vt2.8B →
result.val[1]
Vt.8B →
ptr → Xn result.val[0]

Vt4.16B →
result.val[3]
Vt3.16B →
int8x16x4_t vld4q_s8 result.val[2]
LD4 {Vt.16B - Vt4.16B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) Vt2.16B →
result.val[1]
Vt.16B →
ptr → Xn result.val[0]

Vt4.4H →
result.val[3]
Vt3.4H →
int16x4x4_t vld4_s16 result.val[2]
LD4 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) Vt2.4H →
result.val[1]
Vt.4H →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 201 of 348
Non-Confidential
 Vt4.8H →
result.val[3]
Vt3.8H →
int16x8x4_t vld4q_s16 result.val[2]
LD4 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) Vt2.8H →
result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt4.2S →
result.val[3]
Vt3.2S →
int32x2x4_t vld4_s32 result.val[2]
LD4 {Vt.2S - Vt4.2S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) Vt2.2S →
result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt4.4S →
result.val[3]
Vt3.4S →
int32x4x4_t vld4q_s32 result.val[2]
LD4 {Vt.4S - Vt4.4S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) Vt2.4S →
result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt4.8B →
result.val[3]
Vt3.8B →
uint8x8x4_t vld4_u8 result.val[2]
LD4 {Vt.8B - Vt4.8B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) Vt2.8B →
result.val[1]
Vt.8B →
ptr → Xn result.val[0]

Vt4.16B →
result.val[3]
Vt3.16B →
uint8x16x4_t vld4q_u8 result.val[2]
LD4 {Vt.16B - Vt4.16B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) Vt2.16B →
result.val[1]
Vt.16B →
ptr → Xn result.val[0]

Vt4.4H →
result.val[3]
Vt3.4H →
uint16x4x4_t vld4_u16 result.val[2]
LD4 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) Vt2.4H →
result.val[1]
Vt.4H →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 202 of 348
Non-Confidential
 Vt4.8H →
result.val[3]
Vt3.8H →
uint16x8x4_t vld4q_u16 result.val[2]
LD4 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) Vt2.8H →
result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt4.2S →
result.val[3]
Vt3.2S →
uint32x2x4_t vld4_u32 result.val[2]
LD4 {Vt.2S - Vt4.2S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) Vt2.2S →
result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt4.4S →
result.val[3]
Vt3.4S →
uint32x4x4_t vld4q_u32 result.val[2]
LD4 {Vt.4S - Vt4.4S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) Vt2.4S →
result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt4.4H →
result.val[3]
Vt3.4H →
float16x4x4_t vld4_f16 result.val[2]
LD4 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) Vt2.4H →
result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt4.8H →
result.val[3]
Vt3.8H →
float16x8x4_t vld4q_f16 result.val[2]
LD4 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) Vt2.8H →
result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt4.2S →
result.val[3]
Vt3.2S →
float32x2x4_t vld4_f32 result.val[2]
LD4 {Vt.2S - Vt4.2S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) Vt2.2S →
result.val[1]
Vt.2S →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 203 of 348
Non-Confidential
 Vt4.4S →
result.val[3]
Vt3.4S →
float32x4x4_t vld4q_f32 result.val[2]
LD4 {Vt.4S - Vt4.4S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) Vt2.4S →
result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt4.8B →
result.val[3]
Vt3.8B →
poly8x8x4_t vld4_p8 result.val[2]
LD4 {Vt.8B - Vt4.8B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) Vt2.8B →
result.val[1]
Vt.8B →
ptr → Xn result.val[0]

Vt4.16B →
result.val[3]
Vt3.16B →
poly8x16x4_t vld4q_p8 result.val[2]
LD4 {Vt.16B - Vt4.16B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) Vt2.16B →
result.val[1]
Vt.16B →
ptr → Xn result.val[0]

Vt4.4H →
result.val[3]
Vt3.4H →
poly16x4x4_t vld4_p16 result.val[2]
LD4 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) Vt2.4H →
result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt4.8H →
result.val[3]
Vt3.8H →
poly16x8x4_t vld4q_p16 result.val[2]
LD4 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) Vt2.8H →
result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt4.1D →
result.val[3]
Vt3.1D →
int64x1x4_t vld4_s64 result.val[2]
LD1 {Vt.1D - Vt4.1D},[Xn] ARMv7, ARMv8
(int64_t const * ptr) Vt2.1D →
result.val[1]
Vt.1D →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 204 of 348
Non-Confidential
 Vt4.1D →
result.val[3]
Vt3.1D →
uint64x1x4_t vld4_u64 result.val[2]
LD1 {Vt.1D - Vt4.1D},[Xn] ARMv7, ARMv8
(uint64_t const * ptr) Vt2.1D →
result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt4.1D →
result.val[3]
Vt3.1D →
poly64x1x4_t vld4_p64 result.val[2]
LD1 {Vt.1D - Vt4.1D},[Xn] ARMv8
(poly64_t const * ptr) Vt2.1D →
result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt4.2D →
result.val[3]
Vt3.2D →
int64x2x4_t vld4q_s64 result.val[2]
LD4 {Vt.2D - Vt4.2D},[Xn] ARMv8(AArch64)
(int64_t const * ptr) Vt2.2D →
result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt4.2D →
result.val[3]
Vt3.2D →
uint64x2x4_t vld4q_u64 result.val[2]
LD4 {Vt.2D - Vt4.2D},[Xn] ARMv8(AArch64)
(uint64_t const * ptr) Vt2.2D →
result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt4.2D →
result.val[3]
Vt3.2D →
poly64x2x4_t vld4q_p64 result.val[2]
LD4 {Vt.2D - Vt4.2D},[Xn] ARMv8(AArch64)
(poly64_t const * ptr) Vt2.2D →
result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt4.1D →
result.val[3]
Vt3.1D →
float64x1x4_t vld4_f64 result.val[2]
LD1 {Vt.1D - Vt4.1D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) Vt2.1D →
result.val[1]
Vt.1D →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 205 of 348
Non-Confidential
 Vt4.2D →
result.val[3]
Vt3.2D →
float64x2x4_t vld4q_f64 result.val[2]
LD4 {Vt.2D - Vt4.2D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) Vt2.2D →
result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt2.8B →
int8x8x2_t vld2_dup_s8 result.val[1]
LD2R {Vt.8B - Vt2.8B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) Vt.8B →
ptr → Xn result.val[0]

Vt2.16B →
int8x16x2_t vld2q_dup_s8 result.val[1]
LD2R {Vt.16B - Vt2.16B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) Vt.16B →
ptr → Xn result.val[0]

Vt2.4H →
int16x4x2_t vld2_dup_s16 result.val[1]
LD2R {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) Vt.4H →
ptr → Xn result.val[0]

Vt2.8H →
int16x8x2_t vld2q_dup_s16 result.val[1]
LD2R {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) Vt.8H →
ptr → Xn result.val[0]

Vt2.2S →
int32x2x2_t vld2_dup_s32 result.val[1]
LD2R {Vt.2S - Vt2.2S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) Vt.2S →
ptr → Xn result.val[0]

Vt2.4S →
int32x4x2_t vld2q_dup_s32 result.val[1]
LD2R {Vt.4S - Vt2.4S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) Vt.4S →
ptr → Xn result.val[0]

Vt2.8B →
uint8x8x2_t vld2_dup_u8 result.val[1]
LD2R {Vt.8B - Vt2.8B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) Vt.8B →
ptr → Xn result.val[0]

Vt2.16B →
uint8x16x2_t vld2q_dup_u8 result.val[1]
LD2R {Vt.16B - Vt2.16B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) Vt.16B →
ptr → Xn result.val[0]

Vt2.4H →
uint16x4x2_t vld2_dup_u16 result.val[1]
LD2R {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) Vt.4H →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 206 of 348
Non-Confidential
 Vt2.8H →
uint16x8x2_t vld2q_dup_u16 result.val[1]
LD2R {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) Vt.8H →
ptr → Xn result.val[0]

Vt2.2S →
uint32x2x2_t vld2_dup_u32 result.val[1]
LD2R {Vt.2S - Vt2.2S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) Vt.2S →
ptr → Xn result.val[0]

Vt2.4S →
uint32x4x2_t vld2q_dup_u32 result.val[1]
LD2R {Vt.4S - Vt2.4S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) Vt.4S →
ptr → Xn result.val[0]

Vt2.4H →
float16x4x2_t vld2_dup_f16 result.val[1]
LD2R {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) Vt.4H →
ptr → Xn result.val[0]

Vt2.8H →
float16x8x2_t vld2q_dup_f16 result.val[1]
LD2R {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) Vt.8H →
ptr → Xn result.val[0]

Vt2.2S →
float32x2x2_t vld2_dup_f32 result.val[1]
LD2R {Vt.2S - Vt2.2S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) Vt.2S →
ptr → Xn result.val[0]

Vt2.4S →
float32x4x2_t vld2q_dup_f32 result.val[1]
LD2R {Vt.4S - Vt2.4S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) Vt.4S →
ptr → Xn result.val[0]

Vt2.8B →
poly8x8x2_t vld2_dup_p8 result.val[1]
LD2R {Vt.8B - Vt2.8B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) Vt.8B →
ptr → Xn result.val[0]

Vt2.16B →
poly8x16x2_t vld2q_dup_p8 result.val[1]
LD2R {Vt.16B - Vt2.16B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) Vt.16B →
ptr → Xn result.val[0]

Vt2.4H →
poly16x4x2_t vld2_dup_p16 result.val[1]
LD2R {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) Vt.4H →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 207 of 348
Non-Confidential
 Vt2.8H →
poly16x8x2_t vld2q_dup_p16 result.val[1]
LD2R {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) Vt.8H →
ptr → Xn result.val[0]

Vt2.1D →
int64x1x2_t vld2_dup_s64 result.val[1]
LD2R {Vt.1D - Vt2.1D},[Xn] ARMv7, ARMv8
(int64_t const * ptr) Vt.1D →
ptr → Xn result.val[0]

Vt2.1D →
uint64x1x2_t vld2_dup_u64 result.val[1]
LD2R {Vt.1D - Vt2.1D},[Xn] ARMv7, ARMv8
(uint64_t const * ptr) Vt.1D →
ptr → Xn result.val[0]

Vt2.1D →
poly64x1x2_t vld2_dup_p64 result.val[1]
LD2R {Vt.1D - Vt2.1D},[Xn] ARMv8
(poly64_t const * ptr) Vt.1D →
ptr → Xn result.val[0]

Vt2.2D →
int64x2x2_t vld2q_dup_s64 result.val[1]
LD2R {Vt.2D - Vt2.2D},[Xn] ARMv8(AArch64)
(int64_t const * ptr) Vt.2D →
ptr → Xn result.val[0]

Vt2.2D →
uint64x2x2_t vld2q_dup_u64 result.val[1]
LD2R {Vt.2D - Vt2.2D},[Xn] ARMv8(AArch64)
(uint64_t const * ptr) Vt.2D →
ptr → Xn result.val[0]

Vt2.2D →
poly64x2x2_t vld2q_dup_p64 result.val[1]
LD2R {Vt.2D - Vt2.2D},[Xn] ARMv8(AArch64)
(poly64_t const * ptr) Vt.2D →
ptr → Xn result.val[0]

Vt2.1D →
float64x1x2_t vld2_dup_f64 result.val[1]
LD2R {Vt.1D - Vt2.1D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) Vt.1D →
ptr → Xn result.val[0]

Vt2.2D →
float64x2x2_t vld2q_dup_f64 result.val[1]
LD2R {Vt.2D - Vt2.2D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) Vt.2D →
ptr → Xn result.val[0]

Vt3.8B →
result.val[2]
int8x8x3_t vld3_dup_s8 Vt2.8B →
LD3R {Vt.8B - Vt3.8B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) result.val[1]
Vt.8B →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 208 of 348
Non-Confidential
 Vt3.16B →
result.val[2]
int8x16x3_t vld3q_dup_s8 Vt2.16B →
LD3R {Vt.16B - Vt3.16B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) result.val[1]
Vt.16B →
ptr → Xn result.val[0]

Vt3.4H →
result.val[2]
int16x4x3_t vld3_dup_s16 Vt2.4H →
LD3R {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt3.8H →
result.val[2]
int16x8x3_t vld3q_dup_s16 Vt2.8H →
LD3R {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt3.2S →
result.val[2]
int32x2x3_t vld3_dup_s32 Vt2.2S →
LD3R {Vt.2S - Vt3.2S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt3.4S →
result.val[2]
int32x4x3_t vld3q_dup_s32 Vt2.4S →
LD3R {Vt.4S - Vt3.4S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt3.8B →
result.val[2]
uint8x8x3_t vld3_dup_u8 Vt2.8B →
LD3R {Vt.8B - Vt3.8B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) result.val[1]
Vt.8B →
ptr → Xn result.val[0]

Vt3.16B →
result.val[2]
uint8x16x3_t vld3q_dup_u8 Vt2.16B →
LD3R {Vt.16B - Vt3.16B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) result.val[1]
Vt.16B →
ptr → Xn result.val[0]

Vt3.4H →
result.val[2]
uint16x4x3_t vld3_dup_u16 Vt2.4H →
LD3R {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) result.val[1]
Vt.4H →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 209 of 348
Non-Confidential
 Vt3.8H →
result.val[2]
uint16x8x3_t vld3q_dup_u16 Vt2.8H →
LD3R {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt3.2S →
result.val[2]
uint32x2x3_t vld3_dup_u32 Vt2.2S →
LD3R {Vt.2S - Vt3.2S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt3.4S →
result.val[2]
uint32x4x3_t vld3q_dup_u32 Vt2.4S →
LD3R {Vt.4S - Vt3.4S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt3.4H →
result.val[2]
float16x4x3_t vld3_dup_f16 Vt2.4H →
LD3R {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt3.8H →
result.val[2]
float16x8x3_t vld3q_dup_f16 Vt2.8H →
LD3R {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt3.2S →
result.val[2]
float32x2x3_t vld3_dup_f32 Vt2.2S →
LD3R {Vt.2S - Vt3.2S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt3.4S →
result.val[2]
float32x4x3_t vld3q_dup_f32 Vt2.4S →
LD3R {Vt.4S - Vt3.4S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt3.8B →
result.val[2]
poly8x8x3_t vld3_dup_p8 Vt2.8B →
LD3R {Vt.8B - Vt3.8B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) result.val[1]
Vt.8B →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 210 of 348
Non-Confidential
 Vt3.16B →
result.val[2]
poly8x16x3_t vld3q_dup_p8 Vt2.16B →
LD3R {Vt.16B - Vt3.16B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) result.val[1]
Vt.16B →
ptr → Xn result.val[0]

Vt3.4H →
result.val[2]
poly16x4x3_t vld3_dup_p16 Vt2.4H →
LD3R {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt3.8H →
result.val[2]
poly16x8x3_t vld3q_dup_p16 Vt2.8H →
LD3R {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt3.1D →
result.val[2]
int64x1x3_t vld3_dup_s64 Vt2.1D →
LD3R {Vt.1D - Vt3.1D},[Xn] ARMv7, ARMv8
(int64_t const * ptr) result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt3.1D →
result.val[2]
uint64x1x3_t vld3_dup_u64 Vt2.1D →
LD3R {Vt.1D - Vt3.1D},[Xn] ARMv7, ARMv8
(uint64_t const * ptr) result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt3.1D →
result.val[2]
poly64x1x3_t vld3_dup_p64 Vt2.1D →
LD3R {Vt.1D - Vt3.1D},[Xn] ARMv8
(poly64_t const * ptr) result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt3.2D →
result.val[2]
int64x2x3_t vld3q_dup_s64 Vt2.2D →
LD3R {Vt.2D - Vt3.2D},[Xn] ARMv8(AArch64)
(int64_t const * ptr) result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt3.2D →
result.val[2]
uint64x2x3_t vld3q_dup_u64 Vt2.2D →
LD3R {Vt.2D - Vt3.2D},[Xn] ARMv8(AArch64)
(uint64_t const * ptr) result.val[1]
Vt.2D →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 211 of 348
Non-Confidential
 Vt3.2D →
result.val[2]
poly64x2x3_t vld3q_dup_p64 Vt2.2D →
LD3R {Vt.2D - Vt3.2D},[Xn] ARMv8(AArch64)
(poly64_t const * ptr) result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt3.1D →
result.val[2]
float64x1x3_t vld3_dup_f64 Vt2.1D →
LD3R {Vt.1D - Vt3.1D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt3.2D →
result.val[2]
float64x2x3_t vld3q_dup_f64 Vt2.2D →
LD3R {Vt.2D - Vt3.2D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt4.8B →
result.val[3]
Vt3.8B →
int8x8x4_t vld4_dup_s8 result.val[2]
LD4R {Vt.8B - Vt4.8B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) Vt2.8B →
result.val[1]
Vt.8B →
ptr → Xn result.val[0]

Vt4.16B →
result.val[3]
Vt3.16B →
int8x16x4_t vld4q_dup_s8 result.val[2]
LD4R {Vt.16B - Vt4.16B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) Vt2.16B →
result.val[1]
Vt.16B →
ptr → Xn result.val[0]

Vt4.4H →
result.val[3]
Vt3.4H →
int16x4x4_t vld4_dup_s16 result.val[2]
LD4R {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) Vt2.4H →
result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt4.8H →
result.val[3]
Vt3.8H →
int16x8x4_t vld4q_dup_s16 result.val[2]
LD4R {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) Vt2.8H →
result.val[1]
Vt.8H →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 212 of 348
Non-Confidential
 Vt4.2S →
result.val[3]
Vt3.2S →
int32x2x4_t vld4_dup_s32 result.val[2]
LD4R {Vt.2S - Vt4.2S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) Vt2.2S →
result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt4.4S →
result.val[3]
Vt3.4S →
int32x4x4_t vld4q_dup_s32 result.val[2]
LD4R {Vt.4S - Vt4.4S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) Vt2.4S →
result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt4.8B →
result.val[3]
Vt3.8B →
uint8x8x4_t vld4_dup_u8 result.val[2]
LD4R {Vt.8B - Vt4.8B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) Vt2.8B →
result.val[1]
Vt.8B →
ptr → Xn result.val[0]

Vt4.16B →
result.val[3]
Vt3.16B →
uint8x16x4_t vld4q_dup_u8 result.val[2]
LD4R {Vt.16B - Vt4.16B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) Vt2.16B →
result.val[1]
Vt.16B →
ptr → Xn result.val[0]

Vt4.4H →
result.val[3]
Vt3.4H →
uint16x4x4_t vld4_dup_u16 result.val[2]
LD4R {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) Vt2.4H →
result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt4.8H →
result.val[3]
Vt3.8H →
uint16x8x4_t vld4q_dup_u16 result.val[2]
LD4R {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) Vt2.8H →
result.val[1]
Vt.8H →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 213 of 348
Non-Confidential
 Vt4.2S →
result.val[3]
Vt3.2S →
uint32x2x4_t vld4_dup_u32 result.val[2]
LD4R {Vt.2S - Vt4.2S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) Vt2.2S →
result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt4.4S →
result.val[3]
Vt3.4S →
uint32x4x4_t vld4q_dup_u32 result.val[2]
LD4R {Vt.4S - Vt4.4S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) Vt2.4S →
result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt4.4H →
result.val[3]
Vt3.4H →
float16x4x4_t vld4_dup_f16 result.val[2]
LD4R {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) Vt2.4H →
result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt4.8H →
result.val[3]
Vt3.8H →
float16x8x4_t vld4q_dup_f16 result.val[2]
LD4R {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) Vt2.8H →
result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt4.2S →
result.val[3]
Vt3.2S →
float32x2x4_t vld4_dup_f32 result.val[2]
LD4R {Vt.2S - Vt4.2S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) Vt2.2S →
result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt4.4S →
result.val[3]
Vt3.4S →
float32x4x4_t vld4q_dup_f32 result.val[2]
LD4R {Vt.4S - Vt4.4S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) Vt2.4S →
result.val[1]
Vt.4S →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 214 of 348
Non-Confidential
 Vt4.8B →
result.val[3]
Vt3.8B →
poly8x8x4_t vld4_dup_p8 result.val[2]
LD4R {Vt.8B - Vt4.8B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) Vt2.8B →
result.val[1]
Vt.8B →
ptr → Xn result.val[0]

Vt4.16B →
result.val[3]
Vt3.16B →
poly8x16x4_t vld4q_dup_p8 result.val[2]
LD4R {Vt.16B - Vt4.16B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) Vt2.16B →
result.val[1]
Vt.16B →
ptr → Xn result.val[0]

Vt4.4H →
result.val[3]
Vt3.4H →
poly16x4x4_t vld4_dup_p16 result.val[2]
LD4R {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) Vt2.4H →
result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt4.8H →
result.val[3]
Vt3.8H →
poly16x8x4_t vld4q_dup_p16 result.val[2]
LD4R {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) Vt2.8H →
result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt4.1D →
result.val[3]
Vt3.1D →
int64x1x4_t vld4_dup_s64 result.val[2]
LD4R {Vt.1D - Vt4.1D},[Xn] ARMv7, ARMv8
(int64_t const * ptr) Vt2.1D →
result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt4.1D →
result.val[3]
Vt3.1D →
uint64x1x4_t vld4_dup_u64 result.val[2]
LD4R {Vt.1D - Vt4.1D},[Xn] ARMv7, ARMv8
(uint64_t const * ptr) Vt2.1D →
result.val[1]
Vt.1D →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 215 of 348
Non-Confidential
 Vt4.1D →
result.val[3]
Vt3.1D →
poly64x1x4_t vld4_dup_p64 result.val[2]
LD4R {Vt.1D - Vt4.1D},[Xn] ARMv8
(poly64_t const * ptr) Vt2.1D →
result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt4.2D →
result.val[3]
Vt3.2D →
int64x2x4_t vld4q_dup_s64 result.val[2]
LD4R {Vt.2D - Vt4.2D},[Xn] ARMv8(AArch64)
(int64_t const * ptr) Vt2.2D →
result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt4.2D →
result.val[3]
Vt3.2D →
uint64x2x4_t vld4q_dup_u64 result.val[2]
LD4R {Vt.2D - Vt4.2D},[Xn] ARMv8(AArch64)
(uint64_t const * ptr) Vt2.2D →
result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt4.2D →
result.val[3]
Vt3.2D →
poly64x2x4_t vld4q_dup_p64 result.val[2]
LD4R {Vt.2D - Vt4.2D},[Xn] ARMv8(AArch64)
(poly64_t const * ptr) Vt2.2D →
result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt4.1D →
result.val[3]
Vt3.1D →
float64x1x4_t vld4_dup_f64 result.val[2]
LD4R {Vt.1D - Vt4.1D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) Vt2.1D →
result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt4.2D →
result.val[3]
Vt3.2D →
float64x2x4_t vld4q_dup_f64 result.val[2]
LD4R {Vt.2D - Vt4.2D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) Vt2.2D →
result.val[1]
Vt.2D →
ptr → Xn result.val[0]

ptr → Xn
void vst2_s8
val.val[1] →
(int8_t * ptr, ST2 {Vt.8B - Vt2.8B},[Xn] ARMv7, ARMv8
Vt2.8B
int8x8x2_t val)
val.val[0] → Vt.8B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 216 of 348
Non-Confidential
 ptr → Xn
void vst2q_s8 val.val[1] →
(int8_t * ptr, Vt2.16B ST2 {Vt.16B - Vt2.16B},[Xn] ARMv7, ARMv8
int8x16x2_t val) val.val[0] →
Vt.16B

ptr → Xn
void vst2_s16
val.val[1] →
(int16_t * ptr, ST2 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
Vt2.4H
int16x4x2_t val)
val.val[0] → Vt.4H

ptr → Xn
void vst2q_s16
val.val[1] →
(int16_t * ptr, ST2 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
Vt2.8H
int16x8x2_t val)
val.val[0] → Vt.8H

ptr → Xn
void vst2_s32
val.val[1] →
(int32_t * ptr, ST2 {Vt.2S - Vt2.2S},[Xn] ARMv7, ARMv8
Vt2.2S
int32x2x2_t val)
val.val[0] → Vt.2S

ptr → Xn
void vst2q_s32
val.val[1] →
(int32_t * ptr, ST2 {Vt.4S - Vt2.4S},[Xn] ARMv7, ARMv8
Vt2.4S
int32x4x2_t val)
val.val[0] → Vt.4S

ptr → Xn
void vst2_u8
val.val[1] →
(uint8_t * ptr, ST2 {Vt.8B - Vt2.8B},[Xn] ARMv7, ARMv8
Vt2.8B
uint8x8x2_t val)
val.val[0] → Vt.8B

ptr → Xn
void vst2q_u8 val.val[1] →
(uint8_t * ptr, Vt2.16B ST2 {Vt.16B - Vt2.16B},[Xn] ARMv7, ARMv8
uint8x16x2_t val) val.val[0] →
Vt.16B

ptr → Xn
void vst2_u16
val.val[1] →
(uint16_t * ptr, ST2 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
Vt2.4H
uint16x4x2_t val)
val.val[0] → Vt.4H

ptr → Xn
void vst2q_u16
val.val[1] →
(uint16_t * ptr, ST2 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
Vt2.8H
uint16x8x2_t val)
val.val[0] → Vt.8H

ptr → Xn
void vst2_u32
val.val[1] →
(uint32_t * ptr, ST2 {Vt.2S - Vt2.2S},[Xn] ARMv7, ARMv8
Vt2.2S
uint32x2x2_t val)
val.val[0] → Vt.2S

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Non-Confidential
 ptr → Xn
void vst2q_u32
val.val[1] →
(uint32_t * ptr, ST2 {Vt.4S - Vt2.4S},[Xn] ARMv7, ARMv8
Vt2.4S
uint32x4x2_t val)
val.val[0] → Vt.4S

ptr → Xn
void vst2_f16
val.val[1] →
(float16_t * ptr, ST2 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
Vt2.4H
float16x4x2_t val)
val.val[0] → Vt.4H

ptr → Xn
void vst2q_f16
val.val[1] →
(float16_t * ptr, ST2 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
Vt2.8H
float16x8x2_t val)
val.val[0] → Vt.8H

ptr → Xn
void vst2_f32
val.val[1] →
(float32_t * ptr, ST2 {Vt.2S - Vt2.2S},[Xn] ARMv7, ARMv8
Vt2.2S
float32x2x2_t val)
val.val[0] → Vt.2S

ptr → Xn
void vst2q_f32
val.val[1] →
(float32_t * ptr, ST2 {Vt.4S - Vt2.4S},[Xn] ARMv7, ARMv8
Vt2.4S
float32x4x2_t val)
val.val[0] → Vt.4S

ptr → Xn
void vst2_p8
val.val[1] →
(poly8_t * ptr, ST2 {Vt.8B - Vt2.8B},[Xn] ARMv7, ARMv8
Vt2.8B
poly8x8x2_t val)
val.val[0] → Vt.8B

ptr → Xn
void vst2q_p8 val.val[1] →
(poly8_t * ptr, Vt2.16B ST2 {Vt.16B - Vt2.16B},[Xn] ARMv7, ARMv8
poly8x16x2_t val) val.val[0] →
Vt.16B

ptr → Xn
void vst2_p16
val.val[1] →
(poly16_t * ptr, ST2 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
Vt2.4H
poly16x4x2_t val)
val.val[0] → Vt.4H

ptr → Xn
void vst2q_p16
val.val[1] →
(poly16_t * ptr, ST2 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
Vt2.8H
poly16x8x2_t val)
val.val[0] → Vt.8H

ptr → Xn
void vst2_s64
val.val[1] →
(int64_t * ptr, ST1 {Vt.1D - Vt2.1D},[Xn] ARMv7, ARMv8
Vt2.1D
int64x1x2_t val)
val.val[0] → Vt.1D

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Non-Confidential
 ptr → Xn
void vst2_u64
val.val[1] →
(uint64_t * ptr, ST1 {Vt.1D - Vt2.1D},[Xn] ARMv7, ARMv8
Vt2.1D
uint64x1x2_t val)
val.val[0] → Vt.1D

ptr → Xn
void vst2_p64
val.val[1] →
(poly64_t * ptr, ST1 {Vt.1D - Vt2.1D},[Xn] ARMv8
Vt2.1D
poly64x1x2_t val)
val.val[0] → Vt.1D

ptr → Xn
void vst2q_s64
val.val[1] →
(int64_t * ptr, ST2 {Vt.2D - Vt2.2D},[Xn] ARMv8(AArch64)
Vt2.2D
int64x2x2_t val)
val.val[0] → Vt.2D

ptr → Xn
void vst2q_u64
val.val[1] →
(uint64_t * ptr, ST2 {Vt.2D - Vt2.2D},[Xn] ARMv8(AArch64)
Vt2.2D
uint64x2x2_t val)
val.val[0] → Vt.2D

ptr → Xn
void vst2q_p64
val.val[1] →
(poly64_t * ptr, ST2 {Vt.2D - Vt2.2D},[Xn] ARMv8(AArch64)
Vt2.2D
poly64x2x2_t val)
val.val[0] → Vt.2D

ptr → Xn
void vst2_f64
val.val[1] →
(float64_t * ptr, ST1 {Vt.1D - Vt2.1D},[Xn] ARMv8(AArch64)
Vt2.1D
float64x1x2_t val)
val.val[0] → Vt.1D

ptr → Xn
void vst2q_f64
val.val[1] →
(float64_t * ptr, ST2 {Vt.2D - Vt2.2D},[Xn] ARMv8(AArch64)
Vt2.2D
float64x2x2_t val)
val.val[0] → Vt.2D

ptr → Xn
val.val[2] →
void vst3_s8
Vt3.8B
(int8_t * ptr, ST3 {Vt.8B - Vt3.8B},[Xn] ARMv7, ARMv8
val.val[1] →
int8x8x3_t val)
Vt2.8B
val.val[0] → Vt.8B

ptr → Xn
val.val[2] →
void vst3q_s8 Vt3.16B
(int8_t * ptr, val.val[1] → ST3 {Vt.16B - Vt3.16B},[Xn] ARMv7, ARMv8
int8x16x3_t val) Vt2.16B
val.val[0] →
Vt.16B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 219 of 348
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 ptr → Xn
val.val[2] →
void vst3_s16
Vt3.4H
(int16_t * ptr, ST3 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
val.val[1] →
int16x4x3_t val)
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[2] →
void vst3q_s16
Vt3.8H
(int16_t * ptr, ST3 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
val.val[1] →
int16x8x3_t val)
Vt2.8H
val.val[0] → Vt.8H

ptr → Xn
val.val[2] →
void vst3_s32
Vt3.2S
(int32_t * ptr, ST3 {Vt.2S - Vt3.2S},[Xn] ARMv7, ARMv8
val.val[1] →
int32x2x3_t val)
Vt2.2S
val.val[0] → Vt.2S

ptr → Xn
val.val[2] →
void vst3q_s32
Vt3.4S
(int32_t * ptr, ST3 {Vt.4S - Vt3.4S},[Xn] ARMv7, ARMv8
val.val[1] →
int32x4x3_t val)
Vt2.4S
val.val[0] → Vt.4S

ptr → Xn
val.val[2] →
void vst3_u8
Vt3.8B
(uint8_t * ptr, ST3 {Vt.8B - Vt3.8B},[Xn] ARMv7, ARMv8
val.val[1] →
uint8x8x3_t val)
Vt2.8B
val.val[0] → Vt.8B

ptr → Xn
val.val[2] →
void vst3q_u8 Vt3.16B
(uint8_t * ptr, val.val[1] → ST3 {Vt.16B - Vt3.16B},[Xn] ARMv7, ARMv8
uint8x16x3_t val) Vt2.16B
val.val[0] →
Vt.16B

ptr → Xn
val.val[2] →
void vst3_u16
Vt3.4H
(uint16_t * ptr, ST3 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
val.val[1] →
uint16x4x3_t val)
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[2] →
void vst3q_u16
Vt3.8H
(uint16_t * ptr, ST3 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
val.val[1] →
uint16x8x3_t val)
Vt2.8H
val.val[0] → Vt.8H

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 220 of 348
Non-Confidential
 ptr → Xn
val.val[2] →
void vst3_u32
Vt3.2S
(uint32_t * ptr, ST3 {Vt.2S - Vt3.2S},[Xn] ARMv7, ARMv8
val.val[1] →
uint32x2x3_t val)
Vt2.2S
val.val[0] → Vt.2S

ptr → Xn
val.val[2] →
void vst3q_u32
Vt3.4S
(uint32_t * ptr, ST3 {Vt.4S - Vt3.4S},[Xn] ARMv7, ARMv8
val.val[1] →
uint32x4x3_t val)
Vt2.4S
val.val[0] → Vt.4S

ptr → Xn
val.val[2] →
void vst3_f16
Vt3.4H
(float16_t * ptr, ST3 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
val.val[1] →
float16x4x3_t val)
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[2] →
void vst3q_f16
Vt3.8H
(float16_t * ptr, ST3 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
val.val[1] →
float16x8x3_t val)
Vt2.8H
val.val[0] → Vt.8H

ptr → Xn
val.val[2] →
void vst3_f32
Vt3.2S
(float32_t * ptr, ST3 {Vt.2S - Vt3.2S},[Xn] ARMv7, ARMv8
val.val[1] →
float32x2x3_t val)
Vt2.2S
val.val[0] → Vt.2S

ptr → Xn
val.val[2] →
void vst3q_f32
Vt3.4S
(float32_t * ptr, ST3 {Vt.4S - Vt3.4S},[Xn] ARMv7, ARMv8
val.val[1] →
float32x4x3_t val)
Vt2.4S
val.val[0] → Vt.4S

ptr → Xn
val.val[2] →
void vst3_p8
Vt3.8B
(poly8_t * ptr, ST3 {Vt.8B - Vt3.8B},[Xn] ARMv7, ARMv8
val.val[1] →
poly8x8x3_t val)
Vt2.8B
val.val[0] → Vt.8B

ptr → Xn
val.val[2] →
void vst3q_p8 Vt3.16B
(poly8_t * ptr, val.val[1] → ST3 {Vt.16B - Vt3.16B},[Xn] ARMv7, ARMv8
poly8x16x3_t val) Vt2.16B
val.val[0] →
Vt.16B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 221 of 348
Non-Confidential
 ptr → Xn
val.val[2] →
void vst3_p16
Vt3.4H
(poly16_t * ptr, ST3 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
val.val[1] →
poly16x4x3_t val)
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[2] →
void vst3q_p16
Vt3.8H
(poly16_t * ptr, ST3 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
val.val[1] →
poly16x8x3_t val)
Vt2.8H
val.val[0] → Vt.8H

ptr → Xn
val.val[2] →
void vst3_s64
Vt3.1D
(int64_t * ptr, ST1 {Vt.1D - Vt3.1D},[Xn] ARMv7, ARMv8
val.val[1] →
int64x1x3_t val)
Vt2.1D
val.val[0] → Vt.1D

ptr → Xn
val.val[2] →
void vst3_u64
Vt3.1D
(uint64_t * ptr, ST1 {Vt.1D - Vt3.1D},[Xn] ARMv7, ARMv8
val.val[1] →
uint64x1x3_t val)
Vt2.1D
val.val[0] → Vt.1D

ptr → Xn
val.val[2] →
void vst3_p64
Vt3.1D
(poly64_t * ptr, ST1 {Vt.1D - Vt3.1D},[Xn] ARMv8
val.val[1] →
poly64x1x3_t val)
Vt2.1D
val.val[0] → Vt.1D

ptr → Xn
val.val[2] →
void vst3q_s64
Vt3.2D
(int64_t * ptr, ST3 {Vt.2D - Vt3.2D},[Xn] ARMv8(AArch64)
val.val[1] →
int64x2x3_t val)
Vt2.2D
val.val[0] → Vt.2D

ptr → Xn
val.val[2] →
void vst3q_u64
Vt3.2D
(uint64_t * ptr, ST3 {Vt.2D - Vt3.2D},[Xn] ARMv8(AArch64)
val.val[1] →
uint64x2x3_t val)
Vt2.2D
val.val[0] → Vt.2D

ptr → Xn
val.val[2] →
void vst3q_p64
Vt3.2D
(poly64_t * ptr, ST3 {Vt.2D - Vt3.2D},[Xn] ARMv8(AArch64)
val.val[1] →
poly64x2x3_t val)
Vt2.2D
val.val[0] → Vt.2D

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 222 of 348
Non-Confidential
 ptr → Xn
val.val[2] →
void vst3_f64
Vt3.1D
(float64_t * ptr, ST1 {Vt.1D - Vt3.1D},[Xn] ARMv8(AArch64)
val.val[1] →
float64x1x3_t val)
Vt2.1D
val.val[0] → Vt.1D

ptr → Xn
val.val[2] →
void vst3q_f64
Vt3.2D
(float64_t * ptr, ST3 {Vt.2D - Vt3.2D},[Xn] ARMv8(AArch64)
val.val[1] →
float64x2x3_t val)
Vt2.2D
val.val[0] → Vt.2D

ptr → Xn
val.val[3] →
Vt4.8B
void vst4_s8
val.val[2] →
(int8_t * ptr, ST4 {Vt.8B - Vt4.8B},[Xn] ARMv7, ARMv8
Vt3.8B
int8x8x4_t val)
val.val[1] →
Vt2.8B
val.val[0] → Vt.8B

ptr → Xn
val.val[3] →
Vt4.16B
void vst4q_s8 val.val[2] →
(int8_t * ptr, Vt3.16B ST4 {Vt.16B - Vt4.16B},[Xn] ARMv7, ARMv8
int8x16x4_t val) val.val[1] →
Vt2.16B
val.val[0] →
Vt.16B

ptr → Xn
val.val[3] →
Vt4.4H
void vst4_s16
val.val[2] →
(int16_t * ptr, ST4 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
Vt3.4H
int16x4x4_t val)
val.val[1] →
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[3] →
Vt4.8H
void vst4q_s16
val.val[2] →
(int16_t * ptr, ST4 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
Vt3.8H
int16x8x4_t val)
val.val[1] →
Vt2.8H
val.val[0] → Vt.8H

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 223 of 348
Non-Confidential
 ptr → Xn
val.val[3] →
Vt4.2S
void vst4_s32
val.val[2] →
(int32_t * ptr, ST4 {Vt.2S - Vt4.2S},[Xn] ARMv7, ARMv8
Vt3.2S
int32x2x4_t val)
val.val[1] →
Vt2.2S
val.val[0] → Vt.2S

ptr → Xn
val.val[3] →
Vt4.4S
void vst4q_s32
val.val[2] →
(int32_t * ptr, ST4 {Vt.4S - Vt4.4S},[Xn] ARMv7, ARMv8
Vt3.4S
int32x4x4_t val)
val.val[1] →
Vt2.4S
val.val[0] → Vt.4S

ptr → Xn
val.val[3] →
Vt4.8B
void vst4_u8
val.val[2] →
(uint8_t * ptr, ST4 {Vt.8B - Vt4.8B},[Xn] ARMv7, ARMv8
Vt3.8B
uint8x8x4_t val)
val.val[1] →
Vt2.8B
val.val[0] → Vt.8B

ptr → Xn
val.val[3] →
Vt4.16B
void vst4q_u8 val.val[2] →
(uint8_t * ptr, Vt3.16B ST4 {Vt.16B - Vt4.16B},[Xn] ARMv7, ARMv8
uint8x16x4_t val) val.val[1] →
Vt2.16B
val.val[0] →
Vt.16B

ptr → Xn
val.val[3] →
Vt4.4H
void vst4_u16
val.val[2] →
(uint16_t * ptr, ST4 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
Vt3.4H
uint16x4x4_t val)
val.val[1] →
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[3] →
Vt4.8H
void vst4q_u16
val.val[2] →
(uint16_t * ptr, ST4 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
Vt3.8H
uint16x8x4_t val)
val.val[1] →
Vt2.8H
val.val[0] → Vt.8H

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 224 of 348
Non-Confidential
 ptr → Xn
val.val[3] →
Vt4.2S
void vst4_u32
val.val[2] →
(uint32_t * ptr, ST4 {Vt.2S - Vt4.2S},[Xn] ARMv7, ARMv8
Vt3.2S
uint32x2x4_t val)
val.val[1] →
Vt2.2S
val.val[0] → Vt.2S

ptr → Xn
val.val[3] →
Vt4.4S
void vst4q_u32
val.val[2] →
(uint32_t * ptr, ST4 {Vt.4S - Vt4.4S},[Xn] ARMv7, ARMv8
Vt3.4S
uint32x4x4_t val)
val.val[1] →
Vt2.4S
val.val[0] → Vt.4S

ptr → Xn
val.val[3] →
Vt4.4H
void vst4_f16
val.val[2] →
(float16_t * ptr, ST4 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
Vt3.4H
float16x4x4_t val)
val.val[1] →
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[3] →
Vt4.8H
void vst4q_f16
val.val[2] →
(float16_t * ptr, ST4 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
Vt3.8H
float16x8x4_t val)
val.val[1] →
Vt2.8H
val.val[0] → Vt.8H

ptr → Xn
val.val[3] →
Vt4.2S
void vst4_f32
val.val[2] →
(float32_t * ptr, ST4 {Vt.2S - Vt4.2S},[Xn] ARMv7, ARMv8
Vt3.2S
float32x2x4_t val)
val.val[1] →
Vt2.2S
val.val[0] → Vt.2S

ptr → Xn
val.val[3] →
Vt4.4S
void vst4q_f32
val.val[2] →
(float32_t * ptr, ST4 {Vt.4S - Vt4.4S},[Xn] ARMv7, ARMv8
Vt3.4S
float32x4x4_t val)
val.val[1] →
Vt2.4S
val.val[0] → Vt.4S

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 225 of 348
Non-Confidential
 ptr → Xn
val.val[3] →
Vt4.8B
void vst4_p8
val.val[2] →
(poly8_t * ptr, ST4 {Vt.8B - Vt4.8B},[Xn] ARMv7, ARMv8
Vt3.8B
poly8x8x4_t val)
val.val[1] →
Vt2.8B
val.val[0] → Vt.8B

ptr → Xn
val.val[3] →
Vt4.16B
void vst4q_p8 val.val[2] →
(poly8_t * ptr, Vt3.16B ST4 {Vt.16B - Vt4.16B},[Xn] ARMv7, ARMv8
poly8x16x4_t val) val.val[1] →
Vt2.16B
val.val[0] →
Vt.16B

ptr → Xn
val.val[3] →
Vt4.4H
void vst4_p16
val.val[2] →
(poly16_t * ptr, ST4 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
Vt3.4H
poly16x4x4_t val)
val.val[1] →
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[3] →
Vt4.8H
void vst4q_p16
val.val[2] →
(poly16_t * ptr, ST4 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
Vt3.8H
poly16x8x4_t val)
val.val[1] →
Vt2.8H
val.val[0] → Vt.8H

ptr → Xn
val.val[3] →
Vt4.1D
void vst4_s64
val.val[2] →
(int64_t * ptr, ST1 {Vt.1D - Vt4.1D},[Xn] ARMv7, ARMv8
Vt3.1D
int64x1x4_t val)
val.val[1] →
Vt2.1D
val.val[0] → Vt.1D

ptr → Xn
val.val[3] →
Vt4.1D
void vst4_u64
val.val[2] →
(uint64_t * ptr, ST1 {Vt.1D - Vt4.1D},[Xn] ARMv7, ARMv8
Vt3.1D
uint64x1x4_t val)
val.val[1] →
Vt2.1D
val.val[0] → Vt.1D

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 226 of 348
Non-Confidential
 ptr → Xn
val.val[3] →
Vt4.1D
void vst4_p64
val.val[2] →
(poly64_t * ptr, ST1 {Vt.1D - Vt4.1D},[Xn] ARMv8
Vt3.1D
poly64x1x4_t val)
val.val[1] →
Vt2.1D
val.val[0] → Vt.1D

ptr → Xn
val.val[3] →
Vt4.2D
void vst4q_s64
val.val[2] →
(int64_t * ptr, ST4 {Vt.2D - Vt4.2D},[Xn] ARMv8(AArch64)
Vt3.2D
int64x2x4_t val)
val.val[1] →
Vt2.2D
val.val[0] → Vt.2D

ptr → Xn
val.val[3] →
Vt4.2D
void vst4q_u64
val.val[2] →
(uint64_t * ptr, ST4 {Vt.2D - Vt4.2D},[Xn] ARMv8(AArch64)
Vt3.2D
uint64x2x4_t val)
val.val[1] →
Vt2.2D
val.val[0] → Vt.2D

ptr → Xn
val.val[3] →
Vt4.2D
void vst4q_p64
val.val[2] →
(poly64_t * ptr, ST4 {Vt.2D - Vt4.2D},[Xn] ARMv8(AArch64)
Vt3.2D
poly64x2x4_t val)
val.val[1] →
Vt2.2D
val.val[0] → Vt.2D

ptr → Xn
val.val[3] →
Vt4.1D
void vst4_f64
val.val[2] →
(float64_t * ptr, ST1 {Vt.1D - Vt4.1D},[Xn] ARMv8(AArch64)
Vt3.1D
float64x1x4_t val)
val.val[1] →
Vt2.1D
val.val[0] → Vt.1D

ptr → Xn
val.val[3] →
Vt4.2D
void vst4q_f64
val.val[2] →
(float64_t * ptr, ST4 {Vt.2D - Vt4.2D},[Xn] ARMv8(AArch64)
Vt3.2D
float64x2x4_t val)
val.val[1] →
Vt2.2D
val.val[0] → Vt.2D

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 227 of 348
Non-Confidential
 ptr → Xn
int16x4x2_t vld2_lane_s16 Vt2.4H →
src.val[1] →
(int16_t const * ptr, result.val[1]
Vt2.4H LD2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
int16x4x2_t src, Vt.4H →
src.val[0] → Vt.4H
const int lane) result.val[0]
0 <= lane <= 3

ptr → Xn
int16x8x2_t vld2q_lane_s16 Vt2.8H →
src.val[1] →
(int16_t const * ptr, result.val[1]
Vt2.8H LD2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
int16x8x2_t src, Vt.8H →
src.val[0] → Vt.8H
const int lane) result.val[0]
0 <= lane <= 7

ptr → Xn
int32x2x2_t vld2_lane_s32 Vt2.2S →
src.val[1] →
(int32_t const * ptr, result.val[1]
Vt2.2S LD2 {Vt.s - Vt2.s}[lane],[Xn] ARMv7, ARMv8
int32x2x2_t src, Vt.2S →
src.val[0] → Vt.2S
const int lane) result.val[0]
0 <= lane <= 1

ptr → Xn
int32x4x2_t vld2q_lane_s32 Vt2.4S →
src.val[1] →
(int32_t const * ptr, result.val[1]
Vt2.4S LD2 {Vt.s - Vt2.s}[lane],[Xn] ARMv7, ARMv8
int32x4x2_t src, Vt.4S →
src.val[0] → Vt.4S
const int lane) result.val[0]
0 <= lane <= 3

ptr → Xn
uint16x4x2_t vld2_lane_u16 Vt2.4H →
src.val[1] →
(uint16_t const * ptr, result.val[1]
Vt2.4H LD2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
uint16x4x2_t src, Vt.4H →
src.val[0] → Vt.4H
const int lane) result.val[0]
0 <= lane <= 3

ptr → Xn
uint16x8x2_t vld2q_lane_u16 Vt2.8H →
src.val[1] →
(uint16_t const * ptr, result.val[1]
Vt2.8H LD2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
uint16x8x2_t src, Vt.8H →
src.val[0] → Vt.8H
const int lane) result.val[0]
0 <= lane <= 7

ptr → Xn
uint32x2x2_t vld2_lane_u32 Vt2.2S →
src.val[1] →
(uint32_t const * ptr, result.val[1]
Vt2.2S LD2 {Vt.s - Vt2.s}[lane],[Xn] ARMv7, ARMv8
uint32x2x2_t src, Vt.2S →
src.val[0] → Vt.2S
const int lane) result.val[0]
0 <= lane <= 1

ptr → Xn
uint32x4x2_t vld2q_lane_u32 Vt2.4S →
src.val[1] →
(uint32_t const * ptr, result.val[1]
Vt2.4S LD2 {Vt.s - Vt2.s}[lane],[Xn] ARMv7, ARMv8
uint32x4x2_t src, Vt.4S →
src.val[0] → Vt.4S
const int lane) result.val[0]
0 <= lane <= 3

ptr → Xn
float16x4x2_t vld2_lane_f16 Vt2.4H →
src.val[1] →
(float16_t const * ptr, result.val[1]
Vt2.4H LD2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
float16x4x2_t src, Vt.4H →
src.val[0] → Vt.4H
const int lane) result.val[0]
0 <= lane <= 3

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Non-Confidential
 ptr → Xn
float16x8x2_t vld2q_lane_f16 Vt2.8H →
src.val[1] →
(float16_t const * ptr, result.val[1]
Vt2.8H LD2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
float16x8x2_t src, Vt.8H →
src.val[0] → Vt.8H
const int lane) result.val[0]
0 <= lane <= 7

ptr → Xn
float32x2x2_t vld2_lane_f32 Vt2.2S →
src.val[1] →
(float32_t const * ptr, result.val[1]
Vt2.2S LD2 {Vt.s - Vt2.s}[lane],[Xn] ARMv7, ARMv8
float32x2x2_t src, Vt.2S →
src.val[0] → Vt.2S
const int lane) result.val[0]
0 <= lane <= 1

ptr → Xn
float32x4x2_t vld2q_lane_f32 Vt2.4S →
src.val[1] →
(float32_t const * ptr, result.val[1]
Vt2.4S LD2 {Vt.s - Vt2.s}[lane],[Xn] ARMv7, ARMv8
float32x4x2_t src, Vt.4S →
src.val[0] → Vt.4S
const int lane) result.val[0]
0 <= lane <= 3

ptr → Xn
poly16x4x2_t vld2_lane_p16 Vt2.4H →
src.val[1] →
(poly16_t const * ptr, result.val[1]
Vt2.4H LD2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
poly16x4x2_t src, Vt.4H →
src.val[0] → Vt.4H
const int lane) result.val[0]
0 <= lane <= 3

ptr → Xn
poly16x8x2_t vld2q_lane_p16 Vt2.8H →
src.val[1] →
(poly16_t const * ptr, result.val[1]
Vt2.8H LD2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
poly16x8x2_t src, Vt.8H →
src.val[0] → Vt.8H
const int lane) result.val[0]
0 <= lane <= 7

ptr → Xn
int8x8x2_t vld2_lane_s8 Vt2.8B →
src.val[1] →
(int8_t const * ptr, result.val[1]
Vt2.8B LD2 {Vt.b - Vt2.b}[lane],[Xn] ARMv7, ARMv8
int8x8x2_t src, Vt.8B →
src.val[0] → Vt.8B
const int lane) result.val[0]
0 <= lane <= 7

ptr → Xn
uint8x8x2_t vld2_lane_u8 Vt2.8B →
src.val[1] →
(uint8_t const * ptr, result.val[1]
Vt2.8B LD2 {Vt.b - Vt2.b}[lane],[Xn] ARMv7, ARMv8
uint8x8x2_t src, Vt.8B →
src.val[0] → Vt.8B
const int lane) result.val[0]
0 <= lane <= 7

ptr → Xn
poly8x8x2_t vld2_lane_p8 Vt2.8B →
src.val[1] →
(poly8_t const * ptr, result.val[1]
Vt2.8B LD2 {Vt.b - Vt2.b}[lane],[Xn] ARMv7, ARMv8
poly8x8x2_t src, Vt.8B →
src.val[0] → Vt.8B
const int lane) result.val[0]
0 <= lane <= 7

ptr → Xn
int8x16x2_t vld2q_lane_s8 src.val[1] → Vt2.16B →
(int8_t const * ptr, Vt2.16B result.val[1]
LD2 {Vt.b - Vt2.b}[lane],[Xn] ARMv8(AArch64)
int8x16x2_t src, src.val[0] → Vt.16B →
const int lane) Vt.16B result.val[0]
0 <= lane <= 15

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 229 of 348
Non-Confidential
 ptr → Xn
uint8x16x2_t vld2q_lane_u8 src.val[1] → Vt2.16B →
(uint8_t const * ptr, Vt2.16B result.val[1]
LD2 {Vt.b - Vt2.b}[lane],[Xn] ARMv8(AArch64)
uint8x16x2_t src, src.val[0] → Vt.16B →
const int lane) Vt.16B result.val[0]
0 <= lane <= 15

ptr → Xn
poly8x16x2_t vld2q_lane_p8 src.val[1] → Vt2.16B →
(poly8_t const * ptr, Vt2.16B result.val[1]
LD2 {Vt.b - Vt2.b}[lane],[Xn] ARMv8(AArch64)
poly8x16x2_t src, src.val[0] → Vt.16B →
const int lane) Vt.16B result.val[0]
0 <= lane <= 15

ptr → Xn ptr → Xn
int64x1x2_t vld2_lane_s64
src.val[1] → Vt2.1D →
(int64_t const * ptr,
Vt2.1D LD2 {Vt.d - Vt2.d}[lane],[Xn] result.val[1] ARMv8(AArch64)
int64x1x2_t src,
src.val[0] → Vt.1D Vt.1D →
const int lane)
lane == 0 result.val[0]

ptr → Xn ptr → Xn
int64x2x2_t vld2q_lane_s64
src.val[1] → Vt2.2D →
(int64_t const * ptr,
Vt2.2D LD2 {Vt.d - Vt2.d}[lane],[Xn] result.val[1] ARMv8(AArch64)
int64x2x2_t src,
src.val[0] → Vt.2D Vt.2D →
const int lane)
0 <= lane <= 1 result.val[0]

ptr → Xn
uint64x1x2_t vld2_lane_u64 Vt2.1D →
src.val[1] →
(uint64_t const * ptr, result.val[1]
Vt2.1D LD2 {Vt.d - Vt2.d}[lane],[Xn] ARMv8(AArch64)
uint64x1x2_t src, Vt.1D →
src.val[0] → Vt.1D
const int lane) result.val[0]
lane == 0

ptr → Xn
uint64x2x2_t vld2q_lane_u64 Vt2.2D →
src.val[1] →
(uint64_t const * ptr, result.val[1]
Vt2.2D LD2 {Vt.d - Vt2.d}[lane],[Xn] ARMv8(AArch64)
uint64x2x2_t src, Vt.2D →
src.val[0] → Vt.2D
const int lane) result.val[0]
0 <= lane <= 1

ptr → Xn
poly64x1x2_t vld2_lane_p64 Vt2.1D →
src.val[1] →
(poly64_t const * ptr, result.val[1]
Vt2.1D LD2 {Vt.d - Vt2.d}[lane],[Xn] ARMv8(AArch64)
poly64x1x2_t src, Vt.1D →
src.val[0] → Vt.1D
const int lane) result.val[0]
lane == 0

ptr → Xn
poly64x2x2_t vld2q_lane_p64 Vt2.2D →
src.val[1] →
(poly64_t const * ptr, result.val[1]
Vt2.2D LD2 {Vt.d - Vt2.d}[lane],[Xn] ARMv8(AArch64)
poly64x2x2_t src, Vt.2D →
src.val[0] → Vt.2D
const int lane) result.val[0]
0 <= lane <= 1

ptr → Xn
float64x1x2_t vld2_lane_f64 Vt2.1D →
src.val[1] →
(float64_t const * ptr, result.val[1]
Vt2.1D LD2 {Vt.d - Vt2.d}[lane],[Xn] ARMv8(AArch64)
float64x1x2_t src, Vt.1D →
src.val[0] → Vt.1D
const int lane) result.val[0]
lane == 0

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Non-Confidential
 ptr → Xn
float64x2x2_t vld2q_lane_f64 Vt2.2D →
src.val[1] →
(float64_t const * ptr, result.val[1]
Vt2.2D LD2 {Vt.d - Vt2.d}[lane],[Xn] ARMv8(AArch64)
float64x2x2_t src, Vt.2D →
src.val[0] → Vt.2D
const int lane) result.val[0]
0 <= lane <= 1

ptr → Xn
Vt3.4H →
src.val[2] →
int16x4x3_t vld3_lane_s16 result.val[2]
Vt3.4H
(int16_t const * ptr, Vt2.4H →
src.val[1] → LD3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
int16x4x3_t src, result.val[1]
Vt2.4H
const int lane) Vt.4H →
src.val[0] → Vt.4H
result.val[0]
0 <= lane <= 3

ptr → Xn
Vt3.8H →
src.val[2] →
int16x8x3_t vld3q_lane_s16 result.val[2]
Vt3.8H
(int16_t const * ptr, Vt2.8H →
src.val[1] → LD3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
int16x8x3_t src, result.val[1]
Vt2.8H
const int lane) Vt.8H →
src.val[0] → Vt.8H
result.val[0]
0 <= lane <= 7

ptr → Xn
Vt3.2S →
src.val[2] →
int32x2x3_t vld3_lane_s32 result.val[2]
Vt3.2S
(int32_t const * ptr, Vt2.2S →
src.val[1] → LD3 {Vt.s - Vt3.s}[lane],[Xn] ARMv7, ARMv8
int32x2x3_t src, result.val[1]
Vt2.2S
const int lane) Vt.2S →
src.val[0] → Vt.2S
result.val[0]
0 <= lane <= 1

ptr → Xn
Vt3.4S →
src.val[2] →
int32x4x3_t vld3q_lane_s32 result.val[2]
Vt3.4S
(int32_t const * ptr, Vt2.4S →
src.val[1] → LD3 {Vt.s - Vt3.s}[lane],[Xn] ARMv7, ARMv8
int32x4x3_t src, result.val[1]
Vt2.4S
const int lane) Vt.4S →
src.val[0] → Vt.4S
result.val[0]
0 <= lane <= 3

ptr → Xn
Vt3.4H →
src.val[2] →
uint16x4x3_t vld3_lane_u16 result.val[2]
Vt3.4H
(uint16_t const * ptr, Vt2.4H →
src.val[1] → LD3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
uint16x4x3_t src, result.val[1]
Vt2.4H
const int lane) Vt.4H →
src.val[0] → Vt.4H
result.val[0]
0 <= lane <= 3

ptr → Xn
Vt3.8H →
src.val[2] →
uint16x8x3_t vld3q_lane_u16 result.val[2]
Vt3.8H
(uint16_t const * ptr, Vt2.8H →
src.val[1] → LD3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
uint16x8x3_t src, result.val[1]
Vt2.8H
const int lane) Vt.8H →
src.val[0] → Vt.8H
result.val[0]
0 <= lane <= 7

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Non-Confidential
 ptr → Xn
Vt3.2S →
src.val[2] →
uint32x2x3_t vld3_lane_u32 result.val[2]
Vt3.2S
(uint32_t const * ptr, Vt2.2S →
src.val[1] → LD3 {Vt.s - Vt3.s}[lane],[Xn] ARMv7, ARMv8
uint32x2x3_t src, result.val[1]
Vt2.2S
const int lane) Vt.2S →
src.val[0] → Vt.2S
result.val[0]
0 <= lane <= 1

ptr → Xn
Vt3.4S →
src.val[2] →
uint32x4x3_t vld3q_lane_u32 result.val[2]
Vt3.4S
(uint32_t const * ptr, Vt2.4S →
src.val[1] → LD3 {Vt.s - Vt3.s}[lane],[Xn] ARMv7, ARMv8
uint32x4x3_t src, result.val[1]
Vt2.4S
const int lane) Vt.4S →
src.val[0] → Vt.4S
result.val[0]
0 <= lane <= 3

ptr → Xn
Vt3.4H →
src.val[2] →
float16x4x3_t vld3_lane_f16 result.val[2]
Vt3.4H
(float16_t const * ptr, Vt2.4H →
src.val[1] → LD3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
float16x4x3_t src, result.val[1]
Vt2.4H
const int lane) Vt.4H →
src.val[0] → Vt.4H
result.val[0]
0 <= lane <= 3

ptr → Xn
Vt3.8H →
src.val[2] →
float16x8x3_t vld3q_lane_f16 result.val[2]
Vt3.8H
(float16_t const * ptr, Vt2.8H →
src.val[1] → LD3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
float16x8x3_t src, result.val[1]
Vt2.8H
const int lane) Vt.8H →
src.val[0] → Vt.8H
result.val[0]
0 <= lane <= 7

ptr → Xn
Vt3.2S →
src.val[2] →
float32x2x3_t vld3_lane_f32 result.val[2]
Vt3.2S
(float32_t const * ptr, Vt2.2S →
src.val[1] → LD3 {Vt.s - Vt3.s}[lane],[Xn] ARMv7, ARMv8
float32x2x3_t src, result.val[1]
Vt2.2S
const int lane) Vt.2S →
src.val[0] → Vt.2S
result.val[0]
0 <= lane <= 1

ptr → Xn
Vt3.4S →
src.val[2] →
float32x4x3_t vld3q_lane_f32 result.val[2]
Vt3.4S
(float32_t const * ptr, Vt2.4S →
src.val[1] → LD3 {Vt.s - Vt3.s}[lane],[Xn] ARMv7, ARMv8
float32x4x3_t src, result.val[1]
Vt2.4S
const int lane) Vt.4S →
src.val[0] → Vt.4S
result.val[0]
0 <= lane <= 3

ptr → Xn
Vt3.4H →
src.val[2] →
poly16x4x3_t vld3_lane_p16 result.val[2]
Vt3.4H
(poly16_t const * ptr, Vt2.4H →
src.val[1] → LD3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
poly16x4x3_t src, result.val[1]
Vt2.4H
const int lane) Vt.4H →
src.val[0] → Vt.4H
result.val[0]
0 <= lane <= 3

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Non-Confidential
 ptr → Xn
Vt3.8H →
src.val[2] →
poly16x8x3_t vld3q_lane_p16 result.val[2]
Vt3.8H
(poly16_t const * ptr, Vt2.8H →
src.val[1] → LD3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
poly16x8x3_t src, result.val[1]
Vt2.8H
const int lane) Vt.8H →
src.val[0] → Vt.8H
result.val[0]
0 <= lane <= 7

ptr → Xn
Vt3.8B →
src.val[2] →
int8x8x3_t vld3_lane_s8 result.val[2]
Vt3.8B
(int8_t const * ptr, Vt2.8B →
src.val[1] → LD3 {Vt.b - Vt3.b}[lane],[Xn] ARMv7, ARMv8
int8x8x3_t src, result.val[1]
Vt2.8B
const int lane) Vt.8B →
src.val[0] → Vt.8B
result.val[0]
0 <= lane <= 7

ptr → Xn
Vt3.8B →
src.val[2] →
uint8x8x3_t vld3_lane_u8 result.val[2]
Vt3.8B
(uint8_t const * ptr, Vt2.8B →
src.val[1] → LD3 {Vt.b - Vt3.b}[lane],[Xn] ARMv7, ARMv8
uint8x8x3_t src, result.val[1]
Vt2.8B
const int lane) Vt.8B →
src.val[0] → Vt.8B
result.val[0]
0 <= lane <= 7

ptr → Xn
Vt3.8B →
src.val[2] →
poly8x8x3_t vld3_lane_p8 result.val[2]
Vt3.8B
(poly8_t const * ptr, Vt2.8B →
src.val[1] → LD3 {Vt.b - Vt3.b}[lane],[Xn] ARMv7, ARMv8
poly8x8x3_t src, result.val[1]
Vt2.8B
const int lane) Vt.8B →
src.val[0] → Vt.8B
result.val[0]
0 <= lane <= 7

ptr → Xn
src.val[2] → Vt3.16B →
int8x16x3_t vld3q_lane_s8 Vt3.16B result.val[2]
(int8_t const * ptr, src.val[1] → Vt2.16B →
LD3 {Vt.b - Vt3.b}[lane],[Xn] ARMv8(AArch64)
int8x16x3_t src, Vt2.16B result.val[1]
const int lane) src.val[0] → Vt.16B →
Vt.16B result.val[0]
0 <= lane <= 15

ptr → Xn
src.val[2] → Vt3.16B →
uint8x16x3_t vld3q_lane_u8 Vt3.16B result.val[2]
(uint8_t const * ptr, src.val[1] → Vt2.16B →
LD3 {Vt.b - Vt3.b}[lane],[Xn] ARMv8(AArch64)
uint8x16x3_t src, Vt2.16B result.val[1]
const int lane) src.val[0] → Vt.16B →
Vt.16B result.val[0]
0 <= lane <= 15

ptr → Xn
src.val[2] → Vt3.16B →
poly8x16x3_t vld3q_lane_p8 Vt3.16B result.val[2]
(poly8_t const * ptr, src.val[1] → Vt2.16B →
LD3 {Vt.b - Vt3.b}[lane],[Xn] ARMv8(AArch64)
poly8x16x3_t src, Vt2.16B result.val[1]
const int lane) src.val[0] → Vt.16B →
Vt.16B result.val[0]
0 <= lane <= 15

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Non-Confidential
 ptr → Xn
Vt3.1D →
src.val[2] →
int64x1x3_t vld3_lane_s64 result.val[2]
Vt3.1D
(int64_t const * ptr, Vt2.1D →
src.val[1] → LD3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
int64x1x3_t src, result.val[1]
Vt2.1D
const int lane) Vt.1D →
src.val[0] → Vt.1D
result.val[0]
lane == 0

ptr → Xn
Vt3.2D →
src.val[2] →
int64x2x3_t vld3q_lane_s64 result.val[2]
Vt3.2D
(int64_t const * ptr, Vt2.2D →
src.val[1] → LD3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
int64x2x3_t src, result.val[1]
Vt2.2D
const int lane) Vt.2D →
src.val[0] → Vt.2D
result.val[0]
0 <= lane <= 1

ptr → Xn
Vt3.1D →
src.val[2] →
uint64x1x3_t vld3_lane_u64 result.val[2]
Vt3.1D
(uint64_t const * ptr, Vt2.1D →
src.val[1] → LD3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
uint64x1x3_t src, result.val[1]
Vt2.1D
const int lane) Vt.1D →
src.val[0] → Vt.1D
result.val[0]
lane == 0

ptr → Xn
Vt3.2D →
src.val[2] →
uint64x2x3_t vld3q_lane_u64 result.val[2]
Vt3.2D
(uint64_t const * ptr, Vt2.2D →
src.val[1] → LD3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
uint64x2x3_t src, result.val[1]
Vt2.2D
const int lane) Vt.2D →
src.val[0] → Vt.2D
result.val[0]
0 <= lane <= 1

ptr → Xn
Vt3.1D →
src.val[2] →
poly64x1x3_t vld3_lane_p64 result.val[2]
Vt3.1D
(poly64_t const * ptr, Vt2.1D →
src.val[1] → LD3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
poly64x1x3_t src, result.val[1]
Vt2.1D
const int lane) Vt.1D →
src.val[0] → Vt.1D
result.val[0]
lane == 0

ptr → Xn
Vt3.2D →
src.val[2] →
poly64x2x3_t vld3q_lane_p64 result.val[2]
Vt3.2D
(poly64_t const * ptr, Vt2.2D →
src.val[1] → LD3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
poly64x2x3_t src, result.val[1]
Vt2.2D
const int lane) Vt.2D →
src.val[0] → Vt.2D
result.val[0]
0 <= lane <= 1

ptr → Xn
Vt3.1D →
src.val[2] →
float64x1x3_t vld3_lane_f64 result.val[2]
Vt3.1D
(float64_t const * ptr, Vt2.1D →
src.val[1] → LD3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
float64x1x3_t src, result.val[1]
Vt2.1D
const int lane) Vt.1D →
src.val[0] → Vt.1D
result.val[0]
lane == 0

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Non-Confidential
 ptr → Xn
Vt3.2D →
src.val[2] →
float64x2x3_t vld3q_lane_f64 result.val[2]
Vt3.2D
(float64_t const * ptr, Vt2.2D →
src.val[1] → LD3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
float64x2x3_t src, result.val[1]
Vt2.2D
const int lane) Vt.2D →
src.val[0] → Vt.2D
result.val[0]
0 <= lane <= 1

ptr → Xn
Vt4.4H →
src.val[3] →
result.val[3]
Vt4.4H
int16x4x4_t vld4_lane_s16 Vt3.4H →
src.val[2] →
(int16_t const * ptr, result.val[2]
Vt3.4H LD4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
int16x4x4_t src, Vt2.4H →
src.val[1] →
const int lane) result.val[1]
Vt2.4H
Vt.4H →
src.val[0] → Vt.4H
result.val[0]
0 <= lane <= 3

ptr → Xn
Vt4.8H →
src.val[3] →
result.val[3]
Vt4.8H
int16x8x4_t vld4q_lane_s16 Vt3.8H →
src.val[2] →
(int16_t const * ptr, result.val[2]
Vt3.8H LD4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
int16x8x4_t src, Vt2.8H →
src.val[1] →
const int lane) result.val[1]
Vt2.8H
Vt.8H →
src.val[0] → Vt.8H
result.val[0]
0 <= lane <= 7

ptr → Xn
Vt4.2S →
src.val[3] →
result.val[3]
Vt4.2S
int32x2x4_t vld4_lane_s32 Vt3.2S →
src.val[2] →
(int32_t const * ptr, result.val[2]
Vt3.2S LD4 {Vt.s - Vt4.s}[lane],[Xn] ARMv7, ARMv8
int32x2x4_t src, Vt2.2S →
src.val[1] →
const int lane) result.val[1]
Vt2.2S
Vt.2S →
src.val[0] → Vt.2S
result.val[0]
0 <= lane <= 1

ptr → Xn
Vt4.4S →
src.val[3] →
result.val[3]
Vt4.4S
int32x4x4_t vld4q_lane_s32 Vt3.4S →
src.val[2] →
(int32_t const * ptr, result.val[2]
Vt3.4S LD4 {Vt.s - Vt4.s}[lane],[Xn] ARMv7, ARMv8
int32x4x4_t src, Vt2.4S →
src.val[1] →
const int lane) result.val[1]
Vt2.4S
Vt.4S →
src.val[0] → Vt.4S
result.val[0]
0 <= lane <= 3

ptr → Xn
Vt4.4H →
src.val[3] →
result.val[3]
Vt4.4H
uint16x4x4_t vld4_lane_u16 Vt3.4H →
src.val[2] →
(uint16_t const * ptr, result.val[2]
Vt3.4H LD4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
uint16x4x4_t src, Vt2.4H →
src.val[1] →
const int lane) result.val[1]
Vt2.4H
Vt.4H →
src.val[0] → Vt.4H
result.val[0]
0 <= lane <= 3

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 235 of 348
Non-Confidential
 ptr → Xn
Vt4.8H →
src.val[3] →
result.val[3]
Vt4.8H
uint16x8x4_t vld4q_lane_u16 Vt3.8H →
src.val[2] →
(uint16_t const * ptr, result.val[2]
Vt3.8H LD4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
uint16x8x4_t src, Vt2.8H →
src.val[1] →
const int lane) result.val[1]
Vt2.8H
Vt.8H →
src.val[0] → Vt.8H
result.val[0]
0 <= lane <= 7

ptr → Xn
Vt4.2S →
src.val[3] →
result.val[3]
Vt4.2S
uint32x2x4_t vld4_lane_u32 Vt3.2S →
src.val[2] →
(uint32_t const * ptr, result.val[2]
Vt3.2S LD4 {Vt.s - Vt4.s}[lane],[Xn] ARMv7, ARMv8
uint32x2x4_t src, Vt2.2S →
src.val[1] →
const int lane) result.val[1]
Vt2.2S
Vt.2S →
src.val[0] → Vt.2S
result.val[0]
0 <= lane <= 1

ptr → Xn
Vt4.4S →
src.val[3] →
result.val[3]
Vt4.4S
uint32x4x4_t vld4q_lane_u32 Vt3.4S →
src.val[2] →
(uint32_t const * ptr, result.val[2]
Vt3.4S LD4 {Vt.s - Vt4.s}[lane],[Xn] ARMv7, ARMv8
uint32x4x4_t src, Vt2.4S →
src.val[1] →
const int lane) result.val[1]
Vt2.4S
Vt.4S →
src.val[0] → Vt.4S
result.val[0]
0 <= lane <= 3

ptr → Xn
Vt4.4H →
src.val[3] →
result.val[3]
Vt4.4H
float16x4x4_t vld4_lane_f16 Vt3.4H →
src.val[2] →
(float16_t const * ptr, result.val[2]
Vt3.4H LD4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
float16x4x4_t src, Vt2.4H →
src.val[1] →
const int lane) result.val[1]
Vt2.4H
Vt.4H →
src.val[0] → Vt.4H
result.val[0]
0 <= lane <= 3

ptr → Xn
Vt4.8H →
src.val[3] →
result.val[3]
Vt4.8H
float16x8x4_t vld4q_lane_f16 Vt3.8H →
src.val[2] →
(float16_t const * ptr, result.val[2]
Vt3.8H LD4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
float16x8x4_t src, Vt2.8H →
src.val[1] →
const int lane) result.val[1]
Vt2.8H
Vt.8H →
src.val[0] → Vt.8H
result.val[0]
0 <= lane <= 7

ptr → Xn
Vt4.2S →
src.val[3] →
result.val[3]
Vt4.2S
float32x2x4_t vld4_lane_f32 Vt3.2S →
src.val[2] →
(float32_t const * ptr, result.val[2]
Vt3.2S LD4 {Vt.s - Vt4.s}[lane],[Xn] ARMv7, ARMv8
float32x2x4_t src, Vt2.2S →
src.val[1] →
const int lane) result.val[1]
Vt2.2S
Vt.2S →
src.val[0] → Vt.2S
result.val[0]
0 <= lane <= 1

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Non-Confidential
 ptr → Xn
Vt4.4S →
src.val[3] →
result.val[3]
Vt4.4S
float32x4x4_t vld4q_lane_f32 Vt3.4S →
src.val[2] →
(float32_t const * ptr, result.val[2]
Vt3.4S LD4 {Vt.s - Vt4.s}[lane],[Xn] ARMv7, ARMv8
float32x4x4_t src, Vt2.4S →
src.val[1] →
const int lane) result.val[1]
Vt2.4S
Vt.4S →
src.val[0] → Vt.4S
result.val[0]
0 <= lane <= 3

ptr → Xn
Vt4.4H →
src.val[3] →
result.val[3]
Vt4.4H
poly16x4x4_t vld4_lane_p16 Vt3.4H →
src.val[2] →
(poly16_t const * ptr, result.val[2]
Vt3.4H LD4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
poly16x4x4_t src, Vt2.4H →
src.val[1] →
const int lane) result.val[1]
Vt2.4H
Vt.4H →
src.val[0] → Vt.4H
result.val[0]
0 <= lane <= 3

ptr → Xn
Vt4.8H →
src.val[3] →
result.val[3]
Vt4.8H
poly16x8x4_t vld4q_lane_p16 Vt3.8H →
src.val[2] →
(poly16_t const * ptr, result.val[2]
Vt3.8H LD4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
poly16x8x4_t src, Vt2.8H →
src.val[1] →
const int lane) result.val[1]
Vt2.8H
Vt.8H →
src.val[0] → Vt.8H
result.val[0]
0 <= lane <= 7

ptr → Xn
Vt4.8B →
src.val[3] →
result.val[3]
Vt4.8B
int8x8x4_t vld4_lane_s8 Vt3.8B →
src.val[2] →
(int8_t const * ptr, result.val[2]
Vt3.8B LD4 {Vt.b - Vt4.b}[lane],[Xn] ARMv7, ARMv8
int8x8x4_t src, Vt2.8B →
src.val[1] →
const int lane) result.val[1]
Vt2.8B
Vt.8B →
src.val[0] → Vt.8B
result.val[0]
0 <= lane <= 7

ptr → Xn
Vt4.8B →
src.val[3] →
result.val[3]
Vt4.8B
uint8x8x4_t vld4_lane_u8 Vt3.8B →
src.val[2] →
(uint8_t const * ptr, result.val[2]
Vt3.8B LD4 {Vt.b - Vt4.b}[lane],[Xn] ARMv7, ARMv8
uint8x8x4_t src, Vt2.8B →
src.val[1] →
const int lane) result.val[1]
Vt2.8B
Vt.8B →
src.val[0] → Vt.8B
result.val[0]
0 <= lane <= 7

ptr → Xn
Vt4.8B →
src.val[3] →
result.val[3]
Vt4.8B
poly8x8x4_t vld4_lane_p8 Vt3.8B →
src.val[2] →
(poly8_t const * ptr, result.val[2]
Vt3.8B LD4 {Vt.b - Vt4.b}[lane],[Xn] ARMv7, ARMv8
poly8x8x4_t src, Vt2.8B →
src.val[1] →
const int lane) result.val[1]
Vt2.8B
Vt.8B →
src.val[0] → Vt.8B
result.val[0]
0 <= lane <= 7

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 237 of 348
Non-Confidential
 ptr → Xn
src.val[3] → Vt4.16B →
Vt4.16B result.val[3]
int8x16x4_t vld4q_lane_s8 src.val[2] → Vt3.16B →
(int8_t const * ptr, Vt3.16B result.val[2]
LD4 {Vt.b - Vt4.b}[lane],[Xn] ARMv8(AArch64)
int8x16x4_t src, src.val[1] → Vt2.16B →
const int lane) Vt2.16B result.val[1]
src.val[0] → Vt.16B →
Vt.16B result.val[0]
0 <= lane <= 15

ptr → Xn
src.val[3] → Vt4.16B →
Vt4.16B result.val[3]
uint8x16x4_t vld4q_lane_u8 src.val[2] → Vt3.16B →
(uint8_t const * ptr, Vt3.16B result.val[2]
LD4 {Vt.b - Vt4.b}[lane],[Xn] ARMv8(AArch64)
uint8x16x4_t src, src.val[1] → Vt2.16B →
const int lane) Vt2.16B result.val[1]
src.val[0] → Vt.16B →
Vt.16B result.val[0]
0 <= lane <= 15

ptr → Xn
src.val[3] → Vt4.16B →
Vt4.16B result.val[3]
poly8x16x4_t vld4q_lane_p8 src.val[2] → Vt3.16B →
(poly8_t const * ptr, Vt3.16B result.val[2]
LD4 {Vt.b - Vt4.b}[lane],[Xn] ARMv8(AArch64)
poly8x16x4_t src, src.val[1] → Vt2.16B →
const int lane) Vt2.16B result.val[1]
src.val[0] → Vt.16B →
Vt.16B result.val[0]
0 <= lane <= 15

ptr → Xn
Vt4.1D →
src.val[3] →
result.val[3]
Vt4.1D
int64x1x4_t vld4_lane_s64 Vt3.1D →
src.val[2] →
(int64_t const * ptr, result.val[2]
Vt3.1D LD4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
int64x1x4_t src, Vt2.1D →
src.val[1] →
const int lane) result.val[1]
Vt2.1D
Vt.1D →
src.val[0] → Vt.1D
result.val[0]
lane == 0

ptr → Xn
Vt4.2D →
src.val[3] →
result.val[3]
Vt4.2D
int64x2x4_t vld4q_lane_s64 Vt3.2D →
src.val[2] →
(int64_t const * ptr, result.val[2]
Vt3.2D LD4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
int64x2x4_t src, Vt2.2D →
src.val[1] →
const int lane) result.val[1]
Vt2.2D
Vt.2D →
src.val[0] → Vt.2D
result.val[0]
0 <= lane <= 1

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Non-Confidential
 ptr → Xn
Vt4.1D →
src.val[3] →
result.val[3]
Vt4.1D
uint64x1x4_t vld4_lane_u64 Vt3.1D →
src.val[2] →
(uint64_t const * ptr, result.val[2]
Vt3.1D LD4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
uint64x1x4_t src, Vt2.1D →
src.val[1] →
const int lane) result.val[1]
Vt2.1D
Vt.1D →
src.val[0] → Vt.1D
result.val[0]
lane == 0

ptr → Xn
Vt4.2D →
src.val[3] →
result.val[3]
Vt4.2D
uint64x2x4_t vld4q_lane_u64 Vt3.2D →
src.val[2] →
(uint64_t const * ptr, result.val[2]
Vt3.2D LD4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
uint64x2x4_t src, Vt2.2D →
src.val[1] →
const int lane) result.val[1]
Vt2.2D
Vt.2D →
src.val[0] → Vt.2D
result.val[0]
0 <= lane <= 1

ptr → Xn
Vt4.1D →
src.val[3] →
result.val[3]
Vt4.1D
poly64x1x4_t vld4_lane_p64 Vt3.1D →
src.val[2] →
(poly64_t const * ptr, result.val[2]
Vt3.1D LD4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
poly64x1x4_t src, Vt2.1D →
src.val[1] →
const int lane) result.val[1]
Vt2.1D
Vt.1D →
src.val[0] → Vt.1D
result.val[0]
lane == 0

ptr → Xn
Vt4.2D →
src.val[3] →
result.val[3]
Vt4.2D
poly64x2x4_t vld4q_lane_p64 Vt3.2D →
src.val[2] →
(poly64_t const * ptr, result.val[2]
Vt3.2D LD4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
poly64x2x4_t src, Vt2.2D →
src.val[1] →
const int lane) result.val[1]
Vt2.2D
Vt.2D →
src.val[0] → Vt.2D
result.val[0]
0 <= lane <= 1

ptr → Xn
Vt4.1D →
src.val[3] →
result.val[3]
Vt4.1D
float64x1x4_t vld4_lane_f64 Vt3.1D →
src.val[2] →
(float64_t const * ptr, result.val[2]
Vt3.1D LD4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
float64x1x4_t src, Vt2.1D →
src.val[1] →
const int lane) result.val[1]
Vt2.1D
Vt.1D →
src.val[0] → Vt.1D
result.val[0]
lane == 0

ptr → Xn
Vt4.2D →
src.val[3] →
result.val[3]
Vt4.2D
float64x2x4_t vld4q_lane_f64 Vt3.2D →
src.val[2] →
(float64_t const * ptr, result.val[2]
Vt3.2D LD4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
float64x2x4_t src, Vt2.2D →
src.val[1] →
const int lane) result.val[1]
Vt2.2D
Vt.2D →
src.val[0] → Vt.2D
result.val[0]
0 <= lane <= 1

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 239 of 348
Non-Confidential
 ptr → Xn
void vst2_lane_s8
val.val[1] →
(int8_t * ptr,
Vt2.8B ST2 {Vt.b - Vt2.b}[lane],[Xn] ARMv7, ARMv8
int8x8x2_t val,
val.val[0] → Vt.8B
const int lane)
0 <= lane <= 7

ptr → Xn
void vst2_lane_u8
val.val[1] →
(uint8_t * ptr,
Vt2.8B ST2 {Vt.b - Vt2.b}[lane],[Xn] ARMv7, ARMv8
uint8x8x2_t val,
val.val[0] → Vt.8B
const int lane)
0 <= lane <= 7

ptr → Xn
void vst2_lane_p8
val.val[1] →
(poly8_t * ptr,
Vt2.8B ST2 {Vt.b - Vt2.b}[lane],[Xn] ARMv7, ARMv8
poly8x8x2_t val,
val.val[0] → Vt.8B
const int lane)
0 <= lane <= 7

ptr → Xn
val.val[2] →
void vst3_lane_s8
Vt3.8B
(int8_t * ptr,
val.val[1] → ST3 {Vt.b - Vt3.b}[lane],[Xn] ARMv7, ARMv8
int8x8x3_t val,
Vt2.8B
const int lane)
val.val[0] → Vt.8B
0 <= lane <= 7

ptr → Xn
val.val[2] →
void vst3_lane_u8
Vt3.8B
(uint8_t * ptr,
val.val[1] → ST3 {Vt.b - Vt3.b}[lane],[Xn] ARMv7, ARMv8
uint8x8x3_t val,
Vt2.8B
const int lane)
val.val[0] → Vt.8B
0 <= lane <= 7

ptr → Xn
val.val[2] →
void vst3_lane_p8
Vt3.8B
(poly8_t * ptr,
val.val[1] → ST3 {Vt.b - Vt3.b}[lane],[Xn] ARMv7, ARMv8
poly8x8x3_t val,
Vt2.8B
const int lane)
val.val[0] → Vt.8B
0 <= lane <= 7

ptr → Xn
val.val[3] →
Vt4.8B
void vst4_lane_s8
val.val[2] →
(int8_t * ptr,
Vt3.8B ST4 {Vt.b - Vt4.b}[lane],[Xn] ARMv7, ARMv8
int8x8x4_t val,
val.val[1] →
const int lane)
Vt2.8B
val.val[0] → Vt.8B
0 <= lane <= 7

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 240 of 348
Non-Confidential
 ptr → Xn
val.val[3] →
Vt4.8B
void vst4_lane_u8
val.val[2] →
(uint8_t * ptr,
Vt3.8B ST4 {Vt.b - Vt4.b}[lane],[Xn] ARMv7, ARMv8
uint8x8x4_t val,
val.val[1] →
const int lane)
Vt2.8B
val.val[0] → Vt.8B
0 <= lane <= 7

ptr → Xn
val.val[3] →
Vt4.8B
void vst4_lane_p8
val.val[2] →
(poly8_t * ptr,
Vt3.8B ST4 {Vt.b - Vt4.b}[lane],[Xn] ARMv7, ARMv8
poly8x8x4_t val,
val.val[1] →
const int lane)
Vt2.8B
val.val[0] → Vt.8B
0 <= lane <= 7

ptr → Xn
void vst2_lane_s16
val.val[1] →
(int16_t * ptr,
Vt2.4H ST2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
int16x4x2_t val,
val.val[0] → Vt.4H
const int lane)
0 <= lane <= 3

ptr → Xn
void vst2q_lane_s16
val.val[1] →
(int16_t * ptr,
Vt2.8H ST2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
int16x8x2_t val,
val.val[0] → Vt.8H
const int lane)
0 <= lane <= 7

ptr → Xn
void vst2_lane_s32
val.val[1] →
(int32_t * ptr,
Vt2.2S ST2 {Vt.s - Vt2.s}[lane],[Xn] ARMv7, ARMv8
int32x2x2_t val,
val.val[0] → Vt.2S
const int lane)
0 <= lane <= 1

ptr → Xn
void vst2q_lane_s32
val.val[1] →
(int32_t * ptr,
Vt2.4S ST2 {Vt.s - Vt2.s}[lane],[Xn] ARMv7, ARMv8
int32x4x2_t val,
val.val[0] → Vt.4S
const int lane)
0 <= lane <= 3

ptr → Xn
void vst2_lane_u16
val.val[1] →
(uint16_t * ptr,
Vt2.4H ST2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
uint16x4x2_t val,
val.val[0] → Vt.4H
const int lane)
0 <= lane <= 3

ptr → Xn
void vst2q_lane_u16
val.val[1] →
(uint16_t * ptr,
Vt2.8H ST2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
uint16x8x2_t val,
val.val[0] → Vt.8H
const int lane)
0 <= lane <= 7

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 241 of 348
Non-Confidential
 ptr → Xn
void vst2_lane_u32
val.val[1] →
(uint32_t * ptr,
Vt2.2S ST2 {Vt.s - Vt2.s}[lane],[Xn] ARMv7, ARMv8
uint32x2x2_t val,
val.val[0] → Vt.2S
const int lane)
0 <= lane <= 1

ptr → Xn
void vst2q_lane_u32
val.val[1] →
(uint32_t * ptr,
Vt2.4S ST2 {Vt.s - Vt2.s}[lane],[Xn] ARMv7, ARMv8
uint32x4x2_t val,
val.val[0] → Vt.4S
const int lane)
0 <= lane <= 3

ptr → Xn
void vst2_lane_f16
val.val[1] →
(float16_t * ptr,
Vt2.4H ST2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
float16x4x2_t val,
val.val[0] → Vt.4H
const int lane)
0 <= lane <= 3

ptr → Xn
void vst2q_lane_f16
val.val[1] →
(float16_t * ptr,
Vt2.8H ST2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
float16x8x2_t val,
val.val[0] → Vt.8H
const int lane)
0 <= lane <= 7

ptr → Xn
void vst2_lane_f32
val.val[1] →
(float32_t * ptr,
Vt2.2S ST2 {Vt.s - Vt2.s}[lane],[Xn] ARMv7, ARMv8
float32x2x2_t val,
val.val[0] → Vt.2S
const int lane)
0 <= lane <= 1

ptr → Xn
void vst2q_lane_f32
val.val[1] →
(float32_t * ptr,
Vt2.4S ST2 {Vt.s - Vt2.s}[lane],[Xn] ARMv7, ARMv8
float32x4x2_t val,
val.val[0] → Vt.4S
const int lane)
0 <= lane <= 3

ptr → Xn
void vst2_lane_p16
val.val[1] →
(poly16_t * ptr,
Vt2.4H ST2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
poly16x4x2_t val,
val.val[0] → Vt.4H
const int lane)
0 <= lane <= 3

ptr → Xn
void vst2q_lane_p16
val.val[1] →
(poly16_t * ptr,
Vt2.8H ST2 {Vt.h - Vt2.h}[lane],[Xn] ARMv7, ARMv8
poly16x8x2_t val,
val.val[0] → Vt.8H
const int lane)
0 <= lane <= 7

ptr → Xn
void vst2q_lane_s8 val.val[1] →
(int8_t * ptr, Vt2.16B
ST2 {Vt.b - Vt2.b}[lane],[Xn] ARMv8(AArch64)
int8x16x2_t val, val.val[0] →
const int lane) Vt.16B
0 <= lane <= 15

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 242 of 348
Non-Confidential
 ptr → Xn
void vst2q_lane_u8 val.val[1] →
(uint8_t * ptr, Vt2.16B
ST2 {Vt.b - Vt2.b}[lane],[Xn] ARMv8(AArch64)
uint8x16x2_t val, val.val[0] →
const int lane) Vt.16B
0 <= lane <= 15

ptr → Xn
void vst2q_lane_p8 val.val[1] →
(poly8_t * ptr, Vt2.16B
ST2 {Vt.b - Vt2.b}[lane],[Xn] ARMv8(AArch64)
poly8x16x2_t val, val.val[0] →
const int lane) Vt.16B
0 <= lane <= 15

ptr → Xn
void vst2_lane_s64
val.val[1] →
(int64_t * ptr,
Vt2.1D ST2 {Vt.d - Vt2.d}[lane],[Xn] ARMv8(AArch64)
int64x1x2_t val,
val.val[0] → Vt.1D
const int lane)
lane == 0

ptr → Xn
void vst2q_lane_s64
val.val[1] →
(int64_t * ptr,
Vt2.2D ST2 {Vt.d - Vt2.d}[lane],[Xn] ARMv8(AArch64)
int64x2x2_t val,
val.val[0] → Vt.2D
const int lane)
0 <= lane <= 1

ptr → Xn
void vst2_lane_u64
val.val[1] →
(uint64_t * ptr,
Vt2.1D ST2 {Vt.d - Vt2.d}[lane],[Xn] ARMv8(AArch64)
uint64x1x2_t val,
val.val[0] → Vt.1D
const int lane)
lane == 0

ptr → Xn
void vst2q_lane_u64
val.val[1] →
(uint64_t * ptr,
Vt2.2D ST2 {Vt.d - Vt2.d}[lane],[Xn] ARMv8(AArch64)
uint64x2x2_t val,
val.val[0] → Vt.2D
const int lane)
0 <= lane <= 1

ptr → Xn
void vst2_lane_p64
val.val[1] →
(poly64_t * ptr,
Vt2.1D ST2 {Vt.d - Vt2.d}[lane],[Xn] ARMv8(AArch64)
poly64x1x2_t val,
val.val[0] → Vt.1D
const int lane)
lane == 0

ptr → Xn
void vst2q_lane_p64
val.val[1] →
(poly64_t * ptr,
Vt2.2D ST2 {Vt.d - Vt2.d}[lane],[Xn] ARMv8(AArch64)
poly64x2x2_t val,
val.val[0] → Vt.2D
const int lane)
0 <= lane <= 1

ptr → Xn
void vst2_lane_f64
val.val[1] →
(float64_t * ptr,
Vt2.1D ST2 {Vt.d - Vt2.d}[lane],[Xn] ARMv8(AArch64)
float64x1x2_t val,
val.val[0] → Vt.1D
const int lane)
lane == 0

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 243 of 348
Non-Confidential
 ptr → Xn
void vst2q_lane_f64
val.val[1] →
(float64_t * ptr,
Vt2.2D ST2 {Vt.d - Vt2.d}[lane],[Xn] ARMv8(AArch64)
float64x2x2_t val,
val.val[0] → Vt.2D
const int lane)
0 <= lane <= 2

ptr → Xn
val.val[2] →
void vst3_lane_s16
Vt3.4H
(int16_t * ptr,
val.val[1] → ST3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
int16x4x3_t val,
Vt2.4H
const int lane)
val.val[0] → Vt.4H
0 <= lane <= 3

ptr → Xn
val.val[2] →
void vst3q_lane_s16
Vt3.8H
(int16_t * ptr,
val.val[1] → ST3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
int16x8x3_t val,
Vt2.8H
const int lane)
val.val[0] → Vt.8H
0 <= lane <= 7

ptr → Xn
val.val[2] →
void vst3_lane_s32
Vt3.2S
(int32_t * ptr,
val.val[1] → ST3 {Vt.s - Vt3.s}[lane],[Xn] ARMv7, ARMv8
int32x2x3_t val,
Vt2.2S
const int lane)
val.val[0] → Vt.2S
0 <= lane <= 1

ptr → Xn
val.val[2] →
void vst3q_lane_s32
Vt3.4S
(int32_t * ptr,
val.val[1] → ST3 {Vt.s - Vt3.s}[lane],[Xn] ARMv7, ARMv8
int32x4x3_t val,
Vt2.4S
const int lane)
val.val[0] → Vt.4S
0 <= lane <= 3

ptr → Xn
val.val[2] →
void vst3_lane_u16
Vt3.4H
(uint16_t * ptr,
val.val[1] → ST3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
uint16x4x3_t val,
Vt2.4H
const int lane)
val.val[0] → Vt.4H
0 <= lane <= 3

ptr → Xn
val.val[2] →
void vst3q_lane_u16
Vt3.8H
(uint16_t * ptr,
val.val[1] → ST3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
uint16x8x3_t val,
Vt2.8H
const int lane)
val.val[0] → Vt.8H
0 <= lane <= 7

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 244 of 348
Non-Confidential
 ptr → Xn
val.val[2] →
void vst3_lane_u32
Vt3.2S
(uint32_t * ptr,
val.val[1] → ST3 {Vt.s - Vt3.s}[lane],[Xn] ARMv7, ARMv8
uint32x2x3_t val,
Vt2.2S
const int lane)
val.val[0] → Vt.2S
0 <= lane <= 1

ptr → Xn
val.val[2] →
void vst3q_lane_u32
Vt3.4S
(uint32_t * ptr,
val.val[1] → ST3 {Vt.s - Vt3.s}[lane],[Xn] ARMv7, ARMv8
uint32x4x3_t val,
Vt2.4S
const int lane)
val.val[0] → Vt.4S
0 <= lane <= 3

ptr → Xn
val.val[2] →
void vst3_lane_f16
Vt3.4H
(float16_t * ptr,
val.val[1] → ST3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
float16x4x3_t val,
Vt2.4H
const int lane)
val.val[0] → Vt.4H
0 <= lane <= 3

ptr → Xn
val.val[2] →
void vst3q_lane_f16
Vt3.8H
(float16_t * ptr,
val.val[1] → ST3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
float16x8x3_t val,
Vt2.8H
const int lane)
val.val[0] → Vt.8H
0 <= lane <= 7

ptr → Xn
val.val[2] →
void vst3_lane_f32
Vt3.2S
(float32_t * ptr,
val.val[1] → ST3 {Vt.s - Vt3.s}[lane],[Xn] ARMv7, ARMv8
float32x2x3_t val,
Vt2.2S
const int lane)
val.val[0] → Vt.2S
0 <= lane <= 1

ptr → Xn
val.val[2] →
void vst3q_lane_f32
Vt3.4S
(float32_t * ptr,
val.val[1] → ST3 {Vt.s - Vt3.s}[lane],[Xn] ARMv7, ARMv8
float32x4x3_t val,
Vt2.4S
const int lane)
val.val[0] → Vt.4S
0 <= lane <= 3

ptr → Xn
val.val[2] →
void vst3_lane_p16
Vt3.4H
(poly16_t * ptr,
val.val[1] → ST3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
poly16x4x3_t val,
Vt2.4H
const int lane)
val.val[0] → Vt.4H
0 <= lane <= 3

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 245 of 348
Non-Confidential
 ptr → Xn
val.val[2] →
void vst3q_lane_p16
Vt3.8H
(poly16_t * ptr,
val.val[1] → ST3 {Vt.h - Vt3.h}[lane],[Xn] ARMv7, ARMv8
poly16x8x3_t val,
Vt2.8H
const int lane)
val.val[0] → Vt.8H
0 <= lane <= 7

ptr → Xn
val.val[2] →
void vst3q_lane_s8 Vt3.16B
(int8_t * ptr, val.val[1] →
ST3 {Vt.b - Vt3.b}[lane],[Xn] ARMv7, ARMv8
int8x16x3_t val, Vt2.16B
const int lane) val.val[0] →
Vt.16B
0 <= lane <= 15

ptr → Xn
val.val[2] →
void vst3q_lane_u8 Vt3.16B
(uint8_t * ptr, val.val[1] →
ST3 {Vt.b - Vt3.b}[lane],[Xn] ARMv7, ARMv8
uint8x16x3_t val, Vt2.16B
const int lane) val.val[0] →
Vt.16B
0 <= lane <= 15

ptr → Xn
val.val[2] →
void vst3q_lane_p8 Vt3.16B
(poly8_t * ptr, val.val[1] →
ST3 {Vt.b - Vt3.b}[lane],[Xn] ARMv7, ARMv8
poly8x16x3_t val, Vt2.16B
const int lane) val.val[0] →
Vt.16B
0 <= lane <= 15

ptr → Xn
val.val[2] →
void vst3_lane_s64
Vt3.1D
(int64_t * ptr,
val.val[1] → ST3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
int64x1x3_t val,
Vt2.1D
const int lane)
val.val[0] → Vt.1D
lane == 0

ptr → Xn
val.val[2] →
void vst3q_lane_s64
Vt3.2D
(int64_t * ptr,
val.val[1] → ST3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
int64x2x3_t val,
Vt2.2D
const int lane)
val.val[0] → Vt.2D
0 <= lane <= 1

ptr → Xn
val.val[2] →
void vst3_lane_u64
Vt3.1D
(uint64_t * ptr,
val.val[1] → ST3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
uint64x1x3_t val,
Vt2.1D
const int lane)
val.val[0] → Vt.1D
lane == 0

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 246 of 348
Non-Confidential
 ptr → Xn
val.val[2] →
void vst3q_lane_u64
Vt3.2D
(uint64_t * ptr,
val.val[1] → ST3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
uint64x2x3_t val,
Vt2.2D
const int lane)
val.val[0] → Vt.2D
0 <= lane <= 1

ptr → Xn
val.val[2] →
void vst3_lane_p64
Vt3.1D
(poly64_t * ptr,
val.val[1] → ST3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
poly64x1x3_t val,
Vt2.1D
const int lane)
val.val[0] → Vt.1D
lane == 0

ptr → Xn
val.val[2] →
void vst3q_lane_p64
Vt3.2D
(poly64_t * ptr,
val.val[1] → ST3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
poly64x2x3_t val,
Vt2.2D
const int lane)
val.val[0] → Vt.2D
0 <= lane <= 1

ptr → Xn
val.val[2] →
void vst3_lane_f64
Vt3.1D
(float64_t * ptr,
val.val[1] → ST3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
float64x1x3_t val,
Vt2.1D
const int lane)
val.val[0] → Vt.1D
lane == 0

ptr → Xn
val.val[2] →
void vst3q_lane_f64
Vt3.2D
(float64_t * ptr,
val.val[1] → ST3 {Vt.d - Vt3.d}[lane],[Xn] ARMv8(AArch64)
float64x2x3_t val,
Vt2.2D
const int lane)
val.val[0] → Vt.2D
0 <= lane <= 1

ptr → Xn
val.val[3] →
Vt4.4H
void vst4_lane_s16
val.val[2] →
(int16_t * ptr,
Vt3.4H ST4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
int16x4x4_t val,
val.val[1] →
const int lane)
Vt2.4H
val.val[0] → Vt.4H
0 <= lane <= 3

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 247 of 348
Non-Confidential
 ptr → Xn
val.val[3] →
Vt4.8H
void vst4q_lane_s16
val.val[2] →
(int16_t * ptr,
Vt3.8H ST4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
int16x8x4_t val,
val.val[1] →
const int lane)
Vt2.8H
val.val[0] → Vt.8H
0 <= lane <= 7

ptr → Xn
val.val[3] →
Vt4.2S
void vst4_lane_s32
val.val[2] →
(int32_t * ptr,
Vt3.2S ST4 {Vt.s - Vt4.s}[lane],[Xn] ARMv7, ARMv8
int32x2x4_t val,
val.val[1] →
const int lane)
Vt2.2S
val.val[0] → Vt.2S
0 <= lane <= 1

ptr → Xn
val.val[3] →
Vt4.4S
void vst4q_lane_s32
val.val[2] →
(int32_t * ptr,
Vt3.4S ST4 {Vt.s - Vt4.s}[lane],[Xn] ARMv7, ARMv8
int32x4x4_t val,
val.val[1] →
const int lane)
Vt2.4S
val.val[0] → Vt.4S
0 <= lane <= 3

ptr → Xn
val.val[3] →
Vt4.4H
void vst4_lane_u16
val.val[2] →
(uint16_t * ptr,
Vt3.4H ST4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
uint16x4x4_t val,
val.val[1] →
const int lane)
Vt2.4H
val.val[0] → Vt.4H
0 <= lane <= 3

ptr → Xn
val.val[3] →
Vt4.8H
void vst4q_lane_u16
val.val[2] →
(uint16_t * ptr,
Vt3.8H ST4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
uint16x8x4_t val,
val.val[1] →
const int lane)
Vt2.8H
val.val[0] → Vt.8H
0 <= lane <= 7

ptr → Xn
val.val[3] →
Vt4.2S
void vst4_lane_u32
val.val[2] →
(uint32_t * ptr,
Vt3.2S ST4 {Vt.s - Vt4.s}[lane],[Xn] ARMv7, ARMv8
uint32x2x4_t val,
val.val[1] →
const int lane)
Vt2.2S
val.val[0] → Vt.2S
0 <= lane <= 1

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 248 of 348
Non-Confidential
 ptr → Xn
val.val[3] →
Vt4.4S
void vst4q_lane_u32
val.val[2] →
(uint32_t * ptr,
Vt3.4S ST4 {Vt.s - Vt4.s}[lane],[Xn] ARMv7, ARMv8
uint32x4x4_t val,
val.val[1] →
const int lane)
Vt2.4S
val.val[0] → Vt.4S
0 <= lane <= 3

ptr → Xn
val.val[3] →
Vt4.4H
void vst4_lane_f16
val.val[2] →
(float16_t * ptr,
Vt3.4H ST4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
float16x4x4_t val,
val.val[1] →
const int lane)
Vt2.4H
val.val[0] → Vt.4H
0 <= lane <= 3

ptr → Xn
val.val[3] →
Vt4.8H
void vst4q_lane_f16
val.val[2] →
(float16_t * ptr,
Vt3.8H ST4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
float16x8x4_t val,
val.val[1] →
const int lane)
Vt2.8H
val.val[0] → Vt.8H
0 <= lane <= 7

ptr → Xn
val.val[3] →
Vt4.2S
void vst4_lane_f32
val.val[2] →
(float32_t * ptr,
Vt3.2S ST4 {Vt.s - Vt4.s}[lane],[Xn] ARMv7, ARMv8
float32x2x4_t val,
val.val[1] →
const int lane)
Vt2.2S
val.val[0] → Vt.2S
0 <= lane <= 1

ptr → Xn
val.val[3] →
Vt4.4S
void vst4q_lane_f32
val.val[2] →
(float32_t * ptr,
Vt3.4S ST4 {Vt.s - Vt4.s}[lane],[Xn] ARMv7, ARMv8
float32x4x4_t val,
val.val[1] →
const int lane)
Vt2.4S
val.val[0] → Vt.4S
0 <= lane <= 3

ptr → Xn
val.val[3] →
Vt4.4H
void vst4_lane_p16
val.val[2] →
(poly16_t * ptr,
Vt3.4H ST4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
poly16x4x4_t val,
val.val[1] →
const int lane)
Vt2.4H
val.val[0] → Vt.4H
0 <= lane <= 3

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 249 of 348
Non-Confidential
 ptr → Xn
val.val[3] →
Vt4.8H
void vst4q_lane_p16
val.val[2] →
(poly16_t * ptr,
Vt3.8H ST4 {Vt.h - Vt4.h}[lane],[Xn] ARMv7, ARMv8
poly16x8x4_t val,
val.val[1] →
const int lane)
Vt2.8H
val.val[0] → Vt.8H
0 <= lane <= 7

ptr → Xn
val.val[3] →
Vt4.16B
void vst4q_lane_s8 val.val[2] →
(int8_t * ptr, Vt3.16B
ST4 {Vt.b - Vt4.b}[lane],[Xn] ARMv8(AArch64)
int8x16x4_t val, val.val[1] →
const int lane) Vt2.16B
val.val[0] →
Vt.16B
0 <= lane <= 15

ptr → Xn
val.val[3] →
Vt4.16B
void vst4q_lane_u8 val.val[2] →
(uint8_t * ptr, Vt3.16B
ST4 {Vt.b - Vt4.b}[lane],[Xn] ARMv8(AArch64)
uint8x16x4_t val, val.val[1] →
const int lane) Vt2.16B
val.val[0] →
Vt.16B
0 <= lane <= 15

ptr → Xn
val.val[3] →
Vt4.16B
void vst4q_lane_p8 val.val[2] →
(poly8_t * ptr, Vt3.16B
ST4 {Vt.b - Vt4.b}[lane],[Xn] ARMv8(AArch64)
poly8x16x4_t val, val.val[1] →
const int lane) Vt2.16B
val.val[0] →
Vt.16B
0 <= lane <= 15

ptr → Xn
val.val[3] →
Vt4.1D
void vst4_lane_s64
val.val[2] →
(int64_t * ptr,
Vt3.1D ST4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
int64x1x4_t val,
val.val[1] →
const int lane)
Vt2.1D
val.val[0] → Vt.1D
lane == 0

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 250 of 348
Non-Confidential
 ptr → Xn
val.val[3] →
Vt4.2D
void vst4q_lane_s64
val.val[2] →
(int64_t * ptr,
Vt3.2D ST4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
int64x2x4_t val,
val.val[1] →
const int lane)
Vt2.2D
val.val[0] → Vt.2D
0 <= lane <= 1

ptr → Xn
val.val[3] →
Vt4.1D
void vst4_lane_u64
val.val[2] →
(uint64_t * ptr,
Vt3.1D ST4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
uint64x1x4_t val,
val.val[1] →
const int lane)
Vt2.1D
val.val[0] → Vt.1D
lane == 0

ptr → Xn
val.val[3] →
Vt4.2D
void vst4q_lane_u64
val.val[2] →
(uint64_t * ptr,
Vt3.2D ST4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
uint64x2x4_t val,
val.val[1] →
const int lane)
Vt2.2D
val.val[0] → Vt.2D
0 <= lane <= 1

ptr → Xn
val.val[3] →
Vt4.1D
void vst4_lane_p64
val.val[2] →
(poly64_t * ptr,
Vt3.1D ST4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
poly64x1x4_t val,
val.val[1] →
const int lane)
Vt2.1D
val.val[0] → Vt.1D
lane == 0

ptr → Xn
val.val[3] →
Vt4.2D
void vst4q_lane_p64
val.val[2] →
(poly64_t * ptr,
Vt3.2D ST4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
poly64x2x4_t val,
val.val[1] →
const int lane)
Vt2.2D
val.val[0] → Vt.2D
0 <= lane <= 1

ptr → Xn
val.val[3] →
Vt4.1D
void vst4_lane_f64
val.val[2] →
(float64_t * ptr,
Vt3.1D ST4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
float64x1x4_t val,
val.val[1] →
const int lane)
Vt2.1D
val.val[0] → Vt.1D
lane == 0

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 251 of 348
Non-Confidential
 ptr → Xn
val.val[3] →
Vt4.2D
void vst4q_lane_f64
val.val[2] →
(float64_t * ptr,
Vt3.2D ST4 {Vt.d - Vt4.d}[lane],[Xn] ARMv8(AArch64)
float64x2x4_t val,
val.val[1] →
const int lane)
Vt2.2D
val.val[0] → Vt.2D
0 <= lane <= 1

ptr → Xn
void vst1_s8_x2
val.val[1] →
(int8_t * ptr, ST1 {Vt.8B - Vt2.8B},[Xn] ARMv7, ARMv8
Vt2.8B
int8x8x2_t val)
val.val[0] → Vt.8B

ptr → Xn
void vst1q_s8_x2 val.val[1] →
(int8_t * ptr, Vt2.16B ST1 {Vt.16B - Vt2.16B},[Xn] ARMv7, ARMv8
int8x16x2_t val) val.val[0] →
Vt.16B

ptr → Xn
void vst1_s16_x2
val.val[1] →
(int16_t * ptr, ST1 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
Vt2.4H
int16x4x2_t val)
val.val[0] → Vt.4H

ptr → Xn
void vst1q_s16_x2
val.val[1] →
(int16_t * ptr, ST1 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
Vt2.8H
int16x8x2_t val)
val.val[0] → Vt.8H

ptr → Xn
void vst1_s32_x2
val.val[1] →
(int32_t * ptr, ST1 {Vt.2S - Vt2.2S},[Xn] ARMv7, ARMv8
Vt2.2S
int32x2x2_t val)
val.val[0] → Vt.2S

ptr → Xn
void vst1q_s32_x2
val.val[1] →
(int32_t * ptr, ST1 {Vt.4S - Vt2.4S},[Xn] ARMv7, ARMv8
Vt2.4S
int32x4x2_t val)
val.val[0] → Vt.4S

ptr → Xn
void vst1_u8_x2
val.val[1] →
(uint8_t * ptr, ST1 {Vt.8B - Vt2.8B},[Xn] ARMv7, ARMv8
Vt2.8B
uint8x8x2_t val)
val.val[0] → Vt.8B

ptr → Xn
void vst1q_u8_x2 val.val[1] →
(uint8_t * ptr, Vt2.16B ST1 {Vt.16B - Vt2.16B},[Xn] ARMv7, ARMv8
uint8x16x2_t val) val.val[0] →
Vt.16B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 252 of 348
Non-Confidential
 ptr → Xn
void vst1_u16_x2
val.val[1] →
(uint16_t * ptr, ST1 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
Vt2.4H
uint16x4x2_t val)
val.val[0] → Vt.4H

ptr → Xn
void vst1q_u16_x2
val.val[1] →
(uint16_t * ptr, ST1 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
Vt2.8H
uint16x8x2_t val)
val.val[0] → Vt.8H

ptr → Xn
void vst1_u32_x2
val.val[1] →
(uint32_t * ptr, ST1 {Vt.2S - Vt2.2S},[Xn] ARMv7, ARMv8
Vt2.2S
uint32x2x2_t val)
val.val[0] → Vt.2S

ptr → Xn
void vst1q_u32_x2
val.val[1] →
(uint32_t * ptr, ST1 {Vt.4S - Vt2.4S},[Xn] ARMv7, ARMv8
Vt2.4S
uint32x4x2_t val)
val.val[0] → Vt.4S

ptr → Xn
void vst1_f16_x2
val.val[1] →
(float16_t * ptr, ST1 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
Vt2.4H
float16x4x2_t val)
val.val[0] → Vt.4H

ptr → Xn
void vst1q_f16_x2
val.val[1] →
(float16_t * ptr, ST1 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
Vt2.8H
float16x8x2_t val)
val.val[0] → Vt.8H

ptr → Xn
void vst1_f32_x2
val.val[1] →
(float32_t * ptr, ST1 {Vt.2S - Vt2.2S},[Xn] ARMv7, ARMv8
Vt2.2S
float32x2x2_t val)
val.val[0] → Vt.2S

ptr → Xn
void vst1q_f32_x2
val.val[1] →
(float32_t * ptr, ST1 {Vt.4S - Vt2.4S},[Xn] ARMv7, ARMv8
Vt2.4S
float32x4x2_t val)
val.val[0] → Vt.4S

ptr → Xn
void vst1_p8_x2
val.val[1] →
(poly8_t * ptr, ST1 {Vt.8B - Vt2.8B},[Xn] ARMv7, ARMv8
Vt2.8B
poly8x8x2_t val)
val.val[0] → Vt.8B

ptr → Xn
void vst1q_p8_x2 val.val[1] →
(poly8_t * ptr, Vt2.16B ST1 {Vt.16B - Vt2.16B},[Xn] ARMv7, ARMv8
poly8x16x2_t val) val.val[0] →
Vt.16B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 253 of 348
Non-Confidential
 ptr → Xn
void vst1_p16_x2
val.val[1] →
(poly16_t * ptr, ST1 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
Vt2.4H
poly16x4x2_t val)
val.val[0] → Vt.4H

ptr → Xn
void vst1q_p16_x2
val.val[1] →
(poly16_t * ptr, ST1 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
Vt2.8H
poly16x8x2_t val)
val.val[0] → Vt.8H

ptr → Xn
void vst1_s64_x2
val.val[1] →
(int64_t * ptr, ST1 {Vt.1D - Vt2.1D},[Xn] ARMv7, ARMv8
Vt2.1D
int64x1x2_t val)
val.val[0] → Vt.1D

ptr → Xn
void vst1_u64_x2
val.val[1] →
(uint64_t * ptr, ST1 {Vt.1D - Vt2.1D},[Xn] ARMv7, ARMv8
Vt2.1D
uint64x1x2_t val)
val.val[0] → Vt.1D

ptr → Xn
void vst1_p64_x2
val.val[1] →
(poly64_t * ptr, ST1 {Vt.1D - Vt2.1D},[Xn] ARMv8
Vt2.1D
poly64x1x2_t val)
val.val[0] → Vt.1D

ptr → Xn
void vst1q_s64_x2
val.val[1] →
(int64_t * ptr, ST1 {Vt.2D - Vt2.2D},[Xn] ARMv7, ARMv8
Vt2.2D
int64x2x2_t val)
val.val[0] → Vt.2D

ptr → Xn
void vst1q_u64_x2
val.val[1] →
(uint64_t * ptr, ST1 {Vt.2D - Vt2.2D},[Xn] ARMv7, ARMv8
Vt2.2D
uint64x2x2_t val)
val.val[0] → Vt.2D

ptr → Xn
void vst1q_p64_x2
val.val[1] →
(poly64_t * ptr, ST1 {Vt.2D - Vt2.2D},[Xn] ARMv8
Vt2.2D
poly64x2x2_t val)
val.val[0] → Vt.2D

ptr → Xn
void vst1_f64_x2
val.val[1] →
(float64_t * ptr, ST1 {Vt.1D - Vt2.1D},[Xn] ARMv8(AArch64)
Vt2.1D
float64x1x2_t val)
val.val[0] → Vt.1D

ptr → Xn
void vst1q_f64_x2
val.val[1] →
(float64_t * ptr, ST1 {Vt.2D - Vt2.2D},[Xn] ARMv8(AArch64)
Vt2.2D
float64x2x2_t val)
val.val[0] → Vt.2D

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 254 of 348
Non-Confidential
 ptr → Xn
val.val[2] →
void vst1_s8_x3
Vt3.8B
(int8_t * ptr, ST1 {Vt.8B - Vt3.8B},[Xn] ARMv7, ARMv8
val.val[1] →
int8x8x3_t val)
Vt2.8B
val.val[0] → Vt.8B

ptr → Xn
val.val[2] →
void vst1q_s8_x3 Vt3.16B
(int8_t * ptr, val.val[1] → ST1 {Vt.16B - Vt3.16B},[Xn] ARMv7, ARMv8
int8x16x3_t val) Vt2.16B
val.val[0] →
Vt.16B

ptr → Xn
val.val[2] →
void vst1_s16_x3
Vt3.4H
(int16_t * ptr, ST1 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
val.val[1] →
int16x4x3_t val)
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[2] →
void vst1q_s16_x3
Vt3.8H
(int16_t * ptr, ST1 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
val.val[1] →
int16x8x3_t val)
Vt2.8H
val.val[0] → Vt.8H

ptr → Xn
val.val[2] →
void vst1_s32_x3
Vt3.2S
(int32_t * ptr, ST1 {Vt.2S - Vt3.2S},[Xn] ARMv7, ARMv8
val.val[1] →
int32x2x3_t val)
Vt2.2S
val.val[0] → Vt.2S

ptr → Xn
val.val[2] →
void vst1q_s32_x3
Vt3.4S
(int32_t * ptr, ST1 {Vt.4S - Vt3.4S},[Xn] ARMv7, ARMv8
val.val[1] →
int32x4x3_t val)
Vt2.4S
val.val[0] → Vt.4S

ptr → Xn
val.val[2] →
void vst1_u8_x3
Vt3.8B
(uint8_t * ptr, ST1 {Vt.8B - Vt3.8B},[Xn] ARMv7, ARMv8
val.val[1] →
uint8x8x3_t val)
Vt2.8B
val.val[0] → Vt.8B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 255 of 348
Non-Confidential
 ptr → Xn
val.val[2] →
void vst1q_u8_x3 Vt3.16B
(uint8_t * ptr, val.val[1] → ST1 {Vt.16B - Vt3.16B},[Xn] ARMv7, ARMv8
uint8x16x3_t val) Vt2.16B
val.val[0] →
Vt.16B

ptr → Xn
val.val[2] →
void vst1_u16_x3
Vt3.4H
(uint16_t * ptr, ST1 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
val.val[1] →
uint16x4x3_t val)
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[2] →
void vst1q_u16_x3
Vt3.8H
(uint16_t * ptr, ST1 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
val.val[1] →
uint16x8x3_t val)
Vt2.8H
val.val[0] → Vt.8H

ptr → Xn
val.val[2] →
void vst1_u32_x3
Vt3.2S
(uint32_t * ptr, ST1 {Vt.2S - Vt3.2S},[Xn] ARMv7, ARMv8
val.val[1] →
uint32x2x3_t val)
Vt2.2S
val.val[0] → Vt.2S

ptr → Xn
val.val[2] →
void vst1q_u32_x3
Vt3.4S
(uint32_t * ptr, ST1 {Vt.4S - Vt3.4S},[Xn] ARMv7, ARMv8
val.val[1] →
uint32x4x3_t val)
Vt2.4S
val.val[0] → Vt.4S

ptr → Xn
val.val[2] →
void vst1_f16_x3
Vt3.4H
(float16_t * ptr, ST1 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
val.val[1] →
float16x4x3_t val)
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[2] →
void vst1q_f16_x3
Vt3.8H
(float16_t * ptr, ST1 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
val.val[1] →
float16x8x3_t val)
Vt2.8H
val.val[0] → Vt.8H

ptr → Xn
val.val[2] →
void vst1_f32_x3
Vt3.2S
(float32_t * ptr, ST1 {Vt.2S - Vt3.2S},[Xn] ARMv7, ARMv8
val.val[1] →
float32x2x3_t val)
Vt2.2S
val.val[0] → Vt.2S

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 256 of 348
Non-Confidential
 ptr → Xn
val.val[2] →
void vst1q_f32_x3
Vt3.4S
(float32_t * ptr, ST1 {Vt.4S - Vt3.4S},[Xn] ARMv7, ARMv8
val.val[1] →
float32x4x3_t val)
Vt2.4S
val.val[0] → Vt.4S

ptr → Xn
val.val[2] →
void vst1_p8_x3
Vt3.8B
(poly8_t * ptr, ST1 {Vt.8B - Vt3.8B},[Xn] ARMv7, ARMv8
val.val[1] →
poly8x8x3_t val)
Vt2.8B
val.val[0] → Vt.8B

ptr → Xn
val.val[2] →
void vst1q_p8_x3 Vt3.16B
(poly8_t * ptr, val.val[1] → ST1 {Vt.16B - Vt3.16B},[Xn] ARMv7, ARMv8
poly8x16x3_t val) Vt2.16B
val.val[0] →
Vt.16B

ptr → Xn
val.val[2] →
void vst1_p16_x3
Vt3.4H
(poly16_t * ptr, ST1 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
val.val[1] →
poly16x4x3_t val)
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[2] →
void vst1q_p16_x3
Vt3.8H
(poly16_t * ptr, ST1 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
val.val[1] →
poly16x8x3_t val)
Vt2.8H
val.val[0] → Vt.8H

ptr → Xn
val.val[2] →
void vst1_s64_x3
Vt3.1D
(int64_t * ptr, ST1 {Vt.1D - Vt3.1D},[Xn] ARMv7, ARMv8
val.val[1] →
int64x1x3_t val)
Vt2.1D
val.val[0] → Vt.1D

ptr → Xn
val.val[2] →
void vst1_u64_x3
Vt3.1D
(uint64_t * ptr, ST1 {Vt.1D - Vt3.1D},[Xn] ARMv7, ARMv8
val.val[1] →
uint64x1x3_t val)
Vt2.1D
val.val[0] → Vt.1D

ptr → Xn
val.val[2] →
void vst1_p64_x3
Vt3.1D
(poly64_t * ptr, ST1 {Vt.1D - Vt3.1D},[Xn] ARMv8
val.val[1] →
poly64x1x3_t val)
Vt2.1D
val.val[0] → Vt.1D

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 257 of 348
Non-Confidential
 ptr → Xn
val.val[2] →
void vst1q_s64_x3
Vt3.2D
(int64_t * ptr, ST1 {Vt.2D - Vt3.2D},[Xn] ARMv7, ARMv8
val.val[1] →
int64x2x3_t val)
Vt2.2D
val.val[0] → Vt.2D

ptr → Xn
val.val[2] →
void vst1q_u64_x3
Vt3.2D
(uint64_t * ptr, ST1 {Vt.2D - Vt3.2D},[Xn] ARMv7, ARMv8
val.val[1] →
uint64x2x3_t val)
Vt2.2D
val.val[0] → Vt.2D

ptr → Xn
val.val[2] →
void vst1q_p64_x3
Vt3.2D
(poly64_t * ptr, ST1 {Vt.2D - Vt3.2D},[Xn] ARMv7, ARMv8
val.val[1] →
poly64x2x3_t val)
Vt2.2D
val.val[0] → Vt.2D

ptr → Xn
val.val[2] →
void vst1_f64_x3
Vt3.1D
(float64_t * ptr, ST1 {Vt.1D - Vt3.1D},[Xn] ARMv8(AArch64)
val.val[1] →
float64x1x3_t val)
Vt2.1D
val.val[0] → Vt.1D

ptr → Xn
val.val[2] →
void vst1q_f64_x3
Vt3.2D
(float64_t * ptr, ST1 {Vt.2D - Vt3.2D},[Xn] ARMv8(AArch64)
val.val[1] →
float64x2x3_t val)
Vt2.2D
val.val[0] → Vt.2D

ptr → Xn
val.val[3] →
Vt4.8B
void vst1_s8_x4
val.val[2] →
(int8_t * ptr, ST1 {Vt.8B - Vt4.8B},[Xn] ARMv7, ARMv8
Vt3.8B
int8x8x4_t val)
val.val[1] →
Vt2.8B
val.val[0] → Vt.8B

ptr → Xn
val.val[3] →
Vt4.16B
void vst1q_s8_x4 val.val[2] →
(int8_t * ptr, Vt3.16B ST1 {Vt.16B - Vt4.16B},[Xn] ARMv7, ARMv8
int8x16x4_t val) val.val[1] →
Vt2.16B
val.val[0] →
Vt.16B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 258 of 348
Non-Confidential
 ptr → Xn
val.val[3] →
Vt4.4H
void vst1_s16_x4
val.val[2] →
(int16_t * ptr, ST1 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
Vt3.4H
int16x4x4_t val)
val.val[1] →
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[3] →
Vt4.8H
void vst1q_s16_x4
val.val[2] →
(int16_t * ptr, ST1 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
Vt3.8H
int16x8x4_t val)
val.val[1] →
Vt2.8H
val.val[0] → Vt.8H

ptr → Xn
val.val[3] →
Vt4.2S
void vst1_s32_x4
val.val[2] →
(int32_t * ptr, ST1 {Vt.2S - Vt4.2S},[Xn] ARMv7, ARMv8
Vt3.2S
int32x2x4_t val)
val.val[1] →
Vt2.2S
val.val[0] → Vt.2S

ptr → Xn
val.val[3] →
Vt4.4S
void vst1q_s32_x4
val.val[2] →
(int32_t * ptr, ST1 {Vt.4S - Vt4.4S},[Xn] ARMv7, ARMv8
Vt3.4S
int32x4x4_t val)
val.val[1] →
Vt2.4S
val.val[0] → Vt.4S

ptr → Xn
val.val[3] →
Vt4.8B
void vst1_u8_x4
val.val[2] →
(uint8_t * ptr, ST1 {Vt.8B - Vt4.8B},[Xn] ARMv7, ARMv8
Vt3.8B
uint8x8x4_t val)
val.val[1] →
Vt2.8B
val.val[0] → Vt.8B

ptr → Xn
val.val[3] →
Vt4.16B
void vst1q_u8_x4 val.val[2] →
(uint8_t * ptr, Vt3.16B ST1 {Vt.16B - Vt4.16B},[Xn] ARMv7, ARMv8
uint8x16x4_t val) val.val[1] →
Vt2.16B
val.val[0] →
Vt.16B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 259 of 348
Non-Confidential
 ptr → Xn
val.val[3] →
Vt4.4H
void vst1_u16_x4
val.val[2] →
(uint16_t * ptr, ST1 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
Vt3.4H
uint16x4x4_t val)
val.val[1] →
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[3] →
Vt4.8H
void vst1q_u16_x4
val.val[2] →
(uint16_t * ptr, ST1 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
Vt3.8H
uint16x8x4_t val)
val.val[1] →
Vt2.8H
val.val[0] → Vt.8H

ptr → Xn
val.val[3] →
Vt4.2S
void vst1_u32_x4
val.val[2] →
(uint32_t * ptr, ST1 {Vt.2S - Vt4.2S},[Xn] ARMv7, ARMv8
Vt3.2S
uint32x2x4_t val)
val.val[1] →
Vt2.2S
val.val[0] → Vt.2S

ptr → Xn
val.val[3] →
Vt4.4S
void vst1q_u32_x4
val.val[2] →
(uint32_t * ptr, ST1 {Vt.4S - Vt4.4S},[Xn] ARMv7, ARMv8
Vt3.4S
uint32x4x4_t val)
val.val[1] →
Vt2.4S
val.val[0] → Vt.4S

ptr → Xn
val.val[3] →
Vt4.4H
void vst1_f16_x4
val.val[2] →
(float16_t * ptr, ST1 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
Vt3.4H
float16x4x4_t val)
val.val[1] →
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[3] →
Vt4.8H
void vst1q_f16_x4
val.val[2] →
(float16_t * ptr, ST1 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
Vt3.8H
float16x8x4_t val)
val.val[1] →
Vt2.8H
val.val[0] → Vt.8H

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 260 of 348
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 ptr → Xn
val.val[3] →
Vt4.2S
void vst1_f32_x4
val.val[2] →
(float32_t * ptr, ST1 {Vt.2S - Vt4.2S},[Xn] ARMv7, ARMv8
Vt3.2S
float32x2x4_t val)
val.val[1] →
Vt2.2S
val.val[0] → Vt.2S

ptr → Xn
val.val[3] →
Vt4.4S
void vst1q_f32_x4
val.val[2] →
(float32_t * ptr, ST1 {Vt.4S - Vt4.4S},[Xn] ARMv7, ARMv8
Vt3.4S
float32x4x4_t val)
val.val[1] →
Vt2.4S
val.val[0] → Vt.4S

ptr → Xn
val.val[3] →
Vt4.8B
void vst1_p8_x4
val.val[2] →
(poly8_t * ptr, ST1 {Vt.8B - Vt4.8B},[Xn] ARMv7, ARMv8
Vt3.8B
poly8x8x4_t val)
val.val[1] →
Vt2.8B
val.val[0] → Vt.8B

ptr → Xn
val.val[3] →
Vt4.16B
void vst1q_p8_x4 val.val[2] →
(poly8_t * ptr, Vt3.16B ST1 {Vt.16B - Vt4.16B},[Xn] ARMv7, ARMv8
poly8x16x4_t val) val.val[1] →
Vt2.16B
val.val[0] →
Vt.16B

ptr → Xn
val.val[3] →
Vt4.4H
void vst1_p16_x4
val.val[2] →
(poly16_t * ptr, ST1 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
Vt3.4H
poly16x4x4_t val)
val.val[1] →
Vt2.4H
val.val[0] → Vt.4H

ptr → Xn
val.val[3] →
Vt4.8H
void vst1q_p16_x4
val.val[2] →
(poly16_t * ptr, ST1 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
Vt3.8H
poly16x8x4_t val)
val.val[1] →
Vt2.8H
val.val[0] → Vt.8H

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 261 of 348
Non-Confidential
 ptr → Xn
val.val[3] →
Vt4.1D
void vst1_s64_x4
val.val[2] →
(int64_t * ptr, ST1 {Vt.1D - Vt4.1D},[Xn] ARMv7, ARMv8
Vt3.1D
int64x1x4_t val)
val.val[1] →
Vt2.1D
val.val[0] → Vt.1D

ptr → Xn
val.val[3] →
Vt4.1D
void vst1_u64_x4
val.val[2] →
(uint64_t * ptr, ST1 {Vt.1D - Vt4.1D},[Xn] ARMv7, ARMv8
Vt3.1D
uint64x1x4_t val)
val.val[1] →
Vt2.1D
val.val[0] → Vt.1D

ptr → Xn
val.val[3] →
Vt4.1D
void vst1_p64_x4
val.val[2] →
(poly64_t * ptr, ST1 {Vt.1D - Vt4.1D},[Xn] ARMv8
Vt3.1D
poly64x1x4_t val)
val.val[1] →
Vt2.1D
val.val[0] → Vt.1D

ptr → Xn
val.val[3] →
Vt4.2D
void vst1q_s64_x4
val.val[2] →
(int64_t * ptr, ST1 {Vt.2D - Vt4.2D},[Xn] ARMv7, ARMv8
Vt3.2D
int64x2x4_t val)
val.val[1] →
Vt2.2D
val.val[0] → Vt.2D

ptr → Xn
val.val[3] →
Vt4.2D
void vst1q_u64_x4
val.val[2] →
(uint64_t * ptr, ST1 {Vt.2D - Vt4.2D},[Xn] ARMv7, ARMv8
Vt3.2D
uint64x2x4_t val)
val.val[1] →
Vt2.2D
val.val[0] → Vt.2D

ptr → Xn
val.val[3] →
Vt4.2D
void vst1q_p64_x4
val.val[2] →
(poly64_t * ptr, ST1 {Vt.2D - Vt4.2D},[Xn] ARMv8
Vt3.2D
poly64x2x4_t val)
val.val[1] →
Vt2.2D
val.val[0] → Vt.2D

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 262 of 348
Non-Confidential
 ptr → Xn
val.val[3] →
Vt4.1D
void vst1_f64_x4
val.val[2] →
(float64_t * ptr, ST1 {Vt.1D - Vt4.1D},[Xn] ARMv8(AArch64)
Vt3.1D
float64x1x4_t val)
val.val[1] →
Vt2.1D
val.val[0] → Vt.1D

ptr → Xn
val.val[3] →
Vt4.2D
void vst1q_f64_x4
val.val[2] →
(float64_t * ptr, ST1 {Vt.2D - Vt4.2D},[Xn] ARMv8(AArch64)
Vt3.2D
float64x2x4_t val)
val.val[1] →
Vt2.2D
val.val[0] → Vt.2D

Vt2.8B →
int8x8x2_t vld1_s8_x2 result.val[1]
LD1 {Vt.8B - Vt2.8B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) Vt.8B →
ptr → Xn result.val[0]

Vt2.16B →
int8x16x2_t vld1q_s8_x2 result.val[1]
LD1 {Vt.16B - Vt2.16B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) Vt.16B →
ptr → Xn result.val[0]

Vt2.4H →
int16x4x2_t vld1_s16_x2 result.val[1]
LD1 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) Vt.4H →
ptr → Xn result.val[0]

Vt2.8H →
int16x8x2_t vld1q_s16_x2 result.val[1]
LD1 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) Vt.8H →
ptr → Xn result.val[0]

Vt2.2S →
int32x2x2_t vld1_s32_x2 result.val[1]
LD1 {Vt.2S - Vt2.2S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) Vt.2S →
ptr → Xn result.val[0]

Vt2.4S →
int32x4x2_t vld1q_s32_x2 result.val[1]
LD1 {Vt.4S - Vt2.4S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) Vt.4S →
ptr → Xn result.val[0]

Vt2.8B →
uint8x8x2_t vld1_u8_x2 result.val[1]
LD1 {Vt.8B - Vt2.8B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) Vt.8B →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 263 of 348
Non-Confidential
 Vt2.16B →
uint8x16x2_t vld1q_u8_x2 result.val[1]
LD1 {Vt.16B - Vt2.16B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) Vt.16B →
ptr → Xn result.val[0]

Vt2.4H →
uint16x4x2_t vld1_u16_x2 result.val[1]
LD1 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) Vt.4H →
ptr → Xn result.val[0]

Vt2.8H →
uint16x8x2_t vld1q_u16_x2 result.val[1]
LD1 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) Vt.8H →
ptr → Xn result.val[0]

Vt2.2S →
uint32x2x2_t vld1_u32_x2 result.val[1]
LD1 {Vt.2S - Vt2.2S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) Vt.2S →
ptr → Xn result.val[0]

Vt2.4S →
uint32x4x2_t vld1q_u32_x2 result.val[1]
LD1 {Vt.4S - Vt2.4S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) Vt.4S →
ptr → Xn result.val[0]

Vt2.4H →
float16x4x2_t vld1_f16_x2 result.val[1]
LD1 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) Vt.4H →
ptr → Xn result.val[0]

Vt2.8H →
float16x8x2_t vld1q_f16_x2 result.val[1]
LD1 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) Vt.8H →
ptr → Xn result.val[0]

Vt2.2S →
float32x2x2_t vld1_f32_x2 result.val[1]
LD1 {Vt.2S - Vt2.2S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) Vt.2S →
ptr → Xn result.val[0]

Vt2.4S →
float32x4x2_t vld1q_f32_x2 result.val[1]
LD1 {Vt.4S - Vt2.4S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) Vt.4S →
ptr → Xn result.val[0]

Vt2.8B →
poly8x8x2_t vld1_p8_x2 result.val[1]
LD1 {Vt.8B - Vt2.8B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) Vt.8B →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 264 of 348
Non-Confidential
 Vt2.16B →
poly8x16x2_t vld1q_p8_x2 result.val[1]
LD1 {Vt.16B - Vt2.16B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) Vt.16B →
ptr → Xn result.val[0]

Vt2.4H →
poly16x4x2_t vld1_p16_x2 result.val[1]
LD1 {Vt.4H - Vt2.4H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) Vt.4H →
ptr → Xn result.val[0]

Vt2.8H →
poly16x8x2_t vld1q_p16_x2 result.val[1]
LD1 {Vt.8H - Vt2.8H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) Vt.8H →
ptr → Xn result.val[0]

Vt2.1D →
int64x1x2_t vld1_s64_x2 result.val[1]
LD1 {Vt.1D - Vt2.1D},[Xn] ARMv7, ARMv8
(int64_t const * ptr) Vt.1D →
ptr → Xn result.val[0]

Vt2.1D →
uint64x1x2_t vld1_u64_x2 result.val[1]
LD1 {Vt.1D - Vt2.1D},[Xn] ARMv7, ARMv8
(uint64_t const * ptr) Vt.1D →
ptr → Xn result.val[0]

Vt2.1D →
poly64x1x2_t vld1_p64_x2 result.val[1]
LD1 {Vt.1D - Vt2.1D},[Xn] ARMv8
(poly64_t const * ptr) Vt.1D →
ptr → Xn result.val[0]

Vt2.2D →
int64x2x2_t vld1q_s64_x2 result.val[1]
LD1 {Vt.2D - Vt2.2D},[Xn] ARMv7, ARMv8
(int64_t const * ptr) Vt.2D →
ptr → Xn result.val[0]

Vt2.2D →
uint64x2x2_t vld1q_u64_x2 result.val[1]
LD1 {Vt.2D - Vt2.2D},[Xn] ARMv7, ARMv8
(uint64_t const * ptr) Vt.2D →
ptr → Xn result.val[0]

Vt2.2D →
poly64x2x2_t vld1q_p64_x2 result.val[1]
LD1 {Vt.2D - Vt2.2D},[Xn] ARMv8
(poly64_t const * ptr) Vt.2D →
ptr → Xn result.val[0]

Vt2.1D →
float64x1x2_t vld1_f64_x2 result.val[1]
LD1 {Vt.1D - Vt2.1D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) Vt.1D →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 265 of 348
Non-Confidential
 Vt2.2D →
float64x2x2_t vld1q_f64_x2 result.val[1]
LD1 {Vt.2D - Vt2.2D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) Vt.2D →
ptr → Xn result.val[0]

Vt3.8B →
result.val[2]
int8x8x3_t vld1_s8_x3 Vt2.8B →
LD1 {Vt.8B - Vt3.8B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) result.val[1]
Vt.8B →
ptr → Xn result.val[0]

Vt3.16B →
result.val[2]
int8x16x3_t vld1q_s8_x3 Vt2.16B →
LD1 {Vt.16B - Vt3.16B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) result.val[1]
Vt.16B →
ptr → Xn result.val[0]

Vt3.4H →
result.val[2]
int16x4x3_t vld1_s16_x3 Vt2.4H →
LD1 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt3.8H →
result.val[2]
int16x8x3_t vld1q_s16_x3 Vt2.8H →
LD1 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt3.2S →
result.val[2]
int32x2x3_t vld1_s32_x3 Vt2.2S →
LD1 {Vt.2S - Vt3.2S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt3.4S →
result.val[2]
int32x4x3_t vld1q_s32_x3 Vt2.4S →
LD1 {Vt.4S - Vt3.4S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt3.8B →
result.val[2]
uint8x8x3_t vld1_u8_x3 Vt2.8B →
LD1 {Vt.8B - Vt3.8B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) result.val[1]
Vt.8B →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 266 of 348
Non-Confidential
 Vt3.16B →
result.val[2]
uint8x16x3_t vld1q_u8_x3 Vt2.16B →
LD1 {Vt.16B - Vt3.16B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) result.val[1]
Vt.16B →
ptr → Xn result.val[0]

Vt3.4H →
result.val[2]
uint16x4x3_t vld1_u16_x3 Vt2.4H →
LD1 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt3.8H →
result.val[2]
uint16x8x3_t vld1q_u16_x3 Vt2.8H →
LD1 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt3.2S →
result.val[2]
uint32x2x3_t vld1_u32_x3 Vt2.2S →
LD1 {Vt.2S - Vt3.2S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt3.4S →
result.val[2]
uint32x4x3_t vld1q_u32_x3 Vt2.4S →
LD1 {Vt.4S - Vt3.4S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt3.4H →
result.val[2]
float16x4x3_t vld1_f16_x3 Vt2.4H →
LD1 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt3.8H →
result.val[2]
float16x8x3_t vld1q_f16_x3 Vt2.8H →
LD1 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt3.2S →
result.val[2]
float32x2x3_t vld1_f32_x3 Vt2.2S →
LD1 {Vt.2S - Vt3.2S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) result.val[1]
Vt.2S →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 267 of 348
Non-Confidential
 Vt3.4S →
result.val[2]
float32x4x3_t vld1q_f32_x3 Vt2.4S →
LD1 {Vt.4S - Vt3.4S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt3.8B →
result.val[2]
poly8x8x3_t vld1_p8_x3 Vt2.8B →
LD1 {Vt.8B - Vt3.8B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) result.val[1]
Vt.8B →
ptr → Xn result.val[0]

Vt3.16B →
result.val[2]
poly8x16x3_t vld1q_p8_x3 Vt2.16B →
LD1 {Vt.16B - Vt3.16B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) result.val[1]
Vt.16B →
ptr → Xn result.val[0]

Vt3.4H →
result.val[2]
poly16x4x3_t vld1_p16_x3 Vt2.4H →
LD1 {Vt.4H - Vt3.4H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt3.8H →
result.val[2]
poly16x8x3_t vld1q_p16_x3 Vt2.8H →
LD1 {Vt.8H - Vt3.8H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt3.1D →
result.val[2]
int64x1x3_t vld1_s64_x3 Vt2.1D →
LD1 {Vt.1D - Vt3.1D},[Xn] ARMv7, ARMv8
(int64_t const * ptr) result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt3.1D →
result.val[2]
uint64x1x3_t vld1_u64_x3 Vt2.1D →
LD1 {Vt.1D - Vt3.1D},[Xn] ARMv7, ARMv8
(uint64_t const * ptr) result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt3.1D →
result.val[2]
poly64x1x3_t vld1_p64_x3 Vt2.1D →
LD1 {Vt.1D - Vt3.1D},[Xn] ARMv8
(poly64_t const * ptr) result.val[1]
Vt.1D →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 268 of 348
Non-Confidential
 Vt3.2D →
result.val[2]
int64x2x3_t vld1q_s64_x3 Vt2.2D →
LD1 {Vt.2D - Vt3.2D},[Xn] ARMv7, ARMv8
(int64_t const * ptr) result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt3.2D →
result.val[2]
uint64x2x3_t vld1q_u64_x3 Vt2.2D →
LD1 {Vt.2D - Vt3.2D},[Xn] ARMv7, ARMv8
(uint64_t const * ptr) result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt3.2D →
result.val[2]
poly64x2x3_t vld1q_p64_x3 Vt2.2D →
LD1 {Vt.2D - Vt3.2D},[Xn] ARMv8
(poly64_t const * ptr) result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt3.1D →
result.val[2]
float64x1x3_t vld1_f64_x3 Vt2.1D →
LD1 {Vt.1D - Vt3.1D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt3.2D →
result.val[2]
float64x2x3_t vld1q_f64_x3 Vt2.2D →
LD1 {Vt.2D - Vt3.2D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt4.8B →
result.val[3]
Vt3.8B →
int8x8x4_t vld1_s8_x4 result.val[2]
LD1 {Vt.8B - Vt4.8B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) Vt2.8B →
result.val[1]
Vt.8B →
ptr → Xn result.val[0]

Vt4.16B →
result.val[3]
Vt3.16B →
int8x16x4_t vld1q_s8_x4 result.val[2]
LD1 {Vt.16B - Vt4.16B},[Xn] ARMv7, ARMv8
(int8_t const * ptr) Vt2.16B →
result.val[1]
Vt.16B →
ptr → Xn result.val[0]

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Non-Confidential
 Vt4.4H →
result.val[3]
Vt3.4H →
int16x4x4_t vld1_s16_x4 result.val[2]
LD1 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) Vt2.4H →
result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt4.8H →
result.val[3]
Vt3.8H →
int16x8x4_t vld1q_s16_x4 result.val[2]
LD1 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
(int16_t const * ptr) Vt2.8H →
result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt4.2S →
result.val[3]
Vt3.2S →
int32x2x4_t vld1_s32_x4 result.val[2]
LD1 {Vt.2S - Vt4.2S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) Vt2.2S →
result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt4.4S →
result.val[3]
Vt3.4S →
int32x4x4_t vld1q_s32_x4 result.val[2]
LD1 {Vt.4S - Vt4.4S},[Xn] ARMv7, ARMv8
(int32_t const * ptr) Vt2.4S →
result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt4.8B →
result.val[3]
Vt3.8B →
uint8x8x4_t vld1_u8_x4 result.val[2]
LD1 {Vt.8B - Vt4.8B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) Vt2.8B →
result.val[1]
Vt.8B →
ptr → Xn result.val[0]

Vt4.16B →
result.val[3]
Vt3.16B →
uint8x16x4_t vld1q_u8_x4 result.val[2]
LD1 {Vt.16B - Vt4.16B},[Xn] ARMv7, ARMv8
(uint8_t const * ptr) Vt2.16B →
result.val[1]
Vt.16B →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 270 of 348
Non-Confidential
 Vt4.4H →
result.val[3]
Vt3.4H →
uint16x4x4_t vld1_u16_x4 result.val[2]
LD1 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) Vt2.4H →
result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt4.8H →
result.val[3]
Vt3.8H →
uint16x8x4_t vld1q_u16_x4 result.val[2]
LD1 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
(uint16_t const * ptr) Vt2.8H →
result.val[1]
Vt.8H →
ptr → Xn result.val[0]

Vt4.2S →
result.val[3]
Vt3.2S →
uint32x2x4_t vld1_u32_x4 result.val[2]
LD1 {Vt.2S - Vt4.2S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) Vt2.2S →
result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt4.4S →
result.val[3]
Vt3.4S →
uint32x4x4_t vld1q_u32_x4 result.val[2]
LD1 {Vt.4S - Vt4.4S},[Xn] ARMv7, ARMv8
(uint32_t const * ptr) Vt2.4S →
result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt4.4H →
result.val[3]
Vt3.4H →
float16x4x4_t vld1_f16_x4 result.val[2]
LD1 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) Vt2.4H →
result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt4.8H →
result.val[3]
Vt3.8H →
float16x8x4_t vld1q_f16_x4 result.val[2]
LD1 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
(float16_t const * ptr) Vt2.8H →
result.val[1]
Vt.8H →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 271 of 348
Non-Confidential
 Vt4.2S →
result.val[3]
Vt3.2S →
float32x2x4_t vld1_f32_x4 result.val[2]
LD1 {Vt.2S - Vt4.2S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) Vt2.2S →
result.val[1]
Vt.2S →
ptr → Xn result.val[0]

Vt4.4S →
result.val[3]
Vt3.4S →
float32x4x4_t vld1q_f32_x4 result.val[2]
LD1 {Vt.4S - Vt4.4S},[Xn] ARMv7, ARMv8
(float32_t const * ptr) Vt2.4S →
result.val[1]
Vt.4S →
ptr → Xn result.val[0]

Vt4.8B →
result.val[3]
Vt3.8B →
poly8x8x4_t vld1_p8_x4 result.val[2]
LD1 {Vt.8B - Vt4.8B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) Vt2.8B →
result.val[1]
Vt.8B →
ptr → Xn result.val[0]

Vt4.16B →
result.val[3]
Vt3.16B →
poly8x16x4_t vld1q_p8_x4 result.val[2]
LD1 {Vt.16B - Vt4.16B},[Xn] ARMv7, ARMv8
(poly8_t const * ptr) Vt2.16B →
result.val[1]
Vt.16B →
ptr → Xn result.val[0]

Vt4.4H →
result.val[3]
Vt3.4H →
poly16x4x4_t vld1_p16_x4 result.val[2]
LD1 {Vt.4H - Vt4.4H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) Vt2.4H →
result.val[1]
Vt.4H →
ptr → Xn result.val[0]

Vt4.8H →
result.val[3]
Vt3.8H →
poly16x8x4_t vld1q_p16_x4 result.val[2]
LD1 {Vt.8H - Vt4.8H},[Xn] ARMv7, ARMv8
(poly16_t const * ptr) Vt2.8H →
result.val[1]
Vt.8H →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 272 of 348
Non-Confidential
 Vt4.1D →
result.val[3]
Vt3.1D →
int64x1x4_t vld1_s64_x4 result.val[2]
LD1 {Vt.1D - Vt4.1D},[Xn] ARMv7, ARMv8
(int64_t const * ptr) Vt2.1D →
result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt4.1D →
result.val[3]
Vt3.1D →
uint64x1x4_t vld1_u64_x4 result.val[2]
LD1 {Vt.1D - Vt4.1D},[Xn] ARMv7, ARMv8
(uint64_t const * ptr) Vt2.1D →
result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt4.1D →
result.val[3]
Vt3.1D →
poly64x1x4_t vld1_p64_x4 result.val[2]
LD1 {Vt.1D - Vt4.1D},[Xn] ARMv8
(poly64_t const * ptr) Vt2.1D →
result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt4.2D →
result.val[3]
Vt3.2D →
int64x2x4_t vld1q_s64_x4 result.val[2]
LD1 {Vt.2D - Vt4.2D},[Xn] ARMv7, ARMv8
(int64_t const * ptr) Vt2.2D →
result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt4.2D →
result.val[3]
Vt3.2D →
uint64x2x4_t vld1q_u64_x4 result.val[2]
LD1 {Vt.2D - Vt4.2D},[Xn] ARMv7, ARMv8
(uint64_t const * ptr) Vt2.2D →
result.val[1]
Vt.2D →
ptr → Xn result.val[0]

Vt4.2D →
result.val[3]
Vt3.2D →
poly64x2x4_t vld1q_p64_x4 result.val[2]
LD1 {Vt.2D - Vt4.2D},[Xn] ARMv8
(poly64_t const * ptr) Vt2.2D →
result.val[1]
Vt.2D →
ptr → Xn result.val[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 273 of 348
Non-Confidential
 Vt4.1D →
result.val[3]
Vt3.1D →
float64x1x4_t vld1_f64_x4 result.val[2]
LD1 {Vt.1D - Vt4.1D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) Vt2.1D →
result.val[1]
Vt.1D →
ptr → Xn result.val[0]

Vt4.2D →
result.val[3]
Vt3.2D →
float64x2x4_t vld1q_f64_x4 result.val[2]
LD1 {Vt.2D - Vt4.2D},[Xn] ARMv8(AArch64)
(float64_t const * ptr) Vt2.2D →
result.val[1]
Vt.2D →
ptr → Xn result.val[0]

int8x8_t vpadd_s8
(int8x8_t a, a → Vn.8B ADDP Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int16x4_t vpadd_s16
(int16x4_t a, a → Vn.4H ADDP Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int32x2_t vpadd_s32
(int32x2_t a, a → Vn.2S ADDP Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint8x8_t vpadd_u8
(uint8x8_t a, a → Vn.8B ADDP Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint16x4_t vpadd_u16
(uint16x4_t a, a → Vn.4H ADDP Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint32x2_t vpadd_u32
(uint32x2_t a, a → Vn.2S ADDP Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

float32x2_t vpadd_f32
(float32x2_t a, a → Vn.2S FADDP Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

int8x16_t vpaddq_s8
(int8x16_t a, a → Vn.16B ADDP Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
int8x16_t b) b → Vm.16B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 274 of 348
Non-Confidential
int16x8_t vpaddq_s16
(int16x8_t a, a → Vn.8H ADDP Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int32x4_t vpaddq_s32
(int32x4_t a, a → Vn.4S ADDP Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
int32x4_t b) b → Vm.4S

int64x2_t vpaddq_s64
(int64x2_t a, a → Vn.2D ADDP Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
int64x2_t b) b → Vm.2D

uint8x16_t vpaddq_u8
(uint8x16_t a, a → Vn.16B ADDP Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
uint8x16_t b) b → Vm.16B

uint16x8_t vpaddq_u16
(uint16x8_t a, a → Vn.8H ADDP Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
uint16x8_t b) b → Vm.8H

uint32x4_t vpaddq_u32
(uint32x4_t a, a → Vn.4S ADDP Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
uint32x4_t b) b → Vm.4S

uint64x2_t vpaddq_u64
(uint64x2_t a, a → Vn.2D ADDP Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
uint64x2_t b) b → Vm.2D

float32x4_t vpaddq_f32
(float32x4_t a, a → Vn.4S FADDP Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
float32x4_t b) b → Vm.4S

float64x2_t vpaddq_f64
(float64x2_t a, a → Vn.2D FADDP Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

int16x4_t vpaddl_s8
SADDLP Vd.4H,Vn.8B Vd.4H ARMv7, ARMv8
(int8x8_t a) a → Vn.8B

int16x8_t vpaddlq_s8
SADDLP Vd.8H,Vn.16B Vd.8H ARMv7, ARMv8
(int8x16_t a) a → Vn.16B

int32x2_t vpaddl_s16
SADDLP Vd.2S,Vn.4H Vd.2S ARMv7, ARMv8
(int16x4_t a) a → Vn.4H

int32x4_t vpaddlq_s16
SADDLP Vd.4S,Vn.8H Vd.4S ARMv7, ARMv8
(int16x8_t a) a → Vn.8H

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Non-Confidential
int64x1_t vpaddl_s32
SADDLP Vd.1D,Vn.2S Vd.1D ARMv7, ARMv8
(int32x2_t a) a → Vn.2S

int64x2_t vpaddlq_s32
SADDLP Vd.2D,Vn.4S Vd.2D ARMv7, ARMv8
(int32x4_t a) a → Vn.4S

uint16x4_t vpaddl_u8
UADDLP Vd.4H,Vn.8B Vd.4H ARMv7, ARMv8
(uint8x8_t a) a → Vn.8B

uint16x8_t vpaddlq_u8
UADDLP Vd.8H,Vn.16B Vd.8H ARMv7, ARMv8
(uint8x16_t a) a → Vn.16B

uint32x2_t vpaddl_u16
UADDLP Vd.2S,Vn.4H Vd.2S ARMv7, ARMv8
(uint16x4_t a) a → Vn.4H

uint32x4_t vpaddlq_u16
UADDLP Vd.4S,Vn.8H Vd.4S ARMv7, ARMv8
(uint16x8_t a) a → Vn.8H

uint64x1_t vpaddl_u32
UADDLP Vd.1D,Vn.2S Vd.1D ARMv7, ARMv8
(uint32x2_t a) a → Vn.2S

uint64x2_t vpaddlq_u32
UADDLP Vd.2D,Vn.4S Vd.2D ARMv7, ARMv8
(uint32x4_t a) a → Vn.4S

int16x4_t vpadal_s8
(int16x4_t a, a → Vd.4H SADALP Vd.4H,Vn.8B Vd.4H ARMv7, ARMv8
int8x8_t b) b → Vn.8B

int16x8_t vpadalq_s8
(int16x8_t a, a → Vd.8H SADALP Vd.8H,Vn.16B Vd.8H ARMv7, ARMv8
int8x16_t b) b → Vn.16B

int32x2_t vpadal_s16
(int32x2_t a, a → Vd.2S SADALP Vd.2S,Vn.4H Vd.2S ARMv7, ARMv8
int16x4_t b) b → Vn.4H

int32x4_t vpadalq_s16
(int32x4_t a, a → Vd.4S SADALP Vd.4S,Vn.8H Vd.4S ARMv7, ARMv8
int16x8_t b) b → Vn.8H

int64x1_t vpadal_s32
(int64x1_t a, a → Vd.1D SADALP Vd.1D,Vn.2S Vd.1D ARMv7, ARMv8
int32x2_t b) b → Vn.2S

int64x2_t vpadalq_s32
(int64x2_t a, a → Vd.2D SADALP Vd.2D,Vn.4S Vd.2D ARMv7, ARMv8
int32x4_t b) b → Vn.4S

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Non-Confidential
uint16x4_t vpadal_u8
(uint16x4_t a, a → Vd.4H UADALP Vd.4H,Vn.8B Vd.4H ARMv7, ARMv8
uint8x8_t b) b → Vn.8B

uint16x8_t vpadalq_u8
(uint16x8_t a, a → Vd.8H UADALP Vd.8H,Vn.16B Vd.8H ARMv7, ARMv8
uint8x16_t b) b → Vn.16B

uint32x2_t vpadal_u16
(uint32x2_t a, a → Vd.2S UADALP Vd.2S,Vn.4H Vd.2S ARMv7, ARMv8
uint16x4_t b) b → Vn.4H

uint32x4_t vpadalq_u16
(uint32x4_t a, a → Vd.4S UADALP Vd.4S,Vn.8H Vd.4S ARMv7, ARMv8
uint16x8_t b) b → Vn.8H

uint64x1_t vpadal_u32
(uint64x1_t a, a → Vd.1D UADALP Vd.1D,Vn.2S Vd.1D ARMv7, ARMv8
uint32x2_t b) b → Vn.2S

uint64x2_t vpadalq_u32
(uint64x2_t a, a → Vd.2D UADALP Vd.2D,Vn.4S Vd.2D ARMv7, ARMv8
uint32x4_t b) b → Vn.4S

int8x8_t vpmax_s8
(int8x8_t a, a → Vn.8B SMAXP Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int16x4_t vpmax_s16
(int16x4_t a, a → Vn.4H SMAXP Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int32x2_t vpmax_s32
(int32x2_t a, a → Vn.2S SMAXP Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

uint8x8_t vpmax_u8
(uint8x8_t a, a → Vn.8B UMAXP Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint16x4_t vpmax_u16
(uint16x4_t a, a → Vn.4H UMAXP Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint32x2_t vpmax_u32
(uint32x2_t a, a → Vn.2S UMAXP Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

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Non-Confidential
float32x2_t vpmax_f32
(float32x2_t a, a → Vn.2S FMAXP Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

int8x16_t vpmaxq_s8
(int8x16_t a, a → Vn.16B SMAXP Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
int8x16_t b) b → Vm.16B

int16x8_t vpmaxq_s16
(int16x8_t a, a → Vn.8H SMAXP Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int32x4_t vpmaxq_s32
(int32x4_t a, a → Vn.4S SMAXP Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
int32x4_t b) b → Vm.4S

uint8x16_t vpmaxq_u8
(uint8x16_t a, a → Vn.16B UMAXP Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
uint8x16_t b) b → Vm.16B

uint16x8_t vpmaxq_u16
(uint16x8_t a, a → Vn.8H UMAXP Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
uint16x8_t b) b → Vm.8H

uint32x4_t vpmaxq_u32
(uint32x4_t a, a → Vn.4S UMAXP Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
uint32x4_t b) b → Vm.4S

float32x4_t vpmaxq_f32
(float32x4_t a, a → Vn.4S FMAXP Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
float32x4_t b) b → Vm.4S

float64x2_t vpmaxq_f64
(float64x2_t a, a → Vn.2D FMAXP Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

int8x8_t vpmin_s8
(int8x8_t a, a → Vn.8B SMINP Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm.8B

int16x4_t vpmin_s16
(int16x4_t a, a → Vn.4H SMINP Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
int16x4_t b) b → Vm.4H

int32x2_t vpmin_s32
(int32x2_t a, a → Vn.2S SMINP Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
int32x2_t b) b → Vm.2S

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uint8x8_t vpmin_u8
(uint8x8_t a, a → Vn.8B UMINP Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm.8B

uint16x4_t vpmin_u16
(uint16x4_t a, a → Vn.4H UMINP Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv7, ARMv8
uint16x4_t b) b → Vm.4H

uint32x2_t vpmin_u32
(uint32x2_t a, a → Vn.2S UMINP Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
uint32x2_t b) b → Vm.2S

float32x2_t vpmin_f32
(float32x2_t a, a → Vn.2S FMINP Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv7, ARMv8
float32x2_t b) b → Vm.2S

int8x16_t vpminq_s8
(int8x16_t a, a → Vn.16B SMINP Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
int8x16_t b) b → Vm.16B

int16x8_t vpminq_s16
(int16x8_t a, a → Vn.8H SMINP Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int32x4_t vpminq_s32
(int32x4_t a, a → Vn.4S SMINP Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
int32x4_t b) b → Vm.4S

uint8x16_t vpminq_u8
(uint8x16_t a, a → Vn.16B UMINP Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
uint8x16_t b) b → Vm.16B

uint16x8_t vpminq_u16
(uint16x8_t a, a → Vn.8H UMINP Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
uint16x8_t b) b → Vm.8H

uint32x4_t vpminq_u32
(uint32x4_t a, a → Vn.4S UMINP Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
uint32x4_t b) b → Vm.4S

float32x4_t vpminq_f32
(float32x4_t a, a → Vn.4S FMINP Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
float32x4_t b) b → Vm.4S

float64x2_t vpminq_f64
(float64x2_t a, a → Vn.2D FMINP Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

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float32x2_t vpmaxnm_f32
(float32x2_t a, a → Vn.2S FMAXNMP Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
float32x2_t b) b → Vm.2S

float32x4_t vpmaxnmq_f32
(float32x4_t a, a → Vn.4S FMAXNMP Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
float32x4_t b) b → Vm.4S

float64x2_t vpmaxnmq_f64
(float64x2_t a, a → Vn.2D FMAXNMP Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

float32x2_t vpminnm_f32
(float32x2_t a, a → Vn.2S FMINNMP Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
float32x2_t b) b → Vm.2S

float32x4_t vpminnmq_f32
(float32x4_t a, a → Vn.4S FMINNMP Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
float32x4_t b) b → Vm.4S

float64x2_t vpminnmq_f64
(float64x2_t a, a → Vn.2D FMINNMP Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

int64_t vpaddd_s64
ADDP Dd,Vn.2D Dd ARMv8(AArch64)
(int64x2_t a) a → Vn.2D

uint64_t vpaddd_u64
ADDP Dd,Vn.2D Dd ARMv8(AArch64)
(uint64x2_t a) a → Vn.2D

float32_t vpadds_f32
FADDP Sd,Vn.2S Sd ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

float64_t vpaddd_f64
FADDP Dd,Vn.2D Dd ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

float32_t vpmaxs_f32
FMAXP Sd,Vn.2S Sd ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

float64_t vpmaxqd_f64
FMAXP Dd,Vn.2D Dd ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

float32_t vpmins_f32
FMINP Sd,Vn.2S Sd ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

float64_t vpminqd_f64
FMINP Dd,Vn.2D Dd ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

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float32_t vpmaxnms_f32
FMAXNMP Sd,Vn.2S Sd ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

float64_t vpmaxnmqd_f64
FMAXNMP Dd,Vn.2D Dd ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

float32_t vpminnms_f32
FMINNMP Sd,Vn.2S Sd ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

float64_t vpminnmqd_f64
FMINNMP Dd,Vn.2D Dd ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

int8_t vaddv_s8
ADDV Bd,Vn.8B Bd ARMv8(AArch64)
(int8x8_t a) a → Vn.8B

int8_t vaddvq_s8
ADDV Bd,Vn.16B Bd ARMv8(AArch64)
(int8x16_t a) a → Vn.16B

int16_t vaddv_s16
ADDV Hd,Vn.4H Hd ARMv8(AArch64)
(int16x4_t a) a → Vn.4H

int16_t vaddvq_s16
ADDV Hd,Vn.8H Hd ARMv8(AArch64)
(int16x8_t a) a → Vn.8H

int32_t vaddv_s32 a → Vn.2S

ADDP Vd.2S,Vn.2S,Vm.2S Vd.S[0] ARMv8(AArch64)
(int32x2_t a) a → Vm.2S

int32_t vaddvq_s32
ADDV Sd,Vn.4S Sd ARMv8(AArch64)
(int32x4_t a) a → Vn.4S

int64_t vaddvq_s64
ADDP Dd,Vn.2D Dd ARMv8(AArch64)
(int64x2_t a) a → Vn.2D

uint8_t vaddv_u8
ADDV Bd,Vn.8B Bd ARMv8(AArch64)
(uint8x8_t a) a → Vn.8B

uint8_t vaddvq_u8
ADDV Bd,Vn.16B Bd ARMv8(AArch64)
(uint8x16_t a) a → Vn.16B

uint16_t vaddv_u16
ADDV Hd,Vn.4H Hd ARMv8(AArch64)
(uint16x4_t a) a → Vn.4H

uint16_t vaddvq_u16
ADDV Hd,Vn.8H Hd ARMv8(AArch64)
(uint16x8_t a) a → Vn.8H

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uint32_t vaddv_u32 a → Vn.2S
ADDP Vd.2S,Vn.2S,Vm.2S Vd.S[0] ARMv8(AArch64)
(uint32x2_t a) a → Vm.2S

uint32_t vaddvq_u32
ADDV Sd,Vn.4S Sd ARMv8(AArch64)
(uint32x4_t a) a → Vn.4S

uint64_t vaddvq_u64
ADDP Dd,Vn.2D Dd ARMv8(AArch64)
(uint64x2_t a) a → Vn.2D

float32_t vaddv_f32
FADDP Sd,Vn.2S Sd ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

float32_t vaddvq_f32 a → Vn.4S FADDP Vt.4S,Vn.4S,Vm.4S

Sd ARMv8(AArch64)
(float32x4_t a) a → Vm.4S FADDP Sd,Vt.2S

float64_t vaddvq_f64
FADDP Dd,Vn.2D Dd ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

int16_t vaddlv_s8
SADDLV Hd,Vn.8B Hd ARMv8(AArch64)
(int8x8_t a) a → Vn.8B

int16_t vaddlvq_s8
SADDLV Hd,Vn.16B Hd ARMv8(AArch64)
(int8x16_t a) a → Vn.16B

int32_t vaddlv_s16
SADDLV Sd,Vn.4H Sd ARMv8(AArch64)
(int16x4_t a) a → Vn.4H

int32_t vaddlvq_s16
SADDLV Sd,Vn.8H Sd ARMv8(AArch64)
(int16x8_t a) a → Vn.8H

int64_t vaddlv_s32
SADDLP Vd.1D,Vn.2S Dd ARMv8(AArch64)
(int32x2_t a) a → Vn.2S

int64_t vaddlvq_s32
SADDLV Dd,Vn.4S Dd ARMv8(AArch64)
(int32x4_t a) a → Vn.4S

uint16_t vaddlv_u8
UADDLV Hd,Vn.8B Hd ARMv8(AArch64)
(uint8x8_t a) a → Vn.8B

uint16_t vaddlvq_u8
UADDLV Hd,Vn.16B Hd ARMv8(AArch64)
(uint8x16_t a) a → Vn.16B

uint32_t vaddlv_u16
UADDLV Sd,Vn.4H Sd ARMv8(AArch64)
(uint16x4_t a) a → Vn.4H

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uint32_t vaddlvq_u16
UADDLV Sd,Vn.8H Sd ARMv8(AArch64)
(uint16x8_t a) a → Vn.8H

uint64_t vaddlv_u32
UADDLP Vd.1D,Vn.2S Dd ARMv8(AArch64)
(uint32x2_t a) a → Vn.2S

uint64_t vaddlvq_u32
UADDLV Dd,Vn.4S Dd ARMv8(AArch64)
(uint32x4_t a) a → Vn.4S

int8_t vmaxv_s8
SMAXV Bd,Vn.8B Bd ARMv8(AArch64)
(int8x8_t a) a → Vn.8B

int8_t vmaxvq_s8
SMAXV Bd,Vn.16B Bd ARMv8(AArch64)
(int8x16_t a) a → Vn.16B

int16_t vmaxv_s16
SMAXV Hd,Vn.4H Hd ARMv8(AArch64)
(int16x4_t a) a → Vn.4H

int16_t vmaxvq_s16
SMAXV Hd,Vn.8H Hd ARMv8(AArch64)
(int16x8_t a) a → Vn.8H

int32_t vmaxv_s32 a → Vn.2S

SMAXP Vd.2S,Vn.2S,Vm.2S Vd.S[0] ARMv8(AArch64)
(int32x2_t a) a → Vm.2S

int32_t vmaxvq_s32
SMAXV Sd,Vn.4S Sd ARMv8(AArch64)
(int32x4_t a) a → Vn.4S

uint8_t vmaxv_u8
UMAXV Bd,Vn.8B Bd ARMv8(AArch64)
(uint8x8_t a) a → Vn.8B

uint8_t vmaxvq_u8
UMAXV Bd,Vn.16B Bd ARMv8(AArch64)
(uint8x16_t a) a → Vn.16B

uint16_t vmaxv_u16
UMAXV Hd,Vn.4H Hd ARMv8(AArch64)
(uint16x4_t a) a → Vn.4H

uint16_t vmaxvq_u16
UMAXV Hd,Vn.8H Hd ARMv8(AArch64)
(uint16x8_t a) a → Vn.8H

uint32_t vmaxv_u32 a → Vn.2S

UMAXP Vd.2S,Vn.2S,Vm.2S Vd.S[0] ARMv8(AArch64)
(uint32x2_t a) a → Vm.2S

uint32_t vmaxvq_u32
UMAXV Sd,Vn.4S Sd ARMv8(AArch64)
(uint32x4_t a) a → Vn.4S

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float32_t vmaxv_f32
FMAXP Sd,Vn.2S Sd ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

float32_t vmaxvq_f32
FMAXV Sd,Vn.4S Sd ARMv8(AArch64)
(float32x4_t a) a → Vn.4S

float64_t vmaxvq_f64
FMAXP Dd,Vn.2D Dd ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

int8_t vminv_s8
SMINV Bd,Vn.8B Bd ARMv8(AArch64)
(int8x8_t a) a → Vn.8B

int8_t vminvq_s8
SMINV Bd,Vn.16B Bd ARMv8(AArch64)
(int8x16_t a) a → Vn.16B

int16_t vminv_s16
SMINV Hd,Vn.4H Hd ARMv8(AArch64)
(int16x4_t a) a → Vn.4H

int16_t vminvq_s16
SMINV Hd,Vn.8H Hd ARMv8(AArch64)
(int16x8_t a) a → Vn.8H

int32_t vminv_s32 a → Vn.2S

SMINP Vd.2S,Vn.2S,Vm.2S Vd.S[0] ARMv8(AArch64)
(int32x2_t a) a → Vm.2S

int32_t vminvq_s32
SMINV Sd,Vn.4S Sd ARMv8(AArch64)
(int32x4_t a) a → Vn.4S

uint8_t vminv_u8
UMINV Bd,Vn.8B Bd ARMv8(AArch64)
(uint8x8_t a) a → Vn.8B

uint8_t vminvq_u8
UMINV Bd,Vn.16B Bd ARMv8(AArch64)
(uint8x16_t a) a → Vn.16B

uint16_t vminv_u16
UMINV Hd,Vn.4H Hd ARMv8(AArch64)
(uint16x4_t a) a → Vn.4H

uint16_t vminvq_u16
UMINV Hd,Vn.8H Hd ARMv8(AArch64)
(uint16x8_t a) a → Vn.8H

uint32_t vminv_u32 a → Vn.2S

UMINP Vd.2S,Vn.2S,Vm.2S Vd.S[0] ARMv8(AArch64)
(uint32x2_t a) a → Vm.2S

uint32_t vminvq_u32
UMINV Sd,Vn.4S Sd ARMv8(AArch64)
(uint32x4_t a) a → Vn.4S

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float32_t vminv_f32
FMINP Sd,Vn.2S Sd ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

float32_t vminvq_f32
FMINV Sd,Vn.4S Sd ARMv8(AArch64)
(float32x4_t a) a → Vn.4S

float64_t vminvq_f64
FMINP Dd,Vn.2D Dd ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

float32_t vmaxnmv_f32
FMAXNMP Sd,Vn.2S Sd ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

float32_t vmaxnmvq_f32
FMAXNMV Sd,Vn.4S Sd ARMv8(AArch64)
(float32x4_t a) a → Vn.4S

float64_t vmaxnmvq_f64
FMAXNMP Dd,Vn.2D Dd ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

float32_t vminnmv_f32
FMINNMP Sd,Vn.2S Sd ARMv8(AArch64)
(float32x2_t a) a → Vn.2S

float32_t vminnmvq_f32
FMINNMV Sd,Vn.4S Sd ARMv8(AArch64)
(float32x4_t a) a → Vn.4S

float64_t vminnmvq_f64
FMINNMP Dd,Vn.2D Dd ARMv8(AArch64)
(float64x2_t a) a → Vn.2D

int8x8_t vext_s8
(int8x8_t a, a → Vn.8B
EXT Vd.8B,Vn.8B,Vm.8B,#n Vd.8B ARMv7, ARMv8
int8x8_t b, b → Vm.8B
const int n) 0 <= n <= 7

int8x16_t vextq_s8
(int8x16_t a, a → Vn.16B
EXT Vd.16B,Vn.16B,Vm.16B,#n Vd.16B ARMv7, ARMv8
int8x16_t b, b → Vm.16B
const int n) 0 <= n <= 15

int16x4_t vext_s16
(int16x4_t a, a → Vn.8B
EXT Vd.8B,Vn.8B,Vm.8B,#(n<<1) Vd.8B ARMv7, ARMv8
int16x4_t b, b → Vm.8B
const int n) 0 <= n <= 3

int16x8_t vextq_s16
(int16x8_t a, a → Vn.16B EXT
Vd.16B ARMv7, ARMv8
int16x8_t b, b → Vm.16B Vd.16B,Vn.16B,Vm.16B,#(n<<1)
const int n) 0 <= n <= 7

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int32x2_t vext_s32
(int32x2_t a, a → Vn.8B
EXT Vd.8B,Vn.8B,Vm.8B,#(n<<2) Vd.8B ARMv7, ARMv8
int32x2_t b, b → Vm.8B
const int n) 0 <= n <= 1

int32x4_t vextq_s32
(int32x4_t a, a → Vn.16B EXT
Vd.16B ARMv7, ARMv8
int32x4_t b, b → Vm.16B Vd.16B,Vn.16B,Vm.16B,#(n<<2)
const int n) 0 <= n <= 3

int64x1_t vext_s64
(int64x1_t a, a → Vn.8B
EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3) Vd.8B ARMv7, ARMv8
int64x1_t b, b → Vm.8B
const int n) n == 0

int64x2_t vextq_s64
(int64x2_t a, a → Vn.16B EXT
Vd.16B ARMv7, ARMv8
int64x2_t b, b → Vm.16B Vd.16B,Vn.16B,Vm.16B,#(n<<3)
const int n) 0 <= n <= 1

uint8x8_t vext_u8
(uint8x8_t a, a → Vn.8B
EXT Vd.8B,Vn.8B,Vm.8B,#n Vd.8B ARMv7, ARMv8
uint8x8_t b, b → Vm.8B
const int n) 0 <= n <= 7

uint8x16_t vextq_u8
(uint8x16_t a, a → Vn.16B
EXT Vd.16B,Vn.16B,Vm.16B,#n Vd.16B ARMv7, ARMv8
uint8x16_t b, b → Vm.16B
const int n) 0 <= n <= 15

uint16x4_t vext_u16
(uint16x4_t a, a → Vn.8B
EXT Vd.8B,Vn.8B,Vm.8B,#(n<<1) Vd.8B ARMv7, ARMv8
uint16x4_t b, b → Vm.8B
const int n) 0 <= n <= 3

uint16x8_t vextq_u16
(uint16x8_t a, a → Vn.16B EXT
Vd.16B ARMv7, ARMv8
uint16x8_t b, b → Vm.16B Vd.16B,Vn.16B,Vm.16B,#(n<<1)
const int n) 0 <= n <= 7

uint32x2_t vext_u32
(uint32x2_t a, a → Vn.8B
EXT Vd.8B,Vn.8B,Vm.8B,#(n<<2) Vd.8B ARMv7, ARMv8
uint32x2_t b, b → Vm.8B
const int n) 0 <= n <= 1

uint32x4_t vextq_u32
(uint32x4_t a, a → Vn.16B EXT
Vd.16B ARMv7, ARMv8
uint32x4_t b, b → Vm.16B Vd.16B,Vn.16B,Vm.16B,#(n<<2)
const int n) 0 <= n <= 3

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uint64x1_t vext_u64
(uint64x1_t a, a → Vn.8B
EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3) Vd.8B ARMv7, ARMv8
uint64x1_t b, b → Vm.8B
const int n) n == 0

uint64x2_t vextq_u64
(uint64x2_t a, a → Vn.16B EXT
Vd.16B ARMv7, ARMv8
uint64x2_t b, b → Vm.16B Vd.16B,Vn.16B,Vm.16B,#(n<<3)
const int n) 0 <= n <= 1

poly64x1_t vext_p64
(poly64x1_t a, a → Vn.8B
EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3) Vd.8B ARMv8
poly64x1_t b, b → Vm.8B
const int n) n == 0

poly64x2_t vextq_p64
(poly64x2_t a, a → Vn.16B EXT
Vd.16B ARMv8
poly64x2_t b, b → Vm.16B Vd.16B,Vn.16B,Vm.16B,#(n<<3)
const int n) 0 <= n <= 1

float32x2_t vext_f32
(float32x2_t a, a → Vn.8B
EXT Vd.8B,Vn.8B,Vm.8B,#(n<<2) Vd.8B ARMv7, ARMv8
float32x2_t b, b → Vm.8B
const int n) 0 <= n <= 1

float32x4_t vextq_f32
(float32x4_t a, a → Vn.16B EXT
Vd.16B ARMv7, ARMv8
float32x4_t b, b → Vm.16B Vd.16B,Vn.16B,Vm.16B,#(n<<2)
const int n) 0 <= n <= 3

float64x1_t vext_f64
(float64x1_t a, a → Vn.8B
EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3) Vd.8B ARMv8(AArch64)
float64x1_t b, b → Vm.8B
const int n) n == 0

float64x2_t vextq_f64
(float64x2_t a, a → Vn.16B EXT
Vd.16B ARMv8(AArch64)
float64x2_t b, b → Vm.16B Vd.16B,Vn.16B,Vm.16B,#(n<<3)
const int n) 0 <= n <= 1

poly8x8_t vext_p8
(poly8x8_t a, a → Vn.8B
EXT Vd.8B,Vn.8B,Vm.8B,#n Vd.8B ARMv7, ARMv8
poly8x8_t b, b → Vm.8B
const int n) 0 <= n <= 7

poly8x16_t vextq_p8
(poly8x16_t a, a → Vn.16B
EXT Vd.16B,Vn.16B,Vm.16B,#n Vd.16B ARMv7, ARMv8
poly8x16_t b, b → Vm.16B
const int n) 0 <= n <= 15

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poly16x4_t vext_p16
(poly16x4_t a, a → Vn.8B
EXT Vd.8B,Vn.8B,Vm.8B,#(n<<1) Vd.8B ARMv7, ARMv8
poly16x4_t b, b → Vm.8B
const int n) 0 <= n <= 3

poly16x8_t vextq_p16
(poly16x8_t a, a → Vn.16B EXT
Vd.16B ARMv7, ARMv8
poly16x8_t b, b → Vm.16B Vd.16B,Vn.16B,Vm.16B,#(n<<1)
const int n) 0 <= n <= 7

int8x8_t vrev64_s8
REV64 Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(int8x8_t vec) vec → Vn.8B

int8x16_t vrev64q_s8
REV64 Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(int8x16_t vec) vec → Vn.16B

int16x4_t vrev64_s16
REV64 Vd.4H,Vn.4H Vd.4H ARMv7, ARMv8
(int16x4_t vec) vec → Vn.4H

int16x8_t vrev64q_s16
REV64 Vd.8H,Vn.8H Vd.8H ARMv7, ARMv8
(int16x8_t vec) vec → Vn.8H

int32x2_t vrev64_s32
REV64 Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(int32x2_t vec) vec → Vn.2S

int32x4_t vrev64q_s32
REV64 Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(int32x4_t vec) vec → Vn.4S

uint8x8_t vrev64_u8
REV64 Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(uint8x8_t vec) vec → Vn.8B

uint8x16_t vrev64q_u8
REV64 Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(uint8x16_t vec) vec → Vn.16B

uint16x4_t vrev64_u16
REV64 Vd.4H,Vn.4H Vd.4H ARMv7, ARMv8
(uint16x4_t vec) vec → Vn.4H

uint16x8_t vrev64q_u16
REV64 Vd.8H,Vn.8H Vd.8H ARMv7, ARMv8
(uint16x8_t vec) vec → Vn.8H

uint32x2_t vrev64_u32
REV64 Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(uint32x2_t vec) vec → Vn.2S

uint32x4_t vrev64q_u32
REV64 Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(uint32x4_t vec) vec → Vn.4S

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float32x2_t vrev64_f32
REV64 Vd.2S,Vn.2S Vd.2S ARMv7, ARMv8
(float32x2_t vec) vec → Vn.2S

float32x4_t vrev64q_f32
REV64 Vd.4S,Vn.4S Vd.4S ARMv7, ARMv8
(float32x4_t vec) vec → Vn.4S

poly8x8_t vrev64_p8
REV64 Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(poly8x8_t vec) vec → Vn.8B

poly8x16_t vrev64q_p8
REV64 Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(poly8x16_t vec) vec → Vn.16B

poly16x4_t vrev64_p16
REV64 Vd.4H,Vn.4H Vd.4H ARMv7, ARMv8
(poly16x4_t vec) vec → Vn.4H

poly16x8_t vrev64q_p16
REV64 Vd.8H,Vn.8H Vd.8H ARMv7, ARMv8
(poly16x8_t vec) vec → Vn.8H

int8x8_t vrev32_s8
REV32 Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(int8x8_t vec) vec → Vn.8B

int8x16_t vrev32q_s8
REV32 Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(int8x16_t vec) vec → Vn.16B

int16x4_t vrev32_s16
REV32 Vd.4H,Vn.4H Vd.4H ARMv7, ARMv8
(int16x4_t vec) vec → Vn.4H

int16x8_t vrev32q_s16
REV32 Vd.8H,Vn.8H Vd.8H ARMv7, ARMv8
(int16x8_t vec) vec → Vn.8H

uint8x8_t vrev32_u8
REV32 Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(uint8x8_t vec) vec → Vn.8B

uint8x16_t vrev32q_u8
REV32 Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(uint8x16_t vec) vec → Vn.16B

uint16x4_t vrev32_u16
REV32 Vd.4H,Vn.4H Vd.4H ARMv7, ARMv8
(uint16x4_t vec) vec → Vn.4H

uint16x8_t vrev32q_u16
REV32 Vd.8H,Vn.8H Vd.8H ARMv7, ARMv8
(uint16x8_t vec) vec → Vn.8H

poly8x8_t vrev32_p8
REV32 Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(poly8x8_t vec) vec → Vn.8B

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poly8x16_t vrev32q_p8
REV32 Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(poly8x16_t vec) vec → Vn.16B

poly16x4_t vrev32_p16
REV32 Vd.4H,Vn.4H Vd.4H ARMv7, ARMv8
(poly16x4_t vec) vec → Vn.4H

poly16x8_t vrev32q_p16
REV32 Vd.8H,Vn.8H Vd.8H ARMv7, ARMv8
(poly16x8_t vec) vec → Vn.8H

int8x8_t vrev16_s8
REV16 Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(int8x8_t vec) vec → Vn.8B

int8x16_t vrev16q_s8
REV16 Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(int8x16_t vec) vec → Vn.16B

uint8x8_t vrev16_u8
REV16 Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(uint8x8_t vec) vec → Vn.8B

uint8x16_t vrev16q_u8
REV16 Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(uint8x16_t vec) vec → Vn.16B

poly8x8_t vrev16_p8
REV16 Vd.8B,Vn.8B Vd.8B ARMv7, ARMv8
(poly8x8_t vec) vec → Vn.8B

poly8x16_t vrev16q_p8
REV16 Vd.16B,Vn.16B Vd.16B ARMv7, ARMv8
(poly8x16_t vec) vec → Vn.16B

int8x8_t vzip1_s8
(int8x8_t a, a → Vn.8B ZIP1 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
int8x8_t b) b → Vm.8B

int8x16_t vzip1q_s8
(int8x16_t a, a → Vn.16B ZIP1 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
int8x16_t b) b → Vm.16B

int16x4_t vzip1_s16
(int16x4_t a, a → Vn.4H ZIP1 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
int16x4_t b) b → Vm.4H

int16x8_t vzip1q_s16
(int16x8_t a, a → Vn.8H ZIP1 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int32x2_t vzip1_s32
(int32x2_t a, a → Vn.2S ZIP1 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
int32x2_t b) b → Vm.2S

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int32x4_t vzip1q_s32
(int32x4_t a, a → Vn.4S ZIP1 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
int32x4_t b) b → Vm.4S

int64x2_t vzip1q_s64
(int64x2_t a, a → Vn.2D ZIP1 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
int64x2_t b) b → Vm.2D

uint8x8_t vzip1_u8
(uint8x8_t a, a → Vn.8B ZIP1 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
uint8x8_t b) b → Vm.8B

uint8x16_t vzip1q_u8
(uint8x16_t a, a → Vn.16B ZIP1 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
uint8x16_t b) b → Vm.16B

uint16x4_t vzip1_u16
(uint16x4_t a, a → Vn.4H ZIP1 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
uint16x4_t b) b → Vm.4H

uint16x8_t vzip1q_u16
(uint16x8_t a, a → Vn.8H ZIP1 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
uint16x8_t b) b → Vm.8H

uint32x2_t vzip1_u32
(uint32x2_t a, a → Vn.2S ZIP1 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
uint32x2_t b) b → Vm.2S

uint32x4_t vzip1q_u32
(uint32x4_t a, a → Vn.4S ZIP1 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
uint32x4_t b) b → Vm.4S

uint64x2_t vzip1q_u64
(uint64x2_t a, a → Vn.2D ZIP1 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
uint64x2_t b) b → Vm.2D

poly64x2_t vzip1q_p64
(poly64x2_t a, a → Vn.2D ZIP1 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
poly64x2_t b) b → Vm.2D

float32x2_t vzip1_f32
(float32x2_t a, a → Vn.2S ZIP1 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
float32x2_t b) b → Vm.2S

float32x4_t vzip1q_f32
(float32x4_t a, a → Vn.4S ZIP1 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
float32x4_t b) b → Vm.4S

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float64x2_t vzip1q_f64
(float64x2_t a, a → Vn.2D ZIP1 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

poly8x8_t vzip1_p8
(poly8x8_t a, a → Vn.8B ZIP1 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
poly8x8_t b) b → Vm.8B

poly8x16_t vzip1q_p8
(poly8x16_t a, a → Vn.16B ZIP1 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
poly8x16_t b) b → Vm.16B

poly16x4_t vzip1_p16
(poly16x4_t a, a → Vn.4H ZIP1 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
poly16x4_t b) b → Vm.4H

poly16x8_t vzip1q_p16
(poly16x8_t a, a → Vn.8H ZIP1 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
poly16x8_t b) b → Vm.8H

int8x8_t vzip2_s8
(int8x8_t a, a → Vn.8B ZIP2 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
int8x8_t b) b → Vm.8B

int8x16_t vzip2q_s8
(int8x16_t a, a → Vn.16B ZIP2 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
int8x16_t b) b → Vm.16B

int16x4_t vzip2_s16
(int16x4_t a, a → Vn.4H ZIP2 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
int16x4_t b) b → Vm.4H

int16x8_t vzip2q_s16
(int16x8_t a, a → Vn.8H ZIP2 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int32x2_t vzip2_s32
(int32x2_t a, a → Vn.2S ZIP2 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
int32x2_t b) b → Vm.2S

int32x4_t vzip2q_s32
(int32x4_t a, a → Vn.4S ZIP2 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
int32x4_t b) b → Vm.4S

int64x2_t vzip2q_s64
(int64x2_t a, a → Vn.2D ZIP2 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
int64x2_t b) b → Vm.2D

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uint8x8_t vzip2_u8
(uint8x8_t a, a → Vn.8B ZIP2 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
uint8x8_t b) b → Vm.8B

uint8x16_t vzip2q_u8
(uint8x16_t a, a → Vn.16B ZIP2 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
uint8x16_t b) b → Vm.16B

uint16x4_t vzip2_u16
(uint16x4_t a, a → Vn.4H ZIP2 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
uint16x4_t b) b → Vm.4H

uint16x8_t vzip2q_u16
(uint16x8_t a, a → Vn.8H ZIP2 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
uint16x8_t b) b → Vm.8H

uint32x2_t vzip2_u32
(uint32x2_t a, a → Vn.2S ZIP2 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
uint32x2_t b) b → Vm.2S

uint32x4_t vzip2q_u32
(uint32x4_t a, a → Vn.4S ZIP2 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
uint32x4_t b) b → Vm.4S

uint64x2_t vzip2q_u64
(uint64x2_t a, a → Vn.2D ZIP2 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
uint64x2_t b) b → Vm.2D

poly64x2_t vzip2q_p64
(poly64x2_t a, a → Vn.2D ZIP2 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
poly64x2_t b) b → Vm.2D

float32x2_t vzip2_f32
(float32x2_t a, a → Vn.2S ZIP2 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
float32x2_t b) b → Vm.2S

float32x4_t vzip2q_f32
(float32x4_t a, a → Vn.4S ZIP2 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
float32x4_t b) b → Vm.4S

float64x2_t vzip2q_f64
(float64x2_t a, a → Vn.2D ZIP2 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

poly8x8_t vzip2_p8
(poly8x8_t a, a → Vn.8B ZIP2 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
poly8x8_t b) b → Vm.8B

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poly8x16_t vzip2q_p8
(poly8x16_t a, a → Vn.16B ZIP2 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
poly8x16_t b) b → Vm.16B

poly16x4_t vzip2_p16
(poly16x4_t a, a → Vn.4H ZIP2 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
poly16x4_t b) b → Vm.4H

poly16x8_t vzip2q_p16
(poly16x8_t a, a → Vn.8H ZIP2 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
poly16x8_t b) b → Vm.8H

int8x8_t vuzp1_s8
(int8x8_t a, a → Vn.8B UZP1 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
int8x8_t b) b → Vm.8B

int8x16_t vuzp1q_s8
(int8x16_t a, a → Vn.16B UZP1 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
int8x16_t b) b → Vm.16B

int16x4_t vuzp1_s16
(int16x4_t a, a → Vn.4H UZP1 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
int16x4_t b) b → Vm.4H

int16x8_t vuzp1q_s16
(int16x8_t a, a → Vn.8H UZP1 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int32x2_t vuzp1_s32
(int32x2_t a, a → Vn.2S UZP1 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
int32x2_t b) b → Vm.2S

int32x4_t vuzp1q_s32
(int32x4_t a, a → Vn.4S UZP1 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
int32x4_t b) b → Vm.4S

int64x2_t vuzp1q_s64
(int64x2_t a, a → Vn.2D UZP1 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
int64x2_t b) b → Vm.2D

uint8x8_t vuzp1_u8
(uint8x8_t a, a → Vn.8B UZP1 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
uint8x8_t b) b → Vm.8B

uint8x16_t vuzp1q_u8
(uint8x16_t a, a → Vn.16B UZP1 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
uint8x16_t b) b → Vm.16B

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uint16x4_t vuzp1_u16
(uint16x4_t a, a → Vn.4H UZP1 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
uint16x4_t b) b → Vm.4H

uint16x8_t vuzp1q_u16
(uint16x8_t a, a → Vn.8H UZP1 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
uint16x8_t b) b → Vm.8H

uint32x2_t vuzp1_u32
(uint32x2_t a, a → Vn.2S UZP1 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
uint32x2_t b) b → Vm.2S

uint32x4_t vuzp1q_u32
(uint32x4_t a, a → Vn.4S UZP1 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
uint32x4_t b) b → Vm.4S

uint64x2_t vuzp1q_u64
(uint64x2_t a, a → Vn.2D UZP1 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
uint64x2_t b) b → Vm.2D

poly64x2_t vuzp1q_p64
(poly64x2_t a, a → Vn.2D UZP1 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
poly64x2_t b) b → Vm.2D

float32x2_t vuzp1_f32
(float32x2_t a, a → Vn.2S UZP1 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
float32x2_t b) b → Vm.2S

float32x4_t vuzp1q_f32
(float32x4_t a, a → Vn.4S UZP1 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
float32x4_t b) b → Vm.4S

float64x2_t vuzp1q_f64
(float64x2_t a, a → Vn.2D UZP1 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

poly8x8_t vuzp1_p8
(poly8x8_t a, a → Vn.8B UZP1 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
poly8x8_t b) b → Vm.8B

poly8x16_t vuzp1q_p8
(poly8x16_t a, a → Vn.16B UZP1 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
poly8x16_t b) b → Vm.16B

poly16x4_t vuzp1_p16
(poly16x4_t a, a → Vn.4H UZP1 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
poly16x4_t b) b → Vm.4H

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poly16x8_t vuzp1q_p16
(poly16x8_t a, a → Vn.8H UZP1 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
poly16x8_t b) b → Vm.8H

int8x8_t vuzp2_s8
(int8x8_t a, a → Vn.8B UZP2 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
int8x8_t b) b → Vm.8B

int8x16_t vuzp2q_s8
(int8x16_t a, a → Vn.16B UZP2 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
int8x16_t b) b → Vm.16B

int16x4_t vuzp2_s16
(int16x4_t a, a → Vn.4H UZP2 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
int16x4_t b) b → Vm.4H

int16x8_t vuzp2q_s16
(int16x8_t a, a → Vn.8H UZP2 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int32x2_t vuzp2_s32
(int32x2_t a, a → Vn.2S UZP2 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
int32x2_t b) b → Vm.2S

int32x4_t vuzp2q_s32
(int32x4_t a, a → Vn.4S UZP2 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
int32x4_t b) b → Vm.4S

int64x2_t vuzp2q_s64
(int64x2_t a, a → Vn.2D UZP2 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
int64x2_t b) b → Vm.2D

uint8x8_t vuzp2_u8
(uint8x8_t a, a → Vn.8B UZP2 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
uint8x8_t b) b → Vm.8B

uint8x16_t vuzp2q_u8
(uint8x16_t a, a → Vn.16B UZP2 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
uint8x16_t b) b → Vm.16B

uint16x4_t vuzp2_u16
(uint16x4_t a, a → Vn.4H UZP2 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
uint16x4_t b) b → Vm.4H

uint16x8_t vuzp2q_u16
(uint16x8_t a, a → Vn.8H UZP2 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
uint16x8_t b) b → Vm.8H

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uint32x2_t vuzp2_u32
(uint32x2_t a, a → Vn.2S UZP2 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
uint32x2_t b) b → Vm.2S

uint32x4_t vuzp2q_u32
(uint32x4_t a, a → Vn.4S UZP2 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
uint32x4_t b) b → Vm.4S

uint64x2_t vuzp2q_u64
(uint64x2_t a, a → Vn.2D UZP2 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
uint64x2_t b) b → Vm.2D

poly64x2_t vuzp2q_p64
(poly64x2_t a, a → Vn.2D UZP2 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
poly64x2_t b) b → Vm.2D

float32x2_t vuzp2_f32
(float32x2_t a, a → Vn.2S UZP2 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
float32x2_t b) b → Vm.2S

float32x4_t vuzp2q_f32
(float32x4_t a, a → Vn.4S UZP2 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
float32x4_t b) b → Vm.4S

float64x2_t vuzp2q_f64
(float64x2_t a, a → Vn.2D UZP2 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

poly8x8_t vuzp2_p8
(poly8x8_t a, a → Vn.8B UZP2 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
poly8x8_t b) b → Vm.8B

poly8x16_t vuzp2q_p8
(poly8x16_t a, a → Vn.16B UZP2 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
poly8x16_t b) b → Vm.16B

poly16x4_t vuzp2_p16
(poly16x4_t a, a → Vn.4H UZP2 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
poly16x4_t b) b → Vm.4H

poly16x8_t vuzp2q_p16
(poly16x8_t a, a → Vn.8H UZP2 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
poly16x8_t b) b → Vm.8H

int8x8_t vtrn1_s8
(int8x8_t a, a → Vn.8B TRN1 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
int8x8_t b) b → Vm.8B

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int8x16_t vtrn1q_s8
(int8x16_t a, a → Vn.16B TRN1 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
int8x16_t b) b → Vm.16B

int16x4_t vtrn1_s16
(int16x4_t a, a → Vn.4H TRN1 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
int16x4_t b) b → Vm.4H

int16x8_t vtrn1q_s16
(int16x8_t a, a → Vn.8H TRN1 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int32x2_t vtrn1_s32
(int32x2_t a, a → Vn.2S TRN1 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
int32x2_t b) b → Vm.2S

int32x4_t vtrn1q_s32
(int32x4_t a, a → Vn.4S TRN1 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
int32x4_t b) b → Vm.4S

int64x2_t vtrn1q_s64
(int64x2_t a, a → Vn.2D TRN1 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
int64x2_t b) b → Vm.2D

uint8x8_t vtrn1_u8
(uint8x8_t a, a → Vn.8B TRN1 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
uint8x8_t b) b → Vm.8B

uint8x16_t vtrn1q_u8
(uint8x16_t a, a → Vn.16B TRN1 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
uint8x16_t b) b → Vm.16B

uint16x4_t vtrn1_u16
(uint16x4_t a, a → Vn.4H TRN1 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
uint16x4_t b) b → Vm.4H

uint16x8_t vtrn1q_u16
(uint16x8_t a, a → Vn.8H TRN1 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
uint16x8_t b) b → Vm.8H

uint32x2_t vtrn1_u32
(uint32x2_t a, a → Vn.2S TRN1 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
uint32x2_t b) b → Vm.2S

uint32x4_t vtrn1q_u32
(uint32x4_t a, a → Vn.4S TRN1 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
uint32x4_t b) b → Vm.4S

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uint64x2_t vtrn1q_u64
(uint64x2_t a, a → Vn.2D TRN1 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
uint64x2_t b) b → Vm.2D

poly64x2_t vtrn1q_p64
(poly64x2_t a, a → Vn.2D TRN1 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
poly64x2_t b) b → Vm.2D

float32x2_t vtrn1_f32
(float32x2_t a, a → Vn.2S TRN1 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
float32x2_t b) b → Vm.2S

float32x4_t vtrn1q_f32
(float32x4_t a, a → Vn.4S TRN1 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
float32x4_t b) b → Vm.4S

float64x2_t vtrn1q_f64
(float64x2_t a, a → Vn.2D TRN1 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

poly8x8_t vtrn1_p8
(poly8x8_t a, a → Vn.8B TRN1 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
poly8x8_t b) b → Vm.8B

poly8x16_t vtrn1q_p8
(poly8x16_t a, a → Vn.16B TRN1 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
poly8x16_t b) b → Vm.16B

poly16x4_t vtrn1_p16
(poly16x4_t a, a → Vn.4H TRN1 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
poly16x4_t b) b → Vm.4H

poly16x8_t vtrn1q_p16
(poly16x8_t a, a → Vn.8H TRN1 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
poly16x8_t b) b → Vm.8H

int8x8_t vtrn2_s8
(int8x8_t a, a → Vn.8B TRN2 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
int8x8_t b) b → Vm.8B

int8x16_t vtrn2q_s8
(int8x16_t a, a → Vn.16B TRN2 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
int8x16_t b) b → Vm.16B

int16x4_t vtrn2_s16
(int16x4_t a, a → Vn.4H TRN2 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
int16x4_t b) b → Vm.4H

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int16x8_t vtrn2q_s16
(int16x8_t a, a → Vn.8H TRN2 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
int16x8_t b) b → Vm.8H

int32x2_t vtrn2_s32
(int32x2_t a, a → Vn.2S TRN2 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
int32x2_t b) b → Vm.2S

int32x4_t vtrn2q_s32
(int32x4_t a, a → Vn.4S TRN2 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
int32x4_t b) b → Vm.4S

int64x2_t vtrn2q_s64
(int64x2_t a, a → Vn.2D TRN2 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
int64x2_t b) b → Vm.2D

uint8x8_t vtrn2_u8
(uint8x8_t a, a → Vn.8B TRN2 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
uint8x8_t b) b → Vm.8B

uint8x16_t vtrn2q_u8
(uint8x16_t a, a → Vn.16B TRN2 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
uint8x16_t b) b → Vm.16B

uint16x4_t vtrn2_u16
(uint16x4_t a, a → Vn.4H TRN2 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
uint16x4_t b) b → Vm.4H

uint16x8_t vtrn2q_u16
(uint16x8_t a, a → Vn.8H TRN2 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
uint16x8_t b) b → Vm.8H

uint32x2_t vtrn2_u32
(uint32x2_t a, a → Vn.2S TRN2 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
uint32x2_t b) b → Vm.2S

uint32x4_t vtrn2q_u32
(uint32x4_t a, a → Vn.4S TRN2 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
uint32x4_t b) b → Vm.4S

uint64x2_t vtrn2q_u64
(uint64x2_t a, a → Vn.2D TRN2 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
uint64x2_t b) b → Vm.2D

poly64x2_t vtrn2q_p64
(poly64x2_t a, a → Vn.2D TRN2 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
poly64x2_t b) b → Vm.2D

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float32x2_t vtrn2_f32
(float32x2_t a, a → Vn.2S TRN2 Vd.2S,Vn.2S,Vm.2S Vd.2S ARMv8(AArch64)
float32x2_t b) b → Vm.2S

float32x4_t vtrn2q_f32
(float32x4_t a, a → Vn.4S TRN2 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8(AArch64)
float32x4_t b) b → Vm.4S

float64x2_t vtrn2q_f64
(float64x2_t a, a → Vn.2D TRN2 Vd.2D,Vn.2D,Vm.2D Vd.2D ARMv8(AArch64)
float64x2_t b) b → Vm.2D

poly8x8_t vtrn2_p8
(poly8x8_t a, a → Vn.8B TRN2 Vd.8B,Vn.8B,Vm.8B Vd.8B ARMv8(AArch64)
poly8x8_t b) b → Vm.8B

poly8x16_t vtrn2q_p8
(poly8x16_t a, a → Vn.16B TRN2 Vd.16B,Vn.16B,Vm.16B Vd.16B ARMv8(AArch64)
poly8x16_t b) b → Vm.16B

poly16x4_t vtrn2_p16
(poly16x4_t a, a → Vn.4H TRN2 Vd.4H,Vn.4H,Vm.4H Vd.4H ARMv8(AArch64)
poly16x4_t b) b → Vm.4H

poly16x8_t vtrn2q_p16
(poly16x8_t a, a → Vn.8H TRN2 Vd.8H,Vn.8H,Vm.8H Vd.8H ARMv8(AArch64)
poly16x8_t b) b → Vm.8H

int8x8_t vtbl1_s8
(int8x8_t a, Vn → Zeros(64):a TBL Vd.8B,{Vn.16B},Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm

uint8x8_t vtbl1_u8
(uint8x8_t a, Vn → Zeros(64):a TBL Vd.8B,{Vn.16B},Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm

poly8x8_t vtbl1_p8
(poly8x8_t a, Vn → Zeros(64):a TBL Vd.8B,{Vn.16B},Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm

int8x8_t vtbx1_s8 MOVI Vtmp.8B,#8

(int8x8_t a, a → Vd CMHS Vtmp.8B,Vm.8B,Vtmp.8B
Vd.8B ARMv7, ARMv8
int8x8_t b, Vn → Zeros(64):b TBL Vtmp1.8B,{Vn.16B},Vm.8B
int8x8_t c) c → Vm BIF Vd.8B,Vtmp1.8B,Vtmp.8B

uint8x8_t vtbx1_u8 MOVI Vtmp.8B,#8

(uint8x8_t a, a → Vd CMHS Vtmp.8B,Vm.8B,Vtmp.8B
Vd.8B ARMv7, ARMv8
uint8x8_t b, Vn → Zeros(64):b TBL Vtmp1.8B,{Vn.16B},Vm.8B
uint8x8_t c) c → Vm BIF Vd.8B,Vtmp1.8B,Vtmp.8B

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poly8x8_t vtbx1_p8 MOVI Vtmp.8B,#8
(poly8x8_t a, a → Vd CMHS Vtmp.8B,Vm.8B,Vtmp.8B
Vd.8B ARMv7, ARMv8
poly8x8_t b, Vn → Zeros(64):b TBL Vtmp1.8B,{Vn.16B},Vm.8B
uint8x8_t c) c → Vm BIF Vd.8B,Vtmp1.8B, Vtmp.8B

int8x8_t vtbl2_s8 Vn →
(int8x8x2_t a, a.val[1]:a.val[0] TBL Vd.8B,{Vn.16B},Vm.8B Vd.8B ARMv7, ARMv8
int8x8_t b) b → Vm

uint8x8_t vtbl2_u8 Vn →
(uint8x8x2_t a, a.val[1]:a.val[0] TBL Vd.8B,{Vn.16B},Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm

poly8x8_t vtbl2_p8 Vn →
(poly8x8x2_t a, a.val[1]:a.val[0] TBL Vd.8B,{Vn.16B},Vm.8B Vd.8B ARMv7, ARMv8
uint8x8_t b) b → Vm

Vn →
int8x8_t vtbl3_s8 a.val[1]:a.val[0]
TBL
(int8x8x3_t a, Vn+1 → Vd.8B ARMv7, ARMv8
Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
int8x8_t b) Zeros(64):a.val[2]
b → Vm

Vn →
uint8x8_t vtbl3_u8 a.val[1]:a.val[0]
TBL
(uint8x8x3_t a, Vn+1 → Vd.8B ARMv7, ARMv8
Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
uint8x8_t b) Zeros(64):a.val[2]
b → Vm

Vn →
poly8x8_t vtbl3_p8 a.val[1]:a.val[0]
TBL
(poly8x8x3_t a, Vn+1 → Vd.8B ARMv7, ARMv8
Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
uint8x8_t b) Zeros(64):a.val[2]
b → Vm

Vn →
int8x8_t vtbl4_s8 a.val[1]:a.val[0]
TBL
(int8x8x4_t a, Vn+1 → Vd.8B ARMv7, ARMv8
Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
int8x8_t b) a.val[3]:a.val[2]
b → Vm

Vn →
uint8x8_t vtbl4_u8 a.val[1]:a.val[0]
TBL
(uint8x8x4_t a, Vn+1 → Vd.8B ARMv7, ARMv8
Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
uint8x8_t b) a.val[3]:a.val[2]
b → Vm

Vn →
poly8x8_t vtbl4_p8 a.val[1]:a.val[0]
TBL
(poly8x8x4_t a, Vn+1 → Vd.8B ARMv7, ARMv8
Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
uint8x8_t b) a.val[3]:a.val[2]
b → Vm

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 302 of 348
Non-Confidential
int8x8_t vtbx2_s8 a → Vd
(int8x8_t a, Vn →
TBX Vd.8B,{Vn.16B},Vm.8B Vd.8B ARMv7, ARMv8
int8x8x2_t b, b.val[1]:b.val[0]
int8x8_t c) c → Vm

uint8x8_t vtbx2_u8 a → Vd
(uint8x8_t a, Vn →
TBX Vd.8B,{Vn.16B},Vm.8B Vd.8B ARMv7, ARMv8
uint8x8x2_t b, b.val[1]:b.val[0]
uint8x8_t c) c → Vm

poly8x8_t vtbx2_p8 a → Vd
(poly8x8_t a, Vn →
TBX Vd.8B,{Vn.16B},Vm.8B Vd.8B ARMv7, ARMv8
poly8x8x2_t b, b.val[1]:b.val[0]
uint8x8_t c) c → Vm

a → Vd
MOVI Vtmp.8B,#24
int8x8_t vtbx3_s8 Vn →
CMHS Vtmp.8B,Vm.8B,Vtmp.8B
(int8x8_t a, b.val[1]:b.val[0]
TBL Vd.8B ARMv7, ARMv8
int8x8x3_t b, Vn+1 →
Vtmp1.8B,{Vn.16B,Vn+1.16B},Vm.8
int8x8_t c) Zeros(64):b.val[2]
BIF Vd.8B,Vtmp1.8B,Vtmp.8B
c → Vm

a → Vd
MOVI Vtmp.8B,#24
uint8x8_t vtbx3_u8 Vn →
CMHS Vtmp.8B,Vm.8B,Vtmp.8B
(uint8x8_t a, b.val[1]:b.val[0]
TBL Vd.8B ARMv7, ARMv8
uint8x8x3_t b, Vn+1 →
Vtmp1.8B,{Vn.16B,Vn+1.16B},Vm.8B
uint8x8_t c) Zeros(64):b.val[2]
BIF Vd.8B,Vtmp1.8B,Vtmp.8B
c → Vm

a → Vd
MOVI Vtmp.8B,#24
poly8x8_t vtbx3_p8 Vn →
CMHS Vtmp.8B,Vm.8B,Vtmp.8B
(poly8x8_t a, b.val[1]:b.val[0]
TBL Vd.8B ARMv7, ARMv8
poly8x8x3_t b, Vn+1 →
Vtmp1.8B,{Vn.16B,Vn+1.16B},Vm.8B
uint8x8_t c) Zeros(64):b.val[2]
BIF Vd.8B,Vtmp1.8B,Vtmp.8B
c → Vm

a → Vd
int8x8_t vtbx4_s8 Vn →
(int8x8_t a, b.val[1]:b.val[0] TBX
Vd.8B ARMv7, ARMv8
int8x8x4_t b, Vn+1 → Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
int8x8_t c) b.val[3]:b.val[2]
c → Vm

a → Vd
uint8x8_t vtbx4_u8 Vn →
(uint8x8_t a, b.val[1]:b.val[0] TBX
Vd.8B ARMv7, ARMv8
uint8x8x4_t b, Vn+1 → Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
uint8x8_t c) b.val[3]:b.val[2]
c → Vm

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 303 of 348
Non-Confidential
 a → Vd
poly8x8_t vtbx4_p8 Vn →
(poly8x8_t a, b.val[1]:b.val[0] TBX
Vd.8B ARMv7, ARMv8
poly8x8x4_t b, Vn+1 → Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
uint8x8_t c) b.val[3]:b.val[2]
c → Vm

int8x8_t vqtbl1_s8
(int8x16_t t, t → Vn.16B TBL Vd.8B,{Vn.16B},Vm.8B Vd.8B ARMv8(AArch64)
uint8x8_t idx) idx → Vm.8B

int8x16_t vqtbl1q_s8
(int8x16_t t, t → Vn.16B TBL Vd.16B,{Vn.16B},Vm.16B Vd.16B ARMv8(AArch64)
uint8x16_t idx) idx → Vm.16B

uint8x8_t vqtbl1_u8
(uint8x16_t t, t → Vn.16B TBL Vd.8B,{Vn.16B},Vm.8B Vd.8B ARMv8(AArch64)
uint8x8_t idx) idx → Vm.8B

uint8x16_t vqtbl1q_u8
(uint8x16_t t, t → Vn.16B TBL Vd.16B,{Vn.16B},Vm.16B Vd.16B ARMv8(AArch64)
uint8x16_t idx) idx → Vm.16B

poly8x8_t vqtbl1_p8
(poly8x16_t t, t → Vn.16B TBL Vd.8B,{Vn.16B},Vm.8B Vd.8B ARMv8(AArch64)
uint8x8_t idx) idx → Vm.8B

poly8x16_t vqtbl1q_p8
(poly8x16_t t, t → Vn.16B TBL Vd.16B,{Vn.16B},Vm.16B Vd.16B ARMv8(AArch64)
uint8x16_t idx) idx → Vm.16B

int8x8_t vqtbx1_s8
(int8x8_t a, a → Vd.8B
TBX Vd.8B,{Vn.16B},Vm.8B Vd.8B ARMv8(AArch64)
int8x16_t t, t → Vn.16B
uint8x8_t idx) idx → Vm.8B

int8x16_t vqtbx1q_s8
(int8x16_t a, a → Vd.16B
TBX Vd.16B,{Vn.16B},Vm.16B Vd.16B ARMv8(AArch64)
int8x16_t t, t → Vn.16B
uint8x16_t idx) idx → Vm.16B

uint8x8_t vqtbx1_u8
(uint8x8_t a, a → Vd.8B
TBX Vd.8B,{Vn.16B},Vm.8B Vd.8B ARMv8(AArch64)
uint8x16_t t, t → Vn.16B
uint8x8_t idx) idx → Vm.8B

uint8x16_t vqtbx1q_u8
(uint8x16_t a, a → Vd.16B
TBX Vd.16B,{Vn.16B},Vm.16B Vd.16B ARMv8(AArch64)
uint8x16_t t, t → Vn.16B
uint8x16_t idx) idx → Vm.16B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 304 of 348
Non-Confidential
poly8x8_t vqtbx1_p8
(poly8x8_t a, a → Vd.8B
TBX Vd.8B,{Vn.16B},Vm.8B Vd.8B ARMv8(AArch64)
poly8x16_t t, t → Vn.16B
uint8x8_t idx) idx → Vm.8B

poly8x16_t vqtbx1q_p8
(poly8x16_t a, a → Vd.16B
TBX Vd.16B,{Vn.16B},Vm.16B Vd.16B ARMv8(AArch64)
poly8x16_t t, t → Vn.16B
uint8x16_t idx) idx → Vm.16B

t.val[0] → Vn.16B
int8x8_t vqtbl2_s8
t.val[1] → TBL Vd.8B,{Vn.16B -
(int8x16x2_t t, Vd.8B ARMv8(AArch64)
Vn+1.16B Vn+1.16B},Vm.8B
uint8x8_t idx)
idx → Vm.8B

t.val[0] → Vn.16B
int8x16_t vqtbl2q_s8
t.val[1] → TBL Vd.16B,{Vn.16B -
(int8x16x2_t t, Vd.16B ARMv8(AArch64)
Vn+1.16B Vn+1.16B},Vm.16B
uint8x16_t idx)
idx → Vm.16B

t.val[0] → Vn.16B
uint8x8_t vqtbl2_u8
t.val[1] → TBL Vd.8B,{Vn.16B -
(uint8x16x2_t t, Vd.8B ARMv8(AArch64)
Vn+1.16B Vn+1.16B},Vm.8B
uint8x8_t idx)
idx → Vm.8B

t.val[0] → Vn.16B
uint8x16_t vqtbl2q_u8
t.val[1] → TBL Vd.16B,{Vn.16B -
(uint8x16x2_t t, Vd.16B ARMv8(AArch64)
Vn+1.16B Vn+1.16B},Vm.16B
uint8x16_t idx)
idx → Vm.16B

t.val[0] → Vn.16B
poly8x8_t vqtbl2_p8
t.val[1] → TBL Vd.8B,{Vn.16B -
(poly8x16x2_t t, Vd.8B ARMv8(AArch64)
Vn+1.16B Vn+1.16B},Vm.8B
uint8x8_t idx)
idx → Vm.8B

t.val[0] → Vn.16B
poly8x16_t vqtbl2q_p8
t.val[1] → TBL Vd.16B,{Vn.16B -
(poly8x16x2_t t, Vd.16B ARMv8(AArch64)
Vn+1.16B Vn+1.16B},Vm.16B
uint8x16_t idx)
idx → Vm.16B

t.val[0] → Vn.16B
t.val[1] →
int8x8_t vqtbl3_s8
Vn+1.16B TBL Vd.8B,{Vn.16B -
(int8x16x3_t t, Vd.8B ARMv8(AArch64)
t.val[2] → Vn+2.16B},Vm.8B
uint8x8_t idx)
Vn+2.16B
idx → Vm.8B

t.val[0] → Vn.16B
t.val[1] →
int8x16_t vqtbl3q_s8
Vn+1.16B TBL Vd.16B,{Vn.16B -
(int8x16x3_t t, Vd.16B ARMv8(AArch64)
t.val[2] → Vn+2.16B},Vm.16B
uint8x16_t idx)
Vn+2.16B
idx → Vm.16B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 305 of 348
Non-Confidential
 t.val[0] → Vn.16B
t.val[1] →
uint8x8_t vqtbl3_u8
Vn+1.16B TBL Vd.8B,{Vn.16B -
(uint8x16x3_t t, Vd.8B ARMv8(AArch64)
t.val[2] → Vn+2.16B},Vm.8B
uint8x8_t idx)
Vn+2.16B
idx → Vm.8B

t.val[0] → Vn.16B
t.val[1] →
uint8x16_t vqtbl3q_u8
Vn+1.16B TBL Vd.16B,{Vn.16B -
(uint8x16x3_t t, Vd.16B ARMv8(AArch64)
t.val[2] → Vn+2.16B},Vm.16B
uint8x16_t idx)
Vn+2.16B
idx → Vm.16B

t.val[0] → Vn.16B
t.val[1] →
poly8x8_t vqtbl3_p8
Vn+1.16B TBL Vd.8B,{Vn.16B -
(poly8x16x3_t t, Vd.8B ARMv8(AArch64)
t.val[2] → Vn+2.16B},Vm.8B
uint8x8_t idx)
Vn+2.16B
idx → Vm.8B

t.val[0] → Vn.16B
t.val[1] →
poly8x16_t vqtbl3q_p8
Vn+1.16B TBL Vd.16B,{Vn.16B -
(poly8x16x3_t t, Vd.16B ARMv8(AArch64)
t.val[2] → Vn+2.16B},Vm.16B
uint8x16_t idx)
Vn+2.16B
idx → Vm.16B

t.val[0] → Vn.16B
t.val[1] →
Vn+1.16B
int8x8_t vqtbl4_s8
t.val[2] → TBL Vd.8B,{Vn.16B -
(int8x16x4_t t, Vd.8B ARMv8(AArch64)
Vn+2.16B Vn+3.16B},Vm.8B
uint8x8_t idx)
t.val[3] →
Vn+3.16B
idx → Vm.8B

t.val[0] → Vn.16B
t.val[1] →
Vn+1.16B
int8x16_t vqtbl4q_s8
t.val[2] → TBL Vd.16B,{Vn.16B -
(int8x16x4_t t, Vd.16B ARMv8(AArch64)
Vn+2.16B Vn+3.16B},Vm.16B
uint8x16_t idx)
t.val[3] →
Vn+3.16B
idx → Vm.16B

t.val[0] → Vn.16B
t.val[1] →
Vn+1.16B
uint8x8_t vqtbl4_u8
t.val[2] → TBL Vd.8B,{Vn.16B -
(uint8x16x4_t t, Vd.8B ARMv8(AArch64)
Vn+2.16B Vn+3.16B},Vm.8B
uint8x8_t idx)
t.val[3] →
Vn+3.16B
idx → Vm.8B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 306 of 348
Non-Confidential
 t.val[0] → Vn.16B
t.val[1] →
Vn+1.16B
uint8x16_t vqtbl4q_u8
t.val[2] → TBL Vd.16B,{Vn.16B -
(uint8x16x4_t t, Vd.16B ARMv8(AArch64)
Vn+2.16B Vn+3.16B},Vm.16B
uint8x16_t idx)
t.val[3] →
Vn+3.16B
idx → Vm.16B

t.val[0] → Vn.16B
t.val[1] →
Vn+1.16B
poly8x8_t vqtbl4_p8
t.val[2] → TBL Vd.8B,{Vn.16B -
(poly8x16x4_t t, Vd.8B ARMv8(AArch64)
Vn+2.16B Vn+3.16B},Vm.8B
uint8x8_t idx)
t.val[3] →
Vn+3.16B
idx → Vm.8B

t.val[0] → Vn.16B
t.val[1] →
Vn+1.16B
poly8x16_t vqtbl4q_p8
t.val[2] → TBL Vd.16B,{Vn.16B -
(poly8x16x4_t t, Vd.16B ARMv8(AArch64)
Vn+2.16B Vn+3.16B},Vm.16B
uint8x16_t idx)
t.val[3] →
Vn+3.16B
idx → Vm.16B

a → Vd.8B
int8x8_t vqtbx2_s8
t.val[0] → Vn.16B
(int8x8_t a, TBX Vd.8B,{Vn.16B -
t.val[1] → Vd.8B ARMv8(AArch64)
int8x16x2_t t, Vn+1.16B},Vm.8B
Vn+1.16B
uint8x8_t idx)
idx → Vm.8B

a → Vd.16B
int8x16_t vqtbx2q_s8
t.val[0] → Vn.16B
(int8x16_t a, TBX Vd.16B,{Vn.16B -
t.val[1] → Vd.16B ARMv8(AArch64)
int8x16x2_t t, Vn+1.16B},Vm.16B
Vn+1.16B
uint8x16_t idx)
idx → Vm.16B

a → Vd.8B
uint8x8_t vqtbx2_u8
t.val[0] → Vn.16B
(uint8x8_t a, TBX Vd.8B,{Vn.16B -
t.val[1] → Vd.8B ARMv8(AArch64)
uint8x16x2_t t, Vn+1.16B},Vm.8B
Vn+1.16B
uint8x8_t idx)
idx → Vm.8B

a → Vd.16B
uint8x16_t vqtbx2q_u8
t.val[0] → Vn.16B
(uint8x16_t a, TBX Vd.16B,{Vn.16B -
t.val[1] → Vd.16B ARMv8(AArch64)
uint8x16x2_t t, Vn+1.16B},Vm.16B
Vn+1.16B
uint8x16_t idx)
idx → Vm.16B

a → Vd.8B
poly8x8_t vqtbx2_p8
t.val[0] → Vn.16B
(poly8x8_t a, TBX Vd.8B,{Vn.16B -
t.val[1] → Vd.8B ARMv8(AArch64)
poly8x16x2_t t, Vn+1.16B},Vm.8B
Vn+1.16B
uint8x8_t idx)
idx → Vm.8B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 307 of 348
Non-Confidential
 a → Vd.16B
poly8x16_t vqtbx2q_p8
t.val[0] → Vn.16B
(poly8x16_t a, TBX Vd.16B,{Vn.16B -
t.val[1] → Vd.16B ARMv8(AArch64)
poly8x16x2_t t, Vn+1.16B},Vm.16B
Vn+1.16B
uint8x16_t idx)
idx → Vm.16B

a → Vd.8B
t.val[0] → Vn.16B
int8x8_t vqtbx3_s8
t.val[1] →
(int8x8_t a, TBX Vd.8B,{Vn.16B -
Vn+1.16B Vd.8B ARMv8(AArch64)
int8x16x3_t t, Vn+2.16B},Vm.8B
t.val[2] →
uint8x8_t idx)
Vn+2.16B
idx → Vm.8B

a → Vd.16B
t.val[0] → Vn.16B
int8x16_t vqtbx3q_s8
t.val[1] →
(int8x16_t a, TBX Vd.16B,{Vn.16B -
Vn+1.16B Vd.16B ARMv8(AArch64)
int8x16x3_t t, Vn+2.16B},Vm.16B
t.val[2] →
uint8x16_t idx)
Vn+2.16B
idx → Vm.16B

a → Vd.8B
t.val[0] → Vn.16B
uint8x8_t vqtbx3_u8
t.val[1] →
(uint8x8_t a, TBX Vd.8B,{Vn.16B -
Vn+1.16B Vd.8B ARMv8(AArch64)
uint8x16x3_t t, Vn+2.16B},Vm.8B
t.val[2] →
uint8x8_t idx)
Vn+2.16B
idx → Vm.8B

a → Vd.16B
t.val[0] → Vn.16B
uint8x16_t vqtbx3q_u8
t.val[1] →
(uint8x16_t a, TBX Vd.16B,{Vn.16B -
Vn+1.16B Vd.16B ARMv8(AArch64)
uint8x16x3_t t, Vn+2.16B},Vm.16B
t.val[2] →
uint8x16_t idx)
Vn+2.16B
idx → Vm.16B

a → Vd.8B
t.val[0] → Vn.16B
poly8x8_t vqtbx3_p8
t.val[1] →
(poly8x8_t a, TBX Vd.8B,{Vn.16B -
Vn+1.16B Vd.8B ARMv8(AArch64)
poly8x16x3_t t, Vn+2.16B},Vm.8B
t.val[2] →
uint8x8_t idx)
Vn+2.16B
idx → Vm.8B

a → Vd.16B
t.val[0] → Vn.16B
poly8x16_t vqtbx3q_p8
t.val[1] →
(poly8x16_t a, TBX Vd.16B,{Vn.16B -
Vn+1.16B Vd.16B ARMv8(AArch64)
poly8x16x3_t t, Vn+2.16B},Vm.16B
t.val[2] →
uint8x16_t idx)
Vn+2.16B
idx → Vm.16B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 308 of 348
Non-Confidential
 a → Vd.8B
t.val[0] → Vn.16B
t.val[1] →
int8x8_t vqtbx4_s8
Vn+1.16B
(int8x8_t a, TBX Vd.8B,{Vn.16B -
t.val[2] → Vd.8B ARMv8(AArch64)
int8x16x4_t t, Vn+3.16B},Vm.8B
Vn+2.16B
uint8x8_t idx)
t.val[3] →
Vn+3.16B
idx → Vm.8B

a → Vd.16B
t.val[0] → Vn.16B
t.val[1] →
int8x16_t vqtbx4q_s8
Vn+1.16B
(int8x16_t a, TBX Vd.16B,{Vn.16B -
t.val[2] → Vd.16B ARMv8(AArch64)
int8x16x4_t t, Vn+3.16B},Vm.16B
Vn+2.16B
uint8x16_t idx)
t.val[3] →
Vn+3.16B
idx → Vm.16B

a → Vd.8B
t.val[0] → Vn.16B
t.val[1] →
uint8x8_t vqtbx4_u8
Vn+1.16B
(uint8x8_t a, TBX Vd.8B,{Vn.16B -
t.val[2] → Vd.8B ARMv8(AArch64)
uint8x16x4_t t, Vn+3.16B},Vm.8B
Vn+2.16B
uint8x8_t idx)
t.val[3] →
Vn+3.16B
idx → Vm.8B

a → Vd.16B
t.val[0] → Vn.16B
t.val[1] →
uint8x16_t vqtbx4q_u8
Vn+1.16B
(uint8x16_t a, TBX Vd.16B,{Vn.16B -
t.val[2] → Vd.16B ARMv8(AArch64)
uint8x16x4_t t, Vn+3.16B},Vm.16B
Vn+2.16B
uint8x16_t idx)
t.val[3] →
Vn+3.16B
idx → Vm.16B

a → Vd.8B
t.val[0] → Vn.16B
t.val[1] →
poly8x8_t vqtbx4_p8
Vn+1.16B
(poly8x8_t a, TBX Vd.8B,{Vn.16B -
t.val[2] → Vd.8B ARMv8(AArch64)
poly8x16x4_t t, Vn+3.16B},Vm.8B
Vn+2.16B
uint8x8_t idx)
t.val[3] →
Vn+3.16B
idx → Vm.8B

a → Vd.16B
t.val[0] → Vn.16B
t.val[1] →
poly8x16_t vqtbx4q_p8
Vn+1.16B
(poly8x16_t a, TBX Vd.16B,{Vn.16B -
t.val[2] → Vd.16B ARMv8(AArch64)
poly8x16x4_t t, Vn+3.16B},Vm.16B
Vn+2.16B
uint8x16_t idx)
t.val[3] →
Vn+3.16B
idx → Vm.16B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 309 of 348
Non-Confidential
uint8_t vget_lane_u8
(uint8x8_t v, v → Vn.8B UMOV Rd,Vn.B[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 7

uint16_t vget_lane_u16
(uint16x4_t v, v → Vn.4H UMOV Rd,Vn.H[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 3

uint32_t vget_lane_u32
(uint32x2_t v, v → Vn.2S UMOV Rd,Vn.S[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 1

uint64_t vget_lane_u64
(uint64x1_t v, v → Vn.1D UMOV Rd,Vn.D[lane] Rd ARMv7, ARMv8
const int lane) lane == 0

poly64_t vget_lane_p64
(poly64x1_t v, v → Vn.1D UMOV Rd,Vn.D[lane] Rd ARMv8
const int lane) lane == 0

int8_t vget_lane_s8
(int8x8_t v, v → Vn.8B SMOV Rd,Vn.B[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 7

int16_t vget_lane_s16
(int16x4_t v, v → Vn.4H SMOV Rd,Vn.H[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 3

int32_t vget_lane_s32
(int32x2_t v, v → Vn.2S SMOV Rd,Vn.S[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 1

int64_t vget_lane_s64
(int64x1_t v, v → Vn.1D UMOV Rd,Vn.D[lane] Rd ARMv7, ARMv8
const int lane) lane == 0

poly8_t vget_lane_p8
(poly8x8_t v, v → Vn.8B UMOV Rd,Vn.B[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 7

poly16_t vget_lane_p16
(poly16x4_t v, v → Vn.4H UMOV Rd,Vn.H[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 3

float32_t vget_lane_f32
(float32x2_t v, v → Vn.2S DUP Sd,Vn.S[lane] Sd ARMv7, ARMv8
const int lane) 0 <= lane <= 1

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 310 of 348
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float64_t vget_lane_f64
(float64x1_t v, v → Vn.1D DUP Dd,Vn.D[lane] Dd ARMv8(AArch64)
const int lane) lane == 0

uint8_t vgetq_lane_u8
(uint8x16_t v, v → Vn.16B UMOV Rd,Vn.B[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 15

uint16_t vgetq_lane_u16
(uint16x8_t v, v → Vn.8H UMOV Rd,Vn.H[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 7

uint32_t vgetq_lane_u32
(uint32x4_t v, v → Vn.4S UMOV Rd,Vn.S[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 3

uint64_t vgetq_lane_u64
(uint64x2_t v, v → Vn.2D UMOV Rd,Vn.D[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 1

poly64_t vgetq_lane_p64
(poly64x2_t v, v → Vn.2D UMOV Rd,Vn.D[lane] Rd ARMv8
const int lane) 0 <= lane <= 1

int8_t vgetq_lane_s8
(int8x16_t v, v → Vn.16B SMOV Rd,Vn.B[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 15

int16_t vgetq_lane_s16
(int16x8_t v, v → Vn.8H SMOV Rd,Vn.H[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 7

int32_t vgetq_lane_s32
(int32x4_t v, v → Vn.4S SMOV Rd,Vn.S[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 3

int64_t vgetq_lane_s64
(int64x2_t v, v → Vn.2D UMOV Rd,Vn.D[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 1

poly8_t vgetq_lane_p8
(poly8x16_t v, v → Vn.16B UMOV Rd,Vn.B[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 15

poly16_t vgetq_lane_p16
(poly16x8_t v, v → Vn.8H UMOV Rd,Vn.H[lane] Rd ARMv7, ARMv8
const int lane) 0 <= lane <= 7

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 311 of 348
Non-Confidential
float16_t vget_lane_f16
(float16x4_t v, v → Vn.4H DUP Hd,Vn.H[lane] Hd ARMv7, ARMv8
const int lane) 0 <= lane <= 3

float16_t vgetq_lane_f16
(float16x8_t v, v → Vn.8H DUP Hd,Vn.H[lane] Hd ARMv7, ARMv8
const int lane) 0 <= lane <= 7

float32_t vgetq_lane_f32
(float32x4_t v, v → Vn.4S DUP Sd,Vn.S[lane] Sd ARMv7, ARMv8
const int lane) 0 <= lane <= 3

float64_t vgetq_lane_f64
(float64x2_t v, v → Vn.2D DUP Dd,Vn.D[lane] Dd ARMv8(AArch64)
const int lane) 0 <= lane <= 1

uint8x8_t vset_lane_u8
(uint8_t a, a → Rn
INS Vd.B[lane],Rn Vd.8B ARMv7, ARMv8
uint8x8_t v, v → Vd.8B
const int lane) 0 <= lane <= 7

uint16x4_t vset_lane_u16
(uint16_t a, a → Rn
INS Vd.H[lane],Rn Vd.4H ARMv7, ARMv8
uint16x4_t v, v → Vd.4H
const int lane) 0 <= lane <= 3

uint32x2_t vset_lane_u32
(uint32_t a, a → Rn
INS Vd.S[lane],Rn Vd.2S ARMv7, ARMv8
uint32x2_t v, v → Vd.2S
const int lane) 0 <= lane <= 1

uint64x1_t vset_lane_u64
(uint64_t a, a → Rn
INS Vd.D[lane],Rn Vd.1D ARMv7, ARMv8
uint64x1_t v, v → Vd.1D
const int lane) lane == 0

poly64x1_t vset_lane_p64
(poly64_t a, a → Rn
INS Vd.D[lane],Rn Vd.1D ARMv8
poly64x1_t v, v → Vd.1D
const int lane) lane == 0

int8x8_t vset_lane_s8
(int8_t a, a → Rn
INS Vd.B[lane],Rn Vd.8B ARMv7, ARMv8
int8x8_t v, v → Vd.8B
const int lane) 0 <= lane <= 7

int16x4_t vset_lane_s16
(int16_t a, a → Rn
INS Vd.H[lane],Rn Vd.4H ARMv7, ARMv8
int16x4_t v, v → Vd.4H
const int lane) 0 <= lane <= 3

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int32x2_t vset_lane_s32
(int32_t a, a → Rn
INS Vd.S[lane],Rn Vd.2S ARMv7, ARMv8
int32x2_t v, v → Vd.2S
const int lane) 0 <= lane <= 1

int64x1_t vset_lane_s64
(int64_t a, a → Rn
INS Vd.D[lane],Rn Vd.1D ARMv7, ARMv8
int64x1_t v, v → Vd.1D
const int lane) lane == 0

poly8x8_t vset_lane_p8
(poly8_t a, a → Rn
INS Vd.B[lane],Rn Vd.8B ARMv7, ARMv8
poly8x8_t v, v → Vd.8B
const int lane) 0 <= lane <= 7

poly16x4_t vset_lane_p16
(poly16_t a, a → Rn
INS Vd.H[lane],Rn Vd.4H ARMv7, ARMv8
poly16x4_t v, v → Vd.4H
const int lane) 0 <= lane <= 3

float16x4_t vset_lane_f16
(float16_t a, a → VnH
INS Vd.H[lane],Vn.H[0] Vd.4H ARMv7, ARMv8
float16x4_t v, v → Vd.4H
const int lane) 0 <= lane <= 3

float16x8_t vsetq_lane_f16
(float16_t a, a → VnH
INS Vd.H[lane],Vn.H[0] Vd.8H ARMv7, ARMv8
float16x8_t v, v → Vd.8H
const int lane) 0 <= lane <= 7

float32x2_t vset_lane_f32
(float32_t a, a → Rn
INS Vd.S[lane],Rn Vd.2S ARMv7, ARMv8
float32x2_t v, v → Vd.2S
const int lane) 0 <= lane <= 1

float64x1_t vset_lane_f64
(float64_t a, a → Rn
INS Vd.D[lane],Rn Vd.1D ARMv8(AArch64)
float64x1_t v, v → Vd.1D
const int lane) lane == 0

uint8x16_t vsetq_lane_u8
(uint8_t a, a → Rn
INS Vd.B[lane],Rn Vd.16B ARMv7, ARMv8
uint8x16_t v, v → Vd.16B
const int lane) 0 <= lane <= 15

uint16x8_t vsetq_lane_u16
(uint16_t a, a → Rn
INS Vd.H[lane],Rn Vd.8H ARMv7, ARMv8
uint16x8_t v, v → Vd.8H
const int lane) 0 <= lane <= 7

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 313 of 348
Non-Confidential
uint32x4_t vsetq_lane_u32
(uint32_t a, a → Rn
INS Vd.S[lane],Rn Vd.4S ARMv7, ARMv8
uint32x4_t v, v → Vd.4S
const int lane) 0 <= lane <= 3

uint64x2_t vsetq_lane_u64
(uint64_t a, a → Rn
INS Vd.D[lane],Rn Vd.2D ARMv7, ARMv8
uint64x2_t v, v → Vd.2D
const int lane) 0 <= lane <= 1

poly64x2_t vsetq_lane_p64
(poly64_t a, a → Rn
INS Vd.D[lane],Rn Vd.2D ARMv8
poly64x2_t v, v → Vd.2D
const int lane) 0 <= lane <= 1

int8x16_t vsetq_lane_s8
(int8_t a, a → Rn
INS Vd.B[lane],Rn Vd.16B ARMv7, ARMv8
int8x16_t v, v → Vd.16B
const int lane) 0 <= lane <= 15

int16x8_t vsetq_lane_s16
(int16_t a, a → Rn
INS Vd.H[lane],Rn Vd.8H ARMv7, ARMv8
int16x8_t v, v → Vd.8H
const int lane) 0 <= lane <= 7

int32x4_t vsetq_lane_s32
(int32_t a, a → Rn
INS Vd.S[lane],Rn Vd.4S ARMv7, ARMv8
int32x4_t v, v → Vd.4S
const int lane) 0 <= lane <= 3

int64x2_t vsetq_lane_s64
(int64_t a, a → Rn
INS Vd.D[lane],Rn Vd.2D ARMv7, ARMv8
int64x2_t v, v → Vd.2D
const int lane) 0 <= lane <= 1

poly8x16_t vsetq_lane_p8
(poly8_t a, a → Rn
INS Vd.B[lane],Rn Vd.16B ARMv7, ARMv8
poly8x16_t v, v → Vd.16B
const int lane) 0 <= lane <= 15

poly16x8_t vsetq_lane_p16
(poly16_t a, a → Rn
INS Vd.H[lane],Rn Vd.8H ARMv7, ARMv8
poly16x8_t v, v → Vd.8H
const int lane) 0 <= lane <= 7

float32x4_t vsetq_lane_f32
(float32_t a, a → Rn
INS Vd.S[lane],Rn Vd.4S ARMv7, ARMv8
float32x4_t v, v → Vd.4S
const int lane) 0 <= lane <= 3

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 314 of 348
Non-Confidential
float64x2_t vsetq_lane_f64
(float64_t a, a → Rn
INS Vd.D[lane],Rn Vd.2D ARMv8(AArch64)
float64x2_t v, v → Vd.2D
const int lane) 0 <= lane <= 1

float32_t vrecpxs_f32
FRECPX Sd,Sn Sd ARMv8(AArch64)
(float32_t a) a → Sn

float64_t vrecpxd_f64
FRECPX Dd,Dn Dd ARMv8(AArch64)
(float64_t a) a → Dn

float32x2_t vfma_n_f32
(float32x2_t a, a → Vd.2S
FMLA Vd.2S,Vn.2S,Vm.S[0] Vd.2S ARMv7, ARMv8
float32x2_t b, b → Vn.2S
float32_t n) n → Vm.S[0]

float32x4_t vfmaq_n_f32
(float32x4_t a, a → Vd.4S
FMLA Vd.4S,Vn.4S,Vm.S[0] Vd.4S ARMv7, ARMv8
float32x4_t b, b → Vn.4S
float32_t n) n → Vm.S[0]

float32x2_t vfms_n_f32
(float32x2_t a, a → Vd.2S
FMLS Vd.2S,Vn.2S,Vm.S[0] Vd.2S ARMv8(AArch64)
float32x2_t b, b → Vn.2S
float32_t n) n → Vm.S[0]

float32x4_t vfmsq_n_f32
(float32x4_t a, a → Vd.4S
FMLS Vd.4S,Vn.4S,Vm.S[0] Vd.4S ARMv8(AArch64)
float32x4_t b, b → Vn.4S
float32_t n) n → Vm.S[0]

float64x1_t vfma_n_f64
(float64x1_t a, a → Da
FMADD Dd,Dn,Dm,Da Dd ARMv8(AArch64)
float64x1_t b, b → Dn
float64_t n) n → Dm

float64x2_t vfmaq_n_f64
(float64x2_t a, a → Vd.2D
FMLA Vd.2D,Vn.2D,Vm.D[0] Vd.2D ARMv8(AArch64)
float64x2_t b, b → Vn.2D
float64_t n) n → Vm.D[0]

float64x1_t vfms_n_f64
(float64x1_t a, a → Da
FMSUB Dd,Dn,Dm,Da Dd ARMv8(AArch64)
float64x1_t b, b → Dn
float64_t n) n → Dm

float64x2_t vfmsq_n_f64
(float64x2_t a, a → Vd.2D
FMLS Vd.2D,Vn.2D,Vm.D[0] Vd.2D ARMv8(AArch64)
float64x2_t b, b → Vn.2D
float64_t n) n → Vm.D[0]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 315 of 348
Non-Confidential
 Vd1.8B →
int8x8x2_t vtrn_s8
TRN1 Vd1.8B,Vn.8B,Vm.8B result.val[0]
(int8x8_t a, ARMv7, ARMv8
a → Vn.8B TRN2 Vd2.8B,Vn.8B,Vm.8B Vd2.8B →
int8x8_t b)
b → Vm.8B result.val[1]

Vd1.4H →
int16x4x2_t vtrn_s16
TRN1 Vd1.4H,Vn.4H,Vm.4H result.val[0]
(int16x4_t a, ARMv7, ARMv8
a → Vn.4H TRN2 Vd2.4H,Vn.4H,Vm.4H Vd2.4H →
int16x4_t b)
b → Vm.4H result.val[1]

Vd1.8B →
uint8x8x2_t vtrn_u8
TRN1 Vd1.8B,Vn.8B,Vm.8B result.val[0]
(uint8x8_t a, ARMv7, ARMv8
a → Vn.8B TRN2 Vd2.8B,Vn.8B,Vm.8B Vd2.8B →
uint8x8_t b)
b → Vm.8B result.val[1]

Vd1.4H →
uint16x4x2_t vtrn_u16
TRN1 Vd1.4H,Vn.4H,Vm.4H result.val[0]
(uint16x4_t a, ARMv7, ARMv8
a → Vn.4H TRN2 Vd2.4H,Vn.4H,Vm.4H Vd2.4H →
uint16x4_t b)
b → Vm.4H result.val[1]

Vd1.8B →
poly8x8x2_t vtrn_p8
TRN1 Vd1.8B,Vn.8B,Vm.8B result.val[0]
(poly8x8_t a, ARMv7, ARMv8
a → Vn.8B TRN2 Vd2.8B,Vn.8B,Vm.8B Vd2.8B →
poly8x8_t b)
b → Vm.8B result.val[1]

Vd1.4H →
poly16x4x2_t vtrn_p16
TRN1 Vd1.4H,Vn.4H,Vm.4H result.val[0]
(poly16x4_t a, ARMv7, ARMv8
a → Vn.4H TRN2 Vd2.4H,Vn.4H,Vm.4H Vd2.4H →
poly16x4_t b)
b → Vm.4H result.val[1]

Vd1.2S →
int32x2x2_t vtrn_s32
TRN1 Vd1.2S,Vn.2S,Vm.2S result.val[0]
(int32x2_t a, ARMv7, ARMv8
a → Vn.2S TRN2 Vd2.2S,Vn.2S,Vm.2S Vd2.2S →
int32x2_t b)
b → Vm.2S result.val[1]

Vd1.2S →
float32x2x2_t vtrn_f32
TRN1 Vd1.2S,Vn.2S,Vm.2S result.val[0]
(float32x2_t a, ARMv7, ARMv8
a → Vn.2S TRN2 Vd2.2S,Vn.2S,Vm.2S Vd2.2S →
float32x2_t b)
b → Vm.2S result.val[1]

Vd1.2S →
uint32x2x2_t vtrn_u32
TRN1 Vd1.2S,Vn.2S,Vm.2S result.val[0]
(uint32x2_t a, ARMv7, ARMv8
a → Vn.2S TRN2 Vd2.2S,Vn.2S,Vm.2S Vd2.2S →
uint32x2_t b)
b → Vm.2S result.val[1]

Vd1.16B →
int8x16x2_t vtrnq_s8
TRN1 Vd1.16B,Vn.16B,Vm.16B result.val[0]
(int8x16_t a, ARMv7, ARMv8
a → Vn.16B TRN2 Vd2.16B,Vn.16B,Vm.16B Vd2.16B →
int8x16_t b)
b → Vm.16B result.val[1]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 316 of 348
Non-Confidential
 Vd1.8H →
int16x8x2_t vtrnq_s16
TRN1 Vd1.8H,Vn.8H,Vm.8H result.val[0]
(int16x8_t a, ARMv7, ARMv8
a → Vn.8H TRN2 Vd2.8H,Vn.8H,Vm.8H Vd2.8H →
int16x8_t b)
b → Vm.8H result.val[1]

Vd1.4S →
int32x4x2_t vtrnq_s32
TRN1 Vd1.4S,Vn.4S,Vm.4S result.val[0]
(int32x4_t a, ARMv7, ARMv8
a → Vn.4S TRN2 Vd2.4S,Vn.4S,Vm.4S Vd2.4S →
int32x4_t b)
b → Vm.4S result.val[1]

Vd1.4S →
float32x4x2_t vtrnq_f32
TRN1 Vd1.4S,Vn.4S,Vm.4S result.val[0]
(float32x4_t a, ARMv7, ARMv8
a → Vn.4S TRN2 Vd2.4S,Vn.4S,Vm.4S Vd2.4S →
float32x4_t b)
b → Vm.4S result.val[1]

Vd1.16B →
uint8x16x2_t vtrnq_u8
TRN1 Vd1.16B,Vn.16B,Vm.16B result.val[0]
(uint8x16_t a, ARMv7, ARMv8
a → Vn.16B TRN2 Vd2.16B,Vn.16B,Vm.16B Vd2.16B →
uint8x16_t b)
b → Vm.16B result.val[1]

Vd1.8H →
uint16x8x2_t vtrnq_u16
TRN1 Vd1.8H,Vn.8H,Vm.8H result.val[0]
(uint16x8_t a, ARMv7, ARMv8
a → Vn.8H TRN2 Vd2.8H,Vn.8H,Vm.8H Vd2.8H →
uint16x8_t b)
b → Vm.8H result.val[1]

Vd1.4S →
uint32x4x2_t vtrnq_u32
TRN1 Vd1.4S,Vn.4S,Vm.4S result.val[0]
(uint32x4_t a, ARMv7, ARMv8
a → Vn.4S TRN2 Vd2.4S,Vn.4S,Vm.4S Vd2.4S →
uint32x4_t b)
b → Vm.4S result.val[1]

Vd1.16B →
poly8x16x2_t vtrnq_p8
TRN1 Vd1.16B,Vn.16B,Vm.16B result.val[0]
(poly8x16_t a, ARMv7, ARMv8
a → Vn.16B TRN2 Vd2.16B,Vn.16B,Vm.16B Vd2.16B →
poly8x16_t b)
b → Vm.16B result.val[1]

Vd1.8H →
poly16x8x2_t vtrnq_p16
TRN1 Vd1.8H,Vn.8H,Vm.8H result.val[0]
(poly16x8_t a, ARMv7, ARMv8
a → Vn.8H TRN2 Vd2.8H,Vn.8H,Vm.8H Vd2.8H →
poly16x8_t b)
b → Vm.8H result.val[1]

Vd1.8B →
int8x8x2_t vzip_s8
ZIP1 Vd1.8B,Vn.8B,Vm.8B result.val[0]
(int8x8_t a, ARMv7, ARMv8
a → Vn.8B ZIP2 Vd2.8B,Vn.8B,Vm.8B Vd2.8B →
int8x8_t b)
b → Vm.8B result.val[1]

Vd1.4H →
int16x4x2_t vzip_s16
ZIP1 Vd1.4H,Vn.4H,Vm.4H result.val[0]
(int16x4_t a, ARMv7, ARMv8
a → Vn.4H ZIP2 Vd2.4H,Vn.4H,Vm.4H Vd2.4H →
int16x4_t b)
b → Vm.4H result.val[1]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 317 of 348
Non-Confidential
 Vd1.8B →
uint8x8x2_t vzip_u8
ZIP1 Vd1.8B,Vn.8B,Vm.8B result.val[0]
(uint8x8_t a, ARMv7, ARMv8
a → Vn.8B ZIP2 Vd2.8B,Vn.8B,Vm.8B Vd2.8B →
uint8x8_t b)
b → Vm.8B result.val[1]

Vd1.4H →
uint16x4x2_t vzip_u16
ZIP1 Vd1.4H,Vn.4H,Vm.4H result.val[0]
(uint16x4_t a, ARMv7, ARMv8
a → Vn.4H ZIP2 Vd2.4H,Vn.4H,Vm.4H Vd2.4H →
uint16x4_t b)
b → Vm.4H result.val[1]

Vd1.8B →
poly8x8x2_t vzip_p8
ZIP1 Vd1.8B,Vn.8B,Vm.8B result.val[0]
(poly8x8_t a, ARMv7, ARMv8
a → Vn.8B ZIP2 Vd2.8B,Vn.8B,Vm.8B Vd2.8B →
poly8x8_t b)
b → Vm.8B result.val[1]

Vd1.4H →
poly16x4x2_t vzip_p16
ZIP1 Vd1.4H,Vn.4H,Vm.4H result.val[0]
(poly16x4_t a, ARMv7, ARMv8
a → Vn.4H ZIP2 Vd2.4H,Vn.4H,Vm.4H Vd2.4H →
poly16x4_t b)
b → Vm.4H result.val[1]

Vd1.2S →
int32x2x2_t vzip_s32
ZIP1 Vd1.2S,Vn.2S,Vm.2S result.val[0]
(int32x2_t a, ARMv7, ARMv8
a → Vn.2S ZIP2 Vd2.2S,Vn.2S,Vm.2S Vd2.2S →
int32x2_t b)
b → Vm.2S result.val[1]

Vd1.2S →
float32x2x2_t vzip_f32
ZIP1 Vd1.2S,Vn.2S,Vm.2S result.val[0]
(float32x2_t a, ARMv7, ARMv8
a → Vn.2S ZIP2 Vd2.2S,Vn.2S,Vm.2S Vd2.2S →
float32x2_t b)
b → Vm.2S result.val[1]

Vd1.2S →
uint32x2x2_t vzip_u32
ZIP1 Vd1.2S,Vn.2S,Vm.2S result.val[0]
(uint32x2_t a, ARMv7, ARMv8
a → Vn.2S ZIP2 Vd2.2S,Vn.2S,Vm.2S Vd2.2S →
uint32x2_t b)
b → Vm.2S result.val[1]

Vd1.16B →
int8x16x2_t vzipq_s8
ZIP1 Vd1.16B,Vn.16B,Vm.16B result.val[0]
(int8x16_t a, ARMv7, ARMv8
a → Vn.16B ZIP2 Vd2.16B,Vn.16B,Vm.16B Vd2.16B →
int8x16_t b)
b → Vm.16B result.val[1]

Vd1.8H →
int16x8x2_t vzipq_s16
ZIP1 Vd1.8H,Vn.8H,Vm.8H result.val[0]
(int16x8_t a, ARMv7, ARMv8
a → Vn.8H ZIP2 Vd2.8H,Vn.8H,Vm.8H Vd2.8H →
int16x8_t b)
b → Vm.8H result.val[1]

Vd1.4S →
int32x4x2_t vzipq_s32
ZIP1 Vd1.4S,Vn.4S,Vm.4S result.val[0]
(int32x4_t a, ARMv7, ARMv8
a → Vn.4S ZIP2 Vd2.4S,Vn.4S,Vm.4S Vd2.4S →
int32x4_t b)
b → Vm.4S result.val[1]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 318 of 348
Non-Confidential
 Vd1.4S →
float32x4x2_t vzipq_f32
ZIP1 Vd1.4S,Vn.4S,Vm.4S result.val[0]
(float32x4_t a, ARMv7, ARMv8
a → Vn.4S ZIP2 Vd2.4S,Vn.4S,Vm.4S Vd2.4S →
float32x4_t b)
b → Vm.4S result.val[1]

Vd1.16B →
uint8x16x2_t vzipq_u8
ZIP1 Vd1.16B,Vn.16B,Vm.16B result.val[0]
(uint8x16_t a, ARMv7, ARMv8
a → Vn.16B ZIP2 Vd2.16B,Vn.16B,Vm.16B Vd2.16B →
uint8x16_t b)
b → Vm.16B result.val[1]

Vd1.8H →
uint16x8x2_t vzipq_u16
ZIP1 Vd1.8H,Vn.8H,Vm.8H result.val[0]
(uint16x8_t a, ARMv7, ARMv8
a → Vn.8H ZIP2 Vd2.8H,Vn.8H,Vm.8H Vd2.8H →
uint16x8_t b)
b → Vm.8H result.val[1]

Vd1.4S →
uint32x4x2_t vzipq_u32
ZIP1 Vd1.4S,Vn.4S,Vm.4S result.val[0]
(uint32x4_t a, ARMv7, ARMv8
a → Vn.4S ZIP2 Vd2.4S,Vn.4S,Vm.4S Vd2.4S →
uint32x4_t b)
b → Vm.4S result.val[1]

Vd1.16B →
poly8x16x2_t vzipq_p8
ZIP1 Vd1.16B,Vn.16B,Vm.16B result.val[0]
(poly8x16_t a, ARMv7, ARMv8
a → Vn.16B ZIP2 Vd2.16B,Vn.16B,Vm.16B Vd2.16B →
poly8x16_t b)
b → Vm.16B result.val[1]

Vd1.8H →
poly16x8x2_t vzipq_p16
ZIP1 Vd1.8H,Vn.8H,Vm.8H result.val[0]
(poly16x8_t a, ARMv7, ARMv8
a → Vn.8H ZIP2 Vd2.8H,Vn.8H,Vm.8H Vd2.8H →
poly16x8_t b)
b → Vm.8H result.val[1]

Vd1.8B →
int8x8x2_t vuzp_s8
UZP1 Vd1.8B,Vn.8B,Vm.8B result.val[0]
(int8x8_t a, ARMv7, ARMv8
a → Vn.8B UZP2 Vd2.8B,Vn.8B,Vm.8B Vd2.8B →
int8x8_t b)
b → Vm.8B result.val[1]

Vd1.4H →
int16x4x2_t vuzp_s16
UZP1 Vd1.4H,Vn.4H,Vm.4H result.val[0]
(int16x4_t a, ARMv7, ARMv8
a → Vn.4H UZP2 Vd2.4H,Vn.4H,Vm.4H Vd2.4H →
int16x4_t b)
b → Vm.4H result.val[1]

Vd1.2S →
int32x2x2_t vuzp_s32
UZP1 Vd1.2S,Vn.2S,Vm.2S result.val[0]
(int32x2_t a, ARMv7, ARMv8
a → Vn.2S UZP2 Vd2.2S,Vn.2S,Vm.2S Vd2.2S →
int32x2_t b)
b → Vm.2S result.val[1]

Vd1.2S →
float32x2x2_t vuzp_f32
UZP1 Vd1.2S,Vn.2S,Vm.2S result.val[0]
(float32x2_t a, ARMv7, ARMv8
a → Vn.2S UZP2 Vd2.2S,Vn.2S,Vm.2S Vd2.2S →
float32x2_t b)
b → Vm.2S result.val[1]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 319 of 348
Non-Confidential
 Vd1.8B →
uint8x8x2_t vuzp_u8
UZP1 Vd1.8B,Vn.8B,Vm.8B result.val[0]
(uint8x8_t a, ARMv7, ARMv8
a → Vn.8B UZP2 Vd2.8B,Vn.8B,Vm.8B Vd2.8B →
uint8x8_t b)
b → Vm.8B result.val[1]

Vd1.4H →
uint16x4x2_t vuzp_u16
UZP1 Vd1.4H,Vn.4H,Vm.4H result.val[0]
(uint16x4_t a, ARMv7, ARMv8
a → Vn.4H UZP2 Vd2.4H,Vn.4H,Vm.4H Vd2.4H →
uint16x4_t b)
b → Vm.4H result.val[1]

Vd1.2S →
uint32x2x2_t vuzp_u32
UZP1 Vd1.2S,Vn.2S,Vm.2S result.val[0]
(uint32x2_t a, ARMv7, ARMv8
a → Vn.2S UZP2 Vd2.2S,Vn.2S,Vm.2S Vd2.2S →
uint32x2_t b)
b → Vm.2S result.val[1]

Vd1.8B →
poly8x8x2_t vuzp_p8
UZP1 Vd1.8B,Vn.8B,Vm.8B result.val[0]
(poly8x8_t a, ARMv7, ARMv8
a → Vn.8B UZP2 Vd2.8B,Vn.8B,Vm.8B Vd2.8B →
poly8x8_t b)
b → Vm.8B result.val[1]

Vd1.4H →
poly16x4x2_t vuzp_p16
UZP1 Vd1.4H,Vn.4H,Vm.4H result.val[0]
(poly16x4_t a, ARMv7, ARMv8
a → Vn.4H UZP2 Vd2.4H,Vn.4H,Vm.4H Vd2.4H →
poly16x4_t b)
b → Vm.4H result.val[1]

Vd1.16B →
int8x16x2_t vuzpq_s8
UZP1 Vd1.16B,Vn.16B,Vm.16B result.val[0]
(int8x16_t a, ARMv7, ARMv8
a → Vn.16B UZP2 Vd2.16B,Vn.16B,Vm.16B Vd2.16B →
int8x16_t b)
b → Vm.16B result.val[1]

Vd1.8H →
int16x8x2_t vuzpq_s16
UZP1 Vd1.8H,Vn.8H,Vm.8H result.val[0]
(int16x8_t a, ARMv7, ARMv8
a → Vn.8H UZP2 Vd2.8H,Vn.8H,Vm.8H Vd2.8H →
int16x8_t b)
b → Vm.8H result.val[1]

Vd1.4S →
int32x4x2_t vuzpq_s32
UZP1 Vd1.4S,Vn.4S,Vm.4S result.val[0]
(int32x4_t a, ARMv7, ARMv8
a → Vn.4S UZP2 Vd2.4S,Vn.4S,Vm.4S Vd2.4S →
int32x4_t b)
b → Vm.4S result.val[1]

Vd1.4S →
float32x4x2_t vuzpq_f32
UZP1 Vd1.4S,Vn.4S,Vm.4S result.val[0]
(float32x4_t a, ARMv7, ARMv8
a → Vn.4S UZP2 Vd2.4S,Vn.4S,Vm.4S Vd2.4S →
float32x4_t b)
b → Vm.4S result.val[1]

Vd1.16B →
uint8x16x2_t vuzpq_u8
UZP1 Vd1.16B,Vn.16B,Vm.16B result.val[0]
(uint8x16_t a, ARMv7, ARMv8
a → Vn.16B UZP2 Vd2.16B,Vn.16B,Vm.16B Vd2.16B →
uint8x16_t b)
b → Vm.16B result.val[1]

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 320 of 348
Non-Confidential
 Vd1.8H →
uint16x8x2_t vuzpq_u16
UZP1 Vd1.8H,Vn.8H,Vm.8H result.val[0]
(uint16x8_t a, ARMv7, ARMv8
a → Vn.8H UZP2 Vd2.8H,Vn.8H,Vm.8H Vd2.8H →
uint16x8_t b)
b → Vm.8H result.val[1]

Vd1.4S →
uint32x4x2_t vuzpq_u32
UZP1 Vd1.4S,Vn.4S,Vm.4S result.val[0]
(uint32x4_t a, ARMv7, ARMv8
a → Vn.4S UZP2 Vd2.4S,Vn.4S,Vm.4S Vd2.4S →
uint32x4_t b)
b → Vm.4S result.val[1]

Vd1.16B →
poly8x16x2_t vuzpq_p8
UZP1 Vd1.16B,Vn.16B,Vm.16B result.val[0]
(poly8x16_t a, ARMv7, ARMv8
a → Vn.16B UZP2 Vd2.16B,Vn.16B,Vm.16B Vd2.16B →
poly8x16_t b)
b → Vm.16B result.val[1]

Vd1.8H →
poly16x8x2_t vuzpq_p16
UZP1 Vd1.8H,Vn.8H,Vm.8H result.val[0]
(poly16x8_t a, ARMv7, ARMv8
a → Vn.8H UZP2 Vd2.8H,Vn.8H,Vm.8H Vd2.8H →
poly16x8_t b)
b → Vm.8H result.val[1]

int16x4_t vreinterpret_s16_s8
NOP Vd.4H ARMv7, ARMv8
(int8x8_t a) a → Vd.8B

int32x2_t vreinterpret_s32_s8
NOP Vd.2S ARMv7, ARMv8
(int8x8_t a) a → Vd.8B

float32x2_t vreinterpret_f32_s8
NOP Vd.2S ARMv7, ARMv8
(int8x8_t a) a → Vd.8B

uint8x8_t vreinterpret_u8_s8
NOP Vd.8B ARMv7, ARMv8
(int8x8_t a) a → Vd.8B

uint16x4_t vreinterpret_u16_s8
NOP Vd.4H ARMv7, ARMv8
(int8x8_t a) a → Vd.8B

uint32x2_t vreinterpret_u32_s8
NOP Vd.2S ARMv7, ARMv8
(int8x8_t a) a → Vd.8B

poly8x8_t vreinterpret_p8_s8
NOP Vd.8B ARMv7, ARMv8
(int8x8_t a) a → Vd.8B

poly16x4_t vreinterpret_p16_s8
NOP Vd.4H ARMv7, ARMv8
(int8x8_t a) a → Vd.8B

uint64x1_t vreinterpret_u64_s8
NOP Vd.1D ARMv7, ARMv8
(int8x8_t a) a → Vd.8B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 321 of 348
Non-Confidential
int64x1_t vreinterpret_s64_s8
NOP Vd.1D ARMv7, ARMv8
(int8x8_t a) a → Vd.8B

float64x1_t vreinterpret_f64_s8
NOP Vd.1D ARMv8(AArch64)
(int8x8_t a) a → Vd.8B

poly64x1_t vreinterpret_p64_s8
NOP Vd.1D ARMv8
(int8x8_t a) a → Vd.8B

float16x4_t vreinterpret_f16_s8
NOP Vd.4H ARMv7, ARMv8
(int8x8_t a) a → Vd.8B

int8x8_t vreinterpret_s8_s16
NOP Vd.8B ARMv7, ARMv8
(int16x4_t a) a → Vd.4H

int32x2_t vreinterpret_s32_s16
NOP Vd.2S ARMv7, ARMv8
(int16x4_t a) a → Vd.4H

float32x2_t vreinterpret_f32_s16
NOP Vd.2S ARMv7, ARMv8
(int16x4_t a) a → Vd.4H

uint8x8_t vreinterpret_u8_s16
NOP Vd.8B ARMv7, ARMv8
(int16x4_t a) a → Vd.4H

uint16x4_t vreinterpret_u16_s16
NOP Vd.4H ARMv7, ARMv8
(int16x4_t a) a → Vd.4H

uint32x2_t vreinterpret_u32_s16
NOP Vd.2S ARMv7, ARMv8
(int16x4_t a) a → Vd.4H

poly8x8_t vreinterpret_p8_s16
NOP Vd.8B ARMv7, ARMv8
(int16x4_t a) a → Vd.4H

poly16x4_t vreinterpret_p16_s16
NOP Vd.4H ARMv7, ARMv8
(int16x4_t a) a → Vd.4H

uint64x1_t vreinterpret_u64_s16
NOP Vd.1D ARMv7, ARMv8
(int16x4_t a) a → Vd.4H

int64x1_t vreinterpret_s64_s16
NOP Vd.1D ARMv7, ARMv8
(int16x4_t a) a → Vd.4H

float64x1_t vreinterpret_f64_s16
NOP Vd.1D ARMv8(AArch64)
(int16x4_t a) a → Vd.4H

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 322 of 348
Non-Confidential
poly64x1_t vreinterpret_p64_s16
NOP Vd.1D ARMv8
(int16x4_t a) a → Vd.4H

float16x4_t vreinterpret_f16_s16
NOP Vd.4H ARMv7, ARMv8
(int16x4_t a) a → Vd.4H

int8x8_t vreinterpret_s8_s32
NOP Vd.8B ARMv7, ARMv8
(int32x2_t a) a → Vd.2S

int16x4_t vreinterpret_s16_s32
NOP Vd.4H ARMv7, ARMv8
(int32x2_t a) a → Vd.2S

float32x2_t vreinterpret_f32_s32
NOP Vd.2S ARMv7, ARMv8
(int32x2_t a) a → Vd.2S

uint8x8_t vreinterpret_u8_s32
NOP Vd.8B ARMv7, ARMv8
(int32x2_t a) a → Vd.2S

uint16x4_t vreinterpret_u16_s32
NOP Vd.4H ARMv7, ARMv8
(int32x2_t a) a → Vd.2S

uint32x2_t vreinterpret_u32_s32
NOP Vd.2S ARMv7, ARMv8
(int32x2_t a) a → Vd.2S

poly8x8_t vreinterpret_p8_s32
NOP Vd.8B ARMv7, ARMv8
(int32x2_t a) a → Vd.2S

poly16x4_t vreinterpret_p16_s32
NOP Vd.4H ARMv7, ARMv8
(int32x2_t a) a → Vd.2S

uint64x1_t vreinterpret_u64_s32
NOP Vd.1D ARMv7, ARMv8
(int32x2_t a) a → Vd.2S

int64x1_t vreinterpret_s64_s32
NOP Vd.1D ARMv7, ARMv8
(int32x2_t a) a → Vd.2S

float64x1_t vreinterpret_f64_s32
NOP Vd.1D ARMv8(AArch64)
(int32x2_t a) a → Vd.2S

poly64x1_t vreinterpret_p64_s32
NOP Vd.1D ARMv8
(int32x2_t a) a → Vd.2S

float16x4_t vreinterpret_f16_s32
NOP Vd.4H ARMv7, ARMv8
(int32x2_t a) a → Vd.2S

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 323 of 348
Non-Confidential
int8x8_t vreinterpret_s8_f32
NOP Vd.8B ARMv7, ARMv8
(float32x2_t a) a → Vd.2S

int16x4_t vreinterpret_s16_f32
NOP Vd.4H ARMv7, ARMv8
(float32x2_t a) a → Vd.2S

int32x2_t vreinterpret_s32_f32
NOP Vd.2S ARMv7, ARMv8
(float32x2_t a) a → Vd.2S

uint8x8_t vreinterpret_u8_f32
NOP Vd.8B ARMv7, ARMv8
(float32x2_t a) a → Vd.2S

uint16x4_t vreinterpret_u16_f32
NOP Vd.4H ARMv7, ARMv8
(float32x2_t a) a → Vd.2S

uint32x2_t vreinterpret_u32_f32
NOP Vd.2S ARMv7, ARMv8
(float32x2_t a) a → Vd.2S

poly8x8_t vreinterpret_p8_f32
NOP Vd.8B ARMv7, ARMv8
(float32x2_t a) a → Vd.2S

poly16x4_t vreinterpret_p16_f32
NOP Vd.4H ARMv7, ARMv8
(float32x2_t a) a → Vd.2S

uint64x1_t vreinterpret_u64_f32
NOP Vd.1D ARMv7, ARMv8
(float32x2_t a) a → Vd.2S

int64x1_t vreinterpret_s64_f32
NOP Vd.1D ARMv7, ARMv8
(float32x2_t a) a → Vd.2S

float64x1_t vreinterpret_f64_f32
NOP Vd.1D ARMv8(AArch64)
(float32x2_t a) a → Vd.2S

poly64x1_t vreinterpret_p64_f32
NOP Vd.1D ARMv8
(float32x2_t a) a → Vd.2S

poly64x1_t vreinterpret_p64_f64
NOP Vd.1D ARMv8(AArch64)
(float64x1_t a) a → Vd.1D

float16x4_t vreinterpret_f16_f32
NOP Vd.4H ARMv7, ARMv8
(float32x2_t a) a → Vd.2S

int8x8_t vreinterpret_s8_u8
NOP Vd.8B ARMv7, ARMv8
(uint8x8_t a) a → Vd.8B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 324 of 348
Non-Confidential
int16x4_t vreinterpret_s16_u8
NOP Vd.4H ARMv7, ARMv8
(uint8x8_t a) a → Vd.8B

int32x2_t vreinterpret_s32_u8
NOP Vd.2S ARMv7, ARMv8
(uint8x8_t a) a → Vd.8B

float32x2_t vreinterpret_f32_u8
NOP Vd.2S ARMv7, ARMv8
(uint8x8_t a) a → Vd.8B

uint16x4_t vreinterpret_u16_u8
NOP Vd.4H ARMv7, ARMv8
(uint8x8_t a) a → Vd.8B

uint32x2_t vreinterpret_u32_u8
NOP Vd.2S ARMv7, ARMv8
(uint8x8_t a) a → Vd.8B

poly8x8_t vreinterpret_p8_u8
NOP Vd.8B ARMv7, ARMv8
(uint8x8_t a) a → Vd.8B

poly16x4_t vreinterpret_p16_u8
NOP Vd.4H ARMv7, ARMv8
(uint8x8_t a) a → Vd.8B

uint64x1_t vreinterpret_u64_u8
NOP Vd.1D ARMv7, ARMv8
(uint8x8_t a) a → Vd.8B

int64x1_t vreinterpret_s64_u8
NOP Vd.1D ARMv7, ARMv8
(uint8x8_t a) a → Vd.8B

float64x1_t vreinterpret_f64_u8
NOP Vd.1D ARMv8(AArch64)
(uint8x8_t a) a → Vd.8B

poly64x1_t vreinterpret_p64_u8
NOP Vd.1D ARMv8
(uint8x8_t a) a → Vd.8B

float16x4_t vreinterpret_f16_u8
NOP Vd.4H ARMv7, ARMv8
(uint8x8_t a) a → Vd.8B

int8x8_t vreinterpret_s8_u16
NOP Vd.8B ARMv7, ARMv8
(uint16x4_t a) a → Vd.4H

int16x4_t vreinterpret_s16_u16
NOP Vd.4H ARMv7, ARMv8
(uint16x4_t a) a → Vd.4H

int32x2_t vreinterpret_s32_u16
NOP Vd.2S ARMv7, ARMv8
(uint16x4_t a) a → Vd.4H

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 325 of 348
Non-Confidential
float32x2_t vreinterpret_f32_u16
NOP Vd.2S ARMv7, ARMv8
(uint16x4_t a) a → Vd.4H

uint8x8_t vreinterpret_u8_u16
NOP Vd.8B ARMv7, ARMv8
(uint16x4_t a) a → Vd.4H

uint32x2_t vreinterpret_u32_u16
NOP Vd.2S ARMv7, ARMv8
(uint16x4_t a) a → Vd.4H

poly8x8_t vreinterpret_p8_u16
NOP Vd.8B ARMv7, ARMv8
(uint16x4_t a) a → Vd.4H

poly16x4_t vreinterpret_p16_u16
NOP Vd.4H ARMv7, ARMv8
(uint16x4_t a) a → Vd.4H

uint64x1_t vreinterpret_u64_u16
NOP Vd.1D ARMv7, ARMv8
(uint16x4_t a) a → Vd.4H

int64x1_t vreinterpret_s64_u16
NOP Vd.1D ARMv7, ARMv8
(uint16x4_t a) a → Vd.4H

float64x1_t vreinterpret_f64_u16
NOP Vd.1D ARMv8(AArch64)
(uint16x4_t a) a → Vd.4H

poly64x1_t vreinterpret_p64_u16
NOP Vd.1D ARMv8
(uint16x4_t a) a → Vd.4H

float16x4_t vreinterpret_f16_u16
NOP Vd.4H ARMv7, ARMv8
(uint16x4_t a) a → Vd.4H

int8x8_t vreinterpret_s8_u32
NOP Vd.8B ARMv7, ARMv8
(uint32x2_t a) a → Vd.2S

int16x4_t vreinterpret_s16_u32
NOP Vd.4H ARMv7, ARMv8
(uint32x2_t a) a → Vd.2S

int32x2_t vreinterpret_s32_u32
NOP Vd.2S ARMv7, ARMv8
(uint32x2_t a) a → Vd.2S

float32x2_t vreinterpret_f32_u32
NOP Vd.2S ARMv7, ARMv8
(uint32x2_t a) a → Vd.2S

uint8x8_t vreinterpret_u8_u32
NOP Vd.8B ARMv7, ARMv8
(uint32x2_t a) a → Vd.2S

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 326 of 348
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uint16x4_t vreinterpret_u16_u32
NOP Vd.4H ARMv7, ARMv8
(uint32x2_t a) a → Vd.2S

poly8x8_t vreinterpret_p8_u32
NOP Vd.8B ARMv7, ARMv8
(uint32x2_t a) a → Vd.2S

poly16x4_t vreinterpret_p16_u32
NOP Vd.4H ARMv7, ARMv8
(uint32x2_t a) a → Vd.2S

uint64x1_t vreinterpret_u64_u32
NOP Vd.1D ARMv7, ARMv8
(uint32x2_t a) a → Vd.2S

int64x1_t vreinterpret_s64_u32
NOP Vd.1D ARMv7, ARMv8
(uint32x2_t a) a → Vd.2S

float64x1_t vreinterpret_f64_u32
NOP Vd.1D ARMv8(AArch64)
(uint32x2_t a) a → Vd.2S

poly64x1_t vreinterpret_p64_u32
NOP Vd.1D ARMv8
(uint32x2_t a) a → Vd.2S

float16x4_t vreinterpret_f16_u32
NOP Vd.4H ARMv7, ARMv8
(uint32x2_t a) a → Vd.2S

int8x8_t vreinterpret_s8_p8
NOP Vd.8B ARMv7, ARMv8
(poly8x8_t a) a → Vd.8B

int16x4_t vreinterpret_s16_p8
NOP Vd.4H ARMv7, ARMv8
(poly8x8_t a) a → Vd.8B

int32x2_t vreinterpret_s32_p8
NOP Vd.2S ARMv7, ARMv8
(poly8x8_t a) a → Vd.8B

float32x2_t vreinterpret_f32_p8
NOP Vd.2S ARMv7, ARMv8
(poly8x8_t a) a → Vd.8B

uint8x8_t vreinterpret_u8_p8
NOP Vd.8B ARMv7, ARMv8
(poly8x8_t a) a → Vd.8B

uint16x4_t vreinterpret_u16_p8
NOP Vd.4H ARMv7, ARMv8
(poly8x8_t a) a → Vd.8B

uint32x2_t vreinterpret_u32_p8
NOP Vd.2S ARMv7, ARMv8
(poly8x8_t a) a → Vd.8B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 327 of 348
Non-Confidential
poly16x4_t vreinterpret_p16_p8
NOP Vd.4H ARMv7, ARMv8
(poly8x8_t a) a → Vd.8B

uint64x1_t vreinterpret_u64_p8
NOP Vd.1D ARMv7, ARMv8
(poly8x8_t a) a → Vd.8B

int64x1_t vreinterpret_s64_p8
NOP Vd.1D ARMv7, ARMv8
(poly8x8_t a) a → Vd.8B

float64x1_t vreinterpret_f64_p8
NOP Vd.1D ARMv8(AArch64)
(poly8x8_t a) a → Vd.8B

poly64x1_t vreinterpret_p64_p8
NOP Vd.1D ARMv8
(poly8x8_t a) a → Vd.8B

float16x4_t vreinterpret_f16_p8
NOP Vd.4H ARMv7, ARMv8
(poly8x8_t a) a → Vd.8B

int8x8_t vreinterpret_s8_p16
NOP Vd.8B ARMv7, ARMv8
(poly16x4_t a) a → Vd.4H

int16x4_t vreinterpret_s16_p16
NOP Vd.4H ARMv7, ARMv8
(poly16x4_t a) a → Vd.4H

int32x2_t vreinterpret_s32_p16
NOP Vd.2S ARMv7, ARMv8
(poly16x4_t a) a → Vd.4H

float32x2_t vreinterpret_f32_p16
NOP Vd.2S ARMv7, ARMv8
(poly16x4_t a) a → Vd.4H

uint8x8_t vreinterpret_u8_p16
NOP Vd.8B ARMv7, ARMv8
(poly16x4_t a) a → Vd.4H

uint16x4_t vreinterpret_u16_p16
NOP Vd.4H ARMv7, ARMv8
(poly16x4_t a) a → Vd.4H

uint32x2_t vreinterpret_u32_p16
NOP Vd.2S ARMv7, ARMv8
(poly16x4_t a) a → Vd.4H

poly8x8_t vreinterpret_p8_p16
NOP Vd.8B ARMv7, ARMv8
(poly16x4_t a) a → Vd.4H

uint64x1_t vreinterpret_u64_p16
NOP Vd.1D ARMv7, ARMv8
(poly16x4_t a) a → Vd.4H

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 328 of 348
Non-Confidential
int64x1_t vreinterpret_s64_p16
NOP Vd.1D ARMv7, ARMv8
(poly16x4_t a) a → Vd.4H

float64x1_t vreinterpret_f64_p16
NOP Vd.1D ARMv8(AArch64)
(poly16x4_t a) a → Vd.4H

poly64x1_t vreinterpret_p64_p16
NOP Vd.1D ARMv8
(poly16x4_t a) a → Vd.4H

float16x4_t vreinterpret_f16_p16
NOP Vd.4H ARMv7, ARMv8
(poly16x4_t a) a → Vd.4H

int8x8_t vreinterpret_s8_u64
NOP Vd.8B ARMv7, ARMv8
(uint64x1_t a) a → Vd.1D

int16x4_t vreinterpret_s16_u64
NOP Vd.4H ARMv7, ARMv8
(uint64x1_t a) a → Vd.1D

int32x2_t vreinterpret_s32_u64
NOP Vd.2S ARMv7, ARMv8
(uint64x1_t a) a → Vd.1D

float32x2_t vreinterpret_f32_u64
NOP Vd.2S ARMv7, ARMv8
(uint64x1_t a) a → Vd.1D

uint8x8_t vreinterpret_u8_u64
NOP Vd.8B ARMv7, ARMv8
(uint64x1_t a) a → Vd.1D

uint16x4_t vreinterpret_u16_u64
NOP Vd.4H ARMv7, ARMv8
(uint64x1_t a) a → Vd.1D

uint32x2_t vreinterpret_u32_u64
NOP Vd.2S ARMv7, ARMv8
(uint64x1_t a) a → Vd.1D

poly8x8_t vreinterpret_p8_u64
NOP Vd.8B ARMv7, ARMv8
(uint64x1_t a) a → Vd.1D

poly16x4_t vreinterpret_p16_u64
NOP Vd.4H ARMv7, ARMv8
(uint64x1_t a) a → Vd.1D

int64x1_t vreinterpret_s64_u64
NOP Vd.1D ARMv7, ARMv8
(uint64x1_t a) a → Vd.1D

float64x1_t vreinterpret_f64_u64
NOP Vd.1D ARMv8(AArch64)
(uint64x1_t a) a → Vd.1D

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 329 of 348
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poly64x1_t vreinterpret_p64_u64
NOP Vd.1D ARMv8
(uint64x1_t a) a → Vd.1D

float16x4_t vreinterpret_f16_u64
NOP Vd.4H ARMv7, ARMv8
(uint64x1_t a) a → Vd.1D

int8x8_t vreinterpret_s8_s64
NOP Vd.8B ARMv7, ARMv8
(int64x1_t a) a → Vd.1D

int16x4_t vreinterpret_s16_s64
NOP Vd.4H ARMv7, ARMv8
(int64x1_t a) a → Vd.1D

int32x2_t vreinterpret_s32_s64
NOP Vd.2S ARMv7, ARMv8
(int64x1_t a) a → Vd.1D

float32x2_t vreinterpret_f32_s64
NOP Vd.2S ARMv7, ARMv8
(int64x1_t a) a → Vd.1D

uint8x8_t vreinterpret_u8_s64
NOP Vd.8B ARMv7, ARMv8
(int64x1_t a) a → Vd.1D

uint16x4_t vreinterpret_u16_s64
NOP Vd.4H ARMv7, ARMv8
(int64x1_t a) a → Vd.1D

uint32x2_t vreinterpret_u32_s64
NOP Vd.2S ARMv7, ARMv8
(int64x1_t a) a → Vd.1D

poly8x8_t vreinterpret_p8_s64
NOP Vd.8B ARMv7, ARMv8
(int64x1_t a) a → Vd.1D

poly16x4_t vreinterpret_p16_s64
NOP Vd.4H ARMv7, ARMv8
(int64x1_t a) a → Vd.1D

uint64x1_t vreinterpret_u64_s64
NOP Vd.1D ARMv7, ARMv8
(int64x1_t a) a → Vd.1D

float64x1_t vreinterpret_f64_s64
NOP Vd.1D ARMv8(AArch64)
(int64x1_t a) a → Vd.1D

uint64x1_t vreinterpret_u64_p64
NOP Vd.1D ARMv8
(poly64x1_t a) a → Vd.1D

float16x4_t vreinterpret_f16_s64
NOP Vd.4H ARMv7, ARMv8
(int64x1_t a) a → Vd.1D

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 330 of 348
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int8x8_t vreinterpret_s8_f16
NOP Vd.8B ARMv7, ARMv8
(float16x4_t a) a → Vd.4H

int16x4_t vreinterpret_s16_f16
NOP Vd.4H ARMv7, ARMv8
(float16x4_t a) a → Vd.4H

int32x2_t vreinterpret_s32_f16
NOP Vd.2S ARMv7, ARMv8
(float16x4_t a) a → Vd.4H

float32x2_t vreinterpret_f32_f16
NOP Vd.2S ARMv7, ARMv8
(float16x4_t a) a → Vd.4H

uint8x8_t vreinterpret_u8_f16
NOP Vd.8B ARMv7, ARMv8
(float16x4_t a) a → Vd.4H

uint16x4_t vreinterpret_u16_f16
NOP Vd.4H ARMv7, ARMv8
(float16x4_t a) a → Vd.4H

uint32x2_t vreinterpret_u32_f16
NOP Vd.2S ARMv7, ARMv8
(float16x4_t a) a → Vd.4H

poly8x8_t vreinterpret_p8_f16
NOP Vd.8B ARMv7, ARMv8
(float16x4_t a) a → Vd.4H

poly16x4_t vreinterpret_p16_f16
NOP Vd.4H ARMv7, ARMv8
(float16x4_t a) a → Vd.4H

uint64x1_t vreinterpret_u64_f16
NOP Vd.1D ARMv7, ARMv8
(float16x4_t a) a → Vd.4H

int64x1_t vreinterpret_s64_f16
NOP Vd.1D ARMv7, ARMv8
(float16x4_t a) a → Vd.4H

float64x1_t vreinterpret_f64_f16
NOP Vd.1D ARMv8(AArch64)
(float16x4_t a) a → Vd.4H

poly64x1_t vreinterpret_p64_f16
NOP Vd.1D ARMv8
(float16x4_t a) a → Vd.4H

int16x8_t vreinterpretq_s16_s8
NOP Vd.8H ARMv7, ARMv8
(int8x16_t a) a → Vd.16B

int32x4_t vreinterpretq_s32_s8
NOP Vd.4S ARMv7, ARMv8
(int8x16_t a) a → Vd.16B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 331 of 348
Non-Confidential
float32x4_t vreinterpretq_f32_s8
NOP Vd.4S ARMv7, ARMv8
(int8x16_t a) a → Vd.16B

uint8x16_t vreinterpretq_u8_s8
NOP Vd.16B ARMv7, ARMv8
(int8x16_t a) a → Vd.16B

uint16x8_t vreinterpretq_u16_s8
NOP Vd.8H ARMv7, ARMv8
(int8x16_t a) a → Vd.16B

uint32x4_t vreinterpretq_u32_s8
NOP Vd.4S ARMv7, ARMv8
(int8x16_t a) a → Vd.16B

poly8x16_t vreinterpretq_p8_s8
NOP Vd.16B ARMv7, ARMv8
(int8x16_t a) a → Vd.16B

poly16x8_t vreinterpretq_p16_s8
NOP Vd.8H ARMv7, ARMv8
(int8x16_t a) a → Vd.16B

uint64x2_t vreinterpretq_u64_s8
NOP Vd.2D ARMv7, ARMv8
(int8x16_t a) a → Vd.16B

int64x2_t vreinterpretq_s64_s8
NOP Vd.2D ARMv7, ARMv8
(int8x16_t a) a → Vd.16B

float64x2_t vreinterpretq_f64_s8
NOP Vd.2D ARMv8(AArch64)
(int8x16_t a) a → Vd.16B

poly64x2_t vreinterpretq_p64_s8
NOP Vd.2D ARMv8
(int8x16_t a) a → Vd.16B

poly128_t vreinterpretq_p128_s8
NOP Vd.1Q ARMv8
(int8x16_t a) a → Vd.16B

float16x8_t vreinterpretq_f16_s8
NOP Vd.8H ARMv7, ARMv8
(int8x16_t a) a → Vd.16B

int8x16_t vreinterpretq_s8_s16
NOP Vd.16B ARMv7, ARMv8
(int16x8_t a) a → Vd.8H

int32x4_t vreinterpretq_s32_s16
NOP Vd.4S ARMv7, ARMv8
(int16x8_t a) a → Vd.8H

float32x4_t vreinterpretq_f32_s16
NOP Vd.4S ARMv7, ARMv8
(int16x8_t a) a → Vd.8H

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 332 of 348
Non-Confidential
uint8x16_t vreinterpretq_u8_s16
NOP Vd.16B ARMv7, ARMv8
(int16x8_t a) a → Vd.8H

uint16x8_t vreinterpretq_u16_s16
NOP Vd.8H ARMv7, ARMv8
(int16x8_t a) a → Vd.8H

uint32x4_t vreinterpretq_u32_s16
NOP Vd.4S ARMv7, ARMv8
(int16x8_t a) a → Vd.8H

poly8x16_t vreinterpretq_p8_s16
NOP Vd.16B ARMv7, ARMv8
(int16x8_t a) a → Vd.8H

poly16x8_t vreinterpretq_p16_s16
NOP Vd.8H ARMv7, ARMv8
(int16x8_t a) a → Vd.8H

uint64x2_t vreinterpretq_u64_s16
NOP Vd.2D ARMv7, ARMv8
(int16x8_t a) a → Vd.8H

int64x2_t vreinterpretq_s64_s16
NOP Vd.2D ARMv7, ARMv8
(int16x8_t a) a → Vd.8H

float64x2_t vreinterpretq_f64_s16
NOP Vd.2D ARMv8(AArch64)
(int16x8_t a) a → Vd.8H

poly64x2_t vreinterpretq_p64_s16
NOP Vd.2D ARMv8
(int16x8_t a) a → Vd.8H

poly128_t vreinterpretq_p128_s16
NOP Vd.1Q ARMv8
(int16x8_t a) a → Vd.8H

float16x8_t vreinterpretq_f16_s16
NOP Vd.8H ARMv7, ARMv8
(int16x8_t a) a → Vd.8H

int8x16_t vreinterpretq_s8_s32
NOP Vd.16B ARMv7, ARMv8
(int32x4_t a) a → Vd.4S

int16x8_t vreinterpretq_s16_s32
NOP Vd.8H ARMv7, ARMv8
(int32x4_t a) a → Vd.4S

float32x4_t vreinterpretq_f32_s32
NOP Vd.4S ARMv7, ARMv8
(int32x4_t a) a → Vd.4S

uint8x16_t vreinterpretq_u8_s32
NOP Vd.16B ARMv7, ARMv8
(int32x4_t a) a → Vd.4S

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 333 of 348
Non-Confidential
uint16x8_t vreinterpretq_u16_s32
NOP Vd.8H ARMv7, ARMv8
(int32x4_t a) a → Vd.4S

uint32x4_t vreinterpretq_u32_s32
NOP Vd.4S ARMv7, ARMv8
(int32x4_t a) a → Vd.4S

poly8x16_t vreinterpretq_p8_s32
NOP Vd.16B ARMv7, ARMv8
(int32x4_t a) a → Vd.4S

poly16x8_t vreinterpretq_p16_s32
NOP Vd.8H ARMv7, ARMv8
(int32x4_t a) a → Vd.4S

uint64x2_t vreinterpretq_u64_s32
NOP Vd.2D ARMv7, ARMv8
(int32x4_t a) a → Vd.4S

int64x2_t vreinterpretq_s64_s32
NOP Vd.2D ARMv7, ARMv8
(int32x4_t a) a → Vd.4S

float64x2_t vreinterpretq_f64_s32
NOP Vd.2D ARMv8(AArch64)
(int32x4_t a) a → Vd.4S

poly64x2_t vreinterpretq_p64_s32
NOP Vd.2D ARMv8
(int32x4_t a) a → Vd.4S

poly128_t vreinterpretq_p128_s32
NOP Vd.1Q ARMv8
(int32x4_t a) a → Vd.4S

float16x8_t vreinterpretq_f16_s32
NOP Vd.8H ARMv7, ARMv8
(int32x4_t a) a → Vd.4S

int8x16_t vreinterpretq_s8_f32
NOP Vd.16B ARMv7, ARMv8
(float32x4_t a) a → Vd.4S

int16x8_t vreinterpretq_s16_f32
NOP Vd.8H ARMv7, ARMv8
(float32x4_t a) a → Vd.4S

int32x4_t vreinterpretq_s32_f32
NOP Vd.4S ARMv7, ARMv8
(float32x4_t a) a → Vd.4S

uint8x16_t vreinterpretq_u8_f32
NOP Vd.16B ARMv7, ARMv8
(float32x4_t a) a → Vd.4S

uint16x8_t vreinterpretq_u16_f32
NOP Vd.8H ARMv7, ARMv8
(float32x4_t a) a → Vd.4S

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 334 of 348
Non-Confidential
uint32x4_t vreinterpretq_u32_f32
NOP Vd.4S ARMv7, ARMv8
(float32x4_t a) a → Vd.4S

poly8x16_t vreinterpretq_p8_f32
NOP Vd.16B ARMv7, ARMv8
(float32x4_t a) a → Vd.4S

poly16x8_t vreinterpretq_p16_f32
NOP Vd.8H ARMv7, ARMv8
(float32x4_t a) a → Vd.4S

uint64x2_t vreinterpretq_u64_f32
NOP Vd.2D ARMv7, ARMv8
(float32x4_t a) a → Vd.4S

int64x2_t vreinterpretq_s64_f32
NOP Vd.2D ARMv7, ARMv8
(float32x4_t a) a → Vd.4S

float64x2_t vreinterpretq_f64_f32
NOP Vd.2D ARMv8(AArch64)
(float32x4_t a) a → Vd.4S

poly64x2_t vreinterpretq_p64_f32
NOP Vd.2D ARMv8
(float32x4_t a) a → Vd.4S

poly128_t vreinterpretq_p128_f32
NOP Vd.1Q ARMv8
(float32x4_t a) a → Vd.4S

poly64x2_t vreinterpretq_p64_f64
NOP Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vd.2D

poly128_t vreinterpretq_p128_f64
NOP Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vd.1Q

float16x8_t vreinterpretq_f16_f32
NOP Vd.8H ARMv7, ARMv8
(float32x4_t a) a → Vd.4S

int8x16_t vreinterpretq_s8_u8
NOP Vd.16B ARMv7, ARMv8
(uint8x16_t a) a → Vd.16B

int16x8_t vreinterpretq_s16_u8
NOP Vd.8H ARMv7, ARMv8
(uint8x16_t a) a → Vd.16B

int32x4_t vreinterpretq_s32_u8
NOP Vd.4S ARMv7, ARMv8
(uint8x16_t a) a → Vd.16B

float32x4_t vreinterpretq_f32_u8
NOP Vd.4S ARMv7, ARMv8
(uint8x16_t a) a → Vd.16B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 335 of 348
Non-Confidential
uint16x8_t vreinterpretq_u16_u8
NOP Vd.8H ARMv7, ARMv8
(uint8x16_t a) a → Vd.16B

uint32x4_t vreinterpretq_u32_u8
NOP Vd.4S ARMv7, ARMv8
(uint8x16_t a) a → Vd.16B

poly8x16_t vreinterpretq_p8_u8
NOP Vd.16B ARMv7, ARMv8
(uint8x16_t a) a → Vd.16B

poly16x8_t vreinterpretq_p16_u8
NOP Vd.8H ARMv7, ARMv8
(uint8x16_t a) a → Vd.16B

uint64x2_t vreinterpretq_u64_u8
NOP Vd.2D ARMv7, ARMv8
(uint8x16_t a) a → Vd.16B

int64x2_t vreinterpretq_s64_u8
NOP Vd.2D ARMv7, ARMv8
(uint8x16_t a) a → Vd.16B

float64x2_t vreinterpretq_f64_u8
NOP Vd.2D ARMv8(AArch64)
(uint8x16_t a) a → Vd.16B

poly64x2_t vreinterpretq_p64_u8
NOP Vd.2D ARMv8
(uint8x16_t a) a → Vd.16B

poly128_t vreinterpretq_p128_u8
NOP Vd.1Q ARMv8
(uint8x16_t a) a → Vd.16B

float16x8_t vreinterpretq_f16_u8
NOP Vd.8H ARMv7, ARMv8
(uint8x16_t a) a → Vd.16B

int8x16_t vreinterpretq_s8_u16
NOP Vd.16B ARMv7, ARMv8
(uint16x8_t a) a → Vd.8H

int16x8_t vreinterpretq_s16_u16
NOP Vd.8H ARMv7, ARMv8
(uint16x8_t a) a → Vd.8H

int32x4_t vreinterpretq_s32_u16
NOP Vd.4S ARMv7, ARMv8
(uint16x8_t a) a → Vd.8H

float32x4_t vreinterpretq_f32_u16
NOP Vd.4S ARMv7, ARMv8
(uint16x8_t a) a → Vd.8H

uint8x16_t vreinterpretq_u8_u16
NOP Vd.16B ARMv7, ARMv8
(uint16x8_t a) a → Vd.8H

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Non-Confidential
uint32x4_t vreinterpretq_u32_u16
NOP Vd.4S ARMv7, ARMv8
(uint16x8_t a) a → Vd.8H

poly8x16_t vreinterpretq_p8_u16
NOP Vd.16B ARMv7, ARMv8
(uint16x8_t a) a → Vd.8H

poly16x8_t vreinterpretq_p16_u16
NOP Vd.8H ARMv7, ARMv8
(uint16x8_t a) a → Vd.8H

uint64x2_t vreinterpretq_u64_u16
NOP Vd.2D ARMv7, ARMv8
(uint16x8_t a) a → Vd.8H

int64x2_t vreinterpretq_s64_u16
NOP Vd.2D ARMv7, ARMv8
(uint16x8_t a) a → Vd.8H

float64x2_t vreinterpretq_f64_u16
NOP Vd.2D ARMv8(AArch64)
(uint16x8_t a) a → Vd.8H

poly64x2_t vreinterpretq_p64_u16
NOP Vd.2D ARMv8
(uint16x8_t a) a → Vd.8H

poly128_t vreinterpretq_p128_u16
NOP Vd.1Q ARMv8
(uint16x8_t a) a → Vd.8H

float16x8_t vreinterpretq_f16_u16
NOP Vd.8H ARMv7, ARMv8
(uint16x8_t a) a → Vd.8H

int8x16_t vreinterpretq_s8_u32
NOP Vd.16B ARMv7, ARMv8
(uint32x4_t a) a → Vd.4S

int16x8_t vreinterpretq_s16_u32
NOP Vd.8H ARMv7, ARMv8
(uint32x4_t a) a → Vd.4S

int32x4_t vreinterpretq_s32_u32
NOP Vd.4S ARMv7, ARMv8
(uint32x4_t a) a → Vd.4S

float32x4_t vreinterpretq_f32_u32
NOP Vd.4S ARMv7, ARMv8
(uint32x4_t a) a → Vd.4S

uint8x16_t vreinterpretq_u8_u32
NOP Vd.16B ARMv7, ARMv8
(uint32x4_t a) a → Vd.4S

uint16x8_t vreinterpretq_u16_u32
NOP Vd.8H ARMv7, ARMv8
(uint32x4_t a) a → Vd.4S

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 337 of 348
Non-Confidential
poly8x16_t vreinterpretq_p8_u32
NOP Vd.16B ARMv7, ARMv8
(uint32x4_t a) a → Vd.4S

poly16x8_t vreinterpretq_p16_u32
NOP Vd.8H ARMv7, ARMv8
(uint32x4_t a) a → Vd.4S

uint64x2_t vreinterpretq_u64_u32
NOP Vd.2D ARMv7, ARMv8
(uint32x4_t a) a → Vd.4S

int64x2_t vreinterpretq_s64_u32
NOP Vd.2D ARMv7, ARMv8
(uint32x4_t a) a → Vd.4S

float64x2_t vreinterpretq_f64_u32
NOP Vd.2D ARMv8(AArch64)
(uint32x4_t a) a → Vd.4S

poly64x2_t vreinterpretq_p64_u32
NOP Vd.2D ARMv8
(uint32x4_t a) a → Vd.4S

poly128_t vreinterpretq_p128_u32
NOP Vd.1Q ARMv8
(uint32x4_t a) a → Vd.4S

float16x8_t vreinterpretq_f16_u32
NOP Vd.8H ARMv7, ARMv8
(uint32x4_t a) a → Vd.4S

int8x16_t vreinterpretq_s8_p8
NOP Vd.16B ARMv7, ARMv8
(poly8x16_t a) a → Vd.16B

int16x8_t vreinterpretq_s16_p8
NOP Vd.8H ARMv7, ARMv8
(poly8x16_t a) a → Vd.16B

int32x4_t vreinterpretq_s32_p8
NOP Vd.4S ARMv7, ARMv8
(poly8x16_t a) a → Vd.16B

float32x4_t vreinterpretq_f32_p8
NOP Vd.4S ARMv7, ARMv8
(poly8x16_t a) a → Vd.16B

uint8x16_t vreinterpretq_u8_p8
NOP Vd.16B ARMv7, ARMv8
(poly8x16_t a) a → Vd.16B

uint16x8_t vreinterpretq_u16_p8
NOP Vd.8H ARMv7, ARMv8
(poly8x16_t a) a → Vd.16B

uint32x4_t vreinterpretq_u32_p8
NOP Vd.4S ARMv7, ARMv8
(poly8x16_t a) a → Vd.16B

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 338 of 348
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poly16x8_t vreinterpretq_p16_p8
NOP Vd.8H ARMv7, ARMv8
(poly8x16_t a) a → Vd.16B

uint64x2_t vreinterpretq_u64_p8
NOP Vd.2D ARMv7, ARMv8
(poly8x16_t a) a → Vd.16B

int64x2_t vreinterpretq_s64_p8
NOP Vd.2D ARMv7, ARMv8
(poly8x16_t a) a → Vd.16B

float64x2_t vreinterpretq_f64_p8
NOP Vd.2D ARMv8(AArch64)
(poly8x16_t a) a → Vd.16B

poly64x2_t vreinterpretq_p64_p8
NOP Vd.2D ARMv8
(poly8x16_t a) a → Vd.16B

poly128_t vreinterpretq_p128_p8
NOP Vd.1Q ARMv8
(poly8x16_t a) a → Vd.16B

float16x8_t vreinterpretq_f16_p8
NOP Vd.8H ARMv7, ARMv8
(poly8x16_t a) a → Vd.16B

int8x16_t vreinterpretq_s8_p16
NOP Vd.16B ARMv7, ARMv8
(poly16x8_t a) a → Vd.8H

int16x8_t vreinterpretq_s16_p16
NOP Vd.8H ARMv7, ARMv8
(poly16x8_t a) a → Vd.8H

int32x4_t vreinterpretq_s32_p16
NOP Vd.4S ARMv7, ARMv8
(poly16x8_t a) a → Vd.8H

float32x4_t vreinterpretq_f32_p16
NOP Vd.4S ARMv7, ARMv8
(poly16x8_t a) a → Vd.8H

uint8x16_t vreinterpretq_u8_p16
NOP Vd.16B ARMv7, ARMv8
(poly16x8_t a) a → Vd.8H

uint16x8_t vreinterpretq_u16_p16
NOP Vd.8H ARMv7, ARMv8
(poly16x8_t a) a → Vd.8H

uint32x4_t vreinterpretq_u32_p16
NOP Vd.4S ARMv7, ARMv8
(poly16x8_t a) a → Vd.8H

poly8x16_t vreinterpretq_p8_p16
NOP Vd.16B ARMv7, ARMv8
(poly16x8_t a) a → Vd.8H

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 339 of 348
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uint64x2_t vreinterpretq_u64_p16
NOP Vd.2D ARMv7, ARMv8
(poly16x8_t a) a → Vd.8H

int64x2_t vreinterpretq_s64_p16
NOP Vd.2D ARMv7, ARMv8
(poly16x8_t a) a → Vd.8H

float64x2_t vreinterpretq_f64_p16
NOP Vd.2D ARMv8(AArch64)
(poly16x8_t a) a → Vd.8H

poly64x2_t vreinterpretq_p64_p16
NOP Vd.2D ARMv8
(poly16x8_t a) a → Vd.8H

poly128_t vreinterpretq_p128_p16
NOP Vd.1Q ARMv8
(poly16x8_t a) a → Vd.8H

float16x8_t vreinterpretq_f16_p16
NOP Vd.8H ARMv7, ARMv8
(poly16x8_t a) a → Vd.8H

int8x16_t vreinterpretq_s8_u64
NOP Vd.16B ARMv7, ARMv8
(uint64x2_t a) a → Vd.2D

int16x8_t vreinterpretq_s16_u64
NOP Vd.8H ARMv7, ARMv8
(uint64x2_t a) a → Vd.2D

int32x4_t vreinterpretq_s32_u64
NOP Vd.4S ARMv7, ARMv8
(uint64x2_t a) a → Vd.2D

float32x4_t vreinterpretq_f32_u64
NOP Vd.4S ARMv7, ARMv8
(uint64x2_t a) a → Vd.2D

uint8x16_t vreinterpretq_u8_u64
NOP Vd.16B ARMv7, ARMv8
(uint64x2_t a) a → Vd.2D

uint16x8_t vreinterpretq_u16_u64
NOP Vd.8H ARMv7, ARMv8
(uint64x2_t a) a → Vd.2D

uint32x4_t vreinterpretq_u32_u64
NOP Vd.4S ARMv7, ARMv8
(uint64x2_t a) a → Vd.2D

poly8x16_t vreinterpretq_p8_u64
NOP Vd.16B ARMv7, ARMv8
(uint64x2_t a) a → Vd.2D

poly16x8_t vreinterpretq_p16_u64
NOP Vd.8H ARMv7, ARMv8
(uint64x2_t a) a → Vd.2D

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 340 of 348
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int64x2_t vreinterpretq_s64_u64
NOP Vd.2D ARMv7, ARMv8
(uint64x2_t a) a → Vd.2D

float64x2_t vreinterpretq_f64_u64
NOP Vd.2D ARMv7, ARMv8
(uint64x2_t a) a → Vd.2D

float64x2_t vreinterpretq_f64_s64
NOP Vd.2D ARMv8(AArch64)
(int64x2_t a) a → Vd.2D

poly64x2_t vreinterpretq_p64_s64
NOP Vd.2D ARMv8
(int64x2_t a) a → Vd.2D

poly128_t vreinterpretq_p128_s64
NOP Vd.2D ARMv8
(int64x2_t a) a → Vd.1Q

poly64x2_t vreinterpretq_p64_u64
NOP Vd.2D ARMv8
(uint64x2_t a) a → Vd.2D

poly128_t vreinterpretq_p128_u64
NOP Vd.2D ARMv8
(uint64x2_t a) a → Vd.1Q

float16x8_t vreinterpretq_f16_u64
NOP Vd.8H ARMv7, ARMv8
(uint64x2_t a) a → Vd.2D

int8x16_t vreinterpretq_s8_s64
NOP Vd.16B ARMv7, ARMv8
(int64x2_t a) a → Vd.2D

int16x8_t vreinterpretq_s16_s64
NOP Vd.8H ARMv7, ARMv8
(int64x2_t a) a → Vd.2D

int32x4_t vreinterpretq_s32_s64
NOP Vd.4S ARMv7, ARMv8
(int64x2_t a) a → Vd.2D

float32x4_t vreinterpretq_f32_s64
NOP Vd.4S ARMv7, ARMv8
(int64x2_t a) a → Vd.2D

uint8x16_t vreinterpretq_u8_s64
NOP Vd.16B ARMv7, ARMv8
(int64x2_t a) a → Vd.2D

uint16x8_t vreinterpretq_u16_s64
NOP Vd.8H ARMv7, ARMv8
(int64x2_t a) a → Vd.2D

uint32x4_t vreinterpretq_u32_s64
NOP Vd.4S ARMv7, ARMv8
(int64x2_t a) a → Vd.2D

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 341 of 348
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poly8x16_t vreinterpretq_p8_s64
NOP Vd.16B ARMv7, ARMv8
(int64x2_t a) a → Vd.2D

poly16x8_t vreinterpretq_p16_s64
NOP Vd.8H ARMv7, ARMv8
(int64x2_t a) a → Vd.2D

uint64x2_t vreinterpretq_u64_s64
NOP Vd.2D ARMv7, ARMv8
(int64x2_t a) a → Vd.2D

uint64x2_t vreinterpretq_u64_p64
NOP Vd.2D ARMv8
(poly64x2_t a) a → Vd.2D

float16x8_t vreinterpretq_f16_s64
NOP Vd.8H ARMv7, ARMv8
(int64x2_t a) a → Vd.2D

int8x16_t vreinterpretq_s8_f16
NOP Vd.16B ARMv7, ARMv8
(float16x8_t a) a → Vd.8H

int16x8_t vreinterpretq_s16_f16
NOP Vd.8H ARMv7, ARMv8
(float16x8_t a) a → Vd.8H

int32x4_t vreinterpretq_s32_f16
NOP Vd.4S ARMv7, ARMv8
(float16x8_t a) a → Vd.8H

float32x4_t vreinterpretq_f32_f16
NOP Vd.4S ARMv7, ARMv8
(float16x8_t a) a → Vd.8H

uint8x16_t vreinterpretq_u8_f16
NOP Vd.16B ARMv7, ARMv8
(float16x8_t a) a → Vd.8H

uint16x8_t vreinterpretq_u16_f16
NOP Vd.8H ARMv7, ARMv8
(float16x8_t a) a → Vd.8H

uint32x4_t vreinterpretq_u32_f16
NOP Vd.4S ARMv7, ARMv8
(float16x8_t a) a → Vd.8H

poly8x16_t vreinterpretq_p8_f16
NOP Vd.16B ARMv7, ARMv8
(float16x8_t a) a → Vd.8H

poly16x8_t vreinterpretq_p16_f16
NOP Vd.8H ARMv7, ARMv8
(float16x8_t a) a → Vd.8H

uint64x2_t vreinterpretq_u64_f16
NOP Vd.2D ARMv7, ARMv8
(float16x8_t a) a → Vd.8H

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 342 of 348
Non-Confidential
int64x2_t vreinterpretq_s64_f16
NOP Vd.2D ARMv7, ARMv8
(float16x8_t a) a → Vd.8H

float64x2_t vreinterpretq_f64_f16
NOP Vd.2D ARMv8(AArch64)
(float16x8_t a) a → Vd.8H

poly64x2_t vreinterpretq_p64_f16
NOP Vd.2D ARMv8
(float16x8_t a) a → Vd.8H

poly128_t vreinterpretq_p128_f16
NOP Vd.1Q ARMv8
(float16x8_t a) a → Vd.8H

int8x8_t vreinterpret_s8_f64
NOP Vd.8B ARMv8(AArch64)
(float64x1_t a) a → Vd.1D

int16x4_t vreinterpret_s16_f64
NOP Vd.4H ARMv8(AArch64)
(float64x1_t a) a → Vd.1D

int32x2_t vreinterpret_s32_f64
NOP Vd.2S ARMv8(AArch64)
(float64x1_t a) a → Vd.1D

uint8x8_t vreinterpret_u8_f64
NOP Vd.8B ARMv8(AArch64)
(float64x1_t a) a → Vd.1D

uint16x4_t vreinterpret_u16_f64
NOP Vd.4H ARMv8(AArch64)
(float64x1_t a) a → Vd.1D

uint32x2_t vreinterpret_u32_f64
NOP Vd.2S ARMv8(AArch64)
(float64x1_t a) a → Vd.1D

poly8x8_t vreinterpret_p8_f64
NOP Vd.8B ARMv8(AArch64)
(float64x1_t a) a → Vd.1D

poly16x4_t vreinterpret_p16_f64
NOP Vd.4H ARMv8(AArch64)
(float64x1_t a) a → Vd.1D

uint64x1_t vreinterpret_u64_f64
NOP Vd.1D ARMv8(AArch64)
(float64x1_t a) a → Vd.1D

int64x1_t vreinterpret_s64_f64
NOP Vd.1D ARMv8(AArch64)
(float64x1_t a) a → Vd.1D

float16x4_t vreinterpret_f16_f64
NOP Vd.4H ARMv8(AArch64)
(float64x1_t a) a → Vd.1D

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 343 of 348
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float32x2_t vreinterpret_f32_f64
NOP Vd.2S ARMv8(AArch64)
(float64x1_t a) a → Vd.1D

int8x16_t vreinterpretq_s8_f64
NOP Vd.16B ARMv8(AArch64)
(float64x2_t a) a → Vd.2D

int16x8_t vreinterpretq_s16_f64
NOP Vd.8H ARMv8(AArch64)
(float64x2_t a) a → Vd.2D

int32x4_t vreinterpretq_s32_f64
NOP Vd.4S ARMv8(AArch64)
(float64x2_t a) a → Vd.2D

uint8x16_t vreinterpretq_u8_f64
NOP Vd.16B ARMv8(AArch64)
(float64x2_t a) a → Vd.2D

uint16x8_t vreinterpretq_u16_f64
NOP Vd.8H ARMv8(AArch64)
(float64x2_t a) a → Vd.2D

uint32x4_t vreinterpretq_u32_f64
NOP Vd.4S ARMv8(AArch64)
(float64x2_t a) a → Vd.2D

poly8x16_t vreinterpretq_p8_f64
NOP Vd.16B ARMv8(AArch64)
(float64x2_t a) a → Vd.2D

poly16x8_t vreinterpretq_p16_f64
NOP Vd.8H ARMv8(AArch64)
(float64x2_t a) a → Vd.2D

uint64x2_t vreinterpretq_u64_f64
NOP Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vd.2D

int64x2_t vreinterpretq_s64_f64
NOP Vd.2D ARMv8(AArch64)
(float64x2_t a) a → Vd.2D

float16x8_t vreinterpretq_f16_f64
NOP Vd.8H ARMv8(AArch64)
(float64x2_t a) a → Vd.2D

float32x4_t vreinterpretq_f32_f64
NOP Vd.4S ARMv8(AArch64)
(float64x2_t a) a → Vd.2D

int8x8_t vreinterpret_s8_p64
NOP Vd.8B ARMv8
(poly64x1_t a) a → Vd.1D

int16x4_t vreinterpret_s16_p64
NOP Vd.4H ARMv8
(poly64x1_t a) a → Vd.1D

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 344 of 348
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int32x2_t vreinterpret_s32_p64
NOP Vd.2S ARMv8
(poly64x1_t a) a → Vd.1D

uint8x8_t vreinterpret_u8_p64
NOP Vd.8B ARMv8
(poly64x1_t a) a → Vd.1D

uint16x4_t vreinterpret_u16_p64
NOP Vd.4H ARMv8
(poly64x1_t a) a → Vd.1D

uint32x2_t vreinterpret_u32_p64
NOP Vd.2S ARMv8
(poly64x1_t a) a → Vd.1D

poly8x8_t vreinterpret_p8_p64
NOP Vd.8B ARMv8
(poly64x1_t a) a → Vd.1D

poly16x4_t vreinterpret_p16_p64
NOP Vd.4H ARMv8
(poly64x1_t a) a → Vd.1D

uint64x1_t vreinterpret_u64_p64
NOP Vd.1D ARMv8
(poly64x1_t a) a → Vd.1D

int64x1_t vreinterpret_s64_p64
NOP Vd.1D ARMv8
(poly64x1_t a) a → Vd.1D

float64x1_t vreinterpret_f64_p64
NOP Vd.1D ARMv8(AArch64)
(poly64x1_t a) a → Vd.1D

float16x4_t vreinterpret_f16_p64
NOP Vd.4H ARMv8
(poly64x1_t a) a → Vd.1D

int8x16_t vreinterpretq_s8_p64
NOP Vd.16B ARMv8
(poly64x2_t a) a → Vd.2D

int16x8_t vreinterpretq_s16_p64
NOP Vd.8H ARMv8
(poly64x2_t a) a → Vd.2D

int32x4_t vreinterpretq_s32_p64
NOP Vd.4S ARMv8
(poly64x2_t a) a → Vd.2D

uint8x16_t vreinterpretq_u8_p64
NOP Vd.16B ARMv8
(poly64x2_t a) a → Vd.2D

uint16x8_t vreinterpretq_u16_p64
NOP Vd.8H ARMv8
(poly64x2_t a) a → Vd.2D

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 345 of 348
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uint32x4_t vreinterpretq_u32_p64
NOP Vd.4S ARMv8
(poly64x2_t a) a → Vd.2D

poly8x16_t vreinterpretq_p8_p64
NOP Vd.16B ARMv8
(poly64x2_t a) a → Vd.2D

poly16x8_t vreinterpretq_p16_p64
NOP Vd.8H ARMv8
(poly64x2_t a) a → Vd.2D

uint64x2_t vreinterpretq_u64_p64
NOP Vd.2D ARMv8
(poly64x2_t a) a → Vd.2D

int64x2_t vreinterpretq_s64_p64
NOP Vd.2D ARMv8
(poly64x2_t a) a → Vd.2D

float64x2_t vreinterpretq_f64_p64
NOP Vd.2D ARMv8(AArch64)
(poly64x2_t a) a → Vd.2D

float16x8_t vreinterpretq_f16_p64
NOP Vd.8H ARMv8
(poly64x2_t a) a → Vd.2D

int8x16_t vreinterpretq_s8_p128
NOP Vd.16B ARMv8
(poly128_t a) a → Vd.1Q

int16x8_t vreinterpretq_s16_p128
NOP Vd.8H ARMv8
(poly128_t a) a → Vd.1Q

int32x4_t vreinterpretq_s32_p128
NOP Vd.4S ARMv8
(poly128_t a) a → Vd.1Q

uint8x16_t vreinterpretq_u8_p128
NOP Vd.16B ARMv8
(poly128_t a) a → Vd.1Q

uint16x8_t vreinterpretq_u16_p128
NOP Vd.8H ARMv8
(poly128_t a) a → Vd.1Q

uint32x4_t vreinterpretq_u32_p128
NOP Vd.4S ARMv8
(poly128_t a) a → Vd.1Q

poly8x16_t vreinterpretq_p8_p128
NOP Vd.16B ARMv8
(poly128_t a) a → Vd.1Q

poly16x8_t vreinterpretq_p16_p128
NOP Vd.8H ARMv8
(poly128_t a) a → Vd.1Q

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uint64x2_t vreinterpretq_u64_p128
NOP Vd.2D ARMv8
(poly128_t a) a → Vd.1Q

int64x2_t vreinterpretq_s64_p128
NOP Vd.2D ARMv8
(poly128_t a) a → Vd.1Q

float64x2_t vreinterpretq_f64_p128
NOP Vd.2D ARMv8(AArch64)
(poly128_t a) a → Vd.1Q

float16x8_t vreinterpretq_f16_p128
NOP Vd.8H ARMv8
(poly128_t a) a → Vd.1Q

poly128_t vldrq_p128
LDR Qd,[Xn] Qd ARMv8
(poly128_t const * ptr) ptr → Xn

void vstrq_p128
(poly128_t * ptr, ptr → Xn STR Qt,[Xn] ARMv8
poly128_t val) val → Qt

uint8x16_t vaeseq_u8
(uint8x16_t data, data → Vd.16B AESE Vd.16B,Vn.16B Vd.16B ARMv8
uint8x16_t key) key → Vn.16B

uint8x16_t vaesdq_u8
(uint8x16_t data, data → Vd.16B AESD Vd.16B,Vn.16B Vd.16B ARMv8
uint8x16_t key) key → Vn.16B

uint8x16_t vaesmcq_u8
AESMC Vd.16B,Vn.16B Vd.16B ARMv8
(uint8x16_t data) data → Vn.16B

uint8x16_t vaesimcq_u8
AESIMC Vd.16B,Vn.16B Vd.16B ARMv8
(uint8x16_t data) data → Vn.16B

uint32x4_t vsha1cq_u32
(uint32x4_t hash_abcd, hash_abcd → Qd
SHA1C Qd,Sn,Vm.4S Qd ARMv8
uint32_t hash_e, hash_e → Sn
uint32x4_t wk) wk → Vm.4S

uint32x4_t vsha1pq_u32
(uint32x4_t hash_abcd, hash_abcd → Qd
SHA1P Qd,Sn,Vm.4S Qd ARMv8
uint32_t hash_e, hash_e → Sn
uint32x4_t wk) wk → Vm.4S

uint32x4_t vsha1mq_u32
(uint32x4_t hash_abcd, hash_abcd → Qd
SHA1M Qd,Sn,Vm.4S Qd ARMv8
uint32_t hash_e, hash_e → Sn
uint32x4_t wk) wk → Vm.4S

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uint32_t vsha1h_u32
SHA1H Sd,Sn Sd ARMv8
(uint32_t hash_e) hash_e → Sn

uint32x4_t vsha1su0q_u32
(uint32x4_t w0_3, w0_3 → Vd.4S
SHA1SU0 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8
uint32x4_t w4_7, w4_7 → Vn.4S
uint32x4_t w8_11) w8_11 → Vm.4S

uint32x4_t vsha1su1q_u32
(uint32x4_t tw0_3, tw0_3 → Vd.4S SHA1SU1 Vd.4S,Vn.4S Vd.4S ARMv8
uint32x4_t w12_15) w12_15 → Vn.4S

uint32x4_t vsha256hq_u32
(uint32x4_t hash_abcd, hash_abcd → Qd
SHA256H Qd,Qn,Vm.4S Qd ARMv8
uint32x4_t hash_efgh, hash_efgh → Qn
uint32x4_t wk) wk → Vm.4S

uint32x4_t vsha256h2q_u32
(uint32x4_t hash_efgh, hash_efgh → Qd
SHA256H2 Qd,Qn,Vm.4S Qd ARMv8
uint32x4_t hash_abcd, hash_abcd → Qn
uint32x4_t wk) wk → Vm.4S

uint32x4_t vsha256su0q_u32
(uint32x4_t w0_3, w0_3 → Vd.4S SHA256SU0 Vd.4S,Vn.4S Vd.4S ARMv8
uint32x4_t w4_7) w4_7 → Vn.4S

uint32x4_t vsha256su1q_u32
(uint32x4_t tw0_3, tw0_3 → Vd.4S
SHA256SU1 Vd.4S,Vn.4S,Vm.4S Vd.4S ARMv8
uint32x4_t w8_11, w8_11 → Vn.4S
uint32x4_t w12_15) w12_15 → Vm.4S

poly128_t vmull_p64
(poly64_t a, a → Vn.1D PMULL Vd.1Q,Vn.1D,Vm.1D Vd.1Q ARMv8
poly64_t b) b → Vm.1D

poly128_t vmull_high_p64
(poly64x2_t a, a → Vn.2D PMULL2 Vd.1Q,Vn.2D,Vm.2D Vd.1Q ARMv8
poly64x2_t b) b → Vm.2D

IHI 0073B Copyright © 2011-2016 ARM Limited. All rights reserved. Page 348 of 348
Non-Confidential