RM0377

Reference manual
Ultra-low-power STM32L0x1 advanced Arm®-based
32-bit MCUs

Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32L0x1 microcontroller memory and peripherals.
The STM32L0x1 is a line of microcontrollers with different memory sizes, packages and
peripherals.
For ordering information, mechanical and electrical device characteristics please refer to the
corresponding datasheets.
For information on the Arm® Cortex®-M0+ core, refer to the Cortex®-M0+ Technical
Reference Manual.
The STM32L0x1 microcontrollers include state-of-the-art patented technology.

Related documents
• Cortex®-M0+ Technical Reference Manual, available from www.arm.com.
• STM32L0 Series Cortex®-M0+ programming manual (PM0223).
• STM32L0x1 datasheets.
• STM32L0x1 erratasheet.

February 2022 RM0377 Rev 10 1/905

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Contents RM0377

Contents

1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
1.1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
1.3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1.4 Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
1.5 Product category definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2 System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.1.1 S0: Cortex®-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.1.2 S1: DMA-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.1.3 BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
AHB/APB bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

2.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.2.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 52
2.3 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.4 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
BOOT0/GPIO pin sharing (category 1 devices only) . . . . . . . . . . . . . . . . . . . . . .57
Empty check (category 1 devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Bank swapping (category 5 devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Physical remap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Embedded bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

3 Flash program memory and data EEPROM (FLASH) . . . . . . . . . . . . . . 59

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.2 NVM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.3 NVM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.3.1 NVM organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.3.2 Dual-bank boot capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.3.3 Reading the NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Protocol to read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Relation between CPU frequency/Operation mode/NVM read time. . . . . . . . . . .67
Data buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

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3.3.4 Writing/erasing the NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Write/erase protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Unlocking/locking operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Detailed description of NVM write/erase operations. . . . . . . . . . . . . . . . . . . . . . .79
Parallel write half-page Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . .85
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

3.4 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.4.1 RDP (Read Out Protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.4.2 PcROP (Proprietary Code Read-Out Protection) . . . . . . . . . . . . . . . . . . 92
3.4.3 Protections against unwanted write/erase operations . . . . . . . . . . . . . . 94
3.4.4 Write/erase protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.4.5 Protection errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Write protection error flag (WRPERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Read error (RDERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

3.5 NVM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.5.1 Hard fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.6 Memory interface management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.6.1 Operation priority and evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Write/erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Option byte loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
3.6.2 Sequence of operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Read as data while write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Fetch while write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Write while another write operation is ongoing . . . . . . . . . . . . . . . . . . . . . . . . . . .99
3.6.3 Change the number of wait states while reading . . . . . . . . . . . . . . . . . . 99
3.6.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.7 Flash register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Read registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Write to registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
3.7.1 Access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . . . . . 101
3.7.2 Program and erase control register (FLASH_PECR) . . . . . . . . . . . . . 102
3.7.3 Power-down key register (FLASH_PDKEYR) . . . . . . . . . . . . . . . . . . . 106
3.7.4 PECR unlock key register (FLASH_PEKEYR) . . . . . . . . . . . . . . . . . . 106
3.7.5 Program and erase key register (FLASH_PRGKEYR) . . . . . . . . . . . . 106
3.7.6 Option bytes unlock key register (FLASH_OPTKEYR) . . . . . . . . . . . . 107
3.7.7 Status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.7.8 Option bytes register (FLASH_OPTR) . . . . . . . . . . . . . . . . . . . . . . . . . 110

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3.7.9 Write protection register 1 (FLASH_WRPROT1) . . . . . . . . . . . . . . . . . 112

3.7.10 Write protection register 2 (FLASH_WRPROT2) . . . . . . . . . . . . . . . . . 113
3.7.11 Flash register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3.8 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
3.8.1 Option bytes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
3.8.2 Mismatch when loading protection flags . . . . . . . . . . . . . . . . . . . . . . . 116
3.8.3 Reloading Option bytes by software . . . . . . . . . . . . . . . . . . . . . . . . . . 116

4 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 117

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
4.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
4.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
4.3.1 CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.3.2 CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.3.3 CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Polynomial programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

4.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

4.4.1 CRC data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.4.2 CRC independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . 120
4.4.3 CRC control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.4.4 CRC initial value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.4.5 CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.4.6 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

5 Firewall (FW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.2 Firewall main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.3 Firewall functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.3.1 Firewall AMBA bus snoop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
5.3.2 Functional requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Debug consideration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Interrupts management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
5.3.3 Firewall segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Code segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Non-volatile data segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Volatile data segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

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5.3.4 Segment accesses and properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Segment access depending on the Firewall state . . . . . . . . . . . . . . . . . . . . . . .127
Segments properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
5.3.5 Firewall initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.3.6 Firewall states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Opening the Firewall. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Closing the Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130

5.4 Firewall registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

5.4.1 Code segment start address (FW_CSSA) . . . . . . . . . . . . . . . . . . . . . . 131
5.4.2 Code segment length (FW_CSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.4.3 Non-volatile data segment start address (FW_NVDSSA) . . . . . . . . . . 132
5.4.4 Non-volatile data segment length (FW_NVDSL) . . . . . . . . . . . . . . . . . 132
5.4.5 Volatile data segment start address (FW_VDSSA) . . . . . . . . . . . . . . . 133
5.4.6 Volatile data segment length (FW_VDSL) . . . . . . . . . . . . . . . . . . . . . . 133
5.4.7 Configuration register (FW_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.4.8 Firewall register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

6 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

6.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
6.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . 137
On packages with VREF+ pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
On packages without VREF+ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
6.1.2 RTC and RTC backup registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
RTC registers access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
6.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
6.1.4 Dynamic voltage scaling management . . . . . . . . . . . . . . . . . . . . . . . . 138
Range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
Range 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
6.1.5 Dynamic voltage scaling configuration . . . . . . . . . . . . . . . . . . . . . . . . 140
6.1.6 Voltage regulator and clock management when VDD drops
below 1.71 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.1.7 Voltage regulator and clock management when modifying the
VCORE range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.1.8 Voltage range and limitations when VDD ranges from 1.71 V to 2.0 V 141
6.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
6.2.1 Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . 144
6.2.2 Brown out reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
6.2.3 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 145

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6.2.4 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . 146

6.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
6.3.1 Behavior of clocks in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . 148
Sleep and Low-power sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
6.3.2 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6.3.3 Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6.3.4 Low-power run mode (LP run) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Entering Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Exiting Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
6.3.5 Entering low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3.6 Exiting low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3.7 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
I/O states in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Entering Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
Exiting Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
6.3.8 Low-power sleep mode (LP sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
I/O states in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Entering Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
Exiting Low-power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
6.3.9 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
I/O states in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Entering Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
Exiting Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
6.3.10 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
I/O states in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Entering Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Exiting Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
6.3.11 Waking up the device from Stop and Standby modes using the RTC
and comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
RTC auto-wakeup (AWU) from the Stop mode . . . . . . . . . . . . . . . . . . . . . . . . .159
RTC auto-wakeup (AWU) from the Standby mode. . . . . . . . . . . . . . . . . . . . . . .159
Comparator auto-wakeup (AWU) from the Stop mode. . . . . . . . . . . . . . . . . . . .160

6.4 Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

6.4.1 PWR power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . 161
6.4.2 PWR power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . 164
6.4.3 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

7 Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

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7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

7.1.1 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
Low-power management reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
Option byte loader reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
7.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
7.1.3 RTC and backup registers reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
7.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
7.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . . . . . . . .173
7.2.2 HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
7.2.3 MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175
7.2.4 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.2.5 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
7.2.6 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
LSI measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
7.2.7 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
7.2.8 System clock source frequency versus voltage range . . . . . . . . . . . . . 177
7.2.9 HSE clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
7.2.10 LSE Clock Security System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.2.11 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.2.12 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
7.2.13 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
7.2.14 Internal/external clock measurement using TIM21 . . . . . . . . . . . . . . . 179
7.2.15 Clock-independent system clock sources for TIM2/TIM21/TIM22 . . . . 180
7.3 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
7.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
7.3.2 Internal clock sources calibration register (RCC_ICSCR) . . . . . . . . . . 184
7.3.3 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 185
7.3.4 Clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . . . . . 187
7.3.5 Clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . . . . . 189
7.3.6 Clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . . . . . 190
7.3.7 GPIO reset register (RCC_IOPRSTR) . . . . . . . . . . . . . . . . . . . . . . . . . 191
7.3.8 AHB peripheral reset register (RCC_AHBRSTR) . . . . . . . . . . . . . . . . 192

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7.3.9 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 193

7.3.10 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 194
7.3.11 GPIO clock enable register (RCC_IOPENR) . . . . . . . . . . . . . . . . . . . . 196
7.3.12 AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 198
7.3.13 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 199
7.3.14 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 201
7.3.15 GPIO clock enable in Sleep mode register (RCC_IOPSMENR) . . . . . 203
7.3.16 AHB peripheral clock enable in Sleep mode
register (RCC_AHBSMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
7.3.17 APB2 peripheral clock enable in Sleep mode
register (RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.3.18 APB1 peripheral clock enable in Sleep mode
register (RCC_APB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
7.3.19 Clock configuration register (RCC_CCIPR) . . . . . . . . . . . . . . . . . . . . . 208
7.3.20 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
7.3.21 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

8 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
8.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
8.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
8.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8.3.2 I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 219
8.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.3.8 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
8.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
8.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
8.3.13 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 224
8.3.14 Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 224
8.3.15 BOOT0/GPIO pin sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8.4 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

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8.4.1 GPIO port mode register (GPIOx_MODER)

(x =A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8.4.2 GPIO port output type register (GPIOx_OTYPER)
(x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
8.4.3 GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
8.4.5 GPIO port input data register (GPIOx_IDR)
(x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
8.4.6 GPIO port output data register (GPIOx_ODR)
(x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
8.4.7 GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
8.4.8 GPIO port configuration lock register (GPIOx_LCKR)
(x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
8.4.9 GPIO alternate function low register (GPIOx_AFRL)
(x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
8.4.10 GPIO alternate function high register (GPIOx_AFRH)
(x = A to E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to E and H) . . . . . . . 230
8.4.12 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

9 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 233

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
9.2 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
9.2.1 SYSCFG memory remap register (SYSCFG_CFGR1) . . . . . . . . . . . . 234
9.2.2 SYSCFG peripheral mode configuration register (SYSCFG_CFGR2) 235
9.2.3 Reference control and status register (SYSCFG_CFGR3) . . . . . . . . . 236
9.2.4 SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
9.2.5 SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
9.2.6 SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
9.2.7 SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
9.2.8 SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

10 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 241

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

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10.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

10.3 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
10.3.1 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
10.3.2 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242

10.4 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

10.4.1 DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
10.4.2 DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
10.4.3 DMA arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
10.4.4 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Programmable data sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
Pointer incrementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
Channel configuration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
Channel state and disabling a channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
Circular mode (in memory-to-peripheral/peripheral-to-memory transfers) . . . . .249
Memory-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
Peripheral-to-peripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
Programming transfer direction, assigning source/destination . . . . . . . . . . . . . .250
10.4.5 DMA data width, alignment and endianness . . . . . . . . . . . . . . . . . . . . 250
Addressing AHB peripherals not supporting byte/half-word write transfers . . . .251
10.4.6 DMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
10.5 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
10.6 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
10.6.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 253
10.6.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 255
10.6.3 DMA channel x configuration register (DMA_CCRx) . . . . . . . . . . . . . . 256
10.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx) . 259
10.6.5 DMA channel x peripheral address register (DMA_CPARx) . . . . . . . . 260
10.6.6 DMA channel x memory address register (DMA_CMARx) . . . . . . . . . 260
10.6.7 DMA channel selection register (DMA_CSELR) . . . . . . . . . . . . . . . . . 262
10.6.8 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

11 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 265

11.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
11.2 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
11.3 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

12 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . 268

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12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

12.2 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
12.3 EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
12.3.1 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
12.3.2 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
12.3.3 Peripherals asynchronous interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 270
12.3.4 Hardware interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
12.3.5 Hardware event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
12.3.6 Software interrupt/event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
12.4 EXTI interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
12.5 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
12.5.1 EXTI interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . 273
12.5.2 EXTI event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . 273
12.5.3 EXTI rising edge trigger selection register (EXTI_RTSR) . . . . . . . . . . 274
12.5.4 Falling edge trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . 275
12.5.5 EXTI software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . 275
12.5.6 EXTI pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
12.5.7 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

13 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
13.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
13.3 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
13.3.1 ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
13.3.2 ADC voltage regulator (ADVREGEN) . . . . . . . . . . . . . . . . . . . . . . . . . 281
Analog reference for the ADC internal voltage regulator . . . . . . . . . . . . . . . . . .281
ADVREG enable sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
ADVREG disable sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
13.3.3 Calibration (ADCAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Calibration factor forcing software procedure . . . . . . . . . . . . . . . . . . . . . . . . . . .284
13.3.4 ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . . 284
13.3.5 ADC clock (CKMODE, PRESC[3:0], LFMEN) . . . . . . . . . . . . . . . . . . . 285
Low frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286
13.3.6 ADC connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
13.3.7 Configuring the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
13.3.8 Channel selection (CHSEL, SCANDIR) . . . . . . . . . . . . . . . . . . . . . . . . 288
Temperature sensor, VREFINT internal channels . . . . . . . . . . . . . . . . . . . . . . . .288

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13.3.9 Programmable sampling time (SMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 289

13.3.10 Single conversion mode (CONT = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 289
13.3.11 Continuous conversion mode (CONT = 1) . . . . . . . . . . . . . . . . . . . . . . 290
13.3.12 Starting conversions (ADSTART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
13.3.13 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
13.3.14 Stopping an ongoing conversion (ADSTP) . . . . . . . . . . . . . . . . . . . . . 292
13.4 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . 292
13.4.1 Discontinuous mode (DISCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
13.4.2 Programmable resolution (RES) - Fast conversion mode . . . . . . . . . . 293
13.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . 294
13.4.4 End of conversion sequence (EOS flag) . . . . . . . . . . . . . . . . . . . . . . . 294
13.4.5 Example timing diagrams (single/continuous modes
hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
13.5 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
13.5.1 Data register and data alignment (ADC_DR, ALIGN) . . . . . . . . . . . . . 297
13.5.2 ADC overrun (OVR, OVRMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
13.5.3 Managing a sequence of data converted without using the DMA . . . . 298
13.5.4 Managing converted data without using the DMA without overrun . . . 298
13.5.5 Managing converted data using the DMA . . . . . . . . . . . . . . . . . . . . . . 298
DMA one shot mode (DMACFG = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299
DMA circular mode (DMACFG = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299

13.6 Low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

13.6.1 Wait mode conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
13.6.2 Auto-off mode (AUTOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
13.7 Analog window watchdog (AWDEN, AWDSGL, AWDCH,
ADC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
13.7.1 Description of the analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
13.7.2 ADC_AWD1_OUT output signal generation . . . . . . . . . . . . . . . . . . . . 303
13.7.3 Analog watchdog threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
13.8 Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
13.8.1 ADC operating modes supported when oversampling . . . . . . . . . . . . 308
13.8.2 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
13.8.3 Triggered mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
13.9 Temperature sensor and internal reference voltage . . . . . . . . . . . . . . . . 309
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
Reading the temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
Calculating the actual VDDA voltage using the internal reference voltage . . . . .311
Converting a supply-relative ADC measurement to an absolute voltage value .311

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13.10 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

13.11 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
13.11.1 ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . 313
13.11.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 314
13.11.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
13.11.4 ADC configuration register 1 (ADC_CFGR1) . . . . . . . . . . . . . . . . . . . 318
13.11.5 ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . . 322
13.11.6 ADC sampling time register (ADC_SMPR) . . . . . . . . . . . . . . . . . . . . . 323
13.11.7 ADC watchdog threshold register (ADC_TR) . . . . . . . . . . . . . . . . . . . 324
13.11.8 ADC channel selection register (ADC_CHSELR) . . . . . . . . . . . . . . . . 324
13.11.9 ADC data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
13.11.10 ADC Calibration factor (ADC_CALFACT) . . . . . . . . . . . . . . . . . . . . . . 325
13.11.11 ADC common configuration register (ADC_CCR) . . . . . . . . . . . . . . . . 326
13.12 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

14 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
14.2 COMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
14.3 COMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
14.3.1 COMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
14.3.2 COMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
14.3.3 COMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
14.3.4 Comparator LOCK mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
14.3.5 Power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
14.4 COMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
14.5 COMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
14.5.1 Comparator 1 control and status register (COMP1_CSR) . . . . . . . . . . 331
14.5.2 Comparator 2 control and status register (COMP2_CSR) . . . . . . . . . . 333
14.5.3 COMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

15 AES hardware accelerator (AES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
15.2 AES main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
15.3 AES implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
15.4 AES functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
15.4.1 AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

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15.4.2 AES internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

15.4.3 AES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
Typical data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
Chaining modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339
Electronic codebook (ECB) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
Cipher block chaining (CBC) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341
Counter (CTR) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
15.4.4 AES procedure to perform a cipher operation . . . . . . . . . . . . . . . . . . . 342
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .342
Initialization of AES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
Data append . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343
15.4.5 AES decryption key preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
15.4.6 AES ciphertext stealing and data padding . . . . . . . . . . . . . . . . . . . . . . 346
15.4.7 AES task suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
15.4.8 AES basic chaining modes (ECB, CBC) . . . . . . . . . . . . . . . . . . . . . . . 347
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
ECB/CBC encryption sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350
ECB/CBC decryption sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350
Suspend/resume operations in ECB/CBC modes . . . . . . . . . . . . . . . . . . . . . . .351
Alternative single ECB/CBC decryption using Mode 4 . . . . . . . . . . . . . . . . . . . .352
15.4.9 AES counter (CTR) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352
CTR encryption and decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
Suspend/resume operations in CTR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
15.4.10 AES data registers and data swapping . . . . . . . . . . . . . . . . . . . . . . . . 355
Data input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
Data swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
Data padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357
15.4.11 AES key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
15.4.12 AES initialization vector registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
15.4.13 AES DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Data input using DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
Data output using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
DMA operation in different operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . .359
15.4.14 AES error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Read error flag (RDERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360
Write error flag (WDERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360

15.5 AES interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

15.6 AES processing latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

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15.7 AES registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

15.7.1 AES control register (AES_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
15.7.2 AES status register (AES_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
15.7.3 AES data input register (AES_DINR) . . . . . . . . . . . . . . . . . . . . . . . . . 365
15.7.4 AES data output register (AES_DOUTR) . . . . . . . . . . . . . . . . . . . . . . 365
15.7.5 AES key register 0 (AES_KEYR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
15.7.6 AES key register 1 (AES_KEYR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
15.7.7 AES key register 2 (AES_KEYR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
15.7.8 AES key register 3 (AES_KEYR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
15.7.9 AES initialization vector register 0 (AES_IVR0) . . . . . . . . . . . . . . . . . . 368
15.7.10 AES initialization vector register 1 (AES_IVR1) . . . . . . . . . . . . . . . . . . 368
15.7.11 AES initialization vector register 2 (AES_IVR2) . . . . . . . . . . . . . . . . . . 369
15.7.12 AES initialization vector register 3 (AES_IVR3) . . . . . . . . . . . . . . . . . . 369
15.7.13 AES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

16 General-purpose timers (TIM2/TIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . 371

16.1 TIM2/TIM3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
16.2 TIM2/TIM3 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
16.3 TIM2/TIM3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
16.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Prescaler description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
16.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Upcounting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
Downcounting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
Center-aligned mode (up/down counting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
16.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
Internal clock source (CK_INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .385
External clock source mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386
External clock source mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388
16.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
16.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
16.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
16.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
16.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
16.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
PWM edge-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .396
Downcounting configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397
PWM center-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .397

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16.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

Particular case: OCx fast enable: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400
16.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 400
16.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
16.3.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
16.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 404
Slave mode: Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404
Slave mode: Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405
Slave mode: Trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406
Slave mode: External Clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . .407
16.3.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Using one timer as prescaler for another timer . . . . . . . . . . . . . . . . . . . . . . . . .408
Using one timer to enable another timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409
Using one timer to start another timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411
Starting 2 timers synchronously in response to an external trigger . . . . . . . . . .413
16.3.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
16.4 TIM2/TIM3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
16.4.1 TIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 415
16.4.2 TIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 417
16.4.3 TIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 418
16.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 420
16.4.5 TIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
16.4.6 TIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 423
16.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 424
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424
Input capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
16.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 427
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
Input capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428
16.4.9 TIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . 428
16.4.10 TIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
16.4.11 TIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
16.4.12 TIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 430
16.4.13 TIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 431
16.4.14 TIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 431
16.4.15 TIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 432
16.4.16 TIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 432
16.4.17 TIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 433

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16.4.18 TIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 433

Example of how to use the DMA burst feature . . . . . . . . . . . . . . . . . . . . . . . . . .434
16.4.19 TIM2 option register (TIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
16.4.20 TIM3 option register (TIM3_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
16.5 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

17 General-purpose timers (TIM21/22) . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
17.2 TIM21/22 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
17.2.1 TIM21/22 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
17.3 TIM21/22 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
17.3.1 Timebase unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Prescaler description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441
17.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
Upcounting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443
Downcounting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447
Center-aligned mode (up/down counting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450
17.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
Internal clock source (CK_INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .454
External clock source mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .456
17.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
17.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
17.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
17.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
17.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
17.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
PWM center-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .465
Hints on using center-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .466
17.3.10 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 466
17.3.11 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Particular case: OCx fast enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .469
17.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
17.3.13 TIM21/22 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 471
Slave mode: Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .471
Slave mode: Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .472
Slave mode: Trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .473
17.3.14 Timer synchronization (TIM21/22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
17.3.15 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

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17.4 TIM21/22 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

17.4.1 TIM21/22 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . 475
17.4.2 TIM21/22 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . 477
17.4.3 TIM21/22 slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . 478
17.4.4 TIM21/22 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 481
17.4.5 TIM21/22 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 481
17.4.6 TIM21/22 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . 483
17.4.7 TIM21/22 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . 484
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .484
Input capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .486
17.4.8 TIM21/22 capture/compare enable register (TIMx_CCER) . . . . . . . . . 487
17.4.9 TIM21/22 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
17.4.10 TIM21/22 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
17.4.11 TIM21/22 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . 488
17.4.12 TIM21/22 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . 489
17.4.13 TIM21/22 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . 489
17.4.14 TIM21 option register (TIM21_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
17.4.15 TIM22 option register (TIM22_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
17.4.16 TIM21/22 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

18 Basic timers (TIM6/7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
18.2 TIM6/7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
18.3 TIM6/7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
18.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Prescaler description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .495
18.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
18.3.3 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
18.3.4 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
18.4 TIM6/7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
18.4.1 TIM6/7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 502
18.4.2 TIM6/7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 503
18.4.3 TIM6/7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . 503
18.4.4 TIM6/7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
18.4.5 TIM6/7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . 504
18.4.6 TIM6/7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
18.4.7 TIM6/7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

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18.4.8 TIM6/7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . 505

18.4.9 TIM6/7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

19 Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
19.2 LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
19.3 LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
19.4 LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
19.4.1 LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
19.4.2 LPTIM trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
19.4.3 LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
19.4.4 Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
19.4.5 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
19.4.6 Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
19.4.7 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
One-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .511
Continous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .512
19.4.8 Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
19.4.9 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
19.4.10 Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
19.4.11 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
19.4.12 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
19.4.13 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
19.4.14 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
19.5 LPTIM low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
19.6 LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
19.7 LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
19.7.1 LPTIM interrupt and status register (LPTIM_ISR) . . . . . . . . . . . . . . . . 519
19.7.2 LPTIM interrupt clear register (LPTIM_ICR) . . . . . . . . . . . . . . . . . . . . 520
19.7.3 LPTIM interrupt enable register (LPTIM_IER) . . . . . . . . . . . . . . . . . . . 520
19.7.4 LPTIM configuration register (LPTIM_CFGR) . . . . . . . . . . . . . . . . . . . 521
19.7.5 LPTIM control register (LPTIM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 524
19.7.6 LPTIM compare register (LPTIM_CMP) . . . . . . . . . . . . . . . . . . . . . . . 525
19.7.7 LPTIM autoreload register (LPTIM_ARR) . . . . . . . . . . . . . . . . . . . . . . 526
19.7.8 LPTIM counter register (LPTIM_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 526
19.7.9 LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

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20 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
20.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
20.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
20.3.1 IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
20.3.2 Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Configuring the IWDG when the window option is enabled . . . . . . . . . . . . . . . .529
Configuring the IWDG when the window option is disabled . . . . . . . . . . . . . . . .529
20.3.3 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
20.3.4 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
20.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
20.4 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
20.4.1 IWDG key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
20.4.2 IWDG prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . 532
20.4.3 IWDG reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
20.4.4 IWDG status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
20.4.5 IWDG window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . . 535
20.4.6 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

21 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . 537

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
21.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
21.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
21.3.1 WWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
21.3.2 Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
21.3.3 Controlling the down-counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
21.3.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . 538
21.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
21.4 WWDG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
21.5 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
21.5.1 WWDG control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 540
21.5.2 WWDG configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . 541
21.5.3 WWDG status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 541
21.5.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

22 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

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22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

22.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
22.3 RTC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
22.4 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
22.4.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
22.4.2 GPIOs controlled by the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
22.4.3 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
22.4.4 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
22.4.5 Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
22.4.6 Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
22.4.7 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
RTC register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550
RTC register write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550
Calendar initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550
Daylight saving time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .551
Programming the alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .551
Programming the wakeup timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .551
22.4.8 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
When BYPSHAD control bit is cleared in the RTC_CR register. . . . . . . . . . . . .551
When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow reg-
isters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .552
22.4.9 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
22.4.10 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
22.4.11 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
22.4.12 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
Calibration when PREDIV_A<3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .555
Verifying the RTC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .555
Re-calibration on-the-fly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556
22.4.13 Time-stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
22.4.14 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
RTC backup registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
Tamper detection initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
Trigger output generation on tamper event . . . . . . . . . . . . . . . . . . . . . . . . . . . .558
Timestamp on tamper event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .558
Edge detection on tamper inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .558
Level detection with filtering on RTC_TAMPx inputs . . . . . . . . . . . . . . . . . . . . .558
22.4.15 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
22.4.16 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .559

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22.5 RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

22.6 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
22.7 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
22.7.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
22.7.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
22.7.3 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
22.7.4 RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . . 566
22.7.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . . 569
22.7.6 RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . . 570
22.7.7 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . . 571
22.7.8 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . . 572
22.7.9 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . 573
22.7.10 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . . 573
22.7.11 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . . 574
22.7.12 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . . 575
22.7.13 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . . 576
22.7.14 RTC time-stamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . 577
22.7.15 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . . 578
22.7.16 RTC tamper configuration register (RTC_TAMPCR) . . . . . . . . . . . . . . 579
22.7.17 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . . 582
22.7.18 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . . 583
22.7.19 RTC option register (RTC_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
22.7.20 RTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . . 585
22.7.21 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

23 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 588

23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
23.2 I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
23.3 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
23.4 I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
23.4.1 I2C1/3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
23.4.2 I2C2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
23.4.3 I2C pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
23.4.4 I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
23.4.5 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
Communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .593

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23.4.6 I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Enabling and disabling the peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .593
Noise filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .593
I2C timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .595
23.4.7 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
23.4.8 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .599
Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600
Hardware transfer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600
23.4.9 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
I2C slave initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .601
Slave clock stretching (NOSTRETCH = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .602
Slave without clock stretching (NOSTRETCH = 1). . . . . . . . . . . . . . . . . . . . . . .602
Slave byte control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .603
Slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .604
Slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .608
23.4.10 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
I2C master initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .610
Master communication initialization (address phase) . . . . . . . . . . . . . . . . . . . . .612
Initialization of a master receiver addressing a 10-bit address slave . . . . . . . . .613
Master transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .614
Master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .618
23.4.11 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . . 622
23.4.12 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .623
Bus protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .623
Address resolution protocol (ARP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .623
Received command and data acknowledge control . . . . . . . . . . . . . . . . . . . . . .624
Host notify protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .624
SMBus alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .624
Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .624
Timeouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .624
Bus idle detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .626
23.4.13 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
Received command and data acknowledge control (Slave mode). . . . . . . . . . .626
Specific address (Slave mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .626
Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .626
Timeout detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .627
Bus idle detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .627
23.4.14 SMBus: I2C_TIMEOUTR register configuration examples . . . . . . . . . 628
23.4.15 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

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SMBus slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .628

SMBus Slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .630
SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .632
SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .634
23.4.16 Wakeup from Stop mode on address match . . . . . . . . . . . . . . . . . . . . 636
23.4.17 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
Bus error (BERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .636
Arbitration lost (ARLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .637
Overrun/underrun error (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .637
Packet error checking error (PECERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .637
Timeout Error (TIMEOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .637
Alert (ALERT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .638
23.4.18 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .638
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .639
23.4.19 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
23.5 I2C low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
23.6 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
23.7 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
23.7.1 I2C control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
23.7.2 I2C control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
23.7.3 I2C own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . 646
23.7.4 I2C own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . 647
23.7.5 I2C timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
23.7.6 I2C timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . . 649
23.7.7 I2C interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . . 650
23.7.8 I2C interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . . 652
23.7.9 I2C PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
23.7.10 I2C receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . 654
23.7.11 I2C transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . 654
23.7.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655

24 Universal synchronous/asynchronous receiver

transmitter (USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
24.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
24.3 USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
24.4 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

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24.5 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

24.5.1 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
24.5.2 USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
Character transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .664
Single byte communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .665
Break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .666
Idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .666
24.5.3 USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Start bit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .667
Character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .668
Break character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .668
Idle character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .668
Overrun error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .669
Selecting the proper oversampling method . . . . . . . . . . . . . . . . . . . . . . . . . . . .669
Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .671
Configurable stop bits during reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .672
24.5.4 USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672
How to derive USARTDIV from USART_BRR register values . . . . . . . . . . . . . .673
24.5.5 Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . . 674
24.5.6 USART auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
24.5.7 Multiprocessor communication using USART . . . . . . . . . . . . . . . . . . . 677
Idle line detection (WAKE=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .678
4-bit/7-bit address mark detection (WAKE=1) . . . . . . . . . . . . . . . . . . . . . . . . . .678
24.5.8 Modbus communication using USART . . . . . . . . . . . . . . . . . . . . . . . . 679
Modbus/RTU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .679
Modbus/ASCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .679
24.5.9 USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
Even parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .680
Odd parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .680
Parity checking in reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .680
Parity generation in transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .680
24.5.10 USART LIN (local interconnection network) mode . . . . . . . . . . . . . . . 681
LIN transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .681
LIN reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .681
24.5.11 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
24.5.12 USART Single-wire Half-duplex communication . . . . . . . . . . . . . . . . . 686
24.5.13 USART Smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
Block mode (T=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .689
Direct and inverse convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .690
24.5.14 USART IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691

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IrDA low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .692

24.5.15 USART continuous communication in DMA mode . . . . . . . . . . . . . . . . 693
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .693
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .694
Error flagging and interrupt generation in multibuffer communication . . . . . . . .695
24.5.16 RS232 hardware flow control and RS485 driver enable
using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .696
RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .696
RS485 Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .697
24.5.17 Wakeup from Stop mode using USART . . . . . . . . . . . . . . . . . . . . . . . . 697
Using Mute mode with Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .698
Determining the maximum USART baud rate allowing to wakeup correctly from
Stop mode when the USART clock source is the HSI clock. . . . . . . . . . . . . . . .698

24.6 USART in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

24.7 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
24.8 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
24.8.1 USART control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . 701
24.8.2 USART control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . 704
24.8.3 USART control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . 708
24.8.4 USART baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . 712
24.8.5 USART guard time and prescaler register (USART_GTPR) . . . . . . . . 712
24.8.6 USART receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . . 713
24.8.7 USART request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . . 714
24.8.8 USART interrupt and status register (USART_ISR) . . . . . . . . . . . . . . 715
24.8.9 USART interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . . 720
24.8.10 USART receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . . 722
24.8.11 USART transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . . 722
24.8.12 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723

25 Low-power universal asynchronous receiver

transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
25.2 LPUART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
25.3 LPUART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
25.4 LPUART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
25.4.1 LPUART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
25.4.2 LPUART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732

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Character transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .732

Single byte communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .733
Break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .734
Idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .734
25.4.3 LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
Start bit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .734
Character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .735
Break character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .735
Idle character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .735
Overrun error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .736
Selecting the clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .736
Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .737
Configurable stop bits during reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .737
25.4.4 LPUART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
25.4.5 Tolerance of the LPUART receiver to clock deviation . . . . . . . . . . . . . 739
25.4.6 Multiprocessor communication using LPUART . . . . . . . . . . . . . . . . . . 740
Idle line detection (WAKE=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .740
4-bit/7-bit address mark detection (WAKE=1) . . . . . . . . . . . . . . . . . . . . . . . . . .741
25.4.7 LPUART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
Even parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .742
Odd parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .742
Parity checking in reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .743
Parity generation in transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .743
25.4.8 Single-wire Half-duplex communication using LPUART . . . . . . . . . . . 743
25.4.9 Continuous communication in DMA mode using LPUART . . . . . . . . . 743
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .744
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .745
Error flagging and interrupt generation in multibuffer communication . . . . . . . .746
25.4.10 RS232 Hardware flow control and RS485 Driver Enable
using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .747
RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .747
RS485 Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .748
25.4.11 Wakeup from Stop mode using LPUART . . . . . . . . . . . . . . . . . . . . . . . 749
Using Mute mode with Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .750
Determining the maximum LPUART baud rate allowing to wakeup correctly from
Stop mode when the LPUART clock source is the HSI clock. . . . . . . . . . . . . . .750

25.5 LPUART in low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

25.6 LPUART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
25.7 LPUART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753

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25.7.1 Control register 1 (LPUART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753

25.7.2 Control register 2 (LPUART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
25.7.3 Control register 3 (LPUART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
25.7.4 Baud rate register (LPUART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
25.7.5 Request register (LPUART_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
25.7.6 Interrupt & status register (LPUART_ISR) . . . . . . . . . . . . . . . . . . . . . . 761
25.7.7 Interrupt flag clear register (LPUART_ICR) . . . . . . . . . . . . . . . . . . . . . 764
25.7.8 Receive data register (LPUART_RDR) . . . . . . . . . . . . . . . . . . . . . . . . 765
25.7.9 Transmit data register (LPUART_TDR) . . . . . . . . . . . . . . . . . . . . . . . . 765
25.7.10 LPUART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

26 Serial peripheral interface/ inter-IC sound (SPI/I2S) . . . . . . . . . . . . . 768

26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
26.1.1 SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
26.1.2 SPI extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
26.1.3 I2S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
26.2 SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
26.3 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
26.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
26.3.2 Communications between one master and one slave . . . . . . . . . . . . . 771
Full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .771
Half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .771
Simplex communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .772
26.3.3 Standard multi-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . . 774
26.3.4 Multi-master communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
26.3.5 Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . . 775
26.3.6 Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
Clock phase and polarity controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .777
Data frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .778
26.3.7 SPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
26.3.8 Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
26.3.9 Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 780
Rx and Tx buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .780
Tx buffer handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .780
Rx buffer handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .780
Sequence handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .780
26.3.10 Procedure for disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
26.3.11 Communication using DMA (direct memory addressing) . . . . . . . . . . . 783

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26.3.12 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785

Tx buffer empty flag (TXE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .785
Rx buffer not empty (RXNE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .785
Busy flag (BSY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .785
26.3.13 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
Overrun flag (OVR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .786
Mode fault (MODF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .786
CRC error (CRCERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .787
TI mode frame format error (FRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .787

26.4 SPI special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787

26.4.1 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
TI protocol in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .787
26.4.2 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
CRC principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .788
CRC transfer managed by CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .788
CRC transfer managed by DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .789
Resetting the SPIx_TXCRC and SPIx_RXCRC values . . . . . . . . . . . . . . . . . . .789

26.5 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790

26.6 I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
26.6.1 I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
26.6.2 I2S full-duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
26.6.3 Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
I2S Philips standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .794
MSB justified standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .796
LSB justified standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .797
PCM standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .799
26.6.4 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
26.6.5 I2S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .802
Transmission sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .802
Reception sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .803
26.6.6 I2S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
Transmission sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .804
Reception sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .805
26.6.7 I2S status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
Busy flag (BSY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .805
Tx buffer empty flag (TXE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .806
RX buffer not empty (RXNE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .806
Channel Side flag (CHSIDE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .806
26.6.8 I2S error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806

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Underrun flag (UDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .806

Overrun flag (OVR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .807
Frame error flag (FRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .807
26.6.9 I2S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
26.6.10 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
26.7 SPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
26.7.1 SPI control register 1 (SPI_CR1) (not used in I2S mode) . . . . . . . . . . 808
26.7.2 SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
26.7.3 SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
26.7.4 SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
26.7.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I2S
mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
26.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I2S mode) . . . . . . 814
26.7.7 SPI TX CRC register (SPI_TXCRCR) (not used in I2S mode) . . . . . . . 814
26.7.8 SPI_I2S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . . 815
26.7.9 SPI_I2S prescaler register (SPI_I2SPR) . . . . . . . . . . . . . . . . . . . . . . . 816
26.7.10 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817

27 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818

27.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
27.2 Reference Arm® documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
27.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
27.3.1 SWD port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
27.3.2 SW-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
27.3.3 Internal pull-up & pull-down on SWD pins . . . . . . . . . . . . . . . . . . . . . . 820
27.4 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
27.4.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
DBG_IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .820

27.5 SWD port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821

27.5.1 SWD protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
27.5.2 SWD protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
27.5.3 SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . . 822
27.5.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
27.5.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
27.5.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
27.6 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
27.7 BPU (Break Point Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825

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27.7.1 BPU functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825

27.8 DWT (Data Watchpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
27.8.1 DWT functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
27.8.2 DWT Program Counter Sample Register . . . . . . . . . . . . . . . . . . . . . . . 826
27.9 MCU debug component (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
27.9.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 826
27.9.2 Debug support for timers, watchdog and I2C . . . . . . . . . . . . . . . . . . . . 827
27.9.3 Debug MCU configuration register (DBG_CR) . . . . . . . . . . . . . . . . . . 827
27.9.4 Debug MCU APB1 freeze register (DBG_APB1_FZ) . . . . . . . . . . . . . 829
27.9.5 Debug MCU APB2 freeze register (DBG_APB2_FZ) . . . . . . . . . . . . . 831
27.10 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832

28 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833

28.1 Memory size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
28.1.1 Flash size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
28.2 Unique device ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833

Appendix A Code examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835

A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
A.2 NVM/RCC Operation code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
A.2.1 Increasing the CPU frequency preparation sequence code . . . . . . . . . 835
A.2.2 Decreasing the CPU frequency preparation sequence code . . . . . . . . 835
A.2.3 Switch from PLL to HSI16 sequence code . . . . . . . . . . . . . . . . . . . . . . 836
A.2.4 Switch to PLL sequence code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
A.3 NVM Operation code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
A.3.1 Unlocking the data EEPROM and FLASH_PECR register
code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
A.3.2 Locking data EEPROM and FLASH_PECR register code example . . . 837
A.3.3 Unlocking the NVM program memory code example . . . . . . . . . . . . . . 837
A.3.4 Unlocking the option bytes area code example . . . . . . . . . . . . . . . . . . 838
A.3.5 Write to data EEPROM code example . . . . . . . . . . . . . . . . . . . . . . . . . 838
A.3.6 Erase to data EEPROM code example . . . . . . . . . . . . . . . . . . . . . . . . 838
A.3.7 Program Option byte code example . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
A.3.8 Erase Option byte code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
A.3.9 Program a single word to Flash program memory code example . . . . 840
A.3.10 Program half-page to Flash program memory code example . . . . . . . 841
A.3.11 Erase a page in Flash program memory code example . . . . . . . . . . . . 842

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A.3.12 Mass erase code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843

A.4 Clock Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
A.4.1 HSE start sequence code example . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
A.4.2 PLL configuration modification code example . . . . . . . . . . . . . . . . . . . 845
A.4.3 MCO selection code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
A.5 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
A.5.1 Locking mechanism code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
A.5.2 Alternate function selection sequence code example. . . . . . . . . . . . . . 846
A.5.3 Analog GPIO configuration code example . . . . . . . . . . . . . . . . . . . . . . 846
A.6 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
A.6.1 DMA Channel Configuration sequence code example . . . . . . . . . . . . . 847
A.7 Interrupts and event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
A.7.1 NVIC initialization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
A.7.2 Extended interrupt selection code example . . . . . . . . . . . . . . . . . . . . . 847
A.8 ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
A.8.1 Calibration code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
A.8.2 ADC enable sequence code example . . . . . . . . . . . . . . . . . . . . . . . . . 848
A.8.3 ADC disable sequence code example . . . . . . . . . . . . . . . . . . . . . . . . . 849
A.8.4 ADC clock selection code example . . . . . . . . . . . . . . . . . . . . . . . . . . . 849
A.8.5 Single conversion sequence code example - Software trigger . . . . . . . 849
A.8.6 Continuous conversion sequence code example - Software trigger. . . 850
A.8.7 Single conversion sequence code example - Hardware trigger . . . . . . 850
A.8.8 Continuous conversion sequence code example - Hardware trigger . . 851
A.8.9 DMA one shot mode sequence code example . . . . . . . . . . . . . . . . . . . 851
A.8.10 DMA circular mode sequence code example . . . . . . . . . . . . . . . . . . . . 852
A.8.11 Wait mode sequence code example. . . . . . . . . . . . . . . . . . . . . . . . . . . 852
A.8.12 Auto off and no wait mode sequence code example . . . . . . . . . . . . . . 852
A.8.13 Auto off and wait mode sequence code example . . . . . . . . . . . . . . . . . 853
A.8.14 Analog watchdog code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
A.8.15 Oversampling code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
A.8.16 Temperature configuration code example. . . . . . . . . . . . . . . . . . . . . . . 854
A.8.17 Temperature computation code example . . . . . . . . . . . . . . . . . . . . . . . 854
A.9 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
A.9.1 Upcounter on TI2 rising edge code example . . . . . . . . . . . . . . . . . . . . 855
A.9.2 Up counter on each 2 ETR rising edges code example . . . . . . . . . . . . 855
A.9.3 Input capture configuration code example . . . . . . . . . . . . . . . . . . . . . . 856

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A.9.4 Input capture data management code example . . . . . . . . . . . . . . . . . . 856

A.9.5 PWM input configuration code example . . . . . . . . . . . . . . . . . . . . . . . . 857
A.9.6 PWM input with DMA configuration code example . . . . . . . . . . . . . . . . 857
A.9.7 Output compare configuration code example . . . . . . . . . . . . . . . . . . . . 858
A.9.8 Edge-aligned PWM configuration example. . . . . . . . . . . . . . . . . . . . . . 858
A.9.9 Center-aligned PWM configuration example . . . . . . . . . . . . . . . . . . . . 859
A.9.10 ETR configuration to clear OCxREF code example . . . . . . . . . . . . . . . 859
A.9.11 Encoder interface code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
A.9.12 Reset mode code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
A.9.13 Gated mode code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
A.9.14 Trigger mode code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
A.9.15 External clock mode 2 + trigger mode code example. . . . . . . . . . . . . . 862
A.9.16 One-Pulse mode code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
A.9.17 Timer prescaling another timer code example . . . . . . . . . . . . . . . . . . . 863
A.9.18 Timer enabling another timer code example. . . . . . . . . . . . . . . . . . . . . 863
A.9.19 Master and slave synchronization code example . . . . . . . . . . . . . . . . . 864
A.9.20 Two timers synchronized by an external trigger code example . . . . . . 866
A.9.21 DMA burst feature code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
A.10 Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
A.10.1 Pulse counter configuration code example . . . . . . . . . . . . . . . . . . . . . . 868
A.11 IWDG code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
A.11.1 IWDG configuration code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
A.11.2 IWDG configuration with window code example. . . . . . . . . . . . . . . . . . 868
A.12 WWDG code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
A.12.1 WWDG configuration code example. . . . . . . . . . . . . . . . . . . . . . . . . . . 869
A.13 RTC code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
A.13.1 RTC calendar configuration code example. . . . . . . . . . . . . . . . . . . . . . 869
A.13.2 RTC alarm configuration code example . . . . . . . . . . . . . . . . . . . . . . . . 870
A.13.3 RTC WUT configuration code example . . . . . . . . . . . . . . . . . . . . . . . . 870
A.13.4 RTC read calendar code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
A.13.5 RTC calibration code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
A.13.6 RTC tamper and time stamp configuration code example . . . . . . . . . . 871
A.13.7 RTC tamper and time stamp code example . . . . . . . . . . . . . . . . . . . . . 872
A.13.8 RTC clock output code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
A.14 I2C code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
A.14.1 I2C configured in slave mode code example . . . . . . . . . . . . . . . . . . . . 872

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A.14.2 I2C slave transmitter code example . . . . . . . . . . . . . . . . . . . . . . . . . . . 873

A.14.3 I2C slave receiver code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
A.14.4 I2C configured in master mode to receive code example. . . . . . . . . . . 873
A.14.5 I2C configured in master mode to transmit code example . . . . . . . . . . 874
A.14.6 I2C master transmitter code example . . . . . . . . . . . . . . . . . . . . . . . . . . 874
A.14.7 I2C master receiver code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
A.14.8 I2C configured in master mode to transmit with DMA code example . . 874
A.14.9 I2C configured in slave mode to receive with DMA code example . . . . 875
A.15 USART code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
A.15.1 USART transmitter configuration code example. . . . . . . . . . . . . . . . . . 875
A.15.2 USART transmit byte code example. . . . . . . . . . . . . . . . . . . . . . . . . . . 875
A.15.3 USART transfer complete code example . . . . . . . . . . . . . . . . . . . . . . . 875
A.15.4 USART receiver configuration code example . . . . . . . . . . . . . . . . . . . . 875
A.15.5 USART receive byte code example . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
A.15.6 USART LIN mode code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
A.15.7 USART synchronous mode code example . . . . . . . . . . . . . . . . . . . . . . 876
A.15.8 USART single-wire half-duplex code example . . . . . . . . . . . . . . . . . . . 877
A.15.9 USART smartcard mode code example . . . . . . . . . . . . . . . . . . . . . . . . 877
A.15.10 USART IrDA mode code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
A.15.11 USART DMA code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
A.15.12 USART hardware flow control code example . . . . . . . . . . . . . . . . . . . . 878
A.16 LPUART code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
A.16.1 LPUART receiver configuration code example . . . . . . . . . . . . . . . . . . . 879
A.16.2 LPUART receive byte code example . . . . . . . . . . . . . . . . . . . . . . . . . . 879
A.17 SPI code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
A.17.1 SPI master configuration code example . . . . . . . . . . . . . . . . . . . . . . . . 879
A.17.2 SPI slave configuration code example . . . . . . . . . . . . . . . . . . . . . . . . . 879
A.17.3 SPI full duplex communication code example . . . . . . . . . . . . . . . . . . . 879
A.17.4 SPI master configuration with DMA code example . . . . . . . . . . . . . . . . 880
A.17.5 SPI slave configuration with DMA code example . . . . . . . . . . . . . . . . . 880
A.17.6 SPI interrupt code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
A.18 DBG code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
A.18.1 DBG read device Id code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
A.18.2 DBG debug in LPM code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881

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List of tables

Table 1. STM32L0x1 memory density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 2. Overview of features per category . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 3. STM32L0x1 peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 4. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 5. NVM organization (category 1 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 6. NVM organization (category 2 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 7. NVM organization (category 3 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 8. NVM organization for UFB = 0 (192 Kbyte category 5 devices) . . . . . . . . . . . . . . . . . . . . . 62
Table 9. Flash memory and data EEPROM remapping
(192 Kbyte category 5 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 10. NVM organization for UFB = 0 (128 Kbyte category 5 devices) . . . . . . . . . . . . . . . . . . . . . 63
Table 11. Flash memory and data EEPROM remapping (128 Kbyte category 5 devices) . . . . . . . . . 64
Table 12. NVM organization for UFB = 0 (64 Kbyte category 5 devices) . . . . . . . . . . . . . . . . . . . . . . 64
Table 13. Boot pin and BFB2 bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 14. Link between master clock power range and frequencies . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 15. Delays to memory access and number of wait states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 16. Internal buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 17. Configurations for buffers and speculative reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 18. Dhrystone performances in all memory interface configurations . . . . . . . . . . . . . . . . . . . . 74
Table 19. NVM write/erase timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 20. NVM write/erase duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 21. Protection level and content of RDP Option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 22. Link between protection bits of FLASH_WRPROTx register
and protected address in Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 23. Memory access vs mode, protection and Flash program memory sectors. . . . . . . . . . . . . 94
Table 24. Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 25. Flash interface - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 26. Option byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 27. Option byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 28. CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 29. CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 30. Segment accesses according to the Firewall state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 31. Segment granularity and area ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 32. Firewall register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 33. Performance versus VCORE ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 34. Summary of low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 35. Sleep-now . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 36. Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 37. Sleep-now (Low-power sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 38. Sleep-on-exit (Low-power sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 39. Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 40. Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 41. PWR - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 42. HSE/LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 43. System clock source frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 44. RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 45. Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 46. GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

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Table 47. SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Table 48. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Table 49. DMA requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Table 50. Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . . . . . . . 251
Table 51. DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Table 52. DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Table 53. List of vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Table 54. EXTI lines connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Table 55. Extended interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . 277
Table 56. ADC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 57. ADC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 58. External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 59. Latency between trigger and start of conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 60. Configuring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Table 61. tSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 62. Analog watchdog comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 63. Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 64. Maximum output results vs N and M. Grayed values indicates truncation . . . . . . . . . . . . 307
Table 65. ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Table 66. ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
Table 67. COMP register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Table 68. AES internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Table 69. CTR mode initialization vector definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Table 70. Key endianness in AES_KEYRx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Table 71. DMA channel configuration for memory-to-AES data transfer . . . . . . . . . . . . . . . . . . . . . 358
Table 72. DMA channel configuration for AES-to-memory data transfer . . . . . . . . . . . . . . . . . . . . . 359
Table 73. AES interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Table 74. Processing latency (in clock cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Table 75. AES register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Table 76. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Table 77. TIM2/TIM3 internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
Table 78. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Table 79. TIM2/3 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Table 80. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
Table 81. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Table 82. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
Table 83. TIM21/22 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
Table 84. TIM6/7 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Table 85. STM32L0x1 LPTIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Table 86. LPTIM1 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Table 87. Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Table 88. Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Table 89. Effect of low-power modes on the LPTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Table 90. Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
Table 91. LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Table 92. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Table 93. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Table 94. RTC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Table 95. RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Table 96. RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Table 97. Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
Table 98. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

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Table 99. RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

Table 100. STM32L0x1 I2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
Table 101. I2C input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
Table 102. I2C internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
Table 103. Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
Table 104. I2C-SMBus specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
Table 105. I2C configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Table 106. I2C-SMBus specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
Table 107. Examples of timing settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
Table 108. Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
Table 109. SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
Table 110. SMBus with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
Table 111. Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tTIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Table 112. Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . . 628
Table 113. Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tIDLE = 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Table 114. Effect of low-power modes on the I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
Table 115. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Table 116. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
Table 117. STM32L0x1 USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
Table 118. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
Table 119. Error calculation for programmed baud rates at fCK = 32 MHz in both cases of
oversampling by 16 or by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
Table 120. Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . . 675
Table 121. Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . . . . . . . . . 675
Table 122. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
Table 123. Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
Table 124. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
Table 125. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
Table 126. STM32L0x1 USART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
Table 127. Error calculation for programmed baud rates at fck = 32.768 kHz . . . . . . . . . . . . . . . . . . 738
Table 128. Error calculation for programmed baud rates at fck = 32 MHz . . . . . . . . . . . . . . . . . . . . . 738
Table 129. Tolerance of the LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
Table 130. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
Table 131. Effect of low-power modes on the LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
Table 132. LPUART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
Table 133. LPUART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
Table 134. STM32L0x1 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769
Table 135. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
Table 136. Audio-frequency precision using standard 8 MHz HSE . . . . . . . . . . . . . . . . . . . . . . . . . . 801
Table 137. I2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
Table 138. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
Table 139. SW debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
Table 140. REV_ID values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
Table 141. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
Table 142. ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
Table 143. DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
Table 144. SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
Table 145. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . . 824
Table 146. Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
Table 147. DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832

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List of tables RM0377

Table 148. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881

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RM0377 List of figures

List of figures

Figure 1. System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 2. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 3. Structure of one internal buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 4. Timing to fetch and execute instructions with prefetch disabled. . . . . . . . . . . . . . . . . . . . . 71
Figure 5. Timing to fetch and execute instructions with prefetch enabled . . . . . . . . . . . . . . . . . . . . . 73
Figure 6. RDP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 7. CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 8. STM32L0x1 firewall connection schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 9. Firewall functional states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 10. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 11. Performance versus VDD and VCORE range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 12. Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 13. Power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 14. BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 15. PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 16. Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 17. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 18. Using TIM21 channel 1 input capture to measure
frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 19. Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 20. Basic structure of a 5-Volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 21. Input floating / pull up / pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 22. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 23. Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Figure 24. High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 25. DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 26. DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 27. Extended interrupts and events controller (EXTI) block diagram . . . . . . . . . . . . . . . . . . . 269
Figure 28. Extended interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 29. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Figure 30. ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 31. Calibration factor forcing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 32. Enabling/disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Figure 33. ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Figure 34. ADC connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 35. Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 36. ADC conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 37. Stopping an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Figure 38. Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Figure 39. Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Figure 40. Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 41. Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 42. Data alignment and resolution (oversampling disabled: OVSE = 0). . . . . . . . . . . . . . . . . 297
Figure 43. Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Figure 44. Wait mode conversion (continuous mode, software trigger). . . . . . . . . . . . . . . . . . . . . . . 300
Figure 45. Behavior with WAIT = 0, AUTOFF = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Figure 46. Behavior with WAIT = 1, AUTOFF = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 47. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

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Figure 48. ADC_AWD1_OUT signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

Figure 49. ADC_AWD1_OUT signal generation (AWD flag not cleared by software) . . . . . . . . . . . . 305
Figure 50. ADC1_AWD_OUT signal generation (on a single channel) . . . . . . . . . . . . . . . . . . . . . . . 305
Figure 51. Analog watchdog threshold update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Figure 52. 20-bit to 16-bit result truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 53. Numerical example with 5-bits shift and rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Figure 54. Triggered oversampling mode (TOVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Figure 55. Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 310
Figure 56. Comparator 1 and 2 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Figure 57. AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
Figure 58. ECB encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Figure 59. CBC encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Figure 60. CTR encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Figure 61. STM32 cryptolib AES flowchart example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Figure 62. Encryption key derivation for ECB/CBC decryption (Mode 2). . . . . . . . . . . . . . . . . . . . . . 346
Figure 63. Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Figure 64. ECB encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Figure 65. ECB decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Figure 66. CBC encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Figure 67. CBC decryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Figure 68. ECB/CBC encryption (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
Figure 69. ECB/CBC decryption (Mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Figure 70. Message construction in CTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Figure 71. CTR encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Figure 72. CTR decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
Figure 73. 128-bit block construction with respect to data swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
Figure 74. DMA transfer of a 128-bit data block during input phase . . . . . . . . . . . . . . . . . . . . . . . . . 358
Figure 75. DMA transfer of a 128-bit data block during output phase . . . . . . . . . . . . . . . . . . . . . . . . 359
Figure 76. AES interrupt signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Figure 77. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Figure 78. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 374
Figure 79. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 374
Figure 80. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Figure 81. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Figure 82. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Figure 83. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
Figure 84. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 377
Figure 85. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 378
Figure 86. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Figure 87. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Figure 88. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Figure 89. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
Figure 90. Counter timing diagram, Update event when repetition counter
is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Figure 91. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 382
Figure 92. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Figure 93. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 383
Figure 94. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Figure 95. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 384
Figure 96. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 385
Figure 97. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 386
Figure 98. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

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Figure 99. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

Figure 100. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
Figure 101. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
Figure 102. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 390
Figure 103. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Figure 104. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Figure 105. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Figure 106. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Figure 107. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
Figure 108. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Figure 109. Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Figure 110. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Figure 111. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 403
Figure 112. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 403
Figure 113. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Figure 114. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Figure 115. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Figure 116. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Figure 117. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
Figure 118. Gating timer y with OC1REF of timer x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
Figure 119. Gating timer y with Enable of timer x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
Figure 120. Triggering timer y with update of timer x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Figure 121. Triggering timer y with Enable of timer x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Figure 122. Triggering timer x and y with timer x TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
Figure 123. General-purpose timer block diagram (TIM21/22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Figure 124. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 442
Figure 125. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 443
Figure 126. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
Figure 127. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Figure 128. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Figure 129. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Figure 130. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Figure 131. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
Figure 132. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Figure 133. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
Figure 134. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Figure 135. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Figure 136. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 451
Figure 137. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
Figure 138. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 452
Figure 139. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
Figure 140. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 453
Figure 141. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 453
Figure 142. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 454
Figure 143. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Figure 144. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Figure 145. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Figure 146. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Figure 147. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 458
Figure 148. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

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Figure 149. Output stage of capture/compare channel (channel 1 and 2). . . . . . . . . . . . . . . . . . . . . . 459
Figure 150. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Figure 151. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Figure 152. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Figure 153. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Figure 154. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Figure 155. Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Figure 156. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 470
Figure 157. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 471
Figure 158. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Figure 159. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
Figure 160. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
Figure 161. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
Figure 162. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 496
Figure 163. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 496
Figure 164. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Figure 165. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
Figure 166. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
Figure 167. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
Figure 168. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
Figure 169. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Figure 170. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 501
Figure 171. Low-power timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Figure 172. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Figure 173. LPTIM output waveform, single counting mode configuration . . . . . . . . . . . . . . . . . . . . . 512
Figure 174. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Figure 175. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . . 513
Figure 176. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Figure 177. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
Figure 178. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
Figure 179. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Figure 180. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
Figure 181. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Figure 182. I2C1/3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
Figure 183. I2C2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
Figure 184. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Figure 185. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
Figure 186. I2C initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
Figure 187. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Figure 188. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
Figure 189. Slave initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603
Figure 190. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0. . . . . . . . . . . . . . . . 605
Figure 191. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1. . . . . . . . . . . . . . . . 606
Figure 192. Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Figure 193. Transfer sequence flow for slave receiver with NOSTRETCH = 0 . . . . . . . . . . . . . . . . . 608
Figure 194. Transfer sequence flow for slave receiver with NOSTRETCH = 1 . . . . . . . . . . . . . . . . . 609
Figure 195. Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
Figure 196. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Figure 197. Master initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

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Figure 198. 10-bit address read access with HEAD10R = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

Figure 199. 10-bit address read access with HEAD10R = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Figure 200. Transfer sequence flow for I2C master transmitter for N≤255 bytes . . . . . . . . . . . . . . . . 615
Figure 201. Transfer sequence flow for I2C master transmitter for N>255 bytes . . . . . . . . . . . . . . . . 616
Figure 202. Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
Figure 203. Transfer sequence flow for I2C master receiver for N≤255 bytes . . . . . . . . . . . . . . . . . . 619
Figure 204. Transfer sequence flow for I2C master receiver for N >255 bytes . . . . . . . . . . . . . . . . . . 620
Figure 205. Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
Figure 206. Timeout intervals for tLOW:SEXT, tLOW:MEXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
Figure 207. Transfer sequence flow for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . . . . . 629
Figure 208. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . . 630
Figure 209. Transfer sequence flow for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . . . . . . 631
Figure 210. Bus transfer diagrams for SMBus slave receiver (SBC=1). . . . . . . . . . . . . . . . . . . . . . . . 632
Figure 211. Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Figure 212. Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Figure 213. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Figure 214. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
Figure 215. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
Figure 216. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
Figure 217. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
Figure 218. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
Figure 219. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
Figure 220. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678
Figure 221. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679
Figure 222. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 682
Figure 223. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 683
Figure 224. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
Figure 225. USART data clock timing diagram (M bits = 00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
Figure 226. USART data clock timing diagram (M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Figure 227. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
Figure 228. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Figure 229. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
Figure 230. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
Figure 231. IrDA data modulation (3/16) -Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
Figure 232. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Figure 233. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
Figure 234. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
Figure 235. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Figure 236. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
Figure 237. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
Figure 238. LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
Figure 239. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
Figure 240. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
Figure 241. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
Figure 242. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
Figure 243. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
Figure 244. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
Figure 245. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
Figure 246. Hardware flow control between 2 LPUARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
Figure 247. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
Figure 248. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Figure 249. LPUART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752

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Figure 250. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770

Figure 251. Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
Figure 252. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
Figure 253. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
Figure 254. Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
Figure 255. Multi-master application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Figure 256. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
Figure 257. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
Figure 258. TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0,
RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
Figure 259. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0,
RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
Figure 260. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
Figure 261. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
Figure 262. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
Figure 263. I2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
Figure 264. Full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
Figure 265. I2S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . . . . . . . . . . . . . . 794
Figure 266. I2S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . . 794
Figure 267. Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
Figure 268. Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
Figure 269. I2S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . 795
Figure 270. Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 796
Figure 271. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 796
Figure 272. MSB justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
Figure 273. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 797
Figure 274. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 797
Figure 275. LSB justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
Figure 276. Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
Figure 277. Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
Figure 278. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 798
Figure 279. Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 799
Figure 280. PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
Figure 281. PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 799
Figure 282. Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
Figure 283. I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
Figure 284. Block diagram of STM32L0x1 MCU and Cortex®-M0+-level debug support . . . . . . . . . . 818

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1 Documentation conventions

1.1 General information

The STM32L0x1 devices have an Arm®(a) Cortex®-M0+ core.

1.2 List of abbreviations for registers

The following abbreviations(b) are used in register descriptions:

read/write (rw) Software can read and write to this bit.

read-only (r) Software can only read this bit.
write-only (w) Software can only write to this bit. Reading this bit returns the reset value.
read/clear write0 (rc_w0) Software can read as well as clear this bit by writing 0. Writing 1 has no
effect on the bit value.
read/clear write1 (rc_w1) Software can read as well as clear this bit by writing 1. Writing 0 has no
effect on the bit value.
read/clear write (rc_w) Software can read as well as clear this bit by writing to the register. The
value written to this bit is not important.
read/clear by read (rc_r) Software can read this bit. Reading this bit automatically clears it to 0.
Writing this bit has no effect on the bit value.
read/set by read (rs_r) Software can read this bit. Reading this bit automatically sets it to 1.
Writing this bit has no effect on the bit value.
read/set (rs) Software can read as well as set this bit. Writing 0 has no effect on the bit
value.
read/write once (rwo) Software can only write once to this bit and can also read it at any time.
Only a reset can return the bit to its reset value.
toggle (t) The software can toggle this bit by writing 1. Writing 0 has no effect.
read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on
the bit value.
Reserved (Res.) Reserved bit, must be kept at reset value.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of
them may not be used in the current document.

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1.3 Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
• Sector: 32 pages write protection granularity in the Code area
• Page: 32 words for Code and System Memory areas, 1 word for Data, Factory Option
and User Option areas
• Word: data of 32-bit length.
• Half-word: data of 16-bit length.
• Byte: data of 8-bit length.
• IAP (in-application programming): IAP is the ability to re-program the Flash memory
of a microcontroller while the user program is running.
• ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.
• Option bytes: product configuration bits stored in the Flash memory.
• OBL: option byte loader.
• AHB: advanced high-performance bus.
• NVM: non-volatile memory.
• ECC: error code correction.
• DMA: direct memory access.
• MIF: NVM interface.
• PCROP: proprietary code readout protection.

1.4 Availability of peripherals

For availability of peripherals and their number across all sales types, refer to the particular
device datasheet.

1.5 Product category definition

Table 1 gives an overview of memory density versus product line.
The present reference manual describes the superset of features for each product line,
Refer to Table 2 for the list of features per category.

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Table 1. STM32L0x1 memory density

Memory density Category 1 Category 2 Category 3 Category 5

STM32L011x
8 Kbytes - - -
STM32L021x (AES)
STM32L011x STM32L031x
16 Kbytes - -
STM32L021x (AES) STM32L041x (AES)
STM32L031x
32 Kbytes - STM32L051x -
STM32L041x (AES)
64 Kbytes - - STM32L051x STM32L071x
STM32L071x
128 Kbytes - - -
STM32L081x (AES)
STM32L071x
192 Kbytes - - -
STM32L081x (AES)

Table 2. Overview of features per category

Feature Category 1 Category 2 Category 3 Category 5

MPU - - full-featured full-featured

full- full-
full-featured,
NVM featured, featured, full-featured
single bank
single bank single bank
Cyclic redundancy check calculation unit (CRC) full-featured full-featured full-featured full-featured
Firewall (FW) - - full-featured full-featured
Power control (PWR) full-featured full-featured full-featured full-featured
HSE supports
Reset and clock control (RCC) bypass only, no full-featured full-featured full-featured
CSS on HSE
GPIOA full-featured full-featured full-featured full-featured
[0:9],
BOOT0/PB9
GPIOB full-featured full-featured full-featured
sharing the
same pin
GPIOC [14:15] [0][13:15] full-featured full-featured
GPIOD - - [2] full-featured
GPIOE - - - full-featured
GPIOH - [0:1] [0:1] [0:1][9:10]
System configuration controller (SYSCFG) full-featured full-featured full-featured full-featured
Direct memory access controller (DMA1) full-featured full-featured full-featured full-featured
Nested vectored interrupt controller (NVIC) full-featured full-featured full-featured full-featured
Extended interrupt and event controller (EXTI) full-featured full-featured full-featured full-featured
Analog-to-digital converter (ADC1) full-featured full-featured full-featured full-featured

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Documentation conventions RM0377

Table 2. Overview of features per category (continued)

Feature Category 1 Category 2 Category 3 Category 5

Comparator (COMP1) full-featured full-featured full-featured full-featured

Comparator (COMP2) full-featured full-featured full-featured full-featured
Advanced encryption standard hardware accelerator
full-featured full-featured - full-featured
(AES)
General-purpose timers (TIM2) full-featured full-featured full-featured full-featured
General-purpose timers (TIM3) - - - full-featured
General-purpose timers (TIM21) full-featured full-featured full-featured full-featured
General-purpose timers (TIM22) - full-featured full-featured full-featured
Basic timers (TIM6) - - full-featured full-featured
Basic timers (TIM7) - - - full-featured
Low power timer (LPTIM1) full-featured full-featured full-featured full-featured
Independent watchdog (IWDG) full-featured full-featured full-featured full-featured
System window watchdog (WWDG) full-featured full-featured full-featured full-featured
Real-time clock (RTC) full-featured full-featured full-featured full-featured
Inter-integrated circuit (I2C1) interface full-featured full-featured full-featured full-featured
Inter-integrated circuit (I2C2) interface - - full-featured full-featured
Inter-integrated circuit (I2C3) interface - - - full-featured
Universal synchronous asynchronous receiver
- - full-featured full-featured
transmitter (USART1)
no synchronous
mode,
no LIN mode,
Universal synchronous asynchronous receiver no dual clock,
full-featured full-featured full-featured
transmitter (USART2) no receiver
timeout,
no ModBus,
no autobaudrate
Universal synchronous asynchronous receiver
- - - full-featured
transmitter (USART4)
Universal synchronous asynchronous receiver
- - - full-featured
transmitter (USART5)
Low-power universal asynchronous receiver transmitter
full-featured full-featured full-featured full-featured
(LPUART1)
Serial peripheral interface(SPI1) full-featured full-featured full-featured full-featured
Serial peripheral interface/ inter-IC sound (SPI2/I2S2) - - full-featured full-featured
Debug support (DBG) full-featured full-featured full-featured full-featured
Device electronic signature full-featured full-featured full-featured full-featured

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RM0377 System and memory overview

2 System and memory overview

2.1 System architecture

The main system consists of:
• Two masters:
– Cortex®-M0+ core (AHB-lite bus)
– GP-DMA (general-purpose DMA)
• Three slaves:
– Internal SRAM
– Internal Non-volatile memory
– AHB to APB, which connects all the APB peripherals
These are interconnected using a multilayer AHB bus architecture as shown in Figure 1:

Figure 1. System architecture

MIF
Memory interface NVM memory
GPIO ports Cortex
IOPORT System bus
A,B,C,D,E,H M0+
SRAM

Busmatrix
DMA
Controller DMA
(Channels
1 to 7)
SYSCFG
FIREWALL
PWR
EXTI
AHB2APB ADC
APB buses
AHB bus

Bridges COMP1/2
TIM2/3/6/7/21/22
Reset and LPTIM1
clock IWDG
controller WWDG
(RCC) RTC
DBGMCU
CRC I2C1/2/3
USART1/2/3/4/LPUART1
SPI1/2

DMA request
MS34749V2

1. Refer to Table 1: STM32L0x1 memory density, to Table 2: Overview of features per category and to the device datasheets
for the GPIO ports and peripherals available on your device.

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2.1.1 S0: Cortex®-bus

This bus connects the DCode/ICode bus of the Cortex®-M0+ core to the BusMatrix. This
bus is used by the core to fetch instructions, get data and access the AHB/APB resources.

2.1.2 S1: DMA-bus

This bus connects the AHB master interface of the DMA to the BusMatrix which manages
the access of the different masters to Flash memory and data EEPROM, the SRAM and the
AHB/APB peripherals.

2.1.3 BusMatrix
The BusMatrix manages the access arbitration between masters. The arbitration uses a
Round Robin algorithm. The BusMatrix is composed of two masters (CPU, DMA) and three
slaves (NVM interface, SRAM, AHB2APB1/2 bridges).

AHB/APB bridges
The AHB/APB bridge provide full synchronous connections between the AHB and the 2
APB buses. APB1 and APB2 operate at a maximum frequency of 32 MHz.
Refer to Section 2.2.2: Memory map and register boundary addresses on page 52 for the
address mapping of the peripherals connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM and MIF).
Before using a peripheral you have to enable its clock in the RCC_AHBENR,
RCC_APB2ENR, RCC_APB1ENR or RCC_IOPENR register.
Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

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2.2 Memory organization

2.2.1 Introduction
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
The addressable memory space is divided into eight main blocks, of 512 Mbytes each.

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2.2.2 Memory map and register boundary addresses

Figure 2. Memory map

0xFFFF FFFF

7 0x5000 1FFF IOPORT

0xE010 0000
Cortex-M0+ 0x5000 0000
peripherals
0xE000 0000

reserved
6

0xC000 0000
0x4002 63FF

5 AHB
0x4002 0000

0xA000 0000 reserved

0x4001 8000
4 0x1FFF FFFF
Option bytes APB2
0x8000 0000 0x4001 0000
System
memory reserved
3 0x4000 8000

APB1
0x6000 0000
0x4000 0000

2 reserved

0x4000 0000 Peripherals

1 Flash system
memory
0x2000 0000 SRAM 0x0800 0000

reserved
CODE
0 Flash, system
memory or
0x0000 0000 SRAM,
depending on
BOOT
configuration
0x0000 0000
Reserved

MS34761V2

All the memory map areas that are not allocated to on-chip memories and peripherals are
considered “Reserved”. For the detailed mapping of available memory and register areas,
refer to the following table.

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RM0377

The following table gives the boundary addresses of the peripherals available in the
devices.

Table 3. STM32L0x1 peripheral register boundary addresses(1)

Bus Boundary address Size (bytes) Peripheral Peripheral register map

Section 8.4.12: GPIO register

0X5000 1C00 - 0X5000 1FFF 1K GPIOH
map
0X5000 1400 - 0X5000 1BFF 2K Reserved -
Section 8.4.12: GPIO register
0X5000 1000 - 0X5000 13FF 1K GPIOE
map
Section 8.4.12: GPIO register
0X5000 0C00 - 0X5000 0FFF 1K GPIOD
IOPORT map
Section 8.4.12: GPIO register
0X5000 0800 - 0X5000 0BFF 1K GPIO C
map
Section 8.4.12: GPIO register
0X5000 0400 - 0X5000 07FF 1K GPIOB
map
Section 8.4.12: GPIO register
0X5000 0000 - 0X5000 03FF 1K GPIOA
map
0X4002 6400 - 0X4002 FFFF 49 K Reserved -
AES (Cat. 1, 2
Section 15.7.13: AES register
0X4002 6000 - 0X4002 63FF 1K and 5 with AES
map
only)
0X4002 5400 - 0X4002 5FFF 3K Reserved -
0X4002 4400 - 0X4002 53FF 3K Reserved -
0X4002 3400 - 0X4002 3FFF 3K Reserved -
0X4002 3000 - 0X4002 33FF 1K CRC Section 4.4.6: CRC register map
0X4002 2400 - 0X4002 2FFF 3K Reserved -
Section 3.7.11: Flash register
AHB 0X4002 2000 - 0X4002 23FF 1K FLASH
map
0X4002 1400 - 0X4002 1FFF 3K Reserved -
Section 7.3.21: RCC register
0X4002 1000 - 0X4002 13FF 1K RCC
map
0X4002 0400 - 0X4002 0FFF 3K Reserved -
Section 10.6.8: DMA register
0X4002 0000 - 0X4002 03FF 1K DMA1
map

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Table 3. STM32L0x1 peripheral register boundary addresses(1) (continued)

Bus Boundary address Size (bytes) Peripheral Peripheral register map

0X4001 5C00 - 0X4001 FFFF 42 K Reserved -

Section 27.10: DBG register
0X4001 5800 - 0X4001 5BFF 1K DBG
map
0X4001 3C00 - 0X4001 57FF 7K Reserved -
Section 24.8.12: USART
0X4001 3800 - 0X4001 3BFF 1K USART1
register map
0X4001 3400 - 0X4001 37FF 1K Reserved -
Section 26.7.10: SPI register
0X4001 3000 - 0X4001 33FF 1K SPI1
map
0X4001 2800 - 0X4001 2FFF 2K Reserved -
Section 13.12: ADC register
0X4001 2400 - 0X4001 27FF 1K ADC1
map

APB2 0X4001 2000 - 0X4001 23FF 1K Reserved -

Section 5.4.8: Firewall register
0X4001 1C00 - 0X4001 1FFF 1K Firewall
map
0X4001 1800 - 0X4001 1BFF 1K Reserved -
Section 17.4.16: TIM21/22
0X4001 1400 - 0X4001 17FF 1K TIM22
register map
0X4001 0C000 - 0X4001 13FF 2K Reserved -
Section 17.4.16: TIM21/22
0X4001 0800 - 0X4001 0BFF 1K TIM21
register map
Section 12.5.7: EXTI register
0X4001 0400 - 0X4001 07FF 1K EXTI
map
Section 9.2.8: SYSCFG register
SYSCFG,
0X4001 0000 - 0X4001 03FF 1K map, Section 14.5.3: COMP
COMP
register map
0X4000 8000 - 0X4000 FFFF 32 K Reserved -
Section 19.7.9: LPTIM register
0X4000 7C00 - 0X4000 7FFF 1K LPTIM1
map
Section 23.7.12: I2C register
0X4000 7800 - 0X4000 7BFF 1K I2C3
map
Section 6.4.3: PWR register
0X4000 7000 - 0X4000 73FF 1K PWR
map
APB1 0X4000 5C00 - 0x4000 6FFF 1K Reserved -

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Table 3. STM32L0x1 peripheral register boundary addresses(1) (continued)

Bus Boundary address Size (bytes) Peripheral Peripheral register map

Section 23.7.12: I2C register

0X4000 5800 - 0X4000 5BFF 1K I2C2
map
Section 23.7.12: I2C register
0X4000 5400 - 0X4000 57FF 1K I2C1
map
Section 24.8.12: USART
0X4000 5000 - 0X4000 53FF 1K USART5
register map
Section 24.8.12: USART
0X4000 4C00 - 0X4000 4FFF 1K USART4
register map
Section 25.7.10: LPUART
0X4000 4800 - 0X4000 4BFF 1K LPUART1
register map
Section 24.8.12: USART
0X4000 4400 - 0X4000 47FF 1K USART2
register map
0X4000 3C000 - 0X4000 43FF 2K Reserved -
Section 26.7.10: SPI register
0X4000 3800 - 0X4000 3BFF 1K SPI2
map
0X4000 3400 - 0X4000 37FF 1K Reserved -
APB1
Section 20.4.6: IWDG register
0X4000 3000 - 0X4000 33FF 1K IWDG
map
Section 21.5.4: WWDG register
0X4000 2C00 - 0X4000 2FFF 1K WWDG
map
RTC + Section 22.7.21: RTC register
0X4000 2800 - 0X4000 2BFF 1K
BKP_REG map
0X4000 1800 - 0X4000 27FF 3K Reserved -
Section 18.4.9: TIM6/7 register
0X4000 1400 - 0X4000 17FF 1K TIMER7
map
Section 18.4.9: TIM6/7 register
0X4000 1000 - 0X4000 13FF 1K TIMER6
map
0X4000 0800 - 0X4000 0FFF 1K Reserved -
0X4000 0400 - 0X4000 07FF 1K TIMER3 Section 16.5: TIMx register map
0X4000 0000 - 0X4000 03FF 1K TIMER2 Section 16.5: TIMx register map
0X2000 2000 - 0X3FFF FFFF ~524 M Reserved -
SRAM
0X2000 0000 - 0X2000 4FFF up to 20 K SRAM -

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Table 3. STM32L0x1 peripheral register boundary addresses(1) (continued)

Bus Boundary address Size (bytes) Peripheral Peripheral register map

Flash program
0X0800 0000 - 0X0802 FFFF up to 192 K -
memory

0x0808 0000 - 0x0808 17FF up to 6 K Data EEPROM -

System
NVM 0x1FF0 0000 - 0x1FF0 1FFF 8K -
memory
Factory option
0x1FF8 0020 - 0x1FF8 007F 96 -
bytes
User option
0x1FF8 0000 - 0x1FF8 001F 32 -
bytes
1. Refer to Table 1: STM32L0x1 memory density, to Table 2: Overview of features per category and to the device datasheets
for the GPIO ports and peripherals available on your device. The memory area corresponding to unavailable GPIO ports or
peripherals are reserved.

2.3 Embedded SRAM

STM32L0x1 devices feature up to 20 Kbytes of static SRAM.
This RAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). This
memory can be addressed at maximum system clock frequency without wait state and thus
by both CPU and DMA.
The SRAM start address is 0x2000 0000.
The CPU can access the SRAM from address 0x0000 0000 when physical remap is
selected through boot pin or MEM_MODE (see Section 9.2.1: SYSCFG memory remap
register (SYSCFG_CFGR1)).

2.4 Boot configuration

In the STM32L0x1, three different boot modes can be selected through the BOOT0 pin and
boot configuration bits in the User option byte, as shown in the following table.

Table 4. Boot modes(1)

Boot mode configuration
Aliasing
nBOOT1 BOOT0 nBOOT_SEL nBOOT0
bit pin bit bit

Flash program memory is selected as boot

X 0 0 X
area
1 1 0 X System memory is selected as boot area
0 1 0 X Embedded SRAM is selected as boot area
Flash program memory is selected as boot
X X 1 1
area
1 X 1 0 System memory is selected as boot area
0 X 1 0 Embedded SRAM is selected as boot area

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1. Grayed options are available on category 1 devices only.

The boot mode configuration is latched on the 2nd rising edge of SYSCLK after reset. For
category 1 devices, the value present on BOOT0 pin is latched on NRST rising edge. It is up
to the user to set nBOOT1 and BOOT0 to select the required boot mode.
The boot mode configuration is also re-sampled when exiting from Standby mode, except
for category 1 devices where BOOT0 pin is latched on NRST rising edge. Consequently the
boot mode configuration must not be modified in Standby mode (except for category 1
devices). After this startup delay has elapsed, the CPU fetches the top-of-stack value from
address 0x0000 0000, then starts code execution from the boot memory at 0x0000 0004.
Depending on the selected boot mode, Flash program memory, system memory or SRAM is
accessible as follows:
• Boot from Flash program memory: the Flash program memory is aliased in the boot
memory space (0x0000 0000), but still accessible from its original memory space
(0x0800 0000). In other words, the Flash memory contents can be accessed starting
from address 0x0000 0000 or 0x0800 0000.
• Boot from system memory: the system memory is aliased in the boot memory space
(0x0000 0000), but still accessible from its original memory space (0x1FF0 0000).
• Boot from the embedded SRAM: the SRAM is aliased in the boot memory space
(0x0000 0000), but it is still accessible from its original memory space (0x2000 0000).

BOOT0/GPIO pin sharing (category 1 devices only)

On category 1 devices, the BOOT0 pin is shared with a GPIO pin. The pin state is latched
on NRST rising edge as BOOT0 state. The pin logic level can then be read as an input value
on the shared GPIO pin. This pin feature specific input voltage characteristics (refer to the
corresponding datasheets for details).

Empty check (category 1 devices only)

On category 1 devices, an internal empty check flag is implemented to allow easy
programming of virgin devices by the bootloader. This flag is used when BOOT0 pin is
configured to select Flash program memory as target boot area. When this flag is set, the
device is considered as unprogrammed and the system memory (bootloader) is selected as
boot area instead of the Flash program memory to allow the application to program the
Flash memory.
The empty check flag is updated only when the option bytes are loaded: it is set when the
content of address 0x0800 0000 is read as 0x0000 0000 and cleared otherwise. As a result,
only a power-on reset or setting OBL_LAUNCH bit in FLASH_CR register can clear this flag
after programming a virgin device to execute user code after system reset.
Note: If the device is programmed for the first time but the option bytes are not reloaded, the
system memory will still be selected as boot area after system reset. In this case, the
bootloader code switches the boot memory mapping to Flash program memory and
performs a jump to the user code it hosts.

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Bank swapping (category 5 devices only)

For devices featuring two banks, the bank swapping mechanism allows the CPU to point
either to bank1 or to bank 2 in the boot memory space (0x0000 0000). Either Flash program
and data EEPROM address are changed (see Table 10: NVM organization for UFB = 0
(128 Kbyte category 5 devices), Table 12: NVM organization for UFB = 0 (64 Kbyte category
5 devices)).

Physical remap
Once the boot pin and bit are selected, the application software can modify the memory
accessible in the code area. This modification is performed by programming the
MEM_MODE bits in the SYSCFG memory remap register (SYSCFG_CFGR1).

Embedded bootloader
The embedded bootloader is located in the System memory, programmed by ST during
production. It is used to reprogram the Flash memory using one of the following serial
interfaces:
• For category 1 devices: USART2 or SPI1.
• For category 2 devices: USART2 or SPI1.
• For category 3 devices: USART1, USART2, SPI1 or SPI2
• For category 5 devices: USART1, USART2, SPI1, SPI2, I2C1 or I2C2.
For details concerning the bootloader serial interface corresponding I/O, refer to your device
datasheet.
For further details on STM32 bootloader, please refer to AN2606.

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RM0377 Flash program memory and data EEPROM (FLASH)

3 Flash program memory and data EEPROM (FLASH)

3.1 Introduction
The non-volatile memory (NVM) is composed of:
• Up to 192 Kbytes of Flash program memory. This area is used to store the application
code.
• Up to 6 Kbytes of data EEPROM
• An information block:
– Up to 8 Kbytes of System memory
– Up to 8x4 bytes of user Option bytes
– Up to 96 bytes of factory Option bytes

3.2 NVM main features

The NVM interface features:
• Read interface organized by word, half-word or byte in every area
• Programming in the Flash memory performed by word or half-page
• Programming in the Option bytes area performed by word
• Programming in the data EEPROM performed by word, half-word or byte (granularity of
the data EEPROM is one word, erase/write endurance cycles are linked to one word
granularity)
• Erase operation performed by page (in Flash memory, data EEPROM and Option
bytes)
• Option byte Loader
• ECC (Error Correction Code): 6 bits stored for every word to recognize and correct just
one error
• Mass erase operation
• Read / Write protection
• PCROP protection
• Low-power mode
• Category 5 devices only:
– Dual-bank memory with read-while-write
– Dual-bank boot capability allowing to boot either from Bank 1 or Bank 2 at startup
– Bank swapping capability.

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3.3 NVM functional description

3.3.1 NVM organization

The NVM is organized as 32-bit memory cells that can be used to store code, data, boot
code or Option bytes.
The memory array is divided into pages. A page is composed of 32 words (or 128 bytes) in
Flash program memory and System memory, and 1 single word (or 4 bytes) in data
EEPROM and Option bytes areas (user and factory). The erase/write endurance cycles are
linked to one page granularity for Flash program memory and one single word granularity for
data EEPROM.
A Flash sector is made of 32 pages (or 4 Kbytes). The sector is the granularity of the write
protection.

Table 5. NVM organization (category 1 devices)

Size
NVM NVM addresses Name Description
(bytes)

0x0800 0000 - 0x0800 007F 128 bytes Page 0

0x0800 0080 - 0x0800 00FF 128 bytes Page 1
sector 0
- - -
0x0800 0F80 - 0x0800 0FFF 128 bytes Page 31

Flash program . . . .
. . . .
memory . . . .

0x0800 3000 - 0x0800 307F 128 bytes Page 96

0x0800 3080 - 0x0800 30FF 128 bytes Page 97
sector 3
- - -
0x0800 3F80 - 0x0800 3FFF 128 bytes Page 127
Data EEPROM 0x0808 0000 - 0x0808 01FF 512 bytes Data EEPROM
0x1FF0 0000 - 0x1FF0 0FFF 4 Kbytes System memory
Information block 0x1FF8 0020 - 0x1FF8 007F 96 bytes Factory Options
0x1FF8 0000 - 0x1FF8 001F 32 bytes User Option bytes

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Table 6. NVM organization (category 2 devices)

Size
NVM NVM addresses Name Description
(bytes)

0x0800 0000 - 0x0800 007F 128 bytes Page 0

0x0800 0080 - 0x0800 00FF 128 bytes Page 1
sector 0
- - -
0x0800 0F80 - 0x0800 0FFF 128 bytes Page 31

Flash program . . . .
. . . .
memory . . . .

0x0800 7000 - 0x0800 707F 128 bytes Page 224

0x0800 7080 - 0x0800 70FF 128 bytes Page 225
sector 7
- - -
0x0800 7F80 - 0x0800 7FFF 128 bytes Page 255
Data EEPROM 0x0808 0000 - 0x0808 03FF 1 Kbytes Data EEPROM
0x1FF0 0000 - 0x1FF0 0FFF 4 Kbytes System memory
Information block 0x1FF8 0020 - 0x1FF8 007F 96 bytes Factory Options
0x1FF8 0000 - 0x1FF8 001F 32 bytes User Option bytes

Table 7. NVM organization (category 3 devices)

Size
NVM NVM addresses Name Description
(bytes)

0x0800 0000 - 0x0800 007F 128 bytes Page 0

0x0800 0080 - 0x0800 00FF 128 bytes Page 1
sector 0
- - -
0x0800 0F80 - 0x0800 0FFF 128 bytes Page 31
. . . .
. . . .
. . . .

0x0800 7000 - 0x0800 707F 128 bytes Page 224

Flash program 0x0800 7080 - 0x0800 70FF 128 bytes Page 225
sector 7
memory(1) - - -
0x0800 7F80 - 0x0800 7FFF 128 bytes Page 255
. . . .
. . . .
. . . .

0x0800 F000 - 0x0800 F07F 128 bytes Page 480

0x0800 F080 - 0x0800 F0FF 128 bytes Page 481
sector 15
- - -
0x0800 FF80 - 0x0800 FFFF 128 bytes Page 511
Data EEPROM 0x0808 0000 - 0x0808 07FF 2 Kbytes - Data EEPROM

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Table 7. NVM organization (category 3 devices) (continued)

Size
NVM NVM addresses Name Description
(bytes)

0x1FF0 0000 - 0x1FF0 0FFF 4 Kbytes - System memory

Information block 0x1FF8 0020 - 0x1FF8 007F 96 bytes - Factory Options
0x1FF8 0000 - 0x1FF8 001F 32 bytes - User Option bytes
1. For 32 Kbyte category 3 devices, the Flash program memory is divided into 256 pages of 128 bytes each.

Table 8. NVM organization for UFB = 0 (192 Kbyte category 5 devices)

Size
NVM NVM addresses Name Description
(bytes)

0x0800 0000 - 0x0800 007F 128 bytes Page 0

0x0800 0080 - 0x0800 00FF 128 bytes Page 1

sector 0
- - -
0x0800 0F80 - 0x0800 0FFF 128 bytes Page 31

. . . .
. . . .
. . . .

0x0800 7000 - 0x0800 707F 128 bytes Page 224

Bank 1
0x0800 7080 - 0x0800 70FF 128 bytes Page 225
sector 7
- - -

0x0800 7F80 - 0x0800 7FFF 128 bytes Page 255

Flash program . . . .
memory . . . .
. . . .

- - -
0x0801 7F80- 0x0801 7FFF 128 bytes Page 767 sector 23

0x0801 8000 - 0x0801 807F 128 bytes Page 768 sector 24

. . . .
. . . .
. . . .

0x0802 F000 - 0x0802 F07F 128 bytes Page 1504 Bank 2

0x0802 F080 - 0x0802 F0FF 128 bytes Page 1505

sector 47
- - -

0x0802 FF80 - 0x0802 FFFF 128 bytes Page 1535

0x0808 0000 - 0x0808 0BFF - Data EEPROM Bank 1

Data EEPROM 6 Kbytes
0x0808 0C00 - 0x0808 17FF - Data EEPROM Bank 2

0x1FF0 0000 - 0x1FF0 1FFF 8 Kbytes - System memory

Information block 0x1FF8 0020 - 0x1FF8 007F 96 bytes - Factory Options

0x1FF8 0000 - 0x1FF8 001F 32 bytes - User Option bytes

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Table 9. Flash memory and data EEPROM remapping

(192 Kbyte category 5 devices)
NVM addresses Remapped addresses

NVM Description MEM_MODE = 0, MEM_MODE = 0, MEM_MODE = 0, MEM_MODE = 0,

BOOT0= 0 and BOOT0= 0 and BOOT0= 0 and BOOT0= 0 and
UFB = 0 UFB = 1 UFB = 0 UFB = 1

0x0800 0000 - 0x0801 8000 - 0x0000 0000 - 0x0001 8000 -

Flash Bank 1
0x0801 7FFF 0x0802 FFFF 0x0001 7FFF 0x0002 FFFF
program
memory 0x0801 8000 - 0x08000 0000 - 0x0001 8000 - 0x0000 0000 -
Bank 2
0x0802 FFFF 0x0801 7FFF 0x0002 FFFF 0x0001 7FFF

0x0808 0000 - 0x0808 0C00 - 0x0008 0000 - 0x0008 0C00 -

Bank 1
Data 0x0808 0BFF 0x0808 17FF 0x0008 0BFF 0x0008 17FF
EEPROM 0x0808 0C00 - 0x0808 0000 - 0x0008 0C00 - 0x0008 0000 -
Bank 2
0x0808 17FF 0x0008 0BFF 0x0008 17FF 0x0008 0BFF

Table 10. NVM organization for UFB = 0 (128 Kbyte category 5 devices)
NVM NVM addresses Size (bytes) Name Description

0x0800 0000 - 0x0800 007F 128 bytes Page 0

0x0800 0080 - 0x0800 00FF 128 bytes Page 1

sector 0
- - -

0x0800 0F80 - 0x0800 0FFF 128 bytes Page 31

. . . .
. . . .
. . . .

0x0800 7000 - 0x0800 707F 128 bytes Page 224 Bank 1

0x0800 7080 - 0x0800 70FF 128 bytes Page 225

sector 7
- - -

0x0800 7F80 - 0x0800 7FFF 128 bytes Page 255

Flash program
memory . . . .
. . . .
. . . .

0x0800 FF80- 0x0800 FFFF 128 bytes Page 511 sector 15

0x0801 0000 - 0x0801 007F 128 bytes Page 512 sector 16

. . . .
. . . .
. . . .

0x0801 F000 - 0x0801 F07F Page 992 Bank 2

sector 31
- - -
0x0801 FF80 - 0x0801 FFFF 128 bytes Page 1023

0x0808 0000 - 0x0808 0BFF - Data EEPROM Bank 1

Data EEPROM 6 Kbytes
0x0808 0C00 - 0x0808 17FF - Data EEPROM Bank 2

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Table 10. NVM organization for UFB = 0 (128 Kbyte category 5 devices) (continued)
NVM NVM addresses Size (bytes) Name Description

0x1FF0 0000 - 0x1FF0 1FFF 8 Kbytes - System memory

Information block 0x1FF8 0020 - 0x1FF8 007F 96 bytes - Factory Options

0x1FF8 0000 - 0x1FF8 001F 32 bytes User Option bytes

Table 11. Flash memory and data EEPROM remapping (128 Kbyte category 5 devices)
NVM addresses Remapped addresses

NVM Description MEM_MODE = 0, MEM_MODE = 0, MEM_MODE = 0, MEM_MODE = 0,

BOOT0= 0 and BOOT0= 0 and BOOT0= 0 and BOOT0= 0 and
UFB = 0 UFB = 1 UFB = 0 UFB = 1

0x0800 0000 - 0x0801 0000 - 0x0000 0000 - 0x0001 0000 -

Bank 1
Flash program 0x0800 FFFF 0x0801 FFFF 0x0000 FFFF 0x0001 FFFF
memory 0x0801 0000 - 0x0800 0000 - 0x0001 0000 - 0x0000 0000 -
Bank 2
0x0801 FFFF 0x0800 FFFF 0x0001 FFFF 0x0000 FFFF
0x0808 0000 - 0x0808 0C00 - 0x0008 0000 - 0x0008 0C00 -
Bank 1
0x0808 0BFF 0x0808 17FF 0x0008 0BFF 0x0008 17FF
Data EEPROM
0x0808 0C00 - 0x0808 0000 - 0x0008 0C00 - 0x0008 0000 -
Bank 2
0x0808 17FF 0x0808 0BFF 0x0008 17FF 0x0008 0BFF

Table 12. NVM organization for UFB = 0 (64 Kbyte category 5 devices)(1)
NVM NVM addresses Size (bytes) Name Description

0x0800 0000 - 0x0800 007F 128 bytes Page 0

0x0800 0080 - 0x0800 00FF 128 bytes Page 1

sector 0
- - -

0x0800 0F80 - 0x0800 0FFF 128 bytes Page 31

. . . .
Flash program
. . . . Bank 1
memory . . . .

0x0800 F000 - 0x0800 F07F 128 bytes Page 480

- - -
sector 15
- - -

0x0800 FF80 - 0x0800 FFFF 128 bytes Page 511

Data EEPROM 0x0808 0C00 - 0x0808 17FF 3 Kbytes - Data EEPROM Bank 2

0x1FF0 0000 - 0x1FF0 1FFF 8 Kbytes - System memory

Information block 0x1FF8 0020 - 0x1FF8 007F 96 bytes - Factory Options

0x1FF8 0000 - 0x1FF8 001F 32 bytes User Option bytes

1. Flash memory and data EEPROM remapping is not possible on 64 Kbyte category 5 devices.

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3.3.2 Dual-bank boot capability

Category 5 devices have two Flash memory banks: Bank 1 and Bank 2. They feature an
additional boot mechanism which allows booting either from Bank 2 or from Bank 1
depending on BFB2 bit status (bit 23 in FLASH_OPTR register).
• When the BFB2 bit is set and the boot pins are configured to boot from Flash memory
(BOOT0 = 0 and BOOT1 = x), the device maps the System memory at address 0. It
boots from the System memory after reset and Standby and executes (during
approximately 440 µs) the embedded bootloader code which implements the dual-
bank boot mechanism:
a) The System memory code first checks Bank 2. If it contains a valid code (see note
below), it sets the UFB bit in SYSCFG_CFGR1 register to map Bank 2 at address
0x0800 0000, jumps to the application code located in Bank 2, and leaves the
bootloader.
b) If the code located in Bank 2 is not valid, the System memory code checks Bank 1
code. If it is valid (see note below), it jumps to the application located in Bank 1
(UFB is kept at ‘0’ so that Bank 1 remains mapped at address 0x0800 0000).
c) If both Bank 2 and Bank 1 do not contain valid code (see note below), the normal
bootloader operations are executed when the protection level2 is disabled.
Otherwise, the System memory code jumps to Bank 1 regardless of its validity.
Refer to Table 13 for more details.
• When BFB2 bit is reset (default state), the dual-bank boot mechanism is not performed.
Note: The code is considered as valid when the first data located at the bank start address (which
should be the stack pointer) points to a valid address (stack top address).
For category 5 devices, the Flash memory Bank 1 and Bank 2, System memory or SRAM
can be selected as the boot area, as shown in Table 13 below.

Table 13. Boot pin and BFB2 bit configuration

Boot mode
selection
Protection BFB2
Boot mode Aliasing
level bit nBOOT1
BOOT0
option
pin
bit

User Flash memory Bank1 is selected as the

X 0 User Flash memory
boot area.
0
1 1 System memory Boot on System memory to execute bootloader.
0 1 Embedded SRAM Boot on Embedded SRAM
0 or 1 Boot on System memory to execute dual bank
X 0 System memory boot mechanism. If Bank 2 and Bank 1are not
valid, bootloader is executed for Flash update.
1
1 1 System memory Boot on System memory to execute bootloader.
0 1 Embedded SRAM Boot on Embedded SRAM.

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Table 13. Boot pin and BFB2 bit configuration (continued)

Boot mode
selection
Protection BFB2
Boot mode Aliasing
level bit nBOOT1
BOOT0
option
pin
bit

X 0 User Flash memory

User Flash memory Bank1 is selected as the
0 1 1 User Flash memory
boot area.
0 1 User Flash memory
2
X 0 System memory
Boot on System memory to execute dual bank
1 1 1 System memory boot mechanism. If Bank 2 isn’t valid, it jumps to
Bank 1.
0 1 System memory

When entering System memory, you can either execute the bootloader (for Flash update) or
execute Dual Bank Jump (see Table 13).
When protection level2 is enabled, the bootloader is never executed to perform a Flash
update.
When the conditions a, b, and c described below are fulfilled, it is equivalent to configuring
boot pins for System memory boot (BOOT0 = 1 and BOOT1 = 0). In this case when
protection level2 is disabled, normal bootloader operations are executed.
a) BFB2 bit is set.
b) Both banks do not contain valid code.
c) Boot pins configured as follows: BOOT0 = 0 and BOOT1 = x.
When the BFB2 bit is set, and Bank 2 and/or Bank 1 contain valid user application code, the
Dual Bank Boot is always performed (bootloader always jumps to the user code).
Consequently, if you have set the BFB2 bit (to boot from Bank 2) then, to be able to execute
the bootloader code for Flash update when protection level2 is disabled, you have to:
a) Set the BFB2 bit to 0, BOOT0 = 1 and BOOT1 = 0 or,
b) Program the content of address 0x0801 8000/0x0801 0000 (base address of
Bank2) and 0x0800 0000 (base address of Bank1) to 0x0.

3.3.3 Reading the NVM

Protocol to read
To read the NVM content, take any address from Section 3.3.1: NVM organization. The
clock of the memory interface must be running. (see MIFEN bit in Section 7.3.12: AHB
peripheral clock enable register (RCC_AHBENR)).
Depending on the clock frequency, a 0 or a 1 wait state can be necessary to read the NVM.
The user must set the correct number of wait states (LATENCY bit in the FLASH_ACR
register). No control is done to verify if the frequency or the power used is correct, with
respect to the number of wait states. A wrong number of wait states can generate wrong
read values (high frequency and 0 wait states) or a long time to execute a code (low
frequency with 1 wait state).

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You can read the NVM by word (4 bytes), half-word (2 bytes) or byte.
When the NVM features only one bank, it is not possible to read the NVM during a
write/erase operation. If a write/erase operation is ongoing, the reading will be in a wait state
until the write/erase operation completes, stalling the master that requested the read
operation, except when the address is read-protected. In this case, the error is sent to the
master by a hard fault or a memory interface flag; no stall is generated and no read is
waiting.
When two banks are available (category 5 devices), read operations from one bank can be
performed while write or erase operations are performed on the other bank.

Relation between CPU frequency/Operation mode/NVM read time

The device (and the NVM) can work at different power ranges. For every range, some
master clock frequencies can be set. Table 14 resumes the link between the power range
and the frequencies to ensure a correct time access to the NVM.

Table 14. Link between master clock power range and frequencies
Maximum frequency Maximum frequency
Name Power range
(with 1 wait state) (without wait states)

Range 1 1.65 V - 1.95 V 32 MHz 16 MHz

Range 2 1.35 V - 1.65 V 16 MHz 8 MHz
Range 3 1.05 V - 1.35 V 4.2 MHz 4.2 MHz

Table 15 shows the delays to read a word in the NVM. Comparing the complete time to read
a word (Ttotal) with the clock period, you can see that in Range 3 no wait state is necessary,
also with the maximum frequency (4.2 MHz) allowed by the device. Ttotal is the time that the
NVM needs to return a value, and not the complete time to read it (from memory to Core
through the memory interface); all remaining time is lost.

Table 15. Delays to memory access and number of wait states

Number of wait
Name Ttotal Frequency Period
state required

32 MHz 31.25 1
Range 1 46.1 ns
16 MHz 62.5 0
16 MHz 62.5 1
Range 2 86.8 ns
8 MHz 125 0
4 MHz 250 0
Range 3 184.6 ns
2 MHz 500 0

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Change the CPU Frequency

After reset, the clock used is the MSI (2.1 MHz) and 0 wait state is configured in the
FLASH_ACR register. The following software sequences have to be respected to tune the
number of wait states needed to access the NVM with the CPU frequency.
A CPU clock or a number of wait state configuration changes may take some time before
being effective. Checking the AHB prescaler factor and the clock source status values is a
way to ensure that the correct CPU clock frequency is the configured one. Similarly, the read
of FLASH_ACR is a way to ensure that the number of programmed wait states is effective.
Increasing the CPU frequency (in the same voltage range)
1. Program 1 wait state in LATENCY bit of FLASH_ACR register, if necessary.
2. Check that the new number of wait states is taken into account by reading the
FLASH_ACR register. When the number of wait states changes, the memory interface
modifies the way the read access is done to the NVM. The number of wait states
cannot be modified when a read operation is ongoing, so the memory interface waits
until no read is done on the NVM. If the master reads back the content of the
FLASH_ACR register, this reading is stopped (and also the master which requested
the reading) until the number of wait states is really changed. If the user does not read
back the register, the following access to the NVM may be done with 0 wait states,
even if the clock frequency has been increased, and consequently the values are
wrong.
3. Modify the CPU clock source and/or the AHB clock prescaler in the Reset & Clock
Controller (RCC).
4. Check that the new CPU clock source and/or the new CPU clock prescaler value is
taken into account by reading respectively the clock source status and/or the AHB
prescaler value in the Reset & Clock Controller (RCC). This check is important as some
clocks may take time to get available.
For code example, refer to A.2.1: Increasing the CPU frequency preparation sequence
code, A.2.3: Switch from PLL to HSI16 sequence code and A.2.4: Switch to PLL sequence
code.
Decreasing the CPU frequency (in the same voltage range)
1. Modify the CPU clock source and/or the AHB clock prescaler in the Reset & Clock
Controller (RCC).
2. Check that the new CPU clock source and/or the new CPU clock prescaler value is
taken into account by reading respectively the clock source status and/or the AHB
prescaler value in the Reset and Clock Controller (RCC).
3. Program 0 wait state in LATENCY bit of the FLASH_ACR register, if needed.
4. Check that the new number of wait states is taken into account by reading
FLASH_ACR. It is necessary to read back the register for the reasons explained in the
previous paragraph.

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Data buffering
In the NVM, six buffers can impact the performance (and in some conditions help to reduce
the power consumption) during read operations, both for fetch and data. The structure of
one buffer is shown on Figure 3.

Figure 3. Structure of one internal buffer

Address

Value

History

MS32395V1

Each buffer stores 3 different types of information: address, data and history. In a read
operation, if the address is found, the memory interface can return data without accessing
the NVM. Data in the buffer is 32 bit wide (even if the master only reads 8 or 16 bits), so that
a value can be returned whatever the size used in a previous reading. The history is used to
know if the content of a buffer is valid and to delete (with a new value) the older one.
The buffers are used to store the value received by the NVM during normal read operations,
and for speculative readings. Disabling the speculative reading makes that only the data
requested by masters is stored in buffers, if enabled (default). This can increase the
performance as no wait state is necessary if the value is already available in buffers, and
reduce the power consumption as the number of reads in memory is reduced and all
combinatorial paths from memory are stable.
The buffers are divided in groups to manage different tasks. The number of buffers in every
group can change starting from the configuration selected by the user (see Table 16). The
total number of buffers used is always 6 (if enabled). The history is always managed by
group.
The memory interface always searches if a particular address is available in all buffers
without checking the group of buffers and if the read is fetch or data.
At reset or after a write/erase operation that changes several addresses, all buffers are
empty and the history is set to EMPTY. After a program by word, half-word or byte, only the
buffer with the concerned address is cleaned.

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Table 16. Internal buffer management

Buffers for fetch Buffers for data
DISAB_BUF PREFTEN PRE_READ
Buffers for Buffers for Buffers for Buffers for Buffers for
jumps prefetch last value pre-read last value

1 - - 0 0 0 0 0
0 0 0 3 0 1 0 2
0 1 0 2 1 1 0 2
0 0 1 3 0 1 1 1
0 1 1 2 1 1 1 1

If a value in a buffer is not empty, the history shows the time elapsed between the moment it
has been read or written. The history is organized as a list of values from the latest to the
oldest one. At a given instant, only one buffer in a group can have a particular value of
history (except the empty value). Moving a buffer to the latest position, all other buffers in
the group move one step further, thus maintaining the order. The history is changed to the
latest position when the buffer is read (the master requests for the buffer content) or written
(with a new value from the NVM). The memory interface always writes the oldest buffer (or
one empty buffer, if any) of the right group when a new address is required in memory.
Three configuration bits of the FLASH_ACR register are used to manage the buffering:
• DISAB_BUF
Setting this bit disables all buffers. When this bit is 1, the prefetch or the pre-read
operations cannot be enabled and if, for example, the master requests the same
address twice, two readings are generated in the NVM.
• PRFTEN
Setting this bit to 1 (with DISAB_BUF to 0) enables the prefetch. When the memory
interface does not have any operation in progress, the address following the last
address fetched is read and stored in a buffer.
• PRE_READ
Setting this bit to 1 (with DISAB_BUF to 0) enables the pre-read. When the memory
interface does not have any operation in progress or prefetch to execute, the address
following the last data address is read and stored in a buffer.
Fetch and prefetch
A memory interface fetch is a read from the NVM to execute the operation that has been
read. The memory interface does not check the master who performs the read operation, or
the location it reads from, but it only verifies if the read operation is done to execute what
has been read. It means that a fetch can be performed:
• in all areas,
• with any size (16 or 32 bits).
The memory interface stores in the buffers:
• The address of jumps so that, in a loop, it is only necessary to access the NVM the first
time, because then the jump address is already available.
• The last read address so that, when performing a fetching on 16 bits, the other 16 bits
are already available.

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To manage the fetch, the memory interface uses 4 buffers: at reset (DISAB_BUF = 0,
PRFTEN = 0, PRE_READ = 0). 3 buffers are used to manage the jumps and 1 buffer to
store the last value fetched. With this configuration, the 4 buffers for fetch are organized in 2
groups with separate histories: the group for loops and the group for the last value fetched.
Setting the PRFTEN bit to 1 enables the prefetch. The prefetch is a speculative read in the
NVM, which is executed when no read is requested by masters, and where the memory
interface reads from the last address fetched increased by 4 (one word). This read is with a
lower priority and it is aborted if a master requests a read (data or fetch) to a different
address than the prefetch one. When the prefetch is enabled, one buffer for loops is moved
to a new group (of only one buffer) to store the prefetched value: 2 buffers continue to store
the jumps, 1 buffer is used for prefetch and 1 buffer is used for the last value.
The memory interface can only prefetch one address, so the function is temporarily disabled
when no fetch is done and the prefetch is already completed. After a prefetch, if the master
requests the prefetched value, the content of the prefetch buffer is copied to the last value
buffer and a new prefetch is enabled. If, instead, the master requests a different address,
the content of the prefetch buffer is lost, a read in the NVM is started (if necessary) and,
when it is complete, a new prefetch is enabled at the new address fetched increased by 4.
The prefetch can only increase the performance when reading with 1 wait state and for
mostly linear codes: the user must evaluate the pros and cons to enable or not the prefetch
in every situation. The prefetch increases the consumption because many more readings
are done in the NVM (and not all of them will be used by the master). To see the advantages
of prefetch on Dhrystone code, refer to the Dhrystone performances section.
Figure 4 shows the timing to fetch a linear code in the NVM when the prefetch is disabled,
both for 0 wait state (a) and 1 wait state (b). You can compare these two sequences with the
ones in Figure 5, when the prefetch is enabled, to have an idea of the advantages of a
prefetch on a linear code with 0 and 1 wait states.

Figure 4. Timing to fetch and execute instructions with prefetch disabled

cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
1 2 3 4 5 6 7 8 9 10 11
Addr Fetch Exec. Exec.
1&2 1&2 1 2
(a)
Addr Fetch Exec. Exec.
3&4 3&4 3 4
Addr Fetch Exec. Exec.
5&6 5&6 5 6

Addr Fetch Exec. Exec.

1&2 1&2 Wait 1 2
(b)
Addr Fetch Exec. Exec.
3&4 3&4 Wait 3 4
Addr Fetch Exec. Exec.
5&6 5&6 Wait 5 6

MS32396V1

1. (a) corresponds to 0 wait state.

2. (b) corresponds to 1 wait state.

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Figure 5 shows the timing to fetch and execute instructions from the NVM with 0 wait states
(a) and 1 wait state (b) when the prefetch is enabled. The read executed by the prefetch
appears in green.
Read as data and pre-read
A data read from the memory interface, corresponds to any read operation that is not a
fetch. The master reads operation constants and parameters as data. All reads done by
DMA (to copy from one address to another) are read as data. No check is done on the
location of the data read (can be in every area of the NVM).
At reset, (DISAB_BUF = 0, PRFTEN = 0, PRE_READ = 0), the memory interface uses 2
buffers organized in one group to store the last two values read as data.
In some particular cases (for example when the DMA is reading a lot of consecutive words
in the NVM), it can be useful to enable the pre-read (PRE_READ = 1 with DISAB_BUF = 0).
The pre-read works exactly like the prefetch: it is a speculative reading at the last data
address increased by 4 (one word). With this configuration, one buffer of data is moved to a
new group to store the pre-read value, while the second buffer continues to store the last
value read. For a prefetch, the pre-read value is copied in the last read value if the master
requests it, or is lost if the master requests a different address.
The pre-read has a lower priority than a normal read or a prefetch operation: this means that
it will be launched only when no other type of read is ongoing. Pay attention to the fact that
a pre-read used in a wrong situation can be harmful: in a code where a data read is not
done linearly, reducing the number of buffers (from 2 to 1) used for the last read value can
increase the number of accesses to the NVM (and the time to read the value). Moreover,
this can generate a delay on prefetch. An example of this situation is the code Dhrystone,
whose results are shown in the corresponding section.
As for a prefetch operation, the user must select the right moment to enable and disable the
pre-read.

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Figure 5. Timing to fetch and execute instructions with prefetch enabled

cycle cycle cycle cycle cycle cycle cycle cycle cycle

1 2 3 4 5 6 7 8 9

Addr Fetch Exec. Exec.

1&2 1&2 1 2
(a)
Addr Fetch Exec. Exec.
3&4 3&4 3 4
Addr Read Addr Fetch Exec. Exec.
3&4 3&4 5&6 5&6 5 6
Addr Read
5&6 5&6

Addr Fetch Exec. Exec.

Wait
1&2 1&2 1 2
(b)
Addr Fetch Exec. Exec.
3&4 3&4 3 4
Addr Read Addr Fetch Exec. Exec.
Wait
3&4 3&4 5&6 5&6 5 6
Addr Read
Wait
5&6 5&6

MS32397V1

Table 17 is a summary of the possible configurations.

Table 17. Configurations for buffers and speculative reading

DISAB_BUF PRFTEN PRE_READ Description

1 X X Buffers disabled
0 0 0 Buffer enabled: no speculative reading is done
Prefetch enabled: speculative reading on fetch
0 1 0
enabled
pre-read enabled: speculative reading on data
0 0 1
enabled
Prefetch and pre-read enabled: speculative reading
0 1 1
on fetch and data enabled

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Dhrystone performances
The Dhrystone test is used to evaluate the memory interface performances. The test has
been executed in all memory interface configurations. Refer to Table 18 for a summary of
the results.
Common parameters are:
• the matrix size is 20 x 20
• the loop is executed 1757 times
• the version of Arm® compiler is 4.1 [Build 561]
Here is some explanation about the results:

Table 18. Dhrystone performances in all memory interface configurations

Number of Number of
DISAB_BUF PRFTEN PRE_READ DMIPS x MHz
wait states DMIPS (x1000)

0 1 0 0 953 15.25
0 0 0 0 953 15.25
0 0 1 0 953 15.25
0 0 0 1 953 15.25
0 0 1 1 953 15.25
1 1 0 0 677 21.66
1 0 0 0 690 22.08
1 0 1 0 823 26.34
1 0 0 1 691 22.11
1 0 1 1 816 26.11

• The pre-read is not useful for this test: when enabled with the prefetch, it reduces the
memory interface performance because only one buffer is used to store the last data
read and, in this code, the master rarely reads the data linearly. This justifies the very
small increase of performance when enabled without a prefetch.
• The buffers (without speculative readings) with 1 wait state give a little advantage that
can be considered without any costs.
• At a 0 wait state, the best performance (as certified by Arm®) may be due to a different
code alignment during the compilation.

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3.3.4 Writing/erasing the NVM

There are many ways to change the NVM content. The memory interface helps to reduce
the possibility of unwanted changes and to implement by hardware all sequences necessary
to erase or write in the different memory areas.

Write/erase protocol
To write/erase memory content when the protections have been removed, the user needs
to:
1. configure the operation to execute,
2. send to the memory interface the right number of data, writing one or several
addresses in the NVM,
3. wait for the operation to complete.
During the waiting time, the user can prepare the next operation (except in very particular
cases) writing the new configuration and starting to write data for the next write/erase
operation.
The waiting time depends on the type of operation. A write/erase can last from Tprog (3.2
ms) to 2 x Tglob (3.7 ms) + Tprog (3.2 ms). The memory interface can be configured to write
a half-page (16 words in the Flash program memory) with only one waiting time. This can
reduce the time to program a big amount of data.
Two different protocols can be used: single programming and multiple programming
operation.
Single programming operation
With this protocol, the software has to write a value in a not-protected address of the NVM.
When the memory interface receives this writing request, it stalls the master for some
pulses of clock (for more details, see Table 19) while it checks the protections and the
previous value and it latches the new value inside the NVM. The software can then start to
configure the next operation. The operation will complete when the EOP bit of FLASH_SR
register rises (if it was 0 at the operation start). The operation time is resumed in Table 21
for all operations.
Multiple programming operation (half page)
You can write a half-page (16 words) in Flash program memory, To execute this protocol,
follow the next conditions:
• PGAERR bit in the FLASH_SR register has to be zero (no previous alignment errors).
• The first address has to be half-page aligned (the 6 lower bits of the address have to be
at zero).
• All 16 words must be in the same half-page (address bits 7 to 31 must be the same for
all 16 words). This means that the first address sets the half-page and the next ones
must be inside this half-page. The written data will be stored sequentially in the next
addresses. It is not important that the addresses increase or change (for example, the
same address can be used 16 times), as the memory interface will automatically
increase the address internally.
• Only words (32 bits) can be written.

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When the memory interface receives the first address, it stalls the master for some pulses of
clock while it checks the protections and the previous value and it latches the new value
inside the NVM (for more details, see Table 19). Then, the memory interface waits for the
second address. No read is accepted: only a fetch will be executed, but it aborts the ongoing
write operation. After the second address, the memory interface stalls the core for a short
time (less than the previous one) to perform a check and to latch it in the NVM before
waiting for the next one. This sequence continues until all 16 words have been latched
inside the NVM. A wrong alignment or size will abort the write operation. If the 16 addresses
are correctly latched, the memory interface starts the write operation. The operation will
complete when EOP bit of FLASH_SR register rises (if it was 0 at the operation start). The
operation time is resumed in Table 21.
This protocol can be used either through application code running from RAM or through
DMA with application code running from RAM or core sleeping.

Unlocking/locking operations
Before performing a write/erase operation, it is necessary to enable it. The user can write
into the Flash program memory, data EEPROM and Option bytes areas.
To perform a write/erase operation, unlock PELOCK bit of the FLASH_PECR register. When
this bit is unlocked (its value is 0), the other bits of the same register can be modified. When
PELOCK is 0, the write/erase operations can be executed in the data EEPROM.
To write/erase the Flash program memory, unlock PRGLOCK bit of the FLASH_PECR
register. The bit can only be unlocked when PELOCK is 0.
To write/erase the user Option bytes, unlock OPTLOCK bit of the FLASH_PECR register.
The bit can only be unlocked when PELOCK is 0. No relation exists between PRGLOCK
and OPTLOCK: the first one can be unlocked when the second one is locked and vice
versa.
Unlocking the data EEPROM and the FLASH_PECR register
After a reset, the data EEPROM and the FLASH_PECR register are not accessible in write
mode because PELOCK bit in the FLASH_PECR register is set. The same unlocking
sequence unprotects both of them at the same time.
The following sequence is used to unlock the data EEPROM and the FLASH_PECR
register:
• Write PEKEY1 = 0x89ABCDEF to the FLASH_PEKEYR register
• Write PEKEY2 = 0x02030405 to the FLASH_PEKEYR register
For code example, refer to A.3.1: Unlocking the data EEPROM and FLASH_PECR register
code example.

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Any wrong key sequence will lock up FLASH_PECR until the next reset and generate a
hard fault. Idem if the master tries to write another register between the two key sequences
or if it uses the wrong key. A reading access does not generate an error and does not
interrupt the sequence. A hard fault is returned in any of the four cases below:
• After the first write access if the PEKEY1 value entered is erroneous.
• During the second write access if PEKEY1 is correctly entered but the value of
PEKEY2 does not match.
• If there is any attempt to write a third value to PEKEYR (pay attention: this is also true
for the debugger).
• If there is any attempt to write a different register of the memory interface between
PEKEY1 and PEKEY2.
When properly executed, the unlocking sequence clears PELOCK bit in the FLASH_PECR
register.
To lock FLASH_PECR and the data EEPROM again, the software only needs to set
PELOCK bit in FLASH_PECR. When locked again, PELOCK bit needs a new sequence to
return to 0.
For code example, refer to A.3.2: Locking data EEPROM and FLASH_PECR register code
example.
Unlocking the Flash program memory
An additional protection is implemented to write/erase the Flash program memory.
After a reset, the Flash program memory is no more accessible in write mode: PRGLOCK
bit is set in the FLASH_PECR register. A write access to the Flash program memory is
granted by clearing PRGLOCK bit.
The following sequence is used to unlock the Flash program memory:
• Unlock the FLASH_PECR register (see the Unlocking the data EEPROM and the
FLASH_PECR register section).
• Write PRGKEY1 = 0x8C9DAEBF to the FLASH_PRGKEYR register.
• Write PRGKEY2 = 0x13141516 to the FLASH_PRGKEYR register.
For code example, refer to A.3.3: Unlocking the NVM program memory code example.
If the keys are written with PELOCK set to 1, no error is generated and PRGLOCK remains
at 1. It will be unlocked while re-executing the sequence with PELOCK = 0.
Any wrong key sequence will lock up PRGLOCK in FLASH_PECR until the next reset, and
return a hard fault. A hard fault is returned in any of the four cases below:
• After the first write access if the entered PRGKEY1 value is erroneous.
• During the second write access if PRGKEY1 is correctly entered but the PRGKEY2
value does not match.
• If there is any attempt to write a third value to PRGKEYR (this is also true for the
debugger).
• If there is any attempt to write a different register of the memory interface between
PRGKEY1 and PRGKEY2.
When properly executed, the unlocking sequence clears the PRGLOCK bit and the Flash
program memory is write-accessible.

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To lock the Flash program memory again, the software only needs to set PRGLOCK bit in
FLASH_PECR. When locked again, PRGLOCK bit needs a new sequence to return to 0. If
PELOCK returns to 1 (locked), PRGLOCK is automatically locked, too.
Unlocking the Option bytes area
An additional write protection is implemented on the Option bytes area. It is necessary to
unlock OPTLOCK to reload or write/erase the Option bytes area.
After a reset, the Option bytes area is not accessible in write mode: OPTLOCK bit in the
FLASH_PECR register is set. A write access to the Option bytes area is granted by clearing
OPTLOCK.
The following sequence is used to unlock the Option bytes area:
1. Unlock the FLASH_PECR register (see the Unlocking the data EEPROM and the
FLASH_PECR register section).
2. Write OPTKEY1 = 0xFBEAD9C8 to the FLASH_OPTKEYR register.
3. Write OPTKEY2 = 0x24252627 to the FLASH_OPTKEYR register.
For code example, refer to A.3.4: Unlocking the option bytes area code example.
If the keys are written with PELOCK = 1, no error is generated, OPTLOCK remains at 1 and
it will be unlocked when re-executing the sequence with PELOCK to 0.
Any wrong key sequence will lock up OPTLOCK in FLASH_PECR until the next reset, and
return a hard fault. A hard fault is returned in any of the four cases below:
• After the first write access if the OPTKEY1 value entered is erroneous.
• During the second write access if OPTKEY1 is correctly entered but the OPTKEY2
value does not match.
• If there is any attempt to write a third value to OPTKEYR (this is also true for the
debugger).
• If there is any attempt to write a different register of the memory interface between
OPTKEY1 and OPTKEY2.
When properly executed, the unlocking sequence clears the OPTLOCK bit and the Option
bytes area is write-accessible.
To lock the Option bytes area again, the software only needs to set OPTLOCK bit in
FLASH_PECR. When relocked, OPTLOCK bit needs a new sequence to return to 0. If
PELOCK returns to 1 (locked), OPTLOCK is automatically locked, too.
Select between different types of operations
When the necessary unlock sequence has been executed (PELOCK, PRGLOCK and
OPTLOCK), the user can enable different types of write and erase operations, writing the
right configuration in the FLASH_PECR register. The bits involved are:
• PRG
• DATA
• FIX
• ERASE
• FPRG

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Detailed description of NVM write/erase operations

This section details the different types of write and erase operations, showing the necessary
bits for each one.
Write to data EEPROM
• Purpose
Write one word in the data EEPROM with a specific value.
• Size
Write by byte, half-word or word.
• Address
Select a valid address in the data EEPROM.
• Protocol
Single programming operation.
• Requests
PELOCK = 0, ERASE = 0.
• Errors
WRPERR is set to 1 (and the write operation is not executed) if PELOCK = 1 or if the
memory is read-out protected.
• Description
This operation aims at writing a word or a part of a word in the data EEPROM. The user
must write the right value at the right address and with the right size. The memory
interface automatically executes an erase operation when necessary (if all bits are
currently set to 0, there is no need to delete the old content before writing). Similarly, if
the data to write is at 0, only the erase operation is executed. When only a write
operation or an erase operation is executed, the duration is Tprog (3.2 ms); if both are
executed, the duration is 2 x Tprog (6.4 ms). It is possible to force the memory interface
to execute every time both erase and write operations set the FIX flag to 1.
• Duration
Tprog (3.2 ms) or 2 x Tprog (6.4 ms).
• Options
Set the FIX bit to force the memory interface to execute every time an erase (to delete
the old content) and a write operation (to write new data) occur. This gives a fix time for
the operation for any data value and for previous data.
• Erase/write endurance cycles in data EEPROM are linked to one single word
granularity (one erase/write cycle degrades only one programmed word area in data
EEPROM).
For code example, refer to A.3.5: Write to data EEPROM code example.

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Erase data EEPROM

• Purpose
Delete one row in data EEPROM. This operation performs the same function as Write a
word which size is null to data EEPROM. It is available for compatibility purpose only.
• Size
Erase only by word.
• Address
Select one valid address in the data EEPROM.
• Protocol
Single programming operation.
• Requests
PELOCK = 0, ERASE = 1 (optional DATA = 1).
• Errors
WRPERR is set to 1 if PELOCK = 1 or if the memory is read-out protected.
SIZERR is set to 1 if the size is not a word.
• Description
This operation aims at deleting the content of a row in the data EEPROM. A row
contains only 1 word. The user must write a value at the right address with a word size.
The data is not important: only an erase is executed (also with data different from zero).
• Duration
Tprog (3.2 ms).
For code example, refer to A.3.6: Erase to data EEPROM code example.
Write Option bytes
• Purpose
Write one word in the Option bytes area with a specific value.
• Size
Write only by word.
• Address
Select a valid address in the Option bytes area.
• Protocol
Single programming operation.
• Requests
PELOCK = 0, OPTLOCK = 0, ERASE = 0.
• Errors
WRPERR is set to 1 if PELOCK = 1 or OPTLOCK = 1.
WRPERR is set to 1 if the actual read-out protection level is 2 (the Option bytes area
cannot be written at Level 2).
SIZERR is set to 1 if the size is not the word
• Description

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This operation aims at writing a word in the Option bytes area. The Option bytes area
can only be written in Level 0 or Level 1.
The user must consider that, in a word, the 16 higher bits (from 16 to 31) have to be the
complement of the 16 lower bits (from 0 to 15): a mismatch between the higher and
lower parts of data would generate an error during the Option bytes loading (see
Section 3.8: Option bytes) and force the memory interface to load the default values.
The memory interface does not check at the write time if the data is correctly
complemented. The user must write the desired value at the right address with a word
size.
As for data EEPROM, the memory interface deletes the previous content before
writing, if necessary. If the data to write is at 0, the memory interface does not execute
the useless write operation. When only a write operation or only an erase operation is
executed, the duration is Tprog (3.2 ms). If both are executed, the duration is 2 x Tprog
(6.4 ms). The memory interface can be forced to execute every time both erase and
write operations set the FIX flag to 1.
Some configurations need a closer attention because they change the protections. The
memory interface can change the Option bytes write in a Mass Erase or force some
bits not to reduce the protections: for more details, see Section 3.4.4: Write/erase
protection management.
• Duration
Tprog (3.2 ms) or 2 x Tprog (6.4 ms).
• Options
FIX bit can be set to force the memory interface to execute every time an erase (to
delete the old content) and a write operation (to write the new data) occur. This gives a
fix time to program for every data value and for previous data.
For code example, refer to A.3.7: Program Option byte code example.

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Erase Option bytes

• Purpose
Delete one row in the Option bytes area. This operation performs the same function as
Write Option Byte with a zero value. It is available for compatibility purpose only.
• Size
Erase only by word.
• Address
Select a valid address in the Option bytes area.
• Protocol
Single programming operation.
• Requests
PELOCK = 0, OPTLOCK = 0, ERASE = 1 (optional OPT = 1).
• Errors
WRPERR is set to 1 if PELOCK = 1 or OPTLOCK = 1.
WRPERR is set to 1 if the actual protection level is 2 (the Option bytes area cannot be
erased at Level 2).
SIZERR is set to 1 if the size is not the word.
• Description
This operation aims at deleting the content of a row in the Option bytes area. A row
contains only 1 word. The use must write zero at the right address with a word size.
Refer to Section : Write Option bytes for additional information.
Since all bits are set to 0 after an erase operation, there will be a mismatch during the
Option bytes loading and the default values will be loaded.
• Duration
Tprog (3.2 ms).
For code example, refer to A.3.8: Erase Option byte code example.

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Program a single word to Flash program memory

• Purpose
Write one word in the Flash program memory with a specific value.
• Size
Write only by word.
• Address
Select an address in the Flash program memory.
• Protocol
Single programming operation.
• Requests
PELOCK = 0, PRGLOCK = 0.
• Errors
WRPERR is set to 1 if PELOCK = 1 or PRGLOCK = 1.
WRPERR is set to 1 if the user tries to write in a write-protected sector (see the PcROP
(Proprietary Code Read-Out Protection) section).
NOTZEROERR is set to 1 if the user tries to write a value in a word which is not zero.
This error does not stop the write operation on category 3 devices while the operation
is stopped on other categories.
SIZERR is set to 1 if the size is not a word.
• Description
This operation allows writing a word in Flash program memory. The user must write the
right value at the right address with a word size. The memory interface cannot execute
an erase to delete the previous content before the write operation is performed.
If the previous content is not null:
– Category 3 devices
NOTZEROERR is set to 1.
The real value written in the memory is the OR of the previous value and the new
value (the memory interface writes 1 when there was 0 before). This is done both
for data and ECC. Reading back the data might not return the old value, the new
one or the ORed values. The ECC is not compatible with the data any more.
– Other categories
NOTZEROERR is set to 1. Writing a word to an address containing a non-null
value is not performed.
• Duration
Tprog (3.2 ms).
• The erase/write endurance cycles in Flash program memory are linked to one page
granularity (one erase/write cycle will degrade one programmed page in word area in
Flash program memory).
For code example, refer to A.3.9: Program a single word to Flash program memory code
example.

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Program half-page in Flash program memory

• Purpose
Write one half page (16 words) in the Flash program memory.
• Size
Write only by word.
• Address
Select one address in the Flash program memory aligned to a half-page (for the first
address) and inside the same half-page selected by the second address for the next 15
addresses.
• Protocol
Multiple programming operation.
• Requests
PELOCK = 0, PRGLOCK = 0, FPRG = 1, PRG = 1.
• Errors
WRPERR is set to 1 if PELOCK = 1 or PRGLOCK = 1. WRPERR is set to 1 if the user
tries to write in a write-protected sector (see the PcROP (Proprietary Code Read-Out
Protection) section).
NOTZEROERR is set to 1 if the user tries to write a value in a word which is not zero.
This error does not stop the write operation on category 3 devices while the operation
is stopped on other categories. The check is done when all 16 addresses have been
received, before the current write phase in Flash memory. The error flags are set only
when all checks are performed.
SIZERR is set to 1 if the size is not the word.
PGAERR is set to 1 if the first address is not aligned to a half-page and if one of the
following addresses (address from 2 to 16) is outside the half-page determined by the
first address. No check is done to verify if the address has increased or if it has
changed: this is done automatically by the memory interface. What is important is that
the first address is aligned to the half-page, and that the next addresses are in the
same half-page.
FWWERR is set to 1 if the write is aborted because the master fetched in the NVM.
The read as data does not stop the write operation.
• Description
This operation allows writing a half-page in Flash program memory. The user must
write the 16 desired values at the right address with a word size (as explained in the
multiple programming operation). The memory interface cannot execute an erase to
delete the previous content before writing (the user must delete the page before
writing).
As for the single programming operation, if the previous content is not null:
– Category 3 devices
NOTZEROERR is set to 1.
The written value is the OR of previous and new data. This means that reading
back the written address may return a value which is different from the written one.

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– Other categories
NOTZEROERR is set to 1. Writing a word to an address containing a non-null
value is not performed.
When a half-page operation starts, the memory interface waits for 16 addresses/data,
aborting (with a hard fault) all read accesses that are not a fetch (refer to Fetch and
prefetch). A fetch stops the half-page operation. The memory content remains
unchanged, the FWWERR error is set in the FLASH_SR register. To complete the half-
page programming operation, all the desired values should be written again.
• Duration
Tprog (3.2 ms).
For code example, refer to A.3.10: Program half-page to Flash program memory code
example.

Parallel write half-page Flash program memory

• Purpose
Write 2 half-pages (one per bank) in parallel in Flash program memory.
• Size
Write only by word.
• Address
For each half-page, one address, aligned to half-page start address, must be selected
in Flash program memory. The following 15 addresses must point to the half-page
selected by first address.
Furthermore, the addresses of the second half-page must be on a different bank with
respect to the start address of the first half-page (only the first address is checked).
• Protocol
Multiple programming operation.
• Requests
PELOCK = 0, PRGLOCK = 0, FPRG = 1, PRG = 1, PARALLELBANK=1.
• Errors
This operation can generate the same kind of errors as program half-page in flash
program memory. However, PGAERR is also generated when the second half-page
selected is located in the same bank as the first half-page.
All the errors detected during this operation abort the whole program operation (i.e.
both banks).
• Description
This operation programs in parallel one half-page on both Flash program memory
banks. This speeds up the initial programming of the whole NVM.
It is possible to start with Bank 1 or Bank 2.
• Duration
Tprog (3.2 ms).

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Erase a page in Flash program memory

• Purpose
Delete one page (32 words) in the Flash program memory.
• Size
Erase only by word (it deletes a page of the Flash program memory writing with a word
size)
• Address
Select a valid address in the Flash program memory.
• Protocol
Single programming operation.
• Requests
PELOCK = 0, PRGLOCK = 0, ERASE = 1, PRG = 1.
• Errors
WRPERR is set to 1 if PELOCK = 1 or PRGLOCK = 1.
WRPERR is set to 1 if the row is in a protected sector (see PcROP (Proprietary Code
Read-Out Protection)).
SIZERR is set to 1 if the size is not the word.
• Description
This operation aims at deleting the content of a row in the Flash program memory. The
user must write a value in the right address with a word size. The data is not important:
only an erase is executed (also with data not at zero). The address does not need to be
aligned to the page: the memory interface will delete the page which contents the
address.
• Duration
Tprog (3.2 ms).
For code example, refer to A.3.11: Erase a page in Flash program memory code example.

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Mass erase
• Purpose
Remove the read and write protection on the Flash program memory and data
EEPROM.
• Size
Erase only by word.
• Address
To generate a mass erase, it is necessary to write 0x015500AA to the first Option bytes
address (bits 31 to 25 and 15 to 9 are not complemented because they are not used,
and not checked) with Level 1 as the actual level.
• Protocol
Single programming operation.
• Requests
PELOCK = 0, OPTLOCK = 0, Protection Level = 1, the lower nibble of data has to be
0xAA (Level 0), with 0x55 as the third nibble.
• Errors
WRPERR is set to 1 if PELOCK = 1 or OPTLOCK = 1.
WRPERR is set to 1 if the actual protection level is 2 (the Option bytes area cannot be
written in Level 2).
SIZERR is set to 1 if the size is not the word.
• Description
This operation is similar to the write user Option byte operation: the memory interface
changes it in a mass erase when the actual Protection Level is 1 and the requested
Protection Level is 0. The user must write the desired value in the first address of the
Option bytes area with a word size.
A mass erase deletes the content of the Flash program memory and data EEPROM,
changes the protection level to Level 0 and disables PcROP. (WPRMOD = 0). The bits
write protection and BOR_LEVEL remain unchanged.
Unlike all other operations, the software cannot request new writing operations while a
mass erase is ongoing. To be sure that a mass erase has completed, the software can
reset the EOP bit of FLASH_SR register before the write operation and check when
EOP goes to 1 (End Of Program). If this limitation is not respected, a wrong value may
be written in the Flash program memory and data EEPROM when the Protection Level
is written, thus adding unwanted protections (also for mismatch) that could make the
device useless.
• Duration
2 x Tprog (6.4 ms) + Tglob (3.7 ms)
For code example, refer to A.3.12: Mass erase code example.

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Timing tables

Table 19. NVM write/erase timings

Delay to latch the first Delay to latch the next
Operation address/data address/data
(in AHB clock pulses) (in AHB clock pulses)

Write to data EEPROM 18 -

Erase data EEPROM 17 -
Write Option bytes 18 -
Erase Option bytes 17 -
Program a single word in Flash
78 -
program memory
Program half-page in Flash
63 6
program memory
Erase a page in Flash program
76 -
memory

Table 20. NVM write/erase duration

Operation Parameters/Conditions Duration

Previous data = 0
Tprog (3.2 ms)
FIX = 0
Previous data /= 0
Write to data EEPROM New data = 0
Tprog (3.2 ms)
Size = word
FIX = 0
Other situations 2 x Tprog (6.4 ms)
Erase data EEPROM - Tprog (3.2 ms)
Previous data = 0
Tprog (3.2 ms)
FIX = 0
Previous data /= 0
Write Option bytes
New data = 0 Tprog (3.2 ms)
FIX = 0
Other situations 2 x Tprog (6.4 ms)
Erase Option bytes - Tprog (3.2 ms)
Program a single word in
- Tprog (3.2 ms)
Flash program memory
Program a half-page in
- Tprog (3.2 ms)
Flash program memory
Erase a page in Flash
- Tprog (3.2 ms)
program memory
Mass erase - 2 x Tprog (6.4 ms) + Tglob (3.7 ms)

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Status register
The FLASH_SR Status Register gives some information on the memory interface or the
NVM status (operation(s) ongoing) and about errors that happened.
BSY
This flags is set and reset by hardware. It is set to 1 every time the memory interface
executes a write/erase operation, and it informs that no other operation can be executed. If
a new operation is requested, different behaviors can occur:
• Waiting for read, or waiting for write/erase, or waiting for option loading:
If the software requests a write operation while a write/erase operation is executing
(HVOFF = 0), the memory interface stalls the master and has the pending operation
execute as soon as the write/erase operation is complete.
• Hard fault:
If the software requests a data read in a half-page operation when the memory
interface is waiting for the next address/data (BSY is already 1 but HVOFF = 0), the
memory interface generates a hard fault (because it cannot execute the read) and
continues to wait for missing addresses.
• RDERR error:
If the software requests a read operation while a write/erase operation is executing
(HVOFF = 0) but the address is protected, the memory interface rises the flag and
continues to wait for the end of the write/erase operation.
• Write abort:
If the software fetches in the NVM when the memory interface is waiting for an
address/data in a half-page operation, the write/erase operation is aborted, the
FWWERR flag is raised and the fetch is executed.
EOP
This flag is set by hardware and reset by software. The software can reset it writing 1 in the
status register. This bit is set when the write/erase operation is completed and the memory
interface can work on other operations (or start to work on pending operations).
It is useful to clear it before starting a new write/erase operation, in order to know when the
actual operation is complete. It is very important to wait for this flag to rise when a mass
erase is ongoing, before requesting a new operation.
HVOFF
This flag is set and reset by hardware and it is a memory interface information copy coming
from the NVM: it informs when the High-Voltage Regulators are on (= 0) or off (= 1).
PGAERR
This flag is set by hardware and reset by software. It informs when an alignment error
happened. It is raised when:
• The first address in a half-page operation is not aligned to a half-page (lower 6 bits
equal to zero).
• A half-page change happened in a half-page operation (the addresses from 2 to 16 in a
half-page operation are not in the same half-page, selected by the first address).
An alignment error aborts the write/erase operation and an interrupt can be generated (if
ERRIE = 1 in the FLASH_PECR register). The content of the NVM is not changed.
If this flag is set, the memory interface blocks all other half-page operations.

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To reset this flag, the software need to write it to 1.

SIZERR
This flag is set by hardware and reset by software. It informs when a size error happened. It
is raised when:
• A write by byte and half-word occurs in the Flash program memory and Option bytes.
• An erase (with bit ERASE = 1 in FLASH_PECR register) by byte or half-word occurs in
all areas.
A size error aborts the write/erase operation and an interrupt can be generated (if
ERRIE = 1 in the FLASH_PECR register). The content of the NVM is not changed.
To reset this flag, the software needs to write it to 1.
NOTZEROERR
This flag is set by hardware and reset by software. It indicates that the application software
is attempting to write to one or more NVM addresses that contain a non-zero value.
Except for category 3 devices, the modify operation is always aborted when this condition is
met. For category 3 devices, a not-zero error does not abort the write/erase operation but
the value might be corrupted.
In a write by half-page, all 16 words are checked between the first address/value and the
second one, and the flag is only set when all words are checked. If the flag is set, it means
that at least one word has an actual value not at zero.
In a write by word, only the targeted word is checked and the flag is immediately set if the
content is not zero.
An interrupt is generated if ERRIE = 1 in FLASH_PECR register. To reset this flag, the
application software needs to program it to 1.
Note: Notification of a not-zero error condition (i.e. NOTZEROERR flag and the associated
interrupt) can be disabled by the application software via the NZDISABLE bit in
FLASH_PECR register. However, for all device except category 3 devices, the condition is
still checked internally and modify operation is anyway blocked

3.4 Memory protection

The user can protect part of the NVM (Flash program memory, data EEPROM and Option
bytes areas) from unwanted write and against code hacking (unwanted read).
The read protection is activated by setting the RDP option byte and then applying a system
reset to reload the new RDP option byte.
Note: If the read protection is set while the debugger has been active (through SWD) after last
POR (power-on reset), apply a POR (power-on reset) or wakeup from Standby mode
instead of a system reset (the option bytes loading is not sufficient).

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Three types of protections are implemented.

3.4.1 RDP (Read Out Protection)

This type of protection aims at protecting against unwanted read (hacking) of the NVM
content. This protection is managed by RDPROT bitfield in the FLASH_OPTR register. The
value is loaded from the Option bytes area during a boot and copied in the read-only
register.
Three protection levels are defined:
• Level 0: no protection
Level 0 is set when RDPROT is set to 0xAA. When this level is enabled, and if no other
protection is enabled, read and write can be done in the Flash program memory, data
EEPROM and Option bytes areas without restrictions. It is also possible to read and
write the backup registers freely.
• Level 1: memory read protection
Level 1 is set when RDPROT is set to any value except 0xAA and 0xCC, respectively
used for Level 0 and Level 2. This is the default protection level after an Option bytes
erase or when there is a mismatch in the RDPROT field.
Level 1 protects the Flash program memory and data EEPROM. When protection Level
1 is set through boot from RAM, bootloader or debugger, a power-down or a standby is
required to execute the user code.
When this level is enabled:
– No access to the Flash program memory and data EEPROM (read both for fetch
and data and write) and no backup register reading is performed if the debug
features (single-wire), or the device boot in the RAM, or the System memory is
connected. If the user tries to read the Flash memory or data EEPROM, a hard
fault is generated. No restriction is present on other areas: it is possible to read
and write/erase the Option bytes area and to execute or read in the System
Memory.
– All operations are possible when the boot is done in the Flash program memory.
– Writing the first Option byte with a value that changes the protection level to Level
0 (it is necessary that byte 0 is 0xAA and byte 2 is 0x55), a mass erase is
generated. The mass erase deletes the Flash program memory and data
EEPROM, deletes the first Option byte and then rewrites it to enable Level 0 and
disable PCROP (WPRMOD = 0), and deletes the backup registers content.
• Level 2: disable debug and chip read protection
Level 2 is set when RDPROT is set to 0xCC. When this level is enabled, it is only
possible to boot from the Flash program memory, and the debug features (single-wire)
are disabled. The Option bytes are protected against write/erase and the protection
level can no longer be changed. The application can write/erase to the Flash program
memory and data EEPROM (it is only possible to boot from the Flash program memory
and execute the customer code) and access the backup registers. When an Option
bytes loading is executed and Level 2 is enabled, old information on debug or boot in
the RAM or System memory are deleted.
Note: The debug feature is also disabled under reset. STMicroelectronics is not able to perform
analysis on defective parts on which level 2 protection has been set.
Figure 6 resumes the way the protection level can be changed and Table 21 the link
between the values read in the Option bytes and the protection level.

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Figure 6. RDP levels

Write Level 1
RDP = 0xCC RDP /= 0xAA
RDP /= 0xCC
Write
(default) RDP = 0xAA
Write
Mass erase
RDP /= 0xCC and
Write RDP /= 0xAA
RDP /= 0xAA and
RDP /= 0xCC
Level 2 Level 0

RDP = 0xCC Write RDP = 0xAA

RDP = 0xCC

Write
RDP = 0xAA
RDP decrease

RDP increase

RDP unchanged

MS34776V1

Table 21. Protection level and content of RDP Option bytes

RDP byte value RDP complementary value Read Protection status

0xAA 0x55 Level 0

0xCC 0x33 Level 2
Any other value Complement of RDP byte Level 1
Any value Not the complement value of RDP byte Level 1

3.4.2 PcROP (Proprietary Code Read-Out Protection)

The Flash program memory can be protected from being read by a hacking code: the read
data are blocked (not for a fetch). The protected code must not access data in the protected
zone, including the literal pool.
The Flash program memory can be protected against a hacking code read: this blocks the
data read (not for a fetch), assuming that the native code is compiled according to the
PcROP option. This mode is activated setting WPRMOD = 1 in the FLASH_OPTR register.
The protection granularity is the sector (1 sector = 32 pages = 4 KB). To protect a sector, set
to 0 the right bit in the WRPROT configuration: 0 means read and write protection, 1 means
no protection.
Table 22 shows the link between the bits of the WRPROT configuration and the address of
the Flash memory sectors.

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Any read access performed as data (see Read as data and pre-read) in a protected sector
will trigger the RDERR flag in the FLASH_SR register. Any read-protected sector is also
write-protected and any write access to one of these sectors will trigger the WRPERR flag in
the FLASH_SR register.

Table 22. Link between protection bits of FLASH_WRPROTx register

and protected address in Flash program memory(1)
Bit Start address End address Bit Start address End address

0 0x0800 0000 0x0800 0FFF 24 0x0801 8000 0x0801 8FFF

1 0x0800 1000 0x0800 1FFF 25 0x0801 9000 0x0801 9FFF
2 0x0800 2000 0x0800 2FFF 26 0x0801 A000 0x0801 AFFF
3 0x0800 3000 0x0800 3FFF 27 0x0801 B000 0x0801 BFFF
4 0x0800 4000 0x0800 4FFF 28 0x0801 C000 0x0801 CFFF
5 0x0800 5000 0x0800 5FFF 29 0x0801 D000 0x0801 DFFF
6 0x0800 6000 0x0800 6FFF 30 0x0801 E000 0x0801 EFFF
7 0x0800 7000 0x0800 7FFF 31 0x0801 F000 0x0801 FFFF
8 0x0800 8000 0x0800 8FFF 32 0x0802 0000 0x0802 0FFF
9 0x0800 9000 0x0800 9FFF 33 0x0802 1000 0x0802 1FFF
10 0x0800 A000 0x0800 AFFF 34 0x0802 2000 0x0802 2FFF
11 0x0800 B000 0x0800 BFFF 35 0x0802 3000 0x0802 3FFF
12 0x0800 C000 0x0800 CFFF 36 0x0802 4000 0x0802 4FFF
13 0x0800 D000 0x0800 DFFF 37 0x0802 5000 0x0802 5FFF
14 0x0800 E000 0x0800 EFFF 38 0x0802 6000 0x0802 6FFF
15 0x0800 F000 0x0800 FFFF 39 0x0802 7000 0x0802 7FFF
16 0x0801 0000 0x0801 0FFF 40 0x0802 8000 0x0802 8FFF
17 0x0801 1000 0x0801 1FFF 41 0x0802 9000 0x0802 9FFF
18 0x0801 2000 0x0801 2FFF 42 0x0802 A000 0x0802 AFFF
19 0x0801 3000 0x0801 3FFF 43 0x0802 B000 0x0802 BFFF
20 0x0801 4000 0x0801 4FFF 44 0x0802 C000 0x0802 CFFF
21 0x0801 5000 0x0801 5FFF 45 0x0802 D000 0x0802 DFFF
22 0x0801 6000 0x0801 6FFF 46 0x0802 E000 0x0802 EFFF
23 0x0801 7000 0x0801 7FFF 47 0x0802 F000 0x0802 FFFF
1. Bits 0 to 3 apply to category 1 devices only, bits 0 to 7 apply to category 2, and bits 0 to 15 to
category 3.

When WPRMOD = 1 (PcROP enabled), it is not possible to reduce the protection on a

sector: new zeros (to protect new sectors) can be set, but new ones (to remove the
protection from sectors) cannot be added. This is valid regardless of the protection level
(RDPROT configuration). When WPRMOD is active, if the user tries to reset WPRMOD or
to remove the protection from a sector, the programming is launched but WPRMOD or
protected sectors remain unchanged.

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The only way to remove a protection from a sector is to request a mass erase (which
changes the protection level to 0 and disables PcROP): when PcROP is disabled, the
protection on sectors can be changed freely.

3.4.3 Protections against unwanted write/erase operations

The memory interface implements two ways to protect against unwanted write/erase
operations which are valid for all matrix or only for specific sectors of the Flash program
memory.
As explained in the Unlocking/locking operations section, the user can:
• Write/erase to the data EEPROM only when PELOCK = 0 in the FLASH_PECR
register.
• Write/erase to the Option bytes area only when PELOCK = 0 and OPTLOCK = 0 in the
FLASH_PECR register.
• Write/erase to the Flash program memory only when PELOCK = 0 and PRGLOCK = 0
in the FLASH_PECR register.
To see the sequences to set PELOCK, PRGLOCK and OPTLOCK, refer to the Unlocking
the data EEPROM and the FLASH_PECR register, Unlocking the Flash program memory
and Unlocking the Option bytes area sections.
In the Flash program memory, it is possible to add another write protection with the sector
granularity. When PcROP is disabled (WPRMODE = 0), the bits of WRPROT are used to
enable the write protection on the sectors. The polarity is opposed relatively to PcROP: to
protect a sector, it is necessary to set the bit to 1; to remove the protection, it is necessary to
set the bit to 0. Table 22 is valid for a write protection as well. As explained, when PcROP is
enabled, the sectors protected against read are also protected against write/erase. It is
always possible to change the write protection on sectors both in Level 0 and Level 1
(provided that it is possible to write/erase to Option bytes and that PcROP is disabled).
Table 23 resumes the protections.

Table 23. Memory access vs mode, protection and Flash program memory sectors
Mode

User
Flash program memory (including In Application User
sectors Programming) in Debug, or
no Debug, or with Boot in RAM, or
no Boot in RAM, or with Boot in System memory
no Boot in System memory

Level 1
RDP Level 2 Level 0 Level 1 Level 2
Level 0

Flash program memory Protected

R R R NA(1)
(FLASH_PRGLOCK = 1) (no access)
Flash memory Protected
R/W R/W R/W NA(1)
(FLASH_PRLOCK = 0) (no access)
Flash program memory Protected
R R R NA(1)
in WRP pages (no access)

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Table 23. Memory access vs mode, protection and Flash program memory sectors (continued)
Mode

User
Flash program memory (including In Application User
sectors Programming) in Debug, or
no Debug, or with Boot in RAM, or
no Boot in RAM, or with Boot in System memory
no Boot in System memory

Level 1
RDP Level 2 Level 0 Level 1 Level 2
Level 0

Flash program memory Protected

Fetch Fetch Fetch NA(1)
in PCROP pages (no access)
Data EEPROM Protected
R R R NA(1)
(FLASH_PELOCK = 1) (no access)

Data EEPROM Protected

R/W R/W R/W NA(1)
(FLASH_PELOCK = 0) (no access)
Option bytes
R R R R NA(1)
(FLASH_OPTLOCK = 1)
Option bytes
R/W R R/W R/W NA(1)
(FLASH_OPTLOCK = 0)
1. NA stands for “not applicable”.

3.4.4 Write/erase protection management

Here is a summary of the rules to change all previous protections:
• When the protection Level is 2, no protection change can be done.
• When in Level 0 or 1, it is always possible to move to Level 2, writing xx33xxCC (the x
are the hexadecimal digits that can have any value) in the first Option byte word.
• When in Level 0, it is possible to move to Level 1, writing any value in the first Option
byte word that is not xx33xxCC (Level 2) or xx55xxAA (Level 0).
• when in Level 1, the protection can be reduced to Level 0, writing xx55xxAA in the first
Option byte word. This generates a mass erase and deletes the PcROP field too.
• It is always possible to enable PcROP (except in Level 2), writing x0xxx1xx in the first
Option byte word. If there is a mismatch during an Option byte loading on this flag,
PcROP is enabled.
• PcROP can be removed on requesting a mass erase (move from Level 1 to Level 0).
• When PcROP is disabled, a write protection can be added on sectors (writing 1) or
removed (writing 0) in the third word of the Option bytes. A mismatch concerns all
write-protected sectors (if PcROP is disabled).
• When PcROP is enabled, protected sectors can be added (writing 0) but cannot be
removed. A mismatch concerns all read- and write-protected sectors (if PcROP is
enabled).
• A mass erase does not delete the third word of the Option bytes: the user must write it
correctly.

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3.4.5 Protection errors

Write protection error flag (WRPERR)
If an erase/program operation to a write-protected page of the Flash program memory and
data EEPROM is launched, the Write Protection Error flag (WRPERR) is set in the
FLASH_SR register. Consequently, the WRPERR flag is set when the software tries to:
• Write to a WRP page.
• Write to a System memory page or to factory option bytes.
• Write to the Flash program memory, data EEPROM or Option bytes if they are not
unlocked by PEKEY, PRGKEY or OPTKEY.
• Write to the Flash program memory, data EEPROM or Option bytes when the RDP
Option byte is set and the device is in debug mode or is booting from the RAM or from
the System memory.
A write-protection error aborts the write/erase operation and an interrupt can be generated
(if ERRIE = 1 in the FLASH_PECR register).
To reset this flag, the software needs to write it to 1.

Read error (RDERR)

If the software tries to read a sector protected by PcROP, the RDERR flag of FLASH_SR is
raised. The data received on the bus is at 0.
If the error interrupt is enabled (ERRIE = 1 in the FLASH_PECR register), an interrupt is
generated.
To reset this flag, the software needs to write it to 1.

3.5 NVM interrupts

Setting the End of programming interrupt enable bit (EOPIE) in the FLASH_PECR register
enables an interrupt generation when an erase or a programming operation ends
successfully. In this case, the End of programming (EOP) bit in the FLASH_SR register is
set. To reset it, the software needs to write it to 1.
Setting the Error interrupt enable bit (ERRIE) in the FLASH_PECR register enables an
interrupt generation if an error occurs during a programming or an erase operation request.
In this case, one or several error flags are set in the FLASH_SR register:
• RDERR (PCROP Read protection error flags)
• WRPERR (Write protection error flags)
• PGAERR (Programming alignment error flag)
• OPTVERR (Option validity error flag)
• SIZERR (Size error flag)
• FWWERR (Fetch while write error flag)
• NOTZEROERR (Write a not zero word error flag)
To reset the error flag, the software needs to write the right flag to 1.

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Table 24. Flash interrupt request

Interrupt event Event flag Enable control bit

End of operation EOP EOPIE

RDERR
WRPERR
PGAERR
Error OPTVERR ERRIE
SIZERR
FWWERR
NOTZEROERR

3.5.1 Hard fault

A hard fault is generated on:
• The memory bus if a read access is attempted when RDP is set.
• The memory bus if a read as data is received; then, the memory interface is waiting for
a data/address during a half-page write (after the 1st address and before the 16th
address).
• The register bus if an incorrect value is written in PEKEYR, PRGKEYR, or OPTKEYR.

3.6 Memory interface management

The purpose of this section is to clarify what happens when one operation is requested
while another is ongoing: the way the different operations work together and are managed
by the memory interface.

3.6.1 Operation priority and evolution

There are three types of operations and each of them has different flows:

Read
• If no operation is ongoing and the read address is not protected, the read is executed
without delays and with the actual configurations.
• If the read address is protected, the operation is filtered (the read requested is never
sent to the memory) and an error is raised.
• If the read address is not protected but the memory interface is busy and cannot
perform the operation, the read is put on hold to be executed as soon as possible.

Write/erase
• If no operation is ongoing and the write address is not protected, the write/erase will
start immediately; after some clock pulses (see Table 19) during which the bus and the

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master are blocked, the memory interface continues the operation freeing the bus and
the master.
• If the address is protected, the write/erase is filtered (the write/erase requested is never
sent to the memory) and an error is raised.
• If the address is not protected but one or several conditions are not met, the operation
is aborted (the abort needs more time to be executed because the NVM and data
EEPROM need to return to default configuration) and an error is raised.
• If the address to write/erase is not protected and all rules are respected, and if the
memory interface is busy, the operation is put on hold to be executed as soon as
possible.

Option byte loading

• If a write/erase is ongoing, the Option byte loading waits for the end of operation then it
is executed: no other write/erase is accepted, even if waiting.
• If no write/erase is ongoing, the Option byte is executed directly (the read operation is
executed until the system reset goes to 0 as a result of the Option byte request).
This means that the Option byte loading has a bigger priority than the read and write/erase
operations. All other operations are executed in the order of request.

3.6.2 Sequence of operations

Read as data while write
If the master requests a read as data (see Read as data and pre-read) while a write
operation is ongoing, there are three different cases:
1. If the read is in a protected area, the RDERR flag is raised and the write operation
continues.
2. If the write operation uses a Single programming operation or a Multiple programming
operation (half page) and all addresses/data have been sent to the memory interface,
any read operation from the same bank is put on hold and will be executed when the
write operation is complete. It is important to emphasize that, during all the time spent
when the read waits to be executed, the master is blocked and no other operation can
be executed until the write and read operations are complete. However, any authorized
read operation from the other bank is accepted and served.
3. if the write operation uses a Multiple programming operation (half page) and not all
addresses/data have been sent to the memory interface, the read operation is not
accepted whatever the targeted bank, a hard fault is generated and the memory
interface continues to wait for the missing addresses/data to complete the write
operation.

Fetch while write

If the master fetches an instruction while a write is ongoing, the situation is similar to a read
as data (see step 1 and 2 above), but the last case is as follows:
• If the write operation uses a Multiple programming operation (half page) and not all
addresses/data have been sent to the memory interface, the write is aborted and it is
as it had never happened: the read operation is accepted whatever the targeted bank,
and the value is sent to the master.

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Write while another write operation is ongoing

If the master requests a write operation while another one is ongoing, there are different
cases:
• If the previous write uses a Single programming operation or a Multiple programming
operation (half page) and all addresses/data have been sent to the memory interface,
and if the new write is in a protected area, the WRPERR flag is raised, the previous
write continues and the new write is deleted.
• If the previous write uses a Single programming operation or a Multiple programming
operation (half page) and all addresses/data have been sent to the memory interface,
and if the new Single programming operation or Multiple programming operation (half
page) is not in a protected area, the new write is put on hold and will be executed when
the first write operation is complete. It is important to emphasize that the master who
requested the second write is blocked until the first write completes and the second has
stored the address and data internally.
• It is forbidden to request a new write when a mass erase is ongoing: during all the
steps of the mass erase, the data is not stored internally and the new data can change
the value stored as a protection, adding unwanted protections.
• It is possible to change configurations to prepare a new write operation when the first
operation uses a Single programming operation or a Multiple programming operation
(half page) and all addresses/data have been sent to the memory interface.

3.6.3 Change the number of wait states while reading

To change the number of wait states, it is necessary to write to the FLASH_ACR register.
The read/write of a register uses a different interface than the memory read/write. The
number of wait states cannot be changed while the memory interface is reading and the
memory interface cannot be stopped if a request is sent to the register interface. For this
reason, while a master is reading the memory and another master changes the wait state
number, the register interface will be locked until the change takes effect (until the readings
stop). To stop the master which is changing the number of wait states, it is important to read
back the content of the FLASH_ACR register: it is not possible to know the number of clock
cycles that will be necessary to change the number of wait states as it depends on the
customer code.

3.6.4 Power-down
To put the NVM in power-down, it is necessary to execute an unlocking sequence.
The following sequence is used to unlock RUN_PD bit of the FLASH_ACR register:
• Write PDKEY1 = 0x04152637 to the FLASH_PDKEYR register.
• Write PEKEY2 = 0xFAFBFCFD to the FLASH_PDKEYR register.
It is necessary to write the two keys without constraints about other read or write. No error is
generated if the wrong key is used: when both have been written, RUN_PD bit is unlocked
and can be written to 1, putting the NVM in power-down mode.
Resetting the RUN_PD flag to 0 (making the NVM available) automatically resets the
sequence and the two keys are requested to re-enable RUN_PD.

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3.7 Flash register description

Read registers
To read all internal registers of the memory interface, the user must read at the register
addresses. The content is available immediately (no wait state is necessary to read
registers). If the user tries to read the FLASH_ACR register after modifying the number of
wait states, the content will be available when the change takes effect (when no read is
done in the NVM memory, so the number of wait states is changed).
When no register is selected or when a wrong address is sent to the memory interface, a
zero value is sent as an answer. No error is generated.
When the master sends a request to read 8 or 16 bits, the memory interface returns the
corresponding part of the register on the data output bus. For example, if a register content
is 0x12345678 and the master sends a request to read the second byte, the output will be
0x34343434 (because 0x34 is the content of the second register byte when starting to count
bytes from zero). Similarly, if the master sends a request to read half-word zero of the
previous register, the output will be 0x56785678.

Write to registers
In the configuration registers of the memory interface, there are two types of bits:
• the bits that can be written to directly
• the bits needing a particular sequence to unlock.
To know which category a bit belongs to, see the next sections where every bit is explained
in details.
When it is possible to write directly to a register or a key-register, the user must write the
expected value at the register address. If the address is not correct, no error is generated. If
the user tries to modify a read-only register, no error is generated and the modify operation
does not take any effect. It is possible to write registers by byte, half-word and word.
When an unlock sequence is necessary, the correct values to use are given.

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3.7.1 Access control register (FLASH_ACR)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DISAB_BUF
PRE_READ

SLEEP_PD

LATENCY
RUN_PD

PRFTEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw

Bits 31:7 Reserved, must be kept at reset value

Bit 6 PRE_READ
This bit enables the pre-read.
0: The pre-read is disabled
1: The pre-read is enabled. The memory interface stores the last address read as data and
tries to read the next one when no other read or write or prefetch operation is ongoing.
Note: It is automatically reset every time the DISAB_BUF bit (in this register) is set to 1.
Bit 5 DISAB_BUF
This bit disables the buffers used as a cache during a read. This means that every read will
access the NVM even for an address already read (for example, the previous address). When
this bit is reset, the PRFTEN and PRE_READ bits are automatically reset, too.
0: The buffers are enabled
1: The buffers are disabled. Every time one NVM value is necessary, one new memory read
sequence has do be done.
Bit 4 RUN_PD
This bit determines if the NVM is in power-down mode or in idle mode when the device is in run
mode. It is possible to write this bit only when there is an unlocked writing of the
FLASH_PDKEYR register.
The correct sequence is explained in Section 3.6.4: Power-down. When writing this bit to 0, the
keys are automatically lost and a new unlock sequence is necessary to re-write it to 1.
0: When the device is in Run mode, the NVM is in Idle mode.
1: When the device is in Run mode, the NVM is in power-down mode.
Bit 3 SLEEP_PD
This bit allows to have the Flash program memory and data EEPROM in power-down mode or
in idle mode when the device is in Sleep mode.
0: When the device is in Sleep mode, the NVM is in Idle mode.
1: When the device is in Sleep mode, the NVM is in power-down mode.

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Bit 2 Reserved, must be kept at reset value

Bit 1 PRFTEN
This bit enables the prefetch. It is automatically reset every time the DISAB_BUF bit (in this
register) is set to 1. To know how the prefetch works, see the Fetch and prefetch section.
0: The prefetch is disabled.
1: The prefetch is enabled. The memory interface stores the last address fetched and tries to
read the next one when no other read or write operation is ongoing.
Bit 0 LATENCY
The value of this bit specifies if a 0 or 1 wait-state is necessary to read the NVM. The user must
write the correct value relative to the core frequency and the operation mode (power). The
correct value to use can be found in Table 15. No check is done to verify if the configuration is
correct.
To increase the clock frequency, the user has to change this bit to ‘1’, then to increase the
frequency. To reduce the clock frequency, the user has to decrease the frequency, then to
change this bit to ‘0’.
0: Zero wait state is used to read a word in the NVM.
1: One wait state is used to read a word in the NVM.

3.7.2 Program and erase control register (FLASH_PECR)

Address offset: 0x04
Reset value: 0x0000 0007
This register can only be written after a good write sequence done in FLASH_PEKEYR,
resetting the PELOCK bit.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OBL_LAUNCH
NZDISABLE

ERRIE

EOPIE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PARRALELBANK

PRG_LOCK
OPT_LOCK

PE_LOCK
ERASE

PROG
FPRG

DATA
FIX

Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rs rs rs

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Bits 31:24 Reserved, must be kept at reset value

Bit 23 NZDISABLE: Non-Zero check notification disable
When this bit is set, the application software does not check if the previous NVM content is
zero before programming a word or an half-page in the program or boot area. As a result,
the NOTZEROERR flag will always remain at 0 and no interrupt will be generated if the
above condition is met. By default, NZDISABLE is set to 0. It can be modified only when
PELOCK is 0.
0: error interrupt disabled
1: error interrupt enabled
On category 3 devices, this bit is not available and the behavior corresponds to
NZDISABLE=0.
Bits 22:19 Reserved, must be kept at reset value
Bit 18 OBL_LAUNCH
Setting this bit, the software requests the reloading of Option byte. The Option byte reloading
does not stop an ongoing modify operation, but it blocks new ones. The Option byte reloading
generates a system reset.
0: Option byte loading completed.
1: Option byte loading to be done.
Note: This bit can only be modified when OPTLOCK is 0. Locking OPTLOCK (or other lock
bits) does not reset this bit.
Bit 17 ERRIE: Error interrupt enable
0: Error interrupt disable.
1: Error interrupt enable.
Note: This bit can only be modified when PELOCK is 0. Locking PELOCK does not reset this
bit; the interrupt remains enabled.
Bit 16 EOPIE: End of programming interrupt enable
0: End of program interrupt disable.
1: End of program interrupt enable.
Note: This bit can only be modified when PELOCK is 0. Locking PELOCK does not reset this
bit; the interrupt remains enabled.
Bit 15 PARALLELBANK: Parallel bank programming mode.
This bit can be set and cleared by software when no program or erase operation is ongoing.
When it is set, 2 half-pages can be programmed, the first one in Bank 1 and the second one
in Bank 2.
0: Parallel bank mode disabled
1: Parallel bank mode enabled
This bit is available only for category 5 devices.
Bits 14:11 Reserved, must be kept at reset value
Bit 10 FPRG: Half Page programming mode
0: Half Page programming disabled.
1: Half Page programming enabled.
Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.
Bit 9 ERASE
0: No erase operation requested.
1: Erase operation requested.
Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.

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Bit 8 FIX
0: An erase phase is automatically performed, when necessary, before a program operation
in the data EEPROM and the Option bytes areas. The programming time can be:
Tprog (program operation) or 2 * Tprog (erase + program operations).
1: The program operation is always performed with a preliminary erase and the
programming time is: 2 * Tprog.
Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.
Bits 7:5 Reserved, must be kept at reset value
Bit 4 DATA
0: Data EEPROM not selected.
1: Data memory selected.
Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.This bit is
not very useful as the page and word have the same size in the data EEPROM, but it is
used to identify an erase operation (by page) from a word operation.
Bit 3 PROG
This bit is used for half-page program operations and for page erase operations in the Flash
program memory.
0: The Flash program memory is not selected.
1: The Flash program memory is selected.
Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.

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RM0377 Flash program memory and data EEPROM (FLASH)

Bit 2 OPTLOCK: Option bytes lock

This bit blocks the write/erase operations to the user Option bytes area and the
OBL_LAUNCH bit (in this register). It can only be written to 1 to re-lock. To reset to 0, a correct
sequence of unlock with OPTKEYR register is necessary (see Unlocking the Option bytes
area), with PELOCK bit at 0. If the sequence is not correct, the bit will be locked until the next
system reset and a hard fault is generated. If the sequence is executed when PELOCK = 1,
the bit remains locked and no hard fault is generated. The keys to unlock are:
– First key:0xFBEAD9C8
– Second key: 0x24252627
0: The write and erase operations in the Option bytes area are disabled.
1: The write and erase operations in the Option bytes area are enabled.
Note: This bit is set when PELOCK is set.
Bit 1 PRGLOCK: Program memory lock
This bit blocks the write/erase operations to the Flash program memory. It can only be written
to 1 to re-lock. To reset to 0, a correct sequence of unlock with PRGKEYR register is
necessary (see Unlocking the Flash program memory), with PELOCK bit at 0. If the sequence
is not correct, the bit will be locked until the next system reset and a hard fault is generated. If
the sequence is executed when PELOCK = 1, the bit remains locked and no hard fault is
generated. The keys to unlock are:
– First key:0x8C9DAEBF
– Second key: 0x13141516
0: The write and erase operations in the Flash program memory are disabled.
1: The write and erase operations in the Flash program memory are enabled.
Note: This bit is set when PELOCK is set.
Bit 0 PELOCK: FLASH_PECR lock
This bit locks the FLASH_PECR register. It can only be written to 1 to re-lock. To reset to 0, a
correct sequence of unlock with PEKEYR register (see Unlocking the data EEPROM and the
FLASH_PECR register) is necessary. If the sequence is not correct, the bit will be locked until
the next system reset and one hard fault is generated. The keys to unlock are:
– First key: 0x89ABCDEF
– Second key: 0x02030405
0: The FLASH_PECR register is unlocked; it can be modified and the other bits unlocked.
Data write/erase operations are enabled.
1: The FLASH_PECR register is locked and no write/erase operation can start.

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3.7.3 Power-down key register (FLASH_PDKEYR)

Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLASH_PDKEYR[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASH_PDKEYR15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with
0x04152637 and the second one with 0xFAFBFCFD), the write size being that of a word, it is
possible to unlock the RUN_PD bit of the FLASH_ACR register. For more details, refer to
Section 3.6.4: Power-down.

3.7.4 PECR unlock key register (FLASH_PEKEYR)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLASH_PEKEYR[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASH_PEKEYR15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with
0x89ABCDEF and the second one with 0x02030405), the write size being that of a word, it is
possible to unlock the FLASH_PECR register. For more details, refer to Unlocking the data
EEPROM and the FLASH_PECR register.

3.7.5 Program and erase key register (FLASH_PRGKEYR)

Address offset: 0x10
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLASH_PRGKEYR[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASH_PRGKEYR15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with
0x8C9DAEBF and the second one with 0x13141516), the write size being that of a word, it is
possible to unlock the Flash program memory. The sequence can only be executed when
PELOCK is already unlocked. For more details, refer to Unlocking the Flash program memory.

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RM0377 Flash program memory and data EEPROM (FLASH)

3.7.6 Option bytes unlock key register (FLASH_OPTKEYR)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FLASH_OPTKEYR[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FLASH_OPTKEYR[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with
0xFBEAD9C8 and the second one with 0x24252627), the write size being that of a word, it is
possible to unlock the Option bytes area and the OBL_LAUNCH bit. The sequence can only be
executed when PELOCK is already unlocked. For more details, refer to Unlocking the Option
bytes area.

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3.7.7 Status register (FLASH_SR)

Address offset: 0x018
Reset value: 0x0000 000C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

NOTZERO
FWWER

ERR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rc_w1 rc_w1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTVERR

WRPERR
PGAERR
SIZERR
RDERR

ENDHV
READY

EOP

BSY
Res. Res. Res. Res. Res. Res. Res.

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 r r rc_w1 r

Bits 31:18 Reserved, must be kept at reset value

Bit 17 FWWERR
This bit is set by hardware when a write/erase operation is aborted to perform a fetch. This is
not a real error, but it is used to inform that the write/erase operation did not execute. To reset
this flag, write 1.
0: No write/erase operation aborted to perform a fetch.
1: A write/erase operation aborted to perform a fetch.
Bit 16 NOTZEROERR
This bit is set by hardware when a program in the Flash program or System Memory tries to
overwrite a not-zero area. In category 3 devices, this flag does not stop the program operation:
it is possible that the value found when reading back is not what the user wrote. To reset this
flag, write 1.
0: The write operation is done in an erased region or the memory interface can apply an
erase before a write.
1: The write operation is attempting to write to a not-erased region and the memory interface
cannot apply an erase before a write. Except for category 3 devices, the modify operation is
aborted. For category 3 devices a not-zero error does not abort the write/erase operation.
Bits 15:14 Reserved, must be kept at reset value
Bit 13 RDERR
This bit is set by hardware when the user tries to read an area protected by PcROP. It is
cleared by writing 1.
0: No read protection error happened.
1: One read protection error happened.
Bit 12 Reserved, must be kept at reset value
Bit 11 OPTVERR: Option valid error
This bit is set by hardware when, during an Option byte loading, there was a mismatch for one
or more configurations. It means that the configurations loaded may be different from what the
user wrote in the memory. It is cleared by writing 1.
If an error happens while loading the protections (WPRMOD, RDPROT, WRPROT), the source
code in the Flash program memory may not execute correctly.
0: No error happened during the Option bytes loading.
1: One or more errors happened during the Option bytes loading.

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RM0377 Flash program memory and data EEPROM (FLASH)

Bit 10 SIZERR: Size error

This bit is set by hardware when the size of data to program is not correct. It is cleared by
writing 1.
0: No size error happened.
1: One size error happened.
Bit 9 PGAERR: Programming alignment error
This bit is set by hardware when an alignment error has happened: the first word of a half-page
operation is not aligned to a half-page, or one of the following words in a half-page operation
does not belong to the same half-page as the first word. When this bit is set, it has to be
cleared before writing 1, and no half-page operation is accepted.
0: No alignment error happened.
1: One alignment error happened.
Bit 8 WRPERR: Write protection error
This bit is set by hardware when an address to be programmed or erased is write-protected. It
is cleared by writing 1.
0: No protection error happened.
1: One protection error happened.
Bits 7:4 Reserved, must be kept at reset value
Bit 3 READY
When this bit is set, the NVM is ready for read and write/erase operations.
0: The NVM is not ready. No read or write/erase operation can be done.
1: The NVM is ready.
Bit 2 ENDHV
This bit is set and reset by hardware.
0: High voltage is executing a write/erase operation in the NVM.
1: High voltage is off, no write/erase operation is ongoing.
Bit 1 EOP: End of program
This bit is set by hardware at the end of a write or erase operation when the operation has not
been aborted. It is reset by software (writing 1).
0: No EOP operation occurred
1: An EOP event occurred. An interrupt is generated if EOPIE bit is set.
Bit 0 BSY: Memory interface busy
Write/erase operations are in progress.
0: No write/erase operation is in progress.
1: A write/erase operation is in progress.

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3.7.8 Option bytes register (FLASH_OPTR)

Address offset 0x1C
Reset value: 0xX0XX 0XXX. It depends on the value programmed in the option bytes.
During production, it is set to 0x8070 00AA.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BOR_LEV[3:0]
nRST_STDBY
nBOOT_SEL

nRTS_STOP

WDG_SW
nBOOT1

nBOOT0

BFB2
Res. Res. Res. Res. Res.

r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WPRMOD

RDPROT
Res. Res. Res. Res. Res. Res. Res.

r r r r r r r r r

Bit 31 nBOOT1
This bit is used in conjunction with BOOT0 signal to configure the device boot mode (see
Section 2.4: Boot configuration).
If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1.
If the device is protected at Level 2, BOOT0 and nBOOT1 lose their meaning: the boot is
always forced in the Flash program memory.
Bit 30 nBOOT0
This bit is available on category 1 devices only.
When nBOOT_SEL is set, nBOOT0 bit defines the value of BOOT0 signal that is used to
select the device boot mode (see Section 2.4: Boot configuration).
Bit 29 nBOOT_SEL
0: BOOT0 signal is defined by BOOT0 pin value (default mode)
1: BOOT0 signal is defined by nBOOT0 option bit
This bit is available on category 1 devices only. It is held at ‘0’ on other devices.
Bits 28:24 Reserved, must be kept at reset value
Bit 23 BFB2: Boot from Bank 2
This bit contains the user option byte loaded by the device OPTL. This bit is used to boot
from Bank 2. Actually this bit indicates whether a boot from System memory or from Flash
program memory has been selected. If boot from System memory is selected, the jump to
Bank 1 or Bank 2 is performed by software depending on the value of the first two words at
the beginning of each bank. When BFB2 is set, user Flash memory is not aliased at address
0. Instead, the System Flash memory is aliased at address 0 through MEM_MODE bits in
SYSCFG_CFGR1. When BFB2 is set, the PRIMASK is set at code startup. It prevents the
activation of all exceptions that have a configurable priority.
0: BOOT from Bank 1 (category 5 devices) or USER Flash memory (other categories)
1: BOOT from System memory
Note: This bit is available in category 5 devices only.
Bit 22 nRST_STDBY
If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1.
0: Reset generated when entering the Standby mode.
1: No reset generated.

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Bit 21 nRST_STOP
If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1.
0: Reset generated when entering the Stop mode.
1: No reset generated.
Bit 20 WDG_SW
If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1.
0: Hardware watchdog.
1: Software watchdog.
Bits 19:16 BOR_LEV: Brownout reset threshold level
These bits reset the threshold level for a 1.45 V to 1.55 V voltage range (power-down only). In
this particular case, VDD must have been above VBOR0 to start the device OBL sequence, in
order to disable the BOR. The power-down is then monitored by the PDR. If the BOR is
disabled, a “grey zone” exists between 1.65 V and the VPDR threshold (this means VDD can
be below the minimum operating voltage (1.65 V) without any reset until the VPDR threshold).
If there is a mismatch on this configuration during the Option bytes loading, it is loaded with
0x8.
0xxx: BOR OFF. This is the reset threshold level for the 1.45 V - 1.55 V voltage range
(power-down only).
In this particular case, VDD must have been above BOR LEVEL 1 to start the device OBL
sequence in order to disable the BOR. The power-down is then monitored by the PDR.
Note: If the BOR is disabled, a "grey zone" exists between 1.65 V and the VPDR threshold
(this means that VDD may be below the minimum operating voltage (1.65 V) without
causing a reset until it crosses the VPDR threshold)
1000: BOR LEVEL 1 is the reset threshold level for VBOR0 (around 1.8 V)
1001: BOR LEVEL 2 is the reset threshold level for VBOR1 (around 2.0 V)
1010: BOR LEVEL 3 is the reset threshold level for VBOR2 (around 2.5 V)
1011: BOR LEVEL 4 is the reset threshold level for VBOR3 (around 2.7 V).
1100: BOR LEVEL 5 is the reset threshold level for VBOR4 (around 3.0 V)
Note: Refer to the device datasheets for the exact definition of BOR levels.
Bits 15:9 Reserved, must be kept at reset value
Bit 8 WPRMOD
This bit selects between write and read protection of Flash program memory sectors. If there is
a mismatch on this configuration during the Option bytes loading, it is loaded with 1.
0: PCROP disabled. The WRPROT bits are used as a write protection on a sector.
1: PCROP enabled. The WRPROT bits are used as a read protection on a sector.
Bits 7:0 RDPROT: Read protection
These bits contain the protection level loaded during the Option byte loading. If there is a
mismatch on this configuration during the Option bytes loading, it is loaded with 0x00.
0xAA: Level 0
0xCC: Level 2
Others: Level 1

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3.7.9 Write protection register 1 (FLASH_WRPROT1)

Address offset: 0x20
Reset value: 0xXXXX XXXX. It depends on the value programmed in the option bytes.
During production, it is set to 0x0000 0000.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WRPROT1[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRPROT1[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 WRPROT1: Write protection

– If WPRMOD = 0 in the FLASH_OPTR register, these bits contain the write protection
configuration for the Flash memory (every bit protects a 4-Kbyte sector: the first bit protects
the first sector, the second bit protects the second page and so on). In this case, 1 = sector
protected, 0 = no protection.
– If WPRMOD = 1, these bits are used to protect from reading as data (see Read as data and
pre-read), and then also from writing, with the same granularity and with the same
combination of bits and sectors. The read protection does not protect against a fetch. In this
case, 1 = no protection, 0 = sector protected.
When WPRMOD = 0, it is possible to set or reset these bits without any limitation changing
the relative Option bytes.
When WPRMOD = 1, it is only possible to increase the protection, which means that the user
can add zeros but cannot add ones.
The mass erase deletes the WPRMOD bits but does not delete the content of this register.
After a mass erase, the user must write the relative Option bytes with zeros to remove
completely the write protections.
If there is a mismatch on this configuration during the Option bytes loading, and the content of
WPRMOD in the FLASH_OPTR register is:
1, this configuration is loaded with 0x0000.
0, this configuration is loaded with 0xFFFF.
If there was a mismatch when WPRMOD was loaded in the FLASH_OPTR register (thus
loaded with ones), the register is loaded with 0x0000.

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RM0377 Flash program memory and data EEPROM (FLASH)

3.7.10 Write protection register 2 (FLASH_WRPROT2)

Address offset: 0x80
Reset value: 0x 0000 XXXX. It depends on the value programmed in the option bytes.
During production, it is set to 0x0000 0000.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WRPROT2 [15:0]
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value

Bits 15:0 WRPROT2: Write protection
– If WPRMOD = 0 in the FLASH_OPTR register, these bits contain the write protection
configuration for the Flash memory (every bit protects a 4-Kbyte sector: the first bit protects
the first sector, the second bit protects the second page and so on). In this case, 1 = sector
protected, 0 = no protection.
– If WPRMOD = 1, these bits are used to protect from reading as data (see Read as data and
pre-read), and then also from writing, with the same granularity and with the same
combination of bits and sectors. The read protection does not protect against a fetch. In this
case, 1 = no protection, 0 = sector protected.
When WPRMOD = 0, it is possible to set or reset these bits without any limitation changing
the relative Option bytes.
When WPRMOD = 1, it is only possible to increase the protection, which means that the user
can add zeros but cannot add ones.
The mass erase deletes the WPRMOD bits but does not delete the content of this register.
After a mass erase, the user must write the relative Option bytes with zeros to remove
completely the write protections.
If there is a mismatch on this configuration during the Option bytes loading, and the content of
WPRMOD in the FLASH_OPTR register is:
1, this configuration is loaded with 0x0000.
0, this configuration is loaded with 0xFFFF.
If there was a mismatch when WPRMOD was loaded in the FLASH_OPTR register (thus
loaded with ones), the register is loaded with 0x0000.

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3.7.11 Flash register map

Table 25. Flash interface - register map and reset values

Off- Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
set

DESAB_8BUF
PRE_READ

SLEEP_PD

LATENCY
RUN_PD

PRFTEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
FLASH_ACR
0x00

0x00000000 0 0 0 0 0 0

PARALLELBANK
OBL_LAUNCH
NZDISABLE

PRGLOCK
OPTLOCK

PELOCK
ERASE
ERRIE
EOPIE

FPRG

DATA
PRG
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

Res.
Res.
Res.
FIX
FLASH_PECR
0x004

0x00000007 0 0 0 0 0 0 0 0 0 0 1 1 1

FLASH_
PDKEYR[31:0]
0x008 PDKEYR

0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASH_
PKEYR[31:0]
0x00C PKEYR

0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASH_
PRGKEYR[31:0]
PRGKEYR
0x010
0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASH_
OPTKEYR[31:0]
OPTKEYR
0x014
0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NOTZEROERR

OPTVERR
FWWERR

WRPERR
PGAERR
SIZERR
RDERR

ENDHV
READY

EOP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.

Res.
Res.
Res.
Res.

BSY
FLASH_SR
0x018

0x0000000C 0 0 0 0 0 0 0 1 1 0 0
nBOOT_SEL

nRST_STOP
nRST_STBY

WPRMOD
WDG_SW
nBOOT1
nBOOT0

BFB2
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.

FLASH_OPTR BOR_LEV:0] RDPROT[7:0]

0x01C

0xXXXX0XXX X X X X X X X X X X X X X X X X X X X X

FLASH_
WRPROT1[31:0]
WRPROT1
0x020
0x0000XXXX X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X

FLASH_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

WRPROT2[15:0]
WRPROT2
0x080
0xXXX 0000 X X X X X X X X X X X X X X X X

Refer to Section 2.2 on page 51 for the register boundary addresses.

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RM0377 Flash program memory and data EEPROM (FLASH)

3.8 Option bytes

On the NVM, an area is reserved to store a set of Option bytes which are used to configure
the product. Some option bytes are written in factory while others can be configured by the
end user.
The configuration managed by an end user is stored the Option bytes area (32 bytes). To be
taken into account, a boot sequence must be executed. This boot sequence occurs after a
power-on reset when exiting from Standby mode, or by reloading the option bytes by
software (Section 3.8.3: Reloading Option bytes by software). The Option bytes are
automatically loaded during the boot. They are used to set the content of the FLASH_OPTR
and FLASH_WRPROTx registers.
Every word, when read during the boot, is interpreted as explained in Table 26: the lower 16
bits contain the data to copy in the memory interface registers and the higher 16 bits contain
the complemented value used to check that the data read are correct. If there is an error
during loading operation (the higher part is not the complement of the lower one), the default
value is stored in the registers. The check is done by configuration. Section 3.8.2 explains
what happens when there is a mismatch on protection configurations.
During a write, no control is done to check if the higher part of a word is the complement of
the lower part: this check must be performed by the user application.

Table 26. Option byte format

31-24 23-16 15-8 7-0

Complemented Complemented
Option byte 1 Option byte 0
Option byte 1 Option byte 0

3.8.1 Option bytes description

The Option bytes can be read from the memory locations listed in Table 27.

Table 27. Option byte organization

Address [31:16] [15:0]

0x1FF8 0000 nFLASH_OPTR[15:0] FLASH_OPTR[15:0]

0x1FF8 0004 nFLASH_OPTR[31:16] FLASH_OPTR[31:16]
0x1FF8 0008 nFLASH_WRPROT1[15:0] FLASH_WRPROT1[15:0]
0x1FF8 000C nFLASH_WRPROT1[31:16] FLASH_WRPROT1[31:16]
0x1FF8 0010 nFLASH_WRPROT2[15:0] FLASH_WRPROT2[15:0]

Refer to Section 3.7.8: Option bytes register (FLASH_OPTR) and Section 3.7.9: Write
protection register 1 (FLASH_WRPROT1) for the meaning of each bit.

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3.8.2 Mismatch when loading protection flags

When there is a mismatch during an Option byte loading, the memory interface sets the
default value in registers.
In the Option byte area, there are three kinds of protection information:
• RDPROT
This configuration sets the Protection Level. As explained in the next section, changing
this level changes the possibility to access the NVM and the product. The default value
is Level 1. It is possible to return to Level 0 from Level 1 but all content of the data
EEPROM and Flash program memory will be deleted (mass erase). It is always
possible to move to Level 2, but not to change protection levels when Level 2 is loaded
(if the user writes in Option bytes a Level 2 but never reloads the Option bytes, the
memory interface continues to works in the previous level and it is possible to write
again a different protection level in the Option bytes area).
• WPRMOD
This flag is independent from RDPROT and set if the Flash program memory is
protected from read or write. When this flag is 1 (read protection), the only way to reset
it is to request a mass erase (also returning to Level 0). This means that there is no
way to remove the read protection when the device is in Level 2. The default value is 1
(read protection) and a mismatch on this bit also generates the default value for the
WRPROT configuration.
• WRPROT
This configuration sets which sectors of the Flash program memory are read- or write-
protected. If the read protection is disabled (WPRMOD = 0), 1 must be set in the right
bit to protect a sector. If the read protection is enabled (WPRMOD = 1), 0 must be in
the right bit to protect a sector. If during boot there is a mismatch on WPRMOD, this
configuration is loaded with zeros so that all sectors of the Flash program memory are
protected from read. If WPRMOD has been read correctly but there is a mismatch
reading WRPROT, the register will be loaded with zeros if WPRMOD = 1, and with
ones if WPRMOD = 0.
Thus, a mismatch on a protection can have a serious impact on the normal execution of
code (if it is in the Flash program memory): when there is a read protection, only a fetch is
possible. In the Flash program memory, some values are read as data (the constants, for
example) during a code execution; protecting all sectors from read prevents the execution of
the application code from the Flash program memory.

3.8.3 Reloading Option bytes by software

It is possible to request an Option byte reloading by setting the OBL_LAUNCH flag to 1 in
the FLASH_PECR register. This bit can be set only when OPTLOCK = 0 (and PELOCK =
0). Setting this bit, the ongoing write/erase is completed, but no new write/erase or read
operation is executed.
The reload of Option bytes generates a reset of the device but without a power-down. The
options must be reloaded after every change of the Option bytes in the NVM, so that the
changes can apply. It is possible to reload by setting OBL_LAUNCH, or with a power-on of
the V18 domain (i.e. after a power-on reset or after a standby).

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4 Cyclic redundancy check calculation unit (CRC)

4.1 Introduction
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16-
or 32-bit data word and a generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the functional safety standards, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.

4.2 CRC main features

• Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1
• Alternatively, uses fully programmable polynomial with programmable size (7, 8, 16, 32
bits)
• Handles 8-,16-, 32-bit data size
• Programmable CRC initial value
• Single input/output 32-bit data register
• Input buffer to avoid bus stall during calculation
• CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size
• General-purpose 8-bit register (can be used for temporary storage)
• Reversibility option on I/O data
• Accessed through AHB slave peripheral by 32-bit words only, with the exception of
CRC_DR register that can be accessed by words, right-aligned half-words and right-
aligned bytes

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4.3 CRC functional description

4.3.1 CRC block diagram

Figure 7. CRC calculation unit block diagram

32-bit AHB bus

read access write access 32-bit accesses

Data register Data register

crc_hclk
(output) (input)
CRC_INIT

CRC_CR
CRC computation
CRC_POL

CRC_IDR

MS19882V3

4.3.2 CRC internal signals

Table 28. CRC internal input/output signals

Signal name Signal type Description

crc_hclk Digital input AHB clock

4.3.3 CRC operation

The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to
input new data (write access), and holds the result of the previous CRC calculation (read
access).
Each write operation to the data register creates a combination of the previous CRC value
(stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data
word or byte by byte depending on the format of the data being written.
The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned
byte. For the other registers only 32-bit access is allowed.
The duration of the computation depends on data width:
• 4 AHB clock cycles for 32 bits
• 2 AHB clock cycles for 16 bits
• 1 AHB clock cycles for 8 bits
An input buffer allows a second data to be immediately written without waiting for any wait
states due to the previous CRC calculation.

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The data size can be dynamically adjusted to minimize the number of write accesses for a
given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write
followed by a byte write.
The input data can be reversed, to manage the various endianness schemes. The reversing
operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits
in the CRC_CR register.
For example: input data 0x1A2B3C4D is used for CRC calculation as:
• 0x58D43CB2 with bit-reversal done by byte
• 0xD458B23C with bit-reversal done by half-word
• 0xB23CD458 with bit-reversal done on the full word
The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register.
The operation is done at bit level: for example, output data 0x11223344 is converted into
0x22CC4488.
The CRC calculator can be initialized to a programmable value using the RESET control bit
in the CRC_CR register (the default value is 0xFFFFFFFF).
The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR
register is automatically initialized upon CRC_INIT register write access.
The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It
is not affected by the RESET bit in the CRC_CR register.

Polynomial programmability
The polynomial coefficients are fully programmable through the CRC_POL register, and the
polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the
POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported.
Note: The type of an even polynomial is X+X2+..+Xn, while the type of an odd polynomial is
1+X+X2+..+Xn.
If the CRC data is less than 32-bit, its value can be read from the least significant bits of the
CRC_DR register.
To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can
not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the
application must either reset it or perform a CRC_DR read before changing the polynomial.
The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7.

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4.4 CRC registers

The CRC_DR register can be accessed by words, right-aligned half-words and right-aligned
bytes. For the other registers only 32-bit accesses are allowed.

4.4.1 CRC data register (CRC_DR)

Address offset: 0x00
Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DR[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DR[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DR[31:0]: Data register bits

This register is used to write new data to the CRC calculator.
It holds the previous CRC calculation result when it is read.
If the data size is less than 32 bits, the least significant bits are used to write/read the correct
value.

4.4.2 CRC independent data register (CRC_IDR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. IDR[7:0]

rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 IDR[7:0]: General-purpose 8-bit data register bits
These bits can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR
register

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4.4.3 CRC control register (CRC_CR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_
Res. Res. Res. Res. Res. Res. Res. Res. REV_IN[1:0] POLYSIZE[1:0] Res. Res. RESET
OUT
rw rw rw rw rw rs

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 REV_OUT: Reverse output data
This bit controls the reversal of the bit order of the output data.
0: Bit order not affected
1: Bit-reversed output format
Bits 6:5 REV_IN[1:0]: Reverse input data
These bits control the reversal of the bit order of the input data
00: Bit order not affected
01: Bit reversal done by byte
10: Bit reversal done by half-word
11: Bit reversal done by word
Bits 4:3 POLYSIZE[1:0]: Polynomial size
These bits control the size of the polynomial.
00: 32 bit polynomial
01: 16 bit polynomial
10: 8 bit polynomial
11: 7 bit polynomial
Bits 2:1 Reserved, must be kept at reset value.
Bit 0 RESET: RESET bit
This bit is set by software to reset the CRC calculation unit and set the data register to the
value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by
hardware

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4.4.4 CRC initial value (CRC_INIT)

Address offset: 0x10
Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CRC_INIT[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC_INIT[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value

This register is used to write the CRC initial value.

4.4.5 CRC polynomial (CRC_POL)

Address offset: 0x14
Reset value: 0x04C1 1DB7

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

POL[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

POL[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 POL[31:0]: Programmable polynomial

This register is used to write the coefficients of the polynomial to be used for CRC
calculation.
If the polynomial size is less than 32 bits, the least significant bits have to be used to program
the correct value.

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4.4.6 CRC register map

Table 29. CRC register map and reset values

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

CRC_DR DR[31:0]
0x00
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRC_IDR IDR[7:0]
0x04
Reset value 0 0 0 0 0 0 0 0

POLYSIZE[1:0]
REV_IN[1:0]
REV_OUT

RESET
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
CRC_CR
0x08

Reset value 0 0 0 0 0 0

CRC_INIT CRC_INIT[31:0]
0x10
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CRC_POL POL[31:0]
0x14
Reset value 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1

Refer to Section 2.2 on page 51 for the register boundary addresses.

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5 Firewall (FW)

5.1 Introduction
The Firewall is made to protect a specific part of code or data into the Non-Volatile Memory,
and/or to protect the Volatile data into the SRAM from the rest of the code executed outside
the protected area.

5.2 Firewall main features

• The code to protect by the Firewall (Code Segment) may be located in:
– The Flash program memory map
– The SRAM memory, if declared as an executable protected area during the
Firewall configuration step.
• The data to protect can be located either
– in the Flash program or the Data EEPROM memory (non-volatile data segment)
– in the SRAM memory (volatile data segment)
The software can access these protected areas once the Firewall is opened. The Firewall
can be opened or closed using a mechanism based on “call gate” (Refer to Opening the
Firewall).
The start address of each segment and its respective length must be configured before
enabling the Firewall (Refer to Section 5.3.5: Firewall initialization).
Each illegal access into these protected segments (if the Firewall is enabled) generates a
reset which immediately kills the detected intrusion.
Any DMA access to protected segments is forbidden whatever the Firewall state (opened or
closed). It is considered as an illegal access and generates a reset.

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5.3 Firewall functional description

5.3.1 Firewall AMBA bus snoop

The Firewall peripheral is snooping the AMBA buses on which the memories (volatile and
non-volatile) are connected. A global architecture view is illustrated in Figure 8.

Figure 8. STM32L0x1 firewall connection schematics

I
N
AHB Slave T
AHB Master 1 E Flash program
R memory and data
CORTEX M0+
F EEPROM
A
B C
U E
S

AHB Master 2 M FIREWALL

DMA A
T
R
I
X
SRAM
AHB Slave

MS32388V3

5.3.2 Functional requirements

There are several requirements to guaranty the highest security level by the application
code/data which needs to be protected by the Firewall and to avoid unwanted Firewall alarm
(reset generation).

Debug consideration
In debug mode, if the Firewall is opened, the accesses by the debugger to the protected
segments are not blocked. For this reason, the Read out level 2 protection must be active in
conjunction with the Firewall implementation.
If the debug is needed, it is possible to proceed in the following way:
• A dummy code having the same API as the protected code may be developed during
the development phase of the final user code. This dummy code may send back
coherent answers (in terms of function and potentially timing if needed), as the
protected code should do in production phase.
• In the development phase, the protected code can be given to the customer-end under
NDA agreement and its software can be developed in level 0 protection. The customer-
end code needs to embed an IAP located in a write protected segment in order to allow
future code updates when the production parts will be Level 2 ROP.

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Write protection
In order to offer a maximum security level, the following points need to be respected:
• It is mandatory to keep a write protection on the part of the code enabling the Firewall.
This activation code should be located outside the segments protected by the Firewall.
• The write protection is also mandatory on the code segment protected by the Firewall.
• The page including the reset vector must be write-protected.

Interrupts management
The code protected by the Firewall must not be interruptible. It is up to the user code to
disable any interrupt source before executing the code protected by the Firewall. If this
constraint is not respected, if an interrupt comes while the protected code is executed
(Firewall opened), the Firewall will be closed as soon as the interrupt subroutine is
executed. When the code returns back to the protected code area, a Firewall alarm will raise
since the “call gate” sequence will not be applied and a reset will be generated.
Concerning the interrupt vectors and the first user page in the Flash program memory:
• If the first user page (including the reset vector) is protected by the Firewall, the NVIC
vector should be reprogrammed outside the protected segment.
• If the first user page is not protected by the Firewall, the interrupt vectors may be kept
at this location.
There is no interrupt generated by the Firewall.

5.3.3 Firewall segments

The Firewall has been designed to protect three different segment areas:

Code segment
This segment is located into the Flash program memory. It should contain the code to
execute which requires the Firewall protection. The segment must be reached using the
“call gate” entry sequence to open the Firewall. A system reset is generated if the “call gate”
entry sequence is not respected (refer to Opening the Firewall) and if the Firewall is enabled
using the FWDIS bit in the system configuration register. The length of the segment and the
segment base address must be configured before enabling the Firewall (refer to
Section 5.3.5: Firewall initialization).

Non-volatile data segment

This segment contains non-volatile data used by the protected code which must be
protected by the Firewall. The access to this segment is defined into Section 5.3.4: Segment
accesses and properties. The Firewall must be opened before accessing the data in this
area. The Non-Volatile data segment should be located into the Flash program or 2-Kbyte
Data EEPROM memory. The segment length and the base address of the segment must be
configured before enabling the Firewall (refer to Section 5.3.5: Firewall initialization).

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Volatile data segment

Volatile data used by the protected code located into the code segment must be defined into
the SRAM memory. The access to this segment is defined into the Section 5.3.4: Segment
accesses and properties. Depending on the Volatile data segment configuration, the
Firewall must be opened or not before accessing this segment area. The segment length
and the base address of the segment as well as the segment options must be configured
before enabling the Firewall (refer to Section 5.3.5: Firewall initialization).
The Volatile data segment can also be defined as executable (for the code execution) or
shared using two bit of the Firewall configuration register (bit VDS for the volatile data
sharing option and bit VDE for the volatile data execution capability). For more details, refer
to Table 30.

5.3.4 Segment accesses and properties

All DMA accesses to the protected segments are forbidden, whatever the Firewall state, and
generate a system reset.

Segment access depending on the Firewall state

Each of the three segments has specific properties which are presented in Table 30.

Table 30. Segment accesses according to the Firewall state

Firewall opened Firewall closed Firewall disabled
Segment
access allowed access allowed access allowed

No access allowed. All accesses are allowed

Any access to the segment (according to the EEPROM
Code segment Read and execute
(except the “call gate” entry) protection properties in which
generates a system reset the code is located)

All accesses are allowed

Non-volatile data (according to the EEPROM
Read and write No access allowed
segment protection properties in which
the code is located)
No access allowed if VDS = 0
and VDE = 0 into the Firewall
configuration register
Read and Write
Read/write/execute accesses
Volatile data Execute if VDE = 1 and
allowed if VDS = 1 (whatever All accesses are allowed
segment VDS = 0 into the Firewall
VDE bit value)
configuration register
Execute if VDE = 1 and VDS = 0
but with a “call gate” entry to
open the Firewall at first.

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The Volatile data segment is a bit different from the two others. The segment can be:
• Shared (VDS bit in the register)
It means that the area and the data located into this segment can be shared between
the protected code and the user code executed in a non-protected area. The access is
allowed whether the Firewall is opened or closed or disabled.
The VDS bit gets priority over the VDE bit, this last bit value being ignored in such a
case. It means that the Volatile data segment can execute parts of code located there
without any need to open the Firewall before executing the code.
• Execute
The VDE bit is considered as soon as the VDS bit = 0 in the FW_CR register. If the
VDS bit = 1, refer to the description above on the Volatile data segment sharing. If VDS
= 0 and VDE = 1, the Volatile data segment is executable. To avoid a system reset
generation from the Firewall, the “call gate” sequence should be applied on the Volatile
data segment to open the Firewall as an entry point for the code execution.

Segments properties
Each segment has a specific length register to define the segment size to be protected by
the Firewall: CSL register for the Code segment length register, NVDSL for the Non-volatile
data segment length register, and VDSL register for the Volatile data segment length
register. Granularity and area ranges for each of the segments are presented in Table 31.

Table 31. Segment granularity and area ranges

Segment Granularity Area range

Code segment 256 byte up to 64 Kbytes - 256 bytes

Non-volatile data segment 256 byte up to 64 Kbytes - 256 bytes
Volatile data segment 64 byte 8 Kbytes - 64 bytes

5.3.5 Firewall initialization

The initialization phase should take place at the beginning of the user code execution (refer
to the Write protection).
The initialization phase consists of setting up the addresses and the lengths of each
segment which needs to be protected by the Firewall. It must be done before enabling the
Firewall, because the enabling bit can be written once. Thus, when the Firewall is enabled, it
cannot be disabled anymore until the next system reset.
Once the Firewall is enabled, the accesses to the address and length segments are no
longer possible. All write attempts are discarded.
A segment defined with a length equal to 0 is not considered as protected by the Firewall.
As a consequence, there is no reset generation from the Firewall when an access to the
base address of this segment is performed.
After a reset, the Firewall is disabled by default (FWDIS bit in the SYSCFG register is set). It
has to be cleared to enable the Firewall feature.

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Below is the initialization procedure to follow:

1. Configure the RCC to enable the clock to the Firewall module
2. Configure the RCC to enable the clock of the system configuration registers
3. Set the base address and length of each segment (CSSA, CSL, NVDSSA, NVDSL,
VDSSA, VDSL registers)
4. Set the configuration register of the Firewall (FW_CR register)
5. Enable the Firewall clearing the FWDIS bit in the system configuration register.
The Firewall configuration register (FW_CR register) is the only one which can be managed
in a dynamic way even if the Firewall is enabled:
• when the Non-Volatile data segment is undefined (meaning the NVDSL register is
equal to 0), the accesses to this register are possible whatever the Firewall state
(opened or closed).
• when the Non-Volatile data segment is defined (meaning the NVDSL register is
different from 0), the accesses to this register are only possible when the Firewall is
opened.

5.3.6 Firewall states

The Firewall has three different states as shown in Figure 9:
• Disabled: The FWDIS bit is set by default after the reset. The Firewall is not active.
• Closed: The Firewall protects the accesses to the three segments (Code, Non-volatile
data, and Volatile data segments).
• Opened: The Firewall allows access to the protected segments as defined in
Section 5.3.4: Segment accesses and properties.

Figure 9. Firewall functional states

Firewall disable
(reset)

Illegal accesses to
the protected Enable the firewall Protected code jumps
segments (FWDIS = 0) to an unprotected
segment and FPA = 0

‘‘call gate’’ entry

Firewall Firewall
closed opened

Code protected jumps

to unprotected
segments

MS32390V4

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Opening the Firewall

As soon as the Firewall is enabled, it is closed. It means that most of the accesses to the
protected segments are forbidden (refer to Section 5.3.4: Segment accesses and
properties). In order to open the Firewall to interact with the protected segments, it is
mandatory to apply the “call gate” sequence described hereafter.
“call gate” sequence
The “call gate” is composed of 3 words located on the first three 32-bit addresses of the
base address of the code segment and of the Volatile data segment if it is declared as
not shared (VDS = 0) and executable (VDE = 1).
– 1st word: Dummy 32-bit words always closed in order to protect the “call gate”
opening from an access due to a prefetch buffer.
– 2nd and 3rd words: 2 specific 32-bit words called “call gate” and always opened.
To open the Firewall, the code currently executed must jump to the 2nd word of the “call
gate” and execute the code from this point. The 2nd word and 3rd word execution must not
be interrupted by any intermediate instruction fetch; otherwise, the Firewall is not
considered open and comes back to a close state. Then, executing the 3rd word after
receiving the intermediate instruction fetch would generate a system reset as a
consequence.
As soon as the Firewall is opened, the protected segments can be accessed as described in
Section 5.3.4: Segment accesses and properties.

Closing the Firewall

The Firewall is closed immediately after it is enabled (clearing the FWDIS bit in the system
configuration register).
To close the Firewall, the protected code must:
• Write the correct value in the Firewall Pre Arm Flag into the FW_CR register.
• Jump to any executable location outside the Firewall segments.
If the Firewall Pre Arm Flag is not set when the protected code jumps to a non protected
segment, a reset is generated. This control bit is an additional protection to avoid an
undesired attempt to close the Firewall with the private information not yet cleaned (see the
note below).
For security reasons, following the application for which the Firewall is used, it is advised to
clean all private information from CPU registers and hardware cells.

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5.4 Firewall registers

5.4.1 Code segment start address (FW_CSSA)

Address offset: 0x00
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. ADD[23:16]

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADD[15:8] Res. Res. Res. Res. Res. Res. Res. Res.

rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:8 ADD[23:8]: code segment start address
The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a
256-byte granularity.
Note: These bits can be written only before enabling the Firewall. Refer to Section 5.3.5:
Firewall initialization.
Bits 7:0 Reserved, must be kept at the reset value.

5.4.2 Code segment length (FW_CSL)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LENG[21:16]

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LENG15:8] Res. Res. Res. Res. Res. Res. Res. Res.

rw

Bits 31:22 Reserved, must be kept at the reset value.

Bits 21:8 LENG[21:8]: code segment length
LENG[21:8] selects the size of the code segment expressed in bytes but is a multiple of
256 bytes.
The segment area is defined from {ADD[23:8],0x00} to {ADD[23:8]+LENG[21:8], 0x00} - 0x01
Note: If LENG[21:8] = 0 after enabling the Firewall, this segment is not defined, thus not
protected by the Firewall.
These bits can only be written before enabling the Firewall. Refer to Section 5.3.5:
Firewall initialization.
Bits 7:0 Reserved, must be kept at the reset value.

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5.4.3 Non-volatile data segment start address (FW_NVDSSA)

Address offset: 0x08
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. ADD[23:16]

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADD[15:8] Res. Res. Res. Res. Res. Res. Res. Res.

rw

Bits 31:24 Reserved, must be kept at the reset value.

Bits 23:8 ADD[23:8]: Non-volatile data segment start address
The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a
256-byte granularity.
Note: These bits can only be written before enabling the Firewall. Refer to Section 5.3.5:
Firewall initialization.
Bits 7:0 Reserved, must be kept at the reset value.

5.4.4 Non-volatile data segment length (FW_NVDSL)

Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LENG[21:16]

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LENG[15:8] Res. Res. Res. Res. Res. Res. Res. Res.

rw

Bits 31:22 Reserved, must be kept at the reset value.

Bits 21:8 LENG[21:8]: Non-volatile data segment length
LENG[21:8] selects the size of the Non-volatile data segment expressed in bytes but is a
multiple of 256 bytes.
The segment area is defined from {ADD[23:8],0x00} to {ADD[23:8]+LENG[21:8], 0x00} - 0x01
Note: If LENG[21:8] = 0 after enabling the Firewall, this segment is not defined, thus not
protected by the Firewall.
These bits can only be written before enabling the Firewall. Refer to Section 5.3.5:
Firewall initialization.
Bits 7:0 Reserved, must be kept at the reset value.

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5.4.5 Volatile data segment start address (FW_VDSSA)

Address offset: 0x10
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADD[15:6] Res. Res. Res. Res. Res. Res.

rw

Bits 31:16 Reserved, must be kept at the reset value.

Bits 15:6 ADD[15:6]: Volatile data segment start address
The LSB bit of the start address (bits 5:0) are reserved and forced to 0 in order to allow a
64-byte granularity.
Note: These bits can only be written before enabling the Firewall. Refer to Section 5.3.5:
Firewall initialization.
Bits 5:0 Reserved, must be kept at the reset value.

5.4.6 Volatile data segment length (FW_VDSL)

Address offset: 0x14
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LENG[15:6] Res. Res. Res. Res. Res. Res.

rw

Bits 31:16 Reserved, must be kept at the reset value.

Bits 15:6 LENG[15:6]: Volatile data segment length
LENG[15:6] selects the size of the volatile data segment expressed in bytes but is a multiple
of 64 bytes.
The segment area is defined from {ADD[15:6],0x00} to {ADD[15:6]+LENG[15:6], 0x00} - 0x01
Note: If LENG[15:6] = 0 after enabling the Firewall, this segment is not defined, thus not
protected by the Firewall.
These bits can only be written before enabling the Firewall. Refer to Section 5.3.5:
Firewall initialization.
Bits 5:0 Reserved, must be kept at the reset value.

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5.4.7 Configuration register (FW_CR)

Address offset: 0x20
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VDE VDS FPA

rw rw rw

Bits 31:3 Reserved, must be kept at the reset value.

Bit 2 VDE: Volatile data execution
0: Volatile data segment cannot be executed if VDS = 0
1: Volatile data segment is declared executable whatever VDS bit value
When VDS = 1, this bit has no meaning. The Volatile data segment can be executed whatever
the VDE bit value.
If VDS = 1, the code can be executed whatever the Firewall state (opened or closed)
If VDS = 0, the code can only be executed if the Firewall is opened or applying the “call gate”
entry sequence if the Firewall is closed.
Refer to Segment access depending on the Firewall state.
Bit 1 VDS: Volatile data shared
0: Volatile data segment is not shared and cannot be hit by a non protected executable code
when the Firewall is closed. If it is accessed in such a condition, a system reset will be
generated by the Firewall.
1: Volatile data segment is shared with non protected application code. It can be accessed
whatever the Firewall state (opened or closed).
Refer to Segment access depending on the Firewall state.
Bit 0 FPA: Firewall prearm
0: any code executed outside the protected segment when the Firewall is opened will
generate a system reset.
1: any code executed outside the protected segment will close the Firewall.
Refer to Closing the Firewall.

This register is protected in the same way as the Non-volatile data segment (refer to
Section 5.3.5: Firewall initialization).

134/905 RM0377 Rev 10

 0x8
0x4
0x0

0xC

0x20
0x18
0x14
0x10
5.4.8

0x1C
Offset
RM0377

FW_CR
FW_CSL

FW_VDSL
FW_CSSA
Register

Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value

FW_NVDSL

FW_VDSSA
FW_NVDSSA
Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Firewall register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0

Res. Res. Res. Res. Res. Res. Res. 23

0
0

Res. Res. Res. Res. Res. Res. Res. 22

0
0
0
0

Res. Res. Res. Res. Res. 21

0
0
0
0

Res. Res. Res. Res. Res. 20

0
0
0
0

Res. Res. Res. Res. Res. 19

0
0
0
0

Res. Res. Res. Res. Res. 18

RM0377 Rev 10
0
0
0
0

Res. Res. Res. Res. Res. 0 17

0
0
0

Res. Res. Res. Res. Res. 16

ADD
ADD

0
0
0
0
0

Res. Res. Res. 15

0
0
0
0
0

Res. Res. Res.

LENG
LENG

0
14
0
0
0
0

Res. Res. Res. 13

0
0
0
0
0

Res. Res. Res. 12

0
0
0
0
0

Res. Res. Res. 11

LENG
Table 32. Firewall register map and reset values

ADD

0
0
0
0
0

Res. Res. Res. 10

0
0
0
0
0

Res. Res. Res. 9

The table below provides the Firewall register map and reset values.

Refer to Section 2.2 on page 51 for the register boundary addresses.

0
0
0
0
0

Res. Res. Res. 8

0

Res. Res. Res. Res. Res. Res. Res. 7

0

Res. Res. Res. Res. Res. Res. Res. 6

Res. Res. Res. Res. Res. Res. Res. Res. Res. 5
Res. Res. Res. Res. Res. Res. Res. Res. Res. 4
Res. Res. Res. Res. Res. Res. Res. Res. Res. 3

0
VDE Res. Res. Res. Res. Res. Res. Res. Res. 2
0
VDS Res. Res. Res. Res. Res. Res. Res. Res. 1
0
FPA Res. Res. Res. Res. Res. Res. Res. Res. 0
Firewall (FW)

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6 Power control (PWR)

6.1 Power supplies

The device requires a 1.8-to-3.6 V VDD operating voltage supply (down to 1.65 V at power-
down) when the BOR is available. The device requires a 1.65-to-3.6 V VDD operating
voltage supply when the BOR is not available.
An embedded linear voltage regulator is used to supply the internal digital power, ranging
from 1.2 to 1.8 V.
• VDD = 1.8 V (at power-on) or 1.65 V (at power-down) to 3.6 V when the BOR is
available. VDD = 1.65 V to 3.6 V, when BOR is not available
VDD is the external power supply for I/Os and internal regulator. It is provided externally
through VDD pins
• VCORE = 1.2 to 1.8 V
VCORE is the power supply for digital peripherals, SRAM and Flash memory. It is
generated by a internal voltage regulator. Three VCORE ranges can be selected by
software depending on VDD (refer Figure 11).
• VSSA, VDDA = 1.8 V (at power-on) or 1.65 V (at power-down) to 3.6 V, when BOR is
available and VSSA, VDDA = 1.65 to 3.6 V, when BOR is not available.
VDDA is the external analog power supply for ADC, reset blocks, RC oscillators and
PLL. For category 1 devices in low-pin count packages, VDDA is bonded to VDD (refer to
the corresponding datasheets for more details).
• VREF+
VREF+ is the input reference voltage. It is only available as an external pin on a few
packages, otherwise it is bonded to VDDA.

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Figure 10. Power supply overview

VDDA domain
(from 1.65 V up to VDDA) VREF+
ADC
Temp. Sensor
Reset block
(VDD) VDDA
PLL
(VSS) VSSA

VCore domain
VDD domain
Flash memory
IO supply

Standby
circuitry(Wakeup
logic, IWDG, RTC, Core memories
VSS Digital
LSE crystal 32K
osc., RCC) peripherals
VDD

Voltage regulator
Dynamic voltage
scaling

MSv34752V2

1. VDDA and VSSA must be connected to VDD and VSS, respectively.

2. Depending on the operating power supply range used, some peripherals may be used with limited features
or performance.
3. VREF+ is only available on TFBGA64 package.

6.1.1 Independent A/D converter supply and reference voltage

To improve conversion accuracy, the ADC has an independent power supply that can be
filtered separately, and shielded from noise on the PCB.
• The ADC voltage supply input is available on a separate VDDA pin
• An isolated supply ground connection is provided on the VSSA pin
Note: For category 1 devices in 14-pin package, VDDA is internally connected to VDD.

On packages with VREF+ pin

To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to
VREF+ a separate external reference voltage lower than VDD. VREF+ is the highest voltage,
represented by the full scale value, for an analog input (ADC).
For ADC:
1.65 V ≤ VREF+ < VDDA

On packages without VREF+ pin

VREF+ pin is not available. It is internally connected to the ADC voltage supply (VDDA).

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6.1.2 RTC and RTC backup registers

The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-
of-day clock/calendar, two programmable alarm interrupts, and a periodic programmable
wakeup flag with interrupt capability. The RTC contains 5 backup data registers (20 bytes).
These backup registers are reset when a tamper detection event occurs. For more details
refer to Real-time clock (RTC) section.

RTC registers access

After reset, the RTC Registers (RTC registers and RTC backup registers) are protected
against possible stray write accesses. To enable access to the RTC Registers, proceed as
follows:
1. Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR
register.
2. Set the DBP bit in the PWR_CR register (see Section 6.4.1).
3. Select the RTC clock source through RTCSEL[1:0] bits in RCC_CSR register.
4. Enable the RTC clock by programming the RTCEN bit in the RCC_CSR register.

6.1.3 Voltage regulator

An embedded linear voltage regulator supplies all the digital circuitries except for the
Standby circuitry. The regulator output voltage (VCORE) can be programmed by software to
three different ranges within 1.2 - 1.8 V (typical) (see Section 6.1.4).
The voltage regulator is always enabled after Reset. It works in three different modes: main
(MR), low-power (LPR) and power-down, depending on the application modes.
• In Run mode, the regulator is main (MR) mode and supplies full power to the VCORE
domain (core, memories and digital peripherals).
• In Low-power run mode, the regulator is in low-power (LPR) mode and supplies low-
power to the VCORE domain, preserving the contents of the registers and internal
SRAM.
• In Sleep mode, the regulator is main (MR) mode and supplies full power to the VCORE
domain, preserving the contents of the registers and internal SRAM.
• In Low-power sleep mode, the regulator is in low-power (LPR) mode and supplies low-
power to the VCORE domain, preserving the contents of the registers and internal
SRAM.
• In Stop mode the regulator supplies low power to the VCORE domain, preserving the
content of registers and internal SRAM.
• In Standby mode, the regulator is powered off. The content of the registers and SRAM
are lost except for the Standby circuitry.

6.1.4 Dynamic voltage scaling management

The dynamic voltage scaling is a power management technique which consists in
increasing or decreasing the voltage used for the digital peripherals (VCORE), according to
the circumstances.
Dynamic voltage scaling to increase VCORE is known as overvolting. It allows improving the
device performance. Refer to Figure 11 for a description of the device operating conditions
versus CPU performance and to the datasheet electrical characteristics for ADC clock
frequency versus dynamic range.

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Dynamic voltage scaling to decrease VCORE is known as undervolting. It is performed to

save power, particularly in laptops and other mobile devices where the energy comes from a
battery and is thus limited.

Range 1
Range 1 is the “high performance” range.
The voltage regulator outputs a 1.8 V voltage (typical) as long as the VDD input voltage is
above 1.71 V. Flash program and erase operations can be performed in this range.
When VDD is below 2.0 V, the CPU frequency changes from initial to final state must respect
the following conditions:
• fCPUfinal < 4xfCPUinitial.
• In addition, a 5 μs delay must be respected between two changes. For example to
switch from 4.2 to 32 MHz, switch from 4.2 to 16 MHz, wait for 5 μs, then switch from
16 to 32 MHz.

Range 2 and 3
The regulator can also be programmed to output a regulated 1.5 V (typical, range 2) or a
1.2 V (typical, range 3) without any limitations on VDD (1.65 to 3.6 V).
• At 1.5 V, the Flash memory is still functional but with medium read access time. This is
the “medium performance” range. Program and erase operations on the Flash memory
are still possible.
• At 1.2 V, the Flash memory is still functional but with slow read access time. This is the
“low performance” range. Program and erase operations on the Flash memory are not
possible under these conditions.
Refer to Table 33 for details on the performance for each range.

Table 33. Performance versus VCORE ranges

Max frequency
CPU Power VCORE Typical (MHz)
VDD range
performance performance range Value (V)
1 WS 0 WS

High Low 1 1.8 32 16 1.71 - 3.6

Medium Medium 2 1.5 16 8
1.65 - 3.6
Low High 3 1.2 4.2 4.2

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Power control (PWR) RM0377

Figure 11. Performance versus VDD and VCORE range

MHz

32
32 MHz

24 FCPU > 16 MHz

1WS
16
16 MHz
16 MHz
12
FCPU > 8 MHz
1WS
8
8 MHz
4
4.2 MHz
0WS 0WS 0WS

V CORE 1 .2 V 1.5 V 1.8 V

3 2 1

VD D 1.65 V - 3.6 V 1.71 V – 3.6 V

Rang e 1
Ra nge 2
Range 3
MS32792V1

6.1.5 Dynamic voltage scaling configuration

The following sequence is required to program the voltage regulator ranges:
1. Check VDD to identify which ranges are allowed (see Figure 11: Performance versus
VDD and VCORE range).
2. Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0.
3. Configure the voltage scaling range by setting the VOS[1:0] bits in the PWR_CR
register.
4. Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0.
Note: During voltage scaling configuration, the system clock is stopped until the regulator is
stabilized (VOSF=0). This must be taken into account during application development, in
case a critical reaction time to interrupt is needed, and depending on peripheral used (timer,
communication,...).

6.1.6 Voltage regulator and clock management when VDD drops

below 1.71 V
When VCORE range 1 is selected and VDD drops below 1.71 V, the application must
reconfigure the system.
A three-step sequence is required to reconfigure the system:
1. Detect that VDD drops below 1.71 V:
Use the PVD to monitor the VDD voltage and to generate an interrupt when the voltage
goes under the selected level. To detect the 1.71 V voltage limit, the application can

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select by software PVD threshold 2 (2.26 V typical). For more details on the PVD, refer
to Section 6.2.3.
2. Adapt the clock frequency to the voltage range that will be selected at next step:
Below 1.71 V, the system clock frequency is limited to 16 MHz for range 2 and 4.2 MHz
for range 3.
3. Select the required voltage range:
Note that when VDD is below 1.71 V, only range 2 or range 3 can be selected.
Note: When VCORE range 2 or range 3 is selected and VDD drops below 1.71 V, no system
reconfiguration is required.

6.1.7 Voltage regulator and clock management when modifying the

VCORE range
When VDD is above 1.71 V, any of the 3 voltage ranges can be selected:
• When the voltage range is above the targeted voltage range (e.g. from range 1 to 2):
a) Adapt the clock frequency to the lower voltage range that will be selected at next
step.
b) Select the required voltage range.
• When the voltage range is below the targeted voltage range (e.g. from range 3 to 1):
a) Select the required voltage range.
b) Tune the clock frequency if needed.
When VDD is below 1.71 V, only range 2 and 3 can be selected:
• From range 2 to range 3
a) Adapt the clock frequency to voltage range 3.
b) Select voltage range 3.
• From range 3 to range 2
a) Select the voltage range 2.
b) Tune the clock frequency if needed.

6.1.8 Voltage range and limitations when VDD ranges from 1.71 V to 2.0 V
The STM32L0x1 voltage regulator is based on an architecture designed for Ultra-low-power
a. It does not use any external capacitor. Such regulator is sensitive to fast changes of load.
In this case, the output voltage is reduced for a short period of time. Considering that the
core voltage must be higher than 1.65 V to ensure a 32 MHz operation, this phenomenon is
critical for very low VDD voltages (e.g. 1.71 V VDD minimum value).
To guarantee 32 MHz operation at VDD =1.8 V±5%, with 1 wait state, and VCORE range 1,
the CPU frequency in run mode must be managed to prevent any changes exceeding a
ratio of 4 in one shot. A delay of 5 μs must be respected between 2 changes. There is no
limitation when waking up from low-power mode.

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6.2 Power supply supervisor

The device has an integrated zeropower power-on reset (POR)/power-down reset (PDR),
coupled with a brown out reset (BOR) circuitry. For devices operating between 1.8 and 3.6
V, the BOR is always active at power-on and ensures proper operation starting from 1.8 V.
After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to
confirm or modify default thresholds, or to disable BOR permanently (in which case, the VDD
min value at power-down is 1.65 V). For devices operating between 1.65 V and 3.6 V, the
BOR is permanently disabled. Consequently, the start-up time at power-on can be
decreased down to 1 ms typically.
Five BOR thresholds can be configured by option bytes, starting from 1.65 to 3 V. To reduce
the power consumption in Stop mode, the internal voltage reference, VREFINT, can be
automatically switch off. The device remains in reset mode when VDD is below a specified
threshold, VPOR, VPDR or VBOR, without the need for any external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. 7 different PVD levels can
be selected by software between 1.85 and 3.05 V, with a 200 mV step. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine then generates a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
The different power supply supervisor (POR, PDR, BOR, PVD) are illustrated in Figure 12.

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Figure 12. Power supply supervisors

VDD /VDD A

V PVD 100 mV
hysteresis

V BO R 100 mV
hysteresis

VPOR/ VPDR

IT enabled

PVD output

BOR reset
(NRST)

BOR/PDR reset
(NRST)

POR/PDR reset
(NRST)
PVD
BOR always active
BOR disabled by option byte
POR/PDR (BOR not available)

ai17211b

1. The PVD is available on all devices and it is enabled or disabled by software.

2. The BOR is available only on devices operating from 1.8 to 3.6 V, and unless disabled by option byte it will
mask the POR/PDR threshold.
3. When the BOR is disabled by option byte, the reset is asserted when VDD goes below PDR level
4. For devices operating from 1.65 to 3.6 V, there is no BOR and the reset is released when VDD goes above
POR level and asserted when VDD goes below PDR level

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6.2.1 Power-on reset (POR)/power-down reset (PDR)

The device has an integrated POR/PDR circuitry that allows operation down to 1.5 V.
During power-on, the device remains in Reset mode when VDD/VDDA is below a specified
threshold, VPOR, without the need for an external reset circuit. The POR feature is always
enabled and the POR threshold is 1.5 V.
During power-down, the PDR keeps the device under reset when the supply voltage (VDD)
drops below the VPDR threshold. The PDR feature is always enabled and the PDR threshold
is 1.5 V.
The POR and PDR are used only when the BOR is disabled (see Section 6.2.2: Brown out
reset (BOR))). To insure the minimum operating voltage (1.65 V), the BOR should be
configured to BOR Level 1. When the BOR is disabled, a “gray zone” exist between the
minimum operating voltage (1.65 V) and the VPOR/VPDR threshold. This means that VDD
can be lower than 1.65 V without device reset until the VPDR threshold is reached.
For more details concerning the power-on/power-down reset threshold, refer to the
electrical characteristics of the datasheet.

Figure 13. Power-on reset/power-down reset waveform

VDD/VDDA

POR
PDR

Temporization
tRSTTEMPO

Reset
MS32793V1

6.2.2 Brown out reset (BOR)

During power-on, the Brown out reset (BOR) keeps the device under reset until the supply
voltage reaches the specified VBOR threshold.
For devices operating from 1.65 to 3.6 V, the BOR option is not available and the power
supply is monitored by the POR/PDR. As the POR/PDR thresholds are at 1.5 V, a “gray
zone” exists between the VPOR/VPDR thresholds and the minimum product operating
voltage 1.65 V.
For devices operating from 1.8 to 3.6 V, the BOR is always active at power-on and it's
threshold is 1.8 V.
Then when the system reset is released, the BOR level can be reconfigured or disabled by
option byte loading.
If the BOR level is kept at the lowest level, 1.8 V at power-on and 1.65 V at power-down, the
system reset is fully managed by the BOR and the product operating voltages are within
safe ranges.

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And when the BOR option is disabled by option byte, the power-down reset is controlled by
the PDR and a “gray zone” exists between the 1.65 V and VPDR.
VBOR is configured through device option bytes. By default, the Level 4 threshold is
activated. 5 programmable VBOR thresholds can be selected.
• BOR Level 1 (VBOR0): reset threshold level for 1.69 to 1.80 V voltage range
• BOR Level 2 (VBOR1): reset threshold level for 1.94 to 2.1 V voltage range
• BOR Level 3 (VBOR2): reset threshold level for 2.3 to 2.49 V voltage range
• BOR Level 4 (VBOR3): reset threshold level for 2.54 to 2.74 V voltage range
• BOR Level 5 (VBOR4): reset threshold level for 2.77 to 3.0 V voltage range
When the supply voltage (VDD) drops below the selected VBOR threshold, a device reset is
generated. When the VDD is above the VBOR upper limit the device reset is released and the
system can start.
BOR can be disabled by programming the device option bytes. To disable the BOR function,
VDD must have been higher than VBOR0 to start the device option byte programming
sequence. The power-on and power-down is then monitored by the POR and PDR (see
Section 6.2.1: Power-on reset (POR)/power-down reset (PDR))
The BOR threshold hysteresis is ~100 mV (between the rising and the falling edge of the
supply voltage).

Figure 14. BOR thresholds

VDD/VDDA

100mV
BOR threshold hysteresis

Reset

MS32794V1

6.2.3 Programmable voltage detector (PVD)

You can use the PVD to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the PWR_CR (see Section 6.4.1).
The PVD can use an external input analog voltage (PVD_IN) which is compared internally to
VREFINT. The PVD_IN (PB7) has to be configured in Analog mode when PLS[2:0] = 111.
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available in the PWR_CSR register (see Section 6.4.2). It indicates if VDD is
higher or lower than the PVD threshold. This event is internally connected to EXTI line16
and can generate an interrupt if it has been enabled through the EXTI registers. The
rising/falling edge sensitivity of EXTI Line16 should be configured according to the PVD
output behavior: if EXTI line 16 is configured to rising edge sensitivity, the interrupt will be

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generated when VDD drops below the PVD threshold. As an example the service routine
could perform emergency shutdown tasks.

Figure 15. PVD thresholds

VDD/VDDA

100mV
PVD threshold hysteresis

PVD output

MSv32795V2

6.2.4 Internal voltage reference (VREFINT)

The internal reference (VREFINT) provides stable voltage for analog peripherals. The
functions managed through the internal voltage reference (VREFINT) are BOR, PVD, ADC
and comparators. The internal voltage reference (VREFINT) is always enabled when one of
these features is used.
The internal voltage reference consumption is not negligible, in particular in Stop and
Standby mode. To reduce power consumption, the ULP bit (ultra-low-power) in the
PWR_CR register can be set to disable the internal voltage reference. However, in this
case, when exiting from the Stop/Standby mode, the functions managed through the internal
voltage reference are not reliable during the internal voltage reference startup time (up to
3 ms).
To reduce the wakeup time, the device can exit from Stop/Standby mode without waiting for
the internal voltage reference startup time. This is performed by setting the FWU bit (Fast
wakeup) in the PWR_CR register before entering Stop/Standby mode.
If the ULP bit is set, the functions that were enabled before entering Stop/Standby mode will
be disabled during these modes, and enabled again only after the end of the internal voltage
reference startup time whatever FWU value. The VREFINTRDYF flag in the PWR_CSR
register indicates that the internal voltage reference is ready.
When the device exits from low-power mode on an NRST pulse, it does not wait for internal
voltage reference startup (even if ULP=1 and FWU=0). The application should check the
VREFINTRDYF flag if necessary.

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6.3 Low-power modes

By default, the microcontroller is in Run mode after a system or a power-on reset. In Run
mode the CPU is clocked by HCLK and the program code is executed. Several low-power
modes are available to save power when the CPU does not need to be kept running, for
example when waiting for an external event. It is up to the user to select the mode that gives
the best compromise between low-power consumption, performance, short startup time and
available wakeup sources.
The devices feature five low-power modes:
• Low-power run mode: regulator in low-power mode, limited clock frequency, limited
number of peripherals running (refer to Section 6.3.4)
• Sleep mode: Cortex®-M0+ core stopped, peripherals kept running (refer to
Section 6.3.7)
• Low-power sleep mode: Cortex®-M0+core stopped, limited clock frequency, limited
number of peripherals running, regulator in low-power mode, Flash stopped ((refer to
Section 6.3.8))
• Stop mode (all clocks are stopped, regulator running, regulator in low-power mode
(refer to Section 6.3.9)
• Standby mode: VCORE domain powered off ((refer to Section 6.3.10))
In addition, the power consumption in Run mode can be reduced by one of the following
means:
• Slowing down the system clocks
• Gating the clocks to the APBx and AHBx peripherals when they are unused.

Table 34. Summary of low-power modes

Effect on VDD
Effect on VCORE
Mode name Entry Wakeup domain Voltage regulator
domain clocks
clocks

LPSDSR and The regulator is forced

Low-power In low-power
LPRUN bits + in Main regulator (1.8 None None
run mode
Clock setting V)
WFI or Return CPU CLK OFF
Sleep Any interrupt
from ISR no effect on other
(Sleep now or None ON
clocks or analog
Sleep-on-exit) WFE Wakeup event clock sources
LPSDSR bits + CPU CLK OFF
Low-power WFI or Return Any interrupt no effect on other
sleep (Sleep from ISR In low-power
clocks or analog None
now or Sleep- mode
LPSDSR bits + clock sources,
on-exit) Wakeup event
WFE Flash CLK OFF

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Table 34. Summary of low-power modes (continued)

Effect on VDD
Effect on VCORE
Mode name Entry Wakeup domain Voltage regulator
domain clocks
clocks

PDDS, LPSDSR
Any EXTI line
or LPDS bits +
(configured in the EXTI In low-power
Stop SLEEPDEEP bit +
registers, internal and mode
WFI, Return from
external lines)
ISR or WFE HSI16(1), HSE
All VCORE
Standby WKUP pin rising edge, and MSI
domain clocks
RTC alarm (Alarm A or oscillators
PDDS bit + OFF
Alarm B), RTC Wakeup OFF
SLEEPDEEP bit +
event, RTC tamper OFF
WFI, Return from
event, RTC timestamp
ISR or WFE
event, external reset in
NRST pin, IWDG reset
1. HSI16 can run in Stop mode provided HSI16KERON is set in Clock control register (RCC_CR).

6.3.1 Behavior of clocks in low-power modes

APB peripheral and DMA clocks can be disabled by software.

Sleep and Low-power sleep modes

The CPU clock is stopped in Sleep and Low-power sleep mode. The memory interface
clocks (Flash memory and RAM interfaces) and all peripherals clocks can be stopped by
software during Sleep. The memory interface clock is stopped and the RAM is in power-
down when in Low-power sleep mode. The AHB to APB bridge clocks are disabled by
hardware during Sleep/Low-power sleep mode when all the clocks of the peripherals
connected to them are disabled.

Stop and Standby modes

The system clock and all high speed clocks are stopped in Stop and Standby modes:
• PLL is disabled
• Internal RC 16 MHz (HSI16) oscillator is disabled, except if HSI16KERON is set in Stop
mode (see Section 7.3.1: Clock control register (RCC_CR))
• External 1-24 MHz (HSE) oscillator is disabled
• Internal 65 kHz - 4.2 MHz (MSI) oscillator is disabled
When exiting this mode by an interrupt (Stop mode), the internal MSI or HSI16 can be
selected as system clock. For both oscillators, their respective configuration (range and
trimming) value is kept on Stop mode exit.
When exiting this mode by a reset (Standby mode), the internal MSI oscillator is selected as
system clock. The range and the trimming value are reset to the default 2.1 MHz.
If a Flash program operation or an access to APB domain is ongoing, the Stop/Standby
mode entry is delayed until the Flash memory or the APB access has completed.

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6.3.2 Slowing down system clocks

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be
reduced by programming the prescaler registers. These prescalers can also be used to slow
down peripherals before entering Sleep mode.
For more details refer to Section 7.3.3: Clock configuration register (RCC_CFGR).

6.3.3 Peripheral clock gating

In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped
at any time to reduce power consumption.
To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.
Peripheral clock gating is controlled by the AHB peripheral clock enable register
(RCC_AHBENR), APB2 peripheral clock enable register (RCC_APB2ENR), APB1
peripheral clock enable register (RCC_APB1ENR) (see Section 7.3.12: AHB peripheral
clock enable register (RCC_AHBENR), Section 7.3.14: APB1 peripheral clock enable
register (RCC_APB1ENR) and Section 7.3.13: APB2 peripheral clock enable register
(RCC_APB2ENR)).
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in RCC_AHBLPENR and RCC_APBxLPENR registers (x can 1 or 2).

6.3.4 Low-power run mode (LP run)

To further reduce the consumption when the system is in Run mode, the regulator can be
configured in low-power mode. In this mode, the system frequency should not exceed
f_MSI range1.
Please refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.
Note: To be able to read the RTC calendar register when the APB1 clock frequency is less than
seven times the RTC clock frequency (7*RTCLCK), the software must read the calendar
time and date registers twice.
If the second read of the RTC_TR gives the same result as the first read, this ensures that
the data is correct. Otherwise a third read access must be done.
Low-power run mode can only be entered when VCORE is in range 2. In addition, the
dynamic voltage scaling must not be used when Low-power run mode is selected. Only Stop
and Sleep modes with regulator configured in low-power mode is allowed when Low-power
run mode is selected.
Note: In Low-power run mode, all I/O pins keep the same state as in Run mode.

Entering Low-power run mode

To enter Low-power run mode proceed as follows:
1. Each digital IP clock must be enabled or disabled by using the RCC_APBxENR and
RCC_AHBENR registers.
2. The frequency of the system clock must be decreased to not exceed the frequency of
f_MSI range1.
3. The regulator is forced in low-power mode by software (LPRUN and LPSDSR bits set)

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Exiting Low-power run mode

To exit Low-power run mode proceed as follows:
1. The regulator is forced in Main regulator mode by software.
2. The Flash memory is switched on, if needed.
3. The frequency of the clock system can be increased.

6.3.5 Entering low-power mode

Low-power modes (except for Low-power run mode) are entered by executing the WFI
(Wait For Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in
Cortex®-M0+ System Control register is set on Return from ISR.
Entering low-power mode through WFI or WFE will be executed only is no interrupt and no
event is pending.

6.3.6 Exiting low-power mode

The microcontroller exists from Sleep and Stop mode depending on the way the mode was
entered:
• If the WFI instruction or Return from ISR was used to enter the low-power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device. This includes
EXTI lines and any GPIO toggle.
• If the WFE instruction was used to enter low-power mode, the microcontroller exits the
low-power mode as soon as an event occurs. The wakeup event can be generated
either by:
– An NVIC IRQ interrupt:
This is done by enabling an interrupt in the peripheral control register but not in the
NVIC, and by enabling the SEVONPEND bit in the Cortex®-M0+ System Control
register. When the microcontroller resumes from WFE, the peripheral interrupt
pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC
interrupt clear pending register) have to be cleared.
– An event:
This is done by configuring an external or internal EXTI line in event mode. When
the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt
pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding
to the event line is not set.

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6.3.7 Sleep mode

I/O states in Sleep mode
In Sleep mode, all I/O pins keep the same state as in Run mode.

Entering Sleep mode

The Sleep mode is entered according to Section 6.3.5: Entering low-power mode.
Refer to Table 35: Sleep-now and Table 36: Sleep-on-exit for details on how to enter Sleep
mode.

Exiting Sleep mode

The Sleep mode is exited according to Section 6.3.6: Exiting low-power mode.
Refer to Table 35: Sleep-now and Table 36: Sleep-on-exit for more details on how to exit
Sleep mode.

Table 35. Sleep-now

Sleep-now mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 0 and
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex®-M0+ System Control register (see PM0223 programming
manual).
Mode entry On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1 and
– No interrupt is pending
Refer to the Cortex®-M0+ System Control register (see PM0223 programming
manual).
If WFI or return from ISR was used for entry:
Interrupt: refer to Table 53: List of vectors
If WFE was used for entry and SVONPEND = 0
Mode exit Wakeup event: refer to Section 12.3.2: Wakeup event management
If WFE was used for entry and SVONPEND = 1
Interrupt event when disabled in NVIC (refer to Table 53: List of vectors) or
wakeup event (refer to Section 12.3.2: Wakeup event management)
Wakeup latency None

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Table 36. Sleep-on-exit

Sleep-on-exit Description

WFI (wait for interrupt) while:

– SLEEPDEEP = 0 and
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex®-M0+ System Control register (see PM0223
programming manual).
Mode entry On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1 and
– No interrupt is pending
Refer to the Cortex®-M0+ System Control register (see PM0223
programming manual).
Mode exit Interrupt: refer to Table 53: List of vectors
Wakeup latency None

6.3.8 Low-power sleep mode (LP sleep)

I/O states in Low-power sleep mode
In Low-power sleep mode, all I/O pins keep the same state as in Run mode.

Entering Low-power sleep mode

To enter Low-power sleep mode, proceed as follows:
1. The Flash memory can be switched off by using the control bits (SLEEP_PD in the
FLASH_ACR register. This reduces power consumption but increases the wake-up
time.
2. Each digital IP clock must be enabled or disabled by using the RCC_APBxENR and
RCC_AHBENR registers.
3. The frequency of the system clock must be decreased.
4. The regulator is forced in low-power mode by software (LPSDSR bits set).
5. Follow the steps described in Section 6.3.5: Entering low-power mode.
Refer to Table 37: Sleep-now (Low-power sleep) and Table 38: Sleep-on-exit (Low-power
sleep) for details on how to enter Low-power sleep mode.
In Low-power sleep mode, the Flash memory can be switched off and the RAM memory
remains available.
In this mode, the system frequency should not exceed f_MSI range1.
Please refer to product datasheet for more details on voltage regulator and peripherals
operating conditions.
Low-power sleep mode can only be entered when VCORE is in range 2.

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Note: To be able to read the RTC calendar register when the APB1 clock frequency is less than
seven times the RTC clock frequency (7*RTCLCK), the software must read the calendar
time and date registers twice.
If the second read of the RTC_TR gives the same result as the first read, this ensures that
the data is correct. Otherwise a third read access must be done.

Exiting Low-power sleep mode

The Low-power sleep mode is exited according to Section 6.3.6: Exiting low-power mode.
When exiting Low-power sleep mode by issuing an interrupt or a wakeup event, the
regulator is configured in Main regulator mode, the Flash memory is switched on (if
necessary), and the system clock can be increased.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Low-power sleep mode.
Refer to Table 37: Sleep-now (Low-power sleep) and Table 38: Sleep-on-exit (Low-power
sleep) for more details on how to exit Sleep low-power mode.

Table 37. Sleep-now (Low-power sleep)

Sleep-now mode Description

Voltage regulator in low-power mode and the Flash memory switched off
WFI (Wait for Interrupt) or WFE (wait for event) while:
– SLEEPDEEP = 0 and
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex®-M0+ System Control register (see PM0223 programming
manual).
Mode entry
On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1 and
– No interrupt is pending
Refer to the Cortex®-M0+ System Control register (see PM0223 programming
manual).
Voltage regulator in Main regulator mode and the Flash memory switched on
If WFI or Return from ISR was used for entry:
Interrupt: Refer to Table 53: List of vectors
If WFE was used for entry and SEVONPEND = 0
Mode exit
Wakeup event: Refer to Section 12.3.2: Wakeup event management
If WFE was used for entry and SVONPEND = 1
Interrupt event when disabled in NVIC (refer to Table 53: List of vectors) or
wakeup event (refer to Section 12.3.2: Wakeup event management)
Wakeup latency Regulator wakeup time from low-power mode

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Table 38. Sleep-on-exit (Low-power sleep)

Sleep-on-exit Description

WFI (wait for interrupt) while:

– SLEEPDEEP = 0 and
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex®-M0+ System Control register (see PM0223
programming manual).
Mode entry On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1 and
– No interrupt is pending
Refer to the Cortex®-M0+ System Control register (see PM0223
programming manual).
Mode exit Interrupt: refer to Table 53: List of vectors.
Wakeup latency regulator wakeup time from low-power mode

6.3.9 Stop mode

The Stop mode is based on the Cortex®-M0+ Deepsleep mode combined with peripheral
clock gating. The voltage regulator can be configured either in normal or low-power mode.
In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16
(except if HSI16KERON is set in Stop mode, see Section 7.3.1: Clock control register
(RCC_CR)) and the HSE RC oscillators are disabled. Internal SRAM and register contents
are preserved.
To get the lowest consumption in Stop mode, the internal Flash memory also enters low-
power mode. When the Flash memory is in power-down mode, an additional startup delay is
incurred when waking up from Stop mode.
To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
sensor can be switched off before entering Stop mode. This functionality is controlled by the
ULP bit in the PWR_CR register. If the ULP bit is set, the reference is switched off on Stop
mode entry and enabled again on wakeup. .

I/O states in Low-power sleep mode

In Stop mode, all I/O pins keep the same state as in Run mode.

Entering Stop mode

Refer to Section 6.3.5: Entering low-power mode and to Table 39 for details on how to enter
the Stop mode.
If the application needs to disable the external clock before entering Stop mode, the HSEON
bit must be first disabled and the system clock switched to HSI16.
Otherwise, if the HSEON bit is kept enabled while external clock (external oscillator) can be
removed before entering Stop mode, the clock security system (CSS) feature must be
enabled to detect any external oscillator failure and avoid a malfunction behavior when
entering Stop mode.

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To further reduce power consumption in Stop mode, the internal voltage regulator can be put
in low-power mode. This is configured by the LPSDSR or LPDS bit in the PWR_CR register
(see Section 6.4.1). The internal voltage regulator can also be kept in Main mode but the
consumption will be much higher. As a result, it is always implicitly assumed that the
regulator is in low-power mode during Stop mode. The only advantage of keeping the
regulator in Main mode is that the wakeup time from Stop mode is shorter.
If Flash memory programming or an access to the APB domain is ongoing, the Stop mode
entry is delayed until the memory or APB access has completed.
In Stop mode, the following features can be selected by programming individual control bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. Refer to
Section 20.3: IWDG functional description in Section 20: Independent watchdog
(IWDG).
• Real-time clock (RTC): this is configured by the RTCEN bit in the RCC_CSR register
(see Section 7.3.20).
• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC_CSR
register.
• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
RCC_CSR register.
The ADC can also consume power in Stop mode, unless they are disabled before entering
it. To disable them, the ADDIS bit in the ADC_CR register must be set to 1 must be written
to 0.

Exiting Stop mode

Refer to Section 6.3.6: Exiting low-power mode and to Table 39 for details on how to exit
Stop mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the MSI or HSI16 RC
oscillator is selected as system clock depending the bit STOPWUCK in the RCC_CFGR
register.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop
mode, the consumption is higher although the startup time is reduced.

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Table 39. Stop mode

Stop mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– No interrupt (for WFI) or event (for WFE) is pending.
– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– PDDS bit = 0 in Power Control register (PWR_CR)
– WUF bit = 0 in Power Control/Status register (PWR_CSR)
– MSI or HSI16 RC oscillator are selected as system clock for Stop mode
exit by configuring the STOPWUCK bit in the RCC_CFGR register.
Note: To enter the Stop mode, all EXTI Line pending bits (in
Section 12.5.6: EXTI pending register (EXTI_PR)), all peripherals
interrupt pending bits, the RTC Alarm (Alarm A and Alarm B), RTC
wakeup, RTC tamper, and RTC time-stamp flags, must be reset.
Otherwise, the Stop mode entry procedure is ignored and program
execution continues.
Mode entry On return from ISR while:
– No interrupt is pending.
– SLEEPDEEP bit is set in Cortex®-M0+ System Control register
– SLEEPONEXIT = 1
– PDDS bit = 0 in Power Control register (PWR_CR)
– WUF bit = 0 in Power Control/Status register (PWR_CSR)
– MSI or HSI16 RC oscillator are selected as system clock for Stop mode
exit by configuring the STOPWUCK bit in the RCC_CFGR register.
Note: To enter the Stop mode, all EXTI Line pending bits (in
Section 12.5.6: EXTI pending register (EXTI_PR)), all peripherals
interrupt pending bits, the RTC Alarm (Alarm A and Alarm B), RTC
wakeup, RTC tamper, and RTC time-stamp flags, must be reset.
Otherwise, the Stop mode entry procedure is ignored and program
execution continues.
If WFI or return from ISR was used for entry:
Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). Refer to Table 53: List of
vectors.
If WFE was used for entry and SEVONPEND = 0
Any EXTI Line configured in event mode. Refer to Section 12.3.2:
Wakeup event management on page 269
Mode exit
If WFE was used for entry and SEVONPEND = 1
– Any EXTI Line configured in event mode (even if the corresponding EXTI
interrupt is disabled in the NVIC). The interrupt source can be an external
interrupt or a peripheral with wakeup capability (refer to Table 53: List of
vectors).
– A wakeup event (refer to Section 12.3.2: Wakeup event management on
page 269)
MSI or HSI16 RC wakeup time + regulator wakeup time from Low-power
Wakeup latency
mode + FLASH wakeup time

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6.3.10 Standby mode

The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex®-M0+ Deepsleep mode, with the voltage regulator disabled. The VCORE domain is
consequently powered off. The PLL, the MSI, the HSI16 oscillator and the HSE oscillator
are also switched off. SRAM and register contents are lost except for the RTC registers,
RTC backup registers and Standby circuitry (see Figure 10).

I/O states in Standby mode

In Standby mode, all I/O pins are high impedance except for:
• Reset pad
• Wakeup pins (WKUP1, WKUP2, WKUP3)
• RTC functions (tamper, time-stamp, RTC Alarm out, RTC clock calibration out) on the
following I/Os:
– Category 1: PA0, PA2
– Category 2: PC13, PA0, PA2
– Category 3: PC13, PA0
– Category 5: PC13, PA0, PE6

Entering Standby mode

Refer to Section 6.3.5: Entering low-power mode and to Table 40 for details on how to enter
Standby mode.
In Standby mode, the following features can be selected by programming individual control
bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. Refer to
Section 20.3: IWDG functional description on page 528.
• Real-time clock (RTC): this is configured by the RTCEN bit in the RCC_CSR register
(see Section 7.3.20).
• Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC_CSR
register.
• External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
RCC_CSR register.

Exiting Standby mode

The microcontroller exits Standby mode when an external Reset (NRST pin), an IWDG
Reset, a rising edge on WKUP pins (WUKP1, WKUP2 or WKUP3), an RTC alarm, a tamper
event, or a time-stamp event is detected.
After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the
PWR_CSR register (see Section 6.4.2) indicates that the microcontroller was in Standby
mode. All registers are reset to their default value after a system reset except for the register
bits in the RTC domain (see Section 22.7: RTC registers, SBF status flag in the PWR power
control/status register (PWR_CSR), Control/status register (RCC_CSR) and Clock control
register (RCC_CR)).
Refer to Section 6.3.6: Exiting low-power mode and to Table 40 for more details on how to
exit Standby mode.

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Table 40. Standby mode

Standby mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 1 in Cortex®-M0+ System Control register
– PDDS = 1 bit in Power Control register (PWR_CR)
– No interrupt (for WFI) or event (for WFE) is pending.
– WUF = 0 bit in Power Control/Status register (PWR_CSR)
– the RTC flag corresponding to the chosen wakeup source (RTC Alarm A,
RTC Alarm B, RTC wakeup, Tamper or Time-stamp flags) is cleared
Mode entry On return from ISR while:
– SLEEPDEEP = 1 in Cortex®-M0+ System Control register
– SLEEPONEXIT = 1
– PDDS bit = 1 in Power Control register (PWR_CR)
– No interrupt is pending.
– WUF bit = 0 in Power Control/Status register (PWR_CSR)
– the RTC flag corresponding to the chosen wakeup source (RTC Alarm A,
RTC Alarm B, RTC wakeup, Tamper or Time-stamp flags) is cleared.
WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
Mode exit
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
Wakeup latency Reset phase

Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop or Standby
mode while the debug features are used. This is due to the fact that the Cortex®-M0+ core is
no longer clocked.
However, by setting some configuration bits in the DBG_CR register, the software can be
debugged even when using the low-power modes extensively. For more details, refer to
Section 27.9.1: Debug support for low-power modes.

6.3.11 Waking up the device from Stop and Standby modes using the RTC
and comparators
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC Wakeup
event, a tamper event, a time-stamp event, or a comparator event, without depending on an
external interrupt (Auto-wakeup mode).
These RTC alternate functions can wake up the system from Stop and Standby low-power
modes while the comparator events can only wake up the system from Stop mode.
The system can also wake up from low-power modes without depending on an external
interrupt (Auto-wakeup mode) by using the RTC alarm or the RTC wakeup events.

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The RTC provides a programmable time base for waking up from Stop or Standby mode at
regular intervals. For this purpose, two of the three alternative RTC clock sources can be
selected by programming the RTCSEL[1:0] bits in the RCC_CSR register (see
Section 7.3.20):
• Low-power 32.768 kHz external crystal oscillator (LSE OSC).
This clock source provides a precise time base with very low-power consumption (less
than 1 µA added consumption in typical conditions)
• Low-power internal RC oscillator (LSI RC)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC Oscillator is designed to use minimum power consumption.

RTC auto-wakeup (AWU) from the Stop mode

• To wake up from the Stop mode with an RTC alarm event, it is necessary to:
a) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event
modes)
b) Enable the RTC Alarm interrupt in the RTC_CR register
c) Configure the RTC to generate the RTC alarm
• To wake up from the Stop mode with an RTC Tamper or time stamp event, it is
necessary to:
a) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event
modes)
b) Enable the RTC TimeStamp Interrupt in the RTC_CR register or the RTC Tamper
Interrupt in the RTC_TCR register
c) Configure the RTC to detect the tamper or time stamp event
• To wake up from the Stop mode with an RTC Wakeup event, it is necessary to:
a) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event
modes)
b) Enable the RTC Wakeup Interrupt in the RTC_CR register
c) Configure the RTC to generate the RTC Wakeup event

RTC auto-wakeup (AWU) from the Standby mode

• To wake up from the Standby mode with an RTC alarm event, it is necessary to:
a) Enable the RTC Alarm interrupt in the RTC_CR register
b) Configure the RTC to generate the RTC alarm
• To wake up from the Stop mode with an RTC Tamper or time stamp event, it is
necessary to:
a) Enable the RTC TimeStamp Interrupt in the RTC_CR register or the RTC Tamper
Interrupt in the RTC_TCR register
b) Configure the RTC to detect the tamper or time stamp event
• To wake up from the Stop mode with an RTC Wakeup event, it is necessary to:
a) Enable the RTC Wakeup Interrupt in the RTC_CR register
b) Configure the RTC to generate the RTC Wakeup event

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Comparator auto-wakeup (AWU) from the Stop mode

• To wake up from the Stop mode with a comparator 1 or comparator 2 wakeup event, it
is necessary to:
a) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
(Interrupt or Event mode) to be sensitive to the selected edges (falling, rising or
falling and rising)
b) Configure the comparator to generate the event.

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6.4 Power control registers

The peripheral registers have to be accessed by half-words (16-bit) or words (32-bit).

6.4.1 PWR power control register (PWR_CR)

Address offset: 0x00
Reset value: 0x0000 1000 (reset by wakeup from Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPDS
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DS_EE
Res. LPRUN VOS[1:0] FWU ULP DBP PLS[2:0] PVDE CSBF CWUF PDDS LPSDSR
_KOFF
rw rw rw rw rw rw rw rw rw rw rw rc_w1 rc_w1 rw rw

Bits 31:17 Reserved, always read as 0.

Bit 16 LPDS: Regulator in Low-power deepsleep mode
This bit allows switching the regulator to low-power mode when the CPU enters Stop
mode. Its behavior depends on LPSDSR bit.
– if LPSDSR = 1: bit has no effect.
– if LPSDSR = 0:
0: Voltage regulator in Main mode during Deepsleep mode (Stop mode)
1: Voltage regulator switches to low-power mode when the CPU enters Deepsleep mode
(Stop mode).
The regulator goes back to Main mode when the CPU exits from Deepsleep mode.
Note: The LPDS bit is available on category 1 devices only.
Bit 15 Reserved, always read as 0.
Bit 14 LPRUN: Low-power run mode
When LPRUN bit is set together with the LPSDSR bit, the regulator is switched from Main
mode to low-power mode. Otherwise, it remains in Main mode. The regulator goes back to
operate in Main mode when LPRUN is reset.
If this bit is set (with LPSDSR bit set) and the CPU enters sleep or Deepsleep mode (LP
sleep or Stop mode), then, when the CPU wakes up from these modes, it enters Run
mode but with LPRUN bit set. To enter again Low-power run mode, it is necessary to
perform a reset and set LPRUN bit again.
It is forbidden to reset LPSDSR when the MCU is in Low-power run mode. LPSDSR is
used as a prepositioning for the entry into low-power mode, indicating to the system which
configuration of the regulator will be selected when entering low-power mode. The
LPSDSR bit must be set before the LPRUN bit is set. LPSDSR can be reset only when
LPRUN bit=0.
0: Voltage regulator in Main mode in Low-power run mode
1: Voltage regulator in low-power mode in Low-power run mode
Bit 13 DS_EE_KOFF: Deepsleep mode with non-volatile memory kept off
When entering low-power mode (Stop or Standby only), if DS_EE_KOFF and RUN_PD
bits are both set in FLASH_ACR register (refer to Section 3.7.1: Access control register
(FLASH_ACR), the non-volatile memory (Flash program memory and data EEPROM) will
not be woken up when exiting from Deepsleep mode.
0: NVM woken up when exiting from Deepsleep mode even if the bit RUN_PD is set
1: NVM not woken up when exiting from low-power mode (if the bit RUN_PD is set)

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Bits 12:11 VOS[1:0]: Voltage scaling range selection

These bits are used to select the internal regulator voltage range.
Before resetting the power interface by resetting the PWRRST bit in the RCC_APB1RSTR
register, these bits have to be set to ‘10’ and the frequency of the system has to be
configured accordingly.
00: forbidden (bits are unchanged and keep the previous value, no voltage change
occurs)
01: 1.8 V (range 1)
10: 1.5 V (range 2)
11: 1.2 V (range 3)
Bit 10 FWU: Fast wakeup
This bit works in conjunction with ULP bit.
If ULP = 0, FWU is ignored
If ULP = 1 and FWU = 1: VREFINT startup time is ignored when exiting from low-power mode.
The VREFINTRDYF flag in the PWR_CSR register indicates when the VREFINT is ready
again.
If ULP=1 and FWU = 0: Exiting from low-power mode occurs only when the VREFINT is ready
(after its startup time). This bit is not reset by resetting the PWRRST bit in the
RCC_APB1RSTR register.
0: Low-power modes exit occurs only when VREFINT is ready
1: VREFINT start up time is ignored when exiting low-power modes
Bit 9 ULP: Ultra-low-power mode
When set, the VREFINT is switched off in low-power mode. The BOR, PVD, and temperature
sensor also rely on the voltage reference. This bit is not reset by resetting the PWRRST bit
in the RCC_APB1RSTR register.
0: VREFINT is on in low-power mode
1: VREFINT is off in low-power mode
Bit 8 DBP: Disable backup write protection
In reset state, the RTC, RTC backup registers and RCC CSR register are protected against
parasitic write access. This bit must be set to enable write access to these registers.
0: Access to RTC, RTC Backup and RCC CSR registers disabled
1: Access to RTC, RTC Backup and RCC CSR registers enabled
Note: If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, this bit must remain set
to 1.

Bits 7:5 PLS[2:0]: PVD level selection

These bits are written by software to select the voltage threshold detected by the
programmable voltage detector:
000: 1.9 V
001: 2.1 V
010: 2.3 V
011: 2.5 V
100: 2.7 V
101: 2.9 V
110: 3.1 V
111: External input analog voltage (Compare internally to VREFINT)
PVD_IN input (PB7) has to be configured as analog input when PLS[2:0] = 111.
Note: Refer to the electrical characteristics of the datasheet for more details.

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Bit 4 PVDE: Programmable voltage detector enable

This bit is set and cleared by software.
0: PVD disabled
1: PVD enabled
Bit 3 CSBF: Clear standby flag
This bit is always read as 0.
0: No effect
1: Clear the SBF Standby flag (write).
Bit 2 CWUF: Clear wakeup flag
This bit is always read as 0.
0: No effect
1: Clear the WUF Wakeup flag after 2 system clock cycles
Bit 1 PDDS: Power-down deepsleep
This bit is set and cleared by software.
0: Enter Stop mode when the CPU enters Deepsleep.
1: Enter Standby mode when the CPU enters Deepsleep.
Bit 0 LPSDSR: Low-power deepsleep/Sleep/Low-power run
– DeepSleep/Sleep modes
When this bit is set, the regulator switches in low-power mode when the CPU enters sleep
or Deepsleep mode. The regulator goes back to Main mode when the CPU exits from
these modes.
– Low-power run mode
When this bit is set, the regulator switches in low-power mode when the bit LPRUN is set.
The regulator goes back to Main mode when the bit LPRUN is reset.
This bit is set and cleared by software.
0: Voltage regulator on during Deepsleep/Sleep/Low-power run mode
1: Voltage regulator in low-power mode during Deepsleep/Sleep/Low-power run mode
Note: If the sequence below is executed:
1) Low-power run
2) Low-power sleep
3) Run
4) Low-power run
after returning from Low-power deepsleep/Sleep mode (step 2), the regulator goes
back to Main mode (step 3). Then to switch to Low-power run mode (step 4), it is
necessary to perform a reset and set LPSDSR bit again.

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6.4.2 PWR power control/status register (PWR_CSR)

Address offset: 0x04
Reset value: 0x0000 0008 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EWUP EWUP EWUP REG VREFIN
Res. Res. Res. Res. Res. Res. Res. VOSF PVDO SBF WUF
3 2 1 LPF TRDYF
rw rw rw r r r r r r

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 EWUP3: Enable WKUP pin 3
This bit is set and cleared by software.
0: WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not
wakeup the device from Standby mode.
1: WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode).
Note: This bit is reset by a system reset.
Bit 9 EWUP2: Enable WKUP pin 2
This bit is set and cleared by software.
0: WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not
wakeup the device from Standby mode.
1: WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode).
Note: This bit is reset by a system reset.
Bit 8 EWUP1: Enable WKUP pin 1
This bit is set and cleared by software.
0: WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not
wakeup the device from Standby mode.
1: WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down
configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode).
Note: This bit is reset by a system reset.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 REGLPF: Regulator LP flag
This bit is set by hardware when the MCU is in Low-power run mode.
When the MCU exits from Low-power run mode, this bit stays at 1 until the regulator is ready in
Main mode. A polling on this bit is recommended to wait for the regulator Main mode. This bit is
reset by hardware when the regulator is ready.
0: Regulator is ready in Main mode
1: Regulator voltage is in low-power mode

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Bit 4 VOSF: Voltage Scaling select flag

A delay is required for the internal regulator to be ready after the voltage range is changed.
The VOSF bit indicates that the regulator has reached the voltage level defined with bits VOS
of PWR_CR register.
This bit is set when VOS[1:0] in PWR_CR register change.
It is reset once the regulator is ready.
0: Regulator is ready in the selected voltage range
1: Regulator voltage output is changing to the required VOS level.
Bit 3 VREFINTRDYF: Internal voltage reference (VREFINT) ready flag
This bit indicates the state of the internal voltage reference, VREFINT.
0: VREFINT is OFF
1: VREFINT is ready
Bit 2 PVDO: PVD output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
0: VDD is higher than the PVD threshold selected with the PLS[2:0] bits.
1: VDD is lower than the PVD threshold selected with the PLS[2:0] bits.
Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after
Standby or reset until the PVDE bit is set.
Bit 1 SBF: Standby flag
This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down
reset) or by setting the CSBF bit in the PWR power control register (PWR_CR)
0: Device has not been in Standby mode
1: Device has been in Standby mode
Bit 0 WUF: Wakeup flag
This bit is set by hardware and cleared by a system reset or by setting the CWUF bit in the
PWR power control register (PWR_CR)
0: No wakeup event occurred
1: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or
Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup).
Note: An additional wakeup event is detected if the WKUP pins are enabled (by setting the
EWUPx (x=1, 2, 3) bits) when the WKUP pin levels are already high.

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6.4.3 PWR register map

The following table summarizes the PWR registers.

Table 41. PWR - register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
DS_EE_KOFF.

LPSDSR
LPRUN
VOS

CWUF
PDDS
PVDE
CSBF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
LPDS

FWU

DBP
ULP
PWR_CR PLS[2:0]
0x000 [1:0]

Reset value 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

VREFINTRDYF
REGLPF
EWUP3
EWUP2
EWUP1

PVDO
VOSF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

WUF
SBF
PWR_CSR
0x004

Reset value 0 0 0 0 0 1 0 0 0

Refer to Section 2.2 on page 51 for the register boundary addresses.

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7 Reset and clock control (RCC)

7.1 Reset
There are three types of reset, defined as system reset, power reset and RTC domain reset.

7.1.1 System reset

A system reset sets all registers to their reset values unless specified otherwise in the
register description.
A system reset is generated when one of the following events occurs:
• A low level on the NRST pin (external reset)
• Window watchdog end-of-count condition (WWDG reset)
• Independent watchdog end-of-count condition (IWDG reset)
• A software reset (SW reset) (see Software reset)
• Low-power management reset (see Low-power management reset)
• Option byte loader reset (see Option byte loader reset)
• Exit from Standby mode
• Firewall protection (see Section 5: Firewall (FW))
The reset source can be identified by checking the reset flags in the control/status register,
RCC_CSR (see Section 7.3.20).

Software reset
The SYSRESETREQ bit in Cortex®-M0+ AIRCR register (Application Interrupt and Reset
Control Register) must be set to force a software reset on the device. Refer to Arm®
Cortex®-M0+ Technical Reference Manual for more details.

Low-power management reset

There are two ways to generate a low-power management reset:
• Reset generated when entering Standby mode:
This type of reset is enabled by resetting nRST_STDBY bit in user option bytes. In this
case, whenever a Standby mode entry sequence is successfully executed, the device
is reset instead of entering Standby mode.
• Reset when entering Stop mode:
This type of reset is enabled by resetting nRST_STOP bit in user option bytes. In this
case, whenever a Stop mode entry sequence is successfully executed, the device is
reset instead of entering Stop mode.

Option byte loader reset

The Option byte loader reset is generated when the OBL_LAUNCH bit (bit 18) is set in the
FLASH_PECR register. This bit is used to launch by software the option byte loading.
For further information on the user option bytes, refer to Section 3: Flash program memory
and data EEPROM (FLASH).

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7.1.2 Power reset

A power reset is generated when one of the following events occurs:
• Power-on/power-down reset (POR/PDR reset)
• BOR reset
A power reset sets all registers to their reset values including for the RTC domain (see
Figure 16)
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map. For
more details, refer to Table 53: List of vectors.
The system reset signal provided to the device is output on the NRST pin (except the Exit
from Standby reset which is not output on the NRST pin but generates system reset).
The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal
reset source. In case of an external reset, the reset pulse is generated while the NRST pin is
asserted low.
When an internal reset occurs, the internal pull-up resistor (RPU) is deactivated in order to
save the power consumption through the pull-up resistor.

Figure 16. Simplified diagram of the reset circuit

VDD

RPU System reset

External NRST
Filter
reset
WWDG reset
IWDG reset
Pulse Firewall reset
generator Software reset
(min 20 μs) Low-power manager reset
Option byte loader reset
BOR reset

MSv41924V2

7.1.3 RTC and backup registers reset

The RTC peripheral, RTC clock source selection (in RCC_CSR) and the backup registers
are reset only when one of the following events occurs:
• A software reset, triggered by setting the RTCRST bit in the RCC_CSR register (see
Section 7.3.20)
• Power reset (BOR/POR/PDR).

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7.2 Clocks
Four different clock sources can be used to drive the system clock (SYSCLK):
• HSI16 (high-speed internal) oscillator clock
• HSE (high-speed external) oscillator clock
The HSE external quartz connexion is available only on cat. 2 devices in LQFP48
package.
• PLL clock
• MSI (multispeed internal) oscillator clock
The MSI at 2.1MHz is used as system clock source after startup from power reset,
system or RTC domain reset, and after wake-up from Standby mode.
The HSI16, HSI16 divided by 4, or the MSI at any of its possible frequency can be used
to wake up from Stop mode.
The devices have two secondary clock sources:
• 37 kHz low speed internal RC (LSI RC) which drives the independent watchdog and
optionally the RTC used for Auto-wakeup from Stop/Standby mode and the LPTIMER.
• 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the real-
time clock (RTCCLK), the LPTIMER and USARTs.
Each clock source can be switched on or off independently when it is not used to optimize
power consumption.
Several prescalers can be used to configure the AHB frequency and the two APBs (APB1
and APB2) domains. The maximum frequency of AHB, APB1 and the APB2 domains is
32 MHz. It depends on the device voltage range. For more details refer to Section 6.1.4:
Dynamic voltage scaling management.
All the peripheral clocks are derived from the system clock (SYSCLK) except:
• The ADC can be derived either from the APB clock or the HSI16 clock.
• The LPUART1 and USART1/2 clock which is derived (selected by software) from one
of the four following sources:
– system clock
– HSI16 clock
– LSE clock
– APB clock (PCLK)
• The I2C1 clock which is derived (selected by software) from one of the three following
sources:
– system clock
– HSI16 clock
– APB clock (PCLK)
• The LPTIMER clock which is derived (selected by software) from one of the four
following sources:
– HSI16 clock
– LSE clock
– LSI clock
– APB clock (PCLK)

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• The RTC clock which is derived from the following clock sources:
– LSE clock,
– LSI clock,
– 4 MHz HSE_RTC (HSE divided by a programmable prescaler).
• IWDG clock which is always the LSI clock.
The system clock (SYSCLK) frequency must be higher or equal to the RTC clock frequency.
The RCC feeds the Cortex® System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex® clock
(HCLK), configurable in the SysTick Control and Status Register.

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Figure 17. Clock tree

@V33 Enable Watchdog
Watchdog LS Legend:
LSI RC LSI tempo HSE = High-speed external clock signal
RTCSEL HSI = High-speed internal clock signal
LSI = Low-speed internal clock signal
RTC2 enable LSE = Low-speed external clock signal
MSI = Multispeed internal clock signal
RTC
LSE OSC LSE tempo

LSU LSD LSD

@V18

@V33 MCOSEL ADC enable

LSI
MSI RC ADCCLK
MSI LSE
Level shifters
@V18 / 1,2,4,8,16 MCO
not deepsleep
/ 2,4,8,16
@V33 CK_PWR
not deepsleep
HSI16 RC
ck_rchs HSI16
Level shifters / 1,4 not (sleep or FCLK
@V18 deepsleep)
System
Clock not (sleep or HCLK
deepsleep)
/8
MSI TIMxCLK
@V33
HSI16 AHB
HSE OSC 4 MHz PRESC
HSE PCLK1 to APB1
Level shifters PLLSRC / 1,2,…, 512 peripherals
@V18 @V33
PLLCLK APB1
PRESC
ck_pllin PLL / 1,2,4,8,16
LSU X Peripheral
@V33 3,4,6,8,12,16, clock enable
24,32,48 to TIMx
1 MHz Clock / 2,3,4
If (APB1 presc=1) x1
Detector else x2)
Level shifters
Peripheral
@VDDCORE
HSE present or not Clock clock enable
LSD PCLK2 to APB2
Source 32 MHz peripherals
APB2 max.
Control PRESC
/ 1,2,4,8,16
Peripheral
clock enable
to TIMx
If (APB2 presc=1) x1
else x2)

Peripherals
LSI enable

LPTIMCLK
LSE Peripherals
enable
HSI16
SYSCLK
PCLK Peripherals LPUART/
enable UARTCLK

I2C1CLK

MSv34747V2

1. For full details about the internal and external clock source characteristics, please refer to the “Electrical
characteristics” section in your device datasheet.

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The timer clock frequencies are automatically fixed by hardware. There are two cases:
1. If the APB prescaler is 1, the timer clock frequencies are set to the same frequency as
that of the APB domain to which the timers are connected.
2. Otherwise, they are set to twice (×2) the frequency of the APB domain to which the
timers are connected.
fCLK acts as Cortex®-M0+ free running clock. For more details refer to the Section 27:
Debug support (DBG).

7.2.1 HSE clock

The high speed external clock signal (HSE) can be generated from two possible clock
sources:
• HSE external crystal/ceramic resonator
• HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.

Table 42. HSE/LSE clock sources

Clock source Hardware configuration

External clock for

OSC_IN OSC_OUT
category 2 (LQFP48
only), category 3 and
5 devices
GPIO
External
source
MSv31915V1

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Table 42. HSE/LSE clock sources (continued)

Clock source Hardware configuration

External clock for

category 1 and 2 CK_IN
devices (packages
with less that 48 GPIO
pins)
External
source

MSv36151V1

OSC_IN OSC_OUT
Crystal/Ceramic
resonators for
category 2 (LQFP48
only), category 3 and
CL1 CL2
5 devices Load
capacitors
MSv31916V1

External source (HSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to
32 MHz. This mode is selected by setting the HSEBYP and HSEON bits in the RCC_CR
register (see Section 7.3.1: Clock control register (RCC_CR)). The external clock signal
with ~50% duty cycle has to drive the following pin (see Figure 42):
• On devices where OSC_IN and OSC_OUT pins are available: the OSC_IN pin must be
driven while the OSC_OUT pin should be left hi-Z.
• Otherwise, the CK_IN pin must be driven.
Note: For details on pin availability, refers to the pinout section in your device datasheet.
The external clock signal can be square, sinus or triangle. To minimize the consumption, it
is recommended to use the square signal.

External crystal/ceramic resonator (HSE crystal)

The 1 to 24 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.
The associated hardware configuration is shown in Figure 42. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag of the RCC_CR register (see Section 7.3.1) indicates whether the HSE
oscillator is stable or not. At startup, the HSE clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the RCC_CR register.
The HSE Crystal can be switched on and off using the HSEON bit in the RCC_CR register.
For code example, refer to A.4.1: HSE start sequence code example.

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7.2.2 HSI16 clock

The HSI16 clock signal is generated from an internal 16 MHz RC oscillator. It can be used
directly as a system clock or as PLL input.
The HSI16 clock can be used after wake-up from the Stop low-power mode, this ensure a
smaller wake-up time than a wake-up using MSI clock.
The HSI16 RC oscillator has the advantage of providing a clock source at low cost (no
external components). It also has a faster startup time than the HSE crystal oscillator
however, even with calibration the frequency is less accurate than an external crystal
oscillator or ceramic resonator.
The HSI16 clock can be kept running in Stop mode by setting HSI16KERON bit in RCC_CR
register (see Section 7.3.1: Clock control register (RCC_CR)). In this case the HSI16 clock
can be used for dedicated peripherals which can run in Stop mode.

Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at an ambient
temperature, TA, of 25 °C.
After reset, the factory calibration value is loaded in the HSI16CAL[7:0] bits in the Internal
Clock Sources Calibration Register (RCC_ICSCR) (see Section 7.3.2).
If the application is subject to voltage or temperature variations, this may affect the RC
oscillator speed. You can trim the HSI16 frequency in the application by using the
HSI16TRIM[4:0] bits in the RCC_ICSCR register. For more details on how to measure the
HSI16 frequency variation please refer to Section 7.2.14: Internal/external clock
measurement using TIM21.
The HSI16RDY flag in the RCC_CR register indicates whether the HSI16 oscillator is stable
or not. At startup, the HSI16 RC output clock is not released until this bit is set by hardware.
The HSI16 RC oscillator can be switched on and off using the HSI16ON bit in the RCC_CR
register.

7.2.3 MSI clock

The MSI clock signal is generated from an internal RC oscillator. Its frequency range can be
adjusted by software by using the MSIRANGE[2:0] bits in the RCC_ICSCR register (see
Section 7.3.2: Internal clock sources calibration register (RCC_ICSCR)). Seven frequency
ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz,
2.097 MHz (default value) and 4.194 MHz.
The MSI clock is always used as system clock after restart from Reset and wake-up from
Standby. After wake-up from Stop mode, the MSI clock can be selected as system clock
instead of HSI16 (or HSI16/4).
When the device restarts after a reset or a wake-up from Standby, the MSI frequency is set
to its default value. The MSI frequency does not change after waking up from Stop.
The MSI RC oscillator has the advantage of providing a low-cost (no external components)
low-power clock source. It is used as wake-up clock in low-power modes to reduce power
consumption.
The MSIRDY flag in the RCC_CR register indicates whether the MSI RC is stable or not. At
startup, the MSI RC output clock is not released until this bit is set by hardware.

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The MSI RC can be switched on and off by using the MSION bit in the RCC_CR register
(see Section 7.3.1).
It can also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator
fails. Refer to Section 7.2.9: HSE clock security system (CSS) on page 177.

Calibration
The MSI RC oscillator frequency can vary from one chip to another due to manufacturing
process variations, this is why each device is factory calibrated by ST for 1% accuracy at an
ambient temperature, TA, of 25 °C.
After reset, the factory calibration value is loaded in the MSICAL[7:0] bits in the
RCC_ICSCR register. If the application is subject to voltage or temperature variations, this
may affect the RC oscillator speed. You can trim the MSI frequency in the application by
using the MSITRIM[7:0] bits in the RCC_ICSCR register. For more details on how to
measure the MSI frequency variation please refer to Section 7.2.14: Internal/external clock
measurement using TIM21.

7.2.4 PLL
The internal PLL can be clocked by the HSI16 RC or HSE clocks.
The PLL input clock frequency must range between 2 and 24 MHz.
The desired frequency is obtained by using the multiplication factor and output division
embedded in the PLL:
• The system clock is derived from the PLL VCO divided by the output division factor.
Note: The application software must set correctly the PLL multiplication factor to avoid exceeding
96 MHz as PLLVCO when the product is in range 1,
48 MHz as PLLVCO when the product is in range 2,
24 MHz when the product is in range 3.
It must also set correctly the output division to avoid exceeding 32 MHz as SYSCLK.
The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source).
The PLL configuration (selection of the source clock, multiplication factor and output division
factor) must be performed before enabling the PLL. Once the PLL is enabled, these
parameters cannot be changed.
To modify the PLL configuration, proceed as follows:
1. Disable the PLL by setting PLLON to 0.
2. Wait until PLLRDY is cleared. The PLL is now fully stopped.
3. Change the desired parameter.
4. Enable the PLL again by setting PLLON to 1.
An interrupt can be generated when the PLL is ready if enabled in the RCC_CIER register
(see Section 7.3.4).
For code example, refer to A.4.2: PLL configuration modification code example.

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7.2.5 LSE clock

The LSE crystal is a 32.768 kHz low speed external crystal or ceramic resonator. It has the
advantage of providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off through the LSEON bit in the RCC_CSR register
(see Section 7.3.20).
The crystal oscillator driving strength can be changed at runtime through the LSEDRV[1:0]
bits of the RCC_CSR register to obtain the best compromise between robustness and short
start-up time on one hand and low power consumption on the other hand. The driving
capability should be changed dynamically to determine the driving level that best matches
the used crystal. In the final application, it is then recommended to program this value in
LSEDRV[1:0] bits.
The LSERDY flag in the RCC_CSR register indicates whether the LSE crystal is stable or
not. At startup, the LSE crystal output clock signal is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the RCC_CIER register (see
Section 7.3.4).

External source (LSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the RCC_CSR
(see Section 7.3.1). The external clock signal (square, sinus or triangle) with ~50% duty
cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left Hi-Z (see
Figure 42).

7.2.6 LSI clock

The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG). The clock frequency is around
37 kHz.
The LSI RC oscillator can be switched on and off using the LSION bit in the RCC_CSR
register (see Section 7.3.20).
The LSIRDY flag in RCC_CSR indicates whether the low-speed internal oscillator is stable
or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can
be generated if enabled in the RCC_CIER (see Section 7.3.4).
Since the IWDG is activated, the LSI oscillator cannot be stopped by LSION=0. The LSI
oscillator is stopped by system reset (except if IWDG is enabled by hardware option through
WDG_SW option bit in FLASH_OPTR register). If the IWDG was enabled by software, then
the LSI oscillator must be enabled again after system reset to ensure correct IWDG and/or
RTC operation.

LSI measurement
The frequency dispersion of the LSI oscillator can be measured to have accurate RTC time
base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an
acceptable accuracy. For more details, refer to the electrical characteristics section of the
datasheets. For more details on how to measure the LSI frequency, please refer to
Section 7.2.14: Internal/external clock measurement using TIM21.

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7.2.7 System clock (SYSCLK) selection

Four different clock sources can be used to drive the system clock (SYSCLK):
• The HSI16 oscillator
• The HSE oscillator
• The PLL
• The MSI oscillator clock (default after reset)
When a clock source is used directly or through the PLL as system clock, it is not possible to
stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch will occur when the clock source will be ready. Status bits in the
RCC_CR register indicate which clock(s) is (are) ready and which clock is currently used as
system clock.

7.2.8 System clock source frequency versus voltage range

The following table gives the different clock source maximum frequencies depending on the
product voltage range.

Table 43. System clock source frequency

Clock frequency
Product voltage
range
MSI HSI16 HSE PLL

HSE 32 MHz (external clock) 32 MHz

Range 1 (1.8 V) 4.2 MHz 16 MHz
or 24 MHz (crystal) (PLLVCO max = 96 MHz)
16 MHz
Range 2 (1.5 V) 4.2 MHz 16 MHz 16 MHz
(PLLVCO max = 48 MHz)
4 MHz
Range 3 (1.2 V) 4.2 MHz NA 8 MHz
(PLLVCO max = 24 MHz)

7.2.9 HSE clock security system (CSS)

The Clock security system can be activated on the HSE by software. In this case, the clock
detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is
stopped.
If an HSE clock failure is detected, this oscillator is automatically disabled and an CSSHSEI
interrupt (Clock Security System Interrupt) is generated to inform the software of the failure,
thus allowing the MCU to perform rescue operations. The CSSHSEI is linked to the
Cortex®-M0+ NMI (Non-Maskable Interrupt) exception vector.
Note: Once the CSSHSE is enabled, if the HSE clock fails, the CSSHSE interrupt occurs and an
NMI is automatically generated. The NMI is executed indefinitely unless the CSSHSE
interrupt pending bit is cleared. As a consequence, the NMI interrupt service routine (ISR)
must clear the CSSHSE interrupt by setting the CSSHSEC bit in the RCC_CICR register.

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If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock, and the PLL clock is used as system clock), a detected failure
causes a switch of the system clock and the disabling of the HSE oscillator. If the HSE
oscillator clock is the clock entry of the PLL used as system clock when the failure occurs,
the PLL is disabled too.
When an HSE failure occurs, the system clock can be switched to the MSI or to the internal
16-MHz HSI clock depending on the value of STOPWUCK bit in the RCC_CFGR register.
Note: Category 1 devices do not feature HSE clock security system. The HSE clock is available
only in bypass mode.

7.2.10 LSE Clock Security System

Clock Security System can be activated on the LSE by software. This is done by writing the
CSSLSEON bit in the RCC_CSR register. This bit can be disabled by a hardware reset, an
RTC software reset, or after an LSE clock failure detection. CSSLSEON bit must be written
after the LSE and LSI clocks are enabled (LSEON and LSION set) and ready (LSERDY and
LSIRDY bits set by hardware), and after the RTC clock has been selected through the
RTCSEL bit.
The LSE CSS works in all modes: run, Sleep, Stop and Standby.
If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied
to the RTC but the content of the registers does not change.
A wakeup is generated in Standby mode. In any other modes, an interrupt can be sent to
wake-up the software (see Section 7.3.4).
The software MUST then reset the CSSLSEON bit and stop the defective 32 kHz oscillator
by resetting LSEON bit. It can change the RTC clock source (LSI, HSE or no clock) through
the RTCSEL bit, or take any required action to secure the application.
The frequency of LSE oscillator must be higher than 30 kHz to avoid false positive CSS
detection.

7.2.11 RTC clock

The RTC has the same clock source which can be either the LSE, the LSI, or the HSE
4 MHz clock (HSE divided by a programmable prescaler). It is selected by programming the
RTCSEL[1:0] bits in the RCC_CSR register (see Section 7.3.20) and the RTCPRE[1:0] bits
in the RCC_CR register (see Section 7.3.1).
Once the RTC clock source have been selected, the only possible way of modifying the
selection is to set the RTCRST bit in the RCC_CSR register, or by a POR.
If the LSE or LSI is used as RTC clock source, the RTC continues to work in Stop and
Standby low-power modes, and can be used as wakeup source. However, when the HSE is
the RTC clock source, the RTC cannot be used in the Stop and Standby low-power modes.
When the RTC is clocked by the LSE, the RTC remains clocked and functional under
system reset.
Note: To be able to read the RTC calendar register when the APB1 clock frequency is less than
seven times the RTC clock frequency (7*RTCLCK), the software must read the calendar
time and date registers twice.
If the second read of the RTC_TR gives the same result as the first read, this ensures that
the data is correct. Otherwise a third read access must be done.

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7.2.12 Watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
If the IWDG was enabled by software, the LSI clock is disabled after system reset. The LSI
oscillator must then be enabled again to ensure correct IWDG operation.

7.2.13 Clock-out capability

The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin using a configurable prescaler (1, 2, 4, 8, or 16). The configuration
registers of the corresponding GPIO port must be programmed in alternate function mode.
One of 7 clock signals can be selected as the MCO clock:
• SYSCLK
• HSI16
• MSI
• HSE
• PLL
• LSI
• LSE
The selection is controlled by the MCOSEL[3:0] bits of the RCC_CFGR register (see
Section 7.3.19).
For code example, refer to A.4.3: MCO selection code example.

7.2.14 Internal/external clock measurement using TIM21

It is possible to indirectly measure the frequency of all on-board clock source generators by
means of the TIM21 channel 1 input capture, as represented on Figure 18.

Figure 18. Using TIM21 channel 1 input capture to measure

frequencies

TI1_RMP[2:0] TIM21
GPIO
MSI TI(1)
LSI
HSE_RTC
LSE

ETR
LSE
GPIO TI(2)
MS32913V1

TIM21 has an input multiplexer that selects which of the I/O or the internal clock is to trigger
the input capture. This selection is performed through the TI1_RMP [2:0] bits in the
TIM21_OR register.

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The primary purpose of connecting the LSE to the channel 1 input capture is to be able to
accurately measure the HSI16 and MSI system clocks (for this, either the HSI16 or MSI
should be used as the system clock source). The number of HSI16 (MSI, respectively) clock
counts between consecutive edges of the LSE signal provides a measure of the internal
clock period. Taking advantage of the high precision of LSE crystals (typically a few tens of
ppm’s), it is possible to determine the internal clock frequency with the same resolution, and
trim the source to compensate for manufacturing-process- and/or temperature- and voltage-
related frequency deviations.
The MSI and HSI16 oscillators both have dedicated user-accessible calibration bits for this
purpose.
The basic concept consists in providing a relative measurement (e.g. the HSI16/LSE ratio):
the precision is therefore closely related to the ratio between the two clock sources. The
higher the ratio, the better the measurement.
It is however not possible to have a good enough resolution when the MSI clock is low
(typically below 1 MHz). In this case, it is advised to:
• accumulate the results of several captures in a row
• use the timer’s input capture prescaler (up to 1 capture every 8 periods)
• use the RTC_OUT signal at 512 Hz (when the RTC is clocked by the LSE) as the input
for the channel1 input capture. This improves the measurement precision
TIM21 can also be used to measure the LSI, MSI, or HSE_RTC: this is useful for
applications with no crystal. The ultra-low-power LSI oscillator has a wide manufacturing
process deviation: by measuring it as a function of the HSI16 clock source, its frequency
can be determined with the precision of the HSI16.The HSE_RTC frequency (HSE divided
by a programmable prescaler) being relatively high (4 MHz), the relative frequency
measurement is not very accurate. Its main purpose is consequently to obtain a rough
indication of the external crystal frequency. This can be useful to meet the requirements of
the IEC 60730/IEC 61335 standards, which require to be able to determine harmonic or
subharmonic frequencies (–50/+100% deviations).

7.2.15 Clock-independent system clock sources for TIM2/TIM21/TIM22

In a number of applications using the 32.768 kHz clock as RTC timebase, timebases
completely independently from the system clock are useful. This allows to schedule tasks
without having to take into account the processor state (the processor may be stopped or
executing at low, medium or full speed).
For this purpose, the LSE clock is internally redirected to the 3 timers’ ETR inputs, which are
used as additional clock sources. This gives up to three independent time bases (using the
auto-reload feature) with 1 or 2 compare additional channels for fractional events. For
instance, the TIM21 auto-reload interrupt can be programmed for a 1 second tick interrupt
with an additional interrupt occurring 250 ms after the main tick.
Note: In this configuration, make sure that you have at least a ratio of 2 between the external clock
(LSE) and the APB clock. If the application uses an APB clock frequency lower than twice
the LSE clock frequency (typically LSE = 32.768 kHz, so twice LSE = 65.536 kHz), it is
mandatory to use the external trigger prescaler feature of the timer: it can divide the ETR
clock by up to 8.

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7.3 RCC registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.

7.3.1 Clock control register (RCC_CR)

Address offset: 0x00
System Reset value: 0b0000 0000 00XX 0X00 0000 0011 0000 0000 where X is undefined
Power-on reset value: 0x0000 0300
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL CSSHS HSE HSE HSE
Res. Res. Res. Res. Res. Res. PLLON Res. Res. RTCPRE[1:0]
RDY EON. BYP RDY ON
r rw rw rw rw rw r rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSI HSI16 HSI16 HSI16 HSI16 HSI16K HSI16
Res. Res. Res. Res. Res. Res. MSION Res. Res.
RDY OUTEN DIVF DIVEN RDYF ERON ON
r rw rw r rw r rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 PLLRDY: PLL clock ready flag
This bit is set by hardware to indicate that the PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: PLL enable bit
This bit is set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the
PLL clock is used as system clock or is selected to become the system clock.
0: PLL OFF
1: PLL ON
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:20 RTCPRE[1:0] RTC prescaler
These bits are set and reset by software to obtain a 4 MHz clock from HSE. This prescaler
cannot be modified if HSE is enabled (HSEON = 1).These bits are reset by a power -on
reset,. Their value is not modified by a system reset.
00: HSE is divided by 2 for RTC clock
01: HSE is divided by 4 for RTC clock
10: HSE is divided by 8 for RTC clock
11: HSE is divided by 16 for RTC clock
Bit 19 CSSHSEON: Clock security system on HSE enable bit
This bit is set by software to enable the clock security system (CSS) on HSE. This bit is "set
only" (disabled by system reset). When CSSHSEON is set, the clock detector is enabled by
hardware when the HSE oscillator is ready, and disabled by hardware if an oscillator failure
is detected.
0: Clock security system OFF (clock detector OFF)
1: Clock security system ON (clock detector ON if HSE oscillator is stable, OFF otherwise)

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Bit 18 HSEBYP: HSE clock bypass bit

This bit is set and cleared by software to bypass the oscillator with an external clock. The
external clock must be enabled with the HSEON bit, to be used by the device.
The HSEBYP bit can be written only if the HSE oscillator is disabled. This bit is reset by
power-on reset. Its value is not modified by system reset
0: HSE oscillator not bypassed
1: HSE oscillator bypassed with an external clock
Bit 17 HSERDY: HSE clock ready flag
This bit is set by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is
cleared, HSERDY goes low after 6 HSE oscillator clock cycles.
0: HSE oscillator not ready
1: HSE oscillator ready
Bit 16 HSEON: HSE clock enable bit
This bit is set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This
bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:10 Reserved, must be kept at reset value.
Bit 9 MSIRDY: MSI clock ready flag
This bit is set by hardware to indicate that the MSI oscillator is stable.
0: MSI oscillator not ready
1: MSI oscillator ready
Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles.
Bit 8 MSION: MSI clock enable bit
This bit is set and cleared by software.
Set by hardware to force the MSI oscillator ON when exiting from Stop or Standby mode, or
in case of a failure of the HSE oscillator used directly or indirectly as system clock. This bit
cannot be cleared if the MSI is used as system clock.
0: MSI oscillator OFF
1: MSI oscillator ON
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 HSI16OUTEN: 16 MHz high-speed internal clock output enable
This bit is set and cleared by software. When this bit is set, TIM2 ETR input is connected to
the 16 MHz HSI output clock (HSI16) provided ETR_RMP is set to 011 in TIM2 option
register (TIM2_OR). This bit can be written anytime by the application.
0: HSI16 output clock disabled
1: HSI16 output clock enabled
Bit 4 HSI16DIVF HSI16 divider flag
This bit is set and reset by hardware. As a write in HSI16DIVEN has not an immediate effect
on the frequency, this flag indicates the current status of the HSI16 divider.
0: 16 MHz HSI clock not divided
1: 16 MHz HSI clock divided by 4
Bit 3 HSI16DIVEN HSI16 divider enable bit
This bit is set and reset by software to enable/disable the 16 MHz HSI divider by 4. It can be
written anytime.
0: no 16 MHz HSI division requested
1: 16 MHz HSI division by 4 requested

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Bit 2 HSI16RDYF: Internal high-speed clock ready flag

This bit is set by hardware to indicate that the HSI 16 MHz oscillator is stable. After the
HSI16ON bit is cleared, HSI16RDY goes low after 6 HSI16 clock cycles.
0: HSI 16 MHz oscillator not ready
1: HSI 16 MHz oscillator ready
Bit 1 HSI16KERON: High-speed internal clock enable bit for some IP kernels
This bit is set and reset by software to force the HSI 16 MHz oscillator ON, even in Stop
mode, so that it can be quickly available as kernel clock for USARTs or I2C1. This bit has no
effect on the value of HSI16ON.
0: HSI 16 MHz oscillator not forced ON
1: HSI 16 MHz oscillator forced ON even in Stop mode
Bit 0 HSI16ON: 16 MHz high-speed internal clock enable
This bit is set and cleared by software. It cannot be cleared if the 16 MHz HSI is used directly
or indirectly as system clock.
0: HSI16 oscillator OFF
1: HSI16 oscillator ON

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7.3.2 Internal clock sources calibration register (RCC_ICSCR)

Address offset: 0x04
Reset value: 0x00XX B0XX where X is undefined.
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSITRIM[7:0] MSICAL[7:0]
rw rw rw rw rw rw rw rw r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSIRANGE[2:0] HSI16TRIM[4:0] HSI16CAL[7:0]
rw rw rw rw rw rw rw rw r r r r r r r r

Bits 31:24 MSITRIM[7:0]: MSI clock trimming

These bits are set by software to adjust MSI calibration.
These bits provide an additional user-programmable trimming value that is added to the
MSICAL[7:0] bits. They can be programmed to compensate for the variations in voltage and
temperature that influence the frequency of the internal MSI RC.
Bits 23:16 MSICAL[7:0]: MSI clock calibration
These bits are automatically initialized at startup.
Bits 15:13 MSIRANGE[2:0]: MSI clock ranges
These bits are set by software to choose the frequency range of MSI.7 frequency ranges are
available:
000: range 0 around 65.536 kHz
001: range 1 around 131.072 kHz
010: range 2 around 262.144 kHz
011: range 3 around 524.288 kHz
100: range 4 around 1.048 MHz
101: range 5 around 2.097 MHz (reset value)
110: range 6 around 4.194 MHz
111: not allowed
Bits 12:8 HSI16TRIM[4:0]: High speed internal clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSI16CAL[7:0] bits. They can be programmed to compensated for the variations in voltage
and temperature that influence the frequency of the internal HSI16 RC.
Bits 7:0 HSI16CAL[7:0] Internal high speed clock calibration
These bits are initialized automatically at startup.

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7.3.3 Clock configuration register (RCC_CFGR)

Address offset: 0x0C
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during clock source switch.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLL
Res. MCOPRE[2:0] MCOSEL[3:0] PLLDIV[1:0] PLLMUL[3:0] Res.
SRC
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOP
Res. PPRE2[2:0] PPRE1[2:0] HPRE[3:0] SWS[1:0] SW[1:0]
WUCK.
rw rw rw rw rw rw rw rw rw rw rw r r rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler
These bits are set and cleared by software.
It is highly recommended to change this prescaler before MCO output is enabled.
000: MCO is divided by 1
001: MCO is divided by 2
010: MCO is divided by 4
011: MCO is divided by 8
100: MCO is divided by 16
Others: not allowed
Bits 27:24 MCOSEL[3:0]: Microcontroller clock output selection
These bits are set and cleared by software.
0000: MCO output disabled, no clock on MCO
0001: SYSCLK clock selected
0010: HSI16 oscillator clock selected
0011: MSI oscillator clock selected
0100: HSE oscillator clock selected
0101: PLL clock selected
0110: LSI oscillator clock selected
0111: LSE oscillator clock selected
1000: Reserved
Others: reserved
Note: This clock output may have some truncated cycles at startup or during MCO clock
source switching.
Bits 23:22 PLLDIV[1:0]: PLL output division
These bits are set and cleared by software to control PLL output clock division from PLL VCO
clock. These bits can be written only when the PLL is disabled.
00: not allowed
01: PLL clock output = PLLVCO / 2
10: PLL clock output = PLLVCO / 3
11: PLL clock output = PLLVCO / 4

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Bits 21:18 PLLMUL[3:0]: PLL multiplication factor

These bits are written by software to define the PLL multiplication factor to generate the PLL
VCO clock. These bits can be written only when the PLL is disabled.
0000: PLLVCO = PLL clock entry x 3
0001: PLLVCO = PLL clock entry x 4
0010: PLLVCO = PLL clock entry x 6
0011: PLLVCO = PLL clock entry x 8
0100: PLLVCO = PLL clock entry x 12
0101: PLLVCO = PLL clock entry x 16
0110: PLLVCO = PLL clock entry x 24
0111: PLLVCO = PLL clock entry x 32
1000: PLLVCO = PLL clock entry x 48
others: not allowed
Caution: The PLL VCO clock frequency must not exceed 96 MHz when the product is in
Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is in
Range 3.
Bit 17 Reserved, must be kept at reset value.
Bit 16 PLLSRC: PLL entry clock source
This bit is set and cleared by software to select PLL clock source. This bit can be written only
when PLL is disabled.
0: HSI16 oscillator clock selected as PLL input clock
1: HSE oscillator clock selected as PLL input clock
Note: The PLL minimum input clock frequency is 2 MHz.
Bit 15 STOPWUCK: Wake-up from Stop clock selection
This bit is set and cleared by software to select the wake-up from Stop clock.
0: internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock
1: internal 16 MHz (HSI16) oscillator selected as wake-up from Stop clock (or HSI16/4 if
HSI16DIVEN=1)
Bit 14 Reserved, must be kept at reset value.
Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2)
These bits are set and cleared by software to control the division factor of the APB high-
speed clock (PCLK2).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Bits 10:8 PPRE1[2:0]: APB low-speed prescaler (APB1)
These bits are set and cleared by software to control the division factor of the APB low-speed
clock (PCLK1).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16

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Bits 7:4 HPRE[3:0]: AHB prescaler

These bits are set and cleared by software to control the division factor of the AHB clock.
Caution: Depending on the device voltage range, the software has to set correctly these bits
to ensure that the system frequency does not exceed the maximum allowed
frequency (for more details please refer to the Dynamic voltage scaling management
section in the PWR chapter.) After a write operation to these bits and before
decreasing the voltage range, this register must be read to be sure that the new
value has been taken into account.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Bits 3:2 SWS[1:0]: System clock switch status
These bits are set and cleared by hardware to indicate which clock source is used as system
clock.
00: MSI oscillator used as system clock
01: HSI16 oscillator used as system clock
10: HSE oscillator used as system clock
11: PLL used as system clock
Bits 1:0 SW[1:0]: System clock switch
These bits are set and cleared by software to select SYSCLK source.
Set by hardware to force MSI selection when leaving Standby mode or in case of failure of
the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is
enabled).
00: MSI oscillator used as system clock
01: HSI16 oscillator used as system clock
10: HSE oscillator used as system clock
11: PLL used as system clock

7.3.4 Clock interrupt enable register (RCC_CIER)

Address: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSS MSI PLL HSE HSI16 LSE LSI
Res. Res. Res. Res. Res. Res. Res. Res. Res.
LSE RDYIE RDYIE RDYIE RDYIE RDYIE RDYIE
rw rw rw rw rw rw rw rw

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Bits 31:8 Reserved, must be kept at reset value.

Bit 7 CSSLSE: LSE CSS interrupt flag
This bit is set and reset by software to enable/disable the interrupt caused by the Clock
Security System on external 32 kHz oscillator.
0: LSE CSS interrupt disabled
1: LSE CSS interrupt enabled
Bit 6 Reserved, must be kept at reset value.
Bit 5 MSIRDYIE: MSI ready interrupt flag
This bit is set and reset by software to enable/disable the interrupt caused by the MSI
oscillator stabilization.
0: MSI ready interrupt disabled
1: MSI ready interrupt enabled
Bit 4 PLLRDYIE: PLL ready interrupt flag
This bit is set and reset by software to enable/disable the interrupt caused by the PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 3 HSERDYIE: HSE ready interrupt flag
This bit is set and reset by software to enable/disable the interrupt caused by the HSE
oscillator stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Bit 2 HSI16RDYIE: HSI16 ready interrupt flag
This bit is set and reset by software to enable/disable the interrupt caused by the HSI16
oscillator stabilization.
0: HSI16 ready interrupt disabled
1: HSI16 ready interrupt enabled
Bit 1 LSERDYIE: LSE ready interrupt flag
This bit is set and reset by software to enable/disable the interrupt caused by the LSE
oscillator stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 0 LSIRDYIE: LSI ready interrupt flag
This bit is set and reset by software to enable/disable the interrupt caused by the LSI
oscillator stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled

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7.3.5 Clock interrupt flag register (RCC_CIFR)

Address: 0x14
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSS CSS MSI PLL HSE HSI16 LSE LSI
Res. Res. Res. Res. Res. Res. Res. Res.
HSEF LSEF RDYF RDYF RDYF RDYF RDYF RDYF
r r r r r r r r r

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 CSSHSEF: Clock Security System Interrupt flag
This bit is reset by software by writing the CSSHSEC bit. It is set by hardware in case of HSE
clock failure.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bit 7 CSSLSEF: LSE Clock Security System Interrupt flag
This bit is reset by software by writing the CSSLSEC bit. It is set by hardware in case of LSE
clock failure and the CSSLSE is set.
0: No failure detected on LSE clock failure
1: Failure detected on LSE clock failure
Bit:6 Reserved, must be kept at reset value.
Bit 5 MSIRDYF: MSI ready interrupt flag
This bit is reset by software by writing the MSIRDYC bit. It is set by hardware when the MSI
clock becomes stable and the MSIRDYIE is set.
0: No clock ready interrupt caused by MSI clock failure
1: Clock ready interrupt caused by MSI clock failure
Bit 4 PLLRDYF: PLL ready interrupt flag
This bit is reset by software by writing the PLLRDYC bit. It is set by hardware when the PLL
clock becomes stable and the PLLRDYIE is set.
0: No clock ready interrupt caused by PLL clock failure
1: Clock ready interrupt caused by PLL clock failure
Bit 3 HSERDYF: HSE ready interrupt flag
This bit is reset by software by writing the HSERDYC bit. It is set by hardware when the HSE
clock becomes stable and the HSERDYIE is set.
0: No clock ready interrupt caused by HSE clock failure
1: Clock ready interrupt caused by HSE clock failure

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Bit 2 HSI16RDYF: HSI16 ready interrupt flag

This bit is reset by software by writing the HSI16RDYC bit. It is set by hardware when the
HSE clock becomes stable and the HSI16RDYIE is set.
0: No clock ready interrupt caused by HSI16 clock failure
1: Clock ready interrupt caused by HSI16 clock failure
Bit 1 LSERDYF: LSE ready interrupt flag
This bit is reset by software by writing the LSERDYC bit. It is set by hardware when the LSE
clock becomes stable and the LSERDYIE is set.
0: No clock ready interrupt caused by LSE clock failure
1: Clock ready interrupt caused by LSE clock failure
Bit 0 LSIRDYF: LSI ready interrupt flag
This bit is reset by software by writing the LSIRDYC bit. It is set by hardware when the LSI
clock becomes stable and the LSIRDYIE is set.
0: No clock ready interrupt caused by LSI clock failure
1: Clock ready interrupt caused by LSI clock failure

7.3.6 Clock interrupt clear register (RCC_CICR)

Address: 0x18
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSS CSS MSI PLL HSE HSI16 LSE LSI
Res. Res. Res. Res. Res. Res. Res. Res.
HSEC LSEC RDYC RDYC RDYC RDYC RDYIC RDYC
w w w w w w w w

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 CSSHSEC: Clock Security System Interrupt clear
This bit is set by software to clear the CSSHSEF flag. It is reset by hardware.
0: No effect
1: CSSHSEF flag cleared
Bit 7 CSSLSEC: LSE Clock Security System Interrupt clear
This bit is set by software to clear the CSSLSEF flag. It is reset by hardware.
0: No effect
1: CSSLSEF flag cleared
Bit:6 Reserved, must be kept at reset value.
Bit 5 MSIRDYC: MSI ready Interrupt clear
This bit is set by software to clear the MSIRDYF flag. It is reset by hardware.
0: No effect
1: MSIRDYF flag cleared

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Bit 4 PLLRDYC: PLL ready Interrupt clear

This bit is set by software to clear the PLLRDYF flag. It is reset by hardware.
0: No effect
1: PLLRDYF flag cleared
Bit 3 HSERDYC: HSE ready Interrupt clear
This bit is set by software to clear the HSERDYF flag. It is reset by hardware.
0: No effect
1: HSERDYF flag cleared
Bit 2 HSI16RDYC: HSI16 ready Interrupt clear
This bit is set by software to clear the HSI16RDYF flag. It is reset by hardware.
0: No effect
1: HSI16RDYF flag cleared
Bit 1 LSERDYC: LSE ready Interrupt clear
This bit is set by software to clear the LSERDYF flag. It is reset by hardware.
0: No effect
1: LSERDYF flag cleared
Bit 0 LSIRDYC: LSI ready Interrupt clear
This bit is set by software to clear the LSIRDYF flag. It is reset by hardware.
0: No effect
1: LSIRDYF flag cleared

7.3.7 GPIO reset register (RCC_IOPRSTR)

Address: 0x1C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOPH IOPER IOPD IOPC IOPB IOPA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST ST RST RST RST RST
rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 IOPHRST: I/O port H reset
This bit is set and cleared by software.
0: no effect
1: resets I/O port H
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 IOPERST: I/O port E reset
This bit is set and cleared by software.
0: no effect
1: resets I/O port E

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Bit 3 IOPDRST: I/O port D reset

This bit is set and cleared by software.
0: no effect
1: resets I/O port D
Bit 2 IOPCRST: I/O port C reset
This bit is set and cleared by software.
0: no effect
1: resets I/O port C
Bit 1 IOPBRST: I/O port B reset
This bit is set and cleared by software.
0: no effect
1: resets I/O port B
Bit 0 IOPARST: I/O port A reset
This bit is set and cleared by software.
0: no effect
1: resets I/O port A

7.3.8 AHB peripheral reset register (RCC_AHBRSTR)

Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRYP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC MIF DMA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST RST RST
rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 CRYPTRST: Crypto module reset
This bit is set and reset by software.
0: no effect
1: resets CRYPTO module
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 Reserved, must be kept at reset value.
Bits 15: 13 Reserved, must be kept at reset value.
Bit 12 CRCRST: Test integration module reset
This bit is set and reset by software.
0: no effect
1: resets test integration module
Bits 11:9 Reserved, must be kept at reset value.

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Bit 8 MIFRST: Memory interface reset

This bit is set and reset by software.
This reset can be activated only when the E2 is in IDDQ mode.
0: no effect
1: resets memory interface
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 DMARST: DMA reset
This bit is set and reset by software.
0: no effect
1: resets DMA

7.3.9 APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x24
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1 SPI1 ADC TIM22 TIM21 SYSCF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RST RST RST RST RST GRST
rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 DBGRST: DBG reset
This bit is set and cleared by software.
0: No effect
1: Resets DBG
Bits 21:15 Reserved, must be kept at reset value.
Bit 14 USART1RST: USART1 reset
This bit is set and cleared by software.
0: No effect
1: Reset USART1
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1RST: SPI 1 reset
This bit is set and cleared by software.
0: No effect
1: Reset SPI 1
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 ADCRST: ADC interface reset
This bit is set and cleared by software.
0: No effect
1: Reset ADC interface

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Bits 8:6 Reserved, must be kept at reset value.

Bit 5 TIM22RST: TIM22 timer reset
This bit is set and cleared by software.
0: No effect
1: Reset TIM22 timer
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 TIM21RST: TIM21 timer reset
This bit is set and cleared by software.
0: No effect
1: Reset TIM21 timer
Bit 1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST: System configuration controller reset
This bit is set and cleared by software.
0: No effect
1: Reset System configuration controller

7.3.10 APB1 peripheral reset register (RCC_APB1RSTR)

Address offset: 0x28
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1 I2C3R PWR I2C2R I2C1R USART5 USART4 LPUART1 USART2
Res. Res. Res. Res. Res. Res. Res.
RST ST RST ST ST RST RST RST RST
rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIM7R TIM6RS TIM3RS
SPI2R WWDG TIM2
Res. Res. Res. Res. Res. Res. Res. Res. ST T Res. Res. T
ST RST RST

rw rw rw rw rw rw

Bit 31 LPTIM1RST: Low-power timer reset

This bit is set and cleared by software.
0: No effect
1: Resets low-power timer
Bit 30 I2C3RST: I2C3 reset
This bit is set and cleared by software.
0: No effect
1: Resets I2C3
Bit 29 Reserved, must be kept at reset value.
Bit 28 PWRRST: Power interface reset
This bit is set and cleared by software.
0: No effect
1: Reset power interface
Bit 27 Reserved, must be kept at reset value.

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Bits 26:23 Reserved, must be kept at reset value.

Bit 22 I2C2RST: I2C2 reset
This bit is set and cleared by software.
0: No effect
1: Resets I2C2
Bit 21 I2C1RST: I2C1 reset
This bit is set and cleared by software.
0: No effect
1: Resets I2C1
Bit 20 USART5RST: USART5 reset
This bit is set and cleared by software.
0: No effect
1: Resets USART5
Bit 19 USART4RST: USART4 reset
This bit is set and cleared by software.
0: No effect
1: Resets USART4
Bit 18 LPUART1RST: LPUART1 reset
This bit is set and cleared by software.
0: No effect
1: Resets LPUART1
Bit 17 USART2RST: USART2 reset
This bit is set and cleared by software.
0: No effect
1: Resets USART2
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2RST: SPI2 reset
This bit is set and cleared by software.
0: No effect
1: Resets SPI2
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGRST: Window watchdog reset
This bit is set and cleared by software.
0: No effect
1: Resets window watchdog
Bits 10:9 Reserved, must be kept at reset value.
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 TIM7RST: Timer 7 reset
Set and cleared by software.
0: No effect
1: Resets timer7
Bit 4 TIM6RST: Timer 6 reset
Set and cleared by software.
0: No effect
1: Resets timer6

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Bits 3:2 Reserved, must be kept at reset value.

Bit 1 TIM3RST: Timer3 reset
Set and cleared by software.
0: No effect
1: Resets timer3
Bit 0 TIM2RST: Timer2 reset
Set and cleared by software.
0: No effect
1: Resets timer2

7.3.11 GPIO clock enable register (RCC_IOPENR)

Address: 0x2C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOPH IOPE IOPD IOPC IOPB IOPA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN EN EN EN EN EN
rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 IOPHEN: I/O port H clock enable bit
This bit is set and cleared by software.
0: port H clock disabled
1: port H clock enabled
Bits 6:45 Reserved, must be kept at reset value.
Bit 4 IOPEEN: I/O port E clock enable bit
This bit is set and cleared by software.
0: port E clock disabled
1: port E clock enabled
Bit 3 IOPDEN: I/O port D clock enable bit
This bit is set and cleared by software.
0: port D clock disabled
1: port D clock enabled

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Bit 2 IOPCEN: IO port C clock enable bit

This bit is set and cleared by software.
0: port C clock disabled
1: port C clock enabled
Bit 1 IOPBEN: IO port B clock enable bit
This bit is set and cleared by software.
0: port B clock disabled
1: port B clock enabled
Bit 0 IOPAEN: IO port A clock enable bit
This bit is set and cleared by software.
0: port A clock disabled
1: port A clock enabled

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7.3.12 AHB peripheral clock enable register (RCC_AHBENR)

Address offset: 0x30
Reset value: 0x0000 0100
Access: no wait state, word, half-word and byte access
When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRYP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC MIF DMA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN EN EN
rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 CRYPEN: Crypto clock enable bit
This bit is set and reset by software.
0: Crypto clock disabled
1: Crypto clock enabled
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 Reserved, must be kept at reset value.
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable bit
This bit is set and reset by software.
0: Test integration module clock disabled
1: Test integration module clock enabled
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 MIFEN: NVM interface clock enable bit
This bit is set and reset by software.
This reset can be activated only when the NVM is in power-down mode.
0: NVM interface clock disabled
1: NVM interface clock enabled
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 DMAEN: DMA clock enable bit
This bit is set and reset by software.
0: DMA clock disabled
1: DMA clock enabled

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7.3.13 APB2 peripheral clock enable register (RCC_APB2ENR)

Address: 0x34
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in the APB2
domain is on going. In this case, wait states are inserted until the access to APB2 peripheral
is finished.
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1 SPI1 ADC TIM22 TIM21 SYSCF
Res. Res. Res. Res. Res. FWEN Res. Res. Res. Res.
EN EN EN EN EN EN
rw rw rw rs rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 DBGEN: DBG clock enable bit
This bit is set and cleared by software.
0: DBG clock disabled
1: DBG clock enabled
Bits 21:15 Reserved, must be kept at reset value.
Bit 14 USART1EN: USART1 clock enable bit
This bit is set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1EN: SPI1 clock enable bit
This bit is set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 ADCEN: ADC clock enable bit
This bit is set and cleared by software.
0: ADC clock disabled
1: ADC clock enabled
Bit 8 Reserved, must be kept at reset value.
Bit 7 FWEN: Firewall clock enable bit
This bit is set by software and reset by hardware. Software can only program this bit to 1.
Writing 0 has not effect.
0: Firewall disabled
1: Firewall clock enabled

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Bit 6 Reserved, must be kept at reset value.

Bit 5 TIM22EN: TIM22 timer clock enable bit
This bit is set and cleared by software.
0:TIM22 clock disabled
1: TIM22 clock enabled
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 TIM21EN: TIM21 timer clock enable bit
This bit is set and cleared by software.
0: TIM21 clock disabled
1: TIM21 clock enabled
Bit 1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: System configuration controller clock enable bit
This bit is set and cleared by software.
0: System configuration controller clock disabled
1: System configuration controller clock enabled

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7.3.14 APB1 peripheral clock enable register (RCC_APB1ENR)

Address: 0x38
Reset value: 0x0000 0000
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.
Note: When the peripheral clock is not active, the peripheral register values may not be readable
by software and the returned value is always 0x0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1 I2C3E PWRE I2C2E I2C1E USART5 USART4 LPUART1 USART2
Res. Res Res. Res. Res. Res. Res.
EN N N N N EN EN EN EN
rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2E WWDG TIM7E TIM2E
Res. Res. Res. Res. Res. Res. Res. Res. TIM6EN Res. Res. TIM3EN
N EN N N
rw rw rw rw rw rw

Bit 31 LPTIM1EN: Low-power timer clock enable bit

This bit is set and cleared by software.
0: Low-power timer clock disabled
1: Low-power timer clock enabled
Bit 30 I2C3EN: I2C3 clock enable bit
This bit is set and cleared by software.
0: I2C3 clock disabled
1: I2C3 clock enabled
Bit 28 PWREN: Power interface clock enable bit
This bit is set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enabled
Bit 27 Reserved, must be kept at reset value.
Bits 26:23 Reserved, must be kept at reset value.
Bit 22 I2C2EN: I2C2 clock enable bit
This bit is set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
Bit 21 I2C1EN: I2C1 clock enable bit
This bit is set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
Bit 20 USART5EN: USART5 clock enable bit
This bit is set and cleared by software.
0: USART5 clock disabled
1: USART5 clock enabled

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Reset and clock control (RCC) RM0377

Bit 19 USART4EN: USART4 clock enable bit

This bit is set and cleared by software.
0: USART4 clock disabled
1: USART4 clock enabled
Bit 18 LPUART1EN: LPUART1 clock enable bit
This bit is set and cleared by software.
0: LPUART1 clock disabled
1: LPUART1 clock enabled
Bit 17 USART2EN: USART2 clock enable bit
This bit is set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2EN: SPI2 clock enable bit
This bit is set and cleared by software.
0: SPI2 clock disabled
1: SPI2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable bit
This bit is set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bits 10:9 Reserved, must be kept at reset value.
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 TIM7EN: Timer 7 clock enable bit
Set and cleared by software.
0: Timer 7 clock disabled
1: Timer 7 clock enabled
Bit 4 TIM6EN: Timer 6 clock enable bit
Set and cleared by software.
0: Timer 6 clock disabled
1: Timer 6 clock enabled
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM3EN: Timer3 clock enable bit
Set and cleared by software.
0: Timer3 clock disabled
1: Timer3 clock enabled
Bit 0 TIM2EN: Timer2 clock enable bit
Set and cleared by software.
0: Timer2 clock disabled
1: Timer2 clock enabled

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RM0377 Reset and clock control (RCC)

7.3.15 GPIO clock enable in Sleep mode register (RCC_IOPSMENR)

Address: 0x3C
Reset value: the bits corresponding to the available GPIO ports are set
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IOPHS IOPES IOPDS IOPCS IOPBS IOPAS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
MEN MEN MEN MEN MEN MEN
rw rw rw rw rw rw

Bits 31: 8 Reserved, must be kept at reset value.

Bit 7 IOPHSMEN: Port H clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Port H clock is disabled in Sleep mode
1: Port H clock is enabled in Sleep mode (if enabled by IOPHEN)
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 IOPESMEN: Port E clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Port E clock is disabled in Sleep mode
1: Port E clock is enabled in Sleep mode (if enabled by IOPDEN)
Bit 3 IOPDSMEN: Port D clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Port D clock is disabled in Sleep mode
1: Port D clock is enabled in Sleep mode (if enabled by IOPDEN)
Bit 2 IOPCSMEN: Port C clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Port C clock is disabled in Sleep mode
1: Port C clock is enabled in Sleep mode (if enabled by IOPCEN)
Bit 1 IOPBSMEN: Port B clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Port B clock is disabled in Sleep mode
1: Port B clock is enabled in Sleep mode (if enabled by IOPBEN)
Bit 0 IOPASMEN: Port A clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Port A clock is disabled in Sleep mode
1: Port A clock is enabled in Sleep mode (if enabled by IOPAEN)

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Reset and clock control (RCC) RM0377

7.3.16 AHB peripheral clock enable in Sleep mode

register (RCC_AHBSMENR)
Address: 0x40
Reset value: the bits corresponding to the available peripherals are set
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CRYP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC SRAM MIF DMA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SMEN SMEN SMEN SMEN
rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 CRYPSMEN: Crypto clock enable during Sleep mode bit
This bit is set and reset by software.
0: Crypto clock disabled in Sleep mode
1: Crypto clock enabled in Sleep mode
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 Reserved, must be kept at reset value.
Bits 15: 13 Reserved, must be kept at reset value.
Bit 12 CRCSMEN: CRC clock enable during Sleep mode bit
This bit is set and reset by software.
0: Test integration module clock disabled in Sleep mode
1: Test integration module clock enabled in Sleep mode (if enabled by CRCEN)
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 SRAMSMEN: SRAM interface clock enable during Sleep mode bit
This bit is set and reset by software.
0: NVM interface clock disabled in Sleep mode
1: NVM interface clock enabled in Sleep mode
Bit 8 MIFSMEN: NVM interface clock enable during Sleep mode bit
This bit is set and reset by software.
0: NVM interface clock disabled in Sleep mode
1: NVM interface clock enabled in Sleep mode
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 DMASMEN: DMA clock enable during Sleep mode bit
This bit is set and reset by software.
0: DMA clock disabled in Sleep mode
1: DMA clock enabled in Sleep mode

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RM0377 Reset and clock control (RCC)

7.3.17 APB2 peripheral clock enable in Sleep mode

register (RCC_APB2SMENR)
Address: 0x44
Reset value: the bits corresponding to the available peripherals are set.
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SMEN
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART1 SPI1 ADC TIM22 TIM21 SYSCF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SMEN SMEN SMEN SMEN SMEN SMEN
rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 DBGSMEN: DBG clock enable during Sleep mode bit
This bit is set and cleared by software.
0: DBG clock disabled in Sleep mode
1: DBG clock enabled in Sleep mode (if enabled by DBGEN)
Bits 21:15 Reserved, must be kept at reset value.
Bit 14 USART1SMEN: USART1 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: USART1 clock disabled in Sleep mode
1: USART1 clock enabled in Sleep mode (if enabled by USART1EN)
Bit 13 Reserved, must be kept at reset value.
Bit 12 SPI1SMEN: SPI1 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: SPI1 clock disabled in Sleep mode
1: SPI1 clock enabled in Sleep mode (if enabled by SPI1EN)
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 ADCSMEN: ADC clock enable during Sleep mode bit
This bit is set and cleared by software.
0: ADC clock disabled in Sleep mode
1: ADC clock enabled in Sleep mode (if enabled by ADCEN)
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 TIM22SMEN: TIM22 timer clock enable during Sleep mode bit
This bit is set and cleared by software.
0:TIM22 clock disabled in Sleep mode
1: TIM22 clock enabled in Sleep mode (if enabled by TIM22EN)
Bits 4:3 Reserved, must be kept at reset value.

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Reset and clock control (RCC) RM0377

Bit 2 TIM21SMEN: TIM21 timer clock enable during Sleep mode bit
This bit is set and cleared by software.
0: TIM21 clock disabled in Sleep mode
1: TIM21 clock enabled in Sleep mode (if enabled by TIM21EN)
Bit 1 Reserved, must be kept at reset value.
Bit 0 SYSCFGSMEN: System configuration controller clock enable during Sleep mode bit
This bit is set and cleared by software.
0: System configuration controller clock disabled in Sleep mode
1: System configuration controller clock enabled in Sleep mode

7.3.18 APB1 peripheral clock enable in Sleep mode

register (RCC_APB1SMENR)
Address: 0x48
Reset value: the bits corresponding to the available peripherals are set
Note: Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1 I2C3S PWRS I2C2S I2C1S USART5 USART4 LPUART1 USART2
Res. Res. Res. Res. Res. Res. Res.
SMEN MEN MEN MEN MEN SMEN SMEN SMEN SMEN
rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPI2S WWDG TIM7S TIM6SM TIM3SM TIM2S
Res. Res. Res. Res. Res. Res. Res. Res. Res.
MEN SMEN MEN EN EN MEN
rw rw rw rw rw rw

Bit 31 LPTIM1SMEN: Low-power timer clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Low-power timer clock disabled in Sleep mode
1: Low-power timer clock enabled in Sleep mode (if enabled by LPTIM1EN)
Bit 30 I2C3SMEN: I2C3 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: I2C3 clock disabled in Sleep mode
1: I2C3 clock enabled in Sleep mode (if enabled by I2C3EN)
Bit 29 Reserved, must be kept at reset value.
Bit 28 PWRSMEN: Power interface clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Power interface clock disabled in Sleep mode
1: Power interface clock enabled in Sleep mode (if enabled by PWREN)
Bit 27 Reserved, must be kept at reset value.
Bits 26:23 Reserved, must be kept at reset value.
Bit 22 I2C2SMEN: I2C2 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: I2C2 clock disabled in Sleep mode
1: I2C2 clock enabled in Sleep mode (if enabled by I2C2EN)

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RM0377 Reset and clock control (RCC)

Bit 21 I2C1SMEN: I2C1 clock enable during Sleep mode bit

This bit is set and cleared by software.
0: I2C1 clock disabled in Sleep mode
1: I2C1 clock enabled in Sleep mode (if enabled by I2C1EN)
Bit 20 USART5SMEN: USART5 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: USART5 clock disabled in Sleep mode
1: USART5 clock enabled in Sleep mode (if enabled by USART5EN)
Bit 19 USART4SMEN: USART4 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: USART4 clock disabled in Sleep mode
1: USART4 clock enabled in Sleep mode (if enabled by USART4EN)
Bit 18 LPUART1SMEN: LPUART1 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: LPUART1 clock disabled in Sleep mode
1: LPUART1 clock enabled in Sleep mode (if enabled by LPUART1EN)
Bit 17 USART2SMEN: USART2 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: USART2 clock disabled in Sleep mode
1: USART2 clock enabled in Sleep mode (if enabled by USART2EN)
Bits 16:15 Reserved, must be kept at reset value.
Bit 14 SPI2SMEN: SPI2 clock enable during Sleep mode bit
This bit is set and cleared by software.
0: SPI2 clock disabled in Sleep mode
1: SPI2 clock enabled in Sleep mode (if enabled by SPI2SEN)
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGSMEN: Window watchdog clock enable during Sleep mode bit
This bit is set and cleared by software.
0: Window watchdog clock disabled in Sleep mode
1: Window watchdog clock enabled in Sleep mode (if enabled by WWDGEN)
Bits 10:9 Reserved, must be kept at reset value.
Bits 8:6 Reserved, must be kept at reset value.
Bit 5 TIM7SMEN: Timer 7 clock enable during Sleep mode bit
Set and cleared by software.
0: Timer 7 clock disabled in Sleep mode
1: Timer 7 clock enabled in Sleep mode (if enabled by TIM7EN)
Bit 4 TIM6SMEN: Timer 6 clock enable during Sleep mode bit
Set and cleared by software.
0: Timer 6 clock disabled in Sleep mode
1: Timer 6 clock enabled in Sleep mode (if enabled by TIM6EN)

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Bits 3:2 Reserved, must be kept at reset value.

Bit 1 TIM3SMEN: Timer3 clock enable during Sleep mode bit
Set and cleared by software.
0: Timer3 clock disabled in Sleep mode
1: Timer3 clock enabled in Sleep mode (if enabled by TIM3EN)
Bit 0 TIM2SMEN: Timer2 clock enable during Sleep mode bit
Set and cleared by software.
0: Timer2 clock disabled in Sleep mode
1: Timer2 clock enabled in Sleep mode (if enabled by TIM2EN)

7.3.19 Clock configuration register (RCC_CCIPR)

Address: 0x4C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPTIM1 LPTIM1S I2C3SE I2C3SE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SEL1 EL0 L1 L0
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C1 I2C1 LPUART1 LPUART1 USART2 USART2 USART1 USART1
Res. Res. Res. Res. Res. Res. Res. Res.
SEL1 SEL0 SEL1 SEL0 SEL1 SEL0 SEL1 SEL0
rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:20 Reserved, must be kept at reset value.
Bits 19:18 LPTIM1SEL: Low-power Timer clock source selection bits
This bit is set and cleared by software.
00: APB clock selected as LP Timer clock
01: LSI clock selected as LP Timer clock
10: HSI16 clock selected as LP Timer clock
11: LSE clock selected as LP Timer clock
Bits 17:16 I2C3SEL: I2C3 clock source selection bits
This bit is set and cleared by software.
00: APB clock selected as I2C3 clock
01: System clock selected as I2C3 clock
10: HSI16 clock selected as I2C3 clock
11: not used
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:12 I2C1SEL: I2C1 clock source selection bits
This bit is set and cleared by software.
00: APB clock selected as I2C1 clock
01: System clock selected as I2C1 clock
10: HSI16 clock selected as I2C1 clock
11: not used

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RM0377 Reset and clock control (RCC)

Bits 11:10 LPUART1SEL: LPUART1 clock source selection bits

This bit is set and cleared by software.
00: APB clock selected as LPUART1 clock
01: System clock selected as LPUART1 clock
10: HSI16 clock selected as LPUART1 clock
11: LSE clock selected as LPUART1 clock
Bits 9:4 Reserved, must be kept at reset value.
Bits 3:2 USART2SEL: USART2 clock source selection bits
This bit is set and cleared by software.
00: APB clock selected as USART2 clock
01: System clock selected as USART2 clock
10: HSI16 clock selected as USART2 clock
11: LSE clock selected as USART2 clock
Bits 1:0 USART1SEL: USART1 clock source selection bits
This bit is set and cleared by software.
00: APB clock selected as USART1 clock
01: System clock selected as USART1 clock
10: HSI16 clock selected as USART1 clock
11: LSE clock selected as USART1 clock

7.3.20 Control/status register (RCC_CSR)

Address: 0x50
Power-on reset value: 0x0C00 0004
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note: The LSEON, LSEBYP, RTCSEL,LSEDRV and RTCEN bits in the RCC control and status
register (RCC_CSR) are in the RTC domain. As these bits are write protected after reset,
the DBP bit in the Power control register (PWR_CR) has to be set to be able to modify them.
Refer to Section 6.1.2: RTC and RTC backup registers for further information. These bits
are only reset after a RTC domain reset (see Section 6.1.2). Any internal or external reset
does not have any effect on them.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LPWR WWDG IWDG SFT POR PIN OBL FW RTC RTC
RMVF Res. Res. Res. RTCSEL[1:0]
RSTF RSTF RSTF RSTF RSTF RSTF RS TF RSTF RST. EN
r r r r r r r r rt_w rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSSLS CSSLS LSE LSI
Res. LSEDRV[1:0] LSERDY LSEON Res. Res. Res. Res. Res. Res. LSION
ED EON BYP RDY
r rw rw rw r rw r rw

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Reset and clock control (RCC) RM0377

Bit 31 LPWRRSTF: Low-power reset flag

This bit is set by hardware when a Low-power management reset occurs.
It is cleared by writing to the RMVF bit, or by a POR.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to Section : Low-power
management reset.
Bit 30 WWDGRSTF: Window watchdog reset flag
This bit is set by hardware when a window watchdog reset occurs.
It is cleared by writing to the RMVF bit, or by a POR.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent watchdog reset flag
This bit is set by hardware when an independent watchdog reset from VDD domain occurs.
It is cleared by writing to the RMVF bit, or by a POR.
0: No watchdog reset occurred
1: Watchdog reset occurred
Bit 28 SFTRSTF: Software reset flag
This bit is set by hardware when a software reset occurs.
It is cleared by writing to the RMVF bit, or by a POR.
0: No software reset occurred
1: Software reset occurred
Bit 27 PORRSTF: POR/PDR reset flag
This bit is set by hardware when a POR/PDR reset occurs.
It is cleared by writing to the RMVF bit.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred
Bit 26 PINRSTF: PIN reset flag
This bit is set by hardware when a reset from the NRST pin occurs.
It is cleared by writing to the RMVF bit, or by a POR.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 OBLRSTF Options bytes loading reset flag
This bit is set by hardware when an OBL reset occurs.
It is cleared by writing to the RMVF bit, or by a POR.
0: No OBL reset occurred
1: OBL reset occurred
Bit 24 FWRSTF: Firewall reset flag
This bit is set by hardware when the firewall has generated a reset. It is cleared by writing to
the RMVF bit, or by a power-on reset.
0: No firewall reset occurred
1: firewall reset occurred
Bit 23 RMVF: Remove reset flag
This bit is set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
Bits 22:20 Reserved, must be kept at reset value.

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RM0377 Reset and clock control (RCC)

Bit 19 RTCRST: RTC software reset bit

This bit is set and cleared by software.
0: Reset not activated
1: Resets the RTC peripheral, its clock source selection and the backup registers.
Bit 18 RTCEN: RTC clock enable bit
This bit is set and cleared by software.
It is reset by setting the RTCRST bit or by a POR.
0: RTC clock disabled
1: RTC clock enabled
Bits 17:16 RTCSEL[1:0]: RTC clock source selection bits
These bits are set by software to select the clock source for the RTC.
Once the RTC clock source has been selected it cannot be switched until RTCRST is set or
a Power On Reset occurred. The only exception is if the LSE oscillator clock was selected, if
the LSE clock stops and it is detected by the CSSLSE, in that case the clock can be
switched.
00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by a programmable prescaler (selection through the
RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock

If the LSE or LSI is used as RTC clock source, the RTC continues to work in Stop and
Standby low-power modes, and can be used as wake-up source. However, when the HSE
clock is used as RTC clock source, the RTC cannot be used in Stop and Standby low-power
modes.
Bit 15 Reserved, must be kept at reset value.
Bit 14 CSSLSED: CSS on LSE failure detection flag
This bit is set by hardware to indicate when a failure has been detected by the clock security
system on the external 32 kHz oscillator (LSE).
It is cleared by a power-on reset or by an RTC software reset (RTCRST bit).
0: No failure detected on LSE (32 kHz oscillator)
1: Failure detected on LSE (32 kHz oscillator)
Bit 13 CSSLSEON CSS on LSE enable bit
This bit is set by software to enable the Clock Security System on LSE (32 kHz oscillator).
CSSLSEON must be enabled after the LSE and LSI oscillators are enabled (LSEON and
LSION bits enabled) and ready (LSERDY and LSIRDY flags set by hardware), and after the
RTCSEL bit is selected.
Once enabled this bit cannot be disabled, except after an LSE failure detection (CSSLSED
=1). In that case the software MUST disable the CSSLSEON bit.
Reset by power on reset and RTC software reset (RTCRST bit).
0: CSS on LSE (32 kHz oscillator) OFF
1: CSS on LSE (32 kHz oscillator) ON
Bits 12-11 LSEDRV; LSE oscillator Driving capability bits
These bits are set by software to select the driving capability of the LSE oscillator.
They are cleared by a power-on reset or an RTC reset. Once “00” has been written, the
content of LSEDRV cannot be changed by software.
00: Lowest drive
01: Medium low drive
10: Medium high drive
11: Highest drive

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Reset and clock control (RCC) RM0377

Bit 10 LSEBYP: External low-speed oscillator bypass bit

This bit is set and cleared by software to bypass oscillator in debug mode. This bit can be
written only when the LSE oscillator is disabled.
It is reset by setting the RTCRST bit or by a POR.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 9 LSERDY: External low-speed oscillator ready bit
This bit is set and cleared by hardware to indicate when the LSE oscillator is stable. After the
LSEON bit is cleared, LSERDY goes low after 6 LSE oscillator clock cycles.
It is reset by setting the RTCRST bit or by a POR.
0: External 32 kHz oscillator not ready
1: External 32 kHz oscillator ready
Bit 8 LSEON: External low-speed oscillator enable bit
This bit is set and cleared by software.
It is reset by setting the RTCRST bit or by a POR.
0: LSE oscillator OFF
1:LSE oscillator ON
Bits 7:3 Reserved, must be kept at reset value.
Bit 1 LSIRDY: Internal low-speed oscillator ready bit
This bit is set and cleared by hardware to indicate when the LSI oscillator is stable. After the
LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles.
This bit is reset by system reset.
0: LSI oscillator not ready
1: LSI oscillator ready
Bit 0 LSION: Internal low-speed oscillator enable bit
This bit is set and cleared by software.
It is reset by system reset.
0: LSI oscillator OFF
1: LSI oscillator ON

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 0x08
set

0x20
0x18
0x14
0x10
0x04
0x00
Off-

0x1C
0x0C
7.3.21
RM0377

RCC_CR

RCC_CIFR
RCC_CIER
Register

RCC_CICR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

RCC_CFGR
RCC_ICSCR

RCC_IOPRSTR

RCC_AHBRSTR
0
Res. Res. Res. Res. Res. Res. Res. 31

0
0
Res. Res. Res. Res. Res. Res. 30

0
0

E
Res. Res. Res. Res. Res. Res. 29

[2:0]
MCOPR

0
0
Res. Res. Res. Res. Res. Res. 28

0
RCC register map

Res. Res. Res. Res. Res. Res. Res. 27

0
0
Res. Res. Res. Res. Res. Res.

MSITRIM[7:0]
26

0
0
0
Res. Res. Res. Res. Res. PLL RDY 25

L [3:0]
MCOSE

0
0
0
0
CRYPRST Res. Res. Res. Res. PLL ON 24

0
Res. Res. Res. Res. Res. Res. 23

DIV
PLL

[1:0]
x

0
Res. Res. Res. Res. Res. Res. 22

0
Res. Res. Res. Res. Res. 21
[1:0]
RTC
PRE

0
0
Res. Res. Res. Res. Res. 20

0]
x

0
Res. Res. Res. Res. Res. CSSLSEON 19

PLLMUL[3:
x

0
Res. Res. Res. Res. Res. HSEBYP
MSICAL[7:0]

Reserved
18

RM0377 Rev 10
x
X X 0 X 0

Res. Res. Res. Res. Res. Res. HSERDY 17

x

0
0
0

Res. Res. Res. Res. Res. PLLSRC HSEON 16

0
1

Res. Res. Res. Res. Res. STOPWUCK Res. 15

0

Res. Res. Res. Res. Res. Res. Res. 14

GE[2:0]

0
1
MSIRAN

Res. Res. Res. Res. Res. Res. 13

0
0
1

CRCRST Res. Res. Res. Res. Res. 12

[2:0]
Table 44. RCC register map and reset values

PPRE2

0
0

Res. Res. Res. Res. Res. Res. 11

]

0
0

Res. Res. Res. Res. Res. Res. 10

0
0
1

Res. Res. Res. Res. Res. MSIRDY

The following table gives the RCC register map and the reset values.

9
[2:0]
PPRE1
HSI16TRIM[4:0

0
0
0
1

0
0
MIFRST Res. CSSHSEC. CSSHSEF. Res. MSION 8
x

0
0
0
0
Res. IOPHRS CSSLSEC. CSSLSEF. CSSLSE Res. 7
x

0
0
0

Res. Res. Res. Res. Res. Res. 6

x

0
0
0
0

Res. Res. MSIRDYC MSIRDYF MSIRDYIE HSI16OUTEN 5

HPRE[3:0]
x

0
0
0

0
0
Res. IOPERST PLLRDYC PLLRDYF PLLRDYIE HSI16DIVF 4
x

0
0
0

0
0
Res. IOPDRS HSERDYC HSERDYF HSERDYIE HSI16DIVEN 3
[1:0]
x

0
0
0

0
0
SWS

Res. IOPCRS HSI16RDYC HSI16RDYF HSI16RDYIE HSI16RDYF 2

HSI16CAL[7:0]

0
0
0

0
0
Res. IOPBRST LSERDYC LSERDYF LSERDYIE HSI16KERON 1
SW
[1:0]
x

0
0

0
0
0
0
0

DMARST IOPARST LSIRDYC LSIRDYF LSIRDYIE HSI16ON

Reset and clock control (RCC)

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215
 set

0x44
0x40
0x38
0x34
0x30
0x28
0x24
Off-

0x3C
0x2C

214/905
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value

RCC_IOPENR

RCC_AHBENR

RCC_IOPSMEN
RCC_APB1ENR
RCC_APB2ENR
RCC_APB1RSTR
RCC_APB2RSTR

RCC_AHBSMENR

RCC_APB2SMENR
0
0
Res. Res. Res. LPTIM1EN Res. Res. Res. LPTIM1RST Res. 31

0
0
Res. Res. Res. I2C3EN Res. Res. Res. I2C3RST Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Reset and clock control (RCC)

0
0
Res. Res. Res. PWREN Res. Res. Res. PWRRST Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

1
0
Res. CRYPSMEN Res. Res. Res. CRYPEN Res. Res. Res. 24
Res. Res. Res. Res Res. Res. Res. Res. Res. 23

1
0
0

0
0
DBGSMEN Res. Res. I2C2EN DBGEN Res. Res. I2C2RST DBGRST 22

0
0
Res. Res. Res. I2C1EN Res. Res. Res. I2C1RST Res. 21

0
0
Res. Res. Res. USART5EN Res. Res. Res. USART5RST Res. 20

0
0

Res. Res. Res. USART4EN Res. Res. Res. USART4RST Res. 19

0
0

Res. Res. Res. LPUART1EN Res. Res. Res. LPUART1RST Res. 18

RM0377 Rev 10
0
0

Res. Res. Res. USART2EN Res. Res. Res. USART2RST Res. 17

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. 15

1
0
0

0
0

USART1SMEN Res. Res. SPI2EN USART1EN Res. Res. SPI2RST USART1RST 14

Res. Res. Res. Res. Res. Res. Res. Res. Res. 13

1
1
0
0
0

SPI1SMEN CRCSMEN Res. Res. SPI1EN CRCEN Res. Res. SPI1RST 12

0
0

Res. Res. Res. WWDGEN Res. Res. Res. WWDRST Res. 11

Res. Res. Res. Res. Res. Res. Res. Res. Res. 10

1
1
0
0

ADCSMEN SRAMSMEN Res. Res ADCEN Res. Res. Res. ADCRST 9

Table 44. RCC register map and reset values (continued)

1
1

Res. MIFSMEN Res. Res. Res. MIFEN Res. Res. Res. 8

0

1
0

Res. Res. IOPHSMEN Res. FWEN Res. IOPHEN Res. Res. 7

Res. Res. Res. Res. Res. Res. Res. Res. Res. 6

1
0
0

0
0

TIM22SMEN Res. Res. TIM7EN TIM22EN Res. Res. TIM7RST TM12RST 5

0
0

1
0

Res. Res. IOPESMEN TIM6EN Res. Res. IOPEEN TIM6RST Res. 4

1
0

Res. Res. IOPDSMEN Res. Res. Res. IOPDEN Res. Res. 3

1
0
0

1
0

TIM21SMEN Res. IOPCSMEN 0 Res. TIM21EN Res. IOPCEN Res. TIM21RST 2

0

1
0

Res. Res. IOPBSMEN TIM3EN Res. Res. IOPBEN TIM3RST Res. 1

1
1
0
0
0

0
0

1
0

SYSCFGSMEN DMASMEN IOPASMEN TIM2EN SYSCFGEN DMAEN IOPAEN TIM2RST SYSCFGRST

RM0377

0
 set

0x50
0x48
Off-

0x4C
RM0377

RCC_CSR
Register

Reset value
Reset value
Reset value

RCC_CCIPR
RCC_APB1SMENR

0
1
LPWRSTF Res. LPTIM1SMEN 31

0
1
WWDGRSTF Res. I2C3SMEN 30

0
IWDGRSTF Res. Res. 29

0
1
SFTRSTF Res. PWRSMEN 28

1
PORRSTF Res. Res. 27

1
PINRSTF Res Res. 26

0
OBLRSTF Res. Res. 25

0
FWRSTF Res. Res. 24

0
RMVF Res. Res 23
1

Res. Res. I2C2SMEN 22

1

Res. Res. I2C1SMEN 21

1

Res. Res. USART5SMEN 20

0
0
1

RTCRST LPTIM1SEL1 USART4SMEN 19

0
0
1

RTCEN LPTIM1SEL0 LPUART1SMEN 18

RM0377 Rev 10
0
0
1

SEL I2C3SEL1 USART2SMEN 17

[1:0]
RTC

0
0

I2C3SEL0 Res. 16
Res. Res. Res. 15
0
1

0 CSSLSED Res. SPI2SMEN 14

0

CSSLSEON I2C1SEL1 Res. 13

0
0

I2C1SEL0 Res. 12
LSE

[1:0]
DRV

0
0
1

LPUART1SEL1 WWDGSMEN 11
0
0

LSEBYP LPUART1SEL0 Res. 10

0

LSERDY Res. Res

Refer to Section 2.2 on page 51 for the register boundary addresses.

9
Table 44. RCC register map and reset values (continued)

LSEON Res. Res. 8

Res. Res. Res. 7
Res. Res. Res. 6
1

Res. Res. TIM7SMEN 5

1

Res. Res. TIM6SMEN 4

0

Res. USART2SEL1 Res. 3

0

Res. USART2SEL0 Res. 2

0
0
1

LSIRDY USART1SEL1 TIM3SMEN 1

0
0
1

LSION USART1SEL0 TIM2SMEN

Reset and clock control (RCC)

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General-purpose I/Os (GPIO) RM0377

8 General-purpose I/Os (GPIO)

8.1 Introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition
all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function
selection registers (GPIOx_AFRH and GPIOx_AFRL).

8.2 GPIO main features

• Output states: push-pull or open drain + pull-up/down
• Output data from output data register (GPIOx_ODR) or peripheral (alternate function
output)
• Speed selection for each I/O
• Input states: floating, pull-up/down, analog
• Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
• Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR
• Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations
• Analog function
• Alternate function selection registers
• Fast toggle capable of changing every two clock cycles
• Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several
peripheral functions

8.3 GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in
several modes:
• Input floating
• Input pull-up
• Input-pull-down
• Analog
• Output open-drain with pull-up or pull-down capability
• Output push-pull with pull-up or pull-down capability
• Alternate function push-pull with pull-up or pull-down capability
• Alternate function open-drain with pull-up or pull-down capability
Each I/O port bit is freely programmable, however the I/O port registers have to be
accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is
to allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there
is no risk of an IRQ occurring between the read and the modify access.

216/905 RM0377 Rev 10

RM0377 General-purpose I/Os (GPIO)

Figure 19 and Figure 20 show the basic structures of a standard and a 5-Volt tolerant I/O
port bit, respectively. Table 45 gives the possible port bit configurations.

Figure 19. Basic structure of an I/O port bit

Analog
To on-chip
peripheral Alternate function input

Input data register on/off

Read
VDDIOxVDDIOx
Bit set/reset registers

Protection
trigger on/off
Pull diode
up
Input driver I/O pin
Output data register

Write

Output driver VDDIOx on/off Protection

Pull
down diode
P-MOS
VSS
Output VSS
control
N-MOS
Read/write
VSS
Push-pull,
From on-chip open-drain or
peripheral Alternate function output
disabled
Analog

MS31476V1

Figure 20. Basic structure of a 5-Volt tolerant I/O port bit

To on-chip
peripheral
Alternate function input

on/off
Input data register

Read (1)
VDDIOx VDD_FT

TTL Schmitt
Bit set/reset registers

Protection
trigger on/off
Pull diode
up
Input driver I/O pin
Write
Output data register

Output driver VDDIOx on/off Pull Protection

down
diode
P-MOS
Output VSS
VSS
control
Read/write N-MOS

From on-chip VSS

Push-pull,
peripheral Alternate function output open-drain or
disabled

ai15939d

1. VDD_FT is a potential specific to 5-Volt tolerant I/Os and different from VDD.

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General-purpose I/Os (GPIO) RM0377

Table 45. Port bit configuration table(1)

MODE(i) OSPEED(i) PUPD(i)
OTYPER(i) I/O configuration
[1:0] [1:0] [1:0]

0 0 0 GP output PP
0 0 1 GP output PP + PU
0 1 0 GP output PP + PD
0 SPEED 1 1 Reserved
01
1 [1:0] 0 0 GP output OD
1 0 1 GP output OD + PU
1 1 0 GP output OD + PD
1 1 1 Reserved (GP output OD)
0 0 0 AF PP
0 0 1 AF PP + PU
0 1 0 AF PP + PD
0 SPEED 1 1 Reserved
10
1 [1:0] 0 0 AF OD
1 0 1 AF OD + PU
1 1 0 AF OD + PD
1 1 1 Reserved
x x x 0 0 Input Floating
x x x 0 1 Input PU
00
x x x 1 0 Input PD
x x x 1 1 Reserved (input floating)
x x x 0 0 Input/output Analog
x x x 0 1
11
x x x 1 0 Reserved
x x x 1 1
1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate
function.

8.3.1 General-purpose I/O (GPIO)

During and just after reset, the alternate functions are not active and most of the I/O ports
are configured in analog mode.
The debug pins are in AF pull-up/pull-down after reset:
• PA14: SWCLK in pull-down
• PA13: SWDIO in pull-up

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RM0377 General-purpose I/Os (GPIO)

When the pin is configured as output, the value written to the output data register
(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull
mode or open-drain mode (only the low level is driven, high level is HI-Z).
The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB
clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or
not depending on the value in the GPIOx_PUPDR register.

8.3.2 I/O pin alternate function multiplexer and mapping

The device I/O pins are connected to on-board peripherals/modules through a multiplexer
that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In
this way, there can be no conflict between peripherals available on the same I/O pin.
Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that
can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to
15) registers:
• After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are
configured in alternate function mode through GPIOx_MODER register.
• The specific alternate function assignments for each pin are detailed in the device
datasheet.
In addition to this flexible I/O multiplexing architecture, each peripheral has alternate
functions mapped onto different I/O pins to optimize the number of peripherals available in
smaller packages.
To use an I/O in a given configuration, the user has to proceed as follows:
• Debug function: after each device reset these pins are assigned as alternate function
pins immediately usable by the debugger host
• GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER
register.
• Peripheral alternate function:
– Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH
register.
– Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively.
– Configure the desired I/O as an alternate function in the GPIOx_MODER register.
• Additional functions:
– For the ADC and COMP, configure the desired I/O in analog mode in the
GPIOx_MODER register and configure the required function in the ADC and
COMP registers.
– For the additional functions like RTC, WKUPx and oscillators, configure the
required function in the related RTC, PWR and RCC registers. These functions
have priority over the configuration in the standard GPIO registers.
Refer to the “Alternate function mapping” table in the device datasheet for the detailed
mapping of the alternate function I/O pins.

RM0377 Rev 10 219/905

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General-purpose I/Os (GPIO) RM0377

8.3.3 I/O port control registers

Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The
GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The
GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-
pull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pull-
up/pull-down whatever the I/O direction.

8.3.4 I/O port data registers

Each GPIO has two 16-bit memory-mapped data registers: input and output data registers
(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write
accessible. The data input through the I/O are stored into the input data register
(GPIOx_IDR), a read-only register.
See Section 8.4.5: GPIO port input data register (GPIOx_IDR) (x = A to E and H) and
Section 8.4.6: GPIO port output data register (GPIOx_ODR) (x = A to E and H) for the
register descriptions.

8.3.5 I/O data bitwise handling

The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to
set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset
register has twice the size of GPIOx_ODR.
To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i).
When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i)
resets the ODR(i) corresponding bit.
Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in
GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set
action takes priority.
Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a
“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always
be accessed directly. The GPIOx_BSRR register provides a way of performing atomic
bitwise handling.
There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify one or more bits in a single atomic AHB write access.

8.3.6 GPIO locking mechanism

It is possible to freeze the GPIO control registers by applying a specific write sequence to
the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When
the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used
to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must
be the same). When the LOCK sequence has been applied to a port bit, the value of the port
bit can no longer be modified until the next MCU reset or peripheral reset. Each
GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.

220/905 RM0377 Rev 10

RM0377 General-purpose I/Os (GPIO)

The LOCK sequence (refer to Section 8.4.8: GPIO port configuration lock register
(GPIOx_LCKR) (x = A to E and H)) can only be performed using a word (32-bit long)
access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set
at the same time as the [15:0] bits.
For code example, refer to A.5.1: Locking mechanism code example.
For more details refer to LCKR register description in Section 8.4.8: GPIO port configuration
lock register (GPIOx_LCKR) (x = A to E and H).

8.3.7 I/O alternate function input/output

Two registers are provided to select one of the alternate function inputs/outputs available for
each I/O. With these registers, the user can connect an alternate function to some other pin
as required by the application.
This means that a number of possible peripheral functions are multiplexed on each GPIO
using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can
thus select any one of the possible functions for each I/O. The AF selection signal being
common to the alternate function input and alternate function output, a single channel is
selected for the alternate function input/output of a given I/O.
To know which functions are multiplexed on each GPIO pin refer to the device datasheet.
For code example, refer to A.5.2: Alternate function selection sequence code example.

8.3.8 External interrupt/wakeup lines

All ports have external interrupt capability. To use external interrupt lines, the port must be
configured in input mode.
Refer to Section 12: Extended interrupt and event controller (EXTI) and to Section 12.3.2:
Wakeup event management.

8.3.9 Input configuration

When the I/O port is programmed as input:
• The output buffer is disabled
• The Schmitt trigger input is activated
• The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register provides the I/O state
Figure 21 shows the input configuration of the I/O port bit.

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General-purpose I/Os (GPIO) RM0377

Figure 21. Input floating / pull up / pull down configurations

Input data register

on
Read
VDDIOx VDDIOx
Bit set/reset registers
TTL Schmitt on/off
trigger protection
pull diode
Write Output data register up
input driver I/O pin
on/off
output driver
pull protection
down diode
VSS VSS
Read/write

MS31477V1

8.3.10 Output configuration

When the I/O port is programmed as output:
• The output buffer is enabled:
– Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1”
in the Output register leaves the port in Hi-Z (the P-MOS is never activated)
– Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in
the Output register activates the P-MOS
• The Schmitt trigger input is activated
• The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register gets the I/O state
• A read access to the output data register gets the last written value

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RM0377 General-purpose I/Os (GPIO)

Figure 22 shows the output configuration of the I/O port bit.

Figure 22. Output configuration

Input data register

on
Read

Bit set/reset registers TTL Schmitt VDDIOx VDDIOx

trigger
on/off
Write protection
Input driver diode
Output data register pull
up
I/O pin
Output driver VDDIOx on/off

P-MOS pull protection

Output down diode
Read/write control VSS
N-MOS VSS
Push-pull or
VSS Open-drain
MS31478V1

8.3.11 Alternate function configuration

When the I/O port is programmed as alternate function:
• The output buffer can be configured in open-drain or push-pull mode
• The output buffer is driven by the signals coming from the peripheral (transmitter
enable and data)
• The Schmitt trigger input is activated
• The weak pull-up and pull-down resistors are activated or not depending on the value
in the GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register gets the I/O state
Figure 23 shows the alternate function configuration of the I/O port bit.

Figure 23. Alternate function configuration

To on-chip Alternate function input

peripheral
Input data register

on

Read
VDDIOxVDDIOx
TTL Schmitt on/off
Bit set/reset registers

trigger protection
Pull diode
Input driver up
Write
Output data register

I/O pin
Output driver VDD on/off

Pull protection
P-MOS down diode
Output
control VSS VSS
N-MOS
Read/write
VSS push-pull or
open-drain
From on-chip
peripheral Alternate function output

MSv34756V1

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General-purpose I/Os (GPIO) RM0377

8.3.12 Analog configuration

When the I/O port is programmed as analog configuration:
• The output buffer is disabled
• The Schmitt trigger input is deactivated, providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
• The weak pull-up and pull-down resistors are disabled by hardware
• Read access to the input data register gets the value “0”
For code example, refer to A.5.3: Analog GPIO configuration code example.
Figure 24 shows the high-impedance, analog-input configuration of the I/O port bits.

Figure 24. High impedance-analog configuration

Analog
To on-chip
peripheral
Input data register

Read off
0
VDDIOx
Bit set/reset registers

TTL Schmitt
trigger protection
Write diode
Output data register

Input driver
I/O pin

protection
diode

Read/write VSS

From on-chip Analog

peripheral MS31480V1

8.3.13 Using the HSE or LSE oscillator pins as GPIOs

When the HSE or LSE oscillator is switched OFF (default state after reset), the related
oscillator pins can be used as normal GPIOs.
When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the
RCC_CSR register) the oscillator takes control of its associated pins and the GPIO
configuration of these pins has no effect.
When the oscillator is configured in a user external clock mode, only the OSC_IN, CK_IN or
OSC32_IN pin is reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be
used as normal GPIO.

8.3.14 Using the GPIO pins in the RTC supply domain

The PC13/PC14/PC15/PA0/PA2 GPIO functionality is lost when the core supply domain is
powered off (when the device enters Standby mode). In this case, if their GPIO configuration
is not bypassed by the RTC configuration, these pins are set in an analog input mode.
For details about I/O control by the RTC, refer to Section 22.4: RTC functional description.

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RM0377 General-purpose I/Os (GPIO)

8.3.15 BOOT0/GPIO pin sharing

On category 1 devices, the BOOT0 pin is shared with a GPIO pin. The BOOT0 pin input
level can be read as an input value on the shared GPIO pin. This pin features specific input
voltage characteristics (refer to the corresponding datasheet for more details).

8.4 GPIO registers

For a summary of register bits, register address offsets and reset values, refer to Table 46.
The peripheral registers can be written in word, half word or byte mode.

8.4.1 GPIO port mode register (GPIOx_MODER)

(x =A to E and H)
Address offset:0x00
Reset value: 0xEBFF FCFF for port A
Reset value: 0xFFFF FFFF for the other ports

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MODE15[1:0] MODE14[1:0] MODE13[1:0] MODE12[1:0] MODE11[1:0] MODE10[1:0] MODE9[1:0] MODE8[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MODE7[1:0] MODE6[1:0] MODE5[1:0] MODE4[1:0] MODE3[1:0] MODE2[1:0] MODE1[1:0] MODE0[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MODE[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O mode.
00: Input mode
01: General purpose output mode
10: Alternate function mode
11: Analog mode (reset state)

8.4.2 GPIO port output type register (GPIOx_OTYPER)

(x = A to E and H)
Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15 OT14 OT13 OT12 OT11 OT10 OT9 OT8 OT7 OT6 OT5 OT4 OT3 OT2 OT1 OT0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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General-purpose I/Os (GPIO) RM0377

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OT[15:0]: Port x configuration I/O pin y (y = 15 to 0)
These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain

8.4.3 GPIO port output speed register (GPIOx_OSPEEDR)

(x = A to E and H)
Address offset: 0x08
Reset value: 0x0C00 0000 (for port A)
Reset value: 0x0000 0000 (for the other ports)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED15 OSPEED14 OSPEED13 OSPEED12 OSPEED11 OSPEED10 OSPEED9 OSPEED8
[1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED7 OSPEED6 OSPEED5 OSPEED4 OSPEED3 OSPEED2 OSPEED1 OSPEED0
[1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 OSPEED[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output speed.
00: Low speed
01: Medium speed
10: High speed
11: Very high speed
Note: Refer to the device datasheet for the frequency specifications and the power supply
and load conditions for each speed..

8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)

(x = A to E and H)
Address offset: 0x0C
Reset value: 0x2400 0000 (for port A)
Reset value: 0x0000 0000 (for the other ports)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPD15[1:0] PUPD14[1:0] PUPD13[1:0] PUPD12[1:0] PUPD11[1:0] PUPD10[1:0] PUPD9[1:0] PUPD8[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPD7[1:0] PUPD6[1:0] PUPD5[1:0] PUPD4[1:0] PUPD3[1:0] PUPD2[1:0] PUPD1[1:0] PUPD0[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

226/905 RM0377 Rev 10

RM0377 General-purpose I/Os (GPIO)

Bits 31:0 PUPD[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved

8.4.5 GPIO port input data register (GPIOx_IDR)

(x = A to E and H)
Address offset: 0x10
Reset value: 0x0000 XXXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ID[15:0]: Port x input data I/O pin y (y = 15 to 0)
These bits are read-only. They contain the input value of the corresponding I/O port.

8.4.6 GPIO port output data register (GPIOx_ODR)

(x = A to E and H)
Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OD[15:0]: Port output data I/O pin y (y = 15 to 0)
These bits can be read and written by software.
Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the
GPIOx_BSRR register (x = A..E and H).

RM0377 Rev 10 227/905

232
General-purpose I/Os (GPIO) RM0377

8.4.7 GPIO port bit set/reset register (GPIOx_BSRR)

(x = A to E and H)
Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0
w w w w w w w w w w w w w w w w

Bits 31:16 BR[15:0]: Port x reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Resets the corresponding ODx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BS[15:0]: Port x set I/O pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Sets the corresponding ODx bit

8.4.8 GPIO port configuration lock register (GPIOx_LCKR)

(x = A to E and H)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next MCU reset or peripheral reset.
Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

228/905 RM0377 Rev 10

RM0377 General-purpose I/Os (GPIO)

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU
reset or peripheral reset.
LOCK key write sequence:
WR LCKR[16] = 1 + LCKR[15:0]
WR LCKR[16] = 0 + LCKR[15:0]
WR LCKR[16] = 1 + LCKR[15:0]
RD LCKR
RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit
returns 1 until the next MCU reset or peripheral reset.
Bits 15:0 LCK[15:0]: Port x lock I/O pin y (y = 15 to 0)
These bits are read/write but can only be written when the LCKK bit is 0.
0: Port configuration not locked
1: Port configuration locked

8.4.9 GPIO alternate function low register (GPIOx_AFRL)

(x = A to E and H)
Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 AFSEL[7:0][3:0]: Alternate function selection for port x I/O pin y (y = 7 to 0)
These bits are written by software to configure alternate function I/Os.
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
Others: Reserved

RM0377 Rev 10 229/905

232
General-purpose I/Os (GPIO) RM0377

8.4.10 GPIO alternate function high register (GPIOx_AFRH)

(x = A to E and H)
Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0] AFSEL12[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11[3:0] AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 AFSEL[15:8][3:0]: Alternate function selection for port x I/O pin y (y = 15 to 8)
These bits are written by software to configure alternate function I/Os.
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
Others: Reserved

8.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to E and H)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
w w w w w w w w w w w w w w w w

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BR[15:0]: Port x reset IO pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Reset the corresponding ODx bit

230/905 RM0377 Rev 10

 0x24
0x20
0x18
0x14
0x10
0x08
0x08
0x04
0x00
0x00

0x1C
0x0C
8.4.12
RM0377

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

GPIOx_IDR

GPIOx_ODR

GPIOx_AFRL

GPIOx_AFRH
GPIOx_LCKR
GPIOx_BSRR
GPIOA_PUPDR
GPIOx_MODER
GPIOA_MODER

GPIOx_OTYPER

(where x = A..E,H)
(where x = A..E,H)
(where x = A..E,H)
(where x = A..E,H)
(where x = A..E,H)
(where x = A..E,H)
(where x = B..E,H)
(where x = A..E,H)

GPIOx_OSPEEDR
(where x = B..E, H)

GPIOA_OSPEEDR
Offset Register name

0
0
0
0
0
0
1
1
Res. BR15 Res. Res. Res. 31
PUPD15[1:0] OSPEED15[1:0] OSPEED15[1:0] MODE15[1:0] MODE15[1:0]

0
0
0
0
0
0
1
1
Res. BR14 Res. Res. Res. 30

]
0
0
0
1
0
0
1
1
Res. BR13 Res. Res. Res. 29
PUPD14[1:0] OSPEED14[1:0] OSPEED14[1:0] MODE14[1:0] MODE14[1:0]

0
0
0
0
0
0
1
0
Res. BR12 Res. Res. Res. 28

0
0
0
0
0
1
1
1
Res. BR11 Res. Res. Res. 27
PUPD13[1:0] OSPEED13[1:0] OSPEED13[1:0] MODE13[1:0] MODE13[1:0]
GPIO register map

0
0
0
1
0
1
1
Res. BR10 Res. Res. Res. 0
26

]
0
0
0
0
0
0
1
1
Res. BR9 Res. Res. Res. 25
PUPD12[1:0] OSPEED12[1:0] OSPEED12[1:0] MODE12[1:0] MODE12[1:0]

0
0
0
0
0
0
1
1

Res. BR8 Res. Res. Res. 24

0
0
0
0
0
0
1
1

Res. BR7 Res. Res. Res. 23

PUPD11[1:0] OSPEED11[1:0] OSPEED11[1:0] MODE11[1:0] MODE11[1:0]

0
0
0
0
0
0
1
1

Res. BR6 Res. Res. Res. 22

]
0
0
0
0
0
0
1
1

Res. BR5 Res. Res. Res. 21

PUPD10[1:0] OSPEED10[1:0] OSPEED10[1:0] MODE10[1:0] MODE10[1:0]

0
0
0
0
0
0
1
1

Res. BR4 Res. Res. Res. 20

0
0
0
0
0
0
1
1

Res. BR3 Res. Res. Res. 19

PUPD9[1:0] OSPEED9[1:0] OSPEED9[1:0] MODE9[1:0] MODE9[1:0]

0
0
0
0
0
0
1
1

Res. BR2 Res. Res. Res. 18

RM0377 Rev 10
0
0
0
0
0
0
1
1

Res. BR1 Res. Res. Res. 17

PUPD8[1:0] OSPEED8[1:0] OSPEED8[1:0] MODE8[1:0] MODE8[1:0]

0
0
0
0
0
0
1
1

0
LCKK BR0 Res. Res. Res. 16

0
0
0
0
0
0
1
1

0
0
0

LCK15 BS15 OD15 ID15 OT15 15

PUPD7[1:0] OSPEED7[1:0] OSPEED7[1:0] MODE7[1:0] MODE7[1:0]

0
0
0
0
0
0
1
1

0
0
0

LCK14 BS14 OD14 ID14 OT14 14

]
x

0
0
0
0
0
0
1
1

0
0
0

LCK13 BS13 OD13 ID13 OT13 13

PUPD6[1:0] OSPEED6[1:0] OSPEED6[1:0] MODE6[1:0] MODE6[1:0]

0
0
0
0
0
0
1
1

0
0
0

LCK12 BS12 OD12 ID12 OT12

AFSEL15[3:0 AFSEL14[3:0 AFSEL13[3:0 AFSEL12[3:0 AFSEL11[3:0

12

0
0
0
0
0
0
1
1

0
0
0

LCK11 BS11 OD11 ID11 OT11

Table 46. GPIO register map and reset values

PUPD5[1:0] OSPEED5[1:0] OSPEED5[1:0] MODE5[1:0] MODE5[1:0]

11

0
0
0
0
0
0
1
1

0
0
0

LCK10 BS10 OD10 ID10 OT10 10

The following table gives the GPIO register map and reset values.

0
0
0
0
0
0
1
0

0
0
0

LCK9 BS9 OD9 ID9 OT9 9

PUPD4[1:0] OSPEED4[1:0] OSPEED4[1:0] MODE4[1:0] MODE4[1:0]

0
0
0
0
0
0
1
0

0
0
0

LCK8 BS8 OD8 ID8 OT8 8

0
0
0
0
0
0
1
1

0
0
0

LCK7 BS7 OD7 ID7 OT7 7

PUPD3[1:0] OSPEED3[1:0] OSPEED3[1:0] MODE3[1:0] MODE3[1:0]

0
0
0
0
0
0
1
1

0
0
0

LCK6 BS6 OD6 ID6 OT6 6

0
0
0

0
0
0
0
0
0
1
1

LCK5 BS5 OD5 ID5 OT5 5

PUPD2[1:0] OSPEED2[1:0] OSPEED2[1:0] MODE2[1:0] MODE2[1:0]

0
0
0

0
0
0
0
0
0
1
1

LCK4 BS4 OD4 ID4 OT4 4

0
0
0

0
0
0
0
0
0
1
1

LCK3 BS3 OD3 ID3 OT3 3

PUPD1[1:0] OSPEED1[1:0] OSPEED1[1:0] MODE1[1:0] MODE1[1:0]

0
0
0

0
0
0
0
0
0
1
1

LCK2 BS2 OD2 ID2 OT2 2

0
0
0

0
0
0
0
0
0
1
1

LCK1 BS1 OD1 ID1 OT1 1

PUPD0[1:0] OSPEED0[1:0] OSPEED0[1:0] MODE0[1:0] MODE0[1:0]

0
0
0

0
0
0
0
0
0
1
1

LCK0 BS0 OD0 ID0 OT0

AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]

AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0]

0

231/905
General-purpose I/Os (GPIO)

232
General-purpose I/Os (GPIO) RM0377

Table 46. GPIO register map and reset values (continued)

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
GPIOx_BRR

BR15
BR14
BR13
BR12

BR10
BR11
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
0x28 (where x = A..E,H)
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 51 for the register boundary addresses.

232/905 RM0377 Rev 10

RM0377 System configuration controller (SYSCFG)

9 System configuration controller (SYSCFG)

9.1 Introduction
The devices feature a set of configuration registers. The main purposes of the system
configuration controller are the following:
• Remapping memories
• Remapping some trigger sources to timer input capture channels
• Managing external interrupts line multiplexing to the internal edge detector
• Enabling dedicated functions such as input capture multiplexing or oscillator pin
remapping
• I2C Fm+ mode management
• Firewall management
• Temperature sensor and Internal voltage reference management (including for
Comparator and ADC purposes).
The Cortex®-M0+ can wake up from WFE (Wait For Event) when a transition occurs on the
eventin input signal. To support semaphore management in multiprocessor environment,
the core can also output events on the signal output EVENTOUT, during SEV instruction
execution.
In STM32L0x1 devices, an event input can be generated by an external interrupt line or by
an RTC alarm interrupt. It is also possible to select which output pin is connected to the
EVENTOUT signal of the Cortex®-M0+. The EVENTOUT multiplexing is managed by the
GPIO alternate function capability (see Section 8.4.9: GPIO alternate function low register
(GPIOx_AFRL) (x = A to E and H) and Section 8.4.10: GPIO alternate function high register
(GPIOx_AFRH) (x = A to E and H)).
Note: EVENTOUT is not mapped on all GPIOs (for example PC13, PC14, PC15).

RM0377 Rev 10 233/905

240
System configuration controller (SYSCFG) RM0377

9.2 SYSCFG registers

The peripheral registers have to be accessed by words (32-bit).

9.2.1 SYSCFG memory remap register (SYSCFG_CFGR1)

This register is used for specific configurations related to memory remap:
Note: This register is not reset through the SYSCFGRST bit in the RCC_APB2RSTR register.
Address offset: 0x00
Reset value: 0x000x 000x (X is the memory mode selected by the boot configuration).
)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. BOOT_MODE Res. Res. Res. Res. UFB Res. MEM_MODE
r r rw rw rw

Bits 31:10 Reserved, must be kept at reset value

Bits 9:8 BOOT_MODE: Boot mode selected by the boot pins status bits
These bits are read-only. They indicate the boot mode selected by the boot configuration
(see Section 2.4: Boot configuration on page 56).
00: Main Flash memory boot mode
01: System Flash memory boot mode
10: Reserved
11: Embedded SRAM boot mode
Bits 7:4 Reserved, must be kept at reset value
Bit 3 UFB: User bank swapping
This bit is available only on category 5 devices and reserved on other categories.
It is set and cleared by software. It controls the Bank 1/2 mapping (see Table 10: NVM
organization for UFB = 0 (128 Kbyte category 5 devices) and Table 12: NVM organization
for UFB = 0 (64 Kbyte category 5 devices)).
0: Flash Program memory Bank 1 is mapped at 0x0800 0000 (and aliased at 0x0000 0000 if
MEM_MODE=00) and Data EEPROM Bank 1 at 0x0808 0000 (aliased at 0x0008 0000 if
MEM_MODE=00)
1: Flash Program memory Bank 2 is mapped at 0x0800 0000 (and aliased at 0x0000 0000 if
MEM_MODE=00) and Data EEPROM Bank 2 at 0x0808 0000 (and aliased at 0x0008 0000
if MEM_MODE=00)
Bit 2 Reserved, must be kept at reset value
Bits 1:0 MEM_MODE: Memory mapping selection bits
These bits are set and cleared by software. This bit controls the memory’s internal mapping
at address 0x0000 0000. After reset these bits take on the memory mapping selected by the
boot configuration (see Section 2.4: Boot configuration on page 56).
00: Main Flash memory mapped at 0x0000 0000
01: System Flash memory mapped at 0x0000 0000
10: reserved
11: SRAM mapped at 0x0000 0000.

234/905 RM0377 Rev 10

RM0377 System configuration controller (SYSCFG)

9.2.2 SYSCFG peripheral mode configuration register (SYSCFG_CFGR2)

Address offset: 0x04
Reset value: 0x0000 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2C3_ I2C_PB9 I2C_PB8 I2C_PB7 I2C_PB6
Res. I2C2_FMP I2C1_FMP Res. Res. Res. FWDIS
FMP _FMP _FMP _FMP _FMP
rw rw rw rw

Bits 31:15 Reserved, must be kept at reset value

Bit 14 I2C3 FMP: I2C3 Fm+ drive capability enable bit
This bit is set and cleared by software. When it is set, Fm+ mode is enabled on I2C3 pins
PC0, PC1, PA8 and PB4 selected through the IOPORT control registers AF selection bits.
Bit 13 I2C2 FMP: I2C2 Fm+ drive capability enable bit
This bit is set and cleared by software. When it is set, Fm+ mode is enabled on I2C2 pins
PB13 and PB14 selected through the IOPORT control registers AF selection bits.
Bit 12 I2C1 FMP: I2C1 Fm+ drive capability enable bit
This bit is set and cleared by software. When it is set, Fm+ mode is enabled on I2C1 pins
selected through the IOPORT control registers AF selection bits. This bit is bit is OR-ed with
I2C_PBx_FMP bits.
Bit 11 I2C PB9 FMP: Fm+ drive capability on PB9 enable bit
This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB9.
Bit 10 I2C PB8 FMP: Fm+ drive capability on PB8 enable bit
This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB8.
Bit 9 I2C PB7 FMP: Fm+ drive capability on PB7 enable bit
This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB7.
Bit 8 I2C PB6 FMP: Fm+ drive capability on PB6 enable bit
This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB6.
Bits 7:1 Reserved, must be kept at reset value
Bit 0 FWDIS: Firewall disable bit
This bit is set by default (after reset). It is cleared by software to protect the access to the
memory segments according to the Firewall configuration.Once cleared it cannot be set by
software. Only a system reset set the bit.
0: Firewall access enabled
1: Firewall access disabled
Note: This bit cannot be set by an APB reset. A system reset is required to set it.

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9.2.3 Reference control and status register (SYSCFG_CFGR3)

The SYSCFG_CFGR3 register is the reference control/status register. It contains all the
bits/flags related to VREFINT and temperature sensor.
Address offset: 0x20
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REF_ VREFINT
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LOCK _RDYF
rs r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ENBUF_ ENBUF_ ENBUF_
SEL_VREF EN_VR
Res. Res. Res. VREFINT_ Res. Res. SENSOR VREFINT Res. Res. Res. Res. Res.
_OUT EFINT
COMP2 _ADC _ ADC
rw rw rw rw rw rw

Bit 31 REF_LOCK: SYSCFG_CFGR3 lock bit

This bit is set by software and cleared by a hardware system reset. It locks the whole
content of the reference control/Status register, SYSCFG_CFGR3[31:0].
0: SYSCFG_CFGR3[31:0] bits are read/write
1: SYSCFG_CFGR3[31:0] bits are read-only
Bit 30 VREFINT_RDYF: VREFINT ready flag
This bit is read-only. It shows the state of the internal voltage reference, VREFINT. When
set, it indicates that VREFINT is available for BOR, PVD.
0: VREFINT OFF
1: VREFINT ready
Bits 29:13 Reserved, must be kept at reset value
Bit 12 ENBUF_VREFINT_COMP2: VREFINT reference for COMP2 scaler enable bit
This bit is set and cleared by software (only if REF_LOCK not set).
0: Disables the buffer used to generate VREFINT references for COMP2.
1: Enables the buffer used to generate VREFINT references for COMP2.
Bits 11:10 Reserved, must be kept at reset value
Bit 9 ENBUF_SENSOR_ADC: Temperature sensor reference for ADC enable bit
This bit is set and cleared by software (only if REF_LOCK not set). When this bit is set, the
VREFINT is automatically enabled.
0: Disables the buffer used to generate VREFINT reference for the temperature sensor.
1: Enables the buffer used to generate VREFINT reference for the temperature sensor.
Bit 8 ENBUF_VREFINT_ADC: VREFINT reference for ADC enable bit
This bit is set and cleared by software (only if REF_LOCK not set).
0: Disables the buffer used to generate VREFINT reference for the ADC.
1: Enables the buffer used to generate VREFINT reference for the ADC.
Bits 7:6 Reserved, must be kept at reset value

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Bits 5:4 SEL_VREF_OUT: VREFINT_ADC connection bit

These bits are set and cleared by software (only if REF_LOCK not set). These bits select
which pad is connected to VREFINT_ADC when ENBUF_VREFINT_ADC is set.
00: no pad connected
01: PB0 connected
10: PB1 connected
11: PB0 and PB1 connected
Bits 3:1 Reserved, must be kept at reset value
Bit 0 EN_VREFINT: VREFINT enable and scaler control for COMP2 enable bit
This bit is set and cleared by software (only if REF_LOCK not set). It switches on VREFINT
internal reference voltage and enables the scaler for COMP2.
0: VREFINT voltage disabled in low-power mode (if ULP=1) and scaler for COMP2 disabled
1: VREFINT voltage enabled in low-power mode and scaler for COMP2 enabled
Note: It is forbidden to configure both EN_VREFINT = 1 and ULP = 1 if the device is in Stop
mode or in Sleep/Low-power sleep mode (refer to Section 6.4.1: PWR power control
register (PWR_CR) for a description of the ULP bit). If the device is not in low-power
mode, VREFINT is always enabled whatever the state of EN_VREFINT and ULP.
EN_VREFINT controls only COMP2 scaler. The Scaler must be enabled to provide
VREFINT voltage or its fraction to COMP2 (scaler performs VREFINT buffering and
scaling).

9.2.4 SYSCFG external interrupt configuration register 1

(SYSCFG_EXTICR1)
Address offset: 0x08
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3)
These bits are written by software to select the source input for the EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PH[x] (only PH[1:0] and PH[10:9])
Other configurations are reserved

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9.2.5 SYSCFG external interrupt configuration register 2

(SYSCFG_EXTICR2)
Address offset: 0x0C
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7)
These bits are written by software to select the source input for the EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
Other configurations are reserved

9.2.6 SYSCFG external interrupt configuration register 3

(SYSCFG_EXTICR3)
Address offset: 0x10
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 8 to 11)
These bits are written by software to select the source input for the EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PH[x] (only PH[1:0] and PH[10:9])
Other configurations are reserved.

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9.2.7 SYSCFG external interrupt configuration register 4

(SYSCFG_EXTICR4)
Address offset: 0x14
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved

Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15)
These bits are written by software to select the source input for the EXTIx external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
Other configurations are reserved.

9.2.8 SYSCFG register map

The following table gives the SYSCFG register map and the reset values.

Table 47. SYSCFG register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
BOOT_MODE

MEM_MODE
UFB.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

Res.

SYSCFG_CFGR1
0x00

Reset value x x x x x
I2C_PB9_FMP
I2C_PB8_FMP
I2C_PB7_FMP
I2C_PB6_FMP
I2C3_FMP
I2C2_FMP
I2C1_FMP

FWDISEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.

0x04 SYSCFG_CFGR2

Reset value 0 0 0 0 0 0 0 1
SYSCFG_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]

0x08 EXTICR1
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SYSCFG_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]

0x0C EXTICR2
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 47. SYSCFG register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
SYSCFG_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]
0x10 EXTICR3
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SYSCFG_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]
0x14 EXTICR4
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x18 COMP1_CTRL
Refer to Section 14: Comparator (COMP)
0x1C COMP2_CTRL

ENBUF_VREFINT_COMP2

ENBUF_VREFINT_ADC
ENBUF_SENSOR_ADC

SEL_VREF_OUT
VREFINT_RDYF

EN_VREFINT
REF_LOCK

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.
Res.

Res.
Res.
Res.
SYSCFG_CFGR3
0x20

Reset value 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 51 for the register boundary addresses.

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RM0377 Direct memory access controller (DMA)

10 Direct memory access controller (DMA)

10.1 Introduction
The direct memory access (DMA) controller is a bus master and system peripheral.
The DMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories, upon the control of an off-loaded CPU.
The DMA controller features a single AHB master architecture.
There is one instance of DMA with up to 7 channels, except for the category 1 devices that
only feature 5 channels.
Each channel is dedicated to managing memory access requests from one or more
peripherals. The DMA includes an arbiter for handling the priority between DMA requests.

10.2 DMA main features

• Single AHB master
• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-
peripheral data transfers
• Access, as source and destination, to on-chip memory-mapped devices such as Flash
memory, SRAM, and AHB and APB peripherals
• All DMA channels independently configurable:
– Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
– Priority between the requests is programmable by software (4 levels per channel:
very high, high, medium, low) and by hardware in case of equality (such as
request to channel 1 has priority over request to channel 2).
– Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
– Support of transfers from/to peripherals to/from memory with circular buffer
management
– Programmable number of data to be transferred: 0 to 216 - 1
• Generation of an interrupt request per channel. Each interrupt request is caused from
any of the three DMA events: transfer complete, half transfer, or transfer error.

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10.3 DMA implementation

10.3.1 DMA
DMA is implemented with the hardware configuration parameters shown in the table below.

Table 48. DMA implementation

Feature DMA

Number of channels up to 7(1)

1. 7 channels except for category 1 devices that feature 5 channels.

10.3.2 DMA request mapping

DMA controller
The hardware requests from the peripherals (TIM2/6, ADC, SPI1/2, I2C1/2, AES (available
only on category 1, 2 and 5 devices, with AES), USART1/2 and LPUART1) are mapped to
the DMA channels through the DMA_CSELR channel selection registers (see Figure 25).
The peripheral DMA requests can be independently activated/de-activated by programming
the DMA control bit in the registers of the corresponding peripheral.
Caution: A same peripheral request can be assigned to two different channels only if the application
ensures that these channels are not requested to be served at the same time. In other
words, if two different channels receive a same asserted peripheral request at the same
time, an unpredictable DMA hardware behavior occurs.
Table 49 lists the DMA requests for each channel.

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Figure 25. DMA request mapping

Peripheral request signals DMA Fixed hardware priority

High priority
ADC, TIM2_CH3, AES_IN
SW trigger 1
(MEM2MEM bit) C1S
4
ADC, SPI1_RX, USART1_TX,
LPUART1_TX, I2C1_TX, I2C3_TX,
TIM2_UP, TIM6_UP,
AES_OUT, TIM3_CH3,
USART4_RX, USART5_RX,
USART2_TX(1) C2S
SW trigger 2
(MEM2MEM bit) 4

SPI1_TX, USART1_RX,I2C3_RX
LPUART1_RX, I2C1_RX,
TIM2_CH2, TIM3_CH4,TIM3_UP,
USART4_TX,USART5_TX,
USART2_RX(1) , AES_OUT C3S
SW trigger 3
(MEM2MEM bit) 4 Internal DMA
SPI2_RX, USART1_TX,
request
USART2_TX, I2C2_TX, I2C3_TX,
(1)
ADC , SPI_RX(1), LPUART1_TX(1),
I2C1_TX(1), TIM2_CH4,TIM7_UP C4S
SW trigger 4
(MEM2MEM bit) 4
SPI2_TX, USART1_RX,
USART2_RX, I2C2_RX, DMA_CSELR
TIM2_CH1, TIM3_CH1, I2C3_RX, ,
SPI_TX(1), LPUART1_RX(1),
I2C1_RX(1), AES_IN
SW trigger 5 C5S
(MEM2MEM bit)
4
SPI2_RX, USART2_RX,
LPUART1_RX, I2C1_TX,
TIM3_TRIG, USART4_RX,
USART5_RX C6S
SW trigger 6
(MEM2MEM bit) 4
SPI2_TX, USART2_TX,
USART4_TX, USART5_TX,
LPUART1_TX, I2C1_RX,
TIM2_CH2, TIM2_CH4
C7S Low priority
SW trigger 7
(MEM2MEM bit) 4

MSv34755V5

1. Only available on category 1 devices.

Table 49. DMA requests for each channel

Channel 6 Channel 7
CxS[3:0] Peripheral Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 (1) (1)

0000 ADC ADC ADC - ADC(2) - - -

SPI1_RX
0001 SPI1 - SPI1_RX SPI1_TX (2) SPI1_TX(2) - -

0010 SPI2 - - - SPI2_RX SPI2_TX SPI2_RX SPI2_TX

USART1_ USART1_ USART1_ USART1_
0011 USART1 - - -
TX RX TX RX
USART2_ USART2_ USART2_ USART2_ USART2_R USART2_
0100 USART2 -
TX(2) RX(2) TX RX X TX

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Table 49. DMA requests for each channel (continued)

Channel 6 Channel 7
CxS[3:0] Peripheral Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 (1) (1)

LPUART1_ LPUART1_ LPUART1_ LPUART1_ LPUART1_ LPUART1_

0101 LPUART1 -
TX RX TX(2) RX(2) RX TX
0110 I2C1 - I2C1_TX I2C1_RX I2C1_TX(2) I2C1_RX(2) I2C1_TX I2C1_RX
0111 I2C2 - - - I2C2_TX I2C2_RX - -
TIM2_ TIM2_CH2
1000 TIM2 TIM2_UP TIM2_CH2 TIM2_CH4 TIM2_CH1 -
CH3 TIM2_CH4
1001 TIM6_UP - TIM6_UP - - - - -
TIM3_CH4 TIM3_
1010 TIM3 - TIM3_CH3 - TIM3_CH1 -
TIM3_UP TRIG
1011 AES(3) AES_IN AES_OUT AES_OUT - AES_IN - -
USART4_ USART4_ USART4_ USART4_
1100 USART4 - - -
RX TX RX TX
USART5_ USART5_ USART5_ USART5_
1101 USART5 - - -
RX TX RX TX
1110 I2C3 - I2C3_TX I2C3_RX I2C3_TX I2C3_RX - -
1111 TIM7_UP - - - TIM7_UP - - -
1. Not available on category 1 devices.
2. Available only on category 1 devices.
3. Available only on category 1, 2 and 5 with AES.

10.4 DMA functional description

10.4.1 DMA block diagram

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The DMA block diagram is shown in the figure below.

Figure 26. DMA block diagram

FLITF Flash
System
Cortex-
M0+

Bus matrix
SRAM
DMA Reset &
Ch.1
Clock control
Ch.2 DMA CRC
(RCC)
up to
Ch.7 Bridge

Arbiter APB

AHB Slave

DMA request ADC

SPI1/SPI2
USART1/2/4/5
LPUART1
I2C1/2/3
TIM2/3/6/7

MSv34758V2

The DMA controller performs direct memory transfer by sharing the AHB system bus with
other system masters. The bus matrix implements round-robin scheduling. DMA requests
may stop the CPU access to the system bus for a number of bus cycles, when CPU and
DMA target the same destination (memory or peripheral).
According to its configuration through the AHB slave interface, the DMA controller arbitrates
between the DMA channels and their associated received requests. The DMA controller
also schedules the DMA data transfers over the single AHB port master.
The DMA controller generates an interrupt per channel to the interrupt controller.

10.4.2 DMA transfers

The software configures the DMA controller at channel level, in order to perform a block
transfer, composed of a sequence of AHB bus transfers.
A DMA block transfer may be requested from a peripheral, or triggered by the software in
case of memory-to-memory transfer.

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After an event, the following steps of a single DMA transfer occur:

1. The peripheral sends a single DMA request signal to the DMA controller.
2. The DMA controller serves the request, depending on the priority of the channel
associated to this peripheral request.
3. As soon as the DMA controller grants the peripheral, an acknowledge is sent to the
peripheral by the DMA controller.
4. The peripheral releases its request as soon as it gets the acknowledge from the DMA
controller.
5. Once the request is de-asserted by the peripheral, the DMA controller releases the
acknowledge.
The peripheral may order a further single request and initiate another single DMA transfer.
The request/acknowledge protocol is used when a peripheral is either the source or the
destination of the transfer. For example, in case of memory-to-peripheral transfer, the
peripheral initiates the transfer by driving its single request signal to the DMA controller. The
DMA controller reads then a single data in the memory and writes this data to the peripheral.
For a given channel x, a DMA block transfer consists of a repeated sequence of:
• a single DMA transfer, encapsulating two AHB transfers of a single data, over the DMA
AHB bus master:
– a single data read (byte, half-word or word) from the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory
address register.
The start address used for the first single transfer is the base address of the
peripheral or memory, and is programmed in the DMA_CPARx or DMA_CMARx
register.
– a single data write (byte, half-word or word) to the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory
address register.
The start address used for the first transfer is the base address of the peripheral or
memory, and is programmed in the DMA_CPARx or DMA_CMARx register.
• post-decrementing of the programmed DMA_CNDTRx register
This register contains the remaining number of data items to transfer (number of AHB
‘read followed by write’ transfers).
This sequence is repeated until DMA_CNDTRx is null.
Note: The AHB master bus source/destination address must be aligned with the programmed size
of the transferred single data to the source/destination.

10.4.3 DMA arbitration

The DMA arbiter manages the priority between the different channels.
When an active channel x is granted by the arbiter (hardware requested or software
triggered), a single DMA transfer is issued (such as a AHB ‘read followed by write’ transfer
of a single data). Then, the arbiter considers again the set of active channels and selects the
one with the highest priority.

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The priorities are managed in two stages:

• software: priority of each channel is configured in the DMA_CCRx register, to one of
the four different levels:
– very high
– high
– medium
– low
• hardware: if two requests have the same software priority level, the channel with the
lowest index gets priority. For example, channel 2 gets priority over channel 4.
When a channel x is programmed for a block transfer in memory-to-memory mode,
re arbitration is considered between each single DMA transfer of this channel x. Whenever
there is another concurrent active requested channel, the DMA arbiter automatically
alternates and grants the other highest-priority requested channel, which may be of lower
priority than the memory-to-memory channel.

10.4.4 DMA channels

Each channel may handle a DMA transfer between a peripheral register located at a fixed
address, and a memory address. The amount of data items to transfer is programmable.
The register that contains the amount of data items to transfer is decremented after each
transfer.
A DMA channel is programmed at block transfer level.

Programmable data sizes

The transfer sizes of a single data (byte, half-word, or word) to the peripheral and memory
are programmable through, respectively, the PSIZE[1:0] and MSIZE[1:0] fields of the
DMA_CCRx register.

Pointer incrementation
The peripheral and memory pointers may be automatically incremented after each transfer,
depending on the PINC and MINC bits of the DMA_CCRx register.
If the incremented mode is enabled (PINC or MINC set to 1), the address of the next
transfer is the address of the previous one incremented by 1, 2 or 4, depending on the data
size defined in PSIZE[1:0] or MSIZE[1:0]. The first transfer address is the one programmed
in the DMA_CPARx or DMA_CMARx register. During transfers, these registers keep the
initially programmed value. The current transfer addresses (in the current internal
peripheral/memory address register) are not accessible by software.
If the channel x is configured in non-circular mode, no DMA request is served after the last
data transfer (once the number of single data to transfer reaches zero). The DMA channel
must be disabled in order to reload a new number of data items into the DMA_CNDTRx
register.
Note: If the channel x is disabled, the DMA registers are not reset. The DMA channel registers
(DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during
the channel configuration phase.
In circular mode, after the last data transfer, the DMA_CNDTRx register is automatically
reloaded with the initially programmed value. The current internal address registers are
reloaded with the base address values from the DMA_CPARx and DMA_CMARx registers.

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Channel configuration procedure

The following sequence is needed to configure a DMA channel x:
1. Set the peripheral register address in the DMA_CPARx register.
The data is moved from/to this address to/from the memory after the peripheral event,
or after the channel is enabled in memory-to-memory mode.
2. Set the memory address in the DMA_CMARx register.
The data is written to/read from the memory after the peripheral event or after the
channel is enabled in memory-to-memory mode.
3. Configure the total number of data to transfer in the DMA_CNDTRx register.
After each data transfer, this value is decremented.
4. Configure the parameters listed below in the DMA_CCRx register:
– the channel priority
– the data transfer direction
– the circular mode
– the peripheral and memory incremented mode
– the peripheral and memory data size
– the interrupt enable at half and/or full transfer and/or transfer error
5. Activate the channel by setting the EN bit in the DMA_CCRx register.
A channel, as soon as enabled, may serve any DMA request from the peripheral connected
to this channel, or may start a memory-to-memory block transfer.
Note: The two last steps of the channel configuration procedure may be merged into a single
access to the DMA_CCRx register, to configure and enable the channel.

Channel state and disabling a channel

A channel x in active state is an enabled channel (read DMA_CCRx.EN = 1). An active
channel x is a channel that must have been enabled by the software (DMA_CCRx.EN set
to 1) and afterwards with no occurred transfer error (DMA_ISR.TEIFx = 0). In case there is a
transfer error, the channel is automatically disabled by hardware (DMA_CCRx.EN = 0).
The three following use cases may happen:
• Suspend and resume a channel
This corresponds to the two following actions:
– An active channel is disabled by software (writing DMA_CCRx.EN = 0 whereas
DMA_CCRx.EN = 1).
– The software enables the channel again (DMA_CCRx.EN set to 1) without
reconfiguring the other channel registers (such as DMA_CNDTRx, DMA_CPARx
and DMA_CMARx).
This case is not supported by the DMA hardware, that does not guarantee that the
remaining data transfers are performed correctly.
• Stop and abort a channel
If the application does not need any more the channel, this active channel can be
disabled by software. The channel is stopped and aborted but the DMA_CNDTRx

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register content may not correctly reflect the remaining data transfers versus the
aborted source and destination buffer/register.
• Abort and restart a channel
This corresponds to the software sequence: disable an active channel, then
reconfigure the channel and enable it again.
This is supported by the hardware if the following conditions are met:
– The application guarantees that, when the software is disabling the channel, a
DMA data transfer is not occurring at the same time over its master port. For
example, the application can first disable the peripheral in DMA mode, in order to
ensure that there is no pending hardware DMA request from this peripheral.
– The software must operate separated write accesses to the same DMA_CCRx
register: First disable the channel. Second reconfigure the channel for a next block
transfer including the DMA_CCRx if a configuration change is needed. There are
read-only DMA_CCRx register fields when DMA_CCRx.EN=1. Finally enable
again the channel.
When a channel transfer error occurs, the EN bit of the DMA_CCRx register is cleared by
hardware. This EN bit can not be set again by software to re-activate the channel x, until the
TEIFx bit of the DMA_ISR register is set.

Circular mode (in memory-to-peripheral/peripheral-to-memory transfers)

The circular mode is available to handle circular buffers and continuous data flows (such as
ADC scan mode). This feature is enabled using the CIRC bit in the DMA_CCRx register.
Note: The circular mode must not be used in memory-to-memory mode. Before enabling a
channel in circular mode (CIRC = 1), the software must clear the MEM2MEM bit of the
DMA_CCRx register. When the circular mode is activated, the amount of data to transfer is
automatically reloaded with the initial value programmed during the channel configuration
phase, and the DMA requests continue to be served.
In order to stop a circular transfer, the software needs to stop the peripheral from generating
DMA requests (such as quit the ADC scan mode), before disabling the DMA channel.
The software must explicitly program the DMA_CNDTRx value before starting/enabling a
transfer, and after having stopped a circular transfer.

Memory-to-memory mode
The DMA channels may operate without being triggered by a request from a peripheral. This
mode is called memory-to-memory mode, and is initiated by software.
If the MEM2MEM bit in the DMA_CCRx register is set, the channel, if enabled, initiates
transfers. The transfer stops once the DMA_CNDTRx register reaches zero.
Note: The memory-to-memory mode must not be used in circular mode. Before enabling a
channel in memory-to-memory mode (MEM2MEM = 1), the software must clear the CIRC
bit of the DMA_CCRx register.

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Peripheral-to-peripheral mode
Any DMA channel can operate in peripheral-to-peripheral mode:
• when the hardware request from a peripheral is selected to trigger the DMA channel
This peripheral is the DMA initiator and paces the data transfer from/to this peripheral
to/from a register belonging to another memory-mapped peripheral (this one being not
configured in DMA mode).
• when no peripheral request is selected and connected to the DMA channel
The software configures a register-to-register transfer by setting the MEM2MEM bit of
the DMA_CCRx register.

Programming transfer direction, assigning source/destination

The value of the DIR bit of the DMA_CCRx register sets the direction of the transfer, and
consequently, it identifies the source and the destination, regardless the source/destination
type (peripheral or memory):
• DIR = 1 defines typically a memory-to-peripheral transfer. More generally, if DIR = 1:
– The source attributes are defined by the DMA_MARx register, the MSIZE[1:0]
field and MINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘memory’ register, field and bit are used to
define the source peripheral in peripheral-to-peripheral mode.
– The destination attributes are defined by the DMA_PARx register, the PSIZE[1:0]
field and PINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘peripheral’ register, field and bit are used
to define the destination memory in memory-to-memory mode.
• DIR = 0 defines typically a peripheral-to-memory transfer. More generally, if DIR = 0:
– The source attributes are defined by the DMA_PARx register, the PSIZE[1:0] field
and PINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘peripheral’ register, field and bit are used
to define the source memory in memory-to-memory mode
– The destination attributes are defined by the DMA_MARx register, the
MSIZE[1:0] field and MINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘memory’ register, field and bit are used to
define the destination peripheral in peripheral-to-peripheral mode.

10.4.5 DMA data width, alignment and endianness

When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data
alignments as described in the table below.

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Table 50. Programmable data width and endian behavior (when PINC = MINC = 1)
Source Destinat
port ion port Destination
Number Source content:
width width content:
of data address / data
(MSIZE (PSIZE address / data
items to (DMA_CMARx if DMA transfers
if if (DMA_CPARx if
transfer DIR = 1, else
DIR = 1, DIR = 1, DIR = 1, else
(NDT) DMA_CPARx)
else else DMA_CMARx)
PSIZE) MSIZE)

@0x0 / B0 1: read B0[7:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0

@0x1 / B1 2: read B1[7:0] @0x1 then write B1[7:0] @0x1 @0x1 / B1
8 8 4
@0x2 / B2 3: read B2[7:0] @0x2 then write B2[7:0] @0x2 @0x2 / B2
@0x3 / B3 4: read B3[7:0] @0x3 then write B3[7:0] @0x3 @0x3 / B3

@0x0 / B0 1: read B0[7:0] @0x0 then write 00B0[15:0] @0x0 @0x0 / 00B0
@0x1 / B1 2: read B1[7:0] @0x1 then write 00B1[15:0] @0x2 @0x2 / 00B1
8 16 4
@0x2 / B2 3: read B2[7:0] @0x2 then write 00B2[15:0] @0x4 @0x4 / 00B2
@0x3 / B3 4: read B3[7:0] @0x3 then write 00B3[15:0] @0x6 @0x6 / 00B3

@0x0 / B0 1: read B0[7:0] @0x0 then write 000000B0[31:0] @0x0 @0x0 / 000000B0
@0x1 / B1 2: read B1[7:0] @0x1 then write 000000B1[31:0] @0x4 @0x4 / 000000B1
8 32 4
@0x2 / B2 3: read B2[7:0] @0x2 then write 000000B2[31:0] @0x8 @0x8 / 000000B2
@0x3 / B3 4: read B3[7:0] @0x3 then write 000000B3[31:0] @0xC @0xC / 000000B3

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write B2[7:0] @0x1 @0x1 / B2
16 8 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write B4[7:0] @0x2 @0x2 / B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write B6[7:0] @0x3 @0x3 / B6

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write B1B0[15:0] @0x0 @0x0 / B1B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write B3B2[15:0] @0x2 @0x2 / B3B2
16 16 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write B5B4[15:0] @0x4 @0x4 / B5B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write B7B6[15:0] @0x6 @0x6 / B7B6

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write 0000B1B0[31:0] @0x0 @0x0 / 0000B1B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write 0000B3B2[31:0] @0x4 @0x4 / 0000B3B2
16 32 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write 0000B5B4[31:0] @0x8 @0x8 / 0000B5B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write 0000B7B6[31:0] @0xC @0xC / 0000B7B6

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B4[7:0] @0x1 @0x1 / B4
32 8 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write B8[7:0] @0x2 @0x2 / B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BC[7:0] @0x3 @0x3 / BC

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B1B0[15:0] @0x0 @0x0 / B1B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B5B4[15:0] @0x2 @0x2 / B5B4
32 16 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write B9B8[15:0] @0x4 @0x4 / B9B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BDBC[15:0] @0x6 @0x6 / BDBC

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B3B2B1B0[31:0] @0x0 @0x0 / B3B2B1B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B7B6B5B4[31:0] @0x4 @0x4 / B7B6B5B4
32 32 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write BBBAB9B8[31:0] @0x8 @0x8 / BBBAB9B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BFBEBDBC[31:0] @0xC @0xC / BFBEBDBC

Addressing AHB peripherals not supporting byte/half-word write transfers

When the DMA controller initiates an AHB byte or half-word write transfer, the data are
duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]).
When the AHB slave peripheral does not support byte or half-word write transfers and does
not generate any error, the DMA controller writes the 32 HWDATA bits as shown in the two
examples below:
• To write the half-word 0xABCD, the DMA controller sets the HWDATA bus to
0xABCDABCD with a half-word data size (HSIZE = HalfWord in AHB master bus).
• To write the byte 0xAB, the DMA controller sets the HWDATA bus to 0xABABABAB
with a byte data size (HSIZE = Byte in the AHB master bus).

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Assuming the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take into
account the HSIZE data, any AHB byte or half-word transfer is changed into a 32-bit APB
transfer as described below:
• An AHB byte write transfer of 0xB0 to one of the 0x0, 0x1, 0x2 or 0x3 addresses, is
converted to an APB word write transfer of 0xB0B0B0B0 to the 0x0 address.
• An AHB half-word write transfer of 0xB1B0 to the 0x0 or 0x2 addresses, is converted to
an APB word write transfer of 0xB1B0B1B0 to the 0x0 address.

10.4.6 DMA error management

A DMA transfer error is generated when reading from or writing to a reserved address
space. When a DMA transfer error occurs during a DMA read or write access, the faulty
channel x is automatically disabled through a hardware clear of its EN bit in the
corresponding DMA_CCRx register.
The TEIFx bit of the DMA_ISR register is set. An interrupt is then generated if the TEIE bit of
the DMA_CCRx register is set.
The EN bit of the DMA_CCRx register can not be set again by software (channel x re-
activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of
the DMA_IFCR register).
When the software is notified with a transfer error over a channel which involves a
peripheral, the software has first to stop this peripheral in DMA mode, in order to disable any
pending or future DMA request. Then software may normally reconfigure both DMA and the
peripheral in DMA mode for a new transfer.

10.5 DMA interrupts

An interrupt can be generated on a half transfer, transfer complete or transfer error for each
DMA channel x. Separate interrupt enable bits are available for flexibility.

Table 51. DMA interrupt requests

Interrupt
Interrupt request Interrupt event Event flag
enable bit

Half transfer on channel x HTIFx HTIEx

Transfer complete on channel x TCIFx TCIEx
Channel x interrupt
Transfer error on channel x TEIFx TEIEx
Half transfer or transfer complete or transfer error on channel x GIFx -

10.6 DMA registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The DMA registers have to be accessed by words (32-bit).

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10.6.1 DMA interrupt status register (DMA_ISR)

Address offset: 0x00
Reset value: 0x0000 0000
The content of this register is linked to the DMA channels availability. See Section 10.3:
DMA implementation for more details.
Every status bit is cleared by hardware when the software sets the corresponding clear bit
or the corresponding global clear bit CGIFx, in the DMA_IFCR register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5
r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1
r r r r r r r r r r r r r r r r

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 TEIF7: transfer error (TE) flag for channel 7
0: no TE event
1: a TE event occurred
Bit 26 HTIF7: half transfer (HT) flag for channel 7
0: no HT event
1: a HT event occurred
Bit 25 TCIF7: transfer complete (TC) flag for channel 7
0: no TC event
1: a TC event occurred
Bit 24 GIF7: global interrupt flag for channel 7
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 23 TEIF6: transfer error (TE) flag for channel 6
0: no TE event
1: a TE event occurred
Bit 22 HTIF6: half transfer (HT) flag for channel 6
0: no HT event
1: a HT event occurred
Bit 21 TCIF6: transfer complete (TC) flag for channel 6
0: no TC event
1: a TC event occurred
Bit 20 GIF6: global interrupt flag for channel 6
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 19 TEIF5: transfer error (TE) flag for channel 5
0: no TE event
1: a TE event occurred

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Bit 18 HTIF5: half transfer (HT) flag for channel 5

0: no HT event
1: a HT event occurred
Bit 17 TCIF5: transfer complete (TC) flag for channel 5
0: no TC event
1: a TC event occurred
Bit 16 GIF5: global interrupt flag for channel 5
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 15 TEIF4: transfer error (TE) flag for channel 4
0: no TE event
1: a TE event occurred
Bit 14 HTIF4: half transfer (HT) flag for channel 4
0: no HT event
1: a HT event occurred
Bit 13 TCIF4: transfer complete (TC) flag for channel 4
0: no TC event
1: a TC event occurred
Bit 12 GIF4: global interrupt flag for channel 4
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 11 TEIF3: transfer error (TE) flag for channel 3
0: no TE event
1: a TE event occurred
Bit 10 HTIF3: half transfer (HT) flag for channel 3
0: no HT event
1: a HT event occurred
Bit 9 TCIF3: transfer complete (TC) flag for channel 3
0: no TC event
1: a TC event occurred
Bit 8 GIF3: global interrupt flag for channel 3
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 7 TEIF2: transfer error (TE) flag for channel 2
0: no TE event
1: a TE event occurred
Bit 6 HTIF2: half transfer (HT) flag for channel 2
0: no HT event
1: a HT event occurred
Bit 5 TCIF2: transfer complete (TC) flag for channel 2
0: no TC event
1: a TC event occurred
Bit 4 GIF2: global interrupt flag for channel 2
0: no TE, HT or TC event
1: a TE, HT or TC event occurred

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Bit 3 TEIF1: transfer error (TE) flag for channel 1

0: no TE event
1: a TE event occurred
Bit 2 HTIF1: half transfer (HT) flag for channel 1
0: no HT event
1: a HT event occurred
Bit 1 TCIF1: transfer complete (TC) flag for channel 1
0: no TC event
1: a TC event occurred
Bit 0 GIF1: global interrupt flag for channel 1
0: no TE, HT or TC event
1: a TE, HT or TC event occurred

10.6.2 DMA interrupt flag clear register (DMA_IFCR)

Address offset: 0x04
Reset value: 0x0000 0000
The content of this register is linked to the DMA channels availability. See Section 10.3:
DMA implementation for more details.
Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register, causes the
DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx,
HTIFx, TCIFx, in the DMA_ISR register.
Setting any individual clear bit among CTEIFx, CHTIFx, CTCIFx in this DMA_IFCR register,
causes the DMA hardware to clear the corresponding individual flag and the global flag
GIFx in the DMA_ISR register, provided that none of the two other individual flags is set.
Writing 0 into any flag clear bit has no effect.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHTIF7

CTCIF7

CHTIF6

CTCIF6

CHTIF5

CTCIF5
CTEIF7

CTEIF6

CTEIF5
CGIF7

CGIF6

CGIF5
Res. Res. Res. Res.

w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHTIF4

CTCIF4

CHTIF3

CTCIF3

CHTIF2

CTCIF2

CHTIF1

CTCIF1
CTEIF4

CTEIF3

CTEIF2

CTEIF1
CGIF4

CGIF3

CGIF2

CGIF1

w w w w w w w w w w w w w w w w

Bits 31:28 Reserved, must be kept at reset value.

Bit 27 CTEIF7: transfer error flag clear for channel 7
Bit 26 CHTIF7: half transfer flag clear for channel 7
Bit 25 CTCIF7: transfer complete flag clear for channel 7
Bit 24 CGIF7: global interrupt flag clear for channel 7
Bit 23 CTEIF6: transfer error flag clear for channel 6
Bit 22 CHTIF6: half transfer flag clear for channel 6

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Bit 21 CTCIF6: transfer complete flag clear for channel 6

Bit 20 CGIF6: global interrupt flag clear for channel 6
Bit 19 CTEIF5: transfer error flag clear for channel 5
Bit 18 CHTIF5: half transfer flag clear for channel 5
Bit 17 CTCIF5: transfer complete flag clear for channel 5
Bit 16 CGIF5: global interrupt flag clear for channel 5
Bit 15 CTEIF4: transfer error flag clear for channel 4
Bit 14 CHTIF4: half transfer flag clear for channel 4
Bit 13 CTCIF4: transfer complete flag clear for channel 4
Bit 12 CGIF4: global interrupt flag clear for channel 4
Bit 11 CTEIF3: transfer error flag clear for channel 3
Bit 10 CHTIF3: half transfer flag clear for channel 3
Bit 9 CTCIF3: transfer complete flag clear for channel 3
Bit 8 CGIF3: global interrupt flag clear for channel 3
Bit 7 CTEIF2: transfer error flag clear for channel 2
Bit 6 CHTIF2: half transfer flag clear for channel 2
Bit 5 CTCIF2: transfer complete flag clear for channel 2
Bit 4 CGIF2: global interrupt flag clear for channel 2
Bit 3 CTEIF1: transfer error flag clear for channel 1
Bit 2 CHTIF1: half transfer flag clear for channel 1
Bit 1 CTCIF1: transfer complete flag clear for channel 1
Bit 0 CGIF1: global interrupt flag clear for channel 1

10.6.3 DMA channel x configuration register (DMA_CCRx)

Address offset: 0x08 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
The address offsets of these registers are linked to the DMA channels availability. See
Section 10.3: DMA implementation for more details.
The register fields/bits MEM2MEM, PL[1:0], MSIZE[1:0], PSIZE[1:0], MINC, PINC, and DIR
are read-only when EN = 1.
The states of MEM2MEM and CIRC bits must not be both high at the same time.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2
Res. PL[1:0] MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN
MEM
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:15 Reserved, must be kept at reset value.

Bit 14 MEM2MEM: memory-to-memory mode
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 13:12 PL[1:0]: priority level
00: low
01: medium
10: high
11: very high
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 11:10 MSIZE[1:0]: memory size
Defines the data size of each DMA transfer to the identified memory.
In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: reserved
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 9:8 PSIZE[1:0]: peripheral size
Defines the data size of each DMA transfer to the identified peripheral.
In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and
the peripheral source if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: reserved
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

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Bit 7 MINC: memory increment mode

Defines the increment mode for each DMA transfer to the identified memory.
In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 6 PINC: peripheral increment mode
Defines the increment mode for each DMA transfer to the identified peripheral.
n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and
the peripheral source if DIR = 0.
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 5 CIRC: circular mode
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 4 DIR: data transfer direction
This bit must be set only in memory-to-peripheral and peripheral-to-memory modes.
0: read from peripheral
– Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register.
This is still valid in a memory-to-memory mode.
– Destination attributes are defined by MSIZE and MINC, plus the DMA_CMARx
register. This is still valid in a peripheral-to-peripheral mode.
1: read from memory
– Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx
register. This is still valid in a memory-to-memory mode.
– Source attributes are defined by MSIZE and MINC, plus the DMA_CMARx register.
This is still valid in a peripheral-to-peripheral mode.
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 3 TEIE: transfer error interrupt enable
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).

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Bit 2 HTIE: half transfer interrupt enable

0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 1 TCIE: transfer complete interrupt enable
0: disabled
1: enabled
Note: this bit is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 0 EN: channel enable
When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again
by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by
setting the CTEIFx bit of the DMA_IFCR register).
0: disabled
1: enabled
Note: this bit is set and cleared by software.

10.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx)

Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
The address offsets of these registers are linked to the DMA channels availability. See
Section 10.3: DMA implementation for more details.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 NDT[15:0]: number of data to transfer (0 to 216 - 1)
This field is updated by hardware when the channel is enabled:
– It is decremented after each single DMA ‘read followed by write’ transfer, indicating
the remaining amount of data items to transfer.
– It is kept at zero when the programmed amount of data to transfer is reached, if the
channel is not in circular mode (CIRC = 0 in the DMA_CCRx register).
– It is reloaded automatically by the previously programmed value, when the transfer
is complete, if the channel is in circular mode (CIRC = 1).
If this field is zero, no transfer can be served whatever the channel status (enabled or not).
Note: this field is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

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Direct memory access controller (DMA) RM0377

10.6.5 DMA channel x peripheral address register (DMA_CPARx)

Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
The address offsets of these registers are linked to the DMA channels availability. See
Section 10.3: DMA implementation for more details.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 PA[31:0]: peripheral address

It contains the base address of the peripheral data register from/to which the data will be
read/written.
When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this register identifies the memory destination address if
DIR = 1 and the memory source address if DIR = 0.
In peripheral-to-peripheral mode, this register identifies the peripheral destination address
DIR = 1 and the peripheral source address if DIR = 0.
Note: this register is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).

10.6.6 DMA channel x memory address register (DMA_CMARx)

Address offset: 0x14 + 0x14 * (x - 1), (x = 1 to 7)
Reset value: 0x0000 0000
The address offsets of these registers are linked to the DMA channels availability. See
Section 10.3: DMA implementation for more details.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

260/905 RM0377 Rev 10

RM0377 Direct memory access controller (DMA)

Bits 31:0 MA[31:0]: peripheral address

It contains the base address of the memory from/to which the data will be read/written.
When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this register identifies the memory source address if DIR = 1
and the memory destination address if DIR = 0.
In peripheral-to-peripheral mode, this register identifies the peripheral source address
DIR = 1 and the peripheral destination address if DIR = 0.
Note: this register is set and cleared by software.
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).

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Direct memory access controller (DMA) RM0377

10.6.7 DMA channel selection register (DMA_CSELR)

Address offset: 0xA8
Reset value: 0x0000 0000
This register is used to manage the mapping of DMA channels as detailed in Section 10.3.2:
DMA request mapping.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. C7S[3:0] C6S[3:0] C5S[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C4S[3:0] C3S[3:0] C2S[3:0] C1S[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 C7S[3:0]: DMA channel 7 selection
Details available in Section 10.3.2: DMA request mapping
Bits 23:20 C6S[3:0]: DMA channel 6 selection
Details available in Section 10.3.2: DMA request mapping
Bits 19:16 C5S[3:0]: DMA channel 5 selection
Details available in Section 10.3.2: DMA request mapping
Bits 15:12 C4S[3:0]: DMA channel 4 selection
Details available in Section 10.3.2: DMA request mapping
Bits 11:8 C3S[3:0]: DMA channel 3 selection
Details available in Section 10.3.2: DMA request mapping
Bits 7:4 C2S[3:0]: DMA channel 2 selection
Details available in Section 10.3.2: DMA request mapping
Bits 3:0 C1S[3:0]: DMA channel 1 selection
Details available in Section 10.3.2: DMA request mapping

10.6.8 DMA register map

The table below gives the DMA register map and reset values.

Table 52. DMA register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
HTIF7
TCIF7

HTIF6
TCIF6

HTIF5
TCIF5

HTIF4
TCIF4

HTIF3
TCIF3

HTIF2
TCIF2

HTIF1
TCIF1
TEIF7

TEIF6

TEIF5

TEIF4

TEIF3

TEIF2

TEIF1
GIF7

GIF6

GIF5

GIF4

GIF3

GIF2

GIF1
Res.
Res.
Res.
Res.

DMA_ISR
0x000
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CTCIF7

CTCIF6

CTCIF5

CTCIF4

CTCIF3

CTCIF2

CTCIF1
CHTIF7

CHTIF6

CHTIF5

CHTIF4

CHTIF3

CHTIF2

CHTIF1
CTEIF7

CTEIF6

CTEIF5

CTEIF4

CTEIF3

CTEIF2

CTEIF1
CGIF7

CGIF6

CGIF5

CGIF4

CGIF3

CGIF2

CGIF1
Res.
Res.
Res.
Res.

DMA_IFCR
0x004
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN

DMA_CCR1
0x008

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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RM0377 Direct memory access controller (DMA)

Table 52. DMA register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR1 NDTR[15:0]
0x00C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR1 PA[31:0]
0x010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR1 MA[31:0]
0x014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x018 Reserved Reserved.

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR2
0x01C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR2 NDTR[15:0]
0x020
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR2 PA[31:0]
0x024
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR2 MA[31:0]
0x028
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x02C Reserved Reserved.

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR3
0x030

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR3 NDTR[15:0]
0x034
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR3 PA[31:0]
0x038
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR3 MA[31:0]
0x03C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x040 Reserved Reserved.
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR4
0x044

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR4 NDTR[15:0]
0x048
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR4 PA[31:0]
0x04C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR4 MA[31:0]
0x050
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x054 Reserved Reserved.
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN

DMA_CCR5
0x058

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR5 NDTR[15:0]
0x05C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR5 PA[31:0]
0x060
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Direct memory access controller (DMA) RM0377

Table 52. DMA register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
DMA_CMAR5 MA[31:0]
0x064
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x068 Reserved Reserved.

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR6
0x06C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR6 NDTR[15:0]
0x070
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR6 PA[31:0]
0x074
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR6 MA[31:0]
0x078
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x07C Reserved Reserved.

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]

MINC

CIRC
PINC

HTIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
DMA_CCR7
0x080

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR7 NDTR[15:0]
0x084
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR7 PA[31:0]
0x088
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CMAR7 MA[31:0]
0x08C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x090 to
Reserved Reserved.
0x0A4
Res.
Res.
Res.
Res.

DMA_CSELR C7S[3:0] C6S[3:0] C5S[3:0] C4S[3:0] C3S[3:0] C2S[3:0] C1S[3:0]

0x0A8
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 for the register boundary addresses.

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RM0377 Nested vectored interrupt controller (NVIC)

11 Nested vectored interrupt controller (NVIC)

11.1 Main features

• Up to 39 maskable interrupt channels (see Table 53), These do not include the 16
interrupt lines of Cortex®-M0+.
• 4 programmable priority levels (2 bits of interrupt priority are used)
• Low-latency exception and interrupt handling
• Power management control
• Implementation of system control registers
The NVIC and the processor core interface are closely coupled, which enables low-latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to the STM32L0 Series Cortex®-M0+
programming manual (PM0223).
For code example, refer to A.7.1: NVIC initialization example.

11.2 SysTick calibration value register

The SysTick calibration value is fixed to 4000, which gives a reference time base of 1 ms
with the SysTick clock set to 4 MHz (max HCLK/8).

11.3 Interrupt and exception vectors

Table 53 is the vector table for STM32L0x1 devices.

Table 53. List of vectors(1)(2)

Type of
Position Priority Acronym Description Address
priority

- - - Reserved 0x0000_0000
-3 fixed Reset Reset 0x0000_0004
Non maskable interrupt. The RCC
-2 fixed NMI_Handler Clock Security System (CSS) is 0x0000_0008
linked to the NMI vector.
-1 fixed HardFault_Handler All class of fault 0x0000_000C
0x0000_0010 -
- - - Reserved
0x0000_002B
System service call via SWI
3 settable SVC_Handler 0x0000_002C
instruction
0x0000_0030 -
- - - Reserved
0x0000_0037
5 settable PendSV_Handler Pendable request for system service 0x0000_0038
6 settable SysTick_Handler System tick timer 0x0000_003C

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Nested vectored interrupt controller (NVIC) RM0377

Table 53. List of vectors(1)(2) (continued)

Type of
Position Priority Acronym Description Address
priority

0 7 settable WWDG Window Watchdog interrupt 0x0000_0040

PVD through EXTI Line detection
1 8 settable PVD 0x0000_0044
interrupt
RTC global interrupt through
2 9 settable RTC EXTI17/19/20 line and LSE CSS 0x0000_0048
interrupt through EXTI 19 line
Flash memory and data EEPROM
3 10 settable FLASH 0x0000_004C
global interrupt
4 11 settable RCC_CRS RCC global interrupt 0x0000_0050
5 12 settable EXTI[1:0] EXTI Line0 and 1 interrupts 0x0000_0054
6 13 settable EXTI[3:2] EXTI Line2 and 3 interrupts 0x0000_0058
7 14 settable EXTI[15:4] EXTI Line4 to 15 interrupts 0x0000_005C
8 15 settable - Reserved 0x0000_0060
9 16 settable DMA1_Channel1 DMA1 Channel1 global interrupt 0x0000_0064
10 17 settable DMA1_Channel[3:2] DMA1 Channel2 and 3 interrupts 0x0000_0068
11 18 settable DMA1_Channel[7:4] DMA1 Channel4 to 7 interrupts 0x0000_006C
ADC and comparator interrupts
12 19 settable ADC_COMP 0x0000_0070
through EXTI21 and 22
13 20 settable LPTIM1 LPTIMER1 interrupt through EXTI29 0x0000_0074
14 21 settable USART4/USART5 USART4/USART5 global interrupt 0x0000_0078
15 22 settable TIM2 TIMER2 global interrupt 0x0000_007C
16 23 settable TIM3 TIMER3 global interrupt 0x0000_0080
17 24 settable TIM6 TIMER6 global interrupt 0x0000_0084
18 25 settable TIM7 TIMER7 global interrupt 0x0000_0088
19 26 settable - reserved 0x0000_008C
20 27 settable TIM21 TIMER21 global interrupt 0x0000_0090
21 28 settable I2C3 I2C3 global interrupt 0x0000_0094
22 29 settable TIM22 TIMER22 global interrupt 0x0000_0098
23 30 settable I2C1 I2C1 global interrupt through EXTI23 0x0000_009C
24 31 settable I2C2 I2C2 global interrupt 0x0000_00A0
25 32 settable SPI1 SPI1 global interrupt 0x0000_00A4
26 33 settable SPI2 SPI2 global interrupt 0x0000_00A8
USART1 global interrupt through
27 34 settable USART1 0x0000_00AC
EXTI25

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RM0377 Nested vectored interrupt controller (NVIC)

Table 53. List of vectors(1)(2) (continued)

Type of
Position Priority Acronym Description Address
priority

USART2 global interrupt through

28 35 settable USART2 0x0000_00B0
EXTI26
LPUART1 global interrupt through
29 36 settable LPUART1 + AES 0x0000_00B4
EXTI28 + AES global interrupt
1. The grayed cells correspond to the Cortex®-M0+ interrupts.
2. Refer to Table 1: STM32L0x1 memory density, to Table 2: Overview of features per category and to the device datasheets
for the GPIO ports and peripherals available on your device. The memory area corresponding to unavailable GPIO ports or
peripherals are reserved.

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Extended interrupt and event controller (EXTI) RM0377

12 Extended interrupt and event controller (EXTI)

12.1 Introduction
The extended interrupts and events controller (EXTI) manages the external and internal
asynchronous events/interrupts and generates the event request to the CPU/interrupt
controller plus a wake-up request to the power controller.
The EXTI allows the management of up to 30 event lines which can wake up the device
from Stop mode.
Some of the lines are configurable: in this case the active edge can be chosen
independently, and a status flag indicates the source of the interrupt. The configurable lines
are used by the I/Os external interrupts, and by few peripherals. Some of the lines are
direct: they are used by some peripherals to generate a wakeup from Stop event or
interrupt. In this case the status flag is provided by the peripheral.
Each line can be masked independently for interrupt or event generation.
Te EXTI controller also allows to emulate, by programming to a dedicated register, events or
interrupts by software multiplexed with the corresponding hardware event line.

12.2 EXTI main features

The EXTI main features are the following:
• Generation of up to 30 event/interrupt requests (configurable and direct lines).
• Independent mask on each event/interrupt line
• Configurable rising or falling edge (configurable lines only)
• Dedicated status bit (configurable lines only)
• Emulation of event/interrupt requests (configurable lines only)

12.3 EXTI functional description

For the configurable interrupt lines, the interrupt line should be configured and enabled in
order to generate an interrupt. This is done by programming the two trigger registers with
the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the
corresponding bit in the interrupt mask register. When the selected edge occurs on the
interrupt line, an interrupt request is generated. The pending bit corresponding to the
interrupt line is also set. This request is cleared by writing a ‘1’ in the pending register.
For the direct interrupt lines: the interrupt is enabled by default in the interrupt mask register
and there is no corresponding pending bit in the pending register.
To generate an event, the event line should be configured and enabled. This is done by
programming the two trigger registers with the desired edge detection and by enabling the
event request by writing a ‘1’ to the corresponding bit in the event mask register. When the
selected edge occurs on the event line, an event pulse is generated. The pending bit
corresponding to the event line is not set.
For the configurable lines, an interrupt/event request can also be generated by software by
writing a ‘1’ in the software interrupt/event register.

268/905 RM0377 Rev 10

RM0377 Extended interrupt and event controller (EXTI)

Note: The interrupts or events associated to the direct lines are triggered only when the system is
in Stop mode. If the system is still running, no interrupt/event is generated by the EXTI.

12.3.1 EXTI block diagram

The block diagram is shown in Figure 27.

Figure 27. Extended interrupts and events controller (EXTI) block diagram

APB bus

PCLK Peripheral interface

Falling Rising Software

trigger trigger Event Interrupt Pending
interrupt
selection selection mask mask request
event
register register register register register
register

Interrupts
Configurable Edge detect
events circuit
Events
Rising
Stop mode
Direct edge
events detect.
Wakeup

MSv32798V1

12.3.2 Wakeup event management

The STM32L0x1 microcontrollers are able to handle external or internal events in order to
wake up the core (WFE). The wakeup event can be generated by either:
• enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex®-M0+ system control register (see STM32L0 Series
Cortex®-M0+ programming manual (PM0223)). When the MCU resumes from WFE,
the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in
the NVIC interrupt clear pending register) have to be cleared.
• or configuring an EXTI line in event mode. When the CPU resumes from WFE, it is not
necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel
pending bit as the pending bit corresponding to the event line is not set.

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12.3.3 Peripherals asynchronous interrupts

Some peripherals can generate events when the system is in Run mode or in Stop mode,
thus allowing to wake up the system from Stop mode.
To accomplish this, the peripheral generates both a synchronized (to the system clock, e.g.
APB clock) and an asynchronous version of the event. This asynchronous event is
connected to an EXTI direct line.
Note: Few peripherals with wakeup from Stop capability are connected to an EXTI configurable
line. In this case the EXTI configuration is required to allow the wakeup from Stop mode.

12.3.4 Hardware interrupt selection

To configure a line as an interrupt source, use the following procedure:
1. Configure the mask bits of the Interrupt lines (EXTI_IMR)
2. Configure the Trigger Selection bits of the Interrupt lines (EXTI_RTSR and
EXTI_FTSR)
3. Configure the enable and mask bits that control the NVIC IRQ channel mapped to the
extended interrupt controller (EXTI) so that an interrupt coming from any one of the
lines can be correctly acknowledged.
The direct lines do not require any EXTI configuration.
For code example, refer to A.7.2: Extended interrupt selection code example.

12.3.5 Hardware event selection

To configure a line as an event source, use the following procedure:
1. Configure the mask bits of the Event lines (EXTI_EMR)
2. Configure the Trigger Selection bits of the Event lines (EXTI_RTSR and EXTI_FTSR).

12.3.6 Software interrupt/event selection

Any of the configurable lines can be configured as software interrupt/event lines. The
procedure below must be followed to generate a software interrupt.
1. Configure the mask bits of the Interrupt/Event lines (EXTI_IMR, EXTI_EMR)
2. Set the required bit in the software interrupt register (EXTI_SWIER).

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12.4 EXTI interrupt/event line mapping

In the STM32L0x1, 30 interrupt/event lines are available.The GPIOs are connected to 16
configurable interrupt/event lines as shown in Figure 28.

Figure 28. Extended interrupt/event GPIO mapping

EXTI0[3:0] bits in SYSCFG_EXTICR1 register

PA0 EXTI0
PB0
PC0

EXTI1[3:0] bits in SYSCFG_EXTICR1 register

PA1
EXTI1
PB1
PC1

EXTI2[3:0] bits in SYSCFG_EXTICR1 register

PA2
PB2 EXTI2
PC2
PD2

EXTI15[3:0] bits in SYSCFG_EXTICR4 register

PA15
PB15 EXTI15
PC15

MSv34757V1

Note: Refer to the datasheet for the list of available I/O ports.

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The 30 lines are connected as shown in Table 54: EXTI lines connections:

Table 54. EXTI lines connections

EXTI line Line source Line type

0-15 GPIO configurable

16 PVD configurable
17 RTC alarm configurable
18 Reserved
RTC tamper or timestamp or
19 configurable
CSS_LSE
20 RTC wakeup timer configurable
21 COMP1 output configurable
22 COMP2 output configurable
23 I2C1 wakeup direct
24 I2C3 wakeup direct
25 USART 1 wakeup direct
26 USART2 wakeup direct
27 Reserved
28 LPUART1 wakeup direct
29 LPTIM1 wakeup direct

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12.5 EXTI registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).

12.5.1 EXTI interrupt mask register (EXTI_IMR)

Address offset: 0x00
Reset value: 0x3F84 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. IM29 IM28 Res. IM26 IM25 IM24 IM23 IM22 IM21 IM20 IM19 Res. IM17 IM16
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 IMx: Interrupt mask on line x (x = 29 to 28)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
Bit 27 Reserved, must be kept at reset value.
Bits 26:19 IMx: Interrupt mask on line x (x = 26 to 19)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
Bit 18 Reserved, must be kept at reset value.
Bits 17:0 IMx: Interrupt mask on line x (x = 17 to 0)
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked

12.5.2 EXTI event mask register (EXTI_EMR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. EM29 EM28 Res. EM26 EM25 EM24 EM23 EM22 EM21 EM20 EM19 Res. EM17 EM16
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EM15 EM14 EM13 EM12 EM11 EM10 EM9 EM8 EM7 EM6 EM5 EM4 EM3 EM2 EM1 EM0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 EMx: Event mask on line x (x = 29 to 28)
0: Event request from Line x is masked
1: Event request from Line x is not masked
Bit 27 Reserved, must be kept at reset value.
Bits 26:19 EMx: Event mask on line x (x = 26 to 19)
0: Event request from Line x is masked
1: Event request from Line x is not masked
Bit 18 Reserved, must be kept at reset value.
Bits 17:0 EMx: Event mask on line x (x = 17 to 0)
0: Event request from Line x is masked
1: Event request from Line x is not masked

12.5.3 EXTI rising edge trigger selection register (EXTI_RTSR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. RT22 RT21 RT20 RT19 Res. RT17 RT16
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 RT16 2 1 0

RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:19 RTx: Rising trigger event configuration bit of line x (x = 22 to 19)
0: Rising trigger disabled (for Event and Interrupt) for input line x
1: Rising trigger enabled (for Event and Interrupt) for input line x
Bit 18 Reserved, must be kept at reset value.
Bits 17:0 RTx: Rising trigger event configuration bit of line x (x = 17 to 0)
0: Rising trigger disabled (for Event and Interrupt) for input line x
1: Rising trigger enabled (for Event and Interrupt) for input line x

Note: The configurable wakeup lines are edge triggered, no glitch must be generated on these
lines.
If a rising edge on the configurable interrupt line occurs while writing to the EXTI_RTSR
register, the pending bit will not be set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.

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12.5.4 Falling edge trigger selection register (EXTI_FTSR)

Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. FT22 FT21 FT20 FT19 Res. FT17 FT16
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FT15 FT14 FT13 FT12 FT11 FT10 FT9 FT8 FT7 FT6 FT5 FT4 FT3 FT2 FT1 FT0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:19 FTx: Falling trigger event configuration bit of line x (x = 22 to 19)
0: Falling trigger disabled (for Event and Interrupt) for input line x
1: Falling trigger enabled (for Event and Interrupt) for input line x
Bit 18 Reserved, must be kept at reset value.
Bits 17:0 FTx: Falling trigger event configuration bit of line x (x = 17 to 0)
0: Falling trigger disabled (for Event and Interrupt) for input line x
1: Falling trigger enabled (for Event and Interrupt) for input line x

Note: The configurable wakeup lines are edge triggered, no glitch must be generated on these
lines.
If a falling edge on the configurable interrupt line occurs while writing to the EXTI_FTSR
register, the pending bit will not be set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.

12.5.5 EXTI software interrupt event register (EXTI_SWIER)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. SWI22 SWI21 SWI20 SWI19 Res. SWI17 SWI16
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SWI15 SWI14 SWI13 SWI12 SWI11 SWI10 SWI9 SWI8 SWI7 SWI6 SWI5 SWI4 SWI3 SWI2 SWI1 SWI0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:23 Reserved, must be kept at reset value.

Bits 22:19 SWIx: Software interrupt on line x (x = 22 to 19)
Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR. If the
interrupt is enabled on this line in EXTI_IMR and EXTI_EMR, an interrupt request is
generated.
This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to this bit).
Bit 18 Reserved, must be kept at reset value.
Bits 17:0 SWIx: Software interrupt on line x (x = 17 to 0)
Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR. If the
interrupt is enabled on this line in EXTI_IMR and EXTI_EMR, an interrupt request is
generated.
This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to this bit).

12.5.6 EXTI pending register (EXTI_PR)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. PIF22 PIF21 PIF20 PIF19 Res. PIF17 PIF16
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PIF15 PIF14 PIF13 PIF12 PIF11 PIF10 PIF9 PIF8 PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:19 PIFx: Pending interrupt flag on line x (x = 22 to 19)
0: No trigger request occurred
1: The selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared
by writing it to 1 or by changing the sensitivity of the edge detector.
Bit 18 Reserved, must be kept at reset value.
Bits 17:0 PIFx: Pending interrupt flag on line x (x = 17 to 0)
0: No trigger request occurred
1: The selected trigger request occurred
This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared
by writing it to 1 or by changing the sensitivity of the edge detector.

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12.5.7 EXTI register map

The following table gives the EXTI register map and the reset values.

Table 55. Extended interrupt/event controller register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
IM[29:28]
Res.
Res.

Res.

Res.
EXTI_IMR IM[26:19] IM[17:0]
0x00

Reset value 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EM[29:28]
Res.
Res.

Res.

Res.
EXTI_EMR EM[26:19] EM[17:0]
0x04

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

EXTI_RTSR RT[22:19] RT[17:0]

0x08
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

EXTI_FTSR FT[22:19] FT[17:0]

0x0C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SWI
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

EXTI_SWIER SWI[17:0]
0x10 [22:19]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PIF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

EXTI_PR PIF[17:0]
0x14 [22:19]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 51 for the register boundary addresses.

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13 Analog-to-digital converter (ADC)

13.1 Introduction
The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 18
multiplexed channels allowing it to measure signals from 16 external and 2 internal sources.
A/D conversion of the various channels can be performed in single, continuous, scan or
discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit
data register.
The analog watchdog feature allows the application to detect if the input voltage goes
outside the user-defined higher or lower thresholds.
An efficient low-power mode is implemented to allow very low consumption at low
frequency.
A built-in hardware oversampler allows analog performances to be improved while off-
loading the related computational burden from the CPU.

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13.2 ADC main features

• High performance
– 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
– ADC conversion time: 0.87 µs for 12-bit resolution (1.14 MHz), 0.81 µs conversion
time for 10-bit resolution, faster conversion times can be obtained by lowering
resolution.
– Self-calibration
– Programmable sampling time
– Data alignment with built-in data coherency
– DMA support
• Low-power
– The application can reduce PCLK frequency for low-power operation while still
keeping optimum ADC performance. For example, 0.87 µs conversion time is
kept, whatever the PCLK frequency
– Wait mode: prevents ADC overrun in applications with low PCLK frequency
– Auto off mode: ADC is automatically powered off except during the active
conversion phase. This dramatically reduces the power consumption of the ADC.
• Analog input channels
– 16 external analog inputs
– Three fast channels connected to PA0, PA4 and PA5, and up to 13 standard
channels (refer to the device datasheet for details on the corresponding GPIOs)
– 1 channel for internal temperature sensor (VSENSE)
– 1 channel for internal reference voltage (VREFINT)
• Start-of-conversion can be initiated:
– By software
– By hardware triggers with configurable polarity (timer events or GPIO input
events)
• Conversion modes
– Can convert a single channel or can scan a sequence of channels.
– Single mode converts selected inputs once per trigger
– Continuous mode converts selected inputs continuously
– Discontinuous mode
• Interrupt generation at the end of sampling, end of conversion, end of sequence
conversion, and in case of analog watchdog or overrun events
• Analog watchdog
• Oversampler
– 16-bit data register
– Oversampling ratio adjustable from 2 to 256x
– Programmable data shift up to 8-bits
• ADC input range: VSSA ≤ VIN ≤ VDDA

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13.3 ADC functional description

Figure 29 shows the ADC block diagram and Table 56 gives the ADC pin description.

Figure 29. ADC block diagram

ADC VREF+
1.65 to 3.6 V

Analog supply
SCANDIR up/ 1.8 to 3.6 V AREADY
down EOSMP ADC interrupt
AUTOFF auto-off EOS IRQ
CH_SEL[18:0] EOC CPU
mode
CONT single/ ADEN/ADDIS OVR master
DATA[15:0] AWD
cont.

AHB
AHB
to slave
Supply and APB
VREFINT ADCAL self- reference master
APB
calibration DMA
Input interface
VSENSE
selection SAR ADC
VIN DMA request
& scan
ADC_IN[15:0] control DMAEN
VIN[x] DMACFG
SMP[2:0] Converted data Over-
sampling time start sampler

Start & Stop

control
OVRMOD TOVS AWDx
AUTDLY overrun mode
Auto-delayed conv. ADSTART Analog
ALIGN left/right OVSS[3:0] AWDxEN
S/W trigger watchdog
ADSTP
RSE[1:0] OVSR[2:0] AWDxSGL
12, 10, 8, 6 bits AWDCHx[4:0]
OVSE
LTx[11:0]
HTx[11:0]

TRG0
TRG1
TRG2
H/W
TRG3 trigger DISCEN
TRG4 discontinuous
EXTEN[1:0]
TRG5 mode
trigger enable
TRG6 and edge selection
TRG7

EXTSEL[2:0]
trigger selection

MSv34764V7

1. TRGi are mapped at product level. Refer to Table External triggers in Section 13.3.1: ADC pins and internal signals.

13.3.1 ADC pins and internal signals

Table 56. ADC input/output pins

Name Signal type Remarks

Input, analog power Analog power supply and positive reference voltage
VDDA
supply for the ADC
Input, analog supply
VSSA Ground for analog power supply
ground
ADC_INx Analog input signals Up to 16 external analog input channels

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Table 57. ADC internal input/output signals

Internal signal
Signal type Description
name

Analog Input Connected either to internal channels or to ADC_INi

VIN[x]
channels external channels
TRGx Input ADC conversion triggers
VSENSE Input Internal temperature sensor output voltage
VREFINT Input Internal voltage reference output voltage
Internal analog watchdog output signal connected to on-
ADC_AWDx_OUT Output
chip timers (x = Analog watchdog number = 1)

Table 58. External triggers

Name Source EXTSEL[2:0]

TRG0 TIM6_TRGO 000

TRG1 TIM21_CH2 001
TRG2 TIM2_TRGO 010
TRG3 TIM2_CH4 011
(1)
TRG4 TIM22_TRGO, TIM21_TRGO 100
(2)
TRG5 TIM2_CH3 101
TRG6 TIM3_TRGO 110
TRG7 EXTI11 111
1. TIM21_TRGO is available only in category 1 devices.
2. Available on all categories except category 3.

13.3.2 ADC voltage regulator (ADVREGEN)

The ADC has a specific internal voltage regulator which must be enabled and stable before
using the ADC.
The ADC voltage regulator stabilization time is entirely managed by the hardware and
software does not need to care about it.
After ADC operations are complete, the ADC can be disabled (ADEN = 0). To keep power
consumption low, it is important to disable the ADC voltage regulator before entering low-
power mode (LPRun, LPSleep or Stop mode). Refer to Section : ADVREG disable
sequence.
Note: When the internal voltage regulator is disabled, the internal analog calibration is kept.

Analog reference for the ADC internal voltage regulator

The internal ADC voltage regulator uses a buffered copy of the internal voltage reference.
This buffer is always enabled when the main voltage regulator is in normal Run mode (MR
mode, with the device operating either in Run or Sleep mode). When the main voltage
regulator is in low-power mode (with the device operating in LPRun, LPSleep or Stop
mode), the voltage reference is disabled and the ADC cannot be used anymore.

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The software must follow the procedure described below to manage the ADC in low-power
mode:
1. Make sure that the ADC is disabled (ADEN = 0).
2. Write ADVREGEN = 0.
3. Enter low-power mode.
4. Resume from low-power mode.
5. Check that REGLPF = 0.
6. Enable the ADC voltage regulator by using the sequence described in Section :
ADVREG enable sequence (ADVREGEN = 1 in ADC_CR).
7. Write ADC_CR ADEN = 1 and wait until ADC_CR ADRDY = 1.
8. Write ADRDY = 1 to clear it.

ADVREG enable sequence

There are three ways to enable the voltage regulator:
• by writing ADVREGEN = 1.
• by launching the calibration by writing by ADCAL = 1 (the ADVREGEN bit is
automatically set).
• by enabling the ADC by writing ADEN = 1.

ADVREG disable sequence

To disable the ADC voltage regulator, perform the sequence below:
1. Ensure that the ADC is disabled (ADEN = 0).
2. Write ADVREGEN = 0.

13.3.3 Calibration (ADCAL)

The ADC has a calibration feature. During the procedure, the ADC calculates a calibration
factor which is internally applied to the ADC until the next ADC power-off. The application
must not use the ADC during calibration and must wait until it is complete.
Calibration should be performed before starting A/D conversion. It removes the offset error
which may vary from chip to chip due to process variation.
The calibration is initiated by software by setting bit ADCAL = 1. Calibration can only be
initiated when the ADC is disabled (when ADEN = 0). ADCAL bit stays at 1 during all the
calibration sequence. It is then cleared by hardware as soon the calibration completes. After
this, the calibration factor can be read from the ADC_DR register (from bits 6 to 0).
The internal analog calibration is kept if the ADC is disabled (ADEN = 0) or if the ADC
voltage reference is disabled (ADVREGEN = 0). When the ADC operating conditions
change (VDDA changes are the main contributor to ADC offset variations and temperature
change to a lesser extend), it is recommended to re-run a calibration cycle.
The calibration factor is lost in the following cases:
• The product is in Standby mode (power supply removed from the ADC)
• The ADC peripheral is reset.
The calibration factor is maintained in the following low-power modes: LPRun, LPSleep and
Stop.

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It is still possible to save and restore the calibration factor by software to save time when
re-starting the ADC (as long as temperature and voltage are stable during the ADC power
down).
The calibration factor can be written if the ADC is enabled but not converting (ADEN = 1 and
ADSTART = 0). Then, at the next start of conversion, the calibration factor is automatically
injected into the analog ADC. This loading is transparent and does not add any cycle
latency to the start of the conversion.
Software calibration procedure
1. Ensure that ADEN = 0 and DMAEN = 0.
2. Set ADCAL = 1.
3. Wait until ADCAL = 0 (or until EOCAL = 1). This can be handled by interrupt if the
interrupt is enabled by setting the EOCALIE bit in the ADC_IER register. The ADCAL
bit can remain set for some time even after EOCAL has been set. As a result, the
software must wait for ADCAL = 0 after EOCAL = 1 to be able to set ADEN = 1 for next
ADC conversions.
4. The calibration factor can be read from bits 6:0 of ADC_DR or ADC_CALFACT
registers.
For code example, refer to A.8.1: Calibration code example.

Figure 30. ADC calibration

t CAB

ADCAL

ADC State OFF Startup CALIBRATE OFF

CALIBRATION
ADC_DR[6:0] 0x00 FACTOR
ADC_CALFACT[6:0]
by S/W by H/W
MS33703V1

If the ADC voltage regulator was not previously set, it is automatically enabled when setting
ADCAL = 1 (bit ADVREGEN is automatically set by hardware). In this case, the ADC
calibration time is longer to take into account the stabilization time of the ADC voltage
regulator.
At the end of the calibration, the ADC voltage regulator remains enabled.

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Calibration factor forcing software procedure

1. Ensure that ADEN= 1 and ADSTART = 0 (ADC started with no conversion ongoing)
2. Write ADC_CALFACT with the saved calibration factor
3. The calibration factor is used as soon as a new conversion is launched.

Figure 31. Calibration factor forcing

ADC state Ready (not converting) Converting channel Ready Converting channel
Updating (Single ended) (Single ended)
calibration
Internal
calibration factor[6:0] F1 F2
Start conversion
(hardware or software)

WRITE ADC_CALFACT

CALFACT[6:0] F2

by S/W by H/W
MS31925V1

13.3.4 ADC on-off control (ADEN, ADDIS, ADRDY)

At power-up, the ADC is disabled and put in power-down mode (ADEN = 0).
As shown in Figure 32, the ADC needs a stabilization time of tSTAB before it starts
converting accurately.
Two control bits are used to enable or disable the ADC:
• Set ADEN = 1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready
for operation.
• Set ADDIS = 1 to disable the ADC and put the ADC in power down mode. The ADEN
and ADDIS bits are then automatically cleared by hardware as soon as the ADC is fully
disabled.
If the ADC voltage regulator was not previously set, it is automatically enabled when setting
ADEN=1 (bit ADVREGEN is automatically set by hardware). In this case, the ADC
stabilization time tSTAB is longer to take into account the stabilization time of the ADC
voltage regulator.
Conversion can then start either by setting ADSTART to 1 (refer to Section 13.4: Conversion
on external trigger and trigger polarity (EXTSEL, EXTEN) on page 292) or when an external
trigger event occurs if triggers are enabled.
Follow this procedure to enable the ADC:
1. Clear the ADRDY bit in ADC_ISR register by programming this bit to 1.
2. Set ADEN = 1 in the ADC_CR register.
3. Wait until ADRDY = 1 in the ADC_ISR register (ADRDY is set after the ADC startup
time). This can be handled by interrupt if the interrupt is enabled by setting the
ADRDYIE bit in the ADC_IER register.
For code example, refer to A.8.2: ADC enable sequence code example.

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Follow this procedure to disable the ADC:

1. Check that ADSTART = 0 in the ADC_CR register to ensure that no conversion is
ongoing. If required, stop any ongoing conversion by writing 1 to the ADSTP bit in the
ADC_CR register and waiting until this bit is read at 0.
2. Set ADDIS = 1 in the ADC_CR register.
3. If required by the application, wait until ADEN = 0 in the ADC_CR register, indicating
that the ADC is fully disabled (ADDIS is automatically reset once ADEN = 0).
4. Clear the ADRDY bit in ADC_ISR register by programming this bit to 1 (optional).
For code example, refer to A.8.3: ADC disable sequence code example.

Figure 32. Enabling/disabling the ADC

ADEN
t STAB

ADR DY

ADDIS

ADC
OFF Startup RDY CONVERTING CH RDY REQ
stat -OF OFF

by S/W by H/W
MS30264V2

Note: In Auto-off mode (AUTOFF = 1) the power-on/off phases are performed automatically, by
hardware and the ADRDY flag is not set.

13.3.5 ADC clock (CKMODE, PRESC[3:0], LFMEN)

The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock
(ADC asynchronous clock) independent from the APB clock (PCLK).

Figure 33. ADC clock scheme

RCC ADITF
(Reset & Clock Controller)
APB interface
PCLK
Bits CKMODE[1:0]
of ADC_CFGR2

/1 or /2 or /4 Others
Analog ADC_CK Analog
ADC
00
ADC /1,2,4,6,8,10,12
asynchronous 16,32,64,128,256
clock Bits CKMODE[1:0]
of ADC_CFGR2
Bits PRESC[3:0]
of ADC_CCR

MSv31926V2

1. Refer to Section Reset and clock control (RCC) for how the PCLK clock and ADC asynchronous clock are
enabled.

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The input clock of the analog ADC can be selected between two different clock sources (see
Figure 33: ADC clock scheme to see how the PCLK clock and the ADC asynchronous clock
are enabled):
a) The ADC clock can be a specific clock source, named “ADC asynchronous clock“
which is independent and asynchronous with the APB clock.
Refer to RCC Section for more information on generating this clock source.
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be
reset.
b) The ADC clock can be derived from the APB clock of the ADC bus interface,
divided by a programmable factor (1, 2 or 4) according to bits CKMODE[1:0].
To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be
different from “00”.
For code example, refer to A.8.4: ADC clock selection code example.
In option a), the generated ADC clock can eventually be divided by a prescaler (1, 2, 4, 6, 8,
10, 12, 16, 32, 64, 128, 256) when programming the bits PRESC[3:0] in the ADC_CCR
register).
Option a) has the advantage of reaching the maximum ADC clock frequency whatever the
APB clock scheme selected.
Option b) has the advantage of bypassing the clock domain resynchronizations. This can be
useful when the ADC is triggered by a timer and if the application requires that the ADC is
precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is
added by the resynchronizations between the two clock domains).
Table 59. Latency between trigger and start of conversion(1)
Latency between the trigger event
ADC clock source CKMODE[1:0]
and the start of conversion

HSI16 MHz clock 00 Latency is not deterministic (jitter)

Latency is deterministic (no jitter) and equal to
PCLK divided by 2 01
4.25 ADC clock cycles
Latency is deterministic (no jitter) and equal to
PCLK divided by 4 10
4.125 ADC clock cycles
Latency is deterministic (no jitter) and equal to
PCLK divided by 1 11
4.5 ADC clock cycles
1. Refer to the device datasheet for the maximum ADC_CLK frequency.

Caution: When selecting CKMODE[1:0] = 11 (PCLK divided by 1), the user must ensure that the
PCLK has a 50% duty cycle. This is done by selecting a system clock with a 50% duty cycle
and configuring the APB prescaler in bypass modes in the RCC (refer to there Reset and
clock controller section). If an internal source clock is selected, the AHB and APB prescalers
do not divide the clock.

Low frequency
When selecting an analog ADC clock frequency lower than 3.5 MHz, it is mandatory to first
enable the Low Frequency Mode by setting bit LFMEN = 1 into the ADC_CCR register

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13.3.6 ADC connectivity

ADC inputs are connected to the external channels as well as internal sources as described
in Figure 34.

Figure 34. ADC connectivity

STM32L0x1
ADC
Channel selection
VIN[0] Fast channel
ADC_IN0

VIN[1]
ADC_IN1

VIN[2]
ADC_IN2

VIN[3]
ADC_IN3

VIN[4] Fast channel

ADC_IN4

VIN[5] Fast channel

ADC_IN5

VIN[6]
ADC_IN6

VIN[7] VREF+
ADC_IN7

VIN[8]
ADC_IN8
VIN
SAR
VIN[9]
ADC_IN9 ADC1

VIN[10]
ADC_IN10

VIN[11] VREF-
ADC_IN11

VIN[12]
ADC_IN12

VIN[13]
ADC_IN13

VIN[14]
ADC_IN14

VIN[15]
ADC_IN15

VIN[16]
Reserved

VIN[17]
VREFINT

VIN[18]
VSENSE

MSv68734V1

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13.3.7 Configuring the ADC

The software must write the ADCAL and ADEN bits in the ADC_CR register and configure
the ADC_CFGR1 and ADC_CFGR2 registers only when the ADC is disabled (ADEN must
be cleared).
The software must only write to the ADSTART and ADDIS bits in the ADC_CR register only
if the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and
ADDIS = 0).
For all the other control bits in the ADC_IER, ADC_SMPR, ADC_TR, ADC_CHSELR and
ADC_CCR registers, refer to the description of the corresponding control bit in
Section 13.11: ADC registers.
The software must only write to the ADSTP bit in the ADC_CR register if the ADC is enabled
(and possibly converting) and there is no pending request to disable the ADC (ADSTART =
1 and ADDIS = 0).
Note: There is no hardware protection preventing software from making write operations forbidden
by the above rules. If such a forbidden write access occurs, the ADC may enter an
undefined state. To recover correct operation in this case, the ADC must be disabled (clear
ADEN = 0 and all the bits in the ADC_CR register).

13.3.8 Channel selection (CHSEL, SCANDIR)

There are up to 18 multiplexed channels:
• 16 analog inputs from GPIO pins (ADC_INx)
• 2 internal analog inputs (Temperature Sensor, Internal Reference Voltage)
It is possible to convert a single channel or a sequence of channels.
The sequence of the channels to be converted can be programmed in the ADC_CHSELR
channel selection register: each analog input channel has a dedicated selection bit
(CHSELx).
The order in which the channels is scanned can be configured by programming the bit
SCANDIR bit in the ADC_CFGR1 register:
• SCANDIR = 0: forward scan Channel 0 to Channel 18
• SCANDIR = 1: backward scan Channel 18 to Channel 0

Temperature sensor, VREFINT internal channels

The temperature sensor is connected to channel ADC VIN[18].
The internal voltage reference VREFINT is connected to channel ADC VIN[17].

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13.3.9 Programmable sampling time (SMP)

Before starting a conversion, the ADC needs to establish a direct connection between the
voltage source to be measured and the embedded sampling capacitor of the ADC. This
sampling time must be enough for the input voltage source to charge the sample and hold
capacitor to the input voltage level.
Having a programmable sampling time allows the conversion speed to be trimmed
according to the input resistance of the input voltage source.
Refer to the device datasheet to select the correct sampling time depending on the type of
channel you are using (fast or standard).
The ADC samples the input voltage for a number of ADC clock cycles that can be modified
using the SMP[2:0] bits in the ADC_SMPR register.
This programmable sampling time is common to all channels. If required by the application,
the software can change and adapt this sampling time between each conversions.
The total conversion time is calculated as follows:
tCONV = Sampling time + 12.5 x ADC clock cycles
Example:
With ADC_CLK = 16 MHz and a sampling time of 1.5 ADC clock cycles:
tCONV = 1.5 + 12.5 = 14 ADC clock cycles = 0.875 µs
The ADC indicates the end of the sampling phase by setting the EOSMP flag.

13.3.10 Single conversion mode (CONT = 0)

In Single conversion mode, the ADC performs a single sequence of conversions, converting
all the channels once. This mode is selected when CONT = 0 in the ADC_CFGR1 register.
Conversion is started by either:
• Setting the ADSTART bit in the ADC_CR register
• Hardware trigger event
Inside the sequence, after each conversion is complete:
• The converted data are stored in the 16-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set
Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set
again.
Note: To convert a single channel, program a sequence with a length of 1.

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13.3.11 Continuous conversion mode (CONT = 1)

In continuous conversion mode, when a software or hardware trigger event occurs, the ADC
performs a sequence of conversions, converting all the channels once and then
automatically re-starts and continuously performs the same sequence of conversions. This
mode is selected when CONT = 1 in the ADC_CFGR1 register. Conversion is started by
either:
• Setting the ADSTART bit in the ADC_CR register
• Hardware trigger event
Inside the sequence, after each conversion is complete:
• The converted data are stored in the 16-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set
Then, a new sequence restarts immediately and the ADC continuously repeats the
conversion sequence.
Note: To convert a single channel, program a sequence with a length of 1.
It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.

13.3.12 Starting conversions (ADSTART)

Software starts ADC conversions by setting ADSTART = 1.
When ADSTART is set, the conversion:
• Starts immediately if EXTEN = 00 (software trigger)
• At the next active edge of the selected hardware trigger if EXTEN ≠ 00
The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing. It
is possible to re-configure the ADC while ADSTART = 0, indicating that the ADC is idle.
The ADSTART bit is cleared by hardware:
• In single mode with software trigger (CONT = 0, EXTEN = 00)
– At any end of conversion sequence (EOS = 1)
• In discontinuous mode with software trigger (CONT = 0, DISCEN = 1, EXTEN = 00)
– At end of conversion (EOC = 1)
• In all cases (CONT = x, EXTEN = XX)
– After execution of the ADSTP procedure invoked by software (see
Section 13.3.14: Stopping an ongoing conversion (ADSTP) on page 292)
Note: In continuous mode (CONT = 1), the ADSTART bit is not cleared by hardware when the
EOS flag is set because the sequence is automatically relaunched.
When hardware trigger is selected in single mode (CONT = 0 and EXTEN = 01), ADSTART
is not cleared by hardware when the EOS flag is set (except if DMAEN = 1 and
DMACFG = 0 in which case ADSTART is cleared at end of the DMA transfer). This avoids

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the need for software having to set the ADSTART bit again and ensures the next trigger
event is not missed.

13.3.13 Timings
The elapsed time between the start of a conversion and the end of conversion is the sum of
the configured sampling time plus the successive approximation time depending on data
resolution:

tCONV = tSMPL + tSAR = [ 1.5 |min + 12.5 |12bit ] x tADC_CLK

tCONV = tSMPL + tSAR = 93.8 ns |min + 781.3 ns |12bit = 0.875 µs |min (for fADC_CLK = 16 MHz)

Figure 35. Analog to digital conversion time

ADC state RDY SAMPLING CH(N) CONVERTING CH(N) SAMPLING CH(N+1)

Analog
CH(N) CH(N+1)
channel
Internal S/H Sample AIN(N+1) Hold AIN(N) Sample AIN(N+1)
t SMPL (1) t SAR(2)
set
by SW
ADSTART
set by HW cleared by SW
EOSMP set cleared
EOC by HW by SW

ADC_DR DATA N-1 DATA N

(1) t SMPL depends on SMP[2:0]

(2) t SAR depends on RES[2:0] MS30336V1

Figure 36. ADC conversion timings

ADSTART(1) tLATENCY (2)

ADC state Ready S0 Conversion 0 S1 Conversion 1 S2 Conversion 2 S3 Conversion 3

(3) (3)
WLATENCY WLATENCY WLATENCY (3)
ADC_DR

Data 0 Data 1 Data 2

MSv33174V1

1. EXTEN = 00 or EXTEN ≠ 00
2. Trigger latency (refer to datasheet for more details)
3. ADC_DR register write latency (refer to datasheet for more details)

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13.3.14 Stopping an ongoing conversion (ADSTP)

The software can decide to stop any ongoing conversions by setting ADSTP = 1 in the
ADC_CR register.
This resets the ADC operation and the ADC is idle, ready for a new operation.
When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is
discarded (ADC_DR register is not updated with the current conversion).
The scan sequence is also aborted and reset (meaning that restarting the ADC would re-
start a new sequence).
Once this procedure is complete, the ADSTP and ADSTART bits are both cleared by
hardware and the software must wait until ADSTART=0 before starting new conversions.

Figure 37. Stopping an ongoing conversion

ADC state RDY SAMPLING CH(N) CONVERTING CH(N) RDY

ADSTART set by SW cleared by HW

set by SW cleared by HW
ADSTOP
ADC_DR DATA N-1

MS30337V1

13.4 Conversion on external trigger and trigger polarity (EXTSEL,

EXTEN)
A conversion or a sequence of conversion can be triggered either by software or by an
external event (for example timer capture). If the EXTEN[1:0] control bits are not equal to
“0b00”, then external events are able to trigger a conversion with the selected polarity. The
trigger selection is effective once software has set bit ADSTART = 1.
Any hardware triggers which occur while a conversion is ongoing are ignored.
If bit ADSTART = 0, any hardware triggers which occur are ignored.
Table 60 provides the correspondence between the EXTEN[1:0] values and the trigger
polarity.

Table 60. Configuring the trigger polarity

Source EXTEN[1:0]

Trigger detection disabled 00

Detection on rising edge 01
Detection on falling edge 10
Detection on both rising and falling edges 11

Note: The polarity of the external trigger can be changed only when the ADC is not converting
(ADSTART = 0).
The EXTSEL[2:0] control bits are used to select which of 8 possible events can trigger
conversions.

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Refer to Table 58: External triggers in Section 13.3.1: ADC pins and internal signals for the
list of all the external triggers that can be used for regular conversion.
The software source trigger events can be generated by setting the ADSTART bit in the
ADC_CR register.
Note: The trigger selection can be changed only when the ADC is not converting (ADSTART = 0).

13.4.1 Discontinuous mode (DISCEN)

This mode is enabled by setting the DISCEN bit in the ADC_CFGR1 register.
In this mode (DISCEN = 1), a hardware or software trigger event is required to start each
conversion defined in the sequence. On the contrary, if DISCEN = 0, a single hardware or
software trigger event successively starts all the conversions defined in the sequence.
Example:
• DISCEN = 1, channels to be converted = 0, 3, 7, 10
– 1st trigger: channel 0 is converted and an EOC event is generated
– 2nd trigger: channel 3 is converted and an EOC event is generated
– 3rd trigger: channel 7 is converted and an EOC event is generated
– 4th trigger: channel 10 is converted and both EOC and EOS events are
generated.
– 5th trigger: channel 0 is converted an EOC event is generated
– 6th trigger: channel 3 is converted and an EOC event is generated
– ...
• DISCEN = 0, channels to be converted = 0, 3, 7, 10
– 1st trigger: the complete sequence is converted: channel 0, then 3, 7 and 10. Each
conversion generates an EOC event and the last one also generates an EOS
event.
– Any subsequent trigger events restarts the complete sequence.
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.

13.4.2 Programmable resolution (RES) - Fast conversion mode

It is possible to obtain faster conversion times (tSAR) by reducing the ADC resolution.
The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the
RES[1:0] bits in the ADC_CFGR1 register. Lower resolution allows faster conversion times
for applications where high data precision is not required.
Note: The RES[1:0] bit must only be changed when the ADEN bit is reset.
The result of the conversion is always 12 bits wide and any unused LSB bits are read as
zeros.
Lower resolution reduces the conversion time needed for the successive approximation
steps as shown in Table 61.

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Table 61. tSAR timings depending on resolution

tSAR tSMPL (min) tCONV
RES[1:0] tSAR (ns) at tCONV (ns) at
(ADC clock (ADC clock (ADC clock cycles)
bits fADC = 16 MHz fADC = 16 MHz
cycles) cycles) (with min. tSMPL)

12 12.5 781 ns 1.5 14 875 ns

10 11.5 719 ns 1.5 13 812 ns
8 9.5 594 ns 1.5 11 688 ns
6 7.5 469 ns 1.5 9 562 ns

13.4.3 End of conversion, end of sampling phase (EOC, EOSMP flags)

The ADC indicates each end of conversion (EOC) event.
The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data
result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is
set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or
by reading the ADC_DR register.
The ADC also indicates the end of sampling phase by setting the EOSMP flag in the
ADC_ISR register. The EOSMP flag is cleared by software by writing1 to it. An interrupt can
be generated if the EOSMPIE bit is set in the ADC_IER register.
The aim of this interrupt is to allow the processing to be synchronized with the conversions.
Typically, an analog multiplexer can be accessed in hidden time during the conversion
phase, so that the multiplexer is positioned when the next sampling starts.
Note: As there is only a very short time left between the end of the sampling and the end of the
conversion, it is recommenced to use polling or a WFE instruction rather than an interrupt
and a WFI instruction.

13.4.4 End of conversion sequence (EOS flag)

The ADC notifies the application of each end of sequence (EOS) event.
The ADC sets the EOS flag in the ADC_ISR register as soon as the last data result of a
conversion sequence is available in the ADC_DR register. An interrupt can be generated if
the EOSIE bit is set in the ADC_IER register. The EOS flag is cleared by software by writing
1 to it.

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13.4.5 Example timing diagrams (single/continuous modes

hardware/software triggers)

Figure 38. Single conversions of a sequence, software trigger

ADSTART(1)

EOC

EOS

SCANDIR

ADC state(2) RDY CH0 CH9 CH10 CH17 RDY CH17 CH10 CH9 CH0 RDY

ADC_DR D0 D9 D10 D17 D17 D10 D9 D0

by S/W by H/W

MSv30338V3

1. EXTEN = 00, CONT = 0

2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0
For code example, refer to A.8.5: Single conversion sequence code example - Software
trigger.

Figure 39. Continuous conversion of a sequence, software trigger

ADSTART(1)

EOC

EOS

ADSTP

SCANDIR

ADC state(2) RDY CH0 CH9 CH10 CH17 CH0 CH9 CH10 STP RDY CH17 CH10

ADC_DR D0 D9 D10 D17 D0 D9 D17

by S/W by H/W

MSv30339V2

1. EXTEN = 00, CONT = 1,

2. CHSEL = 0x20601, WAIT = 0, AUTOFF = 0
For code example, refer to A.8.6: Continuous conversion sequence code example -
Software trigger.

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Figure 40. Single conversions of a sequence, hardware trigger

ADSTART(1)

EOC

EOS

TRGx(1)

ADC state(2) RDY CH0 CH1 CH2 CH3 RDY CH0 CH1 CH2 CH3 RDY

ADC_DR D0 D1 D2 D3 D0 D1 D2 D3

by S/W by H/W
triggered ignored

MSv30340V2

1. EXTSEL = TRGx (over-frequency), EXTEN = 01 (rising edge), CONT = 0

2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0
For code example, refer to A.8.7: Single conversion sequence code example - Hardware
trigger.

Figure 41. Continuous conversions of a sequence, hardware trigger

ADSTART(1)

EOC

EOS

ADSTP

TRGx(1)

ADC state(2) RDY CH0 CH1 CH2 CH3 CH0 CH1 CH2 CH3 CH0 STOP RDY

ADC_DR D0 D1 D2 D3 D0 D1 D2 D3

by S/W by H/W
triggered ignored

MSv30341V2

1. EXTSEL = TRGx, EXTEN = 10 (falling edge), CONT = 1

2. CHSEL = 0xF, SCANDIR = 0, WAIT = 0, AUTOFF = 0
For code example, refer to A.8.8: Continuous conversion sequence code example -
Hardware trigger.

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13.5 Data management

13.5.1 Data register and data alignment (ADC_DR, ALIGN)

At the end of each conversion (when an EOC event occurs), the result of the converted data
is stored in the ADC_DR data register which is 16-bit wide.
The format of the ADC_DR depends on the configured data alignment and resolution.
The ALIGN bit in the ADC_CFGR1 register selects the alignment of the data stored after
conversion. Data can be right-aligned (ALIGN = 0) or left-aligned (ALIGN = 1) as shown in
Figure 42.

Figure 42. Data alignment and resolution (oversampling disabled: OVSE = 0)

ALIGN RES 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0x0 0x0 DR[11:0]

0x1 0x00 DR[9:0]
0x2 0x00 DR[7:0]
0x3 0x00 DR[5:0]
1 0x0 DR[11:0] 0x0
0x1 DR[9:0] 0x00
0x2 DR[7:0] 0x00
0x3 0x00 DR[5:0] 0x0

MS30342V1

13.5.2 ADC overrun (OVR, OVRMOD)

The overrun flag (OVR) indicates a data overrun event, when the converted data was not
read in time by the CPU or the DMA, before the data from a new conversion is available.
The OVR flag is set in the ADC_ISR register if the EOC flag is still at ‘1’ at the time when a
new conversion completes. An interrupt can be generated if the OVRIE bit is set in the
ADC_IER register.
When an overrun condition occurs, the ADC keeps operating and can continue to convert
unless the software decides to stop and reset the sequence by setting the ADSTP bit in the
ADC_CR register.
The OVR flag is cleared by software by writing 1 to it.
It is possible to configure if the data is preserved or overwritten when an overrun event
occurs by programming the OVRMOD bit in the ADC_CFGR1 register:
• OVRMOD = 0
– An overrun event preserves the data register from being overwritten: the old data
is maintained and the new conversion is discarded. If OVR remains at 1, further
conversions can be performed but the resulting data is discarded.
• OVRMOD = 1
– The data register is overwritten with the last conversion result and the previous
unread data is lost. If OVR remains at 1, further conversions can be performed
and the ADC_DR register always contains the data from the latest conversion.

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Figure 43. Example of overrun (OVR)

ADSTART(1)

EOC

EOS

OVR

ADSTP

TRGx(1)

ADC state(2)
RDY CH0 CH1 CH2 CH0 CH1 CH2 CH0 STOP RDY

ADC_DR read OVERRUN

access

ADC_DR
(OVRMOD=0) D0 D1 D2 D0

ADC_DR
(OVRMOD=1) D0 D1 D2 D0 D1 D2

by S/W by H/W
triggered

MSv30343V3

13.5.3 Managing a sequence of data converted without using the DMA

If the conversions are slow enough, the conversion sequence can be handled by software.
In this case the software must use the EOC flag and its associated interrupt to handle each
data result. Each time a conversion is complete, the EOC bit is set in the ADC_ISR register
and the ADC_DR register can be read. The OVRMOD bit in the ADC_CFGR1 register
should be configured to 0 to manage overrun events as an error.

13.5.4 Managing converted data without using the DMA without overrun
It may be useful to let the ADC convert one or more channels without reading the data after
each conversion. In this case, the OVRMOD bit must be configured at 1 and the OVR flag
should be ignored by the software. When OVRMOD = 1, an overrun event does not prevent
the ADC from continuing to convert and the ADC_DR register always contains the latest
conversion data.

13.5.5 Managing converted data using the DMA

Since all converted channel values are stored in a single data register, it is efficient to use
DMA when converting more than one channel. This avoids losing the conversion data
results stored in the ADC_DR register.

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When DMA mode is enabled (DMAEN bit set in the ADC_CFGR1 register), a DMA request
is generated after the conversion of each channel. This allows the transfer of the converted
data from the ADC_DR register to the destination location selected by the software.
Note: The DMAEN bit in the ADC_CFGR1 register must be set after the ADC calibration phase.
Despite this, if an overrun occurs (OVR = 1) because the DMA could not serve the DMA
transfer request in time, the ADC stops generating DMA requests and the data
corresponding to the new conversion is not transferred by the DMA. Which means that all
the data transferred to the RAM can be considered as valid.
Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten
(refer to Section 13.5.2: ADC overrun (OVR, OVRMOD) on page 297).
The DMA transfer requests are blocked until the software clears the OVR bit.
Two different DMA modes are proposed depending on the application use and are
configured with bit DMACFG in the ADC_CFGR1 register:
• DMA one shot mode (DMACFG = 0).
This mode should be selected when the DMA is programmed to transfer a fixed
number of data words.
• DMA circular mode (DMACFG = 1)
This mode should be selected when programming the DMA in circular mode.

DMA one shot mode (DMACFG = 0)

In this mode, the ADC generates a DMA transfer request each time a new conversion data
word is available and stops generating DMA requests once the DMA has reached the last
DMA transfer (when a DMA_EOT interrupt occurs, see Section 10: Direct memory access
controller (DMA) on page 241) even if a conversion has been started again.
For code example, refer to A.8.9: DMA one shot mode sequence code example.
When the DMA transfer is complete (all the transfers configured in the DMA controller have
been done):
• The content of the ADC data register is frozen.
• Any ongoing conversion is aborted and its partial result discarded
• No new DMA request is issued to the DMA controller. This avoids generating an
overrun error if there are still conversions which are started.
• The scan sequence is stopped and reset
• The DMA is stopped

DMA circular mode (DMACFG = 1)

In this mode, the ADC generates a DMA transfer request each time a new conversion data
word is available in the data register, even if the DMA has reached the last DMA transfer.
This allows the DMA to be configured in circular mode to handle a continuous analog input
data stream.
For code example, refer to A.8.10: DMA circular mode sequence code example.

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13.6 Low-power features

13.6.1 Wait mode conversion

Wait mode conversion can be used to simplify the software as well as optimizing the
performance of applications clocked at low frequency where there might be a risk of ADC
overrun occurring.
When the WAIT bit is set in the ADC_CFGR1 register, a new conversion can start only if the
previous data has been treated, once the ADC_DR register has been read or if the EOC bit
has been cleared.
This is a way to automatically adapt the speed of the ADC to the speed of the system that
reads the data.
Note: Any hardware triggers which occur while a conversion is ongoing or during the wait time
preceding the read access are ignored.

Figure 44. Wait mode conversion (continuous mode, software trigger)

ADSTART

EOC

EOS

ADSTP

ADC_DR Read access

ADC state RDY CH1 DLY CH2 DLY CH3 DLY CH1 DLY STOP RDY

ADC_DR D1 D2 D3 D1

by S/W by H/W

MSv30344V2

1. EXTEN = 00, CONT = 1

2. CHSEL = 0x3, SCANDIR = 0, WAIT = 1, AUTOFF = 0
For code example, refer to A.8.11: Wait mode sequence code example.

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13.6.2 Auto-off mode (AUTOFF)

The ADC has an automatic power management feature which is called auto-off mode, and
is enabled by setting AUTOFF = 1 in the ADC_CFGR1 register.
When AUTOFF = 1, the ADC is always powered off when not converting and automatically
wakes-up when a conversion is started (by software or hardware trigger). A startup-time is
automatically inserted between the trigger event which starts the conversion and the
sampling time of the ADC. The ADC is then automatically disabled once the sequence of
conversions is complete.
Auto-off mode can cause a dramatic reduction in the power consumption of applications
which need relatively few conversions or when conversion requests are timed far enough
apart (for example with a low frequency hardware trigger) to justify the extra power and
extra time used for switching the ADC on and off.
Auto-off mode can be combined with the wait mode conversion (WAIT = 1) for applications
clocked at low frequency. This combination can provide significant power savings if the ADC
is automatically powered-off during the wait phase and restarted as soon as the ADC_DR
register is read by the application (see Figure 46: Behavior with WAIT = 1, AUTOFF = 1).
Note: Refer to the Section Reset and clock control (RCC) for the description of how to manage
the dedicated 14 MHz internal oscillator. The ADC interface can automatically switch
ON/OFF the 14 MHz internal oscillator to save power.

Figure 45. Behavior with WAIT = 0, AUTOFF = 1

TRGx

EOC

EOS

ADC_DR Read
access

ADC state RDY Startup CH1 CH2 CH3 CH4 OFF Startup

ADC_DR D1 D2 D3 D4

by S/W by H/W
triggered

MSv30345V2

1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1,
AUTOFF = 1
For code example, refer to A.8.12: Auto off and no wait mode sequence code example.

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Figure 46. Behavior with WAIT = 1, AUTOFF = 1

TRGx

EOC

EOS

ADC_DR Read
access DLY DLY DLY DLY

OFF

OFF
ADC state RDY Startup CH1 OFF Startup CH2 Startup CH3 OFF Startup CH1 CH2

D1 D2 D3 D4
ADC_DR

by S/W by H/W
triggered

MSv30346V2

1. EXTSEL = TRGx, EXTEN = 01 (rising edge), CONT = x, ADSTART = 1, CHSEL = 0xF, SCANDIR = 0, WAIT = 1,
AUTOFF = 1
For code example, refer to A.8.13: Auto off and wait mode sequence code example.

13.7 Analog window watchdog (AWDEN, AWDSGL, AWDCH,

ADC_TR)

13.7.1 Description of the analog watchdog

The AWD analog watchdog is enabled by setting the AWDEN bit in the ADC_CFGR1
register. It is used to monitor that either one selected channel or all enabled channels (see
Table 63: Analog watchdog channel selection) remain within a configured voltage range
(window) as shown in Figure 47.
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
HT[11:0] and LT[11:0] bit of ADC_TR register. An interrupt can be enabled by setting the
AWDIE bit in the ADC_IER register.
The AWD flag is cleared by software by programming it to it.
When converting data with a resolution of less than 12-bit (according to bits RES[1:0]), the
LSB of the programmed thresholds must be kept cleared because the internal comparison
is always performed on the full 12-bit raw converted data (left aligned).
For code example, refer to A.8.14: Analog watchdog code example.
Table 62 describes how the comparison is performed for all the possible resolutions.

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Table 62. Analog watchdog comparison

Analog Watchdog comparison between:
Resolution
bits Comments
Raw converted
RES[1:0] Thresholds
data, left aligned(1)

00: 12-bit DATA[11:0] LT[11:0] and HT[11:0] -

01: 10-bit DATA[11:2],00 LT[11:0] and HT[11:0] The user must configure LT1[1:0] and HT1[1:0] to “00”
The user must configure LT1[3:0] and HT1[3:0] to
10: 8-bit DATA[11:4],0000 LT[11:0] and HT[11:0]
“0000”
The user must configure LT1[5:0] and HT1[5:0] to
11: 6-bit DATA[11:6],000000 LT[11:0] and HT[11:0]
“000000”
1. The watchdog comparison is performed on the raw converted data before any alignment calculation.

Table 63 shows how to configure the AWDSGL and AWDEN bits in the ADC_CFGR1
register to enable the analog watchdog on one or more channels.

Figure 47. Analog watchdog guarded area

Analog voltage

Higher threshold HTx

Guarded area
Lower threshold LTx

MS45396V1

Table 63. Analog watchdog channel selection

Channels guarded by the analog watchdog AWDSGL bit AWDEN bit

None x 0
All channels 0 1
Single(1) channel 1 1
1. Selected by the AWDCH[4:0] bits

13.7.2 ADC_AWD1_OUT output signal generation

The analog watchdog is associated to an internal hardware signal, ADC_AWD1_OUT that is
directly connected to the ETR input (external trigger) of some on-chip timers (refer to the
timers section for details on how to select the ADC_AWD1_OUT signal as ETR).

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ADC_AWD1_OUT is activated when the analog watchdog is enabled:

• ADC_AWD1_OUT is set when a guarded conversion is outside the programmed
thresholds.
• ADC_AWD1_OUT is reset after the end of the next guarded conversion which is inside
the programmed thresholds. It remains at 1 if the next guarded conversions are still
outside the programmed thresholds.
• ADC_AWD1_OUT is also reset when disabling the ADC (when setting ADDIS to 1).
Note that stopping conversions (ADSTP set), might clear the ADC_AWD1_OUT state.
• ADC_AWD1_OUT state does not change when the ADC converts the none-guarded
channel (see Figure 48)
AWD flag is set by hardware and reset by software: AWD flag has no influence on the
generation of ADC_AWD1_OUT (as an example, ADC_AWD1_OUT can toggle while AWD
flag remains at 1 if the software has not cleared the flag).
The ADC_AWD1_OUT signal is generated by the ADC_CLK domain. This signal can be
generated even the APB clock is stopped.
The AWD comparison is performed at the end of each ADC conversion. The
ADC_AWD1_OUT rising edge and falling edge occurs two ADC_CLK clock cycles after the
comparison.
As ADC_AWD1_OUT is generated by the ADC_CLK domain and AWD flag is generated by
the APB clock domain, the rising edges of these signals are not synchronized.

Figure 48. ADC_AWD1_OUT signal generation

ADC STATE RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7
inside outside inside outside outside outside inside
EOC FLAG

Cleared Cleared Cleared Cleared

AWD FLAG by SW by SW by SW by SW

ADC_AWD1_OUT

- Converted channels: 1,2,3,4,5,6,7

- Guarded converted channels: 1,2,3,4,5,6,7

MSv65326V1

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Figure 49. ADC_AWD1_OUT signal generation (AWD flag not cleared by software)

ADC STATE RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7

inside outside inside outside outside outside inside

EOC FLAG

not cleared by SW
AWD FLAG

ADC_AWD1_OUT

- Converted channels: 1,2,3,4,5,6,7

- Guarded converted channels: 1,2,3,4,5,6,7
MSv65327V1

Figure 50. ADC1_AWD_OUT signal generation (on a single channel)

ADC STATE Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2

outside inside outside outside

EOC FLAG

EOS FLAG
Cleared Cleared
by SW by SW
AWD FLAG

ADCy_AWD1_OUT

- Converted channels: 1 and 2

- Only channel 1 is guarded

MSv65328V1

13.7.3 Analog watchdog threshold control

LT[11:0] and HT[11:0] can be changed during an analog-to-digital conversion (that is
between the start of the conversion and the end of conversion of the ADC internal state). If
LT and HT bits are programmed during the ADC guarded channel conversion, the watchdog
function is masked for this conversion. This mask is cleared when starting a new
conversion, and the resulting new AWD threshold is applied starting the next ADC
conversion result. AWD comparison is performed at each end of conversion. If the current
ADC data are out of the new threshold interval, this does not generated any interrupt or an
ADC_AWD1_OUT signal. The Interrupt and the ADC_AWD1_OUT generation only occurs
at the end of the ADC conversion that started after the threshold update. If
ADC_AWD1_OUT is already asserted, programming the new threshold does not deassert
the ADC_AWD1_OUT signal.

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Figure 51. Analog watchdog threshold update

ADC state Conversion Conversion Conversion Conversion

Threshould updated

LT, HT XXXX XXXY XXXZ

Comparison Active Masked Active

MSv65329V1

13.8 Oversampler
The oversampling unit performs data preprocessing to offload the CPU. It can handle
multiple conversions and average them into a single data with increased data width, up to
16-bit.
It provides a result with the following form, where N and M can be adjusted:

n = N–1
1
Result = ----- ×
M  Conversion ( t n )
n=0

It allows the following functions to be performed by hardware: averaging, data rate

reduction, SNR improvement, basic filtering.
The oversampling ratio N is defined using the OVFS[2:0] bits in the ADC_CFGR2 register. It
can range from 2x to 256x. The division coefficient M consists of a right bit shift up to 8 bits.
It is configured through the OVSS[3:0] bits in the ADC_CFGR2 register.
For code example, refer to A.8.15: Oversampling code example.
The summation unit can yield a result up to 20 bits (256 x 12-bit), which is first shifted right.
The upper bits of the result are then truncated, keeping only the 16 least significant bits
rounded to the nearest value using the least significant bits left apart by the shifting, before
being finally transferred into the ADC_DR data register.
Note: If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are
simply truncated.

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Figure 52. 20-bit to 16-bit result truncation

19 15 11 7 3 0
Raw 20-bit data

Shifting

15 0
Truncation
and rounding

MS31928V2

The Figure 53 gives a numerical example of the processing, from a raw 20-bit accumulated
data to the final 16-bit result.

Figure 53. Numerical example with 5-bits shift and rounding

19 15 11 7 3
Raw 20-bit data: 3 B 7 D 7

15 0
Final result after 5-bits shift
and rounding to nearest 1 D B F

MS31929V1

The Table 64 below gives the data format for the various N and M combination, for a raw
conversion data equal to 0xFFF.

Table 64. Maximum output results vs N and M. Grayed values indicates truncation
1-bit 2-bit 3-bit 4-bit 5-bit 6-bit 7-bit 8-bit
Oversa No-shift
Max shift shift shift shift shift shift shift shift
mpling OVSS =
ratio Raw data OVSS = OVSS = OVSS = OVSS = OVSS = OVSS = OVSS = OVSS =
0000
0001 0010 0011 0100 0101 0110 0111 1000

2x 0x1FFE 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020
4x 0x3FFC 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040
8x 0x7FF8 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080
16x 0xFFF0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100
32x 0x1FFE0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200
64x 0x3FFC0 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400
128x 0x7FF80 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800
256x 0xFFF00 0xFF00 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF

The conversion timings in oversampled mode do not change compared to standard

conversion mode: the sample time is maintained equal during the whole oversampling

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sequence. New data are provided every N conversion, with an equivalent delay equal to N x
tCONV = N x (tSMPL + tSAR). The flags features are raised as following:
• the end of the sampling phase (EOSMP) is set after each sampling phase
• the end of conversion (EOC) occurs once every N conversions, when the oversampled
result is available
• the end of sequence (EOCSEQ) occurs once the sequence of oversampled data is
completed (i.e. after N x sequence length conversions total)

13.8.1 ADC operating modes supported when oversampling

In oversampling mode, most of the ADC operating modes are available:
• Single or continuous mode conversions, forward or backward scanned sequences
• ADC conversions start either by software or with triggers
• ADC stop during a conversion (abort)
• Data read via CPU or DMA with overrun detection
• Low-power modes (WAIT, AUTOFF)
• Programmable resolution: in this case, the reduced conversion values (as per RES[1:0]
bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the
same way as 12-bit conversions are
Note: The alignment mode is not available when working with oversampled data. The ALIGN bit in
ADC_CFGR1 is ignored and the data are always provided right-aligned.

13.8.2 Analog watchdog

The analog watchdog functionality is available (AWDSGL, AWDEN bits), with the following
differences:
• the RES[1:0] bits are ignored, comparison is always done on using the full 12-bits
values HT[11:0] and LT[11:0]
• the comparison is performed on the most significant 12 bits of the 16 bits oversampled
results ADC_DR[15:4]
Note: Care must be taken when using high shifting values. This reduces the comparison range.
For instance, if the oversampled result is shifted by 4 bits thus yielding a 12-bit data right-
aligned, the affective analog watchdog comparison can only be performed on 8 bits. The
comparison is done between ADC_DR[11:4] and HT[7:0] / LT[[7:0], and HT[11:8] / LT[11:8]
must be kept reset.

13.8.3 Triggered mode

The averager can also be used for basic filtering purposes. Although not a very efficient filter
(slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject
constant parasitic frequencies (typically coming from the mains or from a switched mode
power supply). For this purpose, a specific discontinuous mode can be enabled with TOVS
bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a user and
independent from the conversion time itself.
Figure 54 below shows how conversions are started in response to triggers in discontinuous
mode.
If the TOVS bit is set, the content of the DISCEN bit is ignored and considered as 1.

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Figure 54. Triggered oversampling mode (TOVS bit = 1)

Trigger Trigger

CONT = 0 Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N)

(DISCEN = 1)* 0 1 2 3 0 1 2 3
TOVS = 0
EOC flag set
Trigger Trigger Trigger Trigger Trigger Trigger Trigger
CONT = 0
(DISCEN = 1)* Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N) Ch(N)
TOVS = 1 0 1 2 3 0 1 2

EOC flag set

(DISCEN = 1)*: DISCEN bit is forced to 1 by software when TOVS bit is set

MS33700V1

13.9 Temperature sensor and internal reference voltage

The temperature sensor can be used to measure the junction temperature (TJ) of the
device. The temperature sensor is internally connected to the ADC VIN[18] input channel
which is used to convert the sensor’s output voltage to a digital value. The sampling time for
the temperature sensor analog pin must be greater than the minimum TS_temp value
specified in the datasheet. When not in use, the sensor can be put in power down mode.
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and comparators. VREFINT is internally connected to the ADC VIN[17] input channel.
The precise voltage of VREFINT is individually measured for each part by ST during
production test and stored in the system memory area. It is accessible in read-only mode.
Figure 55 shows the block diagram of connections between the temperature sensor, the
internal voltage reference and the ADC.
The TSEN bit must be set to enable the conversion of ADC VIN[18] (temperature sensor)
and the VREFEN bit must be set to enable the conversion of ADC VIN[17] (VREFINT).
The temperature sensor output voltage changes linearly with temperature. The offset of this
line varies from chip to chip due to process variation (up to 45 °C from one chip to another).
The uncalibrated internal temperature sensor is more suited for applications that detect
temperature variations instead of absolute temperatures. To improve the accuracy of the
temperature sensor measurement, calibration values are stored in system memory for each
device by ST during production.
During the manufacturing process, the calibration data of the temperature sensor and the
internal voltage reference are stored in the system memory area. The user application can
then read them and use them to improve the accuracy of the temperature sensor or the
internal reference. Refer to the datasheet for additional information.

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Main features
• Linearity: ±2 °C max., precision depending on calibration

Figure 55. Temperature sensor and VREFINT channel block diagram

TSEN control bit

Temperature VSENSE

Address/data bus
ADC VIN[18]
sensor
converted
data
ADC

Internal VREFINT
power block ADC VIN[17]

VREFEN control bit

MS34765V2

Reading the temperature

1. Select the ADC VIN[18] input channel.
2. Select an appropriate sampling time specified in the device datasheet (TS_temp).
3. Set the TSEN bit in the ADC_CCR register to wake up the temperature sensor from
power down mode and wait for its stabilization time (tSTART).
For code example, refer to A.8.16: Temperature configuration code example.
4. Start the ADC conversion by setting the ADSTART bit in the ADC_CR register (or by
external trigger).
5. Read the resulting VSENSE data in the ADC_DR register.
6. Calculate the temperature using the following formula

TS_CAL2_TEMP – TS_CAL1_TEMP
Temperature ( in °C ) = ---------------------------------------------------------------------------------------------------- × ( TS_DATA – TS_CAL1 ) + TS_CAL1_TEMP
TS_CAL2 – TS_CAL1

Where:
• TS_CAL2 is the temperature sensor calibration value acquired at TS_CAL2_TEMP
(refer to the datasheet for TS_CAL2 value)
• TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP
(refer to the datasheet for TS_CAL1 value)
• TS_DATA is the actual temperature sensor output value converted by ADC
Refer to the specific device datasheet for more information about TS_CAL1 and
TS_CAL2 calibration points.
For code example, refer to A.8.17: Temperature computation code example.
Note: The sensor has a startup time after waking from power down mode before it can output
VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize
the delay, the ADEN and TSEN bits should be set at the same time.

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Calculating the actual VDDA voltage using the internal reference voltage
The VDDA power supply voltage applied to the device may be subject to variation or not
precisely known. The embedded internal voltage reference (VREFINT) and its calibration
data, acquired by the ADC during the manufacturing process at VDDA_Charac, can be used to
evaluate the actual VDDA voltage level.
The following formula gives the actual VDDA voltage supplying the device:
VDDA = VDDA_Charac x VREFINT_CAL / VREFINT_DATA
Where:
• VDDA_Charac is the value of VDDA voltage characterized at VREFINT during the
manufacturing process. It is specified in the device datasheet.
• VREFINT_CAL is the VREFINT calibration value
• VREFINT_DATA is the actual VREFINT output value converted by ADC

Converting a supply-relative ADC measurement to an absolute voltage value

The ADC is designed to deliver a digital value corresponding to the ratio between the analog
power supply and the voltage applied on the converted channel. For most application use
cases, it is necessary to convert this ratio into a voltage independent of VDDA. For
applications where VDDA is known and ADC converted values are right-aligned you can use
the following formula to get this absolute value:
V DDA
V CHANNELx = ------------------------------------- × ADC_DATA x
FULL_SCALE

For applications where VDDA value is not known, you must use the internal voltage
reference and VDDA can be replaced by the expression provided in Section : Calculating the
actual VDDA voltage using the internal reference voltage, resulting in the following formula:
V DDA_Charac × VREFINT_CAL × ADC_DATA x
V CHANNELx = ----------------------------------------------------------------------------------------------------------------------
-
VREFINT_DATA × FULL_SCALE

Where:
• VDDA_Charac is the value of VDDA voltage characterized at VREFINT during the
manufacturing process. It is specified in the device datasheet.
• VREFINT_CAL is the VREFINT calibration value
• ADC_DATAx is the value measured by the ADC on channelx (right-aligned)
• VREFINT_DATA is the actual VREFINT output value converted by the ADC
• full_SCALE is the maximum digital value of the ADC output. For example with 12-bit
resolution, it is 212 - 1 = 4095 or with 8-bit resolution, 28 - 1 = 255.
Note: If ADC measurements are done using an output format other than 12 bit right-aligned, all the
parameters must first be converted to a compatible format before the calculation is done.

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13.10 ADC interrupts

An interrupt can be generated by any of the following events:
• End Of Calibration (EOCAL flag)
• ADC power-up, when the ADC is ready (ADRDY flag)
• End of any conversion (EOC flag)
• End of a sequence of conversions (EOS flag)
• When an analog watchdog detection occurs (AWD flag)
• When the end of sampling phase occurs (EOSMP flag)
• when a data overrun occurs (OVR flag)
Separate interrupt enable bits are available for flexibility.

Table 65. ADC interrupts

Interrupt event Event flag Enable control bit

End Of Calibration EOCAL EOCALIE

ADC ready ADRDY ADRDYIE
End of conversion EOC EOCIE
End of sequence of conversions EOS EOSIE
Analog watchdog status bit is set AWD AWDIE
End of sampling phase EOSMP EOSMPIE
Overrun OVR OVRIE

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13.11 ADC registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.

13.11.1 ADC interrupt and status register (ADC_ISR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. EOCAL Res. Res. Res. AWD Res. Res. OVR EOS EOC EOSMP ADRDY

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 Reserved, must be kept at reset value.
Bit 11 EOCAL: End Of Calibration flag
This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it.
0: Calibration is not complete
1: Calibration is complete
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 Reserved, must be kept at reset value.
Bit 7 AWD: Analog watchdog flag
This bit is set by hardware when the converted voltage crosses the values programmed in ADC_TR
register. It is cleared by software by programming it to 1.
0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by
software)
1: Analog watchdog event occurred
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 OVR: ADC overrun
This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete
while the EOC flag was already set. It is cleared by software writing 1 to it.
0: No overrun occurred (or the flag event was already acknowledged and cleared by software)
1: Overrun has occurred
Bit 3 EOS: End of sequence flag
This bit is set by hardware at the end of the conversion of a sequence of channels selected by the
CHSEL bits. It is cleared by software writing 1 to it.
0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by
software)
1: Conversion sequence complete

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Bit 2 EOC: End of conversion flag

This bit is set by hardware at the end of each conversion of a channel when a new data result is
available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR
register.
0: Channel conversion not complete (or the flag event was already acknowledged and cleared by
software)
1: Channel conversion complete
Bit 1 EOSMP: End of sampling flag
This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by
software by programming it to ‘1’.
0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by
software)
1: End of sampling phase reached
Bit 0 ADRDY: ADC ready
This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches
a state where it is ready to accept conversion requests.
It is cleared by software writing 1 to it.
0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared
by software)
1: ADC is ready to start conversion

13.11.2 ADC interrupt enable register (ADC_IER)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EOCAL EOSMP ADRDY
Res. Res. Res. Res. Res. Res. Res. AWDIE Res. Res. OVRIE EOSIE EOCIE
IE IE IE
rw rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 Reserved, must be kept at reset value.
Bit 11 EOCALIE: End of calibration interrupt enable
This bit is set and cleared by software to enable/disable the end of calibration interrupt.
0: End of calibration interrupt disabled
1: End of calibration interrupt enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 10 Reserved, must be kept at reset value.
Bits 9:8 Reserved, must be kept at reset value.

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Bit 7 AWDIE: Analog watchdog interrupt enable

This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Note: The Software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bits 6:5 Reserved, must be kept at reset value.
Bit 4 OVRIE: Overrun interrupt enable
This bit is set and cleared by software to enable/disable the overrun interrupt.
0: Overrun interrupt disabled
1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 3 EOSIE: End of conversion sequence interrupt enable
This bit is set and cleared by software to enable/disable the end of sequence of conversions
interrupt.
0: EOS interrupt disabled
1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 2 EOCIE: End of conversion interrupt enable
This bit is set and cleared by software to enable/disable the end of conversion interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 1 EOSMPIE: End of sampling flag interrupt enable
This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt.
0: EOSMP interrupt disabled.
1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).
Bit 0 ADRDYIE: ADC ready interrupt enable
This bit is set and cleared by software to enable/disable the ADC Ready interrupt.
0: ADRDY interrupt disabled.
1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).

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13.11.3 ADC control register (ADC_CR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADVR
ADCAL Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
EGEN
rs rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADSTA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADSTP Res. ADDIS ADEN
RT
rs rs rs rs

Bit 31 ADCAL: ADC calibration

This bit is set by software to start the calibration of the ADC.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress.
Note: The software is allowed to set ADCAL only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
The software is allowed to update the calibration factor by writing ADC_CALFACT only when
ADEN = 1 and ADSTART = 0 (ADC enabled and no conversion is ongoing).
Bits 30:29 Reserved, must be kept at reset value.
Bit 28 ADVREGEN: ADC Voltage Regulator Enable
This bit can be set:
– by software, to enable the ADC internal voltage regulator.
– by hardware, when launching the calibration (setting ADCAL = 1) or when enabling the ADC (setting
ADEN = 1)
It is cleared by software to disable the voltage regulator. It can be cleared only if ADEN is cleared.
0: ADC voltage regulator disabled
1: ADC voltage regulator enabled
Note: The software can program this bit field only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
Bits 27:5 Reserved, must be kept at reset value.
Bit 4 ADSTP: ADC stop conversion command
This bit is set by software to stop and discard an ongoing conversion (ADSTP Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to
accept a new start conversion command.
0: No ADC stop conversion command ongoing
1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress.
Note: Setting ADSTP to ‘1’ is only effective when ADSTART = 1 and ADDIS = 0 (ADC is enabled and
may be converting and there is no pending request to disable the ADC)
Bit 3 Reserved, must be kept at reset value.

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RM0377 Analog-to-digital converter (ADC)

Bit 2 ADSTART: ADC start conversion command

This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits,
a conversion either starts immediately (software trigger configuration) or once a hardware trigger
event occurs (hardware trigger configuration).
It is cleared by hardware:
– In single conversion mode (CONT = 0, DISCEN = 0), when software trigger is selected
(EXTEN = 00): at the assertion of the end of Conversion Sequence (EOS) flag.
– In discontinuous conversion mode(CONT = 0, DISCEN = 1), when the software trigger is selected
(EXTEN = 00): at the assertion of the end of Conversion (EOC) flag.
– In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is
cleared by hardware.
0: No ADC conversion is ongoing.
1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting.
Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled
and there is no pending request to disable the ADC).

Bit 1 ADDIS: ADC disable command

This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state
(OFF state).
It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at
this time).
0: No ADDIS command ongoing
1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
Note: Setting ADDIS to ‘1’ is only effective when ADEN = 1 and ADSTART = 0 (which ensures that no
conversion is ongoing)
Bit 0 ADEN: ADC enable command
This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the
ADRDY flag has been set.
It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command.
0: ADC is disabled (OFF state)
1: Write 1 to enable the ADC.
Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0,
ADSTP = 0, ADSTART = 0, ADDIS = 0 and ADEN = 0)

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13.11.4 ADC configuration register 1 (ADC_CFGR1)

Address offset: 0x0C
Reset value: 0x0000 0000
The software is allowed to program ADC_CFGR1 only when ADEN is cleared in ADC_CR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. AWDCH[4:0] Res. Res. AWDEN AWDSGL Res. Res. Res. Res. Res. DISCEN

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCAND DMAC
AUTOFF WAIT CONT OVRMOD EXTEN[1:0] Res. EXTSEL[2:0] ALIGN RES[1:0] DMAEN
IR FG
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:26 AWDCH[4:0]: Analog watchdog channel selection
These bits are set and cleared by software. They select the input channel to be guarded by
the analog watchdog.
00000: ADC analog input Channel 0 monitored by AWD
00001: ADC analog input Channel 1 monitored by AWD
.....
10001: ADC analog input Channel 17 monitored by AWD
10010: ADC analog input Channel 18 monitored by AWD
Others: Reserved
Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR
register.
The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).The software is allowed to write this bit only when ADEN
bit is cleared.
Bits 25:24 Reserved, must be kept at reset value.
Bit 23 AWDEN: Analog watchdog enable
This bit is set and cleared by software.
0: Analog watchdog disabled
1: Analog watchdog enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).The software is allowed to write this bit only when ADEN
bit is cleared.
Bit 22 AWDSGL: Enable the watchdog on a single channel or on all channels
This bit is set and cleared by software to enable the analog watchdog on the channel
identified by the AWDCH[4:0] bits or on all the channels
0: Analog watchdog enabled on all channels
1: Analog watchdog enabled on a single channel
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).The software is allowed to write this bit only when ADEN
bit is cleared.
Bits 21:17 Reserved, must be kept at reset value.

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Bit 16 DISCEN: Discontinuous mode

This bit is set and cleared by software to enable/disable discontinuous mode.
0: Discontinuous mode disabled
1: Discontinuous mode enabled
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.
The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).The software is allowed to write this bit only when ADEN
bit is cleared.
Bit 15 AUTOFF: Auto-off mode
This bit is set and cleared by software to enable/disable auto-off mode..
0: Auto-off mode disabled
1: Auto-off mode enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).The software is allowed to write this bit only when ADEN
bit is cleared.
Bit 14 WAIT: Wait conversion mode
This bit is set and cleared by software to enable/disable wait conversion mode..
0: Wait conversion mode off
1: Wait conversion mode on
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).The software is allowed to write this bit only when ADEN
bit is cleared.
Bit 13 CONT: Single / continuous conversion mode
This bit is set and cleared by software. If it is set, conversion takes place continuously until it
is cleared.
0: Single conversion mode
1: Continuous conversion mode
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both bits DISCEN = 1 and CONT = 1.
The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).The software is allowed to write this bit only when ADEN
bit is cleared.
Bit 12 OVRMOD: Overrun management mode
This bit is set and cleared by software and configure the way data overruns are managed.
0: ADC_DR register is preserved with the old data when an overrun is detected.
1: ADC_DR register is overwritten with the last conversion result when an overrun is
detected.
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).The software is allowed to write this bit only when ADEN
bit is cleared.

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Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection

These bits are set and cleared by software to select the external trigger polarity and enable
the trigger.
00: Hardware trigger detection disabled (conversions can be started by software)
01: Hardware trigger detection on the rising edge
10: Hardware trigger detection on the falling edge
11: Hardware trigger detection on both the rising and falling edges
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).The software is allowed to write this bit only when ADEN
bit is cleared.
Bit 9 Reserved, must be kept at reset value.
Bits 8:6 EXTSEL[2:0]: External trigger selection
These bits select the external event used to trigger the start of conversion (refer to Table 58:
External triggers for details):
000: TRG0
001: TRG1
010: TRG2
011: TRG3
100: TRG4
101: TRG5
110: TRG6
111: TRG7
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).The software is allowed to write this bit only when ADEN
bit is cleared.
Bit 5 ALIGN: Data alignment
This bit is set and cleared by software to select right or left alignment. Refer to Figure 42:
Data alignment and resolution (oversampling disabled: OVSE = 0) on page 297
0: Right alignment
1: Left alignment
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).The software is allowed to write this bit only when ADEN
bit is cleared.
Bits 4:3 RES[1:0]: Data resolution
These bits are written by software to select the resolution of the conversion.
00: 12 bits
01: 10 bits
10: 8 bits
11: 6 bits
Note: The software is allowed to write these bits only when ADEN is cleared.

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RM0377 Analog-to-digital converter (ADC)

Bit 2 SCANDIR: Scan sequence direction

This bit is set and cleared by software to select the direction in which the channels is scanned
in the sequence.
0: Upward scan (from CHSEL0 to CHSEL18)
1: Backward scan (from CHSEL18 to CHSEL0)
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).The software is allowed to write this bit only when ADEN
bit is cleared.

Bit 1 DMACFG: Direct memory access configuration

This bit is set and cleared by software to select between two DMA modes of operation and is
effective only when DMAEN = 1.
0: DMA one shot mode selected
1: DMA circular mode selected
For more details, refer to Section 13.5.5: Managing converted data using the DMA on
page 298
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).The software is allowed to write this bit only when ADEN
bit is cleared.
Bit 0 DMAEN: Direct memory access enable
This bit is set and cleared by software to enable the generation of DMA requests. This allows
the DMA controller to be used to manage automatically the converted data. For more details,
refer to Section 13.5.5: Managing converted data using the DMA on page 298.
0: DMA disabled
1: DMA enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures
that no conversion is ongoing).The software is allowed to write this bit only when ADEN
bit is cleared.

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13.11.5 ADC configuration register 2 (ADC_CFGR2)

Address offset: 0x10
Reset value: 0x0000 0000
The software is allowed to program ADC_CFGR2 only when ADEN is cleared in ADC_CR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CKMODE[1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. TOVS OVSS[3:0] OVSR[2:0] Res. OVSE

rw rw rw rw rw rw rw rw rw

Bits 31:30 CKMODE[1:0]: ADC clock mode

These bits are set and cleared by software to define how the analog ADC is clocked:
00: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section)
01: PCLK/2 (Synchronous clock mode)
10: PCLK/4 (Synchronous clock mode)
11: PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50%
duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
must by 50% duty cycle)
In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a
conversion.
Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
Bits 29:10 Reserved, must be kept at reset value.
Bit 9 TOVS: Triggered Oversampling
This bit is set and cleared by software.
0: All oversampled conversions for a channel are done consecutively after a trigger
1: Each oversampled conversion for a channel needs a trigger
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).The software is allowed to write this bit only when ADEN bit is cleared.
Bits 8:5 OVSS[3:0]: Oversampling shift
This bit is set and cleared by software.
0000: No shift
0001: Shift 1-bit
0010: Shift 2-bits
0011: Shift 3-bits
0100: Shift 4-bits
0101: Shift 5-bits
0110: Shift 6-bits
0111: Shift 7-bits
1000: Shift 8-bits
Others: Reserved
Note: he software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).The software is allowed to write this bit only when ADEN bit is cleared.

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Bits 4:2 OVSR[2:0]: Oversampling ratio

This bit filed defines the number of oversampling ratio.
000: 2x
001: 4x
010: 8x
011: 16x
100: 32x
101: 64x
110: 128x
111: 256x
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).The software is allowed to write this bit only when ADEN bit is cleared.
Bit 1 Reserved, must be kept at reset value.
Bit 0 OVSE: Oversampler Enable
This bit is set and cleared by software.
0: Oversampler disabled
1: Oversampler enabled
Note: The software is allowed to write this bit only when ADSTART bit is cleared (this ensures that no
conversion is ongoing).The software is allowed to write this bit only when ADEN bit is cleared.

13.11.6 ADC sampling time register (ADC_SMPR)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMP[2:0]

rw rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 SMP[2:0]: Sampling time selection
These bits are written by software to select the sampling time that applies to all channels.
000: 1.5 ADC clock cycles
001: 3.5 ADC clock cycles
010: 7.5 ADC clock cycles
011: 12.5 ADC clock cycles
100: 19.5 ADC clock cycles
101: 39.5 ADC clock cycles
110: 79.5 ADC clock cycles
111: 160.5 ADC clock cycles
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).

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13.11.7 ADC watchdog threshold register (ADC_TR)

Address offset: 0x20
Reset value: 0x0FFF 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. HT[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. LT[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT[11:0]: Analog watchdog higher threshold
These bits are written by software to define the higher threshold for the analog watchdog. Refer to
Section 13.7: Analog window watchdog (AWDEN, AWDSGL, AWDCH, ADC_TR) on page 302
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT[11:0]: Analog watchdog lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Refer to Section 13.7: Analog window watchdog (AWDEN, AWDSGL, AWDCH, ADC_TR) on
page 302.
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).

13.11.8 ADC channel selection register (ADC_CHSELR)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHSEL CHSEL CHSEL
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
18 17 16
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 CHSELx: Channel-x selection
These bits are written by software and define which channels are part of the sequence of channels
to be converted. Refer to Figure 34: ADC connectivity for ADC inputs connected to external
channels and internal sources.
0: Input Channel-x is not selected for conversion
1: Input Channel-x is selected for conversion
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing).

13.11.9 ADC data register (ADC_DR)

Address offset: 0x40
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA[15:0]

r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 DATA[15:0]: Converted data
These bits are read-only. They contain the conversion result from the last converted channel. The data
are left- or right-aligned as shown in Figure 42: Data alignment and resolution (oversampling disabled:
OVSE = 0) on page 297.
Just after a calibration is complete, DATA[6:0] contains the calibration factor.

13.11.10 ADC Calibration factor (ADC_CALFACT)

Address offset: 0xB4
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. CALFACT[6:0]

rw rw rw rw rw rw rw

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Bits 31:7 Reserved, must be kept at reset value.

Bits 6:0 CALFACT[6:0]: Calibration factor
These bits are written by hardware or by software.
– Once a single-ended inputs calibration is complete, they are updated by hardware with the
calibration factors.
– Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it is then applied once a new single-ended
conversion is launched.
– Just after a calibration is complete, DATA[6:0] contains the calibration factor.
Note: Software can write these bits only when ADEN=1 and ADSTART=0 (ADC is enabled and no
calibration is ongoing and no conversion is ongoing).

13.11.11 ADC common configuration register (ADC_CCR)

Address offset: 0x308
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VREF
Res. Res. Res. Res. Res. Res. LFMEN Res. TSEN PRESC[3:0] Res. Res.
EN
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 LFMEN: Low Frequency Mode enable
This bit is set and cleared by software to enable/disable the Low Frequency Mode.
It is mandatory to enable this mode the user selects an ADC clock frequency lower than 3.5 MHz
0: Low Frequency Mode disabled
1: Low Frequency Mode enabled
Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no
conversion is ongoing.
Bit 24 Reserved, must be kept at reset value.
Bit 23 TSEN: Temperature sensor enable
This bit is set and cleared by software to enable/disable the temperature sensor.
0: Temperature sensor disabled
1: Temperature sensor enabled
Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion
is ongoing).

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Bit 22 VREFEN: VREFINT enable

This bit is set and cleared by software to enable/disable the VREFINT.
0: VREFINT disabled
1: VREFINT enabled
Note: Software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion
is ongoing).
Bits 21:18 PRESC[3:0]: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADC. The clock is common for
all the ADCs.
0000: input ADC clock not divided
0001: input ADC clock divided by 2
0010: input ADC clock divided by 4
0011: input ADC clock divided by 6
0100: input ADC clock divided by 8
0101: input ADC clock divided by 10
0110: input ADC clock divided by 12
0111: input ADC clock divided by 16
1000: input ADC clock divided by 32
1001: input ADC clock divided by 64
1010: input ADC clock divided by 128
1011: input ADC clock divided by 256
Other: Reserved
Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL = 0,
ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).
Bits 17:0 Reserved, must be kept at reset value.

13.12 ADC register map

The following table summarizes the ADC registers.

Table 66. ADC register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
EOSMP
ADRDY
EOCAL

AWD

OVR

EOC
EOS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

Res.
Res.

ADC_ISR
0x00

Reset value 0 0 0 0 0 0 0
EOSMPIE
ADRDYIE
EOCALIE

AWDIE

OVRIE

EOCIE
EOSIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

Res.
Res.

ADC_IER
0x04

Reset value 0 0 0 0 0 0 0
ADVREGEN

ADSTART
ADCAL

ADSTP

ADDIS
ADEN
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

ADC_CR
0x08

Reset value 0 0 0 0 0 0
EXTEN[1:0]
OVRMOD

SCANDIR
DMACFG
AWDSGL

AUTOFF
DISCEN
AWDEN

DMAEN
ALIGN
CONT

EXTSEL RES
WAIT
Res.

Res.
Res.

Res.
Res.
Res.
Res.
Res.

Res.

ADC_CFGR1 AWDCH[4:0]
0x0C [2:0] [1:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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 ...
...
...
0x40
0x38
0x34
0x30
0x28
0x24
0x20
0x18
0x14
0x10

0xB4
0x3C
0x2C
0x1C

0x308
Offset

328/905
ADC_TR

ADC_DR

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

ADC_CCR
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

ADC_SMPR
ADC_CFGR2

ADC_CHSELR

ADC_CALFACT
0
Res. Res. Res. Res. Res. Res. 31
CKMODE[1:0]

0
Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res 29
Res. Res. Res. Res. Res. Res. Res. 28

1
Res. Res. Res. Res. Res. Res. 27

1
Res. Res. Res. Res. Res. Res. 26
Analog-to-digital converter (ADC)

0
1
LFMEN Res. Res. Res. Res. Res. 25

1
Res. Res. Res. Res. Res. Res. 24

0
TSEN Res. Res. Res. 1 Res. Res. 23

0
1
VREFEN Res. Res. Res. Res. Res. 22

0
1

PRESC3 Res. Res. Res. Res. Res. 21

HT[11:0]

0
1

PRESC2 Res. Res. Res. Res. Res. 20

0
1

PRESC1 Res. Res. Res. Res. Res. 19

0
1

PRESC0 Res. Res. 0 CHSEL18 Res. Res.

0
18
Res. Res. Res. CHSEL17 Res. Res.

RM0377 Rev 10
17
1 1

Res. Res. Res. CHSEL16 Res. Res. 16

0

Res. Res. CHSEL15 Res. Res. Res. 15

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

0 0
0

Res. Res. CHSEL14 Res. Res. Res. 14

0
0

Res. Res. CHSEL13 Res. Res. Res. 13

0
0

Res. Res. 0 CHSEL12 Res. Res. Res. 12

0
0

Res. Res. CHSEL11 Res. Res. 11

0
0
0

Res. Res. CHSEL10 Res. Res. 10

0
0
0
0

Res. Res. CHSEL9 Res. TOVS 9

Refer to Section 2.2 on page 51 for the register boundary addresses.

0
0
0
0

Res. Res. CHSEL8 Res.

Table 66. ADC register map and reset values (continued)

8
0
0
0
0

Res. Res. CHSEL7 Res. 7

OVSS[3:0]
DATA[15:0]
0
0

0
0
0

Res. CHSEL6 Res. 6

0
0

0
0
0

Res. CHSEL5 Res. 5

LT[11:0]

0
0

0
0
0

Res. CHSEL4 Res. 4

0

0
0
0
0

Res. CHSEL3 Res. OVSR[2:0] 3

0

0
0
0
0

Res. CHSEL2 2
CALFACT[6:0]
0

0
0
0

Res. CHSEL1 Res. 1

[2:0]
SMP

OVSE
0

0
0
0
0 0 0
0 0

Res. CHSEL0 0
RM0377
RM0377 Comparator (COMP)

14 Comparator (COMP)

14.1 Introduction
STM32L0x1 devices embed two ultra-low-power comparators COMP1, and COMP2 that
can be used either as standalone devices (all terminal are available on I/Os) or combined
with the timers.
The comparators can be used for a variety of functions including:
• Wakeup from low-power mode triggered by an analog signal,
• Analog signal conditioning,
• Cycle-by-cycle current control loop when combined with a PWM output from a timer.

14.2 COMP main features

• COMP1 comparator with ultra low consumption
• COMP2 comparator with rail-to-rail inputs, fast or slow mode
• Each comparator has positive and configurable negative inputs used for flexible voltage
selection:
– I/O pins
– Internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by
scaler (buffered voltage divider)
• Programmable speed / consumption (COMP2 only)
• The outputs can be redirected to an I/O or to timer inputs for triggering:
– Capture events
• COMP1, and COMP2 can be combined in a window comparator. Each comparator has
interrupt generation capability with wakeup from Sleep and Stop modes (through the
EXTI controller)

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14.3 COMP functional description

14.3.1 COMP block diagram

The block diagram of the comparators is shown in Figure 56: Comparator 1 and 2 block
diagrams.

Figure 56. Comparator 1 and 2 block diagrams

COMP1INNSEL COMP1

VREFINT
PA0 COMP1POLARITY
PA4 - Wakeup
PA5 EXTI line 21
GPIOx
PA1 ++ COMP1VALUE
TIM2_ETR
TIM2_CH4
COMP1WM TIM21_ETR
TIM21_CH2
TIM22_ETR
COMP2INPSEL
COMP2 TIM22_CH1
PA3 LPTIM_ETR
COMP2INNSEL PA7 (1)
LPTIM_CH2
PB4
PB5 + COMP2POLARITY Wakeup
VREFINT
PA2 PB6 EXTI line 22
PA4 PB7 GPIOx
VREFINT Scaler -
PA5 COMP2VALUE
¼ VREFINT
½ VREFINT TIM2_ETR
¾ VREFINT TIM2_CH4
PB3 TIM21_ETR
TIM21_CH2
ENBUF_ TIM22_ETR
VREFINT TIM22_CH1
_COMP2 LPTIM_ETR
LPTIM_CH2

MSv34753V3

1. Available on category 1 devices only.

14.3.2 COMP pins and internal signals

The I/Os used as comparators inputs must be configured in analog mode in the GPIOs
registers.
The comparator output can be connected to the I/Os using the alternate function channel
given in “Alternate function mapping” table in the datasheet.
The output can also be internally redirected to a variety of timer input for the following
purposes:
• Input capture for timing measures
It is possible to have the comparator output simultaneously redirected internally and
externally.

330/905 RM0377 Rev 10

RM0377 Comparator (COMP)

14.3.3 COMP reset and clocks

The COMP clock provided by the clock controller is synchronous with the PCLK (APB
clock).
There is no clock enable control bit provided in the RCC controller. Reset and clock enable
bits are common for COMP and SYSCFG.
Important: The polarity selection logic and the output redirection to the port works
independently from the PCLK clock. This allows the comparator to work even in Stop mode.

14.3.4 Comparator LOCK mechanism

The comparators can be used for safety purposes, such as over-current or thermal
protection. For applications having specific functional safety requirements, it is necessary to
insure that the comparator programming cannot be altered in case of spurious register
access or program counter corruption.
For this purpose, the comparator control and status registers can be write-protected (read-
only).
Once the programming is completed, the COMPx LOCK bit can be set to 1. This causes the
whole COMPx_CSR register to become read-only, including the COMPx LOCK bit.
The write protection can only be reset by a MCU reset.

14.3.5 Power mode

COMP2 power consumption versus propagation delay can be adjusted to have the optimum
trade-off for a given application.
COMP2_SPEED bit in the COMP2_CSR register can be programmed to provide either
higher speed/consumption or lower speed/consumption.

14.4 COMP interrupts

The comparator outputs are internally connected to the Extended interrupts and events
controller. Each comparator has its own EXTI line and can generate either interrupts or
events. The same mechanism is used to exit from low-power modes.
Refer to Interrupt and events section for more details.

14.5 COMP registers

14.5.1 Comparator 1 control and status register (COMP1_CSR)
The COMP1_CSR is the Comparator1 control/status register. It contains all the bits /flags
related to comparator1.
Address offset: 0x18
System reset value: 0x0000 0000

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Comparator (COMP) RM0377

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP1 COMP1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LOCK VALUE
rs r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP1 COMP1 COMP1 COMP1INN COMP1
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
POLARITY LPTIMIN1 WM SEL EN
rw rw rw rw rw rw

Bit 31 COMP1LOCK: COMP1_CSR register lock bit

This bit is set by software and cleared by a hardware system reset. It locks the whole
content of the comparator 1 control register, COMP1_CSR[31:0]
0: COMP1_CSR[31:0] for comparator 1 are read/write
1: COMP1_CSR[31:0] for comparator 1 are read-only
Bit 30 COMP1VALUE: Comparator 1 output status bit
This bit is read-only. It reflects the current comparator 1 output taking into account
COMP1POLARITY bit effect.
Bits 29:16 Reserved, must be kept at reset value
Bit 15 COMP1POLARITY: Comparator 1 polarity selection bit
This bit is set and cleared by software (only if COMP1LOCK not set). It inverts Comparator
1 polarity.
0: Comparator 1 output value not inverted
1: Comparator 1output value inverted
Bits 14:13 Reserved, must be kept at reset value
Bit 12 COMP1LPTIMIN1: Comparator 1 LPTIM input propagation bit
This bit is set and cleared by software (assuming COMP1LOCK not set). It sends
COMP1VALUE to LPTIM input 1.
0: Comparator 1 output gated
1: Comparator 1 output sent to LPTIM input 1
Bits 11:9 Reserved, must be kept at reset value
Bit 8 COMP1WM: Comparator 1 window mode selection bit
This bit is set and cleared by software (only if COMP1LOCK not set). It selects comparator
1 window mode where the Plus inputs of both comparators are connected together.
0: Plus input of comparator 1 connected to PA1.
1: Plus input of comparator 1 shorted with Plus input of comparator 2 (see COMP1_CSR).
Bits 7:6 Reserved, must be kept at reset value

332/905 RM0377 Rev 10

RM0377 Comparator (COMP)

Bits 5:4 COMP1INNSEL: Comparator 1 Input Minus connection configuration bit

These bits are set and cleared by software (only if COMP1LOCK not set). They select which
input is connected with the Input Minus of comparator 1
00: VREFINT
01: PA0
10: PA4
11: PA5
Bits 3:1 Reserved, must be kept at reset value
Bit 0 COMP1EN: Comparator 1 enable bit
This bit is set and cleared by software (only if COMP1LOCK not set). It switches
oncomparator1
0: Comparator 1 switched OFF.
1: Comparator 1 switched ON.

14.5.2 Comparator 2 control and status register (COMP2_CSR)

The COMP2_CSR is the Comparator2 control/status register. It contains all the bits /flags
related to comparator2.
Address offset: 0x1C
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COMP2 COMP2
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
LOCK VALUE
rs r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMP2 COMP2 COMP2 COMP2 COMP2
Res. Res. COMP2INPSEL Res. COMP2INNSEL Res. Res.
POLARITY LPTIMIN1 LPTIMIN2 SPEED EN
rw rw rw rw rw rw rw rw rw rw rw

Bit 31 COMP2LOCK: COMP2_CSR register lock bit

This bit is set by software and cleared by a hardware system reset. It locks the whole
content of the comparator 2 control register, COMP2_CSR[31:0]
0: COMP2_CSR[31:0] for comparator 1 are read/write
1: COMP2_CSR[31:0] for comparator 1 are read-only
Bit 30 COMP2VALUE: Comparator 2 output status bit
This bit is read-only. It reflects the current comparator 2 output taking into account
COMP2POLARITY bit effect.
Bits 29:16 Reserved, must be kept at reset value
Bit 15 COMP2POLARITY: Comparator 2 polarity selection bit
This bit is set and cleared by software (only if COMP2LOCK not set). It inverts Comparator
1 polarity.
0: Comparator 2 output value not inverted
1: Comparator 2 output value inverted
Bit 14 Reserved, must be kept at reset value

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Comparator (COMP) RM0377

Bit 13 COMP2LPTIMIN1: Comparator 2 LPTIM input 1 propagation bit

This bit is set and cleared by software (assuming COMP2LOCK not set). It sends
COMP2VALUE to LPTIM input 1.
0: Comparator 2 output gated
1: Comparator 2 output sent to LPTIM input 1
Note: COMP2LPTIMIN1 and COMP2LPTIMIN2 cannot both be set to ‘1’.
Bit 12 COMP2LPTIMIN2: Comparator 2 LPTIM input 2 propagation bit
This bit is set and cleared by software (assuming COMP2LOCK not set). It sends
COMP2VALUE to LPTIM input 2.
0: Comparator 2 output gated
1: Comparator 2 output sent to LPTIM input 2
Note: COMP2LPTIMIN1 and COMP2LPTIMIN2 cannot both be set to ‘1’.
Bit 11 Reserved, must be kept at reset value
Bits 10:8 COMP2INPSEL: Comparator 2 Input Plus connection configuration bit
These bits are set and cleared by software (only if COMP2LOCK not set). They select which
input is connected with the Input Plus of comparator 2
000: PA3
001: PB4
010: PB5
011: PB6
100: PB7
101: PA7 (for category 1 devices only)
Others: Reserved.
Bit 7 Reserved, must be kept at reset value
Bits 6:4 COMP2INNSEL: Comparator 2 Input Minus connection configuration bit
These bits are set and cleared by software (only if COMP2LOCK not set). They select which
input is connected with the Input Minus of comparator 2.
000: VREFINT
001: PA2
010: PA4
011: PA5
100: 1/4 VREFINT
101: 1/2 VREFINT
110: 3/4 VREFINT
111: PB3
Note: If VREFINT or a fraction of VREFINT (using the scaler) is selected, then EN_VREFINT
bit must be set in the SYSCFG_CFGR3 register (see Section 9.2.3: Reference control
and status register (SYSCFG_CFGR3)).

334/905 RM0377 Rev 10

RM0377 Comparator (COMP)

Bit 3 COMP2SPEED: Comparator 2 power mode selection bit

This bit is set and cleared by software (only if COMP2LOCK not set). It selects comparator
2 power mode.
0: slow speed
1: fast speed
Bits 2:1 Reserved, must be kept at reset value
Bit 0 COMP2EN: Comparator 2 enable bit
This bit is set and cleared by software (only if COMP2LOCK not set). It switches
oncomparator2.
0: Comparator 2 switched off.
1: Comparator 2 switched ON.

RM0377 Rev 10 335/905

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 0x18

0x1C
Offset

336/905
14.5.3

Register

Reset value
Reset value

COMP2_CSR
COMP1_CSR

0
0
COMP2LOCK COMP1LOCK 31
Comparator (COMP)

0
0
COMP2VALUE COMP1VALUE 30
Res. Res. 29
Res. Res. 28
Res. Res. 27
Res. Res. 26
Res. Res. 25
COMP register map

Res. Res. 24
Res. Res. 23
Res. Res. 22
Res. Res. 21
Res. Res. 20
Res. Res. 19
Res. Res. 18
Res. Res. 17

RM0377 Rev 10
Res. Res. 16
0
0

COMP2POLARITY COMP1POLARITY 15
Res. Res. 14
0

COMP2LPTIMIN1 Res. 13
The following table summarizes the comparator registers.

0
0

COMP2LPTIMIN2 COMP1LPTIMIN1 12
Res. Res. 11
Table 67. COMP register map and reset values

Res. 10
0

COMP2INPSEL Res. 9
Refer to Section 2.2 on page 51 for the register boundary addresses.
0
0

COMP1WM 8
Res. Res. 7
0

Res. 6
0
0

COMP2INNSEL 5
COMP1INNSEL
0
0

4
0

COMP2SPEED Res. 3
Res. Res. 2
Res. Res. 1
0
0

COMP2EN COMP1EN 0
RM0377
RM0377 AES hardware accelerator (AES)

15 AES hardware accelerator (AES)

15.1 Introduction
The AES hardware accelerator (AES) encrypts or decrypts data, using an algorithm and
implementation fully compliant with the advanced encryption standard (AES) defined in
Federal information processing standards (FIPS) publication 197.
Multiple chaining modes are supported (ECB, CBC, CTR), for key size of 128 bits.
The AES accelerator is a 32-bit AHB peripheral. It supports DMA single transfers for
incoming and outgoing data (two DMA channels required).
The AES peripheral provides hardware acceleration to AES cryptographic algorithms
packaged in STM32 cryptographic library.
AES is an AMBA AHB slave peripheral, accessible through 32-bit word single accesses only
(otherwise an AHB bus error is generated and write accesses are ignored).

15.2 AES main features

• Compliance with NIST “Advanced encryption standard (AES), FIPS publication 197”
from November 2001
• 128-bit data block processing
• Support for cipher key length of 128-bit
• Encryption and decryption with multiple chaining modes:
– Electronic codebook (ECB) mode
– Cipher block chaining (CBC) mode
– Counter (CTR) mode
• 213 clock cycle latency for processing one 128-bit block of data
• Integrated key scheduler with its key derivation stage (ECB or CBC decryption only)
• AMBA AHB slave peripheral, accessible through 32-bit word single accesses only
• 128-bit register for storing the cryptographic key (four 32-bit registers)
• 128-bit register for storing initialization vector (four 32-bit registers)
– Used for the initialization vector when AES is configured in CBC mode or for the
32-bit counter initialization when CTR mode is selected
• 32-bit buffer for data input and output
• Automatic data flow control with support of single-transfer direct memory access (DMA)
using two channels (one for incoming data, one for processed data)
• Data-swapping logic to support 1-, 8-, 16- or 32-bit data

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AES hardware accelerator (AES) RM0377

15.3 AES implementation

The device has a single instance of AES peripheral.

15.4 AES functional description

15.4.1 AES block diagram

Figure 57 shows the block diagram of AES.

Figure 57. AES block diagram

AES
32-bit
access Banked registers

32-bit key AES_KEYRx KEY

AHB bus IV, counter AES_IVRx IVI
AHB status AES_SR
interface
control AES_CR AES
swap Core
aes_hclk
data in AES_DINR DIN (AEA)
data out AES_DOUTR DOUT

aes_in_dma DMA
aes_out_dma interface Control Logic

IRQ
aes_it
interface

MSv42155V1

15.4.2 AES internal signals

Table 68 describes the user relevant internal signals interfacing the AES peripheral.

Table 68. AES internal input/output signals

Signal name Signal type Description

aes_hclk digital input AHB bus clock

aes_it digital output AES interrupt request
digital
aes_in_dma Input DMA single request/acknowledge
input/output
digital
aes_out_dma Output DMA single request/acknowledge
input/output

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RM0377 AES hardware accelerator (AES)

15.4.3 AES cryptographic core

Overview
The AES cryptographic core consists of the following components:
• AES algorithm (AEA)
• key input
• initialization vector (IV) input
The AES core works on 128-bit data blocks (four words) with 128-bit key length. Depending
on the chaining mode, the AES requires zero or one 96-bit initialization vector IV (and a 32-
bit counter field).
The AES features the following modes of operation:
• Mode 1:
Plaintext encryption using a key stored in the AES_KEYRx registers
• Mode 2:
ECB or CBC decryption key preparation. It must be used prior to selecting Mode 3 with
ECB or CBC chaining modes. The key prepared for decryption is stored automatically
in the AES_KEYRx registers. Now the AES peripheral is ready to switch to Mode 3 for
executing data decryption.
• Mode 3:
Ciphertext decryption using a key stored in the AES_KEYRx registers. When ECB and
CBC chaining modes are selected, the key must be prepared beforehand, through
Mode 2.
• Mode 4:
ECB or CBC ciphertext single decryption using the key stored in the AES_KEYRx
registers (the initial key is derived automatically).
Note: Mode 2 and mode 4 are only used when performing ECB and CBC decryption.
When Mode 4 is selected only one decryption can be done, therefore usage of Mode 2 and
Mode 3 is recommended instead.
The operating mode is selected by programming the MODE[1:0] bitfield of the AES_CR
register. It may be done only when the AES peripheral is disabled.

Typical data processing

Typical usage of the AES is described in Section 15.4.4: AES procedure to perform a cipher
operation on page 342.
Note: The outputs of the intermediate AEA stages are never revealed outside the cryptographic
boundary, with the exclusion of the IVI bitfield.

Chaining modes
The following chaining modes are supported by AES, selected through the CHMOD[1:0]
bitfield of the AES_CR register:
• Electronic code book (ECB)
• Cipher block chaining (CBC)
• Counter (CTR)

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Note: The chaining mode may be changed only when AES is disabled (bit EN of the AES_CR
register set).
Principle of each AES chaining mode is provided in the following subsections.
Detailed information is in dedicated sections, starting from Section 15.4.8: AES basic
chaining modes (ECB, CBC).

Electronic codebook (ECB) mode

Figure 58. ECB encryption and decryption principle

Encryption
Plaintext block 1 Plaintext block 2 Plaintext block 3

key key key

Encrypt Encrypt Encrypt

Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

Decryption
Plaintext block 1 Plaintext block 2 Plaintext block 3

Legend key key key

Decrypt Decrypt Decrypt
input

output
key
scheduling Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

MSv42140V1

ECB is the simplest mode of operation. There are no chaining operations, and no special
initialization stage. The message is divided into blocks and each block is encrypted or
decrypted separately.
Note: For decryption, a special key scheduling is required before processing the first block.

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RM0377 AES hardware accelerator (AES)

Cipher block chaining (CBC) mode

Figure 59. CBC encryption and decryption principle

Encryption
Plaintext block 1 Plaintext block 2 Plaintext block 3

initialization
vector

key key key

Encrypt Encrypt Encrypt

Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

Decryption
Plaintext block 1 Plaintext block 2 Plaintext block 3
initialization
vector
Legend key key key
Decrypt Decrypt Decrypt
input

output
key
scheduling Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

MSv42141V1

In CBC mode the output of each block chains with the input of the following block. To make
each message unique, an initialization vector is used during the first block processing.
Note: For decryption, a special key scheduling is required before processing the first block.

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Counter (CTR) mode

Figure 60. CTR encryption and decryption principle

Encryption
Counter +1 Counter +1 Counter

value value + 1 value + 2

key key key

Encrypt Encrypt Encrypt

Plaintext block 1 Plaintext block 2 Plaintext block 3

Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

Decryption
Counter +1 Counter +1 Counter

value value + 1 value + 2

Legend key key key

Decrypt Decrypt Decrypt
input

output
Plaintext block 1 Plaintext block 2 Plaintext block 3
XOR
Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

MSv42142V1

The CTR mode uses the AES core to generate a key stream. The keys are then XORed
with the plaintext to obtain the ciphertext as specified in NIST Special Publication 800-38A,
Recommendation for Block Cipher Modes of Operation.
Note: Unlike with ECB and CBC modes, no key scheduling is required for the CTR decryption,
since in this chaining scheme the AES core is always used in encryption mode for producing
the key stream, or counter blocks.

15.4.4 AES procedure to perform a cipher operation

Introduction
A typical cipher operation is explained below. Detailed information is provided in sections
starting from Section 15.4.8: AES basic chaining modes (ECB, CBC).
The flowcharts shown in Figure 61 describe the way STM32 cryptographic library
implements the AES algorithm. AES accelerates the execution of the AES-128
cryptographic algorithm in ECB, CBC, and CTR operating modes.
Note: For more details on the cryptographic library, refer to the UM1924 user manual “STM32
crypto library” available from www.st.com.

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RM0377 AES hardware accelerator (AES)

Figure 61. STM32 cryptolib AES flowchart example

Encryption Decryption
Begin Begin

AES_x encrypt init AES_x decrypt init

Error status Error status

success success

AES_x encrypt AES_x decrypt

append append

Data to append Data to append

Error status Error status

success success

AES_x encrypt finish/ AES_x decrypt finish/

final final

Error status Error status

success success

End End
MSv42146V1

Initialization of AES
To initialize AES, first disable it by clearing the EN bit of the AES_CR register. Then perform
the following steps in any order:
• Configure the AES mode, by programming the MODE[1:0] bitfield of the AES_CR
register.
– For encryption, Mode 1 must be selected (MODE[1:0] = 00).
– For decryption, Mode 3 must be selected (MODE[1:0] = 10), unless ECB or CBC
chaining modes are used. In this latter case, an initial key derivation of the
encryption key must be performed, as described in Section 15.4.5: AES
decryption key preparation.
• Select the chaining mode, by programming the CHMOD[1:0] bitfield of the AES_CR
register
• Write a symmetric key into the AES_KEYRx registers .
• Configure the data type (1-, 8-, 16- or 32-bit), with the DATATYPE[1:0] bitfield in the
AES_CR register.
• When it is required (for example in CBC or CTR chaining modes), write the initialization
vectors into the AES_IVRx register.

Data append
This section describes different ways of appending data for processing, where the size of
data to process is not a multiple of 128 bits.

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For ECB or CBC mode, refer to Section 15.4.6: AES ciphertext stealing and data padding.
The second-last and the last block management in these cases is more complex than in the
sequence described in this section.
Data append through polling
This method uses flag polling to control the data append.
For all other cases, the data is appended through the following sequence:
1. Enable the AES peripheral by setting the EN bit of the AES_CR register.
2. Repeat the following sub-sequence until the payload is entirely processed:
a) Write four input data words into the AES_DINR register.
b) Wait until the status flag CCF is set in the AES_SR, then read the four data words
from the AES_DOUTR register.
c) Clear the CCF flag, by setting the CCFC bit of the AES_CR register.
d) If the data block just processed is the second-last block of the message and the
significant data in the last block to process is inferior to 128 bits, pad the
remainder of the last block with zeros
3. Discard the data that is not part of the payload, then disable the AES peripheral by
clearing the EN bit of the AES_CR register.
Note: Up to three wait cycles are automatically inserted between two consecutive writes to the
AES_DINR register, to allow sending the key to the AES processor.
Data append using interrupt
The method uses interrupt from the AES peripheral to control the data append, through the
following sequence:
1. Enable interrupts from AES by setting the CCFIE bit of the AES_CR register.
2. Enable the AES peripheral by setting the EN bit of the AES_CR register.
3. Write first four input data words into the AES_DINR register.
4. Handle the data in the AES interrupt service routine, upon interrupt:
a) Read four output data words from the AES_DOUTR register.
b) Clear the CCF flag and thus the pending interrupt, by setting the CCFC bit of the
AES_CR register
c) If the data block just processed is the second-last block of an message and the
significant data in the last block to process is inferior to 128 bits, pad the
remainder of the last block with zeros. Then proceed with point 4e).
d) If the data block just processed is the last block of the message, discard the data
that is not part of the payload, then disable the AES peripheral by clearing the EN
bit of the AES_CR register and quit the interrupt service routine.
e) Write next four input data words into the AES_DINR register and quit the interrupt
service routine.
Note: AES is tolerant of delays between consecutive read or write operations, which allows, for
example, an interrupt from another peripheral to be served between two AES computations.
Data append using DMA
With this method, all the transfers and processing are managed by DMA and AES. To use
the method, proceed as follows:

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1. Prepare the last four-word data block (if the data to process does not fill it completely),
by padding the remainder of the block with zeros.
2. Configure the DMA controller so as to transfer the data to process from the memory to
the AES peripheral input and the processed data from the AES peripheral output to the
memory, as described in Section 15.4.13: AES DMA interface. Configure the DMA
controller so as to generate an interrupt on transfer completion.
3. Enable the AES peripheral by setting the EN bit of the AES_CR register
4. Enable DMA requests by setting the DMAINEN and DMAOUTEN bits of the AES_CR
register.
5. Upon DMA interrupt indicating the transfer completion, get the AES-processed data
from the memory.
Note: The CCF flag has no use with this method, because the reading of the AES_DOUTR
register is managed by DMA automatically, without any software action, at the end of the
computation phase.

15.4.5 AES decryption key preparation

For an ECB or CBC decryption, a key for the first round of decryption must be derived from
the key of the last round of encryption. This is why a complete key schedule of encryption is
required before performing the decryption. This key preparation is not required for AES
decryption in modes other than ECB or CBC.
Recommended method is to select the Mode 2 by setting to 01 the MODE[1:0] bitfield of the
AES_CR (key process only), then proceed with the decryption by setting MODE[1:0] to 10
(Mode 3, decryption only). Mode 2 usage is described below:
1. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
2. Select Mode 2 by setting to 01 the MODE[1:0] bitfield of the AES_CR. The
CHMOD[1:0] bitfield is not significant in this case because this key derivation mode is
independent of the chaining algorithm selected.
3. Write the AES_KEYRx registers (128bits) with encryption key, as shown in Figure 62.
Writes to the AES_IVRx registers have no effect.
4. Enable the AES peripheral, by setting the EN bit of the AES_CR register.
5. Wait until the CCF flag is set in the AES_SR register.
6. Derived key is available in AES core, ready to use for decryption. Application can also
read the AES_KEYRx register to obtain the derived key if needed, as shown in
Figure 62 (the processed key is loaded automatically into the AES_KEYRx registers).
Note: The AES is disabled by hardware when the derivation key is available.
To restart a derivation key computation, repeat steps 3, 4, 5 and 6 .

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Figure 62. Encryption key derivation for ECB/CBC decryption (Mode 2)

WR WR WR WR RD RD RD RD
Wait until flag CCF = 1
EK3 EK2 EK1 EK0 DK3 DK2 DK1 DK0
MSB LSB MSB LSB

Input phase Output phase (optional)

4 write operations into Computation phase 4 read operations of
AES_KEYRx[31:0] AES_KEYRx[31:0]

EN = 1 into AES_CR 128-bit derivation key

stored into AES_KEYRx
EK = encryption key = 4 words (EK3, … , EK0)
DK = decryption key = 4 words (DK3, … , DK0)
MS18937V2

If the software stores the initial key prepared for decryption, it is enough to do the key
schedule operation only once for all the data to be decrypted with a given cipher key.
Note: Alternative key preparation is to select Mode 4 by setting to 11 the MODE[1:0] bitfield of the
AES_CR register. In this case Mode 3 cannot be used.

15.4.6 AES ciphertext stealing and data padding

When using AES in ECB or CBC modes to manage messages the size of which is not a
multiple of the block size (128 bits), ciphertext stealing techniques are used, such as those
described in NIST Special Publication 800-38A, Recommendation for Block Cipher Modes
of Operation: Three Variants of Ciphertext Stealing for CBC Mode. Since the AES peripheral
on the device does not support such techniques, the last two blocks of input data must be
handled in a special way by the application.
Note: Ciphertext stealing techniques are not documented in this reference manual.
Similarly, when AES is used in other modes than ECB or CBC, an incomplete input data
block (that is, block with input data shorter than 128 bits) must be padded with zeros prior to
encryption (that is, extra bits must be appended to the trailing end of the data string). After
decryption, the extra bits must be discarded. As AES does not implement automatic data
padding operation to the last block, the application must follow the recommendation given
in Section 15.4.4: AES procedure to perform a cipher operation on page 342 to manage
messages the size of which is not a multiple of 128 bits.
Note: Padding data are swapped in a similar way as normal data, according to the
DATATYPE[1:0] field of the AES_CR register (see Section 15.4.10: AES data registers and
data swapping on page 355 for details).

15.4.7 AES task suspend and resume

A message can be suspended if another message with a higher priority must be processed.
When this highest priority message is sent, the suspended message can resume in both
encryption or decryption mode.
Suspend/resume operations do not break the chaining operation and the message
processing can resume as soon as AES is enabled again to receive the next data block.
Figure 63 gives an example of suspend/resume operation: Message 1 is suspended in
order to send a shorter and higher-priority Message 2.

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Figure 63. Example of suspend mode management

Message 1 Message 2

128-bit block 1

New higher-priority 128-bit block 2

message 2 to be
AES suspend
processed
sequence
128-bit block 3

128-bit block 1

128-bit block 2
128-bit block 4

AES resume
128-bit block 5
sequence

128-bit block 6

...
MSv42148V1

A detailed description of suspend/resume operations is in the sections dedicated to each

AES mode.

15.4.8 AES basic chaining modes (ECB, CBC)

Overview
This section gives a brief explanation of the four basic operation modes provided by the
AES computing core: ECB encryption, ECB decryption, CBC encryption and CBC
decryption. For detailed information, refer to the FIPS publication 197 from November 26,
2001.
Figure 64 illustrates the electronic codebook (ECB) encryption.

Figure 64. ECB encryption

Block 1 Block 2
AES_DINR (plaintext P1) AES_DINR (plaintext P2)

DATATYPE[1:0] Swap DATATYPE[1:0] Swap

management management
I1 I2
AES_KEYRx (KEY) AES_KEYRx (KEY)
Encrypt Encrypt

O1 O2
Legend Swap AES core Swap
DATATYPE[1:0] management DATATYPE[1:0] management
input

output AES_DOUTR (ciphertext C1) AES_DOUTR (ciphertext C2)

MSv19105V2

In ECB encrypt mode, the 128-bit plaintext input data block Px in the AES_DINR register
first goes through bit/byte/half-word swapping. The swap result Ix is processed with the AES
core set in encrypt mode, using a 128--bit key. The encryption result Ox goes through
bit/byte/half-word swapping, then is stored in the AES_DOUTR register as 128-bit ciphertext

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output data block Cx. The ECB encryption continues in this way until the last complete
plaintext block is encrypted.
Figure 65 illustrates the electronic codebook (ECB) decryption.

Figure 65. ECB decryption

Block 1 Block 2
AES_DINR (ciphertext C1) AES_DINR (ciphertext C2)

DATATYPE[1:0] Swap DATATYPE[1:0] Swap

management management
I1 I2
AES_KEYRx (KEY) AES_KEYRx (KEY)
Decrypt Decrypt

O1 O2
Legend Swap Swap
DATATYPE[1:0] management DATATYPE[1:0] management
input

output
AES_DOUTR (plaintext P1) AES_DOUTR (plaintext P2)
MSv19106V2

To perform an AES decryption in the ECB mode, the secret key has to be prepared by
collecting the last-round encryption key (which requires to first execute the complete key
schedule for encryption), and using it as the first-round key for the decryption of the
ciphertext. This preparation is supported by the AES core.
In ECB decrypt mode, the 128-bit ciphertext input data block C1 in the AES_DINR register
first goes through bit/byte/half-word swapping. The keying sequence is reversed compared
to that of the ECB encryption. The swap result I1 is processed with the AES core set in
decrypt mode, using the formerly prepared decryption key. The decryption result goes
through bit/byte/half-word swapping, then is stored in the AES_DOUTR register as 128-bit
plaintext output data block P1. The ECB decryption continues in this way until the last
complete ciphertext block is decrypted.
Figure 66 illustrates the cipher block chaining (CBC) encryption mode.

Figure 66. CBC encryption

Block 1 Block 2
AES_DINR (plaintext P1) AES_DINR (plaintext P2)

DATATYPE[1:0] Swap DATATYPE[1:0] Swap

management management
AES_IVRx (init. vector)
P1' P2'
IVI
I1 I2
AES_KEYRx (KEY) AES_KEYRx (KEY)
Block cipher Block cipher
encryption encryption
O1 O2
Legend
DATATYPE[1:0] Swap DATATYPE[1:0] Swap
input management management

output
AES_DOUTR (ciphertext C1) AES_DOUTR (ciphertext C2)
XOR
MSv19107V2

In CBC encrypt mode, the first plaintext input block, after bit/byte/half-word swapping (P1’),
is XOR-ed with a 128-bit IVI bitfield (initialization vector and counter), producing the I1 input
data for encrypt with the AES core, using a 128- key. The resulting 128-bit output block O1,
after swapping operation, is used as ciphertext C1. The O1 data is then XOR-ed with the

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second-block plaintext data P2’ to produce the I2 input data for the AES core to produce the
second block of ciphertext data. The chaining of data blocks continues in this way until the
last plaintext block in the message is encrypted.
If the message size is not a multiple of 128 bits, the final partial data block is encrypted in
the way explained in Section 15.4.6: AES ciphertext stealing and data padding.
Figure 67 illustrates the cipher block chaining (CBC) decryption mode.

Figure 67. CBC decryption

Block 1 Block 2
AES_DINR (ciphertext C1) AES_DINR (ciphertext C2)

DATATYPE[1:0] Swap DATATYPE[1:0] Swap

management management

I1 I2
AES_KEYRx (KEY) AES_KEYRx (KEY)
Decrypt Decrypt

AES_IVRx (IV) O1 O2
IVI
P1' P2'
Legend
DATATYPE[1:0] Swap DATATYPE[1:0] Swap
management management
input

output
AES_DOUTR (plaintext P1) AES_DOUTR (plaintext P2)
XOR
MSv19104V2

In CBC decrypt mode, like in ECB decrypt mode, the secret key must be prepared to
perform an AES decryption.
After the key preparation process, the decryption goes as follows: the first 128-bit ciphertext
block (after the swap operation) is used directly as the AES core input block I1 for decrypt
operation, using the 128-bit key. Its output O1 is XOR-ed with the 128-bit IVI field (that must
be identical to that used during encryption) to produce the first plaintext block P1.
The second ciphertext block is processed in the same way as the first block, except that the
I1 data from the first block is used in place of the initialization vector.
The decryption continues in this way until the last complete ciphertext block is decrypted.
If the message size is not a multiple of 128 bits, the final partial data block is decrypted in
the way explained in Section 15.4.6: AES ciphertext stealing and data padding.
For more information on data swapping, refer to Section 15.4.10: AES data registers and
data swapping.

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ECB/CBC encryption sequence

The sequence of events to perform an ECB/CBC encryption (more detail in Section 15.4.4):
1. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
2. Select the Mode 1 by to 00 the MODE[1:0] bitfield of the AES_CR register and select
ECB or CBC chaining mode by setting the CHMOD[1:0] bitfield of the AES_CR register
to 00 or 01, respectively. Data type can also be defined, using DATATYPE[1:0] bitfield.
3. Write the AES_KEYRx registers (128 bits) with encryption key. Fill the AES_IVRx
registers with the initialization vector data if CBC mode has been selected.
4. Enable the AES peripheral by setting the EN bit of the AES_CR register.
5. Write the AES_DINR register four times to input the plaintext (MSB first), as shown in
Figure 68.
6. Wait until the CCF flag is set in the AES_SR register.
7. Read the AES_DOUTR register four times to get the ciphertext (MSB first) as shown in
Figure 68. Then clear the CCF flag by setting the CCFC bit of the AES_CR register.
8. Repeat steps 5,6,7to process all the blocks with the same encryption key.

Figure 68. ECB/CBC encryption (Mode 1)

WR WR WR WR RD RD RD RD
Wait until flag CCF = 1
PT3 PT2 PT1 PT0 CT3 CT2 CT1 CT0
MSB LSB MSB LSB

Input phase Computation phase Output phase

4 write operations into 4 read operations of
AES_DINR[31:0] AES_DOUTR[31:0]

PT = plaintext = 4 words (PT3, … , PT0)

CT = ciphertext = 4 words (CT3, … , CT0)
MS18936V3

ECB/CBC decryption sequence

The sequence of events to perform an AES ECB/CBC decryption is as follows (more detail
in Section 15.4.4):
1. Follow the steps described in Section 15.4.5: AES decryption key preparation on
page 345, in order to prepare the decryption key in AES core.
2. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
3. Select the Mode 3 by setting to 10 the MODE[1:0] bitfield of the AES_CR register and
select ECB or CBC chaining mode by setting the CHMOD[1:0] bitfield of the AES_CR
register to 00 or 01, respectively. Data type can also be defined, using DATATYPE[1:0]
bitfield.
4. Write the AES_IVRx registers with the initialization vector (required in CBC mode only).
5. Enable AES by setting the EN bit of the AES_CR register.
6. Write the AES_DINR register four times to input the cipher text (MSB first), as shown in
Figure 69.
7. Wait until the CCF flag is set in the AES_SR register.
8. Read the AES_DOUTR register four times to get the plain text (MSB first), as shown in
Figure 69. Then clear the CCF flag by setting the CCFC bit of the AES_CR register.

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9. Repeat steps 6,7,8 to process all the blocks encrypted with the same key.

Figure 69. ECB/CBC decryption (Mode 3)

WR WR WR WR RD RD RD RD
Wait until flag CCF = 1
CT3 CT2 CT1 CT0 PT3 PT2 PT1 PT0
MSB LSB MSB LSB

Input phase Computation phase Output phase

4 write operations into 4 read operations from
AES_DINR[31:0] AES_DOUTR[31:0]

PT = plaintext = 4 words (PT3, … , PT0)

CT = ciphertext = 4 words (CT3, … , CT0)
MS18938V3

Suspend/resume operations in ECB/CBC modes

To suspend the processing of a message, proceed as follows:
1. If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN
bit of the AES_CR register.
2. If DMA is not used, read four times the AES_DOUTR register to save the last
processed block. If DMA is used, wait until the CCF flag is set in the AES_SR register
then stop the DMA transfers from the OUT FIFO by clearing the DMAOUTEN bit of the
AES_CR register.
3. If DMA is not used, poll the CCF flag of the AES_SR register until it becomes 1
(computation completed).
4. Clear the CCF flag by setting the CCFC bit of the AES_CR register.
5. Save initialization vector registers (only required in CBC mode as AES_IVRx registers
are altered during the data processing).
6. Disable the AES peripheral by clearing the bit EN of the AES_CR register.
7. Save the current AES configuration in the memory (except AES initialization vector
values).
8. If DMA is used, save the DMA controller status (pointers for IN and OUT data transfers,
number of remaining bytes, and so on).
Note: In point 7, the derived key information stored in AES_KEYRx registers can optionally be
saved in memory if the interrupted process is a decryption. Otherwise those registers do not
need to be saved as the original key value is known by the application

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To resume the processing of a message, proceed as follows:

1. If DMA is used, configure the DMA controller so as to complete the rest of the FIFO IN
and FIFO OUT transfers.
2. Ensure that AES is disabled (the EN bit of the AES_CR must be 0).
3. Restore the AES_CR and AES_KEYRx register setting, using the values of the saved
configuration. In case of decryption, derived key information can be written in
AES_KEYRx register instead of the original key value.
4. Prepare the decryption key as described in Section 15.4.5: AES decryption key
preparation (only required for ECB or CBC decryption). This step is not necessary if
derived key information has been loaded in AES_KEYRx registers.
5. Restore AES_IVRx registers using the saved configuration (only required in CBC
mode).
6. Enable the AES peripheral by setting the EN bit of the AES_CR register.
7. If DMA is used, enable AES DMA transfers by setting the DMAINEN and DMAOUTEN
bits of the AES_CR register.

Alternative single ECB/CBC decryption using Mode 4

The sequence of events to perform a single round of ECB/CBC decryption using Mode 4 is:
1. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
2. Select the Mode 4 by setting to 11 the MODE[1:0] bitfield of the AES_CR register and
select ECB or CBC chaining mode by setting the CHMOD[21:0] bitfield of the AES_CR
register to 000 or 001, respectively.
3. Select key length of 128 or 256 bits via KEYSIZE bitfield of the AES_CR register.
4. Write the AES_KEYRx registers with the encryption key. Write the AES_IVRx registers
if the CBC mode is selected.
5. Enable the AES peripheral by setting the EN bit of the AES_CR register.
6. Write the AES_DINR register four times to input the cipher text (MSB first).
7. Wait until the CCF flag is set in the AES_SR register.
8. Read the AES_DOUTR register four times to get the plain text (MSB first). Then clear
the CCF flag by setting the CCFC bit of the AES_CR register.
Note: When mode 4 is selected mode 3 cannot be used.
In mode 4, the AES_KEYRx registers contain the encryption key during all phases of the
processing. No derivation key is stored in these registers. It is stored internally in AES.

15.4.9 AES counter (CTR) mode

Overview
The counter mode (CTR) uses AES as a key-stream generator. The generated keys are
then XOR-ed with the plaintext to obtain the ciphertext.
CTR chaining is defined in NIST Special Publication 800-38A, Recommendation for Block
Cipher Modes of Operation. A typical message construction in CTR mode is given in
Figure 70.

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Figure 70. Message construction in CTR mode

16-byte boundaries

Zero
ICB Ciphertext (C) 0 padding

decrypt
4-byte boundaries
Plaintext (P)
Initialization vector (IV) Counter

MSv42156V1

The structure of this message is:

• A 16-byte initial counter block (ICB), composed of two distinct fields:
– Initialization vector (IV): a 96-bit value that must be unique for each encryption
cycle with a given key.
– Counter: a 32-bit big-endian integer that is incremented each time a block
processing is completed. The initial value of the counter should be set to 1.
• The plaintext P is encrypted as ciphertext C, with a known length. This length can be
non-multiple of 16 bytes, in which case a plaintext padding is required.

CTR encryption and decryption

Figure 71 and Figure 72 describe the CTR encryption and decryption process, respectively,
as implemented in the AES peripheral. The CTR mode is selected by writing 10 to the
CHMOD[1:0] bitfield of AES_CR register.

Figure 71. CTR encryption

Block 1 Block 2
AES_IVRx AES_IVRx
(IV + 32-bit counter) Nonce + 32-bit counter (+1)
Counter
increment (+1)
I1 I2
AES_KEYRx (KEY) AES_KEYRx (KEY)
Encrypt Encrypt

AES_DINR (plaintext P1) O1 AES_DINR (plaintext P2) O2

Swap DATATYPE[1:0] Swap DATATYPE[1:0]

management management
P1' P2'
Legend C1' C2'
DATATYPE[1:0] Swap DATATYPE[1:0] Swap
input management management
output
AES_DOUTR (ciphertext C1) AES_DOUTR (ciphertext C2)
XOR
MSv19102V2

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Figure 72. CTR decryption

Block 1 Block 2
AES_IVRx AES_IVRx
Nonce + 32-bit counter Nonce + 32-bit counter (+1)
Counter
increment (+1)
I1 I2
AES_KEYRx (KEY) AES_KEYRx (KEY)
Encrypt Encrypt

AES_DINR (ciphertext C1) O1 AES_DINR (ciphertext C2) O2

Swap DATATYPE[1:0] Swap DATATYPE[1:0]

management management
C1' C2'
Legend P1' P2'
DATATYPE[1:0] Swap DATATYPE[1:0] Swap
input management management

output
AES_DOUTR (plaintext P1) AES_DOUTR (plaintext P2)
XOR
MSv18942V2

In CTR mode, the cryptographic core output (also called keystream) Ox is XOR-ed with
relevant input block (Px' for encryption, Cx' for decryption), to produce the correct output
block (Cx' for encryption, Px' for decryption). Initialization vectors in AES must be initialized
as shown in Table 69.

Table 69. CTR mode initialization vector definition

AES_IVR3[31:0] AES_IVR2[31:0] AES_IVR1[31:0] AES_IVR0[31:0]

Nonce[31:0] Nonce[63:32] Nonce[95:64] 32-bit counter = 0x0001

Unlike in CBC mode that uses the AES_IVRx registers only once when processing the first
data block, in CTR mode AES_IVRx registers are used for processing each data block, and
the AES peripheral increments the counter bits of the initialization vector (leaving the nonce
bits unchanged).
CTR decryption does not differ from CTR encryption, since the core always encrypts the
current counter block to produce the key stream that is then XOR-ed with the plaintext (CTR
encryption) or ciphertext (CTR decryption) input. In CTR mode, the MODE[1:0] bitfield
settings 11, 10 or 00 default all to encryption mode, and the setting 01 (key derivation) is
forbidden.

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The sequence of events to perform an encryption or a decryption in CTR chaining mode:

1. Ensure that AES is disabled (the EN bit of the AES_CR must be 0).
2. Select CTR chaining mode by setting to 10 the CHMOD[1:0] bitfield of the AES_CR
register. Set MODE[1:0] bitfield to any value other than 01.
3. Initialize the AES_KEYRx registers, and load the AES_IVRx registers as described in
Table 69.
4. Set the EN bit of the AES_CR register, to start encrypting the current counter (EN is
automatically reset when the calculation finishes).
5. If it is the last block, pad the data with zeros to have a complete block, if needed.
6. Append data in AES, and read the result. The three possible scenarios are described in
Section 15.4.4: AES procedure to perform a cipher operation.
7. Repeat the previous step till the second-last block is processed. For the last block,
apply the two previous steps and discard the bits that are not part of the payload (if the
size of the significant data in the last input block is less than 16 bytes).

Suspend/resume operations in CTR mode

Like for the CBC mode, it is possible to interrupt a message to send a higher priority
message, and resume the message that was interrupted. Detailed CBC suspend/resume
sequence is described in Section 15.4.8: AES basic chaining modes (ECB, CBC).
Note: Like for CBC mode, the AES_IVRx registers must be reloaded during the resume operation.

15.4.10 AES data registers and data swapping

Data input and output
A 128-bit data block is entered into the AES peripheral with four successive 32-bit word
writes into the AES_DINR register (bitfield DIN[127:0]), the most significant word (bits
[127:96]) first, the least significant word (bits [31:0]) last.
A 128-bit data block is retrieved from the AES peripheral with four successive 32-bit word
reads from the AES_DOUTR register (bitfield DOUT[127:0]), the most significant word (bits
[127:96]) first, the least significant word (bits [31:0]) last.
The 32-bit data word for AES_DINR register or from AES_DOUTR register is organized in
big endian order, that is:
• the most significant byte of a word to write into AES_DINR must be put on the lowest
address out of the four adjacent memory locations keeping the word to write, or
• the most significant byte of a word read from AES_DOUTR goes to the lowest address
out of the four adjacent memory locations receiving the word
For using DMA for input data block write into AES, the four words of the input block must be
stored in the memory consecutively and in big-endian order, that is, the most significant
word on the lowest address. See Section 15.4.13: AES DMA interface.

Data swapping
The AES peripheral can be configured to perform a bit-, a byte-, a half-word-, or no
swapping on the input data word in the AES_DINR register, before loading it to the AES
processing core, and on the data output from the AES processing core, before sending it to
the AES_DOUTR register. The choice depends on the type of data. For example, a byte
swapping is used for an ASCII text stream.

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The data swap type is selected through the DATATYPE[1:0] bitfield of the AES_CR register.
The selection applies both to the input and the output of the AES core.
For different data swap types, Figure 73 shows the construction of AES processing core
input buffer data P127..0, from the input data entered through the AES_DINR register, or the
construction of the output data available through the AES_DOUTR register, from the AES
processing core output buffer data P127..0.

Figure 73. 128-bit block construction with respect to data swap

increasing memory address
byte 3 byte 2 byte 1 byte 0
D63 D56 D55 D48 D47 D40 D39 D32
DATATYPE[1:0] = 00: no swapping
MSB LSB
Word 3 Word 2 Word 1 Word 0
D127 D96 D95 D64 D63 D32 D31 D0

1 2 3 4
D127 D96 D95
P95 D64 D63 D32 D31 D0
MSB LSB

DATATYPE[1:0] = 01: 16-bit (half-word) swapping

MSB LSB
Word 3 Word 2 Word 1 Word 0
D127 D112 D111 D96 D95 D80 D79 D64 D63 D48 D47 D32 D31 D16 D15 D0

1 2 3 4

D111 D96 D127 D112 D79 D64 D95 D80 D47 D32 D63 D48 D15 D0 D31 D16
MSB LSB

DATATYPE[1:0] = 10: 8-bit (byte) swapping

MSB LSB
Word 3 Word 2 Word 1 Word 0
D127..120 D119..112 D111.104 D103..96 D95..88 D87..80 D79..72 D71...64 D63...56 D55...48 D47...40 D39...32 D31...24 D23...16 D15...8 D7...0

1 2 3 4

D103..96 D111.104 D119..112 D127..120 D71...64 D79..72 D87..80 D95..88 D39...32 D47...40 D55...48 D63...56 D7...0 D15...8 D23...16 D31...24
MSB LSB

DATATYPE[1:0] = 11: bit swapping

MSB LSB
Word 3 Word 2 Word 1 Word 0
D127 D126 D125 D98 D97 D96 D95 D94 D93 D66 D65 D64 D63 D62 D61 D34 D33 D32 D31 D30 D29 D2 D1 D0

1 2 3 4

D96 D97 D98 D125 D126 D127 D64 D65 D66 D93 D94 D95 D32 D33 D34 D61 D62 D63 D0 D1 D2 D29 D30 D31
MSB LSB

Legend: AES input/output data block in memory MSB most significant bit (127) of memory data block / AEC core buffer
AES core input/output buffer data LSB least significant bit (0) of memory data block / AEC core buffer
Zero padding (example) 1 4 Order of write to AES_DINR / read from AES_DOUTR
Data swap Dx input/output data bit ‘x’ MSv42153V2

Note: The data in AES key registers (AES_KEYRx) and initialization registers (AES_IVRx) are not
sensitive to the swap mode selection.

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Data padding
Figure 73 also gives an example of memory data block padding with zeros such that the
zeroed bits after the data swap form a contiguous zone at the MSB end of the AES core
input buffer. The example shows the padding of an input data block containing:
• 48 message bits, with DATATYPE[1:0] = 01
• 56 message bits, with DATATYPE[1:0] = 10
• 34 message bits, with DATATYPE[1:0] = 11

15.4.11 AES key registers

The AES_KEYRx registers store the encryption or decryption key bitfield KEY[127:0]. The
data to write to or to read from each register is organized in the memory in little-endian
order, that is, with most significant byte on the highest address.
The key is spread over the four registers in little-endian configuration, as shown on
Table 70.

Table 70. Key endianness in AES_KEYRx registers

AES_KEYR3[31:0] AES_KEYR2[31:0] AES_KEYR1[31:0] AES_KEYR0[31:0]
KEY[127:96] KEY[95:64] KEY[63:32] KEY[31:0]

The key for encryption or decryption may be written into these registers when the AES
peripheral is disabled.
The key registers are not affected by the data swapping controlled by DATATYPE[1:0]
bitfield of the AES_CR register.

15.4.12 AES initialization vector registers

The four AES_IVRx registers keep the initialization vector input bitfield IVI[127:0]. The data
to write to or to read from each register is organized in the memory in little-endian order, that
is, with most significant byte on the highest address. The registers are also ordered from
lowest address (AES_IVR0) to highest address (AES_IVR3).
The signification of data in the bitfield depends on the chaining mode selected. When used,
the bitfield is updated upon each computation cycle of the AES core.
Write operations to the AES_IVRx registers when the AES peripheral is enabled have no
effect to the register contents. For modifying the contents of the AES_IVRx registers, the EN
bit of the AES_CR register must first be cleared.
Reading the AES_IVRx registers returns the latest counter value (useful for managing
suspend mode) when the AES peripheral is disabled and returns zeros when it is enabled.
The AES_IVRx registers are not affected by the data swapping feature controlled by the
DATATYPE[1:0] bitfield of the CRYP_CR register.

15.4.13 AES DMA interface

The AES peripheral provides an interface to connect to the DMA (direct memory access)
controller. The DMA operation is controlled through the AES_CR register.

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Data input using DMA

Setting the DMAINEN bit of the AES_CR register enables DMA writing into AES. The AES
peripheral then initiates a DMA request during the input phase each time it requires a word
to be written to the AES_DINR register. It asserts four DMA requests to transfer one 128-bit
(four-word) input data block from memory, as shown in Figure 74.
See Table 71 for recommended DMA configuration.

Table 71. DMA channel configuration for memory-to-AES data transfer

DMA channel control
Recommended configuration
register field

Message length: a multiple of 128 bits.

Transfer size According to the algorithm and the mode selected, special padding/
ciphertext stealing might be required.
Source burst size
Single
(memory)
Destination burst size
Single
(peripheral)
DMA FIFO size AES FIFO_size = 4 bytes.
Source transfer width
32-bit words
(memory)
Destination transfer
32-bit words
width (peripheral)
Source address
Yes, after each 32-bit transfer
increment (memory)
Destination address Fixed address of AES_DINR (no increment)
increment (peripheral)

Figure 74. DMA transfer of a 128-bit data block during input phase
Chronological order
Increasing address
Memory accessed through DMA
Word3 Word2 Word1 Word0
System

D127 DIN[127:96] D96 D95 DIN[95:64] D64 D63 DIN[63:32] D32 D31 DIN[31:0] D0
MSB LSB

DMA DMA DMA DMA

DMA req N single write DMA req N+1 single write DMA req N+2 single write DMA req N+3 single write

1 2 3 4
AES_DINR
peripheral

(No swapping) 1 2 3 4
AES

AES core input buffer

I127 I96 I95 I64 I63 I32 I31 I0
MSB LSB

1 4 Order of write to AES_DINR MSv42160V1

Data output using DMA

Setting the DMAOUTEN bit of the AES_CR register enables DMA reading from AES. The
AES peripheral then initiates a DMA request during the Output phase each time it requires a

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word to be read from the AES_DOUTR register. It asserts four DMA requests to transfer one
128-bit (four-word) output data block to memory, as shown in Figure 75.
See Table 72 for recommended DMA configuration.

Table 72. DMA channel configuration for AES-to-memory data transfer

DMA channel control
Recommended configuration
register field

It is the message length multiple of AES block size (4 words). According to

Transfer size
the case extra bytes will have to be discarded.
Source burst size
Single
(peripheral)
Destination burst size
Single
(memory)
DMA FIFIO size AES FIFO_size = 4 bytes
Source transfer width
32-bit words
(peripheral)
Destination transfer
32-bit words
width (memory)
Source address
Fixed address of AES_DINR (no increment)
increment (peripheral)
Destination address Yes, after each 32-bit transfer
increment (memory)

Figure 75. DMA transfer of a 128-bit data block during output phase
Chronological order
Increasing address
Memory accessed through DMA
Word3 Word2 Word1 Word0

System
D127 DOUT[127:96] D96 D95 DOUT[95:64] D64 D63 DOUT[63:32] D32 D31 DOUT[31:0] D0
MSB LSB

DMA DMA DMA DMA

DMA req N single read DMA req N+1 single read DMA req N+2 single read DMA req N+3 single read

1 2 3 4
AES_DOUTR
peripheral

(No swapping) 1 2 3 4
AES

AES core output buffer

O127 O96 O95 O64 O63 O32 O31 O0
MSB LSB

1 4 Order of read from AES_DOUTR MSv42161V1

DMA operation in different operating modes

DMA operations are usable when Mode 1 (encryption) or Mode 3 (decryption) are selected
via the MODE[1:0] bitfield of the register AES_CR. As in Mode 2 (key derivation) the
AES_KEYRx registers must be written by software, enabling the DMA transfer through the
DMAINEN and DMAOUTEN bits of the AES_CR register have no effect in that mode.

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DMA single requests are generated by AES until it is disabled. So, after the data output
phase at the end of processing of a 128-bit data block, AES switches automatically to a new
data input phase for the next data block, if any.
When the data transferring between AES and memory is managed by DMA, the CCF flag is
not relevant and can be ignored (left set) by software. It must only be cleared when
transiting back to data transferring managed by software. See Suspend/resume operations
in ECB/CBC modes in Section 15.4.8: AES basic chaining modes (ECB, CBC) as example.

15.4.14 AES error management

The read error flag (RDERR) and write error flag (WRERR) of the AES_SR register are set
when an unexpected read or write operation, respectively, is detected. An interrupt can be
generated if the error interrupt enable (ERRIE) bit of the AES_CR register is set. For more
details, refer to Section 15.5: AES interrupts.
Note: AES is not disabled after an error detection and continues processing.
AES can be re-initialized at any moment by clearing then setting the EN bit of the AES_CR
register.

Read error flag (RDERR)

When an unexpected read operation is detected during the computation phase or during the
input phase, the AES read error flag (RDERR) is set in the AES_SR register. An interrupt is
generated if the ERRIE bit of the AES_CR register is set.
The RDERR flag is cleared by setting the corresponding ERRC bit of the AES_CR register.

Write error flag (WDERR)

When an unexpected write operation is detected during the computation phase or during the
output phase, the AES write error flag (WRERR) is set in the AES_SR register. An interrupt
is generated if the ERRIE bit of the AES_CR register is set.
The WDERR flag is cleared by setting the corresponding ERRC bit of the AES_CR register.

15.5 AES interrupts

There are three individual maskable interrupt sources generated by the AES peripheral, to
signal the following events:
• computation completed
• read error, see Section 15.4.14
• write error, see Section 15.4.14
These three sources are combined into a common interrupt signal aes_it that connects to
NVIC (nested vectored interrupt controller).

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Figure 76. AES interrupt signal generation

CCF
CCFIE

Flags in AES_SR register WRERR aes_it

Bits of AES_CR register ERRIE (goes to NVIC)

RDERR
ERRIE

MSv42162V1

Each AES interrupt source can individually be enabled/disabled, by setting/clearing the

corresponding enable bit of the AES_CR register. See Figure 76.
The status of the individual maskable interrupt sources can be read from the AES_SR
register.
Table 73 gives a summary of the interrupt sources, their event flags and enable bits.

Table 73. AES interrupt requests

AES interrupt event Event flag Enable bit

computation completed flag CCF CCFIE

read error flag RDERR ERRIE
write error flag WRERR ERRIE

15.6 AES processing latency

The tables below summarize the latency to process a 128-bit block for each mode of
operation.
Table 74. Processing latency (in clock cycle)
Computation Output
Mode of operation Algorithm Input phase Total
phase phase

Mode 1: Encryption ECB, CBC, CTR 8 202 4 214

Mode 2: Key derivation for decryption ECB, CBC - 80 - 80
Mode 3: Decryption ECB, CBC, CTR 8 202 4 214
Mode 4: Key derivation then
ECB, CBC 8 276 4 288
decryption

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15.7 AES registers

15.7.1 AES control register (AES_CR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAO DMAIN
Res. Res. Res. ERRIE CCFIE ERRC CCFC CHMOD[1:0] MODE[1:0] DATATYPE[1:0] EN
UTEN EN
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31:13 Reserved, must be kept at zero

Bit 12 DMAOUTEN: DMA output enable
This bit enables/disables data transferring with DMA, in the output phase:
0: Disable
1: Enable

When the bit is set, DMA requests are automatically generated by AES during the output data
phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0]
bitfield. It is not effective for Mode 2 (key derivation).
Usage of DMA with Mode 4 (single decryption) is not recommended.
Bit 11 DMAINEN: DMA input enable
This bit enables/disables data transferring with DMA, in the input phase:
0: Disable
1: Enable

When the bit is set, DMA requests are automatically generated by AES during the input data phase.
This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is
not effective for Mode 2 (key derivation).
Usage of DMA with Mode 4 (single decryption) is not recommended.
Bit 10 ERRIE: Error interrupt enable
This bit enables or disables (masks) the AES interrupt generation when RDERR and/or WRERR is
set:
0: Disable (mask)
1: Enable
Bit 9 CCFIE: CCF interrupt enable
This bit enables or disables (masks) the AES interrupt generation when CCF (computation complete
flag) is set:
0: Disable (mask)
1: Enable

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Bit 8 ERRC: Error flag clear

Upon written to 1, this bit clears the RDERR and WRERR error flags in the AES_SR register:
0: No effect
1: Clear RDERR and WRERR flags

Reading the flag always returns zero.

Bit 7 CCFC: Computation complete flag clear
Upon written to 1, this bit clears the computation complete flag (CCF) in the AES_SR register:
0: No effect
1: Clear CCF

Reading the flag always returns zero.

Bits 6:5 CHMOD[1:0]: Chaining mode selection
This bitfield selects the AES chaining mode:
00: Electronic codebook (ECB)
01: Cipher-Block Chaining (CBC)
10: Counter Mode (CTR)
11: Reserved

The bitfield value change is allowed only when AES is disabled, so as to avoid an unpredictable
behavior.
Bits 4:3 MODE[1:0]: AES operating mode
This bitfield selects the AES operating mode:
00: Mode 1: encryption
01: Mode 2: key derivation (or key preparation for ECB/CBC decryption)
10: Mode 3: decryption
11: Mode 4: key derivation then single decryption

The bitfield value change is allowed only when AES is disabled, so as to avoid an unpredictable
behavior. Any attempt to selecting Mode 4 while either ECB or CBC chaining mode is not selected,
defaults to effective selection of Mode 3. It is not possible to select a Mode 3 following a Mode 4.
Bits 2:1 DATATYPE[1:0]: Data type selection
This bitfield defines the format of data written in the AES_DINR register or read from the
AES_DOUTR register, through selecting the mode of data swapping:
00: None
01: Half-word (16-bit)
10: Byte (8-bit)
11: Bit

For more details, refer to Section 15.4.10: AES data registers and data swapping.
The bitfield value change is allowed only when AES is disabled, so as to avoid an unpredictable
behavior.
Bit 0 EN: AES enable
This bit enables/disables the AES peripheral:
0: Disable
1: Enable

At any moment, clearing then setting the bit re-initializes the AES peripheral.
This bit is automatically cleared by hardware when the key preparation process ends (Mode 2).

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15.7.2 AES status register (AES_SR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WRERR RDERR CCF
r r r r r r r r r r r r r r r r

Bits 31:3 Reserved, must be kept at zero

Bit 2 WRERR: Write error
This flag indicates the detection of an unexpected write operation to the AES_DINR register (during
computation or data output phase):
0: Not detected
1: Detected

The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR
register.
Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR
register.
The flag setting has no impact on the AES operation.
The flag is not effective when key derivation mode is selected.
Bit 1 RDERR: Read error flag
This flag indicates the detection of an unexpected read operation from the AES_DOUTR register
(during computation or data input phase):
0: Not detected
1: Detected

The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR
register.
Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR
register.
The flag setting has no impact on the AES operation.
The flag is not effective when key derivation mode is selected.
Bit 0 CCF: Computation completed flag
This flag indicates whether the computation is completed:
0: Not completed
1: Completed

The flag is set by hardware upon the completion of the computation. It is cleared by software, upon
setting the CCFC bit of the AES_CR register.
Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the AES_CR
register.
The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1.

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15.7.3 AES data input register (AES_DINR)

Address offset: 0x08
Reset value: 0x0000 0000
Only 32-bit access type is supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIN[x+31:x+16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN[x+15:x]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 This bitfield feeds a 32-bit input buffer. A 4-fold sequential write to this bitfield during the input phase
DIN[x+31:x]: One of four 32-bit words of a 128-bit input data block being written into the peripheral

virtually writes a complete 128-bit block of input data to the AES peripheral. Upon each write, the
data from the input buffer are handled by the data swap block according to the DATATYPE[1:0]
bitfield, then written into the AES core 128-bit input buffer.
The substitution for “x”, from the first to the fourth write operation, is: 96, 64, 32, and 0. In other
words, data from the first to the fourth write operation are: DIN[127:96], DIN[95:64], DIN[63:32], and
DIN[31:0].
The data signification of the input data block depends on the AES operating mode:
- Mode 1 (encryption): plaintext
- Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for input)
- Mode 3 (decryption) and Mode 4 (key derivation then single decryption): ciphertext
The data swap operation is described in Section 15.4.10: AES data registers and data swapping on
page 355.

15.7.4 AES data output register (AES_DOUTR)

Address offset: 0x0C
Reset value: 0x0000 0000
Only 32-bit access type is supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOUT[x+31:x+16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT[x+15:0]
r r r r r r r r r r r r r r r r

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Bits 31:0 DOUT[x+31:x]: One of four 32-bit words of a 128-bit output data block being read from the peripheral
This bitfield fetches a 32-bit output buffer. A 4-fold sequential read of this bitfield, upon the
computation completion (CCF set), virtually reads a complete 128-bit block of output data from the
AES peripheral. Before reaching the output buffer, the data produced by the AES core are handled
by the data swap block according to the DATATYPE[1:0] bitfield.
The substitution for DOUT[x+31:x], from the first to the fourth read operation, is: 96, 64, 32, and 0. In
other words, data from the first to the fourth read operation are: DOUT[127:96], DOUT[95:64],
DOUT[63:32], and DOUT[31:0].
The data signification of the output data block depends on the AES operating mode:
- Mode 1 (encryption): ciphertext
- Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for output).
- Mode 3 (decryption) and Mode 4 (key derivation then single decryption): plaintext
The data swap operation is described in Section 15.4.10: AES data registers and data swapping on
page 355.

15.7.5 AES key register 0 (AES_KEYR0)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 KEY[31:0]: Cryptographic key, bits [31:0]

This bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on the
operating mode:
- In Mode 1 (encryption), Mode 2 (key derivation) and Mode 4 (key derivation then single
decryption): the value to write into the bitfield is the encryption key.
- In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before
being used for decryption. After writing the encryption key into the bitfield, its reading before
enabling AES returns the same value. Its reading after enabling AES and after the CCF flag is set
returns the decryption key derived from the encryption key.
Note: In mode 4 (key derivation then single decryption) the bitfield always contains the encryption
key.
The AES_KEYRx registers may be written only when the AES peripheral is disabled.
Refer to Section 15.4.11: AES key registers on page 357 for more details.

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15.7.6 AES key register 1 (AES_KEYR1)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[63:48]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[47:32]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 KEY[63:32]: Cryptographic key, bits [63:32]

Refer to the AES_KEYR0 register for description of the KEY[127:0] bitfield.

15.7.7 AES key register 2 (AES_KEYR2)

Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[95:80]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[79:64]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 KEY[95:64]: Cryptographic key, bits [95:64]

Refer to the AES_KEYR0 register for description of the KEY[127:0] bitfield.

15.7.8 AES key register 3 (AES_KEYR3)

Address offset: 0x1C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[127:112]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[111:96]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 KEY[127:96]: Cryptographic key, bits [127:96]

Refer to the AES_KEYR0 register for description of the KEY[127:0] bitfield.

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15.7.9 AES initialization vector register 0 (AES_IVR0)

Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 IVI[31:0]: Initialization vector input, bits [31:0]

Refer to Section 15.4.12: AES initialization vector registers on page 357 for description of the
IVI[127:0] bitfield.
The initialization vector is only used in chaining modes other than ECB.
The initialization vector may be written only when the AES peripheral is disabled.
Reading this bitfield while AES is enabled returns 0x0000 0000.

15.7.10 AES initialization vector register 1 (AES_IVR1)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI[63:48]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI[47:32]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 IVI[63:32]: Initialization vector input, bits [63:32]

Refer to Section 15.4.12: AES initialization vector registers on page 357 for description of the
IVI[127:0] bitfield.
The initialization vector is only used in chaining modes other than ECB.
The initialization vector may be written only when the AES peripheral is disabled.
Reading this bitfield while AES is enabled returns 0x0000 0000.

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15.7.11 AES initialization vector register 2 (AES_IVR2)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI[95:80]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI[79:64]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 IVI[95:64]: Initialization vector input, bits [95:64]

Refer to Section 15.4.12: AES initialization vector registers on page 357 for description of the
IVI[127:0] bitfield.
The initialization vector is only used in chaining modes other than ECB.
The initialization vector may be written only when the AES peripheral is disabled.
Reading this bitfield while AES is enabled returns 0x0000 0000.

15.7.12 AES initialization vector register 3 (AES_IVR3)

Address offset: 0x2C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI[127:112]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI[111:96]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 IVI[127:96]: Initialization vector input, bits [127:96]

Refer to Section 15.4.12: AES initialization vector registers on page 357 for description of the
IVI[127:0] bitfield.
The initialization vector is only used in chaining modes other than ECB.
The initialization vector may be written only when the AES peripheral is disabled.
Reading this bitfield while AES is enabled returns 0x0000 0000.

15.7.13 AES register map

Table 75. AES register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
DATATYPE[1:0]
CHMOD[1:0]
DMAOUTEN

MODE[1:0]
DMAINEN
ERRIE
CCFIE
ERRC
CCFC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

AES_CR
EN

0x0000

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 75. AES register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
WRERR
RDERR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

CCF
AES_SR
0x0004

Reset value 0 0 0
AES_DINR
DIN[x+31:x]
0x0008 x=96,64,32,0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AES_DOUTR
0x000 DOUT[x+31:x]
x=96,64,32,0
C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_KEYR0 KEY[31:0]
0x0010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_KEYR1 KEY[63:32]
0x0014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_KEYR2 KEY[95:64]
0x0018
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x001 AES_KEYR3 KEY[127:96]

C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_IVR0 IVI[31:0]
0x0020
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_IVR1 IVI[63:32]
0x0024
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_IVR2 IVI[95:64]
0x0028
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x002 AES_IVR3 IVI[127:96]

C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 51 for the register boundary addresses.

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RM0377 General-purpose timers (TIM2/TIM3)

16 General-purpose timers (TIM2/TIM3)

16.1 TIM2/TIM3 introduction

The general-purpose timers consist of a 16-bit auto-reload counter driven by a
programmable prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The timers are completely independent, and do not share any resources. They can be
synchronized together as described in Section 16.3.15.

16.2 TIM2/TIM3 main features

General-purpose TIMx timer features include:
• 16-bit (TIM2/3) up, down, up/down auto-reload counter.
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65535.
• Up to 4 independent channels for:
– Input capture
– Output compare
– PWM generation (Edge- and Center-aligned modes)
– One-pulse mode output
• Synchronization circuit to control the timer with external signals and to interconnect
several timers.
• Interrupt/DMA generation on the following events:
– Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
– Trigger event (counter start, stop, initialization or count by internal/external trigger)
– Input capture
– Output compare
• Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning
purposes
• Trigger input for external clock or cycle-by-cycle current management

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Figure 77. General-purpose timer block diagram

Internal clock (CK_INT)

TIMxCLK from RCC Trigger
ETRF controller
ETR Polarity selection & edge ETRP TRGO
TIMx_ETR Input filter
detector & prescaler to other timers
to DAC/ADC
ITR0 TGI
ITR1 ITR
Slave
ITR2 TRC TRGI controller Reset, enable, up, count
ITR3
mode
TI1F_ED

TI1FP1 Encoder
TI2FP2 interface

U
Auto-reload register UI
Stop, clear or up/down
U
CK_PSC PSC CK_CNT +/- CNT counter
prescaler
CC1I U CC1I
XOR TI1FP1 OC1REF
TI1 Input filter & IC1 IC1PS Output OC1 TIMx_CH1
TI1FP2 Prescaler Capture/Compare 1 register
edge detector control
TIMx_CH1 TRC
CC2I
U CC2I
TI2FP1
TI2 Input filter & IC2 Output OC2
TIMx_CH2 TI2FP2 Prescaler
IC2PS Capture/Compare 2 register OC2REF TIMx_CH2
edge detector control
TRC
CC3I CC3I
U
TI3FP3 OC3REF
TI3 Input filter & IC3 IC3PS Output OC3 TIMx_CH3
TI3FP4 Prescaler Capture/Compare 3 register
TIMx_CH3 edge detector control
TRC CC4I
U CC4I
TI4FP3
TI4 Input filter & IC4 Output OC4
TIMx_CH4 TI4FP4 Prescaler
IC4PS Capture/Compare 4 register OC4REF TIMx_CH4
edge detector control
TRC

ETRF

Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit

Event

Interrupt & DMA output

MS19673V1

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RM0377 General-purpose timers (TIM2/TIM3)

16.3 TIM2/TIM3 functional description

16.3.1 Time-base unit

The main block of the programmable timer is a 16-bit with its related auto-reload register.
The counter can count up, down or both up and down but also down or both up and down.
The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
• Counter Register (TIMx_CNT)
• Prescaler Register (TIMx_PSC):
• Auto-Reload Register (TIMx_ARR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIMx_CR1 register. It can also be generated by software. The generation of the update
event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC
register). It can be changed on the fly as this control register is buffered. The new prescaler
ratio is taken into account at the next update event.
Figure 78 and Figure 16.3.2 give some examples of the counter behavior when the
prescaler ratio is changed on the fly:

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Figure 78. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

Update event (UEV)

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1
MS31076V2

Figure 79. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

F7 F8 F9 FA FB FC 00 01
Counter register

Update event (UEV)

0 3
Prescaler control register

Write a new value in TIMx_PSC

0 3
Prescaler buffer

0 0 1 2 3 0 1 2 3
Prescaler counter

MS31077V2

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RM0377 General-purpose timers (TIM2/TIM3)

16.3.2 Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
An Update event can be generated at each counter overflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register.
This is to avoid updating the shadow registers while writing new values in the preload
registers. Then no update event occurs until the UDIS bit has been written to 0. However,
the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate
does not change). In addition, if the URS bit (update request selection) in TIMx_CR1
register is set, setting the UG bit generates an update event UEV but without setting the UIF
flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register)
• The auto-reload shadow register is updated with the preload value (TIMx_ARR)
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

Figure 80. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31078V2

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Figure 81. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0000 0001 0002 0003

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31079V2

Figure 82. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0035 0036 0000 0001

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31080V2

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RM0377 General-purpose timers (TIM2/TIM3)

Figure 83. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

Figure 84. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FF 36

Write a new value in TIMx_ARR

MS31082V2

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Figure 85. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
F5 36
register

Auto-reload shadow
register F5 36

Write a new value in TIMx_ARR MS31083V2

Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
An Update event can be generate at each counter underflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
• The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one.

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RM0377 General-purpose timers (TIM2/TIM3)

The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

Figure 86. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow
(cnt_udf)

Update event (UEV)

Update interrupt flag

(UIF)

MS31184V1

Figure 87. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0002 0001 0000 0036 0035 0034 0033

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31185V1

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Figure 88. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0001 0000 0000 0001

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31186V1

Figure 89. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 00 36

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31187V1

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RM0377 General-purpose timers (TIM2/TIM3)

Figure 90. Counter timing diagram, Update event when repetition counter
is not used

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FF 36

Write a new value in TIMx_ARR

MS31188V1

Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-
reload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the
counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center
aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,
CMS = "11").
In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or

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DMA request is sent). This is to avoid generating both update and capture interrupt when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
• The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the auto-
reload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.

Figure 91. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 04 03 02 01 00 01 02 03 04 05 06 05 04 03

Counter underflow

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31189V1

1. Here, center-aligned mode 1 is used (for more details refer to Section 16.4.1: TIMx control register 1
(TIMx_CR1) on page 415).

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RM0377 General-purpose timers (TIM2/TIM3)

Figure 92. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0003 0002 0001 0000 0001 0002 0003

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31190V1

Figure 93. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0035

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow

MS31191V1

1. Center-aligned mode 2 or 3 is used with an UIF on overflow.

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Figure 94. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 01 00

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31192V1

Figure 95. Counter timing diagram, Update event with ARPE=1 (counter underflow)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 06 05 04 03 02 01 00 01 02 03 04 05 06 07

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FD 36

Write a new value in TIMx_ARR

Auto-reload active
register FD 36

MS31193V1

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RM0377 General-purpose timers (TIM2/TIM3)

Figure 96. Counter timing diagram, Update event with ARPE=1 (counter overflow)

CK_PSC

CEN

Timer clock = CK_CNT

Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
FD 36
register

Write a new value in TIMx_ARR

Auto-reload active
register FD 36

MS31194V1

16.3.3 Clock selection

The counter clock can be provided by the following clock sources:
• Internal clock (CK_INT)
• External clock mode1: external input pin (TIx)
• External clock mode2: external trigger input (ETR)
• Internal trigger inputs (ITRx): using one timer as prescaler for another timer. Refer to :
Using one timer as prescaler for another timer on page 408 for more details.

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the
CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except UG which remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 97 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.

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Figure 97. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

UG

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

MS31085V2

External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at
each rising or falling edge on a selected input.

Figure 98. TI2 external clock connection example

TIMx_SMCR
TS[2:0]

or TI2F or
TI1F or Encoder
ITRx mode
0xx
TI1_ED
100 TRGI External clock
TI1FP1 mode 1 CK_PSC
TI2F_Rising 101
TI2 Edge 0 TI2FP2 ETRF External clock
Filter 110
detector 1 ETRF mode 2
TI2F_Falling 111
CK_INT Internal clock
mode
ICF[3:0] CC2P (internal clock)

TIMx_CCMR1 TIMx_CCER
ECE SMS[2:0]
TIMx_SMCR

MS31196V1

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RM0377 General-purpose timers (TIM2/TIM3)

For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the
TIMx_CCMR1 register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).
Note: The capture prescaler is not used for triggering, so it does not need to be configured.
3. Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER
register.
4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.
5. Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register.
6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
For code example, refer to A.9.1: Upcounter on TI2 rising edge code example.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.

Figure 99. Control circuit in external clock mode 1

TI2

CNT_EN

Counter clock = CK_CNT = CK_PSC

Counter register 34 35 36

TIF

Write TIF=0

MS31087V2

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External clock source mode 2

This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
Figure 100 gives an overview of the external trigger input block.

Figure 100. External trigger input block

or TI2F or
TI1F or Encoder
mode

TRGI External clock

ETR mode 1 CK_PSC
0
Divider ETRP
ETR pin Filter ETRF External clock
/1, /2, /4, /8
1 fDTS downcounter mode 2
CK_INT Internal clock
ETP ETPS[1:0] ETF[3:0] mode
(internal clock)
TIMx_SMCR TIMx_SMCR TIMx_SMCR

ECE SMS[2:0]
TIMx_SMCR

MS33116V1

For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
For code example, refer to A.9.2: Up counter on each 2 ETR rising edges code example.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.

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RM0377 General-purpose timers (TIM2/TIM3)

Figure 101. Control circuit in external clock mode 2

f CK_INT

CNT_EN

ETR

ETRP

ETRF

Counter clock =
CK_INT =CK_PSC

Counter register 34 35 36

MS33111V2

16.3.4 Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

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Figure 102. Capture/compare channel (example: channel 1 input stage)

TI1F_ED
To the slave mode controller

TI1 TI1F_Rising
Filter TI1F Edge 0 TI1FP1
fDTS downcounter TI1F_Falling 01
detector 1
TI2FP1 IC1 Divider IC1PS
10
/1, /2, /4, /8
ICF[3:0] CC1P/CC1NP TRC
11
TIMx_CCMR1 TIMx_CCER (from slave mode
TI2F_Rising controller)
0
(from channel 2)
CC1S[1:0] ICPS[1:0] CC1E
TI2F_Falling
1
(from channel 2) TIMx_CCMR1 TIMx_CCER

MS33115V1

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.

Figure 103. Capture/compare channel 1 main circuit

APB Bus

MCU-peripheral interface
(if 16-bit)

8 8
high

S write CCR1H
low

Read CCR1H S write_in_progress

read_in_progress write CCR1L
Read CCR1L Capture/compare preload register R
R Output CC1S[1]
capture_transfer compare_transfer mode
CC1S[0]
CC1S[1] Input
mode OC1PE
CC1S[0] Capture/compare shadow register OC1PE
UEV
TIMx_CCMR1
Comparator (from time
IC1PS Capture
base unit)
CC1E CNT>CCR1
Counter CNT=CCR1
CC1G
TIMx_EGR

MS33144V1

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Figure 104. Output stage of capture/compare channel (channel 1)

TIMx_SMCR
OCCS
To the master
OCREF_CLR 0
mode controller
ETRF 1

ocref_clr_int
CNT > CCR1 0
Output OC1REF Output OC1
mode enable
CNT = CCR1 1 circuit
controller

CC1P
TIMx_CCER CC1E TIM1_CCER
OC1M[2:0]
TIMx_CCMR1

MS33146V1

The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

16.3.5 Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to 0 or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when it is written with 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
1. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.
2. Program the appropriate input filter duration in relation with the signal connected to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been

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detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
3. Select the edge of the active transition on the TI1 channel by writing the CC1P and
CC1NP bits to 00 in the TIMx_CCER register (rising edge in this case).
4. Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the
TIMx_CCMR1 register).
5. Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
6. If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.
For code example, refer to A.9.3: Input capture configuration code example.
When an input capture occurs:
• The TIMx_CCR1 register gets the value of the counter on the active transition.
• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
• An interrupt is generated depending on the CC1IE bit.
• A DMA request is generated depending on the CC1DE bit.
For code example, refer to A.9.4: Input capture data management code example.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note: IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.

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16.3.6 PWM input mode

This mode is a particular case of input capture mode. The procedure is the same except:
• Two ICx signals are mapped on the same TIx input.
• These 2 ICx signals are active on edges with opposite polarity.
• One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
1. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).
2. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P to ‘0’ and the CC1NP bit to ‘0’ (active on rising edge).
3. Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).
4. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
bit to ‘1’ and the CC2NP bit to ’0’(active on falling edge).
5. Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register
(TI1FP1 selected).
6. Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.
7. Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register.
For code example, refer to A.9.5: PWM input configuration code example.

Figure 105. PWM input mode timing

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16.3.7 Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCxREF/OCx) to its active level, one just needs to write
101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCxREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
e.g.: CCxP=0 (OCx active high) => OCx is forced to high level.
OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx
register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the Output Compare Mode section.

16.3.8 Output compare mode

This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
• Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.
• Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
• Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
• Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One-pulse mode).
Procedure:
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be
generated.
4. Select the output mode. For example, one must write OCxM=011, OCxPE=0, CCxP=0
and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not
used, OCx is enabled and active high.
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
For code example, refer to A.9.7: Output compare configuration code example.

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The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 106.

Figure 106. Output compare mode, toggle on OC1.

Write B201h in the CC1R register

TIM1_CNT 0039 003A 003B B200 B201

TIM1_CCR1 003A B201

OC1REF= OC1

Match detected on CCR1

Interrupt generated if enabled

MS31092V1

16.3.9 PWM mode

Pulse width modulation mode allows to generate a signal with a frequency determined by
the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. The corresponding preload register must be enabled by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, all registers must be initialized by setting the UG bit in
the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by the CCxE bit in
the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.

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In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx ≤ TIMx_CNT or TIMx_CNT ≤ TIMx_CCRx (depending on the direction
of the counter). However, to comply with the OCREF_CLR functionality (OCREF can be
cleared by an external event through the ETR signal until the next PWM period), the
OCREF signal is asserted only:
• When the result of the comparison changes, or
• When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from
the “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes
(OCxM=‘110 or ‘111).
This forces the PWM by software while the timer is running.
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.

PWM edge-aligned mode

Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Section :
Upcounting mode on page 375.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1.
If the compare value is 0 then OCxREF is held at ‘0. Figure 107 shows some edge-aligned
PWM waveforms in an example where TIMx_ARR=8.
For code example, refer to A.9.8: Edge-aligned PWM configuration example.

Figure 107. Edge-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 0 1

OCXREF
CCRx=4
CCxIF

OCXREF
CCRx=8
CCxIF

OCXREF ‘1’
CCRx>8
CCxIF

OCXREF ‘0’
CCRx=0
CCxIF

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Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Section :
Downcounting mode on page 378.
In PWM mode 1, the reference signal OCxREF is low as long as TIMx_CNT>TIMx_CCRx
else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload
value in TIMx_ARR, then OCxREF is held at ‘1. 0% PWM is not possible in this mode.

PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00 (all the remaining configurations having the same effect on the OCxREF/OCx signals).
The compare flag is set when the counter counts up, when it counts down or both when it
counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
Section : Center-aligned mode (up/down counting) on page 381.
Figure 108 shows some center-aligned PWM waveforms in an example where:
• TIMx_ARR=8,
• PWM mode is the PWM mode 1,
• The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.
For code example, refer to A.9.9: Center-aligned PWM configuration example.

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Figure 108. Center-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1

OCxREF
CCRx = 4

CCxIF CMS=01
CMS=10
CMS=11

OCxREF
CCRx=7

CMS=10 or 11
CCxIF
‘1’
OCxREF
CCRx=8

CCxIF CMS=01
CMS=10
CMS=11
‘1’
OCxREF
CCRx>8

CCxIF CMS=01
CMS=10
CMS=11
‘0’
OCxREF
CCRx=0

CCxIF CMS=01
CMS=10
CMS=11

AI14681b

Hints on using center-aligned mode:

• When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
• Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
– The direction is not updated if a value greater than the auto-reload value is written
in the counter (TIMx_CNT>TIMx_ARR). For example, if the counter was counting
up, it continues to count up.
– The direction is updated if 0 or the TIMx_ARR value is written in the counter but no
Update Event UEV is generated.
• The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.

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16.3.10 One-pulse mode

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. One-pulse mode is selected
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:
• In upcounting: CNT<CCRx ≤ ARR (in particular, 0<CCRx),
• In downcounting: CNT>CCRx.

Figure 109. Example of one-pulse mode.

TI2

OC1REF
OC1

TIM1_ARR
Counter

TIM1_CCR1

0
tDELAY tPULSE t

MS31099V1

For example one may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
1. Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register.
2. TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER
register.
3. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in
the TIMx_SMCR register.
4. TI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register
(trigger mode).
For code example, refer to A.9.16: One-Pulse mode code example.

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The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
• The tDELAY is defined by the value written in the TIMx_CCR1 register.
• The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1+1).
• Let’s say one want to build a waveform with a transition from ‘0 to ‘1 when a compare
match occurs and a transition from ‘1 to ‘0 when the counter reaches the auto-reload
value. To do this PWM mode 2 must be enabled by writing OC1M=111 in the
TIMx_CCMR1 register. Optionally the preload registers can be enabled by writing
OC1PE=1 in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this
case one has to write the compare value in the TIMx_CCR1 register, the auto-reload
value in the TIMx_ARR register, generate an update by setting the UG bit and wait for
external trigger event on TI2. CC1P is written to ‘0 in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
Since only 1 pulse (Single mode) is needed, a 1 must be written in the OPM bit in the
TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over
from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0',
so the Repetitive Mode is selected.

Particular case: OCx fast enable:

In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If one wants to output a waveform with the minimum delay, the OCxFE bit can be set in the
TIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
For code example, refer to A.9.16: One-Pulse mode code example.

16.3.11 Clearing the OCxREF signal on an external event

1. The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR
register are cleared to 00.
2. The external clock mode 2 must be disabled: bit ECE in the TIMx_SMCR register is
cleared to 0.
3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be
configured according to the application’s needs.
For code example, refer to A.9.10: ETR configuration to clear OCxREF code example.
Figure 110 shows the behavior of the OCxREF signal when the ETRF input becomes high,
for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in
PWM mode.

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Figure 110. Clearing TIMx OCxREF

(CCRx)

Counter (CNT)

ETRF

OCxREF
(OCxCE = ‘0’)

OCxREF
(OCxCE = ‘1’)

OCxREF_CLR OCxREF_CLR
becomes high still high
MS33105V1

1. In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter
overflow.

16.3.12 Encoder interface mode

To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter
is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if
it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER
register. CC1NP and CC2NP must be kept cleared. When needed, the input filter can be
programmed as well.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 76. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware
accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So the
TIMx_ARR must be configured before starting. In the same way, the capture, compare,
prescaler, trigger output features continue to work as normal.
In this mode, the counter is modified automatically following the speed and the direction of
the incremental encoder and its content, therefore, always represents the encoder’s

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position. The count direction correspond to the rotation direction of the connected sensor.
The table summarizes the possible combinations, assuming TI1 and TI2 do not switch at the
same time.

Table 76. Counting direction versus encoder signals

Level on opposite TI1FP1 signal TI2FP2 signal
Active edge signal (TI1FP1 for
TI2, TI2FP2 for TI1) Rising Falling Rising Falling

Counting on High Down Up No Count No Count

TI1 only Low Up Down No Count No Count

Counting on High No Count No Count Up Down

TI2 only Low No Count No Count Down Up

Counting on High Down Up Up Down

TI1 and TI2 Low Up Down Down Up

An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoder’s
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
Figure 111 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are
selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:
• CC1S= 01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1)
• CC2S= 01 (TIMx_CCMR2 register, TI2FP2 mapped on TI2)
• CC1P=0, CC1NP = ‘0’ (TIMx_CCER register, TI1FP1 noninverted, TI1FP1=TI1)
• CC2P=0, CC2NP = ‘0’ (TIMx_CCER register, TI2FP2 noninverted, TI2FP2=TI2)
• SMS= 011 (TIMx_SMCR register, both inputs are active on both rising and falling
edges)
• CEN= 1 (TIMx_CR1 register, Counter is enabled)
For code example, refer to A.9.11: Encoder interface code example.

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Figure 111. Example of counter operation in encoder interface mode

forward jitter backward jitter forward

TI1

TI2

Counter

up down up

MS33107V1

Figure 112 gives an example of counter behavior when TI1FP1 polarity is inverted (same
configuration as above except CC1P=1).

Figure 112. Example of encoder interface mode with TI1FP1 polarity inverted

forward jitter backward jitter forward

TI1

TI2

Counter

down up down

MS33108V1

The timer, when configured in Encoder Interface mode provides information on the sensor’s
current position. Dynamic information can be obtained (speed, acceleration, deceleration)
by measuring the period between two encoder events using a second timer configured in
capture mode. The output of the encoder which indicates the mechanical zero can be used
for this purpose. Depending on the time between two events, the counter can also be read
at regular times. This can be done by latching the counter value into a third input capture
register if available (then the capture signal must be periodic and can be generated by
another timer). when available, it is also possible to read its value through a DMA request
generated by a Real-Time clock.

16.3.13 Timer input XOR function

The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to
the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input
capture.

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16.3.14 Timers and external trigger synchronization

The TIMx Timers can be synchronized with an external trigger in several modes: Reset
mode, Gated mode and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
• Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits
select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect
rising edges only).
• Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
• Start the counter by writing CEN=1 in the TIMx_CR1 register.
For code example, refer to A.9.12: Reset mode code example.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.

Figure 113. Control circuit in reset mode

TI1

UG

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03

TIF

MS31401V2

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Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
1. Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits
select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write
CC1P=1 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect low
level only).
2. Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
3. Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).
For code example, refer to A.9.13: Gated mode code example.
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.

Figure 114. Control circuit in gated mode

TI1

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 37 38

TIF

Write TIF=0

MS31402V1

1. The configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not have any effect
in gated mode because gated mode acts on a level and not on an edge.

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Slave mode: Trigger mode

The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
1. Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so it does not need to be configured. CC2S bits are
selecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write
CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low
level only).
2. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.
For code example, refer to A.9.14: Trigger mode code example.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.

Figure 115. Control circuit in trigger mode

TI2

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 34 35 36 37 38

TIF

MS31403V1

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Slave mode: External Clock mode 2 + trigger mode

The external clock mode 2 can be used in addition to another slave mode (except external
clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock
input, and another input can be selected as trigger input when operating in reset mode,
gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS
bits of TIMx_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR
signal as soon as a rising edge of TI1 occurs:
1. Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
– ETF = 0000: no filter
– ETPS=00: prescaler disabled
– ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.
2. Configure the channel 1 as follows, to detect rising edges on TI:
– IC1F=0000: no filter.
– The capture prescaler is not used for triggering and does not need to be
configured.
– CC1S=01in TIMx_CCMR1 register to select only the input capture source
– CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect
rising edge only).
3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
For code example, refer to A.9.15: External clock mode 2 + trigger mode code example.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.

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Figure 116. Control circuit in external clock mode 2 + trigger mode

TI1

CEN/CNT_EN

ETR

Counter clock = CK_CNT = CK_PSC

Counter register 34 35 36

TIF

MS33110V1

16.3.15 Timer synchronization

The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
Figure 117: Master/Slave timer example presents an overview of the trigger selection and
the master mode selection blocks.
Note: The clock of the slave timer must be enabled prior to receive events from the master timer,
and must not be changed on-the-fly while triggers are received from the master timer.

Using one timer as prescaler for another timer

Figure 117. Master/Slave timer example

TIMx TIMy
Clock
TS
MMS SMS

UEV
Master Slave CK_PSC
TRGO1 ITR1
mode mode
Prescaler Counter control control
Prescaler Counter

Input
trigger
selection

MS33136V1

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For example, Timer x can be configured to act as a prescaler for Timer y. Refer to
Figure 117. To do this, follow the sequence below:
1. Configure Timer x in master mode so that it outputs a periodic trigger signal on each
update event UEV. If MMS=010 is written in the TIMx_CR2 register, a rising edge is
output on TRGO1 each time an update event is generated.
2. To connect the TRGO1 output of Timer x to Timer y, Timer y must be configured in
slave mode using ITR1 as internal trigger. This is selected through the TS bits in the
TIMy_SMCR register (writing TS=000).
3. Then the slave mode controller must be put in external clock mode 1 (write SMS=111 in
the TIMy_SMCR register). This causes Timer y to be clocked by the rising edge of the
periodic Timer x trigger signal (which correspond to the timer x counter overflow).
4. Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1
register).
For code example, refer to A.9.17: Timer prescaling another timer code example.
Note: If OCx is selected on Timer x as trigger output (MMS=1xx), its rising edge is used to clock
the counter of timer y.

Using one timer to enable another timer

In this example, we control the enable of Timer y with the output compare 1 of Timer x.
Refer to Figure 117 for connections. Timer y counts on the divided internal clock only when
OC1REF of Timer x is high. Both counter clock frequencies are divided by 3 by the
prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).
1. Configure Timer x master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIMx_CR2 register).
2. Configure the Timer x OC1REF waveform (TIMx_CCMR1 register).
3. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIMy_SMCR
register).
4. Configure Timer y in gated mode (SMS=101 in TIMy_SMCR register).
5. Enable Timer y by writing ‘1 in the CEN bit (TIMy_CR1 register).
6. Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register).
For code example, refer to A.9.18: Timer enabling another timer code example.
Note: The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer y
counter enable signal.

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Figure 118. Gating timer y with OC1REF of timer x

CK_INT

TIMERx-OC1REF

TIMERx-CNT FC FD FE FF 00 01

TIMERy-CNT 3045 3046 3047 3048

TIMERy-TIF

Write TIF = 0
MS33137V1

In the example in Figure 118, the Timer y counter and prescaler are not initialized before
being started. So they start counting from their current value. It is possible to start from a
given value by resetting both timers before starting Timer x. Then any value can be written
in the timer counters. The timers can easily be reset by software using the UG bit in the
TIMx_EGR registers.
In the next example, we synchronize Timer x and Timer y. Timer x is the master and starts
from 0. Timer y is the slave and starts from 0xE7. The prescaler ratio is the same for both
timers. Timer y stops when Timer x is disabled by writing ‘0 to the CEN bit in the TIMy_CR1
register:
1. Configure Timer x master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIMx_CR2 register).
2. Configure the Timer x OC1REF waveform (TIMx_CCMR1 register).
3. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIMy_SMCR
register).
4. Configure Timer y in gated mode (SMS=101 in TIMy_SMCR register).
5. Reset Timer x by writing ‘1 in UG bit (TIMx_EGR register).
6. Reset Timer y by writing ‘1 in UG bit (TIMy_EGR register).
7. Initialize Timer y to 0xE7 by writing ‘0xE7’ in the timer y counter (TIMy_CNTL).
8. Enable Timer y by writing ‘1 in the CEN bit (TIMy_CR1 register).
9. Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register).
10. Stop Timer x by writing ‘0 in the CEN bit (TIMx_CR1 register).
For code example, refer to A.9.19: Master and slave synchronization code example.

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Figure 119. Gating timer y with Enable of timer x

CK_INT

TIMERx-CEN=CNT_EN

TIMERx-CNT_INIT

TIMERx-CNT 75 00 01 02

TIMERy-CNT AB 00 E7 E8 E9

TIMERy-CNT_INIT

TIMERy-write CNT

TIMERy-TIF

Write TIF = 0
MS33138V1

Using one timer to start another timer

In this example, we set the enable of Timer y with the update event of Timer x. Refer to
Figure 117 for connections. Timer y starts counting from its current value (which can be
nonzero) on the divided internal clock as soon as the update event is generated by Timer x.
When Timer y receives the trigger signal its CEN bit is automatically set and the counter
counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock
frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).
1. Configure Timer x master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIMx_CR2 register).
2. Configure the Timer x period (TIMx_ARR registers).
3. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIMy_SMCR
register).
4. Configure Timer y in trigger mode (SMS=110 in TIMy_SMCR register).
5. Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register).

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Figure 120. Triggering timer y with update of timer x

CK_INT

TIMERx-UEV

TIMERx-CNT FD FE FF 00 01 02

TIMERy-CNT 45 46 47 48

TIMERy-CEN=CNT_EN

TIMERy-TIF

Write TIF = 0

MS33139V1

As in the previous example, both counters can be initialized before starting counting.
Figure 121 shows the behavior with the same configuration as in Figure 120 but in trigger
mode instead of gated mode (SMS=110 in the TIMy_SMCR register).

Figure 121. Triggering timer y with Enable of timer x

CK_INT

TIMERx-CEN=CNT_EN

TIMERx-CNT_INIT

TIMERx-CNT 75 00 01 02

TIMERy-CNT CD 00 E7 E8 E9 EA

TIMERy-CNT_INIT

TIMERy
write CNT

TIMERy-TIF

Write TIF = 0

MS33140V1

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Starting 2 timers synchronously in response to an external trigger

In this example, we set the enable of timer x when its TI1 input rises, and the enable of
Timer y with the enable of Timer x. Refer to Figure 117 for connections. To ensure the
counters are aligned, Timer x must be configured in Master/Slave mode (slave with respect
to TI1, master with respect to Timer y):
1. Configure Timer x master mode to send its Enable as trigger output (MMS=001 in the
TIMx_CR2 register).
2. Configure Timer x slave mode to get the input trigger from TI1 (TS=100 in the
TIMx_SMCR register).
3. Configure Timer x in trigger mode (SMS=110 in the TIMx_SMCR register).
4. Configure the Timer x in Master/Slave mode by writing MSM=1 (TIMx_SMCR register).
5. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIMy_SMCR
register).
6. Configure Timer y in trigger mode (SMS=110 in the TIMy_SMCR register).
For code example, refer to A.9.20: Two timers synchronized by an external trigger code
example.
When a rising edge occurs on TI1 (Timer x), both counters starts counting synchronously on
the internal clock and both TIF flags are set.
Note: In this example both timers are initialized before starting (by setting their respective UG
bits). Both counters starts from 0, but an offset can easily be inserted between them by
writing any of the counter registers (TIMx_CNT). One can see that the master/slave mode
insert a delay between CNT_EN and CK_PSC on timer x.

Figure 122. Triggering timer x and y with timer x TI1 input

CK_INT

TIMERx-TI1

TIMERx-CEN=CNT_EN

TIMERx-CK_PSC

TIMERx-CNT 00 01 02 03 04 05 06 07 08 09

TIMERx-TIF

TIMERy-CEN=CNT_EN

TIMERy-CK_PSC

TIMERy-CNT 00 01 02 03 04 05 06 07 08 09

TIMERy-TIF

MS33141V1

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16.3.16 Debug mode

When the microcontroller enters debug mode (Cortex®-M0+ core - halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to Section 27.9.2: Debug support for timers,
watchdog and I2C.

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16.4 TIM2/TIM3 registers

Refer to Section 1.2 on page 45 for a list of abbreviations used in register descriptions.
The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral
registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be
done by bytes (8 bits), half-words (16 bits) or words (32 bits).

16.4.1 TIMx control register 1 (TIMx_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CKD[1:0] ARPE CMS DIR OPM URS UDIS CEN

rw rw rw rw rw rw rw rw rw rw

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:8 CKD: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (ETR, TIx),
00: tDTS = tCK_INT
01: tDTS = 2 × tCK_INT
10: tDTS = 4 × tCK_INT
11: Reserved
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered
1: TIMx_ARR register is buffered
Bits 6:5 CMS: Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
the counter is enabled (CEN=1)
Bit 4 DIR: Direction
0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder
mode.
Bit 3 OPM: One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN)

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Bit 2 URS: Update request source

This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder mode can work only if the CEN bit has been
previously set by software. However trigger mode can set the CEN bit automatically by
hardware.
CEN is cleared automatically in one-pulse mode, when an update event occurs.

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16.4.2 TIMx control register 2 (TIMx_CR2)

Address offset: 0x04
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. TI1S MMS[2:0] CCDS Res. Res. Res.

rw rw rw rw rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 TI1S: TI1 selection
0: The TIMx_CH1 pin is connected to TI1 input
1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Bits 6:4 MMS: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR
register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO)
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Compare - OC3REF signal is used as trigger output (TRGO)
111: Compare - OC4REF signal is used as trigger output (TRGO)
Note: The clock of the slave timer or ADC must be enabled prior to receiving events from the
master timer, and must not be changed on-the-fly while triggers are received from the
master timer.
Bit 3 CCDS: Capture/compare DMA selection
0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bits 2:0 Reserved, must be kept at reset value.

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16.4.3 TIMx slave mode control register (TIMx_SMCR)

Address offset: 0x08
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP ECE ETPS[1:0] ETF[3:0] MSM TS[2:0] Res. SMS[2:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 ETP: External trigger polarity

This bit selects whether ETR or ETR is used for trigger operations
0: ETR is noninverted, active at high level or rising edge
1: ETR is inverted, active at low level or falling edge
Bit 14 ECE: External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI
connected to ETRF (SMS=111 and TS=111).
2: It is possible to simultaneously use external clock mode 2 with the following slave modes:
reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to
ETRF in this case (TS bits must not be 111).
3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the
external clock input is ETRF.
Bits 13:12 ETPS: External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A
prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8
Bits 11:8 ETF[3:0]: External trigger filter
This bit-field then defines the frequency used to sample ETRP signal and the length of the
digital filter applied to ETRP. The digital filter is made of an event counter in which N
consecutive events are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8

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Bit 7 MSM: Master/Slave mode

0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful if we
want to synchronize several timers on a single external event.
Bits 6:4 TS: Trigger selection
This bit-field selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0).
001: Internal Trigger 1 (ITR1).
010: Internal Trigger 2 (ITR2).
011: Reserved.
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
See Table 77: TIM2/TIM3 internal trigger connection on page 419 for more details on ITRx
meaning for each Timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=000) to
avoid wrong edge detections at the transition.
Bit 3 Reserved, must be kept at ‘1’.
Bits 2:0 SMS: Slave mode selection
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2
level.
010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1
level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100).
Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode
checks the level of the trigger signal.
The clock of the slave timer must be enabled prior to receiving events from the master
timer, and must not be changed on-the-fly while triggers are received from the master
timer."

Table 77. TIM2/TIM3 internal trigger connection

Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010)

TIM2 TIM21 TIM22 TIM3

TIM3 TIM2 TIM22 TIM21

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16.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)

Address offset: 0x0C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. TDE Res. CC4DE CC3DE CC2DE CC1DE UDE Res. TIE Res. CC4IE CC3IE CC2IE CC1IE UIE

rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 Reserved, must be kept at reset value.

Bit 14 TDE: Trigger DMA request enable
0: Trigger DMA request disabled.
1: Trigger DMA request enabled.
Bit 13 Reserved, always read as 0
Bit 12 CC4DE: Capture/Compare 4 DMA request enable
0: CC4 DMA request disabled.
1: CC4 DMA request enabled.
Bit 11 CC3DE: Capture/Compare 3 DMA request enable
0: CC3 DMA request disabled.
1: CC3 DMA request enabled.
Bit 10 CC2DE: Capture/Compare 2 DMA request enable
0: CC2 DMA request disabled.
1: CC2 DMA request enabled.
Bit 9 CC1DE: Capture/Compare 1 DMA request enable
0: CC1 DMA request disabled.
1: CC1 DMA request enabled.
Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
Bit 7 Reserved, must be kept at reset value.
Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4IE: Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled.
1: CC4 interrupt enabled.
Bit 3 CC3IE: Capture/Compare 3 interrupt enable
0: CC3 interrupt disabled
1: CC3 interrupt enabled

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Bit 2 CC2IE: Capture/Compare 2 interrupt enable

0: CC2 interrupt disabled
1: CC2 interrupt enabled
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled
1: CC1 interrupt enabled
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled

16.4.5 TIMx status register (TIMx_SR)

Address offset: 0x10
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. CC4OF CC3OF CC2OF CC1OF Res. Res. TIF Res. CC4IF CC3IF CC2IF CC1IF UIF

rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

Bits 15:13 Reserved, must be kept at reset value.

Bit 12 CC4OF: Capture/Compare 4 overcapture flag
refer to CC1OF description
Bit 11 CC3OF: Capture/Compare 3 overcapture flag
refer to CC1OF description
Bit 10 CC2OF: Capture/compare 2 overcapture flag
refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0.
0: No overcapture has been detected
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 TIF: Trigger interrupt flag
This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode. It is set when the counter
starts or stops when gated mode is selected. It is cleared by software.
0: No trigger event occurred
1: Trigger interrupt pending
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4IF: Capture/Compare 4 interrupt flag
refer to CC1IF description
Bit 3 CC3IF: Capture/Compare 3 interrupt flag
refer to CC1IF description

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Bit 2 CC2IF: Capture/Compare 2 interrupt flag

refer to CC1IF description
Bit 1 CC1IF: Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some
exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register
description). It is cleared by software.
0: No match
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit
goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow
(in downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected
on IC1 which matches the selected polarity)
Bit 0 UIF: Update interrupt flag
″ This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
″ At overflow or underflow and if UDIS=0 in the TIMx_CR1 register.
″ When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
and UDIS=0 in the TIMx_CR1 register.
When CNT is reinitialized by a trigger event (refer to the synchro control register description),
if URS=0 and UDIS=0 in the TIMx_CR1 register.

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16.4.6 TIMx event generation register (TIMx_EGR)

Address offset: 0x14
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. TG Res. CC4G CC3G CC2G CC1G UG

w w w w w w

Bits 15:7 Reserved, must be kept at reset value.

Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if
enabled.
Bit 5 Reserved, must be kept at reset value.
Bit 4 CC4G: Capture/compare 4 generation
refer to CC1G description
Bit 3 CC3G: Capture/compare 3 generation
refer to CC1G description
Bit 2 CC2G: Capture/compare 2 generation
refer to CC1G description
Bit 1 CC1G: Capture/compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload
value (TIMx_ARR) if DIR=1 (downcounting).

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16.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1)

Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So one must take care that the same bit
can have a different meaning for the input stage and for the output stage.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2CE OC2M[2:0] OC2PE OC2FE OC1CE OC1M[2:0] OC1PE OC1FE
CC2S[1:0] CC1S[1:0]
IC2F[3:0] IC2PSC[1:0] IC1F[3:0] IC1PSC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Output compare mode

Bit 15 OC2CE: Output compare 2 clear enable

Bits 14:12 OC2M[2:0]: Output compare 2 mode
Bit 11 OC2PE: Output compare 2 preload enable
Bit 10 OC2FE: Output compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bit 7 OC1CE: Output compare 1 clear enable
OC1CE: Output Compare 1 Clear Enable
0: OC1Ref is not affected by the ETRF input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input

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Bits 6:4 OC1M: Output compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends
on CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing
base).
001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter
TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as
TIMx_CNT>TIMx_CCR1 else active (OC1REF=1).
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else
inactive.
Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.

Bit 3 OC1PE: Output compare 1 preload enable

0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded in the active register at each update event.
Note: The PWM mode can be used without validating the preload register only in one-pulse
mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

Bit 2 OC1FE: Output compare 1 fast enable

This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is
ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is
5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC
is set to the compare level independently from the result of the comparison. Delay to sample
the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if
the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

Input capture mode

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Bits 15:12 IC2F: Input capture 2 filter

Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
Bits 9:8 CC2S: Capture/compare 2 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bits 7:4 IC1F: Input capture 1 filter
This bit-field defines the frequency used to sample TI1 input and the length of the digital filter
applied to TI1. The digital filter is made of an event counter in which N consecutive events
are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS 1000: fSAMPLING=fDTS/8, N=6
0001: fSAMPLING=fCK_INT, N=2 1001: fSAMPLING=fDTS/8, N=8
0010: fSAMPLING=fCK_INT, N=4 1010: fSAMPLING=fDTS/16, N=5
0011: fSAMPLING=fCK_INT, N=8 1011: fSAMPLING=fDTS/16, N=6
0100: fSAMPLING=fDTS/2, N=6 1100: fSAMPLING=fDTS/16, N=8
0101: fSAMPLING=fDTS/2, N=8 1101: fSAMPLING=fDTS/32, N=5
0110: fSAMPLING=fDTS/4, N=6 1110: fSAMPLING=fDTS/32, N=6
0111: fSAMPLING=fDTS/4, N=8 1111: fSAMPLING=fDTS/32, N=8
Bits 3:2 IC1PSC: Input capture 1 prescaler
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=0 (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S: Capture/Compare 1 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

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16.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2)

Address offset: 0x1C
Reset value: 0x0000
Refer to the above CCMR1 register description.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4CE OC4M[2:0] OC4PE OC4FE OC3CE OC3M[2:0] OC3PE OC3FE
CC4S[1:0] CC3S[1:0]
IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Output compare mode

Bit 15 OC4CE: Output compare 4 clear enable

Bits 14:12 OC4M: Output compare 4 mode
Bit 11 OC4PE: Output compare 4 preload enable
Bit 10 OC4FE: Output compare 4 fast enable
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
Bit 7 OC3CE: Output compare 3 clear enable
Bits 6:4 OC3M: Output compare 3 mode
Bit 3 OC3PE: Output compare 3 preload enable
Bit 2 OC3FE: Output compare 3 fast enable
Bits 1:0 CC3S: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

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Input capture mode

Bits 15:12 IC4F: Input capture 4 filter

Bits 11:10 IC4PSC: Input capture 4 prescaler
Bits 9:8 CC4S: Capture/Compare 4 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC4 channel is configured as output
01: CC4 channel is configured as input, IC4 is mapped on TI4
10: CC4 channel is configured as input, IC4 is mapped on TI3
11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER).
Bits 7:4 IC3F: Input capture 3 filter
Bits 3:2 IC3PSC: Input capture 3 prescaler
Bits 1:0 CC3S: Capture/Compare 3 selection
This bit-field defines the direction of the channel (input/output) as well as the used input.
00: CC3 channel is configured as output
01: CC3 channel is configured as input, IC3 is mapped on TI3
10: CC3 channel is configured as input, IC3 is mapped on TI4
11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER).

16.4.9 TIMx capture/compare enable register (TIMx_CCER)

Address offset: 0x20
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4NP Res. CC4P CC4E CC3NP Res. CC3P CC3E CC2NP Res. CC2P CC2E CC1NP Res. CC1P CC1E

rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 CC4NP: Capture/Compare 4 output Polarity.

Refer to CC1NP description
Bit 14 Reserved, must be kept at reset value.
Bit 13 CC4P: Capture/Compare 4 output Polarity.
refer to CC1P description
Bit 12 CC4E: Capture/Compare 4 output enable.
refer to CC1E description
Bit 11 CC3NP: Capture/Compare 3 output Polarity.
refer to CC1NP description
Bit 10 Reserved, must be kept at reset value.
Bit 9 CC3P: Capture/Compare 3 output Polarity.
refer to CC1P description
Bit 8 CC3E: Capture/Compare 3 output enable.
refer to CC1E description

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Bit 7 CC2NP: Capture/Compare 2 output Polarity.

refer to CC1NP description
Bit 6 Reserved, must be kept at reset value.
Bit 5 CC2P: Capture/Compare 2 output Polarity.
refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable.
refer to CC1E description
Bit 3 CC1NP: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
CC1NP must be kept cleared in this case.
CC1 channel configured as input:
This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P
description.
Bit 2 Reserved, must be kept at reset value.
Bit 1 CC1P: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
00: noninverted/rising edge
Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).
01: inverted/falling edge
Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).
10: reserved, do not use this configuration.
11: noninverted/both edges
Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external
clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration
must not be used for encoder mode.
Bit 0 CC1E: Capture/Compare 1 output enable.
CC1 channel configured as output:
0: Off - OC1 is not active
1: On - OC1 signal is output on the corresponding output pin
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled
1: Capture enabled

Table 78. Output control bit for standard OCx channels

CCxE bit OCx output state
0 Output Disabled (OCx=0, OCx_EN=0)
1 OCx=OCxREF + Polarity, OCx_EN=1

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Note: The state of the external I/O pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO registers.

16.4.10 TIMx counter (TIMx_CNT)

Address offset: 0x24
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CNT[15:0]: Low counter value

16.4.11 TIMx prescaler (TIMx_PSC)

Address offset: 0x28
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).

16.4.12 TIMx auto-reload register (TIMx_ARR)

Address offset: 0x2C
Reset value: 0xFFFF FFFF
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0]: Low Auto-reload value

ARR is the value to be loaded in the actual auto-reload register.
Refer to the Section 16.3.1: Time-base unit on page 373 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

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16.4.13 TIMx capture/compare register 1 (TIMx_CCR1)

Address offset: 0x34
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1[15:0]
rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r

Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value

If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.

If channel CC1is configured as input:

CCR1 is the counter value transferred by the last input capture 1 event (IC1). The
TIMx_CCR1 register is read-only and cannot be programmed.

16.4.14 TIMx capture/compare register 2 (TIMx_CCR2)

Address offset: 0x38
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2[15:0]
rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r

Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value

If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2). The
TIMx_CCR2 register is read-only and cannot be programmed.

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16.4.15 TIMx capture/compare register 3 (TIMx_CCR3)

Address offset: 0x3C
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR3[15:0]
rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r

Bits 15:0 CCR3[15:0]: Low Capture/Compare value

If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register
(bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC3 output.
If channel CC3is configured as input:
CCR3 is the counter value transferred by the last input capture 3 event (IC3). The
TIMx_CCR3 register is read-only and cannot be programmed.

16.4.16 TIMx capture/compare register 4 (TIMx_CCR4)

Address offset: 0x40
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR4[15:0]
rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r

Bits 15:0 CCR4[15:0]: Low Capture/Compare value

If CC4 channel is configured as output (CC4S bits):
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register
(bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.
If CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):
CCR4 is the counter value transferred by the last input capture 4 event (IC4). The
TIMx_CCR4 register is read-only and cannot be programmed.

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RM0377 General-purpose timers (TIM2/TIM3)

16.4.17 TIMx DMA control register (TIMx_DCR)

Address offset: 0x48
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. DBL[4:0] Res. Res. Res. DBA[4:0]

rw rw rw rw rw rw rw rw rw rw

Bits 15:13 Reserved, must be kept at reset value.

Bits 12:8 DBL[4:0]: DMA burst length
This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address).
00000: 1 transfer,
00001: 2 transfers,
00010: 3 transfers,
...
10001: 18 transfers.
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DBA[4:0]: DMA base address
This 5-bit vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this
case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.

16.4.18 TIMx DMA address for full transfer (TIMx_DMAR)

Address offset: 0x4C
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAB[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 DMAB[15:0]: DMA register for burst accesses

A read or write operation to the DMAR register accesses the register located at the address
(TIMx_CR1 address) + (DBA + DMA index) x 4
where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIMx_DCR register, DMA index is automatically controlled by the
DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR).

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Example of how to use the DMA burst feature

In this example the timer DMA burst feature is used to update the contents of the CCRx
registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers.
This is done in the following steps:
1. Configure the corresponding DMA channel as follows:
– DMA channel peripheral address is the DMAR register address
– DMA channel memory address is the address of the buffer in the RAM containing
the data to be transferred by DMA into CCRx registers.
– Number of data to transfer = 3 (See note below).
– Circular mode disabled.
2. Configure the DCR register by configuring the DBA and DBL bit fields as follows:
DBL = 3 transfers, DBA = 0xE.
3. Enable the TIMx update DMA request (set the UDE bit in the DIER register).
4. Enable TIMx
5. Enable the DMA channel
For code example, refer to A.9.21: DMA burst feature code example.
Note: This example is for the case where every CCRx register to be updated once. If every CCRx
register is to be updated twice for example, the number of data to transfer should be 6. Let's
take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and
data6. The data is transferred to the CCRx registers as follows: on the first update DMA
request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to
CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is
transferred to CCR3 and data6 is transferred to CCR4.

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RM0377 General-purpose timers (TIM2/TIM3)

16.4.19 TIM2 option register (TIM2_OR)

Address offset: 0x50
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI4_RMP ETR_RMP
rw rw rw rw rw

Bits 15:5 Reserved, must be kept at reset value.

Bits 4:3 TI4_RMP: Internal trigger (TI4 connected to TIM2_CH4) remap
This bit is set and cleared by software.
01: TIM2 TI4 input connected to COMP2_OUT
10: TIM2 TI4 input connected to COMP1_OUT
others: TIM2 TI4 input connected to ORed GPIOs. Refer to the Alternate function mapping
table in the device datasheets.
Bits 2:0 ETR_RMP: Timer2 ETR remap
This bit is set and cleared by software.
111: TIM2 ETR input is connected to COMP1_OUT
110: TIM2 ETR input is connected to COMP2_OUT
101: TIM2 ETR input is connected to LSE
011: TIM2 ETR input is connected to HSI16 when HSI16OUTEN bit is set in Clock control
register (RCC_CR) (except for category 3 devices)
others: TIM2 ETR input is connected to ORed GPIOs. Refer to the Alternate function
mapping table in the device datasheets

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16.4.20 TIM3 option register (TIM3_OR)

Address offset: 0x50
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI_RMP ETR_RMP
rw rw rw rw rw

Bits 15:5 Reserved, must be kept at reset value.

Bit 4 TI_RMP: Timer3 remapping on PC9
This bit is set and cleared by software.
1: TIM3_CH4 selected
0: Reserved
Bit 3 TI_RMP: Timer3 remap on PB5
This bit is set and cleared by software.
1: TIM3_CH2 selected
0: TIM22_CH2 selected
Bit 2 TI_RMP: Timer3 TI remap
This bit is set and cleared by software.
1: TIM3_TI1 input is connected to PE3, PA6, PC6 or PB4
0: Reserved
Bits 1:0 ETR_RMP: Timer3 ETR remap
These bits are set and cleared by software.
others configurations: TIM3_ETR input is connected to PE2 or PD2

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RM0377 General-purpose timers (TIM2/TIM3)

16.5 TIMx register map

TIMx registers are mapped as described in the table below:

Table 79. TIM2/3 register map and reset values

Offset Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ARPE

UDIS
OPM

CEN
URS
Res.

Res.

Res.

Res.

Res.

Res.

DIR
TIMx_CR1 CKD [1:0] CMS[1:0]
0x00
Reset value 0 0 0 0 0 0 0 0 0 0

CCDS
TI1S
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.
TIMx_CR2 MMS[2:0]
0x04
Reset value ETPS [1:0] 0 0 0 0 0

MSM
ECE

Res.
ETP

TIMx_SMCR ETF[3:0] TS[2:0] SMS[2:0]

0x08

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CC4DE

CC3DE

CC2DE

CC1DE

CC4IE

CC3IE

CC2IE

CC1IE
UDE
Res.

Res.

Res.

Res.
TDE

UIE
TIE
TIMx_DIER
0x0C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0
CC4OF

CC3OF

CC2OF

CC1OF

CC4IF

CC3IF

CC2IF

CC1IF
Res.

Res.

Res.

Res.

Res.

Res.

UIF
TIF
TIMx_SR
0x10

Reset value 0 0 0 0 0 0 0 0 0 0

CC4G

CC3G

CC2G

CC1G
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

UG
TIMx_EGR
TG

0x14
Reset value 0 0 0 0 0 0
TIMx_CCMR1
OC2CE

OC1CE
OC2PE

OC1PE
OC2FE

OC1FE
OC2M OC1M
Output CC2S [1:0] CC1S [1:0]
[2:0] [2:0]
Compare mode
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x18
TIMx_CCMR1 IC2 IC1
Input Capture IC2F[3:0] PSC CC2S [1:0] IC1F[3:0] PSC CC1S [1:0]
mode [1:0] [1:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TIMx_CCMR2
OC4CE

OC3CE
OC4PE

OC3PE
OC4FE

OC3FE

OC4M OC3M
Output CC4S [1:0] CC3S [1:0]
[2:0] [2:0]
Compare mode
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x1C
TIMx_CCMR2 IC4 IC3
Input Capture IC4F[3:0] PSC CC4S [1:0] IC3F[3:0] PSC CC3S [1:0]
mode [1:0] [1:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CC4NP

CC3NP

CC2NP

CC1NP
CC4P

CC4E

CC3P

CC3E

CC2P

CC2E

CC1P

CC1E
Res.

Res.

Res.

Res.

TIMx_CCER
0x20

Reset value 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_CNT CNT[15:0]
0x24
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_PSC PSC[15:0]
0x28
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 79. TIM2/3 register map and reset values (continued)

Offset Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TIMx_ARR ARR[15:0]
0x2C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x30 Res.

TIMx_CCR1 CCR1[15:0]
0x34
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_CCR2 CCR2[15:0]
0x38
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_CCR3 CCR3[15:0]
0x3C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_CCR4 CCR4[15:0]
0x40
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x44 Res.
Res.

Res.

Res.

Res.

Res.

Res.
TIMx_DCR DBL[4:0] DBA[4:0]
0x48
Reset value 0 0 0 0 0 0 0 0 0 0

TIMx_DMAR DMAB[15:0]
0x4C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ETR_RMP
TI4_RMP
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM2_OR
0x50

Reset value 0 0 0 0
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM3_OR TI_RMP ETR_RMP

0x50
Reset value 0 0 0 0 0

Refer to Section 2.2 on page 51 for the register boundary addresses.

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RM0377 General-purpose timers (TIM21/22)

17 General-purpose timers (TIM21/22)

17.1 Introduction
The TIM21/22 general-purpose timers consist of a 16-bit auto-reload counter driven by a
programmable prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The TIM21/22 timers are completely independent, and do not share any resources. They
can be synchronized together as described in Section 17.3.14.

17.2 TIM21/22 main features

17.2.1 TIM21/22 main features

The features of the TIM21/22 general-purpose timers include:
• 16-bit up, down, up/down, auto-reload counter
• 16-bit programmable prescaler used to divide the counter clock frequency by any factor
between 1 and 65535 (can be changed “on the fly”)
• Up to 2 independent channels for:
– Input capture
– Output compare
– PWM generation (edge- and center-aligned mode)
– One-pulse mode output
• Synchronization circuit to control the timer with external signals and to interconnect
several timers together
• Interrupt generation on the following events:
– Update: counter overflow/underflow, counter initialization (by software or internal
trigger)
– Trigger event (counter start, stop, initialization or count by internal trigger)
– Input capture
– Output compare

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Figure 123. General-purpose timer block diagram (TIM21/22)

Internal clock (CK_INT)

ETRF
Trigger
ETR ETRP controller
TIMx_ETR Polarity selection & edge Input filter TRGO

TGI
ITR0 ITR Slave
ITR1 Reset, enable, up, count
TRC TRGI controller
mode
TI1F_ED
Encoder
interface
TI1FP1
TI2FP2

U
Auto-reload register UI
Stop, Clear U
CK_PSC PSC CK_CNT +/- CNT counter
prescaler
CC1I U CC1I
TI1FP1 OC1REF OC1
TI1 Input filter & TI1FP2 IC1 IC1PS Capture/Compare 1 register Output
TIMx_CH1 Prescaler TIMx_CH1
edge detector control
TRC CC2I
U CC2I
TI2FP1
TIMx_CH2
TI2 Input filter & IC2 IC2PS Capture/Compare 2 register OC2REF Output OC2
edge detector TI2FP2 Prescaler control TIMx_CH2
TRC

Notes:
Preload registers transferred ETRF
Reg
to active registers on U event
according to control bit
Event

Interrupt MSv33704V2

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RM0377 General-purpose timers (TIM21/22)

17.3 TIM21/22 functional description

17.3.1 Timebase unit

The main block of the timer is a 16-bit counter with its related auto-reload register. The
counters counts up, down or both up and down but also down or both up and down. The
counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The timebase unit includes:
• Counter register (TIMx_CNT)
• Prescaler register (TIMx_PSC)
• Auto-reload register (TIMx_ARR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register are transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter
reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be
generated by software. The generation of the update event is described in detailed for each
configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1
register.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 125 and Figure 126 give some examples of the counter behavior when the prescaler
ratio is changed on the fly.

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Figure 124. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

Update event (UEV)

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1
MS31076V2

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RM0377 General-purpose timers (TIM21/22)

Figure 125. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

F7 F8 F9 FA FB FC 00 01
Counter register

Update event (UEV)

0 3
Prescaler control register

Write a new value in TIMx_PSC

0 3
Prescaler buffer

0 0 1 2 3 0 1 2 3
Prescaler counter

MS31077V2

17.3.2 Counter modes

Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller on TIM21/22) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.

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When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The auto-reload shadow register is updated with the preload value (TIMx_ARR),
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

Figure 126. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31078V2

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RM0377 General-purpose timers (TIM21/22)

Figure 127. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0000 0001 0002 0003

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31079V2

Figure 128. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0035 0036 0000 0001

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31080V2

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Figure 129. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

Figure 130. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FF 36

Write a new value in TIMx_ARR

MS31082V2

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RM0377 General-purpose timers (TIM21/22)

Figure 131. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
F5 36
register

Auto-reload shadow
register F5 36

Write a new value in TIMx_ARR MS31083V2

Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
An Update event can be generate at each counter underflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
• The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one.

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The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

Figure 132. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

Counter underflow
(cnt_udf)

Update event (UEV)

Update interrupt flag

(UIF)

MS31184V1

Figure 133. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0002 0001 0000 0036 0035 0034 0033

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31185V1

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Figure 134. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0001 0000 0000 0001

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31186V1

Figure 135. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 00 36

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31187V1

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Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register) – 1, generates a counter overflow event, then counts from the auto-
reload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to
'00'. The Output compare interrupt flag of channels configured in output is set when: the
counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center
aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3,
CMS = "11").
In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupt when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
• The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
• The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the auto-
reload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.

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Figure 136. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 04 03 02 01 00 01 02 03 04 05 06 05 04 03

Counter underflow

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31189V1

1. Here, center-aligned mode 1 is used (for more details refer to Section 17.4.1: TIM21/22 control register 1
(TIMx_CR1) on page 475).

Figure 137. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0003 0002 0001 0000 0001 0002 0003

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31190V1

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Figure 138. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0035

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Note: Here, center_aligned mode 2 or 3 is updated with an UIF on overflow

MS31191V1

1. Center-aligned mode 2 or 3 is used with an UIF on overflow.

Figure 139. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 20 1F 01 00

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31192V1

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Figure 140. Counter timing diagram, Update event with ARPE=1 (counter underflow)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 06 05 04 03 02 01 00 01 02 03 04 05 06 07

Counter underflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FD 36

Write a new value in TIMx_ARR

Auto-reload active
register FD 36

MS31193V1

Figure 141. Counter timing diagram, Update event with ARPE=1 (counter overflow)

CK_PSC

CEN

Timer clock = CK_CNT

Counter register F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
FD 36
register

Write a new value in TIMx_ARR

Auto-reload active
register FD 36

MS31194V1

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17.3.3 Clock selection

The counter clock can be provided by the following clock sources:
• Internal clock (CK_INT)
• External clock mode1: external input pin (TIx)
• External clock mode2: external trigger input (ETR connected internally to LSE)
• Internal trigger inputs (ITRx): connecting the trigger output from another timer. Refer to
Section : Using one timer as prescaler for another timer for more details.

Internal clock source (CK_INT)

The internal clock source is selected when the slave mode controller is disabled
(SMS=’000’). The CEN bit in the TIMx_CR1 register and the UG bit in the TIMx_EGR
register are then used as control bits and can be changed only by software (except for UG
which remains cleared). As soon as the CEN bit is programmed to 1, the prescaler is
clocked by the internal clock CK_INT.
Figure 142 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.

Figure 142. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

UG

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

MS31085V2

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External clock source mode 1

This mode is selected when SMS=’111’ in the TIMx_SMCR register. The counter can count
at each rising or falling edge on a selected input.

Figure 143. TI2 external clock connection example

TIMx_SMCR
TS[2:0]

or TI2F or
TI1F or Encoder
ITRx mode
0xx
TI1_ED
100 TRGI External clock
TI1FP1 mode 1 CK_PSC
TI2F_Rising 101
TI2 Edge 0 TI2FP2 ETRF External clock
Filter 110
detector 1 ETRF mode 2
TI2F_Falling 111
CK_INT Internal clock
mode
ICF[3:0] CC2P (internal clock)

TIMx_CCMR1 TIMx_CCER
ECE SMS[2:0]
TIMx_SMCR

MS31196V1

For example, to configure the upcounter to count in response to a rising edge on the TI2
input, use the following procedure:
1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in
the TIMx_CCMR1 register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=’0000’).
3. Select the rising edge polarity by writing CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER
register.
4. Configure the timer in external clock mode 1 by writing SMS=’111’ in the TIMx_SMCR
register.
5. Select TI2 as the trigger input source by writing TS=’110’ in the TIMx_SMCR register.
6. Enable the counter by writing CEN=’1’ in the TIMx_CR1 register.
For code example, refer to A.9.1: Upcounter on TI2 rising edge code example.
Note: The capture prescaler is not used for triggering, so it does not need to be configured.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.

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Figure 144. Control circuit in external clock mode 1

TI2

CNT_EN

Counter clock = CK_CNT = CK_PSC

Counter register 34 35 36

TIF

Write TIF=0

MS31087V2

External clock source mode 2

This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 145 gives an overview of the external trigger input block.

Figure 145. External trigger input block

or TI2F or
TI1F or Encoder
mode

TRGI External clock

ETR mode 1 CK_PSC
0
Divider ETRP
ETR pin Filter ETRF External clock
/1, /2, /4, /8
1 fDTS downcounter mode 2
CK_INT Internal clock
ETP ETPS[1:0] ETF[3:0] mode
(internal clock)
TIMx_SMCR TIMx_SMCR TIMx_SMCR

ECE SMS[2:0]
TIMx_SMCR

MS33116V1

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For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
For code example, refer to A.9.2: Up counter on each 2 ETR rising edges code example.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.

Figure 146. Control circuit in external clock mode 2

f CK_INT

CNT_EN

ETR

ETRP

ETRF

Counter clock =
CK_INT =CK_PSC

Counter register 34 35 36

MS33111V2

17.3.4 Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 147 to Figure 149 give an overview of one capture/compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

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Figure 147. Capture/compare channel (example: channel 1 input stage)

TI1F_ED
To the slave mode controller

TI1 TI1F_Rising
Filter TI1F Edge 0 TI1FP1
fDTS downcounter TI1F_Falling 01
detector 1
TI2FP1 IC1 Divider IC1PS
10
/1, /2, /4, /8
ICF[3:0] CC1P/CC1NP TRC
11
TIMx_CCMR1 TIMx_CCER (from slave mode
TI2F_Rising controller)
0
(from channel 2)
CC1S[1:0] ICPS[1:0] CC1E
TI2F_Falling
1
(from channel 2) TIMx_CCMR1 TIMx_CCER

MS33115V1

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.

Figure 148. Capture/compare channel 1 main circuit

APB Bus

MCU-peripheral interface
(if 16-bit)

8 8
high

S write CCR1H
low

Read CCR1H S write_in_progress

read_in_progress write CCR1L
Read CCR1L Capture/compare preload register R
R Output CC1S[1]
capture_transfer compare_transfer mode
CC1S[0]
CC1S[1] Input
mode OC1PE
CC1S[0] Capture/compare shadow register OC1PE
UEV
Comparator (from time TIMx_CCMR1
IC1PS Capture base unit)
CC1E CNT>CCR1
Counter CNT=CCR1
CC1G
TIMx_EGR
MS31089V3

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Figure 149. Output stage of capture/compare channel (channel 1 and 2)

ETRF
To the master
mode controller

CNT > CCR2

Output OCx_REF 0 Output OCx
CNT = CCR2 mode enable
controller 1 circuit

CCxP
OCxM[2:0] TIMx_CCER CCxE

TIMx_CCMR1 TIMx_CCER
MSv33714V1

The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

17.3.5 Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register. CCxOF is cleared when it is written with 0.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
1. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to ‘01’ in the TIMx_CCMR1 register. As soon as CC1S becomes different from ‘00’,
the channel is configured in input mode and the TIMx_CCR1 register becomes read-
only.
2. Program the appropriate input filter duration in relation with the signal connected to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been

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detected (sampled at fDTS frequency). Then write IC1F bits to ‘0011’ in the
TIMx_CCMR1 register.
3. Select the edge of the active transition on the TI1 channel by programming CC1P and
CC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case).
4. Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIMx_CCMR1 register).
5. Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
6. If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register.
For code example, refer to A.9.3: Input capture configuration code example.
When an input capture occurs:
• The TIMx_CCR1 register gets the value of the counter on the active transition.
• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
• An interrupt is generated depending on the CC1IE bit.
For code example, refer to A.9.4: Input capture data management code example.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note: IC interrupt requests can be generated by software by setting the corresponding CCxG bit in
the TIMx_EGR register.

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17.3.6 PWM input mode

This mode is a particular case of input capture mode. The procedure is the same except:
• Two ICx signals are mapped on the same TIx input.
• These 2 ICx signals are active on edges with opposite polarity.
• One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
For example, one can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
1. Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1
register (TI1 selected).
2. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge).
3. Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’ in the TIMx_CCMR1
register (TI1 selected).
4. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): program the
CC2P and CC2NP bits to ‘11’ (active on falling edge).
5. Select the valid trigger input: write the TS bits to ‘101’ in the TIMx_SMCR register
(TI1FP1 selected).
6. Configure the slave mode controller in reset mode: write the SMS bits to ‘100’ in the
TIMx_SMCR register.
7. Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.
For code example, refer to A.9.5: PWM input configuration code example.

Figure 150. PWM input mode timing

1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only
TI1FP1 and TI2FP2 are connected to the slave mode controller.

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17.3.7 Forced output mode

In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, one just needs to write
‘101’ in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=’0’ (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to ‘100’ in the
TIMx_CCMRx register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt requests can be sent accordingly. This is
described in the output compare mode section below.

17.3.8 Output compare mode

This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
1. Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=’000’), be set
active (OCxM=’001’), be set inactive (OCxM=’010’) or can toggle (OCxM=’011’) on
match.
2. Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
3. Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One-pulse mode).
Procedure:
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
– Write OCxM = ‘011’ to toggle OCx output pin when CNT matches CCRx
– Write OCxPE = ‘0’ to disable preload register
– Write CCxP = ‘0’ to select active high polarity
– Write CCxE = ‘1’ to enable the output
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
For code example, refer to A.9.7: Output compare configuration code example.

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The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 151.

Figure 151. Output compare mode, toggle on OC1

Write B201h in the CC1R register

TIM1_CNT 0039 003A 003B B200 B201

TIM1_CCR1 003A B201

OC1REF= OC1

Match detected on CCR1

Interrupt generated if enabled

MS31092V1

17.3.9 PWM mode

Pulse Width Modulation mode allows to generate a signal with a frequency determined by
the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing the OCxM bits in the TIMx_CCMRx register. The corresponding preload
register must be enabled by setting the OCxPE bit in the TIMx_CCMRx register, and
eventually the auto-reload preload register (in upcounting or center-aligned modes) by
setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, all registers must be initialized by setting the UG bit in
the TIMx_EGR register.
The OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register.
It can be programmed as active high or active low. The OCx output is enabled by the CCxE
bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more
details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CNT ≤ TIMx_CCRx.

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The timer is able to generate PWM in edge-aligned mode only since the counter is
upcounting.
• Upcounting configuration
Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the
Upcounting mode on page 443.
In the following example, we consider PWM mode 1. The reference PWM signal
OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the
compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR)
then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’.
Figure 152 shows some edge-aligned PWM waveforms in an example where
TIMx_ARR=8.
For code example, refer to A.9.8: Edge-aligned PWM configuration example.

Figure 152. Edge-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 0 1

OCXREF
CCRx=4
CCxIF

OCXREF
CCRx=8
CCxIF

OCXREF ‘1’
CCRx>8
CCxIF

OCXREF ‘0’
CCRx=0
CCxIF

MS31093V1

• Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the
Downcounting mode on page 447
In PWM mode 1, the reference signal OCxRef is low as long as
TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is
greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM
is not possible in this mode.

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PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals).
The compare flag is set when the counter counts up, when it counts down or both when it
counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
the Center-aligned mode (up/down counting) on page 450.
Figure 153 shows some center-aligned PWM waveforms in an example where:
• TIMx_ARR=8,
• PWM mode is the PWM mode 1,
• The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.
For code example, refer to A.9.9: Center-aligned PWM configuration example.

Figure 153. Center-aligned PWM waveforms (ARR=8)

Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1

OCxREF
CCRx = 4

CCxIF CMS=01
CMS=10
CMS=11

OCxREF
CCRx=7

CMS=10 or 11
CCxIF
‘1’
OCxREF
CCRx=8

CCxIF CMS=01
CMS=10
CMS=11
‘1’
OCxREF
CCRx>8

CCxIF CMS=01
CMS=10
CMS=11
‘0’
OCxREF
CCRx=0

CCxIF CMS=01
CMS=10
CMS=11

AI14681b

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Hints on using center-aligned mode

• When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
• Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
– The direction is not updated if a value greater than the auto-reload value is written
in the counter (TIMx_CNT>TIMx_ARR). For example, if the counter was counting
up, it continues to count up.
– The direction is updated if 0 or the TIMx_ARR value is written in the counter but no
Update Event UEV is generated.
• The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.

17.3.10 Clearing the OCxREF signal on an external event

The OCxREF signal for a given channel can be driven Low by applying a High level to the
ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The
OCxREF signal remains Low until the next update event, UEV, occurs.
This function can only be used in output compare and PWM modes, and does not work in
forced mode.
For example, the ETR signal can be connected to the output of a comparator to be used for
current handling. In this case, the ETR must be configured as follow:
1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR
register set to ‘00’.
2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to
‘0’.
3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be
configured according to the user needs.
For code example, refer to A.9.10: ETR configuration to clear OCxREF code example.
Figure 154 shows the behavior of the OCxREF signal when the ETRF Input becomes High,
for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in
PWM mode.

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Figure 154. Clearing TIMx OCxREF

(CCRx)

Counter (CNT)

ETRF

OCxREF
(OCxCE = ‘0’)

OCxREF
(OCxCE = ‘1’)

OCxREF_CLR OCxREF_CLR
becomes high still high
MS33105V1

Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at
the next counter overflow.

17.3.11 One-pulse mode

One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. One-pulse mode is selected
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be as follows:
CNT < CCRx ≤ ARR (in particular, 0 < CCRx)

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Figure 155. Example of one pulse mode

TI2

OC1REF
OC1

TIM1_ARR
Counter

TIM1_CCR1

0
tDELAY tPULSE t

MS31099V1

For example one may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Use TI2FP2 as trigger 1:
1. Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register.
2. TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP = ‘0’ in the TIMx_CCER
register.
3. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in
the TIMx_SMCR register.
4. TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register
(trigger mode).
The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
• The tDELAY is defined by the value written in the TIMx_CCR1 register.
• The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1+1).
• Let’s say one want to build a waveform with a transition from ‘0’ to ‘1’ when a compare
match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload
value. To do this PWM mode 2 must be enabled by writing OC1M=’111’ in the
TIMx_CCMR1 register. Optionally the preload registers can be enabled by writing
OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this
case one has to write the compare value in the TIMx_CCR1 register, the auto-reload
value in the TIMx_ARR register, generate an update by setting the UG bit and wait for
external trigger event on TI2. CC1P is written to ‘0’ in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
For code example, refer to A.9.16: One-Pulse mode code example.

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Since only 1 pulse (Single mode) is needed, a 1 must be written in the OPM bit in the
TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over
from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0',
so the Repetitive Mode is selected.

Particular case: OCx fast enable

In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If one wants to output a waveform with the minimum delay, the OCxFE bit can be set in the
TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
For code example, refer to A.9.16: One-Pulse mode code example.

17.3.12 Encoder interface mode

To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter
is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if
it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER
register. CC1NP and CC2NP must be kept cleared. When needed, the input filter can be
programmed as well. CC1NP and CC2NP must be kept low.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 80. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware
accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So the
TIMx_ARR must be configured before starting. In the same way, the capture, compare,
prescaler, trigger output features continue to work as normal.
In this mode, the counter is modified automatically following the speed and the direction of
the quadrature encoder and its content, therefore, always represents the encoder’s position.
The count direction correspond to the rotation direction of the connected sensor. The table
summarizes the possible combinations, assuming TI1 and TI2 do not switch at the same
time.

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Table 80. Counting direction versus encoder signals

Level on opposite TI1FP1 signal TI2FP2 signal
Active edge signal (TI1FP1 for
TI2, TI2FP2 for TI1) Rising Falling Rising Falling

Counting on High Down Up No Count No Count

TI1 only Low Up Down No Count No Count

Counting on High No Count No Count Up Down

TI2 only Low No Count No Count Down Up

Counting on High Down Up Up Down

TI1 and TI2 Low Up Down Down Up

An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoder’s
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
Figure 156 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are
selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:
• CC1S= 01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1)
• CC2S= 01 (TIMx_CCMR2 register, TI2FP2 mapped on TI2)
• CC1P and CC1NP = ‘0’ (TIMx_CCER register, TI1FP1 noninverted, TI1FP1=TI1)
• CC2P and CC2NP = ‘0’ (TIMx_CCER register, TI2FP2 noninverted, TI2FP2=TI2)
• SMS= 011 (TIMx_SMCR register, both inputs are active on both rising and falling
edges)
• CEN= 1 (TIMx_CR1 register, Counter is enabled)
For code example, refer to A.9.11: Encoder interface code example.

Figure 156. Example of counter operation in encoder interface mode

forward jitter backward jitter forward

TI1

TI2

Counter

up down up

MS33107V1

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Figure 157 gives an example of counter behavior when TI1FP1 polarity is inverted (same
configuration as above except CC1P=1).

Figure 157. Example of encoder interface mode with TI1FP1 polarity inverted

forward jitter backward jitter forward

TI1

TI2

Counter

down up down

MS33108V1

The timer, when configured in Encoder Interface mode provides information on the sensor’s
current position. Dynamic information can be obtained (speed, acceleration, deceleration)
by measuring the period between two encoder events using a second timer configured in
capture mode. The output of the encoder which indicates the mechanical zero can be used
for this purpose. Depending on the time between two events, the counter can also be read
at regular times. This can be done by latching the counter value into a third input capture
register if available (then the capture signal must be periodic and can be generated by
another timer). when available, it is also possible to read its value through a DMA request
generated by a Real-Time clock.

17.3.13 TIM21/22 external trigger synchronization

The TIM21/22 timers can be synchronized with an external trigger in several modes: Reset
mode, Gated mode and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
1. Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=’0000’). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits
select the input capture source only, CC1S = ‘01’ in the TIMx_CCMR1 register.
Program CC1P and CC1NP to ‘00’ in TIMx_CCER register to validate the polarity (and
detect rising edges only).
2. Configure the timer in reset mode by writing SMS=’100’ in TIMx_SMCR register. Select
TI1 as the input source by writing TS=’101’ in TIMx_SMCR register.
3. Start the counter by writing CEN=’1’ in the TIMx_CR1 register.
For code example, refer to A.9.12: Reset mode code example.

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The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if
enabled (depending on the TIE bit in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.

Figure 158. Control circuit in reset mode

TI1

UG

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03

TIF

MS31401V2

Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.
In the following example, the upcounter counts only when TI1 input is low:
1. Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC1F=’0000’). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC1S bits
select the input capture source only, CC1S=’01’ in TIMx_CCMR1 register. Program
CC1P=’1’ and CC1NP= ‘0’ in TIMx_CCER register to validate the polarity (and detect
low level only).
2. Configure the timer in gated mode by writing SMS=’101’ in TIMx_SMCR register.
Select TI1 as the input source by writing TS=’101’ in TIMx_SMCR register.
3. Enable the counter by writing CEN=’1’ in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=’0’, whatever is the trigger input level).
For code example, refer to A.9.13: Gated mode code example.
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.

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Figure 159. Control circuit in gated mode

TI1

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 30 31 32 33 34 35 36 37 38

TIF

Write TIF=0

MS31402V1

Slave mode: Trigger mode

The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
1. Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
– ETF = 0000: no filter
– ETPS = 00: prescaler disabled
– ETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.
1. Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we do not need any filter, so we keep IC2F=’0000’). The capture
prescaler is not used for triggering, so it does not need to be configured. The CC2S bits
are configured to select the input capture source only, CC2S=’01’ in TIMx_CCMR1
register. Program CC2P=’1’ and CC2NP=’0’ in TIMx_CCER register to validate the
polarity (and detect low level only).
2. Configure the timer in trigger mode by writing SMS=’110’ in TIMx_SMCR register.
Select TI2 as the input source by writing TS=’110’ in TIMx_SMCR register.
For code example, refer to A.9.14: Trigger mode code example.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.

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Figure 160. Control circuit in trigger mode

TI2

cnt_en

Counter clock = ck_cnt = ck_psc

Counter register 34 35 36 37 38

TIF

MS31403V1

17.3.14 Timer synchronization (TIM21/22)

The timers are linked together internally for timer synchronization or chaining. Refer to
Section 16.3.15: Timer synchronization on page 408 for details.

17.3.15 Debug mode

When the microcontroller enters debug mode (Cortex®-M0+ core halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers,
watchdog, bxCAN and I2C.

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17.4 TIM21/22 registers

Refer to Section 1.2 on page 45 for a list of abbreviations used in register descriptions.
The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

17.4.1 TIM21/22 control register 1 (TIMx_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN

rw rw rw rw rw rw rw rw rw rw

Bits 15:10 Reserved, must be kept at reset value.

Bits 9:8 CKD: Clock division
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and
sampling clock used by the digital filters (TIx),
00: tDTS = tCK_INT
01: tDTS = 2 × tCK_INT
10: tDTS = 4 × tCK_INT
11: Reserved
Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
Bits 6:5 CMS[1:0]: Center-aligned mode selection
00: Edge-aligned mode. The counter counts up or down depending on the direction bit
(DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare
interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set
both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as
the counter is enabled (CEN=1).
Bit 4 DIR: Direction
0: Counter used as upcounter
1: Counter used as downcounter
Bit 3 OPM: One-pulse mode
0: Counter is not stopped on the update event
1: Counter stops counting on the next update event (clearing the CEN bit).

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Bit 2 URS: Update request source

This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generates an update interrupt if enabled:
– Counter overflow
– Setting the UG bit
1: Only counter overflow generates an update interrupt if enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable update event (UEV) generation.
0: UEV enabled. An UEV is generated by one of the following events:
– Counter overflow
– Setting the UG bit
Buffered registers are then loaded with their preload values.
1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC,
CCRx). The counter and the prescaler are reinitialized if the UG bit is set.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
CEN is cleared automatically in one-pulse mode, when an update event occurs.

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17.4.2 TIM21/22 control register 2 (TIMx_CR2)

Address offset: 0x04
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS[2:0] Res. Res. Res. Res.

rw rw rw

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 MMS: Master mode selection
These bits allow to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer is
enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR
register).
010: Update - The update event is selected as trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be
set (even if it was already high), as soon as a capture or a compare match occurred.
(TRGO)
100: Compare - OC1REF signal is used as trigger output (TRGO)
101: Compare - OC2REF signal is used as trigger output (TRGO)
110: Reserved
111: Reserved
Bits 3:0 Reserved, must be kept at reset value.

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17.4.3 TIM21/22 slave mode control register (TIMx_SMCR)

Address offset: 0x08
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ETP ECE ETPS[1:0] ETF[3:0] MSM TS[2:0] Res. SMS[2:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 ETP: External trigger polarity

This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge.
1: ETR is inverted, active at low level or falling edge.
Bit 14 ECE: External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF
signal.
Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI
connected to ETRF (SMS=111 and TS=111).
It is possible to simultaneously use external clock mode 2 with the following slave
modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be
connected to ETRF in this case (TS bits must not be 111).
If external clock mode 1 and external clock mode 2 are enabled at the same time, the
external clock input is ETRF.
Bits 13:12 ETPS[1:0]: External trigger prescaler
External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A
prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external
clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
10: ETRP frequency divided by 4
11: ETRP frequency divided by 8

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Bits 11:8 ETF[3:0]: External trigger filter

This bit-field then defines the frequency used to sample ETRP signal and the length of the
digital filter applied to ETRP. The digital filter is made of an event counter in which N
consecutive events are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING=fCK_INT, N=2
0010: fSAMPLING=fCK_INT, N=4
0011: fSAMPLING=fCK_INT, N=8
0100: fSAMPLING=fDTS/2, N=6
0101: fSAMPLING=fDTS/2, N=8
0110: fSAMPLING=fDTS/4, N=6
0111: fSAMPLING=fDTS/4, N=8
1000: fSAMPLING=fDTS/8, N=6
1001: fSAMPLING=fDTS/8, N=8
1010: fSAMPLING=fDTS/16, N=5
1011: fSAMPLING=fDTS/16, N=6
1100: fSAMPLING=fDTS/16, N=8
1101: fSAMPLING=fDTS/32, N=5
1110: fSAMPLING=fDTS/32, N=6
1111: fSAMPLING=fDTS/32, N=8

Bit 7 MSM: Master/Slave mode

0: No action
1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful in
order to synchronize several timers on a single external event.

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Bits 6:4 TS: Trigger selection

This bitfield selects the trigger input to be used to synchronize the counter.
000: Internal Trigger 0 (ITR0)
001: Internal Trigger 1 (ITR1)
010: Reserved
011: Reserved
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: Reserved.
See Table 81: TIMx Internal trigger connection on page 480 for more details on the meaning
of ITRx for each timer.
Note: These bits must be changed only when they are not used (e.g. when SMS=’000’) to
avoid wrong edge detections at the transition.
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 SMS: Slave mode selection
When external signals are selected, the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input control register and Control register
descriptions.
000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal
clock
001: Encoder mode 1
010: Encoder mode 2
011: Encoder mode 3
100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers
101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Counter starts and stops
are both controlled
110: Trigger mode - The counter starts on a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled
111: External Clock Mode 1
Note: The Gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
Gated mode checks the level of the trigger signal.

Table 81. TIMx Internal trigger connection(1)

Slave TIM ITR0 (TS = 000) ITR1 (TS = 001)

TIM21 TIM2 TIM22

TIM22 TIM21 TIM2
1. When a timer is not present in the product, the corresponding trigger ITRx is not available.

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17.4.4 TIM21/22 Interrupt enable register (TIMx_DIER)

Address offset: 0x0C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. TIE Res. Res. Res. CC2IE CC1IE UIE

rw rw rw rw

Bits 15:7 Reserved, must be kept at reset value.

Bit 6 TIE: Trigger interrupt enable
0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
Bits 5:3 Reserved, must be kept at reset value.
Bit 2 CC2IE: Capture/Compare 2 interrupt enable
0: CC2 interrupt disabled.
1: CC2 interrupt enabled.
Bit 1 CC1IE: Capture/Compare 1 interrupt enable
0: CC1 interrupt disabled.
1: CC1 interrupt enabled.
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled.
1: Update interrupt enabled.

17.4.5 TIM21/22 status register (TIMx_SR)

Address offset: 0x10
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. CC2OF CC1OF Res. Res. TIF Res. Res. Res. CC2IF CC1IF UIF

rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0

Bits 15:11 Reserved, must be kept at reset value.

Bit 10 CC2OF: Capture/compare 2 overcapture flag
refer to CC1OF description
Bit 9 CC1OF: Capture/Compare 1 overcapture flag
This flag is set by hardware only when the corresponding channel is configured in input
capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:7 Reserved, must be kept at reset value.

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Bit 6 TIF: Trigger interrupt flag

This flag is set by hardware on trigger event (active edge detected on TRGI input when the
slave mode controller is enabled in all modes but gated mode. It is set when the counter
starts or stops when gated mode is selected. It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
Bits 5:3 Reserved, must be kept at reset value.
Bit 2 CC2IF: Capture/Compare 2 interrupt flag
refer to CC1IF description
Bit 1 CC1IF: Capture/compare 1 interrupt flag
If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value. It is cleared by
software.
0: No match.
1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register.
When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF
bit goes high on the counter overflow.
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred.
1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected
on IC1 which matches the selected polarity).
Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow and if UDIS=’0’ in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and
UDIS=’0’ in the TIMx_CR1 register.
– When CNT is reinitialized by a trigger event (refer to the synchro control register
description), if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register.

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17.4.6 TIM21/22 event generation register (TIMx_EGR)

Address offset: 0x14
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. TG Res. Res. Res. CC2G CC1G UG

w w w w

Bits 15:7 Reserved, must be kept at reset value.

Bit 6 TG: Trigger generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action
1: The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled
Bits 5:3 Reserved, must be kept at reset value.
Bit 2 CC2G: Capture/compare 2 generation
refer to CC1G description
Bit 1 CC1G: Capture/compare 1 generation
This bit is set by software to generate an event, it is automatically cleared by hardware.
0: No action
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
the CC1IF flag is set, the corresponding interrupt is sent if enabled.
If channel CC1 is configured as input:
The current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the
corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was
already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: Re-initializes the counter and generates an update of the registers. The prescaler counter
is also cleared and the prescaler ratio is not affected. The counter is cleared.

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17.4.7 TIM21/22 capture/compare mode register 1 (TIMx_CCMR1)

Address offset: 0x18
Reset value: 0x0000
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits in this register have different functions in input and output modes. For a given bit, OCxx
describes its function when the channel is configured in output mode, ICxx describes its
function when the channel is configured in input mode. So one must take care that the same
bit can have different meanings for the input stage and the output stage.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2M[2:0] OC2PE OC2FE OC1M[2:0] OC1PE OC1FE
Res. CC2S[1:0] Res. CC1S[1:0]
IC2F[3:0] IC2PSC[1:0] IC1F[3:0] IC1PSC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Output compare mode

Bit 15 Reserved, must be kept at reset value.

Bits 14:12 OC2M[2:0]: Output compare 2 mode
Bit 11 OC2PE: Output compare 2 preload enable
Bit 10 OC2FE: Output compare 2 fast enable
Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an
internal trigger input is selected through the TS bit (TIMx_SMCR register
Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bit 7 Reserved, must be kept at reset value.

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RM0377 General-purpose timers (TIM21/22)

Bits 6:4 OC1M: Output compare 1 mode

These bits define the behavior of the output reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N
depend on the CC1P and CC1NP bits, respectively.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and the
counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing
base).
001: Set channel 1 to active level on match. The OC1REF signal is forced high when the
TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. The OC1REF signal is forced low when the
TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1
100: Force inactive level - OC1REF is forced low
101: Force active level - OC1REF is forced high
110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1
else it is inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as
TIMx_CNT>TIMx_CCR1, else it is active (OC1REF=’1’)
111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1
else it is active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1
else it is inactive.
Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
Bit 3 OC1PE: Output compare 1 preload enable
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the
new value is taken into account immediately
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload
register. TIMx_CCR1 preload value is loaded into the active register at each update event
Note: The PWM mode can be used without validating the preload register only in one-pulse
mode (OPM bit set in the TIMx_CR1 register). Else the behavior is not guaranteed.
Bit 2 OC1FE: Output compare 1 fast enable
This bit is used to accelerate the effect of an event on the trigger in input on the CC output.
0: CC1 behaves normally depending on the counter and CCR1 values even when the
trigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the
trigger input is 5 clock cycles
1: An active edge on the trigger input acts like a compare match on the CC1 output. Then,
OC is set to the compare level independently of the result of the comparison. Delay to
sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE
acts only if the channel is configured in PWM1 or PWM2 mode.
Bits 1:0 CC1S: Capture/Compare 1 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an
internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

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Input capture mode

Bits 15:12 IC2F: Input capture 2 filter

Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler
Bits 9:8 CC2S: Capture/compare 2 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is mapped on TI2
10: CC2 channel is configured as input, IC2 is mapped on TI1
11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an
internal trigger input is selected through the TS bit (TIMx_SMCR register)
Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER).
Bits 7:4 IC1F: Input capture 1 filter
This bitfield defines the frequency used to sample the TI1 input and the length of the digital
filter applied to TI1. The digital filter is made of an event counter in which N consecutive
events are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS 1000: fSAMPLING=fDTS/8, N=6
0001: fSAMPLING=fCK_INT, N=2 1001: fSAMPLING=fDTS/8, N=8
0010: fSAMPLING=fCK_INT, N=4 1010: fSAMPLING=fDTS/16, N=5
0011: fSAMPLING=fCK_INT, N=8 1011: fSAMPLING=fDTS/16, N=6
0100: fSAMPLING=fDTS/2, N=6 1100: fSAMPLING=fDTS/16, N=8
0101: fSAMPLING=fDTS/2, N=8 1101: fSAMPLING=fDTS/32, N=5
0110: fSAMPLING=fDTS/4, N=6 1110: fSAMPLING=fDTS/32, N=6
0111: fSAMPLING=fDTS/4, N=8 1111: fSAMPLING=fDTS/32, N=8
Bits 3:2 IC1PSC: Input capture 1 prescaler
This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
00: no prescaler, capture is done each time an edge is detected on the capture input
01: capture is done once every 2 events
10: capture is done once every 4 events
11: capture is done once every 8 events
Bits 1:0 CC1S: Capture/Compare 1 selection
This bitfield defines the direction of the channel (input/output) as well as the used input.
00: CC1 channel is configured as output
01: CC1 channel is configured as input, IC1 is mapped on TI1
10: CC1 channel is configured as input, IC1 is mapped on TI2
11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if
an internal trigger input is selected through TS bit (TIMx_SMCR register)
Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER).

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RM0377 General-purpose timers (TIM21/22)

17.4.8 TIM21/22 capture/compare enable register (TIMx_CCER)

Address offset: 0x20
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. CC2NP Res. CC2P CC2E CC1NP Res. CC1P CC1E

rw rw rw rw rw rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 CC2NP: Capture/Compare 2 output Polarity
refer to CC1NP description
Bit 6 Reserved, must be kept at reset value.
Bit 5 CC2P: Capture/Compare 2 output Polarity
refer to CC1P description
Bit 4 CC2E: Capture/Compare 2 output enable
refer to CC1E description
Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity
CC1 channel configured as output: CC1NP must be kept cleared
CC1 channel configured as input: CC1NP is used in conjunction with CC1P to define
TI1FP1/TI2FP1 polarity (refer to CC1P description).
Bit 2 Reserved, must be kept at reset value.
Bit 1 CC1P: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high.
1: OC1 active low.
CC1 channel configured as input:
CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations.
00: noninverted/rising edge
Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode).
01: inverted/falling edge
Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger
mode), TIxFP1 is inverted (trigger in gated mode, encoder mode).
10: reserved, do not use this configuration.
Note: 11: noninverted/both edges
Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset,
external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This
configuration must not be used for encoder mode.
Bit 0 CC1E: Capture/Compare 1 output enable.
CC1 channel configured as output:
0: Off - OC1 is not active.
1: On - OC1 signal is output on the corresponding output pin.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the input
capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled.
1: Capture enabled.

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Table 82. Output control bit for standard OCx channels

CCxE bit OCx output state

0 Output disabled (OCx=’0’, OCx_EN=’0’)

1 OCx=OCxREF + Polarity, OCx_EN=’1’

Note: The states of the external I/O pins connected to the standard OCx channels depend on the
state of the OCx channel and on the GPIO registers.

17.4.9 TIM21/22 counter (TIMx_CNT)

Address offset: 0x24
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CNT[15:0]: Counter value

17.4.10 TIM21/22 prescaler (TIMx_PSC)

Address offset: 0x28
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).

17.4.11 TIM21/22 auto-reload register (TIMx_ARR)

Address offset: 0x2C
Reset value: 0xFFFF
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0]: Auto-reload value

ARR is the value to be loaded into the actual auto-reload register.
Refer to the Section 17.3.1: Timebase unit on page 441 for more details about ARR update
and behavior.
The counter is blocked while the auto-reload value is null.

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RM0377 General-purpose timers (TIM21/22)

17.4.12 TIM21/22 capture/compare register 1 (TIMx_CCR1)

Address offset: 0x34
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR1[15:0]
rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r

Bits 15:0 CCR1[15:0]: Capture/Compare 1 value

If channel CC1 is configured as output:
CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register
(OC1PE bit). Else the preload value is copied into the active capture/compare 1 register
when an update event occurs.
The active capture/compare register contains the value to be compared to the TIMx_CNT
counter and signaled on the OC1 output.
If channel CC1is configured as input:
CCR1 is the counter value transferred by the last input capture 1 event (IC1). The
TIMx_CCR1 register is read-only and cannot be programmed.

17.4.13 TIM21/22 capture/compare register 2 (TIMx_CCR2)

Address offset: 0x38
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CCR2[15:0]
rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r rw/r

Bits 15:0 CCR2[15:0]: Capture/Compare 2 value

If channel CC2 is configured as output:
CCR2 is the value to be loaded into the actual capture/compare 2 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register
(OC2PE bit). Else the preload value is copied into the active capture/compare 2 register
when an update event occurs.
The active capture/compare register contains the value to be compared to the TIMx_CNT
counter and signalled on the OC2 output.
If channel CC2 is configured as input:
CCR2 is the counter value transferred by the last input capture 2 event (IC2). The
TIMx_CCR2 register is read-only and cannot be programmed.

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17.4.14 TIM21 option register (TIM21_OR)

Address offset: 0x50
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI2_RMP TI1_RMP ETR_RMP
rw rw rw rw rw rw

Bits 15:6 Reserved, must be kept at reset value.

Bit 5 TI2_RMP: Timer21 TI2 (connected to TIM21_CH1) remap
This bit is set and cleared by software.
0: TIM21 TI2 input connected to GPIO. Refer to the Alternate function mapping table in the
device datasheet.
1: TIM21 TI2 input connected to COMP2_OUT
Bits 4:2 TI1_RMP: Timer21 TI1 (connected to TIM21_CH1) remap
This bit is set and cleared by software.
000: TIM21 TI1 input connected to GPIO. Refer to the Alternate function mapping table in the
device datasheet.
001:TIM21 TI1 input connected to RTC WAKEUP interrupt
010: TIM21 TI1 input connected to HSE_RTC clock
011: TIM21 TI1 input connected to MSI clock
100: TIM21 TI1 input connected to LSE clock
101: TIM21 TI1 input connected to LSI clock
110: TIM21 TI1 input connected to COMP1_OUT
111: TIM21 TI1 input connected to MCO clock
Bits 1:0 ETR_RMP: Timer21 ETR remap
This bit is set and cleared by software.
00: TIM21 ETR input connected to GPIO. Refer to the Alternate function mapping table in the
device datasheet.
01: TIM21 ETR input connected to COMP2_OUT
10: TIM21 ETR input connected to COMP1_OUT
11: TIM21 ETR input connected to LSE clock

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RM0377 General-purpose timers (TIM21/22)

17.4.15 TIM22 option register (TIM22_OR)

Address offset: 0x50
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI1_RMP ETR_RMP
rw rw rw rw

Bits 15:4 Reserved, must be kept at reset value.

Bits 3:2 TI1_RMP: Timer 22 TI1 (connected to TIM22_CH1) remap
This bit is set and cleared by software.
00: TIM22 TI1 input connected to GPIO. Refer to the Alternate function mapping table in the
device datasheet.
01:TIM22 TI1 input connected to COMP2_OUT
10: TIM22 TI1 input connected to COMP1_OUT
11: TIM22 TI1 input connected to GPIO. Refer to the Alternate function mapping table in the
device datasheet.
Bits 1:0 ETR_RMP: Timer 22 ETR remap
This bit is set and cleared by software.
00: TIM22 ETR input connected to GPIO. Refer to the Alternate function mapping table in the
device datasheet.
01: TIM22 ETR input connected to COMP2_OUT
10: TIM22 ETR input connected to COMP1_OUT
11: TIM22 ETR input connected to LSE clock

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17.4.16 TIM21/22 register map

The table below shows TIM21/22 register map and reset values.

Table 83. TIM21/22 register map and reset values

Offset Register

15

14

13

12

10
11

0
ARPE
CKD CMS

UDIS
OPM

CEN
URS
Res.

Res.

Res.

Res.

Res.

Res.

DIR
TIMx_CR1
0x00 [1:0] [1:0]

Reset value 0 0 0 0 0 0 0 0
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.
TIMx_CR2 MMS[2:0]
0x04
Reset value 0 0 0
ETPS[1:0]

MSM

Res.
ECE
ETP

TIMx_SMCR ETF[3:0] TS[2:0] SMS[2:0]

0x08

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CC2IE

CC1IE
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

UIE
TIE
TIMx_DIER
0x0C
Reset value 0 0 0 0
CC2OF

CC1OF

CC2IF

CC1IF
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

UIF
TIMx_SR TIF
0x10

Reset value 0 0 0 0 0 0

CC2G

CC1G
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

UG
TG

TIMx_EGR
0x14
Reset value 0 0 0 0
TIMx_CCMR1
OC2PE

OC1PE
OC2FE

OC1FE

OC2M CC2S OC1M CC1S

Res.

Res.

Output Compare
[2:0] [1:0] [2:0] [1:0]
mode

0x18 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_CCMR1 IC2PSC CC2S IC1PSC CC1S
IC2F[3:0] IC1F[3:0]
Input Capture mode [1:0] [1:0] [1:0] [1:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x1C Res.
CC2NP

CC1NP
CC2P

CC2E

CC1P

CC1E
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIMx_CCER
0x20

Reset value 0 0 0 0 0 0

TIMx_CNT CNT[15:0]
0x24
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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RM0377 General-purpose timers (TIM21/22)

Table 83. TIM21/22 register map and reset values (continued)

Offset Register

15

14

13

12

10
11

0
TIMx_PSC PSC[15:0]
0x28
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_ARR ARR[15:0]
0x2C
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0x30 Res.

TIMx_CCR1 CCR1[15:0]
0x34
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_CCR2 CCR2[15:0]
0x38
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x3C to
Res.
0x4C

TIMx_CCR2 CCR2[15:0]
0x38
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ETR_RMP
TI2_RMP

TI1_RMP
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM21_OR
0x50

Reset value 0 0 0 0 0 0

ETR_RMP
TI1_RMP
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

TIM22_OR
0x50

Reset value 0 0 0 0

Refer to Section 2.2 on page 51 for the register boundary addresses.

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Basic timers (TIM6/7) RM0377

18 Basic timers (TIM6/7)

18.1 Introduction
The basic timers TIM6, TIM7 consist of a 16-bit auto-reload counter driven by a
programmable prescaler.

18.2 TIM6/7 main features

Basic timer (TIM6/TIM7) features include:
• 16-bit auto-reload upcounter
• 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock
frequency by any factor between 1 and 65536
• Interrupt/DMA generation on the update event: counter overflow

Figure 161. Basic timer block diagram

Trigger TRGO
Internal clock (CK_INT) Controller
TIMxCLK from RCC

Control Reset, enable, Count

Auto-reload register
U UI
Stop, clear or up
U
CK_PSC PSC CK_CNT +
prescaler CNT counter

Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit

Event

Interrupt & DMA output

MSv34754V1

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RM0377 Basic timers (TIM6/7)

18.3 TIM6/7 functional description

18.3.1 Time-base unit

The main block of the programmable timer is a 16-bit upcounter with its related auto-reload
register. The counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
• Counter Register (TIMx_CNT)
• Prescaler Register (TIMx_PSC)
• Auto-Reload Register (TIMx_ARR)
The auto-reload register is preloaded. The preload register is accessed each time an
attempt is made to write or read the auto-reload register. The contents of the preload
register are transferred into the shadow register permanently or at each update event UEV,
depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The
update event is sent when the counter reaches the overflow value and if the UDIS bit equals
0 in the TIMx_CR1 register. It can also be generated by software. The generation of the
update event is described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in the TIMx_CR1 register is set.
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as the TIMx_PSC control register is buffered. The new
prescaler ratio is taken into account at the next update event.
Figure 162 and Figure 163 give some examples of the counter behavior when the prescaler
ratio is changed on the fly.

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Figure 162. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F7 F8 F9 FA FB FC 00 01 02 03

Update event (UEV)

Prescaler control register 0 1

Write a new value in TIMx_PSC

Prescaler buffer 0 1

Prescaler counter 0 0 1 0 1 0 1 0 1
MS31076V2

Figure 163. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CEN

Timerclock = CK_CNT

F7 F8 F9 FA FB FC 00 01
Counter register

Update event (UEV)

0 3
Prescaler control register

Write a new value in TIMx_PSC

0 3
Prescaler buffer

0 0 1 2 3 0 1 2 3
Prescaler counter

MS31077V2

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RM0377 Basic timers (TIM6/7)

18.3.2 Counting mode

The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register),
then restarts from 0 and generates a counter overflow event.
An update event can be generate at each counter overflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This avoids updating the shadow registers while writing new values into the preload
registers. In this way, no update event occurs until the UDIS bit has been written to 0,
however, the counter and the prescaler counter both restart from 0 (but the prescale rate
does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1
register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set
(so no interrupt or DMA request is sent).
When an update event occurs, all the registers are updated and the update flag (UIF bit in
the TIMx_SR register) is set (depending on the URS bit):
• The buffer of the prescaler is reloaded with the preload value (contents of the
TIMx_PSC register)
• The auto-reload shadow register is updated with the preload value (TIMx_ARR)
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR = 0x36.

Figure 164. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31078V2

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Figure 165. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0034 0035 0036 0000 0001 0002 0003

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31079V2

Figure 166. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

Timerclock = CK_CNT

Counter register 0035 0036 0000 0001

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31080V2

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RM0377 Basic timers (TIM6/7)

Figure 167. Counter timing diagram, internal clock divided by N

CK_PSC

Timerclock = CK_CNT

Counter register 1F 20 00

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

MS31081V2

Figure 168. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)

Auto-reload preload
register FF 36

Write a new value in TIMx_ARR

MS31082V2

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Figure 169. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded)

CK_PSC

CEN

Timerclock = CK_CNT

Counter register F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

Counter overflow

Update event (UEV)

Update interrupt flag

(UIF)
Auto-reload preload
F5 36
register

Auto-reload shadow
register F5 36

Write a new value in TIMx_ARR MS31083V2

18.3.3 Clock source

The counter clock is provided by the Internal clock (CK_INT) source.
The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except for UG that remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 170 shows the behavior of the control circuit and the upcounter in normal mode,
without prescaler.

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Figure 170. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

UG

CNT_INIT

Counter clock = CK_CNT = CK_PSC

Counter register 31 32 33 34 35 36 00 01 02 03 04 05 06 07

MS31085V2

18.3.4 Debug mode

When the microcontroller enters the debug mode (Cortex®-M0+ core - halted), the TIMx
counter either continues to work normally or stops, depending on the DBG_TIMx_STOP
configuration bit in the DBG module. For more details, refer to Section 27.9.2: Debug
support for timers, watchdog and I2C.

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18.4 TIM6/7 registers

Refer to Section 1.2: List of abbreviations for registers for a list of abbreviations used in
register descriptions.
The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read
accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits).

18.4.1 TIM6/7 control register 1 (TIMx_CR1)

Address offset: 0x00
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. ARPE Res. Res. Res. OPM URS UDIS CEN
rw rw rw rw rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 ARPE: Auto-reload preload enable
0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
Bits 6:4 Reserved, must be kept at reset value.
Bit 3 OPM: One-pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the CEN bit).
Bit 2 URS: Update request source
This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generates an update interrupt or DMA request if enabled.
These events can be:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
Bit 1 UDIS: Update disable
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following events:
– Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their value
(ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if
a hardware reset is received from the slave mode controller.
Bit 0 CEN: Counter enable
0: Counter disabled
1: Counter enabled
Note: Gated mode can work only if the CEN bit has been previously set by software.
However trigger mode can set the CEN bit automatically by hardware.
CEN is cleared automatically in one-pulse mode, when an update event occurs.

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18.4.2 TIM6/7 control register 2 (TIMx_CR2)

Address offset: 0x04
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. MMS[2:0] Res. Res. Res. Res.

rw rw rw

Bits 15:7 Reserved, must be kept at reset value.

Bits 6:4 MMS: Master mode selection
These bits are used to select the information to be sent in master mode to slave timers for
synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If
reset is generated by the trigger input (slave mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is
useful to start several timers at the same time or to control a window in which a slave timer
is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit
and the trigger input when configured in gated mode.
When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR
register).
010: Update - The update event is selected as a trigger output (TRGO). For instance a
master timer can then be used as a prescaler for a slave timer.
Bits 3:0 Reserved, must be kept at reset value.

18.4.3 TIM6/7 DMA/Interrupt enable register (TIMx_DIER)

Address offset: 0x0C
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. UDE Res. Res. Res. Res. Res. Res. Res. UIE

rw rw

Bits 15:9 Reserved, must be kept at reset value.

Bit 8 UDE: Update DMA request enable
0: Update DMA request disabled.
1: Update DMA request enabled.
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 UIE: Update interrupt enable
0: Update interrupt disabled.
1: Update interrupt enabled.

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18.4.4 TIM6/7 status register (TIMx_SR)

Address offset: 0x10
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UIF

rc_w0

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UIF: Update interrupt flag
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the
TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0
and UDIS = 0 in the TIMx_CR1 register.

18.4.5 TIM6/7 event generation register (TIMx_EGR)

Address offset: 0x14
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UG

Bits 15:1 Reserved, must be kept at reset value.

Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Re-initializes the timer counter and generates an update of the registers. Note that the
prescaler counter is cleared too (but the prescaler ratio is not affected).

18.4.6 TIM6/7 counter (TIMx_CNT)

Address offset: 0x24
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CNT[15:0]: Counter value

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18.4.7 TIM6/7 prescaler (TIMx_PSC)

Address offset: 0x28
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PSC[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the active prescaler register at each update event
(including when the counter is cleared through UG bit of TIMx_EGR register or through
trigger controller when configured in “reset mode”).

18.4.8 TIM6/7 auto-reload register (TIMx_ARR)

Address offset: 0x2C
Reset value: 0xFFFF
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 ARR[15:0]: Auto-reload value

ARR is the value to be loaded into the actual auto-reload register.
Refer to Section 18.3.1: Time-base unit on page 495 for more details about ARR update and
behavior.
The counter is blocked while the auto-reload value is null.

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18.4.9 TIM6/7 register map

TIMx registers are mapped as 16-bit addressable registers as described in the table below:

Table 84. TIM6/7 register map and reset values

Offset Register

15

14

13

12

10
11

0
ARPE

UDIS
OPM

CEN
URS
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.
TIMx_CR1
0x00
Reset value 0 0 0 0 0
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.
TIMx_CR2 MMS[2:0]
0x04
Reset value 0 0 0

0x08 Res.

UDE
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

UIE
TIMx_DIER
0x0C
Reset value 0 0
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

UIF
TIMx_SR
0x10
Reset value 0
Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

Res.

UG
TIMx_EGR
0x14
Reset value 0

0x18 Res.

0x1C Res.

0x20 Res.

TIMx_CNT CNT[15:0]
0x24
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_PSC PSC[15:0]
0x28
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_ARR ARR[15:0]
0x2C
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Refer to Section 2.2 on page 51 for the register boundary addresses.

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RM0377 Low-power timer (LPTIM)

19 Low-power timer (LPTIM)

19.1 Introduction
The LPTIM is a 16-bit timer that benefits from the ultimate developments in power
consumption reduction. Thanks to its diversity of clock sources, the LPTIM is able to keep
running in all power modes except for Standby mode. Given its capability to run even with
no internal clock source, the LPTIM can be used as a “Pulse Counter” which can be useful
in some applications. Also, the LPTIM capability to wake up the system from low-power
modes, makes it suitable to realize “Timeout functions” with extremely low power
consumption.
The LPTIM introduces a flexible clock scheme that provides the needed functionalities and
performance, while minimizing the power consumption.

19.2 LPTIM main features

• 16 bit upcounter
• 3-bit prescaler with 8 possible dividing factors (1,2,4,8,16,32,64,128)
• Selectable clock
– Internal clock sources: configurable internal clock source (see RCC section)
– External clock source over LPTIM input (working with no embedded oscillator
running, used by Pulse Counter application)
• 16 bit ARR autoreload register
• 16 bit compare register
• Continuous/One-shot mode
• Selectable software/hardware input trigger
• Programmable Digital Glitch filter
• Configurable output: Pulse, PWM
• Configurable I/O polarity
• Encoder mode

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19.3 LPTIM implementation

Table 85 describes LPTIM implementation on STM32L0x1 devices.

Table 85. STM32L0x1 LPTIM features

LPTIM modes/features(1) LPTIM1

Encoder mode X
1. X = supported.

19.4 LPTIM functional description

19.4.1 LPTIM block diagram

Figure 171. Low-power timer block diagram

LPTIM

APB_ITF

Kernel
Up/down
Encoder Glitch
Input 2
filter

Glitch
Input 1
filter
up to 8 ext
trigger
Glitch sw
filter trigger
16-bit ARR
RCC
Mux trigger

1
Out
‘1' 0 COUNT 16-bit counter
APB clock MODE
1
LSE CLKMUX 0 Prescaler
LSI
HSI16 16-bit compare
CKSEL

MS32468V2

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19.4.2 LPTIM trigger mapping

The LPTIM external trigger connections are detailed hereafter:

Table 86. LPTIM1 external trigger connection

TRIGSEL External trigger

lptim_ext_trig0 GPIO (alternate function LPTIM_ETR)

lptim_ext_trig1 RTC alarm A
lptim_ext_trig2 RTC alarm B
lptim_ext_trig3 RTC_TAMP1 input detection
lptim_ext_trig4 RTC_TAMP2 input detection
lptim_ext_trig5 RTC_TAMP3 input detection
lptim_ext_trig6 COMP1_OUT
lptim_ext_trig7 COMP2_OUT

19.4.3 LPTIM reset and clocks

The LPTIM can be clocked using several clock sources. It can be clocked using an internal
clock signal which can be any configurable internal clock source selectable through the
RCC (see RCC section for more details). Also, the LPTIM can be clocked using an external
clock signal injected on its external Input1. When clocked with an external clock source, the
LPTIM may run in one of these two possible configurations:
• The first configuration is when the LPTIM is clocked by an external signal but in the
same time an internal clock signal is provided to the LPTIM from configurable internal
clock source (see RCC section).
• The second configuration is when the LPTIM is solely clocked by an external clock
source through its external Input1. This configuration is the one used to realize Timeout
function or Pulse counter function when all the embedded oscillators are turned off
after entering a low-power mode.
Programming the CKSEL and COUNTMODE bits allows controlling whether the LPTIM will
use an external clock source or an internal one.
When configured to use an external clock source, the CKPOL bits are used to select the
external clock signal active edge. If both edges are configured to be active ones, an internal
clock signal should also be provided (first configuration). In this case, the internal clock
signal frequency should be at least four times higher than the external clock signal
frequency.

19.4.4 Glitch filter

The LPTIM inputs, either external (mapped to GPIOs) or internal (mapped on the chip-level
to other embedded peripherals), are protected with digital filters that prevent any glitches
and noise perturbations to propagate inside the LPTIM. This is in order to prevent spurious
counts or triggers.
Before activating the digital filters, an internal clock source should first be provided to the
LPTIM. This is necessary to guarantee the proper operation of the filters.

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The digital filters are divided into two groups:

• The first group of digital filters protects the LPTIM external inputs. The digital filters
sensitivity is controlled by the CKFLT bits
• The second group of digital filters protects the LPTIM internal trigger inputs. The digital
filters sensitivity is controlled by the TRGFLT bits.
Note: The digital filters sensitivity is controlled by groups. It is not possible to configure each digital
filter sensitivity separately inside the same group.
The filter sensitivity acts on the number of consecutive equal samples that should be
detected on one of the LPTIM inputs to consider a signal level change as a valid transition.
Figure 172 shows an example of glitch filter behavior in case of a 2 consecutive samples
programmed.

Figure 172. Glitch filter timing diagram

CLKMUX

Input

Filter out

2 consecutive samples 2 consecutive samples Filtered

MS32490V1

Note: In case no internal clock signal is provided, the digital filter must be deactivated by setting
the CKFLT and TRGFLT bits to ‘0’. In that case, an external analog filter may be used to
protect the LPTIM external inputs against glitches.

19.4.5 Prescaler
The LPTIM 16-bit counter is preceded by a configurable power-of-2 prescaler. The prescaler
division ratio is controlled by the PRESC[2:0] 3-bit field. The table below lists all the possible
division ratios:

Table 87. Prescaler division ratios

programming dividing factor

000 /1
001 /2
010 /4
011 /8
100 /16
101 /32
110 /64
111 /128

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19.4.6 Trigger multiplexer

The LPTIM counter may be started either by software or after the detection of an active
edge on one of the 8 trigger inputs.
TRIGEN[1:0] is used to determine the LPTIM trigger source:
• When TRIGEN[1:0] equals ‘00’, The LPTIM counter is started as soon as one of the
CNTSTRT or the SNGSTRT bits is set by software. The three remaining possible
values for the TRIGEN[1:0] are used to configure the active edge used by the trigger
inputs. The LPTIM counter starts as soon as an active edge is detected.
• When TRIGEN[1:0] is different than ‘00’, TRIGSEL[2:0] is used to select which of the 8
trigger inputs is used to start the counter.
The external triggers are considered asynchronous signals for the LPTIM. So after a trigger
detection, a two-counter-clock period latency is needed before the timer starts running due
to the synchronization.
If a new trigger event occurs when the timer is already started it will be ignored (unless
timeout function is enabled).
Note: The timer must be enabled before setting the SNGSTRT/CNTSTRT bits. Any write on these
bits when the timer is disabled will be discarded by hardware.
Note: When starting the counter by software (TRIGEN[1:0] = 00), there is a delay of 3 kernel clock
cycles between the LPTIM_CR register update (set one of SNGSTRT or CNTSTRT bits)
and the effective start of the counter.

19.4.7 Operating mode

The LPTIM features two operating modes:
• The Continuous mode: the timer is free running, the timer is started from a trigger event
and never stops until the timer is disabled
• One-shot mode: the timer is started from a trigger event and stops when reaching the
ARR value.

One-shot mode
To enable the one-shot counting, the SNGSTRT bit must be set.
A new trigger event will re-start the timer. Any trigger event occurring after the counter starts
and before the counter reaches ARR will be discarded.
In case an external trigger is selected, each external trigger event arriving after the
SNGSTRT bit is set, and after the counter register has stopped (contains zero value), will
start the counter for a new one-shot counting cycle as shown in Figure 173.

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Figure 173. LPTIM output waveform, single counting mode configuration

LPTIM_ARR
Compare

PWM

External trigger event

MSv39230V2

- Set-once mode activated:

It should be noted that when the WAVE bit-field in the LPTIM_CFGR register is set, the Set-
once mode is activated. In this case, the counter is only started once following the first
trigger, and any subsequent trigger event is discarded as shown in Figure 174.

Figure 174. LPTIM output waveform, Single counting mode configuration

and Set-once mode activated (WAVE bit is set)

LPTIM_ARR
Compare
Discarded trigger

PWM

External trigger event

MSv39231V2

In case of software start (TRIGEN[1:0] = ‘00’), the SNGSTRT setting will start the counter for
one-shot counting.

Continous mode
To enable the continuous counting, the CNTSTRT bit must be set.
In case an external trigger is selected, an external trigger event arriving after CNTSTRT is
set will start the counter for continuous counting. Any subsequent external trigger event will
be discarded as shown in Figure 175.
In case of software start (TRIGEN[1:0] = ‘00’), setting CNTSTRT will start the counter for
continuous counting.

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Figure 175. LPTIM output waveform, Continuous counting mode configuration

Discarded triggers

LPTIM_ARR
Compare

PWM

External trigger event

MSv39229V2

SNGSTRT and CNTSTRT bits can only be set when the timer is enabled (The ENABLE bit
is set to ‘1’). It is possible to change “on the fly” from One-shot mode to Continuous mode.
If the Continuous mode was previously selected, setting SNGSTRT will switch the LPTIM to
the One-shot mode. The counter (if active) will stop as soon as it reaches ARR.
If the One-shot mode was previously selected, setting CNTSTRT will switch the LPTIM to
the Continuous mode. The counter (if active) will restart as soon as it reaches ARR.

19.4.8 Timeout function

The detection of an active edge on one selected trigger input can be used to reset the
LPTIM counter. This feature is controlled through the TIMOUT bit.
The first trigger event will start the timer, any successive trigger event will reset the counter
and the timer will restart.
A low-power timeout function can be realized. The timeout value corresponds to the
compare value; if no trigger occurs within the expected time frame, the MCU is waked-up by
the compare match event.

19.4.9 Waveform generation

Two 16-bit registers, the LPTIM_ARR (autoreload register) and LPTIM_CMP (compare
register), are used to generate several different waveforms on LPTIM output
The timer can generate the following waveforms:
• The PWM mode: the LPTIM output is set as soon as the counter value in LPTIM_CNT
exceeds the compare value in LPTIM_CMP. The LPTIM output is reset as soon as a
match occurs between the LPTIM_ARR and the LPTIM_CNT registers.
• The One-pulse mode: the output waveform is similar to the one of the PWM mode for
the first pulse, then the output is permanently reset
• The Set-once mode: the output waveform is similar to the One-pulse mode except that
the output is kept to the last signal level (depends on the output configured polarity).
The above described modes require that the LPTIM_ARR register value be strictly greater
than the LPTIM_CMP register value.

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The LPTIM output waveform can be configured through the WAVE bit as follow:
• Resetting the WAVE bit to ‘0’ forces the LPTIM to generate either a PWM waveform or
a One pulse waveform depending on which bit is set: CNTSTRT or SNGSTRT.
• Setting the WAVE bit to ‘1’ forces the LPTIM to generate a Set-once mode waveform.
The WAVPOL bit controls the LPTIM output polarity. The change takes effect immediately,
so the output default value will change immediately after the polarity is re-configured, even
before the timer is enabled.
Signals with frequencies up to the LPTIM clock frequency divided by 2 can be generated.
Figure 176 below shows the three possible waveforms that can be generated on the LPTIM
output. Also, it shows the effect of the polarity change using the WAVPOL bit.

Figure 176. Waveform generation

LPTIM_ARR
Compare

PWM

One shot Pol = 0

Set once

PWM

One shot Pol = 1

Set once

MS32467V2

19.4.10 Register update

The LPTIM_ARR register and LPTIM_CMP register are updated immediately after the APB
bus write operation, or at the end of the current period if the timer is already started.
The PRELOAD bit controls how the LPTIM_ARR and the LPTIM_CMP registers are
updated:
• When the PRELOAD bit is reset to ‘0’, the LPTIM_ARR and the LPTIM_CMP registers
are immediately updated after any write access.
• When the PRELOAD bit is set to ‘1’, the LPTIM_ARR and the LPTIM_CMP registers
are updated at the end of the current period, if the timer has been already started.
The LPTIM APB interface and the LPTIM kernel logic use different clocks, so there is some
latency between the APB write and the moment when these values are available to the

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counter comparator. Within this latency period, any additional write into these registers must
be avoided.
The ARROK flag and the CMPOK flag in the LPTIM_ISR register indicate when the write
operation is completed to respectively the LPTIM_ARR register and the LPTIM_CMP
register.
After a write to the LPTIM_ARR register or the LPTIM_CMP register, a new write operation
to the same register can only be performed when the previous write operation is completed.
Any successive write before respectively the ARROK flag or the CMPOK flag be set, will
lead to unpredictable results.

19.4.11 Counter mode

The LPTIM counter can be used to count external events on the LPTIM Input1 or it can be
used to count internal clock cycles. The CKSEL and COUNTMODE bits control which
source will be used for updating the counter.
In case the LPTIM is configured to count external events on Input1, the counter can be
updated following a rising edge, falling edge or both edges depending on the value written
to the CKPOL[1:0] bits.
The count modes below can be selected, depending on CKSEL and COUNTMODE values:
• CKSEL = 0: the LPTIM is clocked by an internal clock source
– COUNTMODE = 0
The LPTIM is configured to be clocked by an internal clock source and the LPTIM
counter is configured to be updated following each internal clock pulse.
– COUNTMODE = 1
The LPTIM external Input1 is sampled with the internal clock provided to the
LPTIM.
Consequently, in order not to miss any event, the frequency of the changes on the
external Input1 signal should never exceed the frequency of the internal clock
provided to the LPTIM. Also, the internal clock provided to the LPTIM must not be
prescaled (PRESC[2:0] = 000).
• CKSEL = 1: the LPTIM is clocked by an external clock source
COUNTMODE value is don’t care.
In this configuration, the LPTIM has no need for an internal clock source (except if the
glitch filters are enabled). The signal injected on the LPTIM external Input1 is used as
system clock for the LPTIM. This configuration is suitable for operation modes where
no embedded oscillator is enabled.
For this configuration, the LPTIM counter can be updated either on rising edges or
falling edges of the input1 clock signal but not on both rising and falling edges.
Since the signal injected on the LPTIM external Input1 is also used to clock the LPTIM
kernel logic, there is some initial latency (after the LPTIM is enabled) before the counter
is incremented. More precisely, the first five active edges on the LPTIM external Input1
(after LPTIM is enable) are lost.
For code example, refer to A.10.1: Pulse counter configuration code example.

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19.4.12 Timer enable

The ENABLE bit located in the LPTIM_CR register is used to enable/disable the LPTIM
kernel logic. After setting the ENABLE bit, a delay of two counter clock is needed before the
LPTIM is actually enabled.
The LPTIM_CFGR and LPTIM_IER registers must be modified only when the LPTIM is
disabled.

19.4.13 Encoder mode

This mode allows handling signals from quadrature encoders used to detect angular
position of rotary elements. Encoder interface mode acts simply as an external clock with
direction selection. This means that the counter just counts continuously between 0 and the
auto-reload value programmed into the LPTIM_ARR register (0 up to ARR or ARR down to
0 depending on the direction). Therefore LPTIM_ARR must be configured before starting
the counter. From the two external input signals, Input1 and Input2, a clock signal is
generated to clock the LPTIM counter. The phase between those two signals determines
the counting direction.
The Encoder mode is only available when the LPTIM is clocked by an internal clock source.
The signals frequency on both Input1 and Input2 inputs must not exceed the LPTIM internal
clock frequency divided by 4. This is mandatory in order to guarantee a proper operation of
the LPTIM.
Direction change is signalized by the two Down and Up flags in the LPTIM_ISR register.
Also, an interrupt can be generated for both direction change events if enabled through the
DOWNIE bit.
To activate the Encoder mode the ENC bit has to be set to ‘1’. The LPTIM must first be
configured in Continuous mode.
When Encoder mode is active, the LPTIM counter is modified automatically following the
speed and the direction of the incremental encoder. Therefore, its content always
represents the encoder’s position. The count direction, signaled by the Up and Down flags,
correspond to the rotation direction of the encoder rotor.
According to the edge sensitivity configured using the CKPOL[1:0] bits, different counting
scenarios are possible. The following table summarizes the possible combinations,
assuming that Input1 and Input2 do not switch at the same time.

Table 88. Encoder counting scenarios

Level on opposite Input1 signal Input2 signal
signal (Input1 for
Active edge
Input2, Input2 for
Rising Falling Rising Falling
Input1)

High Down No count Up No count

Rising Edge
Low Up No count Down No count
High No count Up No count Down
Falling Edge
Low No count Down No count Up
High Down Up Up Down
Both Edges
Low Up Down Down Up

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RM0377 Low-power timer (LPTIM)

The following figure shows a counting sequence for Encoder mode where both-edge
sensitivity is configured.
Caution: In this mode the LPTIM must be clocked by an internal clock source, so the CKSEL bit must
be maintained to its reset value which is equal to ‘0’. Also, the prescaler division ratio must
be equal to its reset value which is 1 (PRESC[2:0] bits must be ‘000’).

Figure 177. Encoder mode counting sequence

T1

T2

Counter

up down up
MS32491V1

19.4.14 Debug mode

When the microcontroller enters debug mode (core halted), the LPTIM counter either
continues to work normally or stops, depending on the DBG_LPTIM_STOP configuration bit
in the DBG module.

19.5 LPTIM low-power modes

Table 89. Effect of low-power modes on the LPTIM
Mode Description

Sleep No effect. LPTIM interrupts cause the device to exit Sleep mode.

Stop The LPTIM peripheral is active when it is clocked by LSE or LSI. LPTIM
interrupts cause the device to exit Stop mode
The LPTIM peripheral is powered down and must be reinitialized after
Standby
exiting Standby mode.

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19.6 LPTIM interrupts

The following events generate an interrupt/wake-up event, if they are enabled through the
LPTIM_IER register:
• Compare match
• Auto-reload match (whatever the direction if encoder mode)
• External trigger event
• Autoreload register write completed
• Compare register write completed
• Direction change (encoder mode), programmable (up / down / both).
Note: If any bit in the LPTIM_IER register (Interrupt Enable Register) is set after that its
corresponding flag in the LPTIM_ISR register (Status Register) is set, the interrupt is not
asserted.

Table 90. Interrupt events

Interrupt event Description

Interrupt flag is raised when the content of the Counter register

Compare match
(LPTIM_CNT) matches the content of the compare register (LPTIM_CMP).
Interrupt flag is raised when the content of the Counter register
Auto-reload match (LPTIM_CNT) matches the content of the Auto-reload register
(LPTIM_ARR).
External trigger event Interrupt flag is raised when an external trigger event is detected
Auto-reload register Interrupt flag is raised when the write operation to the LPTIM_ARR register
update OK is complete.
Compare register Interrupt flag is raised when the write operation to the LPTIM_CMP register
update OK is complete.
Used in Encoder mode. Two interrupt flags are embedded to signal
direction change:
Direction change
– UP flag signals up-counting direction change
– DOWN flag signals down-counting direction change.

19.7 LPTIM registers

The peripheral registers can only be accessed by words (32-bit).

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RM0377 Low-power timer (LPTIM)

19.7.1 LPTIM interrupt and status register (LPTIM_ISR)

Address offset: 0x000
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR CMP EXT
Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWN UP ARRM CMPM
OK OK TRIG
r r r r r r r

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 DOWN: Counter direction change up to down
In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has
changed from up to down. DOWN flag can be cleared by writing 1 to the DOWNCF bit in the
LPTIM_ICR register.
Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
Section 19.3: LPTIM implementation.
Bit 5 UP: Counter direction change down to up
In Encoder mode, UP bit is set by hardware to inform application that the counter direction has
changed from down to up. UP flag can be cleared by writing 1 to the UPCF bit in the LPTIM_ICR
register.
Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
Section 19.3: LPTIM implementation.
Bit 4 ARROK: Autoreload register update OK
ARROK is set by hardware to inform application that the APB bus write operation to the LPTIM_ARR
register has been successfully completed. ARROK flag can be cleared by writing 1 to the ARROKCF
bit in the LPTIM_ICR register.
Bit 3 CMPOK: Compare register update OK
CMPOK is set by hardware to inform application that the APB bus write operation to the
LPTIM_CMP register has been successfully completed. CMPOK flag can be cleared by writing 1 to
the CMPOKCF bit in the LPTIM_ICR register.
Bit 2 EXTTRIG: External trigger edge event
EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger
input has occurred. If the trigger is ignored because the timer has already started, then this flag is
not set. EXTTRIG flag can be cleared by writing 1 to the EXTTRIGCF bit in the LPTIM_ICR register.
Bit 1 ARRM: Autoreload match
ARRM is set by hardware to inform application that LPTIM_CNT register’s value reached the
LPTIM_ARR register’s value. ARRM flag can be cleared by writing 1 to the ARRMCF bit in the
LPTIM_ICR register.
Bit 0 CMPM: Compare match
The CMPM bit is set by hardware to inform application that LPTIM_CNT register value reached the
LPTIM_CMP register’s value. CMPM flag can be cleared by writing 1 to the CMPMCF bit in the
LPTIM_ICR register.

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19.7.2 LPTIM interrupt clear register (LPTIM_ICR)

Address offset: 0x004
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWN ARRO CMPO EXTTR ARRM CMPM
Res. Res. Res. Res. Res. Res. Res. Res. Res. UPCF
CF KCF KCF IGCF CF CF
w w w w w w w

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 DOWNCF: Direction change to down clear flag
Writing 1 to this bit clear the DOWN flag in the LPTIM_ISR register.
Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
Section 19.3: LPTIM implementation.
Bit 5 UPCF: Direction change to UP clear flag
Writing 1 to this bit clear the UP flag in the LPTIM_ISR register.
Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
Section 19.3: LPTIM implementation.
Bit 4 ARROKCF: Autoreload register update OK clear flag
Writing 1 to this bit clears the ARROK flag in the LPTIM_ISR register
Bit 3 CMPOKCF: Compare register update OK clear flag
Writing 1 to this bit clears the CMPOK flag in the LPTIM_ISR register
Bit 2 EXTTRIGCF: External trigger valid edge clear flag
Writing 1 to this bit clears the EXTTRIG flag in the LPTIM_ISR register
Bit 1 ARRMCF: Autoreload match clear flag
Writing 1 to this bit clears the ARRM flag in the LPTIM_ISR register
Bit 0 CMPMCF: Compare match clear flag
Writing 1 to this bit clears the CMPM flag in the LPTIM_ISR register

19.7.3 LPTIM interrupt enable register (LPTIM_IER)

Address offset: 0x008
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOWNI ARRO CMPO EXT ARRM CMPM
Res. Res. Res. Res. Res. Res. Res. Res. Res. UPIE
E KIE KIE TRIGIE IE IE
rw rw rw rw rw rw rw

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RM0377 Low-power timer (LPTIM)

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 DOWNIE: Direction change to down Interrupt Enable
0: DOWN interrupt disabled
1: DOWN interrupt enabled
Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
Section 19.3: LPTIM implementation.
Bit 5 UPIE: Direction change to UP Interrupt Enable
0: UP interrupt disabled
1: UP interrupt enabled
Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
Section 19.3: LPTIM implementation.
Bit 4 ARROKIE: Autoreload register update OK Interrupt Enable
0: ARROK interrupt disabled
1: ARROK interrupt enabled
Bit 3 CMPOKIE: Compare register update OK Interrupt Enable
0: CMPOK interrupt disabled
1: CMPOK interrupt enabled
Bit 2 EXTTRIGIE: External trigger valid edge Interrupt Enable
0: EXTTRIG interrupt disabled
1: EXTTRIG interrupt enabled
Bit 1 ARRMIE: Autoreload match Interrupt Enable
0: ARRM interrupt disabled
1: ARRM interrupt enabled
Bit 0 CMPMIE: Compare match Interrupt Enable
0: CMPM interrupt disabled
1: CMPM interrupt enabled

Caution: The LPTIM_IER register must only be modified when the LPTIM is disabled (ENABLE bit reset to ‘0’)

19.7.4 LPTIM configuration register (LPTIM_CFGR)

Address offset: 0x00C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
COUNT
Res. Res. Res. Res. Res. Res. Res. ENC PRELOAD WAVPOL WAVE TIMOUT TRIGEN[1:0] Res.
MODE
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIGSEL[2:0] Res. PRESC[2:0] Res. TRGFLT[1:0] Res. CKFLT[1:0] CKPOL[1:0] CKSEL
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 Reserved, must be kept at reset value.
Bits 28:25 Reserved, must be kept at reset value.

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Bit 24 ENC: Encoder mode enable

The ENC bit controls the Encoder mode
0: Encoder mode disabled
1: Encoder mode enabled
Note: If the LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
Section 19.3: LPTIM implementation.
Bit 23 COUNTMODE: counter mode enabled
The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter:
0: the counter is incremented following each internal clock pulse
1: the counter is incremented following each valid clock pulse on the LPTIM external Input1
Bit 22 PRELOAD: Registers update mode
The PRELOAD bit controls the LPTIM_ARR and the LPTIM_CMP registers update modality
0: Registers are updated after each APB bus write access
1: Registers are updated at the end of the current LPTIM period
Bit 21 WAVPOL: Waveform shape polarity
The WAVEPOL bit controls the output polarity
0: The LPTIM output reflects the compare results between LPTIM_CNT and LPTIM_CMP
registers
1: The LPTIM output reflects the inverse of the compare results between LPTIM_CNT and
LPTIM_CMP registers

Bit 20 WAVE: Waveform shape

The WAVE bit controls the output shape
0: Deactivate Set-once mode
1: Activate the Set-once mode
Bit 19 TIMOUT: Timeout enable
The TIMOUT bit controls the Timeout feature
0: A trigger event arriving when the timer is already started will be ignored
1: A trigger event arriving when the timer is already started will reset and restart the counter
Bits 18:17 TRIGEN[1:0]: Trigger enable and polarity
The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the
external trigger option is selected, three configurations are possible for the trigger active edge:
00: software trigger (counting start is initiated by software)
01: rising edge is the active edge
10: falling edge is the active edge
11: both edges are active edges
Bit 16 Reserved, must be kept at reset value.

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RM0377 Low-power timer (LPTIM)

Bits 15:13 TRIGSEL[2:0]: Trigger selector

The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among
the below 8 available sources:
000: lptim_ext_trig0
001: lptim_ext_trig1
010: lptim_ext_trig2
011: lptim_ext_trig3
100: lptim_ext_trig4
101: lptim_ext_trig5
110: lptim_ext_trig6
111: lptim_ext_trig7
See Section 19.4.2: LPTIM trigger mapping for details.
Bit 12 Reserved, must be kept at reset value.
Bits 11:9 PRESC[2:0]: Clock prescaler
The PRESC bits configure the prescaler division factor. It can be one among the following division
factors:
000: /1
001: /2
010: /4
011: /8
100: /16
101: /32
110: /64
111: /128
Bit 8 Reserved, must be kept at reset value.
Bits 7:6 TRGFLT[1:0]: Configurable digital filter for trigger
The TRGFLT value sets the number of consecutive equal samples that should be detected when a
level change occurs on an internal trigger before it is considered as a valid level transition. An
internal clock source must be present to use this feature
00: any trigger active level change is considered as a valid trigger
01: trigger active level change must be stable for at least 2 clock periods before it is considered as
valid trigger.
10: trigger active level change must be stable for at least 4 clock periods before it is considered as
valid trigger.
11: trigger active level change must be stable for at least 8 clock periods before it is considered as
valid trigger.
Bit 5 Reserved, must be kept at reset value.

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Bits 4:3 CKFLT[1:0]: Configurable digital filter for external clock

The CKFLT value sets the number of consecutive equal samples that should be detected when a
level change occurs on an external clock signal before it is considered as a valid level transition. An
internal clock source must be present to use this feature
00: any external clock signal level change is considered as a valid transition
01: external clock signal level change must be stable for at least 2 clock periods before it is
considered as valid transition.
10: external clock signal level change must be stable for at least 4 clock periods before it is
considered as valid transition.
11: external clock signal level change must be stable for at least 8 clock periods before it is
considered as valid transition.
Bits 2:1 CKPOL[1:0]: Clock Polarity
If LPTIM is clocked by an external clock source:
When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active
edge or edges used by the counter:
00:the rising edge is the active edge used for counting.
If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 1 is active.
01:the falling edge is the active edge used for counting
If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 2 is active.
10:both edges are active edges. When both external clock signal edges are considered active ones,
the LPTIM must also be clocked by an internal clock source with a frequency equal to at least
four times the external clock frequency.
If the LPTIM is configured in Encoder mode (ENC bit is set), the encoder sub-mode 3 is active.
11:not allowed
Refer to Section 19.4.13: Encoder mode for more details about Encoder mode sub-modes.
Bit 0 CKSEL: Clock selector
The CKSEL bit selects which clock source the LPTIM will use:
0: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)
1: LPTIM is clocked by an external clock source through the LPTIM external Input1

Caution: The LPTIM_CFGR register must only be modified when the LPTIM is disabled (ENABLE bit
reset to ‘0’).

19.7.5 LPTIM control register (LPTIM_CR)

Address offset: 0x010
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT SNG ENA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
STRT STRT BLE
rw rw rw

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RM0377 Low-power timer (LPTIM)

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 CNTSTRT: Timer start in Continuous mode
This bit is set by software and cleared by hardware.
In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode.
If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in
Continuous mode as soon as an external trigger is detected.
If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next
match between the LPTIM_ARR and LPTIM_CNT registers and the LPTIM counter keeps counting
in Continuous mode.
This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware.
Bit 1 SNGSTRT: LPTIM start in Single mode
This bit is set by software and cleared by hardware.
In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode.
If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in
single pulse mode as soon as an external trigger is detected.
If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the
following match between LPTIM_ARR and LPTIM_CNT registers.
This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware.
Bit 0 ENABLE: LPTIM enable
The ENABLE bit is set and cleared by software.
0:LPTIM is disabled
1:LPTIM is enabled

19.7.6 LPTIM compare register (LPTIM_CMP)

Address offset: 0x014
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMP[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 CMP[15:0]: Compare value
CMP is the compare value used by the LPTIM.

Caution: The LPTIM_CMP register must only be modified when the LPTIM is enabled (ENABLE bit
set to ‘1’).

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19.7.7 LPTIM autoreload register (LPTIM_ARR)

Address offset: 0x018
Reset value: 0x0000 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ARR[15:0]: Auto reload value
ARR is the autoreload value for the LPTIM.
This value must be strictly greater than the CMP[15:0] value.

Caution: The LPTIM_ARR register must only be modified when the LPTIM is enabled (ENABLE bit
set to ‘1’).

19.7.8 LPTIM counter register (LPTIM_CNT)

Address offset: 0x01C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 CNT[15:0]: Counter value
When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may
return unreliable values. So in this case it is necessary to perform two consecutive read accesses
and verify that the two returned values are identical.
It should be noted that for a reliable LPTIM_CNT register read access, two consecutive read
accesses must be performed and compared. A read access can be considered reliable when the
values of the two consecutive read accesses are equal.

526/905 RM0377 Rev 10

 1.
0x018
0x014
0x010
0x008
0x004
0x000

0x01C
0x00C
19.7.9
RM0377

LPTIM_CR
LPTIM_IER
LPTIM_ISR

LPTIM_ICR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

LPTIM_CNT
LPTIM_ARR
LPTIM_CMP
LPTIM_CFGR
Offset Register name
Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. 27
LPTIM register map

Res. Res. Res. Res. Res. Res. Res. Res. 26

Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. ENC(1) Res. Res. Res. 24
Res. Res. Res. Res. COUNTMODE Res. Res. Res. 23
Res. Res. Res. Res. PRELOAD Res. Res. Res. 22
Res. Res. Res. Res. WAVEPOL Res. Res. Res. 21
Res. Res. Res. Res. WAVE Res. Res. Res. 20
Res. Res. Res. Res. TIMOUT Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. 18

RM0377 Rev 10
TRIGEN

0 0 0 0 0 0 0 0
Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. 16
The following table summarizes the LPTIM registers.

Res. Res. Res. Res. 15

Res. TRIGSEL[2:0] Res. Res. Res. 14

0 0 0
Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. 11
Table 91. LPTIM register map and reset values

Res. PRESC Res. Res. Res. 10

0 0 0
Res. Res. Res. Res. 9

Refer to Section 2.2 on page 51 for the register boundary addresses.

Res. Res. Res. Res. Res. 8
Res. Res. Res. Res. 7
TRGFLT
0 0

If LPTIM does not support encoder mode feature, this bit is reserved. Please refer to Section 19.3: LPTIM implementation.
Res. DOWNIE(1) DOWNCF(1) DOWN(1) 6

CNT[15:0]
ARR[15:0]
CMP[15:0]
Res. Res. UPIE(1) UPCF(1) UP(1) 5
Res. ARROKIE ARROKCF ARROK 4
CKFLT
Res. CMPOKIE CMPOKCF CMPOK 3
CNTSTRT EXTTRIGIE EXTTRIGCF EXTTRIG 2
CKPOL
SNGSTRT ARRMIE ARRMCF ARRM 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0

0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0

ENABLE CKSEL CMPMIE CMPMCF CMPM 0

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Independent watchdog (IWDG) RM0377

20 Independent watchdog (IWDG)

20.1 Introduction
The devices feature an embedded watchdog peripheral that offers a combination of high
safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral
detects and solves malfunctions due to software failure, and triggers system reset when the
counter reaches a given timeout value.
The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI)
and thus stays active even if the main clock fails.
The IWDG is best suited for applications that require the watchdog to run as a totally
independent process outside the main application, but have lower timing accuracy
constraints. For further information on the window watchdog, refer to Section 21 on page
537.

20.2 IWDG main features

• Free-running downcounter
• Clocked from an independent RC oscillator (can operate in Standby and Stop modes)
• Conditional reset
– Reset (if watchdog activated) when the downcounter value becomes lower than
0x000
– Reset (if watchdog activated) if the downcounter is reloaded outside the window

20.3 IWDG functional description

20.3.1 IWDG block diagram

Figure 178 shows the functional blocks of the independent watchdog module.

Figure 178. Independent watchdog block diagram

VDD
Prescaler register Status register Reload register Key register
IWDG_PR IWDG_SR IWDG_RLR IWDG_KR

12-bit reload value

LSI 8-bit
(32 kHz) prescaler
12-bit downcounter IWDG reset
VDD voltage domain

MSv37838V1

1. The register interface is located in the VDD voltage domain. The watchdog function is located in the VDD
voltage domain, still functional in Standby mode.

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RM0377 Independent watchdog (IWDG)

When the independent watchdog is started by writing the value 0x0000 CCCC in the IWDG
key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF.
When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset).
Whenever the key value 0x0000 AAAA is written in the IWDG key register (IWDG_KR), the
IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented.
Once running, the IWDG cannot be stopped.

20.3.2 Window option

The IWDG can also work as a window watchdog by setting the appropriate window in the
IWDG window register (IWDG_WINR).
If the reload operation is performed while the counter is greater than the value stored in the
IWDG window register (IWDG_WINR), then a reset is provided.
The default value of the IWDG window register (IWDG_WINR) is 0x0000 0FFF, so if it is not
updated, the window option is disabled.
As soon as the window value is changed, a reload operation is performed in order to reset
the downcounter to the IWDG reload register (IWDG_RLR) value and ease the cycle
number calculation to generate the next reload.

Configuring the IWDG when the window option is enabled

1. Enable the IWDG by writing 0x0000 CCCC in the IWDG key register (IWDG_KR).
2. Enable register access by writing 0x0000 5555 in the IWDG key register (IWDG_KR).
3. Write the IWDG prescaler by programming IWDG prescaler register (IWDG_PR) from
0 to 7.
4. Write the IWDG reload register (IWDG_RLR).
5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000).
6. Write to the IWDG window register (IWDG_WINR). This automatically refreshes the
counter value in the IWDG reload register (IWDG_RLR).
Note: Writing the window value allows the counter value to be refreshed by the RLR when IWDG
status register (IWDG_SR) is set to 0x0000 0000.
For code example, refer to A.11.2: IWDG configuration with window code example.

Configuring the IWDG when the window option is disabled

When the window option it is not used, the IWDG can be configured as follows:
1. Enable the IWDG by writing 0x0000 CCCC in the IWDG key register (IWDG_KR).
2. Enable register access by writing 0x0000 5555 in the IWDG key register (IWDG_KR).
3. Write the prescaler by programming the IWDG prescaler register (IWDG_PR) from 0 to
7.
4. Write the IWDG reload register (IWDG_RLR).
5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000).
6. Refresh the counter value with IWDG_RLR (IWDG_KR = 0x0000 AAAA).
For code example, refer to A.11.1: IWDG configuration code example.

RM0377 Rev 10 529/905

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Independent watchdog (IWDG) RM0377

20.3.3 Hardware watchdog

If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog
is automatically enabled at power-on, and generates a reset unless the IWDG key register
(IWDG_KR) is written by the software before the counter reaches end of count or if the
downcounter is reloaded inside the window.

20.3.4 Register access protection

Write access to IWDG prescaler register (IWDG_PR), IWDG reload register (IWDG_RLR)
and IWDG window register (IWDG_WINR) is protected. To modify them, the user must first
write the code 0x0000 5555 in the IWDG key register (IWDG_KR). A write access to this
register with a different value breaks the sequence and register access is protected again.
This is the case of the reload operation (writing 0x0000 AAAA).
A status register is available to indicate that an update of the prescaler or of the
downcounter reload value or of the window value is ongoing.

20.3.5 Debug mode

When the device enters Debug mode (core halted), the IWDG counter either continues to
work normally or stops, depending on the configuration of the corresponding bit in
DBGCMU freeze register.

530/905 RM0377 Rev 10

RM0377 Independent watchdog (IWDG)

20.4 IWDG registers

Refer to Section 1.2 on page 45 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

20.4.1 IWDG key register (IWDG_KR)

Address offset: 0x00
Reset value: 0x0000 0000 (reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[15:0]
w w w w w w w w w w w w w w w w

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 KEY[15:0]: Key value (write only, read 0x0000)
These bits must be written by software at regular intervals with the key value 0xAAAA,
otherwise the watchdog generates a reset when the counter reaches 0.
Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and
IWDG_WINR registers (see Section 20.3.4: Register access protection)
Writing the key value 0xCCCC starts the watchdog (except if the hardware watchdog option
is selected)

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Independent watchdog (IWDG) RM0377

20.4.2 IWDG prescaler register (IWDG_PR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PR[2:0]

rw rw rw

Bits 31:3 Reserved, must be kept at reset value.

Bits 2:0 PR[2:0]: Prescaler divider
These bits are write access protected see Section 20.3.4: Register access protection. They
are written by software to select the prescaler divider feeding the counter clock. PVU bit of
the IWDG status register (IWDG_SR) must be reset in order to be able to change the
prescaler divider.
000: divider /4
001: divider /8
010: divider /16
011: divider /32
100: divider /64
101: divider /128
110: divider /256
111: divider /256
Note: Reading this register returns the prescaler value from the VDD voltage domain. This
value may not be up to date/valid if a write operation to this register is ongoing. For this
reason the value read from this register is valid only when the PVU bit in the IWDG
status register (IWDG_SR) is reset.

532/905 RM0377 Rev 10

RM0377 Independent watchdog (IWDG)

20.4.3 IWDG reload register (IWDG_RLR)

Address offset: 0x08
Reset value: 0x0000 0FFF (reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. RL[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 RL[11:0]: Watchdog counter reload value
These bits are write access protected see Register access protection. They are written by
software to define the value to be loaded in the watchdog counter each time the value
0xAAAA is written in the IWDG key register (IWDG_KR). The watchdog counter counts
down from this value. The timeout period is a function of this value and the clock prescaler.
Refer to the datasheet for the timeout information.
The RVU bit in the IWDG status register (IWDG_SR) must be reset to be able to change the
reload value.
Note: Reading this register returns the reload value from the VDD voltage domain. This value
may not be up to date/valid if a write operation to this register is ongoing on it. For this
reason the value read from this register is valid only when the RVU bit in the IWDG
status register (IWDG_SR) is reset.

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20.4.4 IWDG status register (IWDG_SR)

Address offset: 0x0C
Reset value: 0x0000 0000 (not reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WVU RVU PVU

r r r

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 WVU: Watchdog counter window value update
This bit is set by hardware to indicate that an update of the window value is ongoing. It is
reset by hardware when the reload value update operation is completed in the VDD voltage
domain (takes up to five RC 40 kHz cycles).
Window value can be updated only when WVU bit is reset.
Bit 1 RVU: Watchdog counter reload value update
This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset
by hardware when the reload value update operation is completed in the VDD voltage domain
(takes up to five RC 40 kHz cycles).
Reload value can be updated only when RVU bit is reset.
Bit 0 PVU: Watchdog prescaler value update
This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is
reset by hardware when the prescaler update operation is completed in the VDD voltage
domain (takes up to five RC 40 kHz cycles).
Prescaler value can be updated only when PVU bit is reset.

Note: If several reload, prescaler, or window values are used by the application, it is mandatory to
wait until RVU bit is reset before changing the reload value, to wait until PVU bit is reset
before changing the prescaler value, and to wait until WVU bit is reset before changing the
window value. However, after updating the prescaler and/or the reload/window value it is not
necessary to wait until RVU or PVU or WVU is reset before continuing code execution
except in case of low-power mode entry.

534/905 RM0377 Rev 10

RM0377 Independent watchdog (IWDG)

20.4.5 IWDG window register (IWDG_WINR)

Address offset: 0x10
Reset value: 0x0000 0FFF (reset by Standby mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. WIN[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 WIN[11:0]: Watchdog counter window value
These bits are write access protected, see Section 20.3.4, they contain the high limit of the
window value to be compared with the downcounter.
To prevent a reset, the downcounter must be reloaded when its value is lower than the
window register value and greater than 0x0
The WVU bit in the IWDG status register (IWDG_SR) must be reset in order to be able to
change the reload value.
Note: Reading this register returns the reload value from the VDD voltage domain. This value
may not be valid if a write operation to this register is ongoing. For this reason the value
read from this register is valid only when the WVU bit in the IWDG status register
(IWDG_SR) is reset.

RM0377 Rev 10 535/905

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 0x10
0x08
0x04
0x00

0x0C
Offset

536/905
20.4.6

name

IWDG_SR
IWDG_PR
IWDG_KR
Register

Reset value
Reset value
Reset value
Reset value
Reset value

IWDG_RLR

IWDG_WINR
Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. 27
Independent watchdog (IWDG)

Res. Res. Res. Res. Res. 26

Res. Res. Res. Res. Res.
IWDG register map

25
Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. 18
Res. Res. Res. Res. Res. 17

RM0377 Rev 10
Res. Res. Res. Res. Res. 16
0

Res. Res. Res. Res. 15

0

Res. Res. Res. Res. 14

0

Res. Res. Res. Res. 13

0

Res. Res. Res. Res. 12

1
1
0

Res. Res. 11
Table 92. IWDG register map and reset values

1
1
0

Res. Res. 10
The following table gives the IWDG register map and reset values.

1
1
0

Res. Res. 9
Refer to Section 2.2 on page 51 for the register boundary addresses.
1
1
0

Res. Res. 8
1
1
0

Res. Res. 7
KEY[15:0]

1
1
0

Res. Res. 6
1
1
0

Res. Res. 5
RL[11:0]

WIN[11:0]

1
1
0

Res. Res. 4
1
1
0

Res. Res. 3
1
1
0

0
0

WVU 2
1
1
0

0
0

RVU 1
PR[2:0]

1
1
0

0
0

PVU
RM0377

0
RM0377 System window watchdog (WWDG)

21 System window watchdog (WWDG)

21.1 Introduction
The system window watchdog (WWDG) is used to detect the occurrence of a software fault,
usually generated by external interference or by unforeseen logical conditions, which
causes the application program to abandon its normal sequence. The watchdog circuit
generates an MCU reset on expiry of a programmed time period, unless the program
refreshes the contents of the down-counter before the T6 bit becomes cleared. An MCU
reset is also generated if the 7-bit down-counter value (in the control register) is refreshed
before the down-counter has reached the window register value. This implies that the
counter must be refreshed in a limited window.
The WWDG clock is prescaled from the APB1 clock and has a configurable time-window
that can be programmed to detect abnormally late or early application behavior.
The WWDG is best suited for applications which require the watchdog to react within an
accurate timing window.

21.2 WWDG main features

• Programmable free-running down-counter
• Conditional reset
– Reset (if watchdog activated) when the down-counter value becomes lower than
0x40
– Reset (if watchdog activated) if the down-counter is reloaded outside the window
(see Figure 180)
• Early wakeup interrupt (EWI): triggered (if enabled and the watchdog activated) when
the down-counter is equal to 0x40.

21.3 WWDG functional description

If the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the
7-bit down-counter (T[6:0] bits) is decremented from 0x40 to 0x3F (T6 becomes cleared), it
initiates a reset. If the software reloads the counter while the counter is greater than the
value stored in the window register, then a reset is generated.
The application program must write in the WWDG_CR register at regular intervals during
normal operation to prevent an MCU reset. This operation must occur only when the counter
value is lower than the window register value and higher than 0x3F. The value to be stored
in the WWDG_CR register must be between 0xFF and 0xC0.
Refer to Figure 179 for the WWDG block diagram.

RM0377 Rev 10 537/905

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System window watchdog (WWDG) RM0377

21.3.1 WWDG block diagram

Figure 179. Watchdog block diagram

WWDG
Register interface CMP = 1 when
W[6:0] T[6:0] > W[6:0]
APB bus

WWDG_CFR

CMP
wwdg_out_rst

WWDG_SR WDGA
Write to WWDG_CR
T[6:0] T6

= 0x40 ?
readback

Logic
WWDG_CR T[6:0] EWI wwdg_it
cnt_out EWIF
preload
7-bit DownCounter (CNT)

pclk ÷ 4096 ÷ 2WDGTB

MS47214V1

21.3.2 Enabling the watchdog

The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the
WWDG_CR register, then it cannot be disabled again except by a reset.

21.3.3 Controlling the down-counter

This down-counter is free-running, counting down even if the watchdog is disabled. When
the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset.
The T[5:0] bits contain the number of increments that represent the time delay before the
watchdog produces a reset. The timing varies between a minimum and a maximum value
due to the unknown status of the prescaler when writing to the WWDG_CR register (see
Figure 180). The WWDG configuration register (WWDG_CFR) contains the high limit of the
window: to prevent a reset, the down-counter must be reloaded when its value is lower than
the window register value and greater than 0x3F. Figure 180 describes the window
watchdog process.
Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).

21.3.4 How to program the watchdog timeout

Use the formula in Figure 180 to calculate the WWDG timeout.

Warning: When writing to the WWDG_CR register, always write 1 in the

T6 bit to avoid generating an immediate reset.

538/905 RM0377 Rev 10

RM0377 System window watchdog (WWDG)

Figure 180. Window watchdog timing diagram

CNT DownCounter
Refresh not allowed Refresh allowed

T[6:0]

W[6:0]

0x3F
Time
Tpclk x 4096 x 2WDGTB
0x41
0x40
0x3F

wwdg_ewit

EWIF = 0
wwdg_rst

T6 bit

MS47266V1

The formula to calculate the timeout value is given by:

WDGTB[1:0]
t WWDG = t PCLK1 × 4096 × 2 × ( T [ 5:0 ] + 1 ) ( ms )

where:
tWWDG: WWDG timeout
tPCLK: APB1 clock period measured in ms
4096: value corresponding to internal divider
As an example, if APB1 frequency is 32 MHz, WDGTB[1:0] is set to 3 and T[5:0] is set to 63:

3
t WWDG = ( 1 ⁄ 32000 ) × 4096 × 2 × ( 63 + 1 ) = 65.54ms

Refer to the datasheet for the minimum and maximum values of tWWDG.
For code example, refer to A.12.1: WWDG configuration code example.

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System window watchdog (WWDG) RM0377

21.3.5 Debug mode

When the device enters debug mode (processor halted), the WWDG counter either
continues to work normally or stops, depending on the configuration bit in DBG module. For
more details refer to Section 27.9.2: Debug support for timers, watchdog and I2C.

21.4 WWDG interrupts

The early wakeup interrupt (EWI) can be used if specific safety operations or data logging
must be performed before the actual reset is generated. The EWI interrupt is enabled by
setting the EWI bit in the WWDG_CFR register. When the down-counter reaches the value
0x40, an EWI interrupt is generated and the corresponding interrupt service routine (ISR)
can be used to trigger specific actions (such as communications or data logging) before
resetting the device.
In some applications the EWI interrupt can be used to manage a software system check
and/or system recovery/graceful degradation, without generating a WWDG reset. In this
case the corresponding ISR has to reload the WWDG counter to avoid the WWDG reset,
then trigger the required actions.
The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.
Note: When the EWI interrupt cannot be served (e.g. due to a system lock in a higher priority task)
the WWDG reset is eventually generated.

21.5 WWDG registers

Refer to Section 1.2 on page 45 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed by halfwords (16-bit) or words (32-bit).

21.5.1 WWDG control register (WWDG_CR)

Address offset: 0x000
Reset value: 0x0000 007F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. WDGA T[6:0]

rs rw rw rw rw rw rw rw

540/905 RM0377 Rev 10

RM0377 System window watchdog (WWDG)

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 WDGA: Activation bit
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)
These bits contain the value of the watchdog counter, decremented every
(4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to
0x3F (T6 becomes cleared).

21.5.2 WWDG configuration register (WWDG_CFR)

Address offset: 0x004
Reset value: 0x0000 007F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. EWI WDGTB[1:0] W[6:0]

rs rw rw rw rw rw rw rw rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bit 9 EWI: Early wakeup interrupt
When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is
only cleared by hardware after a reset.
Bits 8:7 WDGTB[1:0]: Timer base
The time base of the prescaler can be modified as follows:
00: CK counter clock (PCLK div 4096) div 1
01: CK counter clock (PCLK div 4096) div 2
10: CK counter clock (PCLK div 4096) div 4
11: CK counter clock (PCLK div 4096) div 8
Bits 6:0 W[6:0]: 7-bit window value
These bits contain the window value to be compared with the down-counter.

21.5.3 WWDG status register (WWDG_SR)

Address offset: 0x008
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EWIF
rc_w0

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Bits 31:1 Reserved, must be kept at reset value.

Bit 0 EWIF: Early wakeup interrupt flag
This bit is set by hardware when the counter has reached the value 0x40. It must be cleared
by software by writing 0. Writing 1 has no effect. This bit is also set if the interrupt is not
enabled.

21.5.4 WWDG register map

The following table gives the WWDG register map and reset values.

Table 93. WWDG register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
WDGA
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WWDG_CR T[6:0]
0x000

Reset value 0 1 1 1 1 1 1 1

WDGTB1
WDGTB0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EWI
WWDG_CFR W[6:0]
0x004

Reset value 0 0 0 1 1 1 1 1 1 1

EWIF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WWDG_SR
0x008

Reset value 0

Refer to Section 2.2 on page 51 for the register boundary addresses.

542/905 RM0377 Rev 10

RM0377 Real-time clock (RTC)

22 Real-time clock (RTC)

22.1 Introduction
The RTC provides an automatic wakeup to manage all low-power modes.
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a time-
of-day clock/calendar with programmable alarm interrupts.
The RTC includes also a periodic programmable wakeup flag with interrupt capability.
Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day
of week), date (day of month), month, and year, expressed in binary coded decimal format
(BCD). The sub-seconds value is also available in binary format.
Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed
automatically. Daylight saving time compensation can also be performed.
Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes,
hours, day, and date.
A digital calibration feature is available to compensate for any deviation in crystal oscillator
accuracy.
After RTC domain reset, all RTC registers are protected against possible parasitic write
accesses.
As long as the supply voltage remains in the operating range, the RTC never stops,
regardless of the device status (Run mode, low-power mode or under reset).

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Real-time clock (RTC) RM0377

22.2 RTC main features

The RTC unit main features are the following (see Figure 181: RTC block diagram):
• Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of
week), date (day of month), month, and year.
• Daylight saving compensation programmable by software.
• Programmable alarm with interrupt function. The alarm can be triggered by any
combination of the calendar fields.
• Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup
interrupt.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Accurate synchronization with an external clock using the subsecond shift feature.
• Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a
calibration window of several seconds
• Time-stamp function for event saving
• Tamper detection event with configurable filter and internal pull-up
• Maskable interrupts/events:
– Alarm A
– Alarm B
– Wakeup interrupt
– Time-stamp
– Tamper detection
• 5 backup registers.

22.3 RTC implementation

Table 94. RTC implementation(1)
RTC Features Category 1 Category 2 Category 3 Category 5

Periodic wakeup timer X X X X

RTC_TAMP1 - X X X
RTC_TAMP2 X X X X
RTC_TAMP3 X X - X
Alarm A X X X X
Alarm B X X X X
1. X = supported, ‘-’= not supported.

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RM0377 Real-time clock (RTC)

22.4 RTC functional description

22.4.1 RTC block diagram

Figure 181. RTC block diagram

RTC_TAMP2
Backup registers
RTC_TAMP1 and RTC tamper TAMPxF
control registers
RTC_TAMP3

RTC_TS Time stamp

TSF
registers
RTC_REFIN

LSE (32.768 Hz)

HSE
prescaled
LSI
RTCCLK

RTC_CALR RTC_PRER ck_apre RTC_PRER ck_spre

(default 256 Hz) (default 1 Hz)
Asynchronous Synchronous
Smooth
7-bit prescaler 15-bit prescaler
calibration
(default = 128) (default = 256) Calendar

Shadow register Shadow registers

RTC_SSR RTC_TR,
RTC_DR
WUCKSEL[1:0]

Prescaler
2, 4, 8, 16

RTC_CALIB

Ouput RTC_OUT
RTC_ALARM control

RTC_WUTR

WUTF
16-bit wakeup
auto reload timer

OSEL[1:0]

Alarm A
= ALRAF
RTC_ALRMAR
RTC_ALRMASSR

Alarm B
= ALRBF
RTC_ALRMBR
RTC_ALRMBSSR

MS33460V5

1. RTC_TAMP3 is available only on category 1, category 2 and category 5 devices.

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The RTC includes:

• Two alarms
• Up to three tamper events from I/Os
– Tamper detection erases the backup registers.
• One timestamp event from I/O
• Tamper event detection can generate a timestamp event
• 5 x 32-bit backup registers
• Output functions: RTC_OUT which selects one of the following two outputs:
– RTC_CALIB: 512 Hz or 1Hz clock output (with an LSE frequency of 32.768 kHz).
This output is enabled by setting the COE bit in the RTC_CR register.
– RTC_ALARM: This output is enabled by configuring the OSEL[1:0] bits in the
RTC_CR register which select the Alarm A, Alarm B or Wakeup outputs.
• Input functions:
– RTC_TS: timestamp event
– RTC_TAMP1: tamper1 event detection
– RTC_TAMP2: tamper2 event detection
– RTC_TAMP3: tamper3 event detection (only on category 1, category 2 and
category 5 devices).
– RTC_REFIN: 50 or 60 Hz reference clock input

22.4.2 GPIOs controlled by the RTC

RTC_OUT, RTC_TS and RTC_TAMP1 are mapped on the same pin (PC13). PC13 pin
configuration is controlled by the RTC, whatever the PC13 GPIO configuration, except for
the RTC_ALARM output open-drain mode.
The output mechanism follows the priority order shown in Table 95.

Table 95. RTC pin PC13 configuration(1)

OSEL[1:0]
COE bit TAMP1E bit TSE bit
PC13 Pin bits RTC_OUT RTC_ALARM
(RTC_CALIB (RTC_TAMP1 (RTC_TS
configuration (RTC_ALARM _RMP _TYPE
output input input
and function output bit bit
enable) enable) enable)
enable)

RTC_ALARM 0
01 or 10 or 11 Don’t care 0 Don’t care Don’t care
output OD 1

RTC_ALARM 0
01 or 10 or 11 Don’t care 1 Don’t care Don’t care
output PP 1
RTC_CALIB
00 1 0 Don’t care Don’t care Don’t care
output PP
00 0 Don’t care
RTC_TAMP1
00 1 Don’t care 1 0
input floating 1
01 or 10 or 11 0

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Table 95. RTC pin PC13 configuration(1) (continued)

OSEL[1:0]
COE bit TAMP1E bit TSE bit
PC13 Pin bits RTC_OUT RTC_ALARM
(RTC_CALIB (RTC_TAMP1 (RTC_TS
configuration (RTC_ALARM _RMP _TYPE
output input input
and function output bit bit
enable) enable) enable)
enable)

00 0 Don’t care
RTC_TS and
RTC_TAMP1 00 1 Don’t care 1 1
input floating 1
01 or 10 or 11 0
00 0 Don’t care
RTC_TS input
00 1 Don’t care 0 1
floating 1
01 or 10 or 11 0
00 0 Don’t care
Wakeup pin or
Standard 00 1 Don’t care 0 0
GPIO 1
01 or 10 or 11 0
1. OD: open drain; PP: push-pull.

In addition, it is possible to remap RTC_OUT on PB14 pin thanks to RTC_OUT_RMP bit. In

this case it is mandatory to configure PB14 GPIO registers as alternate function with the
correct type. The remap functions are shown in Table 96.

Table 96. RTC_OUT mapping

OSEL[1:0] bits COE bit
RTC_OUT_RMP
(RTC_ALARM (RTC_CALIB output RTC_OUT on PC13 RTC_OUT on PB14
bit
output enable) enable)

00 0 - -
00 1 0 RTC_CALIB -
01 or 10 or 11 Don’t care RTC_ALARM -
00 0 - -
00 1 - RTC_CALIB
1
01 or 10 or 11 0 - RTC_ALARM
01 or 10 or 11 1 RTC_ALARM RTC_CALIB

22.4.3 Clock and prescalers

The RTC clock source (RTCCLK) is selected through the clock controller among the LSE
clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock
source configuration, refer to Section 7: Reset and clock control (RCC).

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A programmable prescaler stage generates a 1 Hz clock which is used to update the

calendar. To minimize power consumption, the prescaler is split into 2 programmable
prescalers (see Figure 181: RTC block diagram):
• A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the
RTC_PRER register.
• A 15-bit synchronous prescaler configured through the PREDIV_S bits of the
RTC_PRER register.
Note: When both prescalers are used, it is recommended to configure the asynchronous prescaler
to a high value to minimize consumption.
The asynchronous prescaler division factor is set to 128, and the synchronous division
factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency
of 32.768 kHz.
The minimum division factor is 1 and the maximum division factor is 222.
This corresponds to a maximum input frequency of around 4 MHz.
fck_apre is given by the following formula:
f RTCCLK
f CK_APRE = --------------------------------------
-
PREDIV_A + 1

The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it
reaches 0, RTC_SSR is reloaded with the content of PREDIV_S.
fck_spre is given by the following formula:
f RTCCLK
f CK_SPRE = ----------------------------------------------------------------------------------------------
( PREDIV_S + 1 ) × ( PREDIV_A + 1 )

The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit
wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload
timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous
prescaler (see Section 22.4.6: Periodic auto-wakeup for details).

22.4.4 Real-time clock and calendar

The RTC calendar time and date registers are accessed through shadow registers which
are synchronized with PCLK (APB clock). They can also be accessed directly in order to
avoid waiting for the synchronization duration.
• RTC_SSR for the subseconds
• RTC_TR for the time
• RTC_DR for the date
Every RTCCLK period, the current calendar value is copied into the shadow registers, and
the RSF bit of RTC_ISR register is set (see Section 22.7.4: RTC initialization and status
register (RTC_ISR)). The copy is not performed in Stop and Standby mode. When exiting
these modes, the shadow registers are updated after up to 1 RTCCLK period.
When the application reads the calendar registers, it accesses the content of the shadow
registers. It is possible to make a direct access to the calendar registers by setting the

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BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user
accesses the shadow registers.
When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the
frequency of the APB clock (fAPB) must be at least 7 times the frequency of the RTC clock
(fRTCCLK).
The shadow registers are reset by system reset.

22.4.5 Programmable alarms

The RTC unit provides programmable alarm: Alarm A and Alarm B. The description below is
given for Alarm A, but can be translated in the same way for Alarm B.
The programmable alarm function is enabled through the ALRAE bit in the RTC_CR
register. The ALRAF is set to 1 if the calendar subseconds, seconds, minutes, hours, date
or day match the values programmed in the alarm registers RTC_ALRMASSR and
RTC_ALRMAR. Each calendar field can be independently selected through the MSKx bits
of the RTC_ALRMAR register, and through the MASKSSx bits of the RTC_ALRMASSR
register. The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register.
Caution: If the seconds field is selected (MSK1 bit reset in RTC_ALRMAR), the synchronous
prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct
behavior.
Alarm A and Alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the
RTC_ALARM output. RTC_ALARM output polarity can be configured through bit POL the
RTC_CR register.

22.4.6 Periodic auto-wakeup

The periodic wakeup flag is generated by a 16-bit programmable auto-reload down-counter.
The wakeup timer range can be extended to 17 bits.
The wakeup function is enabled through the WUTE bit in the RTC_CR register.
The wakeup timer clock input can be:
• RTC clock (RTCCLK) divided by 2, 4, 8, or 16.
When RTCCLK is LSE(32.768kHz), this allows to configure the wakeup interrupt period
from 122 µs to 32 s, with a resolution down to 61 µs.
• ck_spre (usually 1 Hz internal clock)
When ck_spre frequency is 1Hz, this allows to achieve a wakeup time from 1 s to
around 36 hours with one-second resolution. This large programmable time range is
divided in 2 parts:
– from 1s to 18 hours when WUCKSEL [2:1] = 10
– and from around 18h to 36h when WUCKSEL[2:1] = 11. In this last case 216 is
added to the 16-bit counter current value.When the initialization sequence is
complete (see Programming the wakeup timer on page 551), the timer starts
counting down.When the wakeup function is enabled, the down-counting remains
active in low-power modes. In addition, when it reaches 0, the WUTF flag is set in
the RTC_ISR register, and the wakeup counter is automatically reloaded with its
reload value (RTC_WUTR register value).
The WUTF flag must then be cleared by software.

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When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR
register, it can exit the device from low-power modes.
The periodic wakeup flag can be routed to the RTC_ALARM output provided it has been
enabled through bits OSEL[1:0] of RTC_CR register. RTC_ALARM output polarity can be
configured through the POL bit in the RTC_CR register.
System reset, as well as low-power modes (Sleep, Stop and Standby) have no influence on
the wakeup timer.

22.4.7 RTC initialization and configuration

RTC register access
The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC
register accesses except on read accesses to calendar shadow registers when
BYPSHAD=0.

RTC register write protection

After system reset, the RTC registers are protected against parasitic write access by
clearing the DBP bit in the PWR_CR register (refer to the power control section). DBP bit
must be set in order to enable RTC registers write access.
After RTC domain reset, all the RTC registers are write-protected. Writing to the RTC
registers is enabled by writing a key into the Write Protection register, RTC_WPR.
The following steps are required to unlock the write protection on all the RTC registers
except for RTC_TAMPCR, RTC_BKPxR, RTC_OR and RTC_ISR[13:8].
1. Write ‘0xCA’ into the RTC_WPR register.
2. Write ‘0x53’ into the RTC_WPR register.
Writing a wrong key reactivates the write protection.
The protection mechanism is not affected by system reset.

Calendar initialization and configuration

To program the initial time and date calendar values, including the time format and the
prescaler configuration, the following sequence is required:
1. Set INIT bit to 1 in the RTC_ISR register to enter initialization mode. In this mode, the
calendar counter is stopped and its value can be updated.
2. Poll INITF bit of in the RTC_ISR register. The initialization phase mode is entered when
INITF is set to 1. It takes around 2 RTCCLK clock cycles (due to clock synchronization).
3. To generate a 1 Hz clock for the calendar counter, program both the prescaler factors in
RTC_PRER register.
4. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR),
and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR
register.
5. Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is
then automatically loaded and the counting restarts after 4 RTCCLK clock cycles.
When the initialization sequence is complete, the calendar starts counting.

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Note: After a system reset, the application can read the INITS flag in the RTC_ISR register to
check if the calendar has been initialized or not. If this flag equals 0, the calendar has not
been initialized since the year field is set at its RTC domain reset default value (0x00).
To read the calendar after initialization, the software must first check that the RSF flag is set
in the RTC_ISR register.
For code example, refer to A.13.1: RTC calendar configuration code example.

Daylight saving time

The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP
of the RTC_CR register.
Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one
single operation without going through the initialization procedure.
In addition, the software can use the BKP bit to memorize this operation.

Programming the alarm

A similar procedure must be followed to program or update the programmable alarms. The
procedure below is given for Alarm A but can be translated in the same way for Alarm B.
1. Clear ALRAE in RTC_CR to disable Alarm A.
2. Program the Alarm A registers (RTC_ALRMASSR/RTC_ALRMAR).
3. Set ALRAE in the RTC_CR register to enable Alarm A again.
Note: Each change of the RTC_CR register is taken into account after around 2 RTCCLK clock
cycles due to clock synchronization.
For code example, refer to A.13.2: RTC alarm configuration code example.

Programming the wakeup timer

The following sequence is required to configure or change the wakeup timer auto-reload
value (WUT[15:0] in RTC_WUTR):
1. Clear WUTE in RTC_CR to disable the wakeup timer.
2. Poll WUTWF until it is set in RTC_ISR to make sure the access to wakeup auto-reload
counter and to WUCKSEL[2:0] bits is allowed. It takes around 2 RTCCLK clock cycles
(due to clock synchronization).
3. Program the wakeup auto-reload value WUT[15:0], and the wakeup clock selection
(WUCKSEL[2:0] bits in RTC_CR). Set WUTE in RTC_CR to enable the timer again.
The wakeup timer restarts down-counting. The WUTWF bit is cleared up to 2 RTCCLK
clock cycles after WUTE is cleared, due to clock synchronization.
For code example, refer to A.13.3: RTC WUT configuration code example.

22.4.8 Reading the calendar

When BYPSHAD control bit is cleared in the RTC_CR register
To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB1
clock frequency (fPCLK) must be equal to or greater than seven times the RTC clock
frequency (fRTCCLK). This ensures a secure behavior of the synchronization mechanism.

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If the APB1 clock frequency is less than seven times the RTC clock frequency, the software
must read the calendar time and date registers twice. If the second read of the RTC_TR
gives the same result as the first read, this ensures that the data is correct. Otherwise a third
read access must be done. In any case the APB1 clock frequency must never be lower than
the RTC clock frequency.
The RSF bit is set in RTC_ISR register each time the calendar registers are copied into the
RTC_SSR, RTC_TR and RTC_DR shadow registers. The copy is performed every
RTCCLK cycle. To ensure consistency between the 3 values, reading either RTC_SSR or
RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is
read. In case the software makes read accesses to the calendar in a time interval smaller
than 1 RTCCLK period: RSF must be cleared by software after the first calendar read, and
then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR
and RTC_DR registers.
After waking up from low-power mode (Stop or Standby), RSF must be cleared by software.
The software must then wait until it is set again before reading the RTC_SSR, RTC_TR and
RTC_DR registers.
The RSF bit must be cleared after wakeup and not before entering low-power mode.
After a system reset, the software must wait until RSF is set before reading the RTC_SSR,
RTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to
their default values.
After an initialization (refer to Calendar initialization and configuration on page 550): the
software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR
registers.
After synchronization (refer to Section 22.4.10: RTC synchronization): the software must
wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers.
For code example, refer to A.13.4: RTC read calendar code example.

When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow
registers)
Reading the calendar registers gives the values from the calendar counters directly, thus
eliminating the need to wait for the RSF bit to be set. This is especially useful after exiting
from low-power modes (STOP or Standby), since the shadow registers are not updated
during these modes.
When the BYPSHAD bit is set to 1, the results of the different registers might not be
coherent with each other if an RTCCLK edge occurs between two read accesses to the
registers. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge
occurs during the read operation. The software must read all the registers twice, and then
compare the results to confirm that the data is coherent and correct. Alternatively, the
software can just compare the two results of the least-significant calendar register.
Note: While BYPSHAD=1, instructions which read the calendar registers require one extra APB
cycle to complete.

22.4.9 Resetting the RTC

The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the
RTC status register (RTC_ISR) are reset to their default values by all available system reset
sources.

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On the contrary, the following registers are reset to their default values by a RTC domain
reset and are not affected by a system reset: the RTC current calendar registers, the RTC
control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration register
(RTC_CALR), the RTC shift register (RTC_SHIFTR), the RTC timestamp registers
(RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC tamper configuration register
(RTC_TAMPCR), the RTC backup registers (RTC_BKPxR), the wakeup timer register
(RTC_WUTR), the Alarm A and Alarm B registers (RTC_ALRMASSR/RTC_ALRMAR and
RTC_ALRMBSSR/RTC_ALRMBR), and the Option register (RTC_OR).
In addition, when it is clocked by the LSE, the RTC keeps on running under system reset if
the reset source is different from the RTC domain reset one (refer to the RTC clock section
of the Reset and clock controller for details on the list of RTC clock sources not affected by
system reset). When a RTC domain reset occurs, the RTC is stopped and all the RTC
registers are set to their reset values.

22.4.10 RTC synchronization

The RTC can be synchronized to a remote clock with a high degree of precision. After
reading the sub-second field (RTC_SSR or RTC_TSSSR), a calculation can be made of the
precise offset between the times being maintained by the remote clock and the RTC. The
RTC can then be adjusted to eliminate this offset by “shifting” its clock by a fraction of a
second using RTC_SHIFTR.
RTC_SSR contains the value of the synchronous prescaler counter. This allows one to
calculate the exact time being maintained by the RTC down to a resolution of
1 / (PREDIV_S + 1) seconds. As a consequence, the resolution can be improved by
increasing the synchronous prescaler value (PREDIV_S[14:0]. The maximum resolution
allowed (30.52 μs with a 32768 Hz clock) is obtained with PREDIV_S set to 0x7FFF.
However, increasing PREDIV_S means that PREDIV_A must be decreased in order to
maintain the synchronous prescaler output at 1 Hz. In this way, the frequency of the
asynchronous prescaler output increases, which may increase the RTC dynamic
consumption.
The RTC can be finely adjusted using the RTC shift control register (RTC_SHIFTR). Writing
to RTC_SHIFTR can shift (either delay or advance) the clock by up to a second with a
resolution of 1 / (PREDIV_S + 1) seconds. The shift operation consists of adding the
SUBFS[14:0] value to the synchronous prescaler counter SS[15:0]: this will delay the clock.
If at the same time the ADD1S bit is set, this results in adding one second and at the same
time subtracting a fraction of second, so this will advance the clock.
Caution: Before initiating a shift operation, the user must check that SS[15] = 0 in order to ensure that
no overflow will occur.
As soon as a shift operation is initiated by a write to the RTC_SHIFTR register, the SHPF
flag is set by hardware to indicate that a shift operation is pending. This bit is cleared by
hardware as soon as the shift operation has completed.
Caution: This synchronization feature is not compatible with the reference clock detection feature:
firmware must not write to RTC_SHIFTR when REFCKON=1.

22.4.11 RTC reference clock detection

The update of the RTC calendar can be synchronized to a reference clock, RTC_REFIN,
which is usually the mains frequency (50 or 60 Hz). The precision of the RTC_REFIN
reference clock should be higher than the 32.768 kHz LSE clock. When the RTC_REFIN

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detection is enabled (REFCKON bit of RTC_CR set to 1), the calendar is still clocked by the
LSE, and RTC_REFIN is used to compensate for the imprecision of the calendar update
frequency (1 Hz).
Each 1 Hz clock edge is compared to the nearest RTC_REFIN clock edge (if one is found
within a given time window). In most cases, the two clock edges are properly aligned. When
the 1 Hz clock becomes misaligned due to the imprecision of the LSE clock, the RTC shifts
the 1 Hz clock a bit so that future 1 Hz clock edges are aligned. Thanks to this mechanism,
the calendar becomes as precise as the reference clock.
The RTC detects if the reference clock source is present by using the 256 Hz clock
(ck_apre) generated from the 32.768 kHz quartz. The detection is performed during a time
window around each of the calendar updates (every 1 s). The window equals 7 ck_apre
periods when detecting the first reference clock edge. A smaller window of 3 ck_apre
periods is used for subsequent calendar updates.
Each time the reference clock is detected in the window, the synchronous prescaler which
outputs the ck_spre clock is forced to reload. This has no effect when the reference clock
and the 1 Hz clock are aligned because the prescaler is being reloaded at the same
moment. When the clocks are not aligned, the reload shifts future 1 Hz clock edges a little
for them to be aligned with the reference clock.
If the reference clock halts (no reference clock edge occurred during the 3 ck_apre window),
the calendar is updated continuously based solely on the LSE clock. The RTC then waits for
the reference clock using a large 7 ck_apre period detection window centered on the
ck_spre edge.
When the RTC_REFIN detection is enabled, PREDIV_A and PREDIV_S must be set to their
default values:
• PREDIV_A = 0x007F
• PREVID_S = 0x00FF
Note: RTC_REFIN clock detection is not available in Standby mode.

22.4.12 RTC smooth digital calibration

The RTC frequency can be digitally calibrated with a resolution of about 0.954 ppm with a
range from -487.1 ppm to +488.5 ppm. The correction of the frequency is performed using
series of small adjustments (adding and/or subtracting individual RTCCLK pulses). These
adjustments are fairly well distributed so that the RTC is well calibrated even when observed
over short durations of time.
The smooth digital calibration is performed during a cycle of about 220 RTCCLK pulses, or
32 seconds when the input frequency is 32768 Hz. This cycle is maintained by a 20-bit
counter, cal_cnt[19:0], clocked by RTCCLK.
The smooth calibration register (RTC_CALR) specifies the number of RTCCLK clock cycles
to be masked during the 32-second cycle:
• Setting the bit CALM[0] to 1 causes exactly one pulse to be masked during the 32-
second cycle.
• Setting CALM[1] to 1 causes two additional cycles to be masked
• Setting CALM[2] to 1 causes four additional cycles to be masked
• and so on up to CALM[8] set to 1 which causes 256 clocks to be masked.

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Note: CALM[8:0] (RTC_CALR) specifies the number of RTCCLK pulses to be masked during the
32-second cycle. Setting the bit CALM[0] to ‘1’ causes exactly one pulse to be masked
during the 32-second cycle at the moment when cal_cnt[19:0] is 0x80000; CALM[1]=1
causes two other cycles to be masked (when cal_cnt is 0x40000 and 0xC0000); CALM[2]=1
causes four other cycles to be masked (cal_cnt = 0x20000/0x60000/0xA0000/ 0xE0000);
and so on up to CALM[8]=1 which causes 256 clocks to be masked (cal_cnt = 0xXX800).
While CALM allows the RTC frequency to be reduced by up to 487.1 ppm with fine
resolution, the bit CALP can be used to increase the frequency by 488.5 ppm. Setting CALP
to ‘1’ effectively inserts an extra RTCCLK pulse every 211 RTCCLK cycles, which means
that 512 clocks are added during every 32-second cycle.
Using CALM together with CALP, an offset ranging from -511 to +512 RTCCLK cycles can
be added during the 32-second cycle, which translates to a calibration range of -487.1 ppm
to +488.5 ppm with a resolution of about 0.954 ppm.
The formula to calculate the effective calibrated frequency (FCAL) given the input frequency
(FRTCCLK) is as follows:
FCAL = FRTCCLK x [1 + (CALP x 512 - CALM) / (220 + CALM - CALP x 512)]

Calibration when PREDIV_A<3

The CALP bit can not be set to 1 when the asynchronous prescaler value (PREDIV_A bits in
RTC_PRER register) is less than 3. If CALP was already set to 1 and PREDIV_A bits are
set to a value less than 3, CALP is ignored and the calibration operates as if CALP was
equal to 0.
To perform a calibration with PREDIV_A less than 3, the synchronous prescaler value
(PREDIV_S) should be reduced so that each second is accelerated by 8 RTCCLK clock
cycles, which is equivalent to adding 256 clock cycles every 32 seconds. As a result,
between 255 and 256 clock pulses (corresponding to a calibration range from 243.3 to
244.1 ppm) can effectively be added during each 32-second cycle using only the CALM bits.
With a nominal RTCCLK frequency of 32768 Hz, when PREDIV_A equals 1 (division factor
of 2), PREDIV_S should be set to 16379 rather than 16383 (4 less). The only other
interesting case is when PREDIV_A equals 0, PREDIV_S should be set to 32759 rather
than 32767 (8 less).
If PREDIV_S is reduced in this way, the formula given the effective frequency of the
calibrated input clock is as follows:
FCAL = FRTCCLK x [1 + (256 - CALM) / (220 + CALM - 256)]
In this case, CALM[7:0] equals 0x100 (the midpoint of the CALM range) is the correct
setting if RTCCLK is exactly 32768.00 Hz.

Verifying the RTC calibration

RTC precision is ensured by measuring the precise frequency of RTCCLK and calculating
the correct CALM value and CALP values. An optional 1 Hz output is provided to allow
applications to measure and verify the RTC precision.
Measuring the precise frequency of the RTC over a limited interval can result in a
measurement error of up to 2 RTCCLK clock cycles over the measurement period,
depending on how the digital calibration cycle is aligned with the measurement period.

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However, this measurement error can be eliminated if the measurement period is the same
length as the calibration cycle period. In this case, the only error observed is the error due to
the resolution of the digital calibration.
• By default, the calibration cycle period is 32 seconds.
Using this mode and measuring the accuracy of the 1 Hz output over exactly 32 seconds
guarantees that the measure is within 0.477 ppm (0.5 RTCCLK cycles over 32 seconds, due
to the limitation of the calibration resolution).
• CALW16 bit of the RTC_CALR register can be set to 1 to force a 16- second calibration
cycle period.
In this case, the RTC precision can be measured during 16 seconds with a maximum error
of 0.954 ppm (0.5 RTCCLK cycles over 16 seconds). However, since the calibration
resolution is reduced, the long term RTC precision is also reduced to 0.954 ppm: CALM[0]
bit is stuck at 0 when CALW16 is set to 1.
• CALW8 bit of the RTC_CALR register can be set to 1 to force a 8- second calibration
cycle period.
In this case, the RTC precision can be measured during 8 seconds with a maximum error of
1.907 ppm (0.5 RTCCLK cycles over 8s). The long term RTC precision is also reduced to
1.907 ppm: CALM[1:0] bits are stuck at 00 when CALW8 is set to 1.

Re-calibration on-the-fly
The calibration register (RTC_CALR) can be updated on-the-fly while RTC_ISR/INITF=0, by
using the follow process:
1. Poll the RTC_ISR/RECALPF (re-calibration pending flag).
2. If it is set to 0, write a new value to RTC_CALR, if necessary. RECALPF is then
automatically set to 1
3. Within three ck_apre cycles after the write operation to RTC_CALR, the new calibration
settings take effect.
For code example, refer to A.13.5: RTC calibration code example.

22.4.13 Time-stamp function

Time-stamp is enabled by setting the TSE bit of RTC_CR register to 1.
The calendar is saved in the time-stamp registers (RTC_TSSSR, RTC_TSTR, RTC_TSDR)
when a time-stamp event is detected on the RTC_TS pin.
When a time-stamp event occurs, the time-stamp flag bit (TSF) in RTC_ISR register is set.
By setting the TSIE bit in the RTC_CR register, an interrupt is generated when a time-stamp
event occurs.
If a new time-stamp event is detected while the time-stamp flag (TSF) is already set, the
time-stamp overflow flag (TSOVF) flag is set and the time-stamp registers (RTC_TSTR and
RTC_TSDR) maintain the results of the previous event.

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Note: TSF is set 2 ck_apre cycles after the time-stamp event occurs due to synchronization
process.
There is no delay in the setting of TSOVF. This means that if two time-stamp events are
close together, TSOVF can be seen as '1' while TSF is still '0'. As a consequence, it is
recommended to poll TSOVF only after TSF has been set.
Caution: If a time-stamp event occurs immediately after the TSF bit is supposed to be cleared, then
both TSF and TSOVF bits are set.To avoid masking a time-stamp event occurring at the
same moment, the application must not write ‘0’ into TSF bit unless it has already read it to
‘1’.
Optionally, a tamper event can cause a time-stamp to be recorded. See the description of
the TAMPTS control bit in Section 22.7.16: RTC tamper configuration register
(RTC_TAMPCR).

22.4.14 Tamper detection

The RTC_TAMPx input events can be configured either for edge detection, or for level
detection with filtering.
The tamper detection can be configured for the following purposes:
• erase the RTC backup registers (default configuration)
• generate an interrupt, capable to wakeup from Stop and Standby modes
• generate a hardware trigger for the low-power timers

RTC backup registers

The backup registers (RTC_BKPxR) are not reset by system reset or when the device
wakes up from Standby mode.
The backup registers are reset when a tamper detection event occurs (see Section 22.7.20:
RTC backup registers (RTC_BKPxR) and Tamper detection initialization on page 557)
except if the TAMPxNOERASE bit is set, or if TAMPxMF is set in the RTC_TAMPCR
register.

Tamper detection initialization

Each input can be enabled by setting the corresponding TAMPxE bits to 1 in the
RTC_TAMPCR register.
Each RTC_TAMPx tamper detection input is associated with a flag TAMPxF in the RTC_ISR
register.
When TAMPxMF is cleared:
The TAMPxF flag is asserted after the tamper event on the pin, with the latency provided
below:
• 3 ck_apre cycles when TAMPFLT differs from 0x0 (Level detection with filtering)
• 3 ck_apre cycles when TAMPTS=1 (Timestamp on tamper event)
• No latency when TAMPFLT=0x0 (Edge detection) and TAMPTS=0
A new tamper occurring on the same pin during this period and as long as TAMPxF is set
cannot be detected.
When TAMPxMF is set:

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A new tamper occurring on the same pin cannot be detected during the latency described
above and 2.5 ck_rtc additional cycles.
By setting the TAMPIE bit in the RTC_TAMPCR register, an interrupt is generated when a
tamper detection event occurs (when TAMPxF is set). Setting TAMPIE is not allowed when
one or more TAMPxMF is set.
When TAMPIE is cleared, each tamper pin event interrupt can be individually enabled by
setting the corresponding TAMPxIE bit in the RTC_TAMPCR register. Setting TAMPxIE is
not allowed when the corresponding TAMPxMF is set.

Trigger output generation on tamper event

The tamper event detection can be used as trigger input by the low-power timers.
When TAMPxMF bit in cleared in RTC_TAMPCR register, the TAMPxF flag must be cleared
by software in order to allow a new tamper detection on the same pin.
When TAMPxMF bit is set, the TAMPxF flag is masked, and kept cleared in RTC_ISR
register. This configuration allows to trig automatically the low-power timers in Stop mode,
without requiring the system wakeup to perform the TAMPxF clearing. In this case, the
backup registers are not cleared.

Timestamp on tamper event

With TAMPTS set to ‘1’, any tamper event causes a timestamp to occur. In this case, either
the TSF bit or the TSOVF bit are set in RTC_ISR, in the same manner as if a normal
timestamp event occurs. The affected tamper flag register TAMPxF is set at the same time
that TSF or TSOVF is set.

Edge detection on tamper inputs

If the TAMPFLT bits are “00”, the RTC_TAMPx pins generate tamper detection events when
either a rising edge or a falling edge is observed depending on the corresponding
TAMPxTRG bit. The internal pull-up resistors on the RTC_TAMPx inputs are deactivated
when edge detection is selected.
Caution: When using the edge detection, it is recommended to check by software the tamper pin
level just after enabling the tamper detection (by reading the GPIO registers), and before
writing sensitive values in the backup registers, to ensure that an active edge did not occur
before enabling the tamper event detection.
When TAMPFLT="00" and TAMPxTRG = 0 (rising edge detection), a tamper event may be
detected by hardware if the tamper input is already at high level before enabling the tamper
detection.
After a tamper event has been detected and cleared, the RTC_TAMPx should be disabled
and then re-enabled (TAMPxE set to 1) before re-programming the backup registers
(RTC_BKPxR). This prevents the application from writing to the backup registers while the
RTC_TAMPx input value still indicates a tamper detection. This is equivalent to a level
detection on the RTC_TAMPx input.

Level detection with filtering on RTC_TAMPx inputs

Level detection with filtering is performed by setting TAMPFLT to a non-zero value. A tamper
detection event is generated when either 2, 4, or 8 (depending on TAMPFLT) consecutive
samples are observed at the level designated by the TAMPxTRG bits.

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The RTC_TAMPx inputs are precharged through the I/O internal pull-up resistance before
its state is sampled, unless disabled by setting TAMPPUDIS to 1,The duration of the
precharge is determined by the TAMPPRCH bits, allowing for larger capacitances on the
RTC_TAMPx inputs.
The trade-off between tamper detection latency and power consumption through the pull-up
can be optimized by using TAMPFREQ to determine the frequency of the sampling for level
detection.
Note: Refer to the datasheets for the electrical characteristics of the pull-up resistors.
For code example, refer to A.13.6: RTC tamper and time stamp configuration code example.

22.4.15 Calibration clock output

When the COE bit is set to 1 in the RTC_CR register, a reference clock is provided on the
RTC_CALIB device output.
If the COSEL bit in the RTC_CR register is reset and PREDIV_A = 0x7F, the RTC_CALIB
frequency is fRTCCLK/64. This corresponds to a calibration output at 512 Hz for an RTCCLK
frequency at 32.768 kHz. The RTC_CALIB duty cycle is irregular: there is a light jitter on
falling edges. It is therefore recommended to use rising edges.
When COSEL is set and “PREDIV_S+1” is a non-zero multiple of 256 (i.e: PREDIV_S[7:0] =
0xFF), the RTC_CALIB frequency is fRTCCLK/(256 * (PREDIV_A+1)). This corresponds to a
calibration output at 1 Hz for prescaler default values (PREDIV_A = Ox7F, PREDIV_S =
0xFF), with an RTCCLK frequency at 32.768 kHz. The 1 Hz output is affected when a shift
operation is on going and may toggle during the shift operation (SHPF=1).
Note: When COSEL bit is cleared, the RTC_CALIB output is the output of the 6th stage of the
asynchronous prescaler.
When COSEL bit is set, the RTC_CALIB output is the output of the 8th stage of the
synchronous prescaler.
For code example, refer to A.13.7: RTC tamper and time stamp code example.

22.4.16 Alarm output

The OSEL[1:0] control bits in the RTC_CR register are used to activate the alarm output
RTC_ALARM, and to select the function which is output. These functions reflect the
contents of the corresponding flags in the RTC_ISR register.
The polarity of the output is determined by the POL control bit in RTC_CR so that the
opposite of the selected flag bit is output when POL is set to 1.

Alarm output
The RTC_ALARM pin can be configured in output open drain or output push-pull using the
control bit RTC_ALARM_TYPE in the RTC_OR register.
Note: Once the RTC_ALARM output is enabled, it has priority over RTC_CALIB (COE bit is don't
care and must be kept cleared).

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22.5 RTC low-power modes

Table 97. Effect of low-power modes on RTC
Mode Description

No effect
Sleep
RTC interrupts cause the device to exit the Sleep mode.
The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC
Stop tamper event, RTC timestamp event, and RTC Wakeup cause the device to exit the Stop
mode.
The RTC remains active when the RTC clock source is LSE or LSI. RTC alarm, RTC
Standby tamper event, RTC timestamp event, and RTC Wakeup cause the device to exit the
Standby mode.

22.6 RTC interrupts

All RTC interrupts are connected to the EXTI controller. Refer to Section 12.5: EXTI
registers.
To enable RTC interrupt(s), the following sequence is required:
1. Configure and enable the NVIC line(s) corresponding to the RTC event(s) in interrupt
mode and select the rising edge sensitivity.
2. Configure and enable the RTC IRQ channel in the NVIC.
3. Configure the RTC to generate RTC interrupt(s).

Table 98. Interrupt control bits

Enable Exit from Exit from Exit from
Interrupt event Event flag control Sleep Stop Standby
bit mode mode mode

Alarm A ALRAF ALRAIE Yes Yes(1) Yes(1)

Alarm B ALRBF ALRBIE Yes Yes(1) Yes(1)
RTC_TS input (timestamp) TSF TSIE Yes Yes(1) Yes(1)
RTC_TAMP1 input detection TAMP1F TAMPIE Yes Yes(1) Yes(1)
RTC_TAMP2 input detection TAMP2F TAMPIE Yes Yes(1) Yes(1)
Wakeup timer interrupt WUTF WUTIE Yes Yes(1) Yes(1)
1. Wakeup from STOP and Standby modes is possible only when the RTC clock source is LSE or LSI.

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22.7 RTC registers

Refer to Section 1.2 on page 45 of the reference manual for a list of abbreviations used in
register descriptions.
The peripheral registers can be accessed by words (32-bit).

22.7.1 RTC time register (RTC_TR)

The RTC_TR is the calendar time shadow register. This register must be written in
initialization mode only. Refer to Calendar initialization and configuration on page 550 and
Reading the calendar on page 551.
This register is write protected. The write access procedure is described in RTC register
write protection on page 550.
Address offset: 0x00
RTC domain reset value: 0x0000 0000
System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. PM HT[1:0] HU[3:0]

rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. MNT[2:0] MNU[3:0] Res. ST[2:0] SU[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format
Bits 19:16 HU[3:0]: Hour units in BCD format
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 MNT[2:0]: Minute tens in BCD format
Bits 11:8 MNU[3:0]: Minute units in BCD format
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 ST[2:0]: Second tens in BCD format
Bits 3:0 SU[3:0]: Second units in BCD format

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22.7.2 RTC date register (RTC_DR)

The RTC_DR is the calendar date shadow register. This register must be written in
initialization mode only. Refer to Calendar initialization and configuration on page 550 and
Reading the calendar on page 551.
This register is write protected. The write access procedure is described in RTC register
write protection on page 550.
Address offset: 0x04
RTC domain reset value: 0x0000 2101
System reset: 0x0000 2101 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. YT[3:0] YU[3:0]

rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU[2:0] MT MU[3:0] Res. Res. DT[1:0] DU[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:20 YT[3:0]: Year tens in BCD format
Bits 19:16 YU[3:0]: Year units in BCD format
Bits 15:13 WDU[2:0]: Week day units
000: forbidden
001: Monday
...
111: Sunday
Bit 12 MT: Month tens in BCD format
Bits 11:8 MU[3:0]: Month units in BCD format
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 DT[1:0]: Date tens in BCD format
Bits 3:0 DU[3:0]: Date units in BCD format

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22.7.3 RTC control register (RTC_CR)

Address offset: 0x08
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. COE OSEL[1:0] POL COSEL BKP SUB1H ADD1H
rw rw rw rw rw rw w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYPS
TSIE WUTIE ALRBIE ALRAIE TSE WUTE ALRBE ALRAE Res. FMT REFCKON TSEDGE WUCKSEL[2:0]
HAD
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 COE: Calibration output enable
This bit enables the RTC_CALIB output
0: Calibration output disabled
1: Calibration output enabled
Bits 22:21 OSEL[1:0]: Output selection
These bits are used to select the flag to be routed to RTC_ALARM output
00: Output disabled
01: Alarm A output enabled
10: Alarm B output enabled
11: Wakeup output enabled
Bit 20 POL: Output polarity
This bit is used to configure the polarity of RTC_ALARM output
0: The pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0])
1: The pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL[1:0]).
Bit 19 COSEL: Calibration output selection
When COE=1, this bit selects which signal is output on RTC_CALIB.
0: Calibration output is 512 Hz (with default prescaler setting)
1: Calibration output is 1 Hz (with default prescaler setting)
These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values
(PREDIV_A=127 and PREDIV_S=255). Refer to Section 22.4.15: Calibration clock output
Bit 18 BKP: Backup
This bit can be written by the user to memorize whether the daylight saving time change has
been performed or not.
Bit 17 SUB1H: Subtract 1 hour (winter time change)
When this bit is set, 1 hour is subtracted to the calendar time if the current hour is not 0. This
bit is always read as 0.
Setting this bit has no effect when current hour is 0.
0: No effect
1: Subtracts 1 hour to the current time. This can be used for winter time change outside
initialization mode.

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Bit 16 ADD1H: Add 1 hour (summer time change)

When this bit is set, 1 hour is added to the calendar time. This bit is always read as 0.
0: No effect
1: Adds 1 hour to the current time. This can be used for summer time change outside
initialization mode.
Bit 15 TSIE: Time-stamp interrupt enable
0: Time-stamp Interrupt disable
1: Time-stamp Interrupt enable
Bit 14 WUTIE: Wakeup timer interrupt enable
0: Wakeup timer interrupt disabled
1: Wakeup timer interrupt enabled
Bit 13 ALRBIE: Alarm B interrupt enable
0: Alarm B Interrupt disable
1: Alarm B Interrupt enable
Bit 12 ALRAIE: Alarm A interrupt enable
0: Alarm A interrupt disabled
1: Alarm A interrupt enabled
Bit 11 TSE: timestamp enable
0: timestamp disable
1: timestamp enable
Bit 10 WUTE: Wakeup timer enable
0: Wakeup timer disabled
1: Wakeup timer enabled
Note: When the wakeup timer is disabled, wait for WUTWF=1 before enabling it again.
Bit 9 ALRBE: Alarm B enable
0: Alarm B disabled
1: Alarm B enabled
Bit 8 ALRAE: Alarm A enable
0: Alarm A disabled
1: Alarm A enabled
Bit 7 Reserved, must be kept at reset value.
Bit 6 FMT: Hour format
0: 24 hour/day format
1: AM/PM hour format
Bit 5 BYPSHAD: Bypass the shadow registers
0: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken from
the shadow registers, which are updated once every two RTCCLK cycles.
1: Calendar values (when reading from RTC_SSR, RTC_TR, and RTC_DR) are taken
directly from the calendar counters.
Note: If the frequency of the APB1 clock is less than seven times the frequency of RTCCLK,
BYPSHAD must be set to ‘1’.

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Bit 4 REFCKON: RTC_REFIN reference clock detection enable (50 or 60 Hz)

0: RTC_REFIN detection disabled
1: RTC_REFIN detection enabled
Note: PREDIV_S must be 0x00FF.
Bit 3 TSEDGE: Time-stamp event active edge
0: RTC_TS input rising edge generates a time-stamp event
1: RTC_TS input falling edge generates a time-stamp event
TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting.
Bits 2:0 WUCKSEL[2:0]: Wakeup clock selection
000: RTC/16 clock is selected
001: RTC/8 clock is selected
010: RTC/4 clock is selected
011: RTC/2 clock is selected
10x: ck_spre (usually 1 Hz) clock is selected
11x: ck_spre (usually 1 Hz) clock is selected and 216 is added to the WUT counter value
(see note below)

Note: Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1).
WUT = Wakeup unit counter value. WUT = (0x0000 to 0xFFFF) + 0x10000 added when
WUCKSEL[2:1 = 11].
Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR
WUTWF bit = 1.
It is recommended not to change the hour during the calendar hour increment as it could
mask the incrementation of the calendar hour.
ADD1H and SUB1H changes are effective in the next second.
This register is write protected. The write access procedure is described in RTC register
write protection on page 550.
Caution: TSE must be reset when TSEDGE is changed to avoid spuriously setting of TSF.

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22.7.4 RTC initialization and status register (RTC_ISR)

This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure
is described in RTC register write protection on page 550.
Address offset: 0x0C
RTC domain reset value: 0x0000 0007
System reset: not affected except INIT, INITF, and RSF bits which are cleared to ‘0’

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RECALPF
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALRB
TAMP3F TAMP2F TAMP1F TSOVF TSF WUTF ALRBF ALRAF INIT INITF RSF INITS SHPF WUTWF ALRAWF
WF
rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rw r rc_w0 r r r r r

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 RECALPF: Recalibration pending Flag
The RECALPF status flag is automatically set to ‘1’ when software writes to the RTC_CALR
register, indicating that the RTC_CALR register is blocked. When the new calibration settings
are taken into account, this bit returns to ‘0’. Refer to Re-calibration on-the-fly.
Bit 15 TAMP3F: RTC_TAMP3 detection flag
This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP3
input.
It is cleared by software writing 0
Bit 14 TAMP2F: RTC_TAMP2 detection flag
This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP2
input.
It is cleared by software writing 0
Bit 13 TAMP1F: RTC_TAMP1 detection flag
This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1
input.
It is cleared by software writing 0
Bit 12 TSOVF: Time-stamp overflow flag
This flag is set by hardware when a time-stamp event occurs while TSF is already set.
This flag is cleared by software by writing 0. It is recommended to check and then clear
TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a time-
stamp event occurs immediately before the TSF bit is cleared.
Bit 11 TSF: Time-stamp flag
This flag is set by hardware when a time-stamp event occurs.
This flag is cleared by software by writing 0.
Bit 10 WUTF: Wakeup timer flag
This flag is set by hardware when the wakeup auto-reload counter reaches 0.
This flag is cleared by software by writing 0.
This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1
again.

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Bit 9 ALRBF: Alarm B flag

This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the
Alarm B register (RTC_ALRMBR).
This flag is cleared by software by writing 0.
Bit 8 ALRAF: Alarm A flag
This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the
Alarm A register (RTC_ALRMAR).
This flag is cleared by software by writing 0.
Bit 7 INIT: Initialization mode
0: Free running mode
1: Initialization mode used to program time and date register (RTC_TR and RTC_DR), and
prescaler register (RTC_PRER). Counters are stopped and start counting from the new
value when INIT is reset.
Bit 6 INITF: Initialization flag
When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler
registers can be updated.
0: Calendar registers update is not allowed
1: Calendar registers update is allowed
Bit 5 RSF: Registers synchronization flag
This bit is set by hardware each time the calendar registers are copied into the shadow
registers (RTC_SSR, RTC_TR and RTC_DR). This bit is cleared by hardware in initialization
mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode
(BYPSHAD=1). This bit can also be cleared by software.
It is cleared either by software or by hardware in initialization mode.
0: Calendar shadow registers not yet synchronized
1: Calendar shadow registers synchronized
Bit 4 INITS: Initialization status flag
This bit is set by hardware when the calendar year field is different from 0 (RTC domain reset
state).
0: Calendar has not been initialized
1: Calendar has been initialized
Bit 3 SHPF: Shift operation pending
0: No shift operation is pending
1: A shift operation is pending
This flag is set by hardware as soon as a shift operation is initiated by a write to the
RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has
been executed. Writing to the SHPF bit has no effect.

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Bit 2 WUTWF: Wakeup timer write flag

This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in
RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The
wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set.
0: Wakeup timer configuration update not allowed
1: Wakeup timer configuration update allowed
Bit 1 ALRBWF: Alarm B write flag
This bit is set by hardware when Alarm B values can be changed, after the ALRBE bit has
been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.
0: Alarm B update not allowed
1: Alarm B update allowed
Bit 0 ALRAWF: Alarm A write flag
This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has
been set to 0 in RTC_CR.
It is cleared by hardware in initialization mode.
0: Alarm A update not allowed
1: Alarm A update allowed

Note: The bits ALRAF, ALRBF, WUTF and TSF are cleared 2 APB clock cycles after programming
them to 0.

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22.7.5 RTC prescaler register (RTC_PRER)

This register must be written in initialization mode only. The initialization must be performed
in two separate write accesses. Refer to Calendar initialization and configuration on
page 550.
This register is write protected. The write access procedure is described in RTC register
write protection on page 550.
Address offset: 0x10
RTC domain reset value: 0x007F 00FF
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. PREDIV_A[6:0]

rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. PREDIV_S[14:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 PREDIV_A[6:0]: Asynchronous prescaler factor
This is the asynchronous division factor:
ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)
Bit 15 Reserved, must be kept at reset value.
Bits 14:0 PREDIV_S[14:0]: Synchronous prescaler factor
This is the synchronous division factor:
ck_spre frequency = ck_apre frequency/(PREDIV_S+1)

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22.7.6 RTC wakeup timer register (RTC_WUTR)

This register can be written only when WUTWF is set to 1 in RTC_ISR.
This register is write protected. The write access procedure is described in RTC register
write protection on page 550.
Address offset: 0x14
RTC domain reset value: 0x0000 FFFF
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WUT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 WUT[15:0]: Wakeup auto-reload value bits
When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0]
+ 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the
RTC_CR register
When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively
becomes WUT[16] the most-significant bit to be reloaded into the timer.
The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting
WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden.

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RM0377 Real-time clock (RTC)

22.7.7 RTC alarm A register (RTC_ALRMAR)

This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization
mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 550.
Address offset: 0x1C
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4 WDSEL DT[1:0] DU[3:0] MSK3 PM HT[1:0] HU[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2 MNT[2:0] MNU[3:0] MSK1 ST[2:0] SU[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 MSK4: Alarm A date mask

0: Alarm A set if the date/day match
1: Date/day don’t care in Alarm A comparison
Bit 30 WDSEL: Week day selection
0: DU[3:0] represents the date units
1: DU[3:0] represents the week day. DT[1:0] is don’t care.
Bits 29:28 DT[1:0]: Date tens in BCD format.
Bits 27:24 DU[3:0]: Date units or day in BCD format.
Bit 23 MSK3: Alarm A hours mask
0: Alarm A set if the hours match
1: Hours don’t care in Alarm A comparison
Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format.
Bits 19:16 HU[3:0]: Hour units in BCD format.
Bit 15 MSK2: Alarm A minutes mask
0: Alarm A set if the minutes match
1: Minutes don’t care in Alarm A comparison
Bits 14:12 MNT[2:0]: Minute tens in BCD format.
Bits 11:8 MNU[3:0]: Minute units in BCD format.
Bit 7 MSK1: Alarm A seconds mask
0: Alarm A set if the seconds match
1: Seconds don’t care in Alarm A comparison
Bits 6:4 ST[2:0]: Second tens in BCD format.
Bits 3:0 SU[3:0]: Second units in BCD format.

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22.7.8 RTC alarm B register (RTC_ALRMBR)

This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization
mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 550.
Address offset: 0x20
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSK4 WDSEL DT[1:0] DU[3:0] MSK3 PM HT[1:0] HU[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSK2 MNT[2:0] MNU[3:0] MSK1 ST[2:0] SU[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 MSK4: Alarm B date mask

0: Alarm B set if the date and day match
1: Date and day don’t care in Alarm B comparison
Bit 30 WDSEL: Week day selection
0: DU[3:0] represents the date units
1: DU[3:0] represents the week day. DT[1:0] is don’t care.
Bits 29:28 DT[1:0]: Date tens in BCD format
Bits 27:24 DU[3:0]: Date units or day in BCD format
Bit 23 MSK3: Alarm B hours mask
0: Alarm B set if the hours match
1: Hours don’t care in Alarm B comparison
Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format
Bits 19:16 HU[3:0]: Hour units in BCD format
Bit 15 MSK2: Alarm B minutes mask
0: Alarm B set if the minutes match
1: Minutes don’t care in Alarm B comparison
Bits 14:12 MNT[2:0]: Minute tens in BCD format
Bits 11:8 MNU[3:0]: Minute units in BCD format
Bit 7 MSK1: Alarm B seconds mask
0: Alarm B set if the seconds match
1: Seconds don’t care in Alarm B comparison
Bits 6:4 ST[2:0]: Second tens in BCD format
Bits 3:0 SU[3:0]: Second units in BCD format

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RM0377 Real-time clock (RTC)

22.7.9 RTC write protection register (RTC_WPR)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. KEY[7:0]

w w w w w w w w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 KEY[7:0]: Write protection key
This byte is written by software.
Reading this byte always returns 0x00.
Refer to RTC register write protection for a description of how to unlock RTC register write
protection.

22.7.10 RTC sub second register (RTC_SSR)

Address offset: 0x28
RTC domain reset value: 0x0000 0000
System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS[15:0]
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SS[15:0]: Sub second value
SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by
the formula below:
Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1)
Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct
time/date is one second less than as indicated by RTC_TR/RTC_DR.

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22.7.11 RTC shift control register (RTC_SHIFTR)

This register is write protected. The write access procedure is described in RTC register
write protection on page 550.
Address offset: 0x2C
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADD1S Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. SUBFS[14:0]

w w w w w w w w w w w w w w w

Bit 31 ADD1S: Add one second

0: No effect
1: Add one second to the clock/calendar
This bit is write only and is always read as zero. Writing to this bit has no effect when a shift
operation is pending (when SHPF=1, in RTC_ISR).
This function is intended to be used with SUBFS (see description below) in order to effectively
add a fraction of a second to the clock in an atomic operation.
Bits 30:15 Reserved, must be kept at reset value.
Bits 14:0 SUBFS[14:0]: Subtract a fraction of a second
These bits are write only and is always read as zero. Writing to this bit has no effect when a
shift operation is pending (when SHPF=1, in RTC_ISR).
The value which is written to SUBFS is added to the synchronous prescaler counter. Since this
counter counts down, this operation effectively subtracts from (delays) the clock by:
Delay (seconds) = SUBFS / (PREDIV_S + 1)
A fraction of a second can effectively be added to the clock (advancing the clock) when the
ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by:
Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))).
Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be
sure that the shadow registers have been updated with the shifted time.

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RM0377 Real-time clock (RTC)

22.7.12 RTC timestamp time register (RTC_TSTR)

The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when
TSF bit is reset.
Address offset: 0x30
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. PM HT[1:0] HU[3:0]

r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. MNT[2:0] MNU[3:0] Res. ST[2:0] SU[3:0]

r r r r r r r r r r r r r r

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 PM: AM/PM notation
0: AM or 24-hour format
1: PM
Bits 21:20 HT[1:0]: Hour tens in BCD format.
Bits 19:16 HU[3:0]: Hour units in BCD format.
Bit 15 Reserved, must be kept at reset value.
Bits 14:12 MNT[2:0]: Minute tens in BCD format.
Bits 11:8 MNU[3:0]: Minute units in BCD format.
Bit 7 Reserved, must be kept at reset value.
Bits 6:4 ST[2:0]: Second tens in BCD format.
Bits 3:0 SU[3:0]: Second units in BCD format.

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22.7.13 RTC timestamp date register (RTC_TSDR)

The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when
TSF bit is reset.
Address offset: 0x34
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDU[2:0] MT MU[3:0] Res. Res. DT[1:0] DU[3:0]

r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:13 WDU[2:0]: Week day units
Bit 12 MT: Month tens in BCD format
Bits 11:8 MU[3:0]: Month units in BCD format
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 DT[1:0]: Date tens in BCD format
Bits 3:0 DU[3:0]: Date units in BCD format

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RM0377 Real-time clock (RTC)

22.7.14 RTC time-stamp sub second register (RTC_TSSSR)

The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the
RTC_ISR/TSF bit is reset.
Address offset: 0x38
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS[15:0]
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SS[15:0]: Sub second value
SS[15:0] is the value of the synchronous prescaler counter when the timestamp event
occurred.

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22.7.15 RTC calibration register (RTC_CALR)

This register is write protected. The write access procedure is described in RTC register
write protection on page 550.
Address offset: 0x3C
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALW
CALP CALW8 Res. Res. Res. Res. CALM[8:0]
16
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 CALP: Increase frequency of RTC by 488.5 ppm
0: No RTCCLK pulses are added.
1: One RTCCLK pulse is effectively inserted every 211 pulses (frequency increased by
488.5 ppm).
This feature is intended to be used in conjunction with CALM, which lowers the frequency of
the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK
pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM.
Refer to Section 22.4.12: RTC smooth digital calibration.
Bit 14 CALW8: Use an 8-second calibration cycle period
When CALW8 is set to ‘1’, the 8-second calibration cycle period is selected.
Note: CALM[1:0] are stuck at “00” when CALW8=’1’. Refer to Section 22.4.12: RTC smooth
digital calibration.
Bit 13 CALW16: Use a 16-second calibration cycle period
When CALW16 is set to ‘1’, the 16-second calibration cycle period is selected.This bit must
not be set to ‘1’ if CALW8=1.
Note: CALM[0] is stuck at ‘0’ when CALW16=’1’. Refer to Section 22.4.12: RTC smooth
digital calibration.
Bits 12:9 Reserved, must be kept at reset value.
Bits 8:0 CALM[8:0]: Calibration minus
The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32
seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar
with a resolution of 0.9537 ppm.
To increase the frequency of the calendar, this feature should be used in conjunction with
CALP. See Section 22.4.12: RTC smooth digital calibration on page 554.

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RM0377 Real-time clock (RTC)

22.7.16 RTC tamper configuration register (RTC_TAMPCR)

Address offset: 0x40
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TAMP3 TAMP2 TAMP1
TAMP3 TAMP3 TAMP2 TAMP2 TAMP1 TAMP1
Res. Res. Res. Res. Res. Res. Res. NO NO NO
MF IE MF IE MF IE
ERASE ERASE ERASE

rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAMP TAMPPRCH TAMP TAMP3 TAMP3 TAMP2 TAMP2 TAMPI TAMP1 TAMP1
TAMPFLT[1:0] TAMPFREQ[2:0]
PUDIS [1:0] TS TRG E TRG E E TRG E
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 TAMP3MF: Tamper 3 mask flag
0: Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to
allow next tamper event detection.
1: Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by
hardware. The backup registers are not erased.
Note: The Tamper 3 interrupt must not be enabled when TAMP3MF is set.
Bit 23 TAMP3NOERASE: Tamper 3 no erase
0: Tamper 3 event erases the backup registers.
1: Tamper 3 event does not erase the backup registers.
Bit 22 TAMP3IE: Tamper 3 interrupt enable
0: Tamper 3 interrupt is disabled if TAMPIE = 0.
1: Tamper 3 interrupt enabled.
Bit 21 TAMP2MF: Tamper 2 mask flag
0: Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to
allow next tamper event detection.
1: Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by
hardware. The backup registers are not erased.
Note: The Tamper 2 interrupt must not be enabled when TAMP2MF is set.
Bit 20 TAMP2NOERASE: Tamper 2 no erase
0: Tamper 2 event erases the backup registers.
1: Tamper 2 event does not erase the backup registers.
Bit 19 TAMP2IE: Tamper 2 interrupt enable
0: Tamper 2 interrupt is disabled if TAMPIE = 0.
1: Tamper 2 interrupt enabled.
Bit 18 TAMP1MF: Tamper 1 mask flag
0: Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to
allow next tamper event detection.
1: Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by
hardware.The backup registers are not erased.
Note: The Tamper 1 interrupt must not be enabled when TAMP1MF is set.

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Bit 17 TAMP1NOERASE: Tamper 1 no erase

0: Tamper 1 event erases the backup registers.
1: Tamper 1 event does not erase the backup registers.
Bit 16 TAMP1IE: Tamper 1 interrupt enable
0: Tamper 1 interrupt is disabled if TAMPIE = 0.
1: Tamper 1 interrupt enabled.
Bit 15 TAMPPUDIS: RTC_TAMPx pull-up disable
This bit determines if each of the RTC_TAMPx pins are precharged before each sample.
0: Precharge RTC_TAMPx pins before sampling (enable internal pull-up)
1: Disable precharge of RTC_TAMPx pins.
Bits 14:13 TAMPPRCH[1:0]: RTC_TAMPx precharge duration
These bit determines the duration of time during which the pull-up/is activated before each
sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs.
0x0: 1 RTCCLK cycle
0x1: 2 RTCCLK cycles
0x2: 4 RTCCLK cycles
0x3: 8 RTCCLK cycles
Bits 12:11 TAMPFLT[1:0]: RTC_TAMPx filter count
These bits determines the number of consecutive samples at the specified level (TAMP*TRG)
needed to activate a Tamper event. TAMPFLT is valid for each of the RTC_TAMPx inputs.
0x0: Tamper event is activated on edge of RTC_TAMPx input transitions to the active level
(no internal pull-up on RTC_TAMPx input).
0x1: Tamper event is activated after 2 consecutive samples at the active level.
0x2: Tamper event is activated after 4 consecutive samples at the active level.
0x3: Tamper event is activated after 8 consecutive samples at the active level.
Bits 10:8 TAMPFREQ[2:0]: Tamper sampling frequency
Determines the frequency at which each of the RTC_TAMPx inputs are sampled.
0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)
0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)
0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)
0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)
0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)
0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)
0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)
0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
Bit 7 TAMPTS: Activate timestamp on tamper detection event
0: Tamper detection event does not cause a timestamp to be saved
1: Save timestamp on tamper detection event
TAMPTS is valid even if TSE=0 in the RTC_CR register.
Bit 6 TAMP3TRG: Active level for RTC_TAMP3 input
if TAMPFLT ≠ 00:
0: RTC_TAMP3 input staying low triggers a tamper detection event.
1: RTC_TAMP3 input staying high triggers a tamper detection event.
if TAMPFLT = 00:
0: RTC_TAMP3 input rising edge triggers a tamper detection event.
1: RTC_TAMP3 input falling edge triggers a tamper detection event.

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RM0377 Real-time clock (RTC)

Bit 5 TAMP3E: RTC_TAMP3 detection enable

0: RTC_TAMP3 input detection disabled
1: RTC_TAMP3 input detection enabled
Bit 4 TAMP2TRG: Active level for RTC_TAMP2 input
if TAMPFLT != 00:
0: RTC_TAMP2 input staying low triggers a tamper detection event.
1: RTC_TAMP2 input staying high triggers a tamper detection event.
if TAMPFLT = 00:
0: RTC_TAMP2 input rising edge triggers a tamper detection event.
1: RTC_TAMP2 input falling edge triggers a tamper detection event.
Bit 3 TAMP2E: RTC_TAMP2 input detection enable
0: RTC_TAMP2 detection disabled
1: RTC_TAMP2 detection enabled
Bit 2 TAMPIE: Tamper interrupt enable
0: Tamper interrupt disabled
1: Tamper interrupt enabled.
Note: This bit enables the interrupt for all tamper pins events, whatever TAMPxIE level. If this
bit is cleared, each tamper event interrupt can be individually enabled by setting
TAMPxIE.
Bit 1 TAMP1TRG: Active level for RTC_TAMP1 input
If TAMPFLT != 00
0: RTC_TAMP1 input staying low triggers a tamper detection event.
1: RTC_TAMP1 input staying high triggers a tamper detection event.
if TAMPFLT = 00:
0: RTC_TAMP1 input rising edge triggers a tamper detection event.
1: RTC_TAMP1 input falling edge triggers a tamper detection event.
Bit 0 TAMP1E: RTC_TAMP1 input detection enable
0: RTC_TAMP1 detection disabled
1: RTC_TAMP1 detection enabled

Caution: When TAMPFLT = 0, TAMPxE must be reset when TAMPxTRG is changed to avoid
spuriously setting TAMPxF.

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22.7.17 RTC alarm A sub second register (RTC_ALRMASSR)

This register can be written only when ALRAE is reset in RTC_CR register, or in initialization
mode.
This register is write protected. The write access procedure is described in RTC register
write protection on page 550
Address offset: 0x44
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. MASKSS[3:0] Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. SS[14:0]

rw rw rw rw rw rw rw rw rw rw rw rw w rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit
0: No comparison on sub seconds for Alarm A. The alarm is set when the seconds unit is
incremented (assuming that the rest of the fields match).
1: SS[14:1] are don’t care in Alarm A comparison. Only SS[0] is compared.
2: SS[14:2] are don’t care in Alarm A comparison. Only SS[1:0] are compared.
3: SS[14:3] are don’t care in Alarm A comparison. Only SS[2:0] are compared.
...
12: SS[14:12] are don’t care in Alarm A comparison. SS[11:0] are compared.
13: SS[14:13] are don’t care in Alarm A comparison. SS[12:0] are compared.
14: SS[14] is don’t care in Alarm A comparison. SS[13:0] are compared.
15: All 15 SS bits are compared and must match to activate alarm.
The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be
different from 0 only after a shift operation.
Bits 23:15 Reserved, must be kept at reset value.
Bits 14:0 SS[14:0]: Sub seconds value
This value is compared with the contents of the synchronous prescaler counter to determine if
Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared.

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RM0377 Real-time clock (RTC)

22.7.18 RTC alarm B sub second register (RTC_ALRMBSSR)

This register can be written only when ALRBE is reset in RTC_CR register, or in initialization
mode.
This register is write protected.The write access procedure is described in Section : RTC
register write protection.
Address offset: 0x48
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. MASKSS[3:0] Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. SS[14:0]

rw rw rw rw rw rw rw rw rw rw rw rw w rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 MASKSS[3:0]: Mask the most-significant bits starting at this bit
0x0: No comparison on sub seconds for Alarm B. The alarm is set when the seconds unit is
incremented (assuming that the rest of the fields match).
0x1: SS[14:1] are don’t care in Alarm B comparison. Only SS[0] is compared.
0x2: SS[14:2] are don’t care in Alarm B comparison. Only SS[1:0] are compared.
0x3: SS[14:3] are don’t care in Alarm B comparison. Only SS[2:0] are compared.
...
0xC: SS[14:12] are don’t care in Alarm B comparison. SS[11:0] are compared.
0xD: SS[14:13] are don’t care in Alarm B comparison. SS[12:0] are compared.
0xE: SS[14] is don’t care in Alarm B comparison. SS[13:0] are compared.
0xF: All 15 SS bits are compared and must match to activate alarm.
The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be
different from 0 only after a shift operation.
Bits 23:15 Reserved, must be kept at reset value.
Bits 14:0 SS[14:0]: Sub seconds value
This value is compared with the contents of the synchronous prescaler counter to determine
if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared.

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22.7.19 RTC option register (RTC_OR)

Address offset: 0x4C
RTC domain reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTC_ RTC_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OUT_ ALARM
RMP _TYPE
rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 RTC_OUT_RMP: RTC_OUT remap
Setting this bit allows to remap the RTC outputs on PB14 as follows:
On category 3 and 5 devices:
RTC_OUT_RMP = ‘0’:
If OSEL/= ‘00’: RTC_ALARM is output on PC13
If OSEL= ‘00’ and COE = ‘1’: RTC_CALIB is output on PC13
RTC_OUT_RMP = ‘1’:
If OSEL /= ‘00’ and COE = ‘0’: RTC_ALARM is output on PB14
If OSEL = ‘00’ and COE = ‘1’: RTC_CALIB is output on PB14
If OSEL /= ‘00’ and COE = ‘1’: RTC_CALIB is output on PB14 and RTC_ALARM is output
on PC13.
On category 1 and 2 devices:
RTC_OUT_RMP = ‘0’:
If OSEL/= ‘00’: RTC_ALARM is output on PA2
If OSEL= ‘00’ and COE = '1' : RTC_CALIB is output on PA2
RTC_OUT_RMP = ‘1’:
If OSEL /= ‘00’ and COE = '0' : RTC_ALARM is output on PB14
If OSEL = ‘00’ and COE = '1': RTC_CALIB is output on PB14
If OSEL /= ‘00’ and COE = '1': RTC_CALIB is output on PB14 and RTC_ALARM is output
on PA2.
Note: The RTC outputs are functional in Standby mode only on PA2.

Bit 0 RTC_ALARM_TYPE: RTC_ALARM output type on PC13 (category 3 and 5)/ on PA2
(category 1 and 2)
This bit is set and cleared by software
On category 3 and 5 devices:
0: RTC_ALARM, when mapped on PC13, is open-drain output
1: RTC_ALARM, when mapped on PC13, is push-pull output

On category 1 and 2 devices:

0: RTC_ALARM, when mapped on PA2, is open-drain output
1: RTC_ALARM, when mapped on PA2, is push-pull output

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RM0377 Real-time clock (RTC)

22.7.20 RTC backup registers (RTC_BKPxR)

Address offset: 0x50 to 0x60
RTC domain reset value: 0x0000 0000
System reset: not affected
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BKP[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BKP[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw w rw rw

Bits 31:0 BKP[31:0]

The application can write or read data to and from these registers.

22.7.21 RTC register map

Table 99. RTC register map and reset values

Register
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name
HT[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
PM

RTC_TR HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0]

0x00

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DT[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
MT

RTC_DR YT[3:0] YU[3:0] WDU[2:0] MU[3:0] DU[3:0]

0x04

Reset value 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1

WUCKSEL[2:0]
REFCKON
BYPSHAD
OSEL[1:0]

TSEDGE
ALRBIE
ALRAIE
COSEL

ADD1H
SUB1H

ALRBE
ALRAE
WUTIE

WUTE
TSIE
COE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
FMT
POL

BKP

TSE

RTC_CR
0x08

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RECALPF

ALRBWF
.TAMP2F

ALRAWF
WUT WF
TAMP3F

TAMP1F
TSOVF

ALRBF
ALRAF
WUTF

SHPF
INITS
INITF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

RSF
TSF

INIT

RTC_ISR
0x0C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

RTC_PRER PREDIV_A[6:0] PREDIV_S[14:0]

0x10
Reset value 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

RTC_WUTR WUT[15:0]
0x14
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
WDSEL

DT[1:0]

HT[1:0]
MSK4

MSK3

MSK2

MSK1
PM

RTC_ALRMAR DU[3:0] HU[3:0] MNT[2:0] MNU[3:0] ST[2:0] SU[3:0]

0x1C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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 0x48
0x44
0x40
0x38
0x34
0x30
0x28
0x24
0x20

0x3C
0x2C
Offset

586/905
RTC_
RTC_
name

RTC_SSR
RTC_WPR
Register

RTC_TSTR
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

RTC_TSDR

RTC_ CALR

ALRMBSSR
ALRMASSR
RTC_TSSSR
RTC_SHIFTR

RTC_TAMPCR
RTC_ALRMBR

0
0
Res. Res. Res. Res. Res. Res. Res. ADD1S Res. Res. MSK4 31
Real-time clock (RTC)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 WDSEL
0
30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
DT[1:0]
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 26

[3:0]
[3:0]

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 25

DU[3:0]

MASKSS
MASKSS

0
0
0
0

TAMP3MF Res. Res. Res. Res. Res. Res. Res. 24

0
0

Res. Res. TAMP3NOERASE Res. Res. Res. Res. Res. Res. Res. MSK3 23

0
0
0

Res. Res. TAMP3IE Res. Res. Res. PM Res. Res. Res. PM 22

0
0
0

Res. Res. TAMP2MF Res. Res. Res. Res. Res. Res. 21

HT[1:0] HT[1:0]

0
0
0

Res. Res. TAMP2NOERASE Res. Res. Res. Res. Res. Res. 20

0
0
0

Res. Res. TAMP2IE Res. Res. Res. Res. Res. Res. 19

0
0
0

Res. Res. TAMP1MF Res. Res. Res. Res. Res. Res. 18

0
0
0

Res. Res. TAMP1NOERASE Res. Res. Res. Res. Res. Res. 17

HU[3:0]
HU[3:0]

RM0377 Rev 10
0
0
0

Res. Res. TAMP1IE Res. Res. Res. Res. Res. Res. 16

0
0

0
0
0
0

Res. Res. TAMPPUDIS CALP Res. Res. Res. MSK2 15

0
0
0

0
0
0
0
0
0
0

CALW8 Res. 14
TAMPPRCH[1:0]
0

0
0
0
0
0
0
0
0
0

WDU[1:0]
CALW16 MNT[2:0] Res. 13
0

0
0
0
0
0
0
0
0
MNT[2:0]

Res. MT Res. 12
TAMPFLT[1:0]
0

0
0
0
0
0
0
0
0

Res. Res. 11
0

0
0
0
0
0
0
0
0

Res. Res. 10
0

0
0
0
0
0
0
0
0

TAMPFREQ[2:0] Res. Res. 9

MU[3:0]
MNU[3:0]
MNU[3:0]
Table 99. RTC register map and reset values (continued)

0
0
0
0
0
0
0
0
0

Res. 8

0
0

0
0
0
0
0
0
0

TAMPTS Res. Res. MSK2 7

SS[15:0]
SS[15:0]

SS[14:0]
SS[14:0]
0

0
0
0
0
0
0
0
0
0

TAMP3TRG Res. 6
SUBFS[14:0]

0
0
0
0
0
0
0
0

0
0
0

TAMP3E 5
DT[1:0]
ST[2:0]
ST[2:0]

0
0
0
0
0
0
0
0

0
0
0

TAMP2TRG 4
KEY

0
0
0
0
0
0
0
0

0
0
0

.TAMP2E
CALM[8:0]

3
0

0
0
0
0
0
0
0
0
0
0

.TAMPIE 2
0

0
0
0
0
0
0
0
0
0
0

TAMP1TRG 1
SU[3:0]
SU[3:0]

DU[3:0]
0

0
0
0
0
0
0
0
0
0
0

TAMP1E
RM0377

0
RM0377 Real-time clock (RTC)

Table 99. RTC register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

RTC_ALARM_TYPE
RTC_OUT_RMP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RTC_ OR
0x4C

Reset value 0 0

RTC_BKP0R BKP[31:0]

0x50 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

to 0x60
to
BKP[31:0]
RTC_BKP4R

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 51 for the register boundary addresses.

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23 Inter-integrated circuit (I2C) interface

23.1 Introduction
The I2C (inter-integrated circuit) bus interface handles communications between the
microcontroller and the serial I2C bus. It provides multimaster capability, and controls all I2C
bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm),
Fast-mode (Fm) and Fast-mode Plus (Fm+).
It is also SMBus (system management bus) and PMBus (power management bus)
compatible.
DMA can be used to reduce CPU overload.

23.2 I2C main features

• I2C bus specification rev03 compatibility:
– Slave and master modes
– Multimaster capability
– Standard-mode (up to 100 kHz)
– Fast-mode (up to 400 kHz)
– Fast-mode Plus (up to 1 MHz)
– 7-bit and 10-bit addressing mode
– Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
– All 7-bit addresses acknowledge mode
– General call
– Programmable setup and hold times
– Easy to use event management
– Optional clock stretching
– Software reset
• 1-byte buffer with DMA capability
• Programmable analog and digital noise filters

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The following additional features are also available depending on the product
implementation (see Section 23.3: I2C implementation):
• SMBus specification rev 3.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
– Command and data acknowledge control
– Address resolution protocol (ARP) support
– Host and Device support
– SMBus alert
– Timeouts and idle condition detection
• PMBus rev 1.3 standard compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming
• Wakeup from Stop mode on address match.

23.3 I2C implementation

This manual describes the full set of features implemented in I2C1, I2C3. I2C2 supports a
smaller set of features, but is otherwise identical to I2C1/I2C3. The differences are listed
below.

Table 100. STM32L0x1 I2C features

I2C features(1) I2C1 I2C2 I2C3

7-bit addressing mode X X X

10-bit addressing mode X X X
Standard-mode (up to 100 kbit/s) X X X
Fast-mode (up to 400 kbit/s) X X X
Fast-mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)(2) X X X
Independent clock X - X
Wakeup from Stop mode X - X
SMBus/PMBus X - X
1. X = supported.
2. Refer to the datasheet for the list of I/Os that support this feature.

23.4 I2C functional description

In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa. The interrupts are enabled or disabled by software. The interface is
connected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected
with a standard (up to 100 kHz), Fast-mode (up to 400 kHz) or Fast-mode Plus (up to
1 MHz) I2C bus.
This interface can also be connected to a SMBus with the data pin (SDA) and clock pin
(SCL).

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If SMBus feature is supported: the additional optional SMBus Alert pin (SMBA) is also
available.

23.4.1 I2C1/3 block diagram

The block diagram of the I2C1 interface is shown in Figure 182.

Figure 182. I2C1/3 block diagram

I2CCLK
i2c_ker_ck

Data control
Digital Analog
Shift register noise noise GPIO
filter I2C_SDA
filter logic
SMBUS
PEC
generation/
check
Wakeup
on
address
match Clock control
Master clock
generation Digital Analog
noise noise
Slave clock GPIO I2C_SCL
filter filter
stretching logic

SMBus
Timeout
check

SMBus Alert
control/status I2C_SMBA

PCLK
i2c_pclk Registers

APB bus

MSv46198V2

The I2C1/3 is clocked by an independent clock source which allows the I2C to operate
independently from the PCLK frequency.
For I2C I/Os supporting 20mA output current drive for Fast-mode Plus operation, the driving
capability is enabled through control bits in the system configuration controller (SYSCFG).
Refer to Section 23.3: I2C implementation.

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23.4.2 I2C2 block diagram

The block diagram of the I2C2 interface is shown in Figure 183.

Figure 183. I2C2 block diagram

I2CCLK
PCLK

Data control
Digital Analog
Shift register noise noise GPIO
filter I2C1_SDA
filter logic
SMBUS
PEC
generation/
check
Wakeup
on
address
match Clock control
Master clock
generation Digital Analog
noise noise
Slave clock GPIO I2C1_SCL
filter filter
stretching logic

SMBus
Timeout
check

SMBus Alert
control/status I2C1_SMBA

Registers

APB bus

MSv46199V2

For I2C I/Os supporting 20 mA output current drive for Fast-mode Plus operation, the driving
capability is enabled through control bits in the system configuration controller (SYSCFG).
Refer to Section 23.3: I2C implementation.

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23.4.3 I2C pins and internal signals

Table 101. I2C input/output pins
Pin name Signal type Description

I2C_SDA Bidirectional I2C data

I2C_SCL Bidirectional I2C clock
I2C_SMBA Bidirectional SMBus alert

Table 102. I2C internal input/output signals

Internal signal name Signal type Description

I2C kernel clock, also named I2CCLK in this

i2c_ker_ck Input
document
i2c_pclk Input I2C APB clock
I2C interrupts, refer to Table 115: I2C Interrupt
i2c_it Output
requests for the full list of interrupt sources
i2c_rx_dma Output I2C receive data DMA request (I2C_RX)
i2c_tx_dma Output I2C transmit data DMA request (I2C_TX)

23.4.4 I2C clock requirements

The I2C kernel is clocked by I2CCLK.
The I2CCLK period tI2CCLK must respect the following conditions:
tI2CCLK < (tLOW - tfilters) / 4 and tI2CCLK < tHIGH
with:
tLOW: SCL low time and tHIGH: SCL high time
tfilters: when enabled, sum of the delays brought by the analog filter and by the digital filter.
Analog filter delay is maximum 260 ns. Digital filter delay is DNF x tI2CCLK.
The PCLK clock period tPCLK must respect the following condition:
tPCLK < 4/3 tSCL
with tSCL: SCL period
Caution: When the I2C kernel is clocked by PCLK, this clock must respect the conditions for tI2CCLK.

23.4.5 Mode selection

The interface can operate in one of the four following modes:
• Slave transmitter
• Slave receiver
• Master transmitter
• Master receiver

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By default, it operates in slave mode. The interface automatically switches from slave to
master when it generates a START condition, and from master to slave if an arbitration loss
or a STOP generation occurs, allowing multimaster capability.

Communication flow
In Master mode, the I2C interface initiates a data transfer and generates the clock signal. A
serial data transfer always begins with a START condition and ends with a STOP condition.
Both START and STOP conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and
the general call address. The general call address detection can be enabled or disabled by
software. The reserved SMBus addresses can also be enabled by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
START condition contain the address (one in 7-bit mode, two in 10-bit mode). The address
is always transmitted in Master mode.
A ninth clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver
must send an acknowledge bit to the transmitter. Refer to the following figure.

Figure 184. I2C bus protocol

SDA
MSB ACK

SCL
1 2 8 9

Start Stop
condition condition

MS19854V1

Acknowledge can be enabled or disabled by software. The I2C interface addresses can be
selected by software.

23.4.6 I2C initialization

Enabling and disabling the peripheral
The I2C peripheral clock must be configured and enabled in the clock controller.
Then the I2C can be enabled by setting the PE bit in the I2C_CR1 register.
When the I2C is disabled (PE = 0), the I2C performs a software reset. Refer to
Section 23.4.7: Software reset for more details.

Noise filters
Before enabling the I2C peripheral by setting the PE bit in I2C_CR1 register, the user must
configure the noise filters, if needed. By default, an analog noise filter is present on the SDA
and SCL inputs. This analog filter is compliant with the I2C specification which requires the

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suppression of spikes with a pulse width up to 50 ns in Fast-mode and Fast-mode Plus. The
user can disable this analog filter by setting the ANFOFF bit, and/or select a digital filter by
configuring the DNF[3:0] bit in the I2C_CR1 register.
When the digital filter is enabled, the level of the SCL or the SDA line is internally changed
only if it remains stable for more than DNF x I2CCLK periods. This allows spikes with a
programmable length of 1 to 15 I2CCLK periods to be suppressed.

Table 103. Comparison of analog vs. digital filters

- Analog filter Digital filter

Pulse width of Programmable length from 1 to 15 I2C peripheral

≥ 50 ns
suppressed spikes clocks
– Programmable length: extra filtering capability
Benefits Available in Stop mode versus standard requirements
– Stable length
Variation vs. temperature, Wakeup from Stop mode on address match is not
Drawbacks
voltage, process available when digital filter is enabled

Caution: Changing the filter configuration is not allowed when the I2C is enabled.

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I2C timings
The timings must be configured in order to guarantee a correct data hold and setup time,
used in master and slave modes. This is done by programming the PRESC[3:0],
SCLDEL[3:0] and SDADEL[3:0] bits in the I2C_TIMINGR register.
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
configuration window

Figure 185. Setup and hold timings

DATA HOLD TIME
SCL falling edge internal
detection

tSYNC1 SDADEL: SCL stretched low by the I2C

SDA output delay

SCL

SDA

tHD;DAT
Data hold time: in case of transmission, the data is sent on SDA output after
the SDADEL delay, if it is already available in I2C_TXDR.

DATA SETUP TIME

SCLDEL
SCL stretched low by the I2C

SCL

SDA

tSU;DAT
SU;STA
Data setup time: in case of transmission, the SCLDEL counter starts
when the data is sent on SDA output. MSv40108V1
MS49608V1

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• When the SCL falling edge is internally detected, a delay is inserted before sending
SDA output. This delay is tSDADEL = SDADEL x tPRESC + tI2CCLK where tPRESC = (PRESC+1)
x tI2CCLK.
TSDADEL impacts the hold time tHD;DAT.

The total SDA output delay is:

tSYNC1 + {[SDADEL x (PRESC+1) + 1] x tI2CCLK }
tSYNC1 duration depends on these parameters:
– SCL falling slope
– When enabled, input delay brought by the analog filter: tAF(min) < tAF < tAF(max)
– When enabled, input delay brought by the digital filter: tDNF = DNF x tI2CCLK
– Delay due to SCL synchronization to I2CCLK clock (2 to 3 I2CCLK periods)
In order to bridge the undefined region of the SCL falling edge, the user must program
SDADEL in such a way that:
{tf (max) +tHD;DAT (min) -tAF(min) - [(DNF +3) x tI2CCLK]} / {(PRESC +1) x tI2CCLK } ≤ SDADEL
SDADEL ≤ {tHD;DAT (max) -tAF(max) - [(DNF+4) x tI2CCLK]} / {(PRESC +1) x tI2CCLK }
Note: tAF(min) / tAF(max) are part of the equation only when the analog filter is enabled. Refer to
device datasheet for tAF values.
The maximum tHD;DAT can be 3.45 µs, 0.9 µs and 0.45 µs for Standard-mode, Fast-mode
and Fast-mode Plus, but must be less than the maximum of tVD;DAT by a transition time.
This maximum must only be met if the device does not stretch the LOW period (tLOW) of the
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before
it releases the clock.
The SDA rising edge is usually the worst case, so in this case the previous equation
becomes:
SDADEL ≤ {tVD;DAT (max) -tr (max) -260 ns - [(DNF+4) x tI2CCLK]} / {(PRESC +1) x tI2CCLK }.
Note: This condition can be violated when NOSTRETCH = 0, because the device stretches SCL
low to guarantee the set-up time, according to the SCLDEL value.
Refer to Table 104: I2C-SMBus specification data setup and hold times for tf, tr, tHD;DAT and
tVD;DAT standard values.
• After tSDADEL delay, or after sending SDA output in case the slave had to stretch the
clock because the data was not yet written in I2C_TXDR register, SCL line is kept at
low level during the setup time. This setup time is tSCLDEL = (SCLDEL+1) x tPRESC where
tPRESC = (PRESC+1) x tI2CCLK.
tSCLDEL impacts the setup time tSU;DAT .

In order to bridge the undefined region of the SDA transition (rising edge usually worst
case), the user must program SCLDEL in such a way that:
{[tr (max) + tSU;DAT (min)] / [(PRESC+1)] x tI2CCLK]} - 1 <= SCLDEL
Refer to Table 104: I2C-SMBus specification data setup and hold times for tr and tSU;DAT
standard values.
The SDA and SCL transition time values to be used are the ones in the application. Using
the maximum values from the standard increases the constraints for the SDADEL and
SCLDEL calculation, but ensures the feature whatever the application.

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Note: At every clock pulse, after SCL falling edge detection, the I2C master or slave stretches SCL
low during at least [(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x tI2CCLK, in both transmission
and reception modes. In transmission mode, in case the data is not yet written in I2C_TXDR
when SDADEL counter is finished, the I2C keeps on stretching SCL low until the next data
is written. Then new data MSB is sent on SDA output, and SCLDEL counter starts,
continuing stretching SCL low to guarantee the data setup time.
If NOSTRETCH = 1 in slave mode, the SCL is not stretched. Consequently the SDADEL
must be programmed in such a way to guarantee also a sufficient setup time.

Table 104. I2C-SMBus specification data setup and hold times

Standard-mode Fast-mode Fast-mode Plus
SMBus
(Sm) (Fm) (Fm+)
Symbol Parameter Unit
Min. Max Min. Max Min. Max Min. Max

tHD;DAT Data hold time 0 - 0 - 0 - 0.3 -

µs
tVD;DAT Data valid time - 3.45 - 0.9 - 0.45 - -
tSU;DAT Data setup time 250 - 100 - 50 - 250 -
Rise time of both SDA
tr - 1000 - 300 - 120 - 1000
and SCL signals ns
Fall time of both SDA
tf - 300 - 300 - 120 - 300
and SCL signals

Additionally, in master mode, the SCL clock high and low levels must be configured by
programming the PRESC[3:0], SCLH[7:0] and SCLL[7:0] bits in the I2C_TIMINGR register.
• When the SCL falling edge is internally detected, a delay is inserted before releasing
the SCL output. This delay is tSCLL = (SCLL+1) x tPRESC where tPRESC = (PRESC+1) x
tI2CCLK.
tSCLL impacts the SCL low time tLOW .
• When the SCL rising edge is internally detected, a delay is inserted before forcing the
SCL output to low level. This delay is tSCLH = (SCLH+1) x tPRESC where tPRESC =
(PRESC+1) x tI2CCLK. tSCLH impacts the SCL high time tHIGH .

Refer to I2C master initialization for more details.

Caution: Changing the timing configuration is not allowed when the I2C is enabled.
The I2C slave NOSTRETCH mode must also be configured before enabling the peripheral.
Refer to I2C slave initialization for more details.
Caution: Changing the NOSTRETCH configuration is not allowed when the I2C is enabled.

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Figure 186. I2C initialization flow

Initial settings

Clear PE bit in I2C_CR1

Configure ANFOFF and DNF[3:0] in I2C_CR1

Configure PRESC[3:0],

SDADEL[3:0], SCLDEL[3:0], SCLH[7:0],

SCLL[7:0] in I2C_TIMINGR

Configure NOSTRETCH in I2C_CR1

Set PE bit in I2C_CR1

End

MS19847V2

23.4.7 Software reset

A software reset can be performed by clearing the PE bit in the I2C_CR1 register. In that
case I2C lines SCL and SDA are released. Internal states machines are reset and
communication control bits, as well as status bits come back to their reset value. The
configuration registers are not impacted.
Here is the list of impacted register bits:
1. I2C_CR2 register: START, STOP, NACK
2. I2C_ISR register: BUSY, TXE, TXIS, RXNE, ADDR, NACKF, TCR, TC, STOPF, BERR,
ARLO, OVR
and in addition when the SMBus feature is supported:
1. I2C_CR2 register: PECBYTE
2. I2C_ISR register: PECERR, TIMEOUT, ALERT
PE must be kept low during at least three APB clock cycles in order to perform the software
reset. This is ensured by writing the following software sequence:
1. Write PE = 0
2. Check PE = 0
3. Write PE = 1.

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23.4.8 Data transfer

The data transfer is managed through transmit and receive data registers and a shift
register.

Reception
The SDA input fills the shift register. After the eighth SCL pulse (when the complete data
byte is received), the shift register is copied into I2C_RXDR register if it is empty (RXNE =
0). If RXNE = 1, meaning that the previous received data byte has not yet been read, the
SCL line is stretched low until I2C_RXDR is read. The stretch is inserted between the eighth
and ninth SCL pulse (before the acknowledge pulse).

Figure 187. Data reception

ACK pulse ACK pulse

legend:
SCL SCL
stretch
Shift register xx data1 xx data2 xx

RXNE

rd data0 rd data1

I2C_RXDR data0 data1 data2

MS19848V1

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Transmission
If the I2C_TXDR register is not empty (TXE=0), its content is copied into the shift register
after the ninth SCL pulse (the Acknowledge pulse). Then the shift register content is shifted
out on SDA line. If TXE = 1, meaning that no data is written yet in I2C_TXDR, SCL line is
stretched low until I2C_TXDR is written. The stretch is done after the ninth SCL pulse.

Figure 188. Data transmission

ACK pulse ACK pulse

legend:
SCL
SCL
stretch

data1

data2
Shift register xx xx xx

TXE

wr data1 wr data2

I2C_TXDR data0 data1 data2

MS19849V1

Hardware transfer management

The I2C has a byte counter embedded in hardware in order to manage byte transfer and to
close the communication in various modes such as:
– NACK, STOP and ReSTART generation in master mode
– ACK control in slave receiver mode
– PEC generation/checking when SMBus feature is supported
The byte counter is always used in master mode. By default it is disabled in slave mode, but
it can be enabled by software by setting the SBC (Slave Byte Control) bit in the I2C_CR2
register.
The number of bytes to be transferred is programmed in the NBYTES[7:0] bit field in the
I2C_CR2 register. If the number of bytes to be transferred (NBYTES) is greater than 255, or
if a receiver wants to control the acknowledge value of a received data byte, the reload
mode must be selected by setting the RELOAD bit in the I2C_CR2 register. In this mode,
the TCR flag is set when the number of bytes programmed in NBYTES is transferred, and
an interrupt is generated if TCIE is set. SCL is stretched as long as TCR flag is set. TCR is
cleared by software when NBYTES is written to a non-zero value.
When the NBYTES counter is reloaded with the last number of bytes, RELOAD bit must be
cleared.

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When RELOAD=0 in master mode, the counter can be used in 2 modes:

• Automatic end mode (AUTOEND = ‘1’ in the I2C_CR2 register). In this mode, the
master automatically sends a STOP condition once the number of bytes programmed
in the NBYTES[7:0] bit field is transferred.
• Software end mode (AUTOEND = ‘0’ in the I2C_CR2 register). In this mode, software
action is expected once the number of bytes programmed in the NBYTES[7:0] bit field
is transferred; the TC flag is set and an interrupt is generated if the TCIE bit is set. The
SCL signal is stretched as long as the TC flag is set. The TC flag is cleared by software
when the START or STOP bit is set in the I2C_CR2 register. This mode must be used
when the master wants to send a RESTART condition.
Caution: The AUTOEND bit has no effect when the RELOAD bit is set.

Table 105. I2C configuration

Function SBC bit RELOAD bit AUTOEND bit

Master Tx/Rx NBYTES + STOP x 0 1

Master Tx/Rx + NBYTES + RESTART x 0 0
Slave Tx/Rx
0 x x
all received bytes ACKed
Slave Rx with ACK control 1 1 x

23.4.9 I2C slave mode

I2C slave initialization
In order to work in slave mode, the user must enable at least one slave address. Two
registers I2C_OAR1 and I2C_OAR2 are available in order to program the slave own
addresses OA1 and OA2.
• OA1 can be configured either in 7-bit mode (by default) or in 10-bit addressing mode by
setting the OA1MODE bit in the I2C_OAR1 register.
OA1 is enabled by setting the OA1EN bit in the I2C_OAR1 register.
• If additional slave addresses are required, the second slave address OA2 can be
configured. Up to 7 OA2 LSB can be masked by configuring the OA2MSK[2:0] bits in
the I2C_OAR2 register. Therefore for OA2MSK configured from 1 to 6, only OA2[7:2],
OA2[7:3], OA2[7:4], OA2[7:5], OA2[7:6] or OA2[7] are compared with the received
address. As soon as OA2MSK is not equal to 0, the address comparator for OA2
excludes the I2C reserved addresses (0000 XXX and 1111 XXX), which are not
acknowledged. If OA2MSK=7, all received 7-bit addresses are acknowledged (except
reserved addresses). OA2 is always a 7-bit address.
These reserved addresses can be acknowledged if they are enabled by the specific
enable bit, if they are programmed in the I2C_OAR1 or I2C_OAR2 register with
OA2MSK=0.
OA2 is enabled by setting the OA2EN bit in the I2C_OAR2 register.
• The general call address is enabled by setting the GCEN bit in the I2C_CR1 register.
When the I2C is selected by one of its enabled addresses, the ADDR interrupt status flag is
set, and an interrupt is generated if the ADDRIE bit is set.

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By default, the slave uses its clock stretching capability, which means that it stretches the
SCL signal at low level when needed, in order to perform software actions. If the master
does not support clock stretching, the I2C must be configured with NOSTRETCH = 1 in the
I2C_CR1 register.
After receiving an ADDR interrupt, if several addresses are enabled the user must read the
ADDCODE[6:0] bits in the I2C_ISR register in order to check which address matched. DIR
flag must also be checked in order to know the transfer direction.

Slave clock stretching (NOSTRETCH = 0)

In default mode, the I2C slave stretches the SCL clock in the following situations:
• When the ADDR flag is set: the received address matches with one of the enabled
slave addresses. This stretch is released when the ADDR flag is cleared by software
setting the ADDRCF bit.
• In transmission, if the previous data transmission is completed and no new data is
written in I2C_TXDR register, or if the first data byte is not written when the ADDR flag
is cleared (TXE = 1). This stretch is released when the data is written to the I2C_TXDR
register.
• In reception when the I2C_RXDR register is not read yet and a new data reception is
completed. This stretch is released when I2C_RXDR is read.
• When TCR = 1 in Slave Byte Control mode, reload mode (SBC=1 and RELOAD=1),
meaning that the last data byte has been transferred. This stretch is released when
then TCR is cleared by writing a non-zero value in the NBYTES[7:0] field.
• After SCL falling edge detection, the I2C stretches SCL low during
[(SDADEL+SCLDEL+1) x (PRESC+1) + 1] x tI2CCLK.

Slave without clock stretching (NOSTRETCH = 1)

When NOSTRETCH = 1 in the I2C_CR1 register, the I2C slave does not stretch the SCL
signal.
• The SCL clock is not stretched while the ADDR flag is set.
• In transmission, the data must be written in the I2C_TXDR register before the first SCL
pulse corresponding to its transfer occurs. If not, an underrun occurs, the OVR flag is
set in the I2C_ISR register and an interrupt is generated if the ERRIE bit is set in the
I2C_CR1 register. The OVR flag is also set when the first data transmission starts and
the STOPF bit is still set (has not been cleared). Therefore, if the user clears the
STOPF flag of the previous transfer only after writing the first data to be transmitted in
the next transfer, he ensures that the OVR status is provided, even for the first data to
be transmitted.
• In reception, the data must be read from the I2C_RXDR register before the ninth SCL
pulse (ACK pulse) of the next data byte occurs. If not an overrun occurs, the OVR flag
is set in the I2C_ISR register and an interrupt is generated if the ERRIE bit is set in the
I2C_CR1 register.

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Slave byte control mode

In order to allow byte ACK control in slave reception mode, The Slave byte control mode
must be enabled by setting the SBC bit in the I2C_CR1 register. This is required to be
compliant with SMBus standards.
The Reload mode must be selected in order to allow byte ACK control in slave reception
mode (RELOAD = 1). To get control of each byte, NBYTES must be initialized to 0x1 in the
ADDR interrupt subroutine, and reloaded to 0x1 after each received byte. When the byte is
received, the TCR bit is set, stretching the SCL signal low between the eighth and ninth SCL
pulses. The user can read the data from the I2C_RXDR register, and then decide to
acknowledge it or not by configuring the ACK bit in the I2C_CR2 register. The SCL stretch is
released by programming NBYTES to a non-zero value: the acknowledge or not-
acknowledge is sent and next byte can be received.
NBYTES can be loaded with a value greater than 0x1, and in this case, the reception flow is
continuous during NBYTES data reception.
Note: The SBC bit must be configured when the I2C is disabled, or when the slave is not
addressed, or when ADDR = 1.
The RELOAD bit value can be changed when ADDR = 1, or when TCR = 1.
Caution: The Slave byte control mode is not compatible with NOSTRETCH mode. Setting SBC when
NOSTRETCH = 1 is not allowed.

Figure 189. Slave initialization flow

Slave
initialization

Initial settings

Clear {OA1EN, OA2EN} in I2C_OAR1 and I2C_OAR2

Configure {OA1[9:0], OA1MODE, OA1EN,

OA2[6:0], OA2MSK[2:0], OA2EN, GCEN}

Configure SBC in I2C_CR1*

Enable interrupts and/or

DMA in I2C_CR1

End

*SBC must be set to support SMBus features

MS19850V2

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For code example, refer to A.14.1: I2C configured in slave mode code example.

Slave transmitter
A transmit interrupt status (TXIS) is generated when the I2C_TXDR register becomes
empty. An interrupt is generated if the TXIE bit is set in the I2C_CR1 register.
The TXIS bit is cleared when the I2C_TXDR register is written with the next data byte to be
transmitted.
When a NACK is received, the NACKF bit is set in the I2C_ISR register and an interrupt is
generated if the NACKIE bit is set in the I2C_CR1 register. The slave automatically releases
the SCL and SDA lines in order to let the master perform a STOP or a RESTART condition.
The TXIS bit is not set when a NACK is received.
When a STOP is received and the STOPIE bit is set in the I2C_CR1 register, the STOPF
flag is set in the I2C_ISR register and an interrupt is generated. In most applications, the
SBC bit is usually programmed to ‘0’. In this case, If TXE = 0 when the slave address is
received (ADDR = 1), the user can choose either to send the content of the I2C_TXDR
register as the first data byte, or to flush the I2C_TXDR register by setting the TXE bit in
order to program a new data byte.
In Slave byte control mode (SBC = 1), the number of bytes to be transmitted must be
programmed in NBYTES in the address match interrupt subroutine (ADDR = 1). In this
case, the number of TXIS events during the transfer corresponds to the value programmed
in NBYTES.
Caution: When NOSTRETCH = 1, the SCL clock is not stretched while the ADDR flag is set, so the
user cannot flush the I2C_TXDR register content in the ADDR subroutine, in order to
program the first data byte. The first data byte to be sent must be previously programmed in
the I2C_TXDR register:
• This data can be the data written in the last TXIS event of the previous transmission
message.
• If this data byte is not the one to be sent, the I2C_TXDR register can be flushed by
setting the TXE bit in order to program a new data byte. The STOPF bit must be
cleared only after these actions, in order to guarantee that they are executed before the
first data transmission starts, following the address acknowledge.
If STOPF is still set when the first data transmission starts, an underrun error is
generated (the OVR flag is set).
If a TXIS event is needed, (transmit interrupt or transmit DMA request), the user must
set the TXIS bit in addition to the TXE bit, in order to generate a TXIS event.

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Figure 190. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 0

Slave
transmission

Slave initialization

No

I2C_ISR.ADDR
=1?

Yes
SCL
stretched
Read ADDCODE and DIR in I2C_ISR
Optional: Set I2C_ISR.TXE = 1
Set I2C_ICR.ADDRCF

No
I2C_ISR.TXIS
=1?

Yes

Write I2C_TXDR.TXDATA

MS19851V2

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Figure 191. Transfer sequence flow for I2C slave transmitter, NOSTRETCH = 1

Slave
transmission

Slave initialization

No
No
I2C_ISR.TXIS I2C_ISR.STOPF
=1? =1?

Yes Yes

Write I2C_TXDR.TXDATA Optional: Set I2C_ISR.TXE = 1

and I2C_ISR.TXIS=1

Set I2C_ICR.STOPCF

MS19852V2

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Figure 192. Transfer bus diagrams for I2C slave transmitter

legend:
Example I2C slave transmitter 3 bytes with 1st data flushed,
NOSTRETCH=0: transmission
ADDR TXIS TXIS TXIS TXIS reception

S Address A A A data3 NA P
SCL stretch
data1 data2

EV1 EV2 EV3 EV4 EV5

TXE

EV1: ADDR ISR: check ADDCODE and DIR, set TXE, set ADDRCF
EV2: TXIS ISR: wr data1
EV3: TXIS ISR: wr data2
EV4: TXIS ISR: wr data3
EV5: TXIS ISR: wr data4 (not sent)

legend :
Example I2C slave transmitter 3 bytes without 1st data flush,
NOSTRETCH=0: transmission
ADDR TXIS TXIS TXIS reception

SCL stretch
S Address A data1 A data2 A data3 NA P

EV1 EV2 EV3 EV4

TXE

EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF

EV2: TXIS ISR: wr data2
EV3: TXIS ISR: wr data3
EV4: TXIS ISR: wr data4 (not sent)

legend:
Example I2C slave transmitter 3 bytes, NOSTRETCH=1:
transmission
TXIS TXIS TXIS STOPF
reception

S Address A data1 A data2 A data3 NA P SCL stretch

EV1 EV2 EV3 EV4 EV5

TXE

EV1: wr data1
EV2: TXIS ISR: wr data2
EV3: TXIS ISR: wr data3
EV4: TXIS ISR: wr data4 (not sent)
EV5: STOPF ISR: (optional: set TXE and TXIS), set STOPCF

MS19853V2

For code example, refer to A.14.2: I2C slave transmitter code example.

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Slave receiver
RXNE is set in I2C_ISR when the I2C_RXDR is full, and generates an interrupt if RXIE is
set in I2C_CR1. RXNE is cleared when I2C_RXDR is read.
When a STOP is received and STOPIE is set in I2C_CR1, STOPF is set in I2C_ISR and an
interrupt is generated.

Figure 193. Transfer sequence flow for slave receiver with NOSTRETCH = 0

Slave reception

Slave initialization

No

I2C_ISR.ADDR
=1?

Yes
SCL
stretched
Read ADDCODE and DIR in I2C_ISR
Set I2C_ICR.ADDRCF

No
I2C_ISR.RXNE
=1?

Yes

Write I2C_RXDR.RXDATA

MS19855V2

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Figure 194. Transfer sequence flow for slave receiver with NOSTRETCH = 1

Slave reception

Slave initialization

No
No
I2C_ISR.RXNE I2C_ISR.STOPF
=1? =1?

Yes Yes

Read I2C_RXDR.RXDATA Set I2C_ICR.STOPCF

MS19856V2

Figure 195. Transfer bus diagrams for I2C slave receiver

legend:
Example I2C slave receiver 3 bytes, NOSTRETCH=0:
transmission
ADDR RXNE RXNE RXNE reception

SCL stretch
S Address A data1 A data2 A data3 A

EV1 EV2 EV3 EV4

RXNE

EV1: ADDR ISR: check ADDCODE and DIR, set ADDRCF

EV2: RXNE ISR: rd data1
EV3 : RXNE ISR: rd data2
EV4: RXNE ISR: rd data3

Example I2C slave receiver 3 bytes, NOSTRETCH=1: legend:

transmission
RXNE RXNE RXNE reception

S Address A data 1 A data 2 A data 3 A P SCL stretch

EV1 EV2 EV3

RXNE

EV1: RXNE ISR: rd data1

EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd data3
EV4: STOPF ISR: set STOPCF
MS19857V3

For code example, refer to A.14.3: I2C slave receiver code example.

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23.4.10 I2C master mode

I2C master initialization
Before enabling the peripheral, the I2C master clock must be configured by setting the
SCLH and SCLL bits in the I2C_TIMINGR register.
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
Configuration window.
A clock synchronization mechanism is implemented in order to support multi-master
environment and slave clock stretching.
In order to allow clock synchronization:
• The low level of the clock is counted using the SCLL counter, starting from the SCL low
level internal detection.
• The high level of the clock is counted using the SCLH counter, starting from the SCL
high level internal detection.
The I2C detects its own SCL low level after a tSYNC1 delay depending on the SCL falling
edge, SCL input noise filters (analog + digital) and SCL synchronization to the I2CxCLK
clock. The I2C releases SCL to high level once the SCLL counter reaches the value
programmed in the SCLL[7:0] bits in the I2C_TIMINGR register.
The I2C detects its own SCL high level after a tSYNC2 delay depending on the SCL rising
edge, SCL input noise filters (analog + digital) and SCL synchronization to I2CxCLK clock.
The I2C ties SCL to low level once the SCLH counter is reached reaches the value
programmed in the SCLH[7:0] bits in the I2C_TIMINGR register.
Consequently the master clock period is:
tSCL = tSYNC1 + tSYNC2 + {[(SCLH+1) + (SCLL+1)] x (PRESC+1) x tI2CCLK}
The duration of tSYNC1 depends on these parameters:
– SCL falling slope
– When enabled, input delay induced by the analog filter.
– When enabled, input delay induced by the digital filter: DNF x tI2CCLK
– Delay due to SCL synchronization with I2CCLK clock (2 to 3 I2CCLK periods)
The duration of tSYNC2 depends on these parameters:
– SCL rising slope
– When enabled, input delay induced by the analog filter.
– When enabled, input delay induced by the digital filter: DNF x tI2CCLK
– Delay due to SCL synchronization with I2CCLK clock (2 to 3 I2CCLK periods)

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Figure 196. Master clock generation

SCL master clock generation

SCL high level detected

SCLH counter starts

tSYNC2 SCLH
SCLL
tSYNC1
SCL

SCL low level detected

SCL released
SCLL counter starts

SCL driven low

SCL master clock synchronization

SCL high level detected SCL high level detected SCL high level detected
SCLH counter starts SCLH counter starts SCLH counter starts

SCLH SCLH SCLH

SCLL SCLL

SCL driven low by SCL driven low by

another device another device
SCL low level detected
SCLL counter starts

SCL low level detected

SCLL counter starts SCL released

MS19858V1

Caution: In order to be I2C or SMBus compliant, the master clock must respect the timings given the
table below.

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Table 106. I2C-SMBus specification clock timings

Standard- Fast-mode Fast-mode
SMBus
mode (Sm) (Fm) Plus (Fm+)
Symbol Parameter Unit
Min Max Min Max Min Max Min Max

fSCL SCL clock frequency - 100 - 400 - 1000 - 100 kHz

tHD:STA Hold time (repeated) START condition 4.0 - 0.6 - 0.26 - 4.0 - µs
Set-up time for a repeated START
tSU:STA 4.7 - 0.6 - 0.26 - 4.7 - µs
condition
tSU:STO Set-up time for STOP condition 4.0 - 0.6 - 0.26 - 4.0 - µs
Bus free time between a STOP and
tBUF 4.7 - 1.3 - 0.5 - 4.7 - µs
START condition
tLOW Low period of the SCL clock 4.7 - 1.3 - 0.5 - 4.7 - µs
tHIGH Period of the SCL clock 4.0 - 0.6 - 0.26 - 4.0 50 µs
tr Rise time of both SDA and SCL signals - 1000 - 300 - 120 - 1000 ns
tf Fall time of both SDA and SCL signals - 300 - 300 - 120 - 300 ns

Note: SCLL is also used to generate the tBUF and tSU:STA timings.
SCLH is also used to generate the tHD:STA and tSU:STO timings.
Refer to Section 23.4.11: I2C_TIMINGR register configuration examples for examples of
I2C_TIMINGR settings vs. I2CCLK frequency.

Master communication initialization (address phase)

In order to initiate the communication, the user must program the following parameters for
the addressed slave in the I2C_CR2 register:
• Addressing mode (7-bit or 10-bit): ADD10
• Slave address to be sent: SADD[9:0]
• Transfer direction: RD_WRN
• In case of 10-bit address read: HEAD10R bit. HEAD10R must be configure to indicate
if the complete address sequence must be sent, or only the header in case of a
direction change.
• The number of bytes to be transferred: NBYTES[7:0]. If the number of bytes is equal to
or greater than 255 bytes, NBYTES[7:0] must initially be filled with 0xFF.
The user must then set the START bit in I2C_CR2 register. Changing all the above bits is
not allowed when START bit is set.
Then the master automatically sends the START condition followed by the slave address as
soon as it detects that the bus is free (BUSY = 0) and after a delay of tBUF.
In case of an arbitration loss, the master automatically switches back to slave mode and can
acknowledge its own address if it is addressed as a slave.
Note: The START bit is reset by hardware when the slave address has been sent on the bus,
whatever the received acknowledge value. The START bit is also reset by hardware if an
arbitration loss occurs.
In 10-bit addressing mode, when the Slave Address first 7 bits is NACKed by the slave, the

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master re-launches automatically the slave address transmission until ACK is received. In
this case ADDRCF must be set if a NACK is received from the slave, in order to stop
sending the slave address.
If the I2C is addressed as a slave (ADDR = 1) while the START bit is set, the I2C switches to
slave mode and the START bit is cleared, when the ADDRCF bit is set.
Note: The same procedure is applied for a Repeated Start condition. In this case BUSY = 1.

Figure 197. Master initialization flow

Master
initialization

Initial settings

Enable interrupts and/or DMA in I2C_CR1

End

MS19859V2

For code example, refer to A.14.4: I2C configured in master mode to receive code example
andA.14.5: I2C configured in master mode to transmit code example.

Initialization of a master receiver addressing a 10-bit address slave

• If the slave address is in 10-bit format, the user can choose to send the complete read
sequence by clearing the HEAD10R bit in the I2C_CR2 register. In this case the master
automatically sends the following complete sequence after the START bit is set:
(Re)Start + Slave address 10-bit header Write + Slave address second byte + REStart
+ Slave address 10-bit header Read

Figure 198. 10-bit address read access with HEAD10R = 0

11110XX 0 11110XX 1

Slave address Slave address Slave address

S R/W A1 A2 Sr R/W A3 DATA A DATA A P
1st 7 bits 2nd byte 1st 7 bits

Write Read

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• If the master addresses a 10-bit address slave, transmits data to this slave and then
reads data from the same slave, a master transmission flow must be done first. Then a
repeated start is set with the 10 bit slave address configured with HEAD10R = 1. In this
case the master sends this sequence: ReStart + Slave address 10-bit header Read.

Figure 199. 10-bit address read access with HEAD10R = 1

11110XX 0

Slave address Slave address

S R/W A A DATA A DATA A/A
1st 7 bits 2nd byte

Write

11110XX 1
Slave address
Sr R/W A DATA A DATA A P
1st 7 bits

Read

MS19823V1

Master transmitter
In the case of a write transfer, the TXIS flag is set after each byte transmission, after the
ninth SCL pulse when an ACK is received.
A TXIS event generates an interrupt if the TXIE bit is set in the I2C_CR1 register. The flag is
cleared when the I2C_TXDR register is written with the next data byte to be transmitted.
The number of TXIS events during the transfer corresponds to the value programmed in
NBYTES[7:0]. If the total number of data bytes to be sent is greater than 255, reload mode
must be selected by setting the RELOAD bit in the I2C_CR2 register. In this case, when
NBYTES data have been transferred, the TCR flag is set and the SCL line is stretched low
until NBYTES[7:0] is written to a non-zero value.
The TXIS flag is not set when a NACK is received.
• When RELOAD=0 and NBYTES data have been transferred:
– In automatic end mode (AUTOEND=1), a STOP is automatically sent.
– In software end mode (AUTOEND=0), the TC flag is set and the SCL line is
stretched low in order to perform software actions:
A RESTART condition can be requested by setting the START bit in the I2C_CR2
register with the proper slave address configuration, and number of bytes to be
transferred. Setting the START bit clears the TC flag and the START condition is
sent on the bus.
A STOP condition can be requested by setting the STOP bit in the I2C_CR2
register. Setting the STOP bit clears the TC flag and the STOP condition is sent on
the bus.
• If a NACK is received: the TXIS flag is not set, and a STOP condition is automatically
sent after the NACK reception. the NACKF flag is set in the I2C_ISR register, and an
interrupt is generated if the NACKIE bit is set.

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Figure 200. Transfer sequence flow for I2C master transmitter for N≤255 bytes

Master
transmission

Master initialization

NBYTES = N
AUTOEND = 0 for RESTART; 1 for STOP
Configure slave address
Set I2C_CR2.START

No

No
I2C_ISR.NACKF = I2C_ISR.TXIS
1? =1?

Yes Yes

Write I2C_TXDR
End

NBYTES No
transmitted?

Yes

Yes
I2C_ISR.TC =
1?

No Set I2C_CR2.START with

slave addess NBYTES ...

End

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Figure 201. Transfer sequence flow for I2C master transmitter for N>255 bytes

Master
transmission

Master initialization

NBYTES = 0xFF; N=N-255

RELOAD = 1
Configure slave address
Set I2C_CR2.START

No

No
I2C_ISR.NACKF I2C_ISR.TXIS
= 1? = 1?

Yes Yes

Write I2C_TXDR
End

No
NBYTES
transmitted ?

Yes

Yes
I2C_ISR.TC
= 1?

Set I2C_CR2.START
with slave addess No
NBYTES ...

I2C_ISR.TCR
= 1?

Yes
IF N< 256
NBYTES = N; N = 0; RELOAD = 0
AUTOEND = 0 for RESTART; 1 for STOP
End
ELSE
NBYTES = 0xFF; N = N-255
RELOAD = 1

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Figure 202. Transfer bus diagrams for I2C master transmitter

Example I2C master transmitter 2 bytes, automatic end mode (STOP)

legend:

TXIS TXIS transmission

reception
S Address A data1 A data2 A P
SCL stretch
INIT EV1 EV2

TXE

NBYTES xx 2

INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START

EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2

Example I2C master transmitter 2 bytes, software end mode (RESTART)

TXIS TXIS TC legend:

transmission
S Address A data1 A data2 A ReS Address
reception

INIT EV1 EV2 EV3 SCL stretch

TXE

NBYTES xx 2

INIT: program Slave address, program NBYTES = 2, AUTOEND=0, set START

EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2
EV3: TC ISR: program Slave address, program NBYTES = N, set START

MS19862V2

For code example, refer to A.14.6: I2C master transmitter code example.

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Master receiver
In the case of a read transfer, the RXNE flag is set after each byte reception, after the eighth
SCL pulse. An RXNE event generates an interrupt if the RXIE bit is set in the I2C_CR1
register. The flag is cleared when I2C_RXDR is read.
If the total number of data bytes to be received is greater than 255, reload mode must be
selected by setting the RELOAD bit in the I2C_CR2 register. In this case, when
NBYTES[7:0] data have been transferred, the TCR flag is set and the SCL line is stretched
low until NBYTES[7:0] is written to a non-zero value.
• When RELOAD=0 and NBYTES[7:0] data have been transferred:
– In automatic end mode (AUTOEND=1), a NACK and a STOP are automatically
sent after the last received byte.
– In software end mode (AUTOEND=0), a NACK is automatically sent after the last
received byte, the TC flag is set and the SCL line is stretched low in order to allow
software actions:
A RESTART condition can be requested by setting the START bit in the I2C_CR2
register with the proper slave address configuration, and number of bytes to be
transferred. Setting the START bit clears the TC flag and the START condition,
followed by slave address, are sent on the bus.
A STOP condition can be requested by setting the STOP bit in the I2C_CR2
register. Setting the STOP bit clears the TC flag and the STOP condition is sent on
the bus.

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Figure 203. Transfer sequence flow for I2C master receiver for N≤255 bytes

Master reception

Master initialization

NBYTES = N
AUTOEND = 0 for RESTART; 1 for STOP
Configure slave address
Set I2C_CR2.START

No
I2C_ISR.RXNE
=1?

Yes

Read I2C_RXDR

NBYTES No
received?

Yes

Yes
I2C_ISR.TC =
1?

No Set I2C_CR2.START with

slave addess NBYTES ...

End

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Figure 204. Transfer sequence flow for I2C master receiver for N >255 bytes

Master reception

Master initialization

NBYTES = 0xFF; N=N-255

RELOAD =1
Configure slave address
Set I2C_CR2.START

No
I2C_ISR.RXNE
=1?

Yes

Read I2C_RXDR

NBYTES No
received?

Yes

Yes
I2C_ISR.TC =
1?

Set I2C_CR2.START with

No
slave addess NBYTES ...
No
I2C_ISR.TCR
= 1?

Yes
IF N< 256
NBYTES =N; N=0;RELOAD=0
AUTOEND=0 for RESTART; 1 for STOP
ELSE
NBYTES =0xFF;N=N-255
RELOAD=1

End

MS19864V2

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Figure 205. Transfer bus diagrams for I2C master receiver

Example I2C master receiver 2 bytes, automatic end mode (STOP)

RXNE RXNE
legend:

S Address A data1 A data2 NA P transmission

reception
INIT EV1 EV2
SCL stretch
NBYTES xx 2

INIT: program Slave address, program NBYTES = 2, AUTOEND=1, set START

EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2

Example I2C master receiver 2 bytes, software end mode (RESTART)

RXNE RXNE TC legend:

transmission
S Address A data1 A data2 NA ReS Address
reception

INIT EV1 EV2 SCL stretch

NBYTES

xx 2 N

INIT: program Slave address, program NBYTES = 2, AUTOEND=0, set START

EV1: RXNE ISR: rd data1
EV2: RXNE ISR: read data2
EV3: TC ISR: program Slave address, program NBYTES = N, set START

MS19865V1

For code example refer to A.14.7: I2C master receiver code example.

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23.4.11 I2C_TIMINGR register configuration examples

The tables below provide examples of how to program the I2C_TIMINGR to obtain timings
compliant with the I2C specification. In order to get more accurate configuration values, the
STM32CubeMX tool (I2C Configuration window) must be used.

Table 107. Examples of timing settings for fI2CCLK = 8 MHz

Standard-mode (Sm) Fast-mode (Fm) Fast-mode Plus (Fm+)
Parameter
10 kHz 100 kHz 400 kHz 500 kHz

PRESC 1 1 0 0
SCLL 0xC7 0x13 0x9 0x6
tSCLL 200 x 250 ns = 50 µs 20 x 250 ns = 5.0 µs 10 x 125 ns = 1250 ns 7 x 125 ns = 875 ns
SCLH 0xC3 0xF 0x3 0x3
tSCLH 196 x 250 ns = 49 µs 16 x 250 ns = 4.0µs 4 x 125 ns = 500 ns 4 x 125 ns = 500 ns
(1)
tSCL ~100 µs(2) ~10 µs(2) ~2500 ns(3) ~2000 ns(4)
SDADEL 0x2 0x2 0x1 0x0
tSDADEL 2 x 250 ns = 500 ns 2 x 250 ns = 500 ns 1 x 125 ns = 125 ns 0 ns
SCLDEL 0x4 0x4 0x3 0x1
tSCLDEL 5 x 250 ns = 1250 ns 5 x 250 ns = 1250 ns 4 x 125 ns = 500 ns 2 x 125 ns = 250 ns
1. SCL period tSCL is greater than tSCLL + tSCLH due to SCL internal detection delay. Values provided for tSCL are examples
only.
2. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 500 ns. Example with tSYNC1 + tSYNC2 = 1000 ns.
3. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 500 ns. Example with tSYNC1 + tSYNC2 = 750 ns.
4. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 500 ns. Example with tSYNC1 + tSYNC2 = 655 ns.

Table 108. Examples of timings settings for fI2CCLK = 16 MHz

Standard-mode (Sm) Fast-mode (Fm) Fast-mode Plus (Fm+)
Parameter
10 kHz 100 kHz 400 kHz 1000 kHz

PRESC 3 3 1 0
SCLL 0xC7 0x13 0x9 0x4
tSCLL 200 x 250 ns = 50 µs 20 x 250 ns = 5.0 µs 10 x 125 ns = 1250 ns 5 x 62.5 ns = 312.5 ns
SCLH 0xC3 0xF 0x3 0x2
tSCLH 196 x 250 ns = 49 µs 16 x 250 ns = 4.0 µs 4 x 125 ns = 500 ns 3 x 62.5 ns = 187.5 ns
(1)
tSCL ~100 µs(2) ~10 µs(2) ~2500 ns(3) ~1000 ns(4)
SDADEL 0x2 0x2 0x2 0x0
tSDADEL 2 x 250 ns = 500 ns 2 x 250 ns = 500 ns 2 x 125 ns = 250 ns 0 ns
SCLDEL 0x4 0x4 0x3 0x2
tSCLDEL 5 x 250 ns = 1250 ns 5 x 250 ns = 1250 ns 4 x 125 ns = 500 ns 3 x 62.5 ns = 187.5 ns
1. SCL period tSCL is greater than tSCLL + tSCLH due to SCL internal detection delay. Values provided for tSCL are examples
only.

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2. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 250 ns. Example with tSYNC1 + tSYNC2 = 1000 ns.
3. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 250 ns. Example with tSYNC1 + tSYNC2 = 750 ns.
4. tSYNC1 + tSYNC2 minimum value is 4 x tI2CCLK = 250 ns. Example with tSYNC1 + tSYNC2 = 500 ns.

23.4.12 SMBus specific features

This section is relevant only when SMBus feature is supported. Refer to Section 23.3: I2C
implementation.

Introduction
The system management bus (SMBus) is a two-wire interface through which various
devices can communicate with each other and with the rest of the system. It is based on I2C
principles of operation. The SMBus provides a control bus for system and power
management related tasks.
This peripheral is compatible with the SMBus specification (http://smbus.org).
The System Management Bus Specification refers to three types of devices.
• A slave is a device that receives or responds to a command.
• A master is a device that issues commands, generates the clocks and terminates the
transfer.
• A host is a specialized master that provides the main interface to the system’s CPU. A
host must be a master-slave and must support the SMBus host notify protocol. Only
one host is allowed in a system.
This peripheral can be configured as master or slave device, and also as a host.

Bus protocols
There are eleven possible command protocols for any given device. A device may use any
or all of the eleven protocols to communicate. The protocols are Quick Command, Send
Byte, Receive Byte, Write Byte, Write Word, Read Byte, Read Word, Process Call, Block
Read, Block Write and Block Write-Block Read Process Call. These protocols should be
implemented by the user software.
For more details of these protocols, refer to SMBus specification (http://smbus.org).

Address resolution protocol (ARP)

SMBus slave address conflicts can be resolved by dynamically assigning a new unique
address to each slave device. In order to provide a mechanism to isolate each device for the
purpose of address assignment each device must implement a unique device identifier
(UDID). This 128-bit number is implemented by software.
This peripheral supports the Address Resolution Protocol (ARP). The SMBus Device
Default Address (0b1100 001) is enabled by setting SMBDEN bit in I2C_CR1 register. The
ARP commands should be implemented by the user software.
Arbitration is also performed in slave mode for ARP support.
For more details of the SMBus address resolution protocol, refer to SMBus specification
(http://smbus.org).

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Received command and data acknowledge control

A SMBus receiver must be able to NACK each received command or data. In order to allow
the ACK control in slave mode, the Slave Byte Control mode must be enabled by setting
SBC bit in I2C_CR1 register. Refer to Slave byte control mode on page 603 for more details.

Host notify protocol

This peripheral supports the host notify protocol by setting the SMBHEN bit in the I2C_CR1
register. In this case the host acknowledges the SMBus host address (0b0001 000).
When this protocol is used, the device acts as a master and the host as a slave.

SMBus alert
The SMBus ALERT optional signal is supported. A slave-only device can signal the host
through the SMBALERT# pin that it wants to talk. The host processes the interrupt and
simultaneously accesses all SMBALERT# devices through the alert response address
(0b0001 100). Only the device(s) which pulled SMBALERT# low acknowledges the alert
response address.
When configured as a slave device(SMBHEN=0), the SMBA pin is pulled low by setting the
ALERTEN bit in the I2C_CR1 register. The Alert Response Address is enabled at the same
time.
When configured as a host (SMBHEN=1), the ALERT flag is set in the I2C_ISR register
when a falling edge is detected on the SMBA pin and ALERTEN=1. An interrupt is
generated if the ERRIE bit is set in the I2C_CR1 register. When ALERTEN=0, the ALERT
line is considered high even if the external SMBA pin is low.
If the SMBus ALERT pin is not needed, the SMBA pin can be used as a standard GPIO if
ALERTEN=0.

Packet error checking

A packet error checking mechanism has been introduced in the SMBus specification to
improve reliability and communication robustness. The packet error checking is
implemented by appending a packet error code (PEC) at the end of each message transfer.
The PEC is calculated by using the C(x) = x8 + x2 + x + 1 CRC-8 polynomial on all the
message bytes (including addresses and read/write bits).
The peripheral embeds a hardware PEC calculator and allows a not acknowledge to be sent
automatically when the received byte does not match with the hardware calculated PEC.

Timeouts
This peripheral embeds hardware timers in order to be compliant with the 3 timeouts defined
in SMBus specification.

Table 109. SMBus timeout specifications

Limits
Symbol Parameter Unit
Min Max

tTIMEOUT Detect clock low timeout 25 35 ms

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Table 109. SMBus timeout specifications (continued)

Limits
Symbol Parameter Unit
Min Max

tLOW:SEXT(1) Cumulative clock low extend time (slave device) - 25 ms

tLOW:MEXT(2) Cumulative clock low extend time (master device) - 10 ms
1. tLOW:SEXT is the cumulative time a given slave device is allowed to extend the clock cycles in one message
from the initial START to the STOP. It is possible that, another slave device or the master also extends the
clock causing the combined clock low extend time to be greater than tLOW:SEXT. Therefore, this parameter is
measured with the slave device as the sole target of a full-speed master.
2. tLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a
message as defined from START-to-ACK, ACK-to-ACK, or ACK-to-STOP. It is possible that a slave device
or another master also extends the clock causing the combined clock low time to be greater than tLOW:MEXT
on a given byte. Therefore, this parameter is measured with a full speed slave device as the sole target of
the master.

Figure 206. Timeout intervals for tLOW:SEXT, tLOW:MEXT.

Start Stop
tLOW:SEXT

ClkAck ClkAck
tLOW:MEXT tLOW:MEXT tLOW:MEXT

SMBCLK

SMBDAT

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Bus idle detection

A master can assume that the bus is free if it detects that the clock and data signals have
been high for tIDLE greater than tHIGH,MAX. (refer to Table 104: I2C-SMBus specification data
setup and hold times)
This timing parameter covers the condition where a master has been dynamically added to
the bus and may not have detected a state transition on the SMBCLK or SMBDAT lines. In
this case, the master must wait long enough to ensure that a transfer is not currently in
progress. The peripheral supports a hardware bus idle detection.

23.4.13 SMBus initialization

This section is relevant only when SMBus feature is supported. Refer to Section 23.3: I2C
implementation.
In addition to I2C initialization, some other specific initialization must be done in order to
perform SMBus communication:

Received command and data acknowledge control (Slave mode)

A SMBus receiver must be able to NACK each received command or data. In order to allow
ACK control in slave mode, the Slave byte control mode must be enabled by setting the
SBC bit in the I2C_CR1 register. Refer to Slave byte control mode on page 603 for more
details.

Specific address (Slave mode)

The specific SMBus addresses must be enabled if needed. Refer to Bus idle detection on
page 626 for more details.
• The SMBus device default address (0b1100 001) is enabled by setting the SMBDEN
bit in the I2C_CR1 register.
• The SMBus host address (0b0001 000) is enabled by setting the SMBHEN bit in the
I2C_CR1 register.
• The alert response address (0b0001100) is enabled by setting the ALERTEN bit in the
I2C_CR1 register.

Packet error checking

PEC calculation is enabled by setting the PECEN bit in the I2C_CR1 register. Then the PEC
transfer is managed with the help of a hardware byte counter: NBYTES[7:0] in the I2C_CR2
register. The PECEN bit must be configured before enabling the I2C.
The PEC transfer is managed with the hardware byte counter, so the SBC bit must be set
when interfacing the SMBus in slave mode. The PEC is transferred after NBYTES - 1 data
have been transferred when the PECBYTE bit is set and the RELOAD bit is cleared. If
RELOAD is set, PECBYTE has no effect.
Caution: Changing the PECEN configuration is not allowed when the I2C is enabled.

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Table 110. SMBus with PEC configuration

Mode SBC bit RELOAD bit AUTOEND bit PECBYTE bit

Master Tx/Rx NBYTES + PEC+ STOP x 0 1 1

Master Tx/Rx NBYTES + PEC + ReSTART x 0 0 1
Slave Tx/Rx with PEC 1 0 x 1

Timeout detection
The timeout detection is enabled by setting the TIMOUTEN and TEXTEN bits in the
I2C_TIMEOUTR register. The timers must be programmed in such a way that they detect a
timeout before the maximum time given in the SMBus specification.
• tTIMEOUT check
In order to enable the tTIMEOUT check, the 12-bit TIMEOUTA[11:0] bits must be
programmed with the timer reload value in order to check the tTIMEOUT parameter. The
TIDLE bit must be configured to ‘0’ in order to detect the SCL low level timeout.
Then the timer is enabled by setting the TIMOUTEN in the I2C_TIMEOUTR register.
If SCL is tied low for a time greater than (TIMEOUTA+1) x 2048 x tI2CCLK, the TIMEOUT
flag is set in the I2C_ISR register.
Refer to Table 111: Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tTIMEOUT = 25 ms).
Caution: Changing the TIMEOUTA[11:0] bits and TIDLE bit configuration is not allowed when the
TIMEOUTEN bit is set.
• tLOW:SEXT and tLOW:MEXT check
Depending on if the peripheral is configured as a master or as a slave, The 12-bit
TIMEOUTB timer must be configured in order to check tLOW:SEXT for a slave and
tLOW:MEXT for a master. As the standard specifies only a maximum, the user can choose
the same value for the both.
Then the timer is enabled by setting the TEXTEN bit in the I2C_TIMEOUTR register.
If the SMBus peripheral performs a cumulative SCL stretch for a time greater than
(TIMEOUTB+1) x 2048 x tI2CCLK, and in the timeout interval described in Bus idle
detection on page 626 section, the TIMEOUT flag is set in the I2C_ISR register.
Refer to Table 112: Examples of TIMEOUTB settings for various I2CCLK frequencies
Caution: Changing the TIMEOUTB configuration is not allowed when the TEXTEN bit is set.

Bus idle detection

In order to enable the tIDLE check, the 12-bit TIMEOUTA[11:0] field must be programmed
with the timer reload value in order to obtain the tIDLE parameter. The TIDLE bit must be
configured to ‘1 in order to detect both SCL and SDA high level timeout.
Then the timer is enabled by setting the TIMOUTEN bit in the I2C_TIMEOUTR register.
If both the SCL and SDA lines remain high for a time greater than (TIMEOUTA+1) x 4 x
tI2CCLK, the TIMEOUT flag is set in the I2C_ISR register.
Refer to Table 113: Examples of TIMEOUTA settings for various I2CCLK frequencies (max
tIDLE = 50 µs)

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Caution: Changing the TIMEOUTA and TIDLE configuration is not allowed when the TIMEOUTEN is
set.

23.4.14 SMBus: I2C_TIMEOUTR register configuration examples

This section is relevant only when SMBus feature is supported. Refer to Section 23.3: I2C
implementation.
• Configuring the maximum duration of tTIMEOUT to 25 ms:

Table 111. Examples of TIMEOUTA settings for various I2CCLK frequencies

(max tTIMEOUT = 25 ms)
fI2CCLK TIMEOUTA[11:0] bits TIDLE bit TIMEOUTEN bit tTIMEOUT
8 MHz 0x61 0 1 98 x 2048 x 125 ns = 25 ms
16 MHz 0xC3 0 1 196 x 2048 x 62.5 ns = 25 ms
32 MHz 0x186 0 1 391 x 2048 x 31.25 ns = 25 ms

• Configuring the maximum duration of tLOW:SEXT and tLOW:MEXT to 8 ms:

Table 112. Examples of TIMEOUTB settings for various I2CCLK frequencies

fI2CCLK TIMEOUTB[11:0] bits TEXTEN bit tLOW:EXT
8 MHz 0x1F 1 32 x 2048 x 125 ns = 8 ms
16 MHz 0x3F 1 64 x 2048 x 62.5 ns = 8 ms
32 MHz 0x7C 1 125 x 2048 x 31.25 ns = 8 ms

• Configuring the maximum duration of tIDLE to 50 µs

Table 113. Examples of TIMEOUTA settings for various I2CCLK frequencies

(max tIDLE = 50 µs)
fI2CCLK TIMEOUTA[11:0] bits TIDLE bit TIMEOUTEN bit tTIDLE
8 MHz 0x63 1 1 100 x 4 x 125 ns = 50 µs
16 MHz 0xC7 1 1 200 x 4 x 62.5 ns = 50 µs
32 MHz 0x18F 1 1 400 x 4 x 31.25 ns = 50 µs

23.4.15 SMBus slave mode

This section is relevant only when the SMBus feature is supported. Refer to Section 23.3:
I2C implementation.
In addition to I2C slave transfer management (refer to Section 23.4.9: I2C slave mode)
some additional software flows are provided to support the SMBus.

SMBus slave transmitter

When the IP is used in SMBus, SBC must be programmed to ‘1’ in order to allow the PEC
transmission at the end of the programmed number of data bytes. When the PECBYTE bit
is set, the number of bytes programmed in NBYTES[7:0] includes the PEC transmission. In

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that case the total number of TXIS interrupts is NBYTES - 1 and the content of the
I2C_PECR register is automatically transmitted if the master requests an extra byte after the
NBYTES - 1 data transfer.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

Figure 207. Transfer sequence flow for SMBus slave transmitter N bytes + PEC

SMBus slave
transmission

Slave initialization

No

I2C_ISR.ADDR =
1?

Yes

Read ADDCODE and DIR in I2C_ISR SCL

I2C_CR2.NBYTES = N + 1 stretched
PECBYTE=1
Set I2C_ICR.ADDRCF

No
I2C_ISR.TXIS
=1?

Yes

Write I2C_TXDR.TXDATA

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Figure 208. Transfer bus diagrams for SMBus slave transmitter (SBC=1)
legend:
Example SMBus slave transmitter 2 bytes + PEC,
transmission
ADDR TXIS TXIS reception

S Address A data1 A A PEC NA P

SCL stretch
data2

EV1 EV2 EV3

NBYTES 3

EV1: ADDR ISR: check ADDCODE, program NBYTES=3, set PECBYTE, set ADDRCF
EV2: TXIS ISR: wr data1
EV3: TXIS ISR: wr data2

MS19869V2

SMBus Slave receiver

When the I2C is used in SMBus mode, SBC must be programmed to ‘1’ in order to allow the
PEC checking at the end of the programmed number of data bytes. In order to allow the
ACK control of each byte, the reload mode must be selected (RELOAD=1). Refer to Slave
byte control mode on page 603 for more details.
In order to check the PEC byte, the RELOAD bit must be cleared and the PECBYTE bit
must be set. In this case, after NBYTES - 1 data have been received, the next received byte
is compared with the internal I2C_PECR register content. A NACK is automatically
generated if the comparison does not match, and an ACK is automatically generated if the
comparison matches, whatever the ACK bit value. Once the PEC byte is received, it is
copied into the I2C_RXDR register like any other data, and the RXNE flag is set.
In the case of a PEC mismatch, the PECERR flag is set and an interrupt is generated if the
ERRIE bit is set in the I2C_CR1 register.
If no ACK software control is needed, the user can program PECBYTE=1 and, in the same
write operation, program NBYTES with the number of bytes to be received in a continuous
flow. After NBYTES - 1 are received, the next received byte is checked as being the PEC.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

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Figure 209. Transfer sequence flow for SMBus slave receiver N Bytes + PEC

SMBus slave
reception

Slave initialization

No

I2C_ISR.ADDR =
1?

Yes

Read ADDCODE and DIR in I2C_ISR SCL

I2C_CR2.NBYTES = 1, RELOAD =1 stretched
PECBYTE=1
Set I2C_ICR.ADDRCF

No
I2C_ISR.RXNE =1?
I2C_ISR.TCR = 1?

Yes
Read I2C_RXDR.RXDATA
Program I2C_CR2.NACK = 0
I2C_CR2.NBYTES = 1
N=N-1

No
N = 1?

Yes
Read I2C_RXDR.RXDATA
Program RELOAD = 0
NACK = 0 and NBYTES = 1

No
I2C_ISR.RXNE =1?

Yes
Read I2C_RXDR.RXDATA

End
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Figure 210. Bus transfer diagrams for SMBus slave receiver (SBC=1)
legend:
Example SMBus slave receiver 2 bytes + PEC
transmission
ADDR RXNE RXNE RXNE
reception

S Address A data1 A data2 A PEC A P SCL stretch

EV1 EV2 EV3 EV4

NBYTES 3

EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 3, PECBYTE=1, RELOAD=0, set ADDRCF
EV2: RXNE ISR: rd data1
EV3: RXNE ISR: rd data2
EV4: RXNE ISR: rd PEC

Example SMBus slave receiver 2 bytes + PEC, with ACK control legend :

(RELOAD=1/0) transmission
ADDR RXNE,TCR RXNE,TCR RXNE
reception

S Address A data1 A data2 A PEC A P SCL stretch

EV1 EV2 EV3 EV4

NBYTES 1

EV1: ADDR ISR: check ADDCODE and DIR, program NBYTES = 1, PECBYTE=1, RELOAD=1, set ADDRCF
EV2: RXNE-TCR ISR: rd data1, program NACK=0 and NBYTES = 1
EV3: RXNE-TCR ISR: rd data2, program NACK=0, NBYTES = 1 and RELOAD=0
EV4: RXNE-TCR ISR: rd PEC

MS19870V2

This section is relevant only when the SMBus feature is supported. Refer to Section 23.3:
I2C implementation.
In addition to I2C master transfer management (refer to Section 23.4.10: I2C master mode),
some additional software flows are provided to support the SMBus.

SMBus master transmitter

When the SMBus master wants to transmit the PEC, the PECBYTE bit must be set and the
number of bytes must be programmed in the NBYTES[7:0] field, before setting the START
bit. In this case the total number of TXIS interrupts is NBYTES - 1. So if the PECBYTE bit is
set when NBYTES = 0x1, the content of the I2C_PECR register is automatically transmitted.
If the SMBus master wants to send a STOP condition after the PEC, automatic end mode
must be selected (AUTOEND = 1). In this case, the STOP condition automatically follows
the PEC transmission.

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When the SMBus master wants to send a RESTART condition after the PEC, software
mode must be selected (AUTOEND=0). In this case, once NBYTES - 1 have been
transmitted, the I2C_PECR register content is transmitted and the TC flag is set after the
PEC transmission, stretching the SCL line low. The RESTART condition must be
programmed in the TC interrupt subroutine.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

Figure 211. Bus transfer diagrams for SMBus master transmitter

Example SMBus master transmitter 2 bytes + PEC, automatic end mode (STOP)

TXIS TXIS
legend:

S Address A data1 A data2 A PEC A P transmission

reception
INIT EV1 EV2
SCL stretch
TXE

NBYTES xx 3

INIT: program Slave address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START
EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2

Example SMBus master transmitter 2 bytes + PEC, software end mode (RESTART)

TC legend:
TXIS TXIS
transmission
S Address A data1 A data2 A PEC A Rstart Address
reception

INIT EV1 EV2 EV3 SCL stretch

xx 3 N

NBYTES

INIT: program Slave address, program NBYTES = 3, AUTOEND=0, set PECBYTE, set START
EV1: TXIS ISR: wr data1
EV2: TXIS ISR: wr data2
EV3: TC ISR: program Slave address, program NBYTES = N, set START

MS19871V2

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SMBus master receiver

When the SMBus master wants to receive the PEC followed by a STOP at the end of the
transfer, automatic end mode can be selected (AUTOEND = 1). The PECBYTE bit must be
set and the slave address must be programmed, before setting the START bit. In this case,
after NBYTES - 1 data have been received, the next received byte is automatically checked
versus the I2C_PECR register content. A NACK response is given to the PEC byte, followed
by a STOP condition.
When the SMBus master receiver wants to receive the PEC byte followed by a RESTART
condition at the end of the transfer, software mode must be selected (AUTOEND=0). The
PECBYTE bit must be set and the slave address must be programmed, before setting the
START bit. In this case, after NBYTES - 1 data have been received, the next received byte
is automatically checked versus the I2C_PECR register content. The TC flag is set after the
PEC byte reception, stretching the SCL line low. The RESTART condition can be
programmed in the TC interrupt subroutine.
Caution: The PECBYTE bit has no effect when the RELOAD bit is set.

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Figure 212. Bus transfer diagrams for SMBus master receiver

Example SMBus master receiver 2 bytes + PEC, automatic end mode (STOP)

RXNE RXNE RXNE

legend:

S Address A data1 A data2 A PEC NA P transmission

reception
INIT EV1 EV2 EV3
SCL stretch
NBYTES xx 3

INIT: program Slave address, program NBYTES = 3, AUTOEND=1, set PECBYTE, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: rd PEC

Example SMBus master receiver 2 bytes + PEC, software end mode (RESTART)

RXNE RXNE RXNE TC legend:

transmission
S Address A data1 A data2 A PEC NA Restart Address
reception

INIT EV1 EV2 EV3 EV4 SCL stretch

NBYTES

xx 3 N

INIT: program Slave address, program NBYTES = 3, AUTOEND=0, set PECBYTE, set START
EV1: RXNE ISR: rd data1
EV2: RXNE ISR: rd data2
EV3: RXNE ISR: read PEC
EV4: TC ISR: program Slave address, program NBYTES = N, set START

MS19872V2

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23.4.16 Wakeup from Stop mode on address match

This section is relevant only when wakeup from Stop mode feature is supported. Refer to
Section 23.3: I2C implementation.
The I2C is able to wakeup the MCU from Stop mode (APB clock is off), when it is
addressed. All addressing modes are supported.
Wakeup from Stop mode is enabled by setting the WUPEN bit in the I2C_CR1 register. The
HSI16 oscillator must be selected as the clock source for I2CCLK in order to allow wakeup
from Stop mode.
During Stop mode, the HSI16 is switched off. When a START is detected, the I2C interface
switches the HSI16 on, and stretches SCL low until HSI16 is woken up.
HSI16 is then used for the address reception.
In case of an address match, the I2C stretches SCL low during MCU wakeup time. The
stretch is released when ADDR flag is cleared by software, and the transfer goes on
normally.
If the address does not match, the HSI16 is switched off again and the MCU is not woken
up.
Note: If the I2C clock is the system clock, or if WUPEN = 0, the HSI16 is not switched on after a
START is received.
Only an ADDR interrupt can wakeup the MCU. Therefore do not enter Stop mode when the
I2C is performing a transfer as a master, or as an addressed slave after the ADDR flag is
set. This can be managed by clearing SLEEPDEEP bit in the ADDR interrupt routine and
setting it again only after the STOPF flag is set.
Caution: The digital filter is not compatible with the wakeup from Stop mode feature. If the DNF bit is
not equal to 0, setting the WUPEN bit has no effect.
Caution: This feature is available only when the I2C clock source is the HSI16 oscillator.
Caution: Clock stretching must be enabled (NOSTRETCH = 0) to ensure proper operation of the
wakeup from Stop mode feature.
Caution: If wakeup from Stop mode is disabled (WUPEN = 0), the I2C peripheral must be disabled
before entering Stop mode (PE = 0).

23.4.17 Error conditions

The following errors are the error conditions which may cause communication to fail.

Bus error (BERR)

A bus error is detected when a START or a STOP condition is detected and is not located
after a multiple of 9 SCL clock pulses. A START or a STOP condition is detected when a
SDA edge occurs while SCL is high.
The bus error flag is set only if the I2C is involved in the transfer as master or addressed
slave (i.e not during the address phase in slave mode).
In case of a misplaced START or RESTART detection in slave mode, the I2C enters
address recognition state like for a correct START condition.
When a bus error is detected, the BERR flag is set in the I2C_ISR register, and an interrupt
is generated if the ERRIE bit is set in the I2C_CR1 register.

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Arbitration lost (ARLO)

An arbitration loss is detected when a high level is sent on the SDA line, but a low level is
sampled on the SCL rising edge.
• In master mode, arbitration loss is detected during the address phase, data phase and
data acknowledge phase. In this case, the SDA and SCL lines are released, the
START control bit is cleared by hardware and the master switches automatically to
slave mode.
• In slave mode, arbitration loss is detected during data phase and data acknowledge
phase. In this case, the transfer is stopped, and the SCL and SDA lines are released.
When an arbitration loss is detected, the ARLO flag is set in the I2C_ISR register, and an
interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Overrun/underrun error (OVR)

An overrun or underrun error is detected in slave mode when NOSTRETCH = 1 and:
• In reception when a new byte is received and the RXDR register has not been read yet.
The new received byte is lost, and a NACK is automatically sent as a response to the
new byte.
• In transmission:
– When STOPF=1 and the first data byte should be sent. The content of the
I2C_TXDR register is sent if TXE=0, 0xFF if not.
– When a new byte must be sent and the I2C_TXDR register has not been written
yet, 0xFF is sent.
When an overrun or underrun error is detected, the OVR flag is set in the I2C_ISR register,
and an interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Packet error checking error (PECERR)

This section is relevant only when the SMBus feature is supported. Refer to Section 23.3:
I2C implementation.
A PEC error is detected when the received PEC byte does not match with the I2C_PECR
register content. A NACK is automatically sent after the wrong PEC reception.
When a PEC error is detected, the PECERR flag is set in the I2C_ISR register, and an
interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Timeout Error (TIMEOUT)

This section is relevant only when the SMBus feature is supported. Refer to Section 23.3:
I2C implementation.
A timeout error occurs for any of these conditions:
• TIDLE=0 and SCL remained low for the time defined in the TIMEOUTA[11:0] bits: this is
used to detect a SMBus timeout.
• TIDLE=1 and both SDA and SCL remained high for the time defined in the TIMEOUTA
[11:0] bits: this is used to detect a bus idle condition.
• Master cumulative clock low extend time reached the time defined in the
TIMEOUTB[11:0] bits (SMBus tLOW:MEXT parameter)
• Slave cumulative clock low extend time reached the time defined in TIMEOUTB[11:0]
bits (SMBus tLOW:SEXT parameter)

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When a timeout violation is detected in master mode, a STOP condition is automatically

sent.
When a timeout violation is detected in slave mode, SDA and SCL lines are automatically
released.
When a timeout error is detected, the TIMEOUT flag is set in the I2C_ISR register, and an
interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

Alert (ALERT)
This section is relevant only when the SMBus feature is supported. Refer to Section 23.3:
I2C implementation.
The ALERT flag is set when the I2C interface is configured as a Host (SMBHEN=1), the
alert pin detection is enabled (ALERTEN=1) and a falling edge is detected on the SMBA pin.
An interrupt is generated if the ERRIE bit is set in the I2C_CR1 register.

23.4.18 DMA requests

Transmission using DMA
DMA (direct memory access) can be enabled for transmission by setting the TXDMAEN bit
in the I2C_CR1 register. Data is loaded from an SRAM area configured using the DMA
peripheral (see Section 11: Direct memory access controller (DMA) on page 361) to the
I2C_TXDR register whenever the TXIS bit is set.
Only the data are transferred with DMA.
• In master mode: the initialization, the slave address, direction, number of bytes and
START bit are programmed by software (the transmitted slave address cannot be
transferred with DMA). When all data are transferred using DMA, the DMA must be
initialized before setting the START bit. The end of transfer is managed with the
NBYTES counter. Refer to Master transmitter on page 614.
For code example refer to A.14.8: I2C configured in master mode to transmit with DMA code
example.
• In slave mode:
– With NOSTRETCH = 0, when all data are transferred using DMA, the DMA must
be initialized before the address match event, or in ADDR interrupt subroutine,
before clearing ADDR.
– With NOSTRETCH = 1, the DMA must be initialized before the address match
event.
• For instances supporting SMBus: the PEC transfer is managed with NBYTES counter.
Refer to SMBus slave transmitter on page 628 and SMBus master transmitter on
page 632.
Note: If DMA is used for transmission, the TXIE bit does not need to be enabled.

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Reception using DMA

DMA (direct memory access) can be enabled for reception by setting the RXDMAEN bit in
the I2C_CR1 register. Data is loaded from the I2C_RXDR register to an SRAM area
configured using the DMA peripheral (refer to Section 10: Direct memory access controller
(DMA) on page 241) whenever the RXNE bit is set. Only the data (including PEC) are
transferred with DMA.
• In Master mode, the initialization, the slave address, direction, number of bytes and
START bit are programmed by software. When all data are transferred using DMA, the
DMA must be initialized before setting the START bit. The end of transfer is managed
with the NBYTES counter. For code example refer to A.14.9: I2C configured in slave
mode to receive with DMA code example.
• In Slave mode with NOSTRETCH = 0, when all data are transferred using DMA, the
DMA must be initialized before the address match event, or in the ADDR interrupt
subroutine, before clearing the ADDR flag.
• If SMBus is supported (see Section 23.3: I2C implementation): the PEC transfer is
managed with the NBYTES counter. Refer to SMBus Slave receiver on page 630 and
SMBus master receiver on page 634.
Note: If DMA is used for reception, the RXIE bit does not need to be enabled.

23.4.19 Debug mode

When the microcontroller enters debug mode (core halted), the SMBus timeout either
continues to work normally or stops, depending on the DBG_I2Cx_SMBUS_TIMEOUT
configuration bits in the DBG module.

23.5 I2C low-power modes

Table 114. Effect of low-power modes on the I2C
Mode Description

Sleep No effect. I2C interrupts cause the device to exit the Sleep mode.
The I2C registers content is kept. If WUPEN = 1 and I2C is clocked by an internal
oscillator (HSI16): the address recognition is functional. The I2C address match
Stop(1)
condition causes the device to exit the Stop mode. If WUPEN=0: the I2C must be
disabled before entering Stop mode
The I2C peripheral is powered down and must be reinitialized after exiting
Standby
Standby mode.
1. Refer to Section 23.3: I2C implementation for information about the Stop modes supported by each
instance. If wakeup from a specific Stop mode is not supported, the instance must be disabled before
entering this Stop mode.

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23.6 I2C interrupts

The table below gives the list of I2C interrupt requests.

Table 115. I2C Interrupt requests

Exit the Exit the Exit the
Interrupt Interrupt Event Enable Interrupt clear
Sleep Stop Standby
acronym event flag control bit method
mode mode mode

Receive buffer Read I2C_RXDR

RXNE RXIE
not empty register
Transmit buffer Write I2C_TXDR
TXIS TXIE
interrupt status register
Stop detection Write
STOPF STOPIE
interrupt flag STOPCF=1
Transfer Write I2C_CR2
complete TCR with No
reload TCIE NBYTES[7:0] ≠ 0
Yes
I2C_EV Transfer Write START=1 No
TC
complete or STOP=1
Address Write
ADDR ADDRIE Yes(1)
matched ADDRCF=1
NACK Write
NACKF NACKIE No
reception NACKCF=1
I2C Write
Bus error BERR
BERRCF=1
Write
Arbitration loss ARLO
ARLOCF=1
Overrun/
OVR Write OVRCF=1
Underrun
I2C_ER ERRIE Yes No No
Write
PEC error PECERR
PECERRCF=1
Timeout/ Write
TIMEOUT
tLOW error TIMEOUTCF=1
Write
SMBus alert ALERT
ALERTCF=1
1. The ADDR match event can wake up the device from Stop mode only if the I2C instance supports the Wakeup from Stop
mode feature. Refer to Section 23.3: I2C implementation.

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23.7 I2C registers

Refer to Section 1.2 on page 45 for a list of abbreviations used in register descriptions.
The peripheral registers are accessed by words (32-bit).

23.7.1 I2C control register 1 (I2C_CR1)

Address offset: 0x00
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to
2 x PCLK1 + 6 x I2CCLK.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ALERT SMBD SMBH WUPE NOSTR
Res. Res. Res. Res. Res. Res. Res. Res. PECEN GCEN SBC
EN EN EN N ETCH

rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXDMA TXDMA ANF STOP NACK ADDR
Res. DNF[3:0] ERRIE TCIE RXIE TXIE PE
EN EN OFF IE IE IE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 PECEN: PEC enable
0: PEC calculation disabled
1: PEC calculation enabled
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 23.3: I2C implementation.
Bit 22 ALERTEN: SMBus alert enable
0: The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode
(SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled
(0001100x followed by NACK).
1: The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode
(SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is
enabled (0001100x followed by ACK).
Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 23.3: I2C implementation.
Bit 21 SMBDEN: SMBus device default address enable
0: Device default address disabled. Address 0b1100001x is NACKed.
1: Device default address enabled. Address 0b1100001x is ACKed.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 23.3: I2C implementation.
Bit 20 SMBHEN: SMBus host address enable
0: Host address disabled. Address 0b0001000x is NACKed.
1: Host address enabled. Address 0b0001000x is ACKed.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 23.3: I2C implementation.

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Bit 19 GCEN: General call enable

0: General call disabled. Address 0b00000000 is NACKed.
1: General call enabled. Address 0b00000000 is ACKed.
Bit 18 WUPEN: Wakeup from Stop mode enable
0: Wakeup from Stop mode disable.
1: Wakeup from Stop mode enable.
Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced
by hardware to ‘0’. Refer to Section 23.3: I2C implementation.
Note: WUPEN can be set only when DNF = ‘0000’
Bit 17 NOSTRETCH: Clock stretching disable
This bit is used to disable clock stretching in slave mode. It must be kept cleared in master
mode.
0: Clock stretching enabled
1: Clock stretching disabled
Note: This bit can only be programmed when the I2C is disabled (PE = 0).
Bit 16 SBC: Slave byte control
This bit is used to enable hardware byte control in slave mode.
0: Slave byte control disabled
1: Slave byte control enabled
Bit 15 RXDMAEN: DMA reception requests enable
0: DMA mode disabled for reception
1: DMA mode enabled for reception
Bit 14 TXDMAEN: DMA transmission requests enable
0: DMA mode disabled for transmission
1: DMA mode enabled for transmission
Bit 13 Reserved, must be kept at reset value.
Bit 12 ANFOFF: Analog noise filter OFF
0: Analog noise filter enabled
1: Analog noise filter disabled
Note: This bit can only be programmed when the I2C is disabled (PE = 0).
Bits 11:8 DNF[3:0]: Digital noise filter
These bits are used to configure the digital noise filter on SDA and SCL input. The digital
filter, filters spikes with a length of up to DNF[3:0] * tI2CCLK
0000: Digital filter disabled
0001: Digital filter enabled and filtering capability up to 1 tI2CCLK
...
1111: digital filter enabled and filtering capability up to15 tI2CCLK
Note: If the analog filter is also enabled, the digital filter is added to the analog filter.
This filter can only be programmed when the I2C is disabled (PE = 0).

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Bit 7 ERRIE: Error interrupts enable

0: Error detection interrupts disabled
1: Error detection interrupts enabled
Note: Any of these errors generate an interrupt:
Arbitration Loss (ARLO)
Bus Error detection (BERR)
Overrun/Underrun (OVR)
Timeout detection (TIMEOUT)
PEC error detection (PECERR)
Alert pin event detection (ALERT)
Bit 6 TCIE: Transfer Complete interrupt enable
0: Transfer Complete interrupt disabled
1: Transfer Complete interrupt enabled
Note: Any of these events generate an interrupt:
Transfer Complete (TC)
Transfer Complete Reload (TCR)
Bit 5 STOPIE: Stop detection Interrupt enable
0: Stop detection (STOPF) interrupt disabled
1: Stop detection (STOPF) interrupt enabled
Bit 4 NACKIE: Not acknowledge received Interrupt enable
0: Not acknowledge (NACKF) received interrupts disabled
1: Not acknowledge (NACKF) received interrupts enabled
Bit 3 ADDRIE: Address match Interrupt enable (slave only)
0: Address match (ADDR) interrupts disabled
1: Address match (ADDR) interrupts enabled
Bit 2 RXIE: RX Interrupt enable
0: Receive (RXNE) interrupt disabled
1: Receive (RXNE) interrupt enabled
Bit 1 TXIE: TX Interrupt enable
0: Transmit (TXIS) interrupt disabled
1: Transmit (TXIS) interrupt enabled
Bit 0 PE: Peripheral enable
0: Peripheral disable
1: Peripheral enable
Note: When PE = 0, the I2C SCL and SDA lines are released. Internal state machines and
status bits are put back to their reset value. When cleared, PE must be kept low for at
least 3 APB clock cycles.

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23.7.2 I2C control register 2 (I2C_CR2)

Address offset: 0x04
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
I2CCLK.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PEC AUTOE RE
Res. Res. Res. Res. Res. NBYTES[7:0]
BYTE ND LOAD

rs rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HEAD1 RD_
NACK STOP START ADD10 SADD[9:0]
0R WRN
rs rs rs rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 PECBYTE: Packet error checking byte
This bit is set by software, and cleared by hardware when the PEC is transferred, or when a
STOP condition or an Address matched is received, also when PE = 0.
0: No PEC transfer.
1: PEC transmission/reception is requested
Note: Writing ‘0’ to this bit has no effect.
This bit has no effect when RELOAD is set.
This bit has no effect is slave mode when SBC=0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 23.3: I2C implementation.
Bit 25 AUTOEND: Automatic end mode (master mode)
This bit is set and cleared by software.
0: software end mode: TC flag is set when NBYTES data are transferred, stretching SCL low.
1: Automatic end mode: a STOP condition is automatically sent when NBYTES data are
transferred.
Note: This bit has no effect in slave mode or when the RELOAD bit is set.
Bit 24 RELOAD: NBYTES reload mode
This bit is set and cleared by software.
0: The transfer is completed after the NBYTES data transfer (STOP or RESTART follows).
1: The transfer is not completed after the NBYTES data transfer (NBYTES is reloaded). TCR
flag is set when NBYTES data are transferred, stretching SCL low.
Bits 23:16 NBYTES[7:0]: Number of bytes
The number of bytes to be transmitted/received is programmed there. This field is don’t care
in slave mode with SBC=0.
Note: Changing these bits when the START bit is set is not allowed.

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Bit 15 NACK: NACK generation (slave mode)

The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP
condition or an Address matched is received, or when PE = 0.
0: an ACK is sent after current received byte.
1: a NACK is sent after current received byte.
Note: Writing ‘0’ to this bit has no effect.
This bit is used in slave mode only: in master receiver mode, NACK is automatically
generated after last byte preceding STOP or RESTART condition, whatever the NACK
bit value.
When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is
automatically generated whatever the NACK bit value.
When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value
does not depend on the NACK value.
Bit 14 STOP: Stop generation (master mode)
The bit is set by software, cleared by hardware when a STOP condition is detected, or when
PE = 0.
In Master Mode:
0: No Stop generation.
1: Stop generation after current byte transfer.
Note: Writing ‘0’ to this bit has no effect.
Bit 13 START: Start generation
This bit is set by software, and cleared by hardware after the Start followed by the address
sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can
also be cleared by software by writing ‘1’ to the ADDRCF bit in the I2C_ICR register.
0: No Start generation.
1: Restart/Start generation:
If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a
Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer.
Otherwise setting this bit generates a START condition once the bus is free.
Note: Writing ‘0’ to this bit has no effect.
The START bit can be set even if the bus is BUSY or I2C is in slave mode.
This bit has no effect when RELOAD is set.
Bit 12 HEAD10R: 10-bit address header only read direction (master receiver mode)
0: The master sends the complete 10 bit slave address read sequence: Start + 2 bytes 10bit
address in write direction + Restart + 1st 7 bits of the 10 bit address in read direction.
1: The master only sends the 1st 7 bits of the 10 bit address, followed by Read direction.
Note: Changing this bit when the START bit is set is not allowed.
Bit 11 ADD10: 10-bit addressing mode (master mode)
0: The master operates in 7-bit addressing mode,
1: The master operates in 10-bit addressing mode
Note: Changing this bit when the START bit is set is not allowed.
Bit 10 RD_WRN: Transfer direction (master mode)
0: Master requests a write transfer.
1: Master requests a read transfer.
Note: Changing this bit when the START bit is set is not allowed.

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Bits 9:0 SADD[9:0]: Slave address (master mode)

In 7-bit addressing mode (ADD10 = 0):
SADD[7:1] should be written with the 7-bit slave address to be sent. The bits SADD[9],
SADD[8] and SADD[0] are don't care.
In 10-bit addressing mode (ADD10 = 1):
SADD[9:0] should be written with the 10-bit slave address to be sent.
Note: Changing these bits when the START bit is set is not allowed.

23.7.3 I2C own address 1 register (I2C_OAR1)

Address offset: 0x08
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
I2CCLK.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA1
OA1EN Res. Res. Res. Res. OA1[9:0]
MODE

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 OA1EN: Own Address 1 enable
0: Own address 1 disabled. The received slave address OA1 is NACKed.
1: Own address 1 enabled. The received slave address OA1 is ACKed.
Bits 14:11 Reserved, must be kept at reset value.
Bit 10 OA1MODE: Own Address 1 10-bit mode
0: Own address 1 is a 7-bit address.
1: Own address 1 is a 10-bit address.
Note: This bit can be written only when OA1EN=0.
Bits 9:0 OA1[9:0]: Interface own slave address
7-bit addressing mode: OA1[7:1] contains the 7-bit own slave address. The bits OA1[9],
OA1[8] and OA1[0] are don't care.
10-bit addressing mode: OA1[9:0] contains the 10-bit own slave address.
Note: These bits can be written only when OA1EN=0.

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23.7.4 I2C own address 2 register (I2C_OAR2)

Address offset: 0x0C
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
I2CCLK.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OA2EN Res. Res. Res. Res. OA2MSK[2:0] OA2[7:1] Res.

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 OA2EN: Own Address 2 enable
0: Own address 2 disabled. The received slave address OA2 is NACKed.
1: Own address 2 enabled. The received slave address OA2 is ACKed.
Bits 14:11 Reserved, must be kept at reset value.
Bits 10:8 OA2MSK[2:0]: Own Address 2 masks
000: No mask
001: OA2[1] is masked and don’t care. Only OA2[7:2] are compared.
010: OA2[2:1] are masked and don’t care. Only OA2[7:3] are compared.
011: OA2[3:1] are masked and don’t care. Only OA2[7:4] are compared.
100: OA2[4:1] are masked and don’t care. Only OA2[7:5] are compared.
101: OA2[5:1] are masked and don’t care. Only OA2[7:6] are compared.
110: OA2[6:1] are masked and don’t care. Only OA2[7] is compared.
111: OA2[7:1] are masked and don’t care. No comparison is done, and all (except reserved)
7-bit received addresses are acknowledged.
Note: These bits can be written only when OA2EN=0.
As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and
0b1111xxx) are not acknowledged even if the comparison matches.
Bits 7:1 OA2[7:1]: Interface address
7-bit addressing mode: 7-bit address
Note: These bits can be written only when OA2EN=0.
Bit 0 Reserved, must be kept at reset value.

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23.7.5 I2C timing register (I2C_TIMINGR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: No wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PRESC[3:0] Res. Res. Res. Res. SCLDEL[3:0] SDADEL[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCLH[7:0] SCLL[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 PRESC[3:0]: Timing prescaler

This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for
data setup and hold counters (refer to I2C timings on page 595) and for SCL high and low
level counters (refer to I2C master initialization on page 610).
tPRESC = (PRESC+1) x tI2CCLK
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:20 SCLDEL[3:0]: Data setup time
This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In
master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during
tSCLDEL.
tSCLDEL = (SCLDEL+1) x tPRESC
Note: tSCLDEL is used to generate tSU:DAT timing.
Bits 19:16 SDADEL[3:0]: Data hold time
This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In
master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during
tSDADEL.
tSDADEL= SDADEL x tPRESC
Note: SDADEL is used to generate tHD:DAT timing.
Bits 15:8 SCLH[7:0]: SCL high period (master mode)
This field is used to generate the SCL high period in master mode.
tSCLH = (SCLH+1) x tPRESC
Note: SCLH is also used to generate tSU:STO and tHD:STA timing.
Bits 7:0 SCLL[7:0]: SCL low period (master mode)
This field is used to generate the SCL low period in master mode.
tSCLL = (SCLL+1) x tPRESC
Note: SCLL is also used to generate tBUF and tSU:STA timings.

Note: This register must be configured when the I2C is disabled (PE = 0).
Note: The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
Configuration window.

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23.7.6 I2C timeout register (I2C_TIMEOUTR)

Address offset: 0x14
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x
I2CCLK.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEXTEN Res. Res. Res. TIMEOUTB[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIMOUTEN Res. Res. TIDLE TIMEOUTA[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 TEXTEN: Extended clock timeout enable

0: Extended clock timeout detection is disabled
1: Extended clock timeout detection is enabled. When a cumulative SCL stretch for more
than tLOW:EXT is done by the I2C interface, a timeout error is detected (TIMEOUT=1).
Bits 30:28 Reserved, must be kept at reset value.
Bits 27:16 TIMEOUTB[11:0]: Bus timeout B
This field is used to configure the cumulative clock extension timeout:
In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected
In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected
tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK
Note: These bits can be written only when TEXTEN=0.
Bit 15 TIMOUTEN: Clock timeout enable
0: SCL timeout detection is disabled
1: SCL timeout detection is enabled: when SCL is low for more than tTIMEOUT (TIDLE=0) or
high for more than tIDLE (TIDLE=1), a timeout error is detected (TIMEOUT=1).
Bits 14:13 Reserved, must be kept at reset value.
Bit 12 TIDLE: Idle clock timeout detection
0: TIMEOUTA is used to detect SCL low timeout
1: TIMEOUTA is used to detect both SCL and SDA high timeout (bus idle condition)
Note: This bit can be written only when TIMOUTEN=0.
Bits 11:0 TIMEOUTA[11:0]: Bus Timeout A
This field is used to configure:
The SCL low timeout condition tTIMEOUT when TIDLE=0
tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK
The bus idle condition (both SCL and SDA high) when TIDLE=1
tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK
Note: These bits can be written only when TIMOUTEN=0.

Note: If the SMBus feature is not supported, this register is reserved and forced by hardware to
“0x00000000”. Refer to Section 23.3: I2C implementation.

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23.7.7 I2C interrupt and status register (I2C_ISR)

Address offset: 0x18
Reset value: 0x0000 0001
Access: No wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. ADDCODE[6:0] DIR

r r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TIME PEC
BUSY Res. ALERT OVR ARLO BERR TCR TC STOPF NACKF ADDR RXNE TXIS TXE
OUT ERR

r r r r r r r r r r r r r rs rs

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:17 ADDCODE[6:0]: Address match code (Slave mode)
These bits are updated with the received address when an address match event occurs
(ADDR = 1).
In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2
MSBs of the address.
Bit 16 DIR: Transfer direction (Slave mode)
This flag is updated when an address match event occurs (ADDR = 1).
0: Write transfer, slave enters receiver mode.
1: Read transfer, slave enters transmitter mode.
Bit 15 BUSY: Bus busy
This flag indicates that a communication is in progress on the bus. It is set by hardware
when a START condition is detected. It is cleared by hardware when a STOP condition is
detected, or when PE = 0.
Bit 14 Reserved, must be kept at reset value.
Bit 13 ALERT: SMBus alert
This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1
and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by
setting the ALERTCF bit.
Note: This bit is cleared by hardware when PE = 0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 23.3: I2C implementation.
Bit 12 TIMEOUT: Timeout or tLOW detection flag
This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared
by software by setting the TIMEOUTCF bit.
Note: This bit is cleared by hardware when PE = 0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 23.3: I2C implementation.

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Bit 11 PECERR: PEC Error in reception

This flag is set by hardware when the received PEC does not match with the PEC register
content. A NACK is automatically sent after the wrong PEC reception. It is cleared by
software by setting the PECCF bit.
Note: This bit is cleared by hardware when PE = 0.
If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 23.3: I2C implementation.
Bit 10 OVR: Overrun/Underrun (slave mode)
This flag is set by hardware in slave mode with NOSTRETCH = 1, when an
overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit.
Note: This bit is cleared by hardware when PE = 0.
Bit 9 ARLO: Arbitration lost
This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the
ARLOCF bit.
Note: This bit is cleared by hardware when PE = 0.
Bit 8 BERR: Bus error
This flag is set by hardware when a misplaced Start or STOP condition is detected whereas
the peripheral is involved in the transfer. The flag is not set during the address phase in slave
mode. It is cleared by software by setting BERRCF bit.
Note: This bit is cleared by hardware when PE = 0.
Bit 7 TCR: Transfer Complete Reload
This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is
cleared by software when NBYTES is written to a non-zero value.
Note: This bit is cleared by hardware when PE = 0.
This flag is only for master mode, or for slave mode when the SBC bit is set.
Bit 6 TC: Transfer Complete (master mode)
This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been
transferred. It is cleared by software when START bit or STOP bit is set.
Note: This bit is cleared by hardware when PE = 0.
Bit 5 STOPF: Stop detection flag
This flag is set by hardware when a STOP condition is detected on the bus and the
peripheral is involved in this transfer:
– either as a master, provided that the STOP condition is generated by the peripheral.
– or as a slave, provided that the peripheral has been addressed previously during
this transfer.
It is cleared by software by setting the STOPCF bit.
Note: This bit is cleared by hardware when PE = 0.
Bit 4 NACKF: Not Acknowledge received flag
This flag is set by hardware when a NACK is received after a byte transmission. It is cleared
by software by setting the NACKCF bit.
Note: This bit is cleared by hardware when PE = 0.
Bit 3 ADDR: Address matched (slave mode)
This bit is set by hardware as soon as the received slave address matched with one of the
enabled slave addresses. It is cleared by software by setting ADDRCF bit.
Note: This bit is cleared by hardware when PE = 0.

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Bit 2 RXNE: Receive data register not empty (receivers)

This bit is set by hardware when the received data is copied into the I2C_RXDR register, and
is ready to be read. It is cleared when I2C_RXDR is read.
Note: This bit is cleared by hardware when PE = 0.
Bit 1 TXIS: Transmit interrupt status (transmitters)
This bit is set by hardware when the I2C_TXDR register is empty and the data to be
transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be
sent is written in the I2C_TXDR register.
This bit can be written to ‘1’ by software when NOSTRETCH = 1 only, in order to generate a
TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN = 1).
Note: This bit is cleared by hardware when PE = 0.
Bit 0 TXE: Transmit data register empty (transmitters)
This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next
data to be sent is written in the I2C_TXDR register.
This bit can be written to ‘1’ by software in order to flush the transmit data register
I2C_TXDR.
Note: This bit is set by hardware when PE = 0.

23.7.8 I2C interrupt clear register (I2C_ICR)

Address offset: 0x1C
Reset value: 0x0000 0000
Access: No wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ALERT TIMOU ARLOC BERRC STOPC NACKC ADDR
Res. Res. PECCF OVRCF Res. Res. Res. Res. Res.
CF TCF F F F F CF

w w w w w w w w w

Bits 31:14 Reserved, must be kept at reset value.

Bit 13 ALERTCF: Alert flag clear
Writing 1 to this bit clears the ALERT flag in the I2C_ISR register.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 23.3: I2C implementation.
Bit 12 TIMOUTCF: Timeout detection flag clear
Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 23.3: I2C implementation.
Bit 11 PECCF: PEC Error flag clear
Writing 1 to this bit clears the PECERR flag in the I2C_ISR register.
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to ‘0’.
Refer to Section 23.3: I2C implementation.

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Bit 10 OVRCF: Overrun/Underrun flag clear

Writing 1 to this bit clears the OVR flag in the I2C_ISR register.
Bit 9 ARLOCF: Arbitration lost flag clear
Writing 1 to this bit clears the ARLO flag in the I2C_ISR register.
Bit 8 BERRCF: Bus error flag clear
Writing 1 to this bit clears the BERRF flag in the I2C_ISR register.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 STOPCF: STOP detection flag clear
Writing 1 to this bit clears the STOPF flag in the I2C_ISR register.
Bit 4 NACKCF: Not Acknowledge flag clear
Writing 1 to this bit clears the NACKF flag in I2C_ISR register.
Bit 3 ADDRCF: Address matched flag clear
Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also
clears the START bit in the I2C_CR2 register.
Bits 2:0 Reserved, must be kept at reset value.

23.7.9 I2C PEC register (I2C_PECR)

Address offset: 0x20
Reset value: 0x0000 0000
Access: No wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. PEC[7:0]

r r r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 PEC[7:0]: Packet error checking register
This field contains the internal PEC when PECEN=1.
The PEC is cleared by hardware when PE = 0.

Note: If the SMBus feature is not supported, this register is reserved and forced by hardware to
“0x00000000”. Refer to Section 23.3: I2C implementation.

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23.7.10 I2C receive data register (I2C_RXDR)

Address offset: 0x24
Reset value: 0x0000 0000
Access: No wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. RXDATA[7:0]

r r r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 RXDATA[7:0]: 8-bit receive data
Data byte received from the I2C bus

23.7.11 I2C transmit data register (I2C_TXDR)

Address offset: 0x28
Reset value: 0x0000 0000
Access: No wait states

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. TXDATA[7:0]

rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 TXDATA[7:0]: 8-bit transmit data
Data byte to be transmitted to the I2C bus
Note: These bits can be written only when TXE = 1.

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 0x8
0x4
0x0

0xC

0x24
0x20
0x18
0x14
0x10

0x1C
Offset
RM0377

23.7.12

I2C_
I2C_
name

I2C_ISR

I2C_ICR
I2C_CR2
I2C_CR1

TIMINGR

I2C_PECR
I2C_OAR2
I2C_OAR1

I2C_RXDR
Register

TIMEOUTR

Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

0
0
Res. Res. Res. Res. TEXTEN Res. Res. Res. Res. 31

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
PRESC[3:0]
Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
I2C register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
Res. Res. Res. Res. Res. Res. Res. PECBYTE Res. 26

0
0
Res. Res. Res. Res. Res. Res. Res. AUTOEND Res. 25

0
0
Res. Res. Res. Res. Res. Res. Res. RELOAD Res. 24

0
0
0
0
0

Res. Res. Res. Res. Res. PECEN 23

0
0
0
0
0

Res. Res. Res. Res. Res. ALERTEN 22

[3:0]

0
0
0
0
0

Res. Res. Res. Res. Res. SMBDEN 21

SCLDEL

0
0
0
0
0

Res. Res. Res. Res. Res. SMBHEN 20

TIMEOUTB[11:0]

0
0
0
0
0

Res. Res. Res. Res. Res. GCEN 19

ADDCODE[6:0]

0
0
0
0
0

NBYTES[7:0]

Res. Res. Res. Res. Res. WUPEN 18

[3:0]

0
0
0
0
0

RM0377 Rev 10
Res. Res. Res. Res. Res. NOSTRETCH 17

SDADEL

0
0
0
0
0

Res. Res. Res. DIR Res. Res. SBC 16

0
0

0
0
0
0
0

Res. Res. Res. BUSY TIMOUTEN OA2EN OA1EN NACK RXDMAEN 15

0
0
0

Res. Res. Res. Res. Res. Res. Res. STOP TXDMAEN 14

0
0
0

0
Res. Res. ALERTCF ALERT Res. Res. Res. START Res. 13

0
0
0
0
0

0
Res. Res. TIMOUTCF TIMEOUT TIDLE Res. Res. HEAD10R ANFOFF 12

0
0
0
0
0

0
Res. Res. PECCF PECERR Res. Res. ADD10 11
Table 116. I2C register map and reset values

SCLH[7:0]

0
0
0
0
0
0
0

0
The table below provides the I2C register map and reset values.

Res. Res. OVRCF OVR OA1MODE RD_WRN 10

0
0
0
0
0
0
0

0
Res. Res. ARLOCF ARLO 9
DNF[3:0]

K [2:0]
OA2MS

0
0
0
0
0
0
0

0
Res. Res. BERRCF BERR 8

0
0
0
0
0
0
0

0
0
Res. TCR ERRIE 7

0
0
0
0
0
0
0

0
0
Res. TC TCIE 6

0
0
0
0
0
0
0

0
0
0
STOPCF STOPF STOPIE 5

0
0
0
0
0
0
0

0
0
0
NACKCF NACKF NACKIE 4
OA1[9:0]

TIMEOUTA[11:0]
SADD[9:0]

OA2[7:1]

0
0
0
0
0
0
0

0
0
0
ADDRCF ADDR ADDRIE 3

PEC[7:0]
SCLL[7:0]

0
0
0
0
0
0
0

0
0

RXDATA[7:0]
Res. RXNE RXIE 2

0
0
0
0
0
0
0

0
0
Res. TXIS TXIE 1

1
0
0
0
0
0

0
0
0

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Res. TXE Res. PE

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Inter-integrated circuit (I2C) interface RM0377

Table 116. I2C register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
I2C_TXDR TXDATA[7:0]
0x28

Reset value 0 0 0 0 0 0 0 0

Refer to Section 2.2 on page 51 for the register boundary addresses.

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24 Universal synchronous/asynchronous receiver

transmitter (USART/UART)

24.1 Introduction
The universal synchronous asynchronous receiver transmitter (USART) offers a flexible
means of Full-duplex data exchange with external equipment requiring an industry standard
NRZ asynchronous serial data format. The USART offers a very wide range of baud rates
using a programmable baud rate generator.
It supports synchronous one-way communication and Half-duplex Single-wire
communication, as well as multiprocessor communications. It also supports the LIN (Local
Interconnect Network), Smartcard protocol and IrDA (Infrared Data Association) SIR
ENDEC specifications and Modem operations (CTS/RTS).
High speed data communication is possible by using the DMA (direct memory access) for
multibuffer configuration.

24.2 USART main features

• Full-duplex asynchronous communications
• NRZ standard format (mark/space)
• Configurable oversampling method by 16 or 8 to give flexibility between speed and
clock tolerance
• A common programmable transmit and receive baud rate of up to 4 Mbit/s when the
clock frequency is 32 MHz and oversampling is by 8
• Dual clock domain allowing:
– USART functionality and wakeup from Stop mode
– Convenient baud rate programming independent from the PCLK reprogramming
• Auto baud rate detection
• Programmable data word length (7, 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Synchronous mode and clock output for synchronous communications
• Single-wire Half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver

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• Communication control/error detection flags

• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Fourteen interrupt sources with flags
• Multiprocessor communications
The USART enters Mute mode if the address does not match.
• Wakeup from Mute mode (by idle line detection or address mark detection)

24.3 USART extended features

• LIN master synchronous break send capability and LIN slave break detection capability
– 13-bit break generation and 10/11-bit break detection when USART is hardware
configured for LIN
• IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode
• Smartcard mode
– Supports the T=0 and T=1 asynchronous protocols for smartcards as defined in
the ISO/IEC 7816-3 standard
– 0.5 and 1.5 stop bits for smartcard operation
• Support for ModBus communication
– Timeout feature
– CR/LF character recognition

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24.4 USART implementation

Table 117. STM32L0x1 USART/LPUART features
USART2 USART2
USART modes/features(1) USART1 (category (category USART4 USART5 LPUART1
1 devices) 2, 3 and 5)

Hardware flow control for modem X X X X - X

Continuous communication using
X X X X X X
DMA
Multiprocessor communication X X X X X X
Synchronous mode X - X X X -
Smartcard mode X X X - - -
Single-wire Half-duplex
X X X X X X
communication
Ir SIR ENDEC block X X X - - -
LIN mode X - X - - -
Dual clock domain and wakeup from
X - X - - X
Stop mode
Receiver timeout interrupt X - X - - -
Modbus communication X - X - - -
Auto baud rate detection X - X - - -
Driver Enable X X X X X X
(2),
USART/LPUART data length 7 8 and 9 bits
1. X = supported.
2. In 7-bit data length mode, Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frame detection) are not
supported.

24.5 USART functional description

Any USART bidirectional communication requires a minimum of two pins: Receive data In
(RX) and Transmit data Out (TX):
• RX: Receive data Input.
This is the serial data input. Oversampling techniques are used for data recovery by
discriminating between valid incoming data and noise.
• TX: Transmit data Output.
When the transmitter is disabled, the output pin returns to its I/O port configuration.
When the transmitter is enabled and nothing is to be transmitted, the TX pin is at high
level. In Single-wire and Smartcard modes, this I/O is used to transmit and receive the
data.

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Serial data are transmitted and received through these pins in normal USART mode. The
frames are comprised of:
• An Idle Line prior to transmission or reception
• A start bit
• A data word (7, 8 or 9 bits) least significant bit first
• 0.5, 1, 1.5, 2 stop bits indicating that the frame is complete
• The USART interface uses a baud rate generator
• A status register (USART_ISR)
• Receive and transmit data registers (USART_RDR, USART_TDR)
• A baud rate register (USART_BRR)
• A guard-time register (USART_GTPR) in case of Smartcard mode.
Refer to Section 24.8: USART registers on page 701 for the definitions of each bit.
The following pin is required to interface in synchronous mode and Smartcard mode:
• CK: Clock output. This pin outputs the transmitter data clock for synchronous
transmission corresponding to SPI master mode (no clock pulses on start bit and stop
bit, and a software option to send a clock pulse on the last data bit). In parallel, data
can be received synchronously on RX. This can be used to control peripherals that
have shift registers. The clock phase and polarity are software programmable. In
Smartcard mode, CK output can provide the clock to the smartcard.
The following pins are required in RS232 Hardware flow control mode:
• CTS: Clear To Send blocks the data transmission at the end of the current transfer
(when high)
• RTS: Request to send indicates that the USART is ready to receive data (when low).
The following pin is required in RS485 Hardware control mode:
• DE: Driver Enable activates the transmission mode of the external transceiver.
Note: DE and RTS share the same pin.

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Figure 213. USART block diagram

PRDATA PWDATA
Write Read DR (data register)
(CPU or DMA) (CPU or DMA)

Transmit shift register Receive shift register

IrDA
TX SIR
Transmit data register Receive data register
ENDEC
RX (TDR) (RDR)
block

USART_GTPR register
GT PSC CK control CK

USART_CR3 register USART_CR2 register

USART_CR2 register
USART_CR1 register

RTS/ Hardware
DE flow
CTS controller Receiver
clock
Transmit Wakeup Receiver
control unit control

USART_CR1 register USART_ISR register

USART
interrupt
control

USART_BRR register
TE Transmitter
rate controller
/USARTDIV or 2/USARTDIV
Transmitter (depending on the
BRR[15:0]
clock oversampling mode)
(Note 1)
Receiver rate
RE controller
fCK
(Note 2) Conventional baud rate generator

MS19821V8

1. For details on coding USARTDIV in the USART_BRR register, refer to Section 24.5.4: USART baud rate
generation.
2. fCK can be fLSE, fHSI, fPCLK, fSYS.

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24.5.1 USART character description

The word length can be selected as being either 7 or 8 or 9 bits by programming the M[1:0]
bits in the USART_CR1 register (see Figure 214).
• 7-bit character length: M[1:0] = 10
• 8-bit character length: M[1:0] = 00
• 9-bit character length: M[1:0] = 01
Note: The 7-bit mode is supported only on some USARTs. In addition, not all modes are
supported in 7-bit data length mode. Refer to Section 24.4: USART implementation for
additional information.
By default, the signal (TX or RX) is in low state during the start bit. It is in high state during
the stop bit.
These values can be inverted, separately for each signal, through polarity configuration
control.
An Idle character is interpreted as an entire frame of “1”s (the number of “1”s includes the
number of stop bits).
A Break character is interpreted on receiving “0”s for a frame period. At the end of the
break frame, the transmitter inserts 2 stop bits.
Transmission and reception are driven by a common baud rate generator, the clock for each
is generated when the enable bit is set respectively for the transmitter and receiver.
The details of each block is given below.

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Figure 214. Word length programming

9-bit word length (M = 01 ), 1 Stop bit

Possible
Data frame Parity
bit
Next
Start Stop Start
bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 bit bit

Clock **

Start
Idle frame bit

Break frame Stop Stop Start

bit bit bit

8-bit word length (M = 00 ), 1 Stop bit

Possible
Data frame Parity
bit
Next
Start Stop Start
bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 bit bit

Clock **

Start
Idle frame bit

Break frame Stop Stop Start

bit bit bit

7-bit word length (M = 10 ), 1 Stop bit

Possible
Data frame Parity
bit
Next
Start Stop Start
bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 bit bit

Clock **

Start
Idle frame bit

Break frame Stop Stop Start

bit bit bit

** LBCL bit controls last data clock pulse

MS33194V2

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24.5.2 USART transmitter

The transmitter can send data words of either 7, 8 or 9 bits depending on the M bits status.
The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The
data in the transmit shift register is output on the TX pin and the corresponding clock pulses
are output on the CK pin.

Character transmission
During an USART transmission, data shifts out least significant bit first (default
configuration) on the TX pin. In this mode, the USART_TDR register consists of a buffer
(TDR) between the internal bus and the transmit shift register (see Figure 213).
Every character is preceded by a start bit which is a logic level low for one bit period. The
character is terminated by a configurable number of stop bits.
The following stop bits are supported by USART: 0.5, 1, 1.5 and 2 stop bits.
Note: The TE bit must be set before writing the data to be transmitted to the USART_TDR.
The TE bit should not be reset during transmission of data. Resetting the TE bit during the
transmission will corrupt the data on the TX pin as the baud rate counters will get frozen.
The current data being transmitted will be lost.
An idle frame will be sent after the TE bit is enabled.
Configurable stop bits
The number of stop bits to be transmitted with every character can be programmed in
Control register 2, bits 13,12.
• 1 stop bit: This is the default value of number of stop bits.
• 2 stop bits: This will be supported by normal USART, Single-wire and Modem modes.
• 1.5 stop bits: To be used in Smartcard mode.
• 0.5 stop bit: To be used when receiving data in Smartcard mode.
An idle frame transmission will include the stop bits.
A break transmission will be 10 low bits (when M[1:0] = 00) or 11 low bits (when M[1:0] = 01)
or 9 low bits (when M[1:0] = 10) followed by 2 stop bits (see Figure 215). It is not possible to
transmit long breaks (break of length greater than 9/10/11 low bits).

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Figure 215. Configurable stop bits

8-bit data, 1 Stop bit

Possible
Data frame Next Next data frame
parity bit
start
Start bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Stop
bit
bit
CLOCK **

** LBCL bit controls last data clock pulse

8-bit data, 1 1/2 Stop bits
Possible
Data frame Next Next data frame
parity bit
start
Start bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 1.5
bit
Stop
bits

8-bit data, 2 Stop bits

Possible
Data frame Next Next data frame
parity bit
start
Start bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 2
bit
Stop
bits
MSv31887V1

Character transmission procedure

1. Program the M bits in USART_CR1 to define the word length.
2. Select the desired baud rate using the USART_BRR register.
3. Program the number of stop bits in USART_CR2.
4. Enable the USART by writing the UE bit in USART_CR1 register to 1.
5. Select DMA enable (DMAT) in USART_CR3 if multibuffer communication is to take
place. Configure the DMA register as explained in multibuffer communication.
6. Set the TE bit in USART_CR1 to send an idle frame as first transmission.
7. Write the data to send in the USART_TDR register (this clears the TXE bit). Repeat this
for each data to be transmitted in case of single buffer.
8. After writing the last data into the USART_TDR register, wait until TC=1. This indicates
that the transmission of the last frame is complete. This is required for instance when
the USART is disabled or enters the Halt mode to avoid corrupting the last
transmission.
For code example, refer to A.15.1: USART transmitter configuration code example.

Single byte communication

Clearing the TXE bit is always performed by a write to the transmit data register.
The TXE bit is set by hardware and it indicates:
• The data has been moved from the USART_TDR register to the shift register and the
data transmission has started.
• The USART_TDR register is empty.
• The next data can be written in the USART_TDR register without overwriting the
previous data.
For code example, refer to A.15.2: USART transmit byte code example.
This flag generates an interrupt if the TXEIE bit is set.

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When a transmission is taking place, a write instruction to the USART_TDR register stores
the data in the TDR register; next, the data is copied in the shift register at the end of the
currently ongoing transmission.
When no transmission is taking place, a write instruction to the USART_TDR register places
the data in the shift register, the data transmission starts, and the TXE bit is set.
If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An
interrupt is generated if the TCIE bit is set in the USART_CR1 register.
After writing the last data in the USART_TDR register, it is mandatory to wait for TC=1
before disabling the USART or causing the microcontroller to enter the low-power mode
(see Figure 216: TC/TXE behavior when transmitting).

Figure 216. TC/TXE behavior when transmitting

Idle preamble Frame 1 Frame 2 Frame 3

TX line
Set by hardware Set by hardware
TXE flag cleared by software cleared by software Set by hardware

USART_DR F1 F2 F3
Set by hardware
TC flag

Software Software waits until TXE=1

enables the TC is not set TC is not set TC is set
and writes F2 into DR
USART because TXE=0 because TXE=0 because TXE=1

Software waits until

Software waits until TXE=1 Software waits until TC=1
and writes F1 into DR TXE=1 and writes
F3 into DR

ai17121b

For code example, refer to A.15.3: USART transfer complete code example.

Break characters
Setting the SBKRQ bit transmits a break character. The break frame length depends on the
M bits (see Figure 214).
If a ‘1’ is written to the SBKRQ bit, a break character is sent on the TX line after completing
the current character transmission. The SBKF bit is set by the write operation and it is reset
by hardware when the break character is completed (during the stop bits after the break
character). The USART inserts a logic 1 signal (STOP) for the duration of 2 bits at the end of
the break frame to guarantee the recognition of the start bit of the next frame.
In the case the application needs to send the break character following all previously
inserted data, including the ones not yet transmitted, the software should wait for the TXE
flag assertion before setting the SBKRQ bit.

Idle characters
Setting the TE bit drives the USART to send an idle frame before the first data frame.

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24.5.3 USART receiver

The USART can receive data words of either 7, 8 or 9 bits depending on the M bits in the
USART_CR1 register.

Start bit detection

The start bit detection sequence is the same when oversampling by 16 or by 8.
In the USART, the start bit is detected when a specific sequence of samples is recognized.
This sequence is: 1 1 1 0 X 0 X 0X 0X 0 X 0X 0.

Figure 217. Start bit detection when oversampling by 16 or 8

Note: If the sequence is not complete, the start bit detection aborts and the receiver returns to the
idle state (no flag is set), where it waits for a falling edge.
The start bit is confirmed (RXNE flag set, interrupt generated if RXNEIE=1) if the 3 sampled
bits are at 0 (first sampling on the 3rd, 5th and 7th bits finds the 3 bits at 0 and second
sampling on the 8th, 9th and 10th bits also finds the 3 bits at 0).
The start bit is validated (RXNE flag set, interrupt generated if RXNEIE=1) but the NF noise
flag is set if,
a) for both samplings, 2 out of the 3 sampled bits are at 0 (sampling on the 3rd, 5th
and 7th bits and sampling on the 8th, 9th and 10th bits)
or
b) for one of the samplings (sampling on the 3rd, 5th and 7th bits or sampling on the
8th, 9th and 10th bits), 2 out of the 3 bits are found at 0.

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If neither conditions a. or b. are met, the start detection aborts and the receiver returns to the
idle state (no flag is set).

Character reception
During an USART reception, data shifts in least significant bit first (default configuration)
through the RX pin. In this mode, the USART_RDR register consists of a buffer (RDR)
between the internal bus and the receive shift register.
Character reception procedure
1. Program the M bits in USART_CR1 to define the word length.
2. Select the desired baud rate using the baud rate register USART_BRR
3. Program the number of stop bits in USART_CR2.
4. Enable the USART by writing the UE bit in USART_CR1 register to 1.
5. Select DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take
place. Configure the DMA register as explained in multibuffer communication.
6. Set the RE bit USART_CR1. This enables the receiver which begins searching for a
start bit.
For code example, refer to A.15.4: USART receiver configuration code example.
When a character is received:
• The RXNE bit is set to indicate that the content of the shift register is transferred to the
RDR. In other words, data has been received and can be read (as well as its
associated error flags).
• An interrupt is generated if the RXNEIE bit is set.
• The error flags can be set if a frame error, noise or an overrun error has been detected
during reception. PE flag can also be set with RXNE.
• In multibuffer, RXNE is set after every byte received and is cleared by the DMA read of
the Receive data Register.
• In single buffer mode, clearing the RXNE bit is performed by a software read to the
USART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ
in the USART_RQR register. The RXNE bit must be cleared before the end of the
reception of the next character to avoid an overrun error.
For code example, refer to A.15.5: USART receive byte code example.

Break character
When a break character is received, the USART handles it as a framing error.

Idle character
When an idle frame is detected, there is the same procedure as for a received data
character plus an interrupt if the IDLEIE bit is set.

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Overrun error
An overrun error occurs when a character is received when RXNE has not been reset. Data
can not be transferred from the shift register to the RDR register until the RXNE bit is
cleared.
The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set
when the next data is received or the previous DMA request has not been serviced. When
an overrun error occurs:
• The ORE bit is set.
• The RDR content will not be lost. The previous data is available when a read to
USART_RDR is performed.
• The shift register will be overwritten. After that point, any data received during overrun
is lost.
• An interrupt is generated if either the RXNEIE bit is set or EIE bit is set.
• The ORE bit is reset by setting the ORECF bit in the ICR register.
Note: The ORE bit, when set, indicates that at least 1 data has been lost. There are two
possibilities:
- if RXNE=1, then the last valid data is stored in the receive register RDR and can be read,
- if RXNE=0, then it means that the last valid data has already been read and thus there is
nothing to be read in the RDR. This case can occur when the last valid data is read in the
RDR at the same time as the new (and lost) data is received.

Selecting the proper oversampling method

When the dual clock domain with the wakeup from Stop mode is supported, the clock
source can be one of the following sources: PCLK (default), LSE, HSI16 or SYSCLK.
Otherwise, the USART clock source is PCLK.
Choosing LSE or HSI16 as clock source may allow the USART to receive data while the
MCU is in low-power mode. Depending on the received data and wakeup mode selection,
the USART wakes up the MCU, when needed, in order to transfer the received data by
software reading the USART_RDR register or by DMA.
For the other clock sources, the system must be active in order to allow USART
communication.
The receiver implements different user-configurable oversampling techniques for data
recovery by discriminating between valid incoming data and noise. This allows a trade-off
between the maximum communication speed and noise/clock inaccuracy immunity.
The oversampling method can be selected by programming the OVER8 bit in the
USART_CR1 register and can be either 16 or 8 times the baud rate clock (Figure 218 and
Figure 219).
Depending on the application:
• Select oversampling by 8 (OVER8=1) to achieve higher speed (up to fCK/8). In this
case the maximum receiver tolerance to clock deviation is reduced (refer to
Section 24.5.5: Tolerance of the USART receiver to clock deviation on page 674)
• Select oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to
clock deviations. In this case, the maximum speed is limited to maximum fCK/16 where
fCK is the clock source frequency.

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Programming the ONEBIT bit in the USART_CR3 register selects the method used to
evaluate the logic level. There are two options:
• The majority vote of the three samples in the center of the received bit. In this case,
when the 3 samples used for the majority vote are not equal, the NF bit is set
• A single sample in the center of the received bit
Depending on the application:
– select the three samples’ majority vote method (ONEBIT=0) when operating in a
noisy environment and reject the data when a noise is detected (refer to
Figure 118) because this indicates that a glitch occurred during the sampling.
– select the single sample method (ONEBIT=1) when the line is noise-free to
increase the receiver’s tolerance to clock deviations (see Section 24.5.5:
Tolerance of the USART receiver to clock deviation on page 674). In this case the
NF bit will never be set.
When noise is detected in a frame:
• The NF bit is set at the rising edge of the RXNE bit.
• The invalid data is transferred from the Shift register to the USART_RDR register.
• No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of
multibuffer communication an interrupt will be issued if the EIE bit is set in the
USART_CR3 register.
The NF bit is reset by setting NFCF bit in ICR register.
Note: Oversampling by 8 is not available in LIN, Smartcard and IrDA modes. In those modes, the
OVER8 bit is forced to ‘0’ by hardware.

Figure 218. Data sampling when oversampling by 16

RX line

sampled values
Sample clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

6/16
7/16 7/16
One bit time

MSv31152V1

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Figure 219. Data sampling when oversampling by 8

RX line

sampled values
Sample
clock (x8) 1 2 3 4 5 6 7 8

2/8
3/8 3/8
One bit time

MSv31153V1

Table 118. Noise detection from sampled data

Sampled value NE status Received bit value

000 0 0
001 1 0
010 1 0
011 1 1
100 1 0
101 1 1
110 1 1
111 0 1

Framing error
A framing error is detected when the stop bit is not recognized on reception at the expected
time, following either a de-synchronization or excessive noise.
When the framing error is detected:
• The FE bit is set by hardware
• The invalid data is transferred from the Shift register to the USART_RDR register.
• No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of
multibuffer communication an interrupt will be issued if the EIE bit is set in the
USART_CR3 register.
The FE bit is reset by writing 1 to the FECF in the USART_ICR register.

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Configurable stop bits during reception

The number of stop bits to be received can be configured through the control bits of Control
Register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode.
• 0.5 stop bit (reception in Smartcard mode): No sampling is done for 0.5 stop bit. As
a consequence, no framing error and no break frame can be detected when 0.5 stop bit
is selected.
• 1 stop bit: Sampling for 1 stop Bit is done on the 8th, 9th and 10th samples.
• 1.5 stop bits (Smartcard mode): When transmitting in Smartcard mode, the device
must check that the data is correctly sent. Thus the receiver block must be enabled (RE
=1 in the USART_CR1 register) and the stop bit is checked to test if the smartcard has
detected a parity error. In the event of a parity error, the smartcard forces the data
signal low during the sampling - NACK signal-, which is flagged as a framing error.
Then, the FE flag is set with the RXNE at the end of the 1.5 stop bits. Sampling for 1.5
stop bits is done on the 16th, 17th and 18th samples (1 baud clock period after the
beginning of the stop bit). The 1.5 stop bits can be decomposed into 2 parts: one 0.5
baud clock period during which nothing happens, followed by 1 normal stop bit period
during which sampling occurs halfway through. Refer to Section 24.5.13: USART
Smartcard mode on page 686 for more details.
• 2 stop bits: Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the
first stop bit. If a framing error is detected during the first stop bit the framing error flag
will be set. The second stop bit is not checked for framing error. The RXNE flag will be
set at the end of the first stop bit.

24.5.4 USART baud rate generation

The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as
programmed in the USART_BRR register.

Equation 1: Baud rate for standard USART (SPI mode included) (OVER8 = 0 or 1)
In case of oversampling by 16, the equation is:
f CK
Tx/Rx baud = --------------------------------
USARTDIV

In case of oversampling by 8, the equation is:

2 × f CK
Tx/Rx baud = --------------------------------
USARTDIV

Equation 2: Baud rate in Smartcard, LIN and IrDA modes (OVER8 = 0)

In Smartcard, LIN and IrDA modes, only Oversampling by 16 is supported:
f CK
Tx/Rx baud = --------------------------------
USARTDIV

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USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.
• When OVER8 = 0, BRR = USARTDIV.
• When OVER8 = 1
– BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right.
– BRR[3] must be kept cleared.
– BRR[15:4] = USARTDIV[15:4]
Note: The baud counters are updated to the new value in the baud registers after a write operation
to USART_BRR. Hence the baud rate register value should not be changed during
communication.
In case of oversampling by 16 or 8, USARTDIV must be greater than or equal to 16d.

How to derive USARTDIV from USART_BRR register values

Example 1
To obtain 9600 baud with fCK = 8 MHz.
• In case of oversampling by 16:
USARTDIV = 8 000 000/9600
BRR = USARTDIV = 833d = 0341h
• In case of oversampling by 8:
USARTDIV = 2 * 8 000 000/9600
USARTDIV = 1666,66 (1667d = 683h)
BRR[3:0] = 3h >> 1 = 1h
BRR = 0x681

Example 2
To obtain 921.6 kbaud with fCK = 32 MHz.
• In case of oversampling by 16:
USARTDIV = 32 000 000/921 600
BRR = USARTDIV = 35d = 23h
• In case of oversampling by 8:
USARTDIV = 2 * 32 000 000/921 600
USARTDIV = 70d = 46h
BRR[3:0] = USARTDIV[3:0] >> 1 = 6h >> 1 = 3h
BRR = 0x43

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Table 119. Error calculation for programmed baud rates at fCK = 32 MHz in both cases of
oversampling by 16 or by 8(1)
Baud rate Oversampling by 16 (OVER8 = 0) Oversampling by 8 (OVER8 = 1)

% Error =
(Calculated -
S.No Desired Actual BRR Actual BRR % Error
Desired)B.Rate /
Desired B.Rate

1 2.4 kbaud 2.4 kbaud 0x3415 0 2.4 kbaud 0x6825 0

2 9.6 kbaud 9.6 kbaud 0xD05 0 9.6 kbaud 0x1A05 0
3 19.2 kbaud 19.19 kbaud 0x683 0.02 19.2 kbaud 0xD02 0
4 38.4 kbaud 38.41 kbaud 0x341 0.04 38.39 kbaud 0x681 0.02
5 57.6 kbaud 57.55 kbaud 0x22C 0.08 57.6 kbaud 0x453 0
6 115.2 kbaud 115.1 kbaud 0x116 0.08 115.11 kbaud 0x226 0.08
7 230.4 kbaud 230.21 kbaud 0x8B 0.08 230.21 kbaud 0x113 0.08
8 460.8 kbaud 463.76 kbaud 0x045 0.64 460.06 kbaud 0x85 0.08
9 921.6 kbaud 914.28 kbaud 0x23 0.79 927.5 kbaud 0x42 0.79
10 2 Mbaud 2 Mbaud 0x10 0 2 Mbaud 0x20 0
12 4Mbaud 4Mbaud NA NA 4Mbaud 0x10 0
1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can
be fixed with these data.

24.5.5 Tolerance of the USART receiver to clock deviation

The asynchronous receiver of the USART works correctly only if the total clock system
deviation is less than the tolerance of the USART receiver. The causes which contribute to
the total deviation are:
• DTRA: Deviation due to the transmitter error (which also includes the deviation of the
transmitter’s local oscillator)
• DQUANT: Error due to the baud rate quantization of the receiver
• DREC: Deviation of the receiver’s local oscillator
• DTCL: Deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-to-
low transition timing)

DTRA + DQUANT + DREC + DTCL + DWU < USART receiver′s tolerance

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where
DWU is the error due to sampling point deviation when the wakeup from Stop mode is
used.
when M[1:0] = 01:
t WUUSART
DWU = --------------------------
-
11 × Tbit

when M[1:0] = 00:

t WUUSART
DWU = --------------------------
-
10 × Tbit

when M[1:0] = 10:

t WUUSART
DWU = --------------------------
-
9 × Tbit

tWUUSART is the time between:

– The detection of start bit falling edge
– The instant when clock (requested by the peripheral) is ready and reaching the
peripheral and regulator is ready.
tWUUSART corresponds to tWUSTOP value provided in the datasheet.
The USART receiver can receive data correctly at up to the maximum tolerated
deviation specified in Table 120 and Table 121 depending on the following choices:
• 9-, 10- or 11-bit character length defined by the M bits in the USART_CR1 register
• Oversampling by 8 or 16 defined by the OVER8 bit in the USART_CR1 register
• Bits BRR[3:0] of USART_BRR register are equal to or different from 0000.
• Use of 1 bit or 3 bits to sample the data, depending on the value of the ONEBIT bit in
the USART_CR3 register.

Table 120. Tolerance of the USART receiver when BRR [3:0] = 0000
OVER8 bit = 0 OVER8 bit = 1
M bits
ONEBIT=0 ONEBIT=1 ONEBIT=0 ONEBIT=1

00 3.75% 4.375% 2.50% 3.75%

01 3.41% 3.97% 2.27% 3.41%
10 4.16% 4.86% 2.77% 4.16%

Table 121. Tolerance of the USART receiver when BRR [3:0] is different from 0000
OVER8 bit = 0 OVER8 bit = 1
M bits
ONEBIT=0 ONEBIT=1 ONEBIT=0 ONEBIT=1

00 3.33% 3.88% 2% 3%
01 3.03% 3.53% 1.82% 2.73%
10 3.7% 4.31% 2.22% 3.33%

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Note: The data specified in Table 120 and Table 121 may slightly differ in the special case when
the received frames contain some Idle frames of exactly 10-bit durations when M bits = 00
(11-bit durations when M bits =01 or 9- bit durations when M bits = 10).

24.5.6 USART auto baud rate detection

The USART is able to detect and automatically set the USART_BRR register value based
on the reception of one character. Automatic baud rate detection is useful under two
circumstances:
• The communication speed of the system is not known in advance
• The system is using a relatively low accuracy clock source and this mechanism allows
the correct baud rate to be obtained without measuring the clock deviation.
The clock source frequency must be compatible with the expected communication speed
(when oversampling by 16, the baud rate is between fCK/65535 and fCK/16. when
oversampling by 8, the baud rate is between fCK/65535 and fCK/8).
Before activating the auto baud rate detection, the auto baud rate detection mode must be
chosen. There are various modes based on different character patterns.
They can be chosen through the ABRMOD[1:0] field in the USART_CR2 register. In these
auto baud rate modes, the baud rate is measured several times during the synchronization
data reception and each measurement is compared to the previous one.
These modes are:
• Mode 0: Any character starting with a bit at 1. In this case the USART measures the
duration of the Start bit (falling edge to rising edge).
• Mode 1: Any character starting with a 10xx bit pattern. In this case, the USART
measures the duration of the Start and of the 1st data bit. The measurement is done
falling edge to falling edge, ensuring better accuracy in the case of slow signal slopes.
• Mode 2: A 0x7F character frame (it may be a 0x7F character in LSB first mode or a
0xFE in MSB first mode). In this case, the baud rate is updated first at the end of the
start bit (BRs), then at the end of bit 6 (based on the measurement done from falling
edge to falling edge: BR6). Bit 0 to bit 6 are sampled at BRs while further bits of the
character are sampled at BR6.
• Mode 3: A 0x55 character frame. In this case, the baud rate is updated first at the end
of the start bit (BRs), then at the end of bit 0 (based on the measurement done from
falling edge to falling edge: BR0), and finally at the end of bit 6 (BR6). Bit 0 is sampled
at BRs, bit 1 to bit 6 are sampled at BR0, and further bits of the character are sampled
at BR6.
In parallel, another check is performed for each intermediate transition of RX line. An
error is generated if the transitions on RX are not sufficiently synchronized with the
receiver (the receiver being based on the baud rate calculated on bit 0).
Prior to activating auto baud rate detection, the USART_BRR register must be initialized by
writing a non-zero baud rate value.
The automatic baud rate detection is activated by setting the ABREN bit in the USART_CR2
register. The USART will then wait for the first character on the RX line. The auto baud rate
operation completion is indicated by the setting of the ABRF flag in the USART_ISR
register. If the line is noisy, the correct baud rate detection cannot be guaranteed. In this
case the BRR value may be corrupted and the ABRE error flag will be set. This also
happens if the communication speed is not compatible with the automatic baud rate

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detection range (bit duration not between 16 and 65536 clock periods (oversampling by 16)
and not between 8 and 65536 clock periods (oversampling by 8)).
The RXNE interrupt will signal the end of the operation.
At any later time, the auto baud rate detection may be relaunched by resetting the ABRF
flag (by writing a 0).
Note: If the USART is disabled (UE=0) during an auto baud rate operation, the BRR value may be
corrupted.

24.5.7 Multiprocessor communication using USART

In multiprocessor communication, the following bits are to be kept cleared:
• LINEN bit in the USART_CR2 register,
• HDSEL, IREN and SCEN bits in the USART_CR3 register.
It is possible to perform multiprocessor communication with the USART (with several
USARTs connected in a network). For instance one of the USARTs can be the master, its TX
output connected to the RX inputs of the other USARTs. The others are slaves, their
respective TX outputs are logically ANDed together and connected to the RX input of the
master.
In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant USART
service overhead for all non addressed receivers.
The non addressed devices may be placed in mute mode by means of the muting function.
In order to use the mute mode feature, the MME bit must be set in the USART_CR1
register.
In mute mode:
• None of the reception status bits can be set.
• All the receive interrupts are inhibited.
• The RWU bit in USART_ISR register is set to 1. RWU can be controlled automatically
by hardware or by software, through the MMRQ bit in the USART_RQR register, under
certain conditions.
The USART can enter or exit from mute mode using one of two methods, depending on the
WAKE bit in the USART_CR1 register:
• Idle Line detection if the WAKE bit is reset,
• Address Mark detection if the WAKE bit is set.

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Idle line detection (WAKE=0)

The USART enters mute mode when the MMRQ bit is written to 1 and the RWU is
automatically set.
It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but
the IDLE bit is not set in the USART_ISR register. An example of mute mode behavior using
Idle line detection is given in Figure 220.

Figure 220. Mute mode using Idle line detection

RXNE RXNE

RX Data 1 Data 2 Data 3 Data 4 IDLE Data 5 Data 6

RWU Mute mode Normal mode

MMRQ written to 1 Idle frame detected

MSv31154V1

Note: If the MMRQ is set while the IDLE character has already elapsed, mute mode will not be
entered (RWU is not set).
If the USART is activated while the line is IDLE, the idle state is detected after the duration
of one IDLE frame (not only after the reception of one character frame).

4-bit/7-bit address mark detection (WAKE=1)

In this mode, bytes are recognized as addresses if their MSB is a ‘1’ otherwise they are
considered as data. In an address byte, the address of the targeted receiver is put in the 4
or 7 LSBs. The choice of 7 or 4-bit address detection is done using the ADDM7 bit. This 4-
bit/7-bit word is compared by the receiver with its own address which is programmed in the
ADD bits in the USART_CR2 register.
Note: In 7-bit and 9-bit data modes, address detection is done on 6-bit and 8-bit addresses
(ADD[5:0] and ADD[7:0]) respectively.
The USART enters mute mode when an address character is received which does not
match its programmed address. In this case, the RWU bit is set by hardware. The RXNE
flag is not set for this address byte and no interrupt or DMA request is issued when the
USART enters mute mode.
The USART also enters mute mode when the MMRQ bit is written to 1. The RWU bit is also
automatically set in this case.
The USART exits from mute mode when an address character is received which matches
the programmed address. Then the RWU bit is cleared and subsequent bytes are received
normally. The RXNE bit is set for the address character since the RWU bit has been
cleared.
An example of mute mode behavior using address mark detection is given in Figure 221.

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Figure 221. Mute mode using address mark detection

In this example, the current address of the receiver is 1
(programmed in the USART_CR2 register)
RXNE RXNE RXNE

RX IDLE Addr=0 Data 1 Data 2 IDLE Addr=1 Data 3 Data 4 Addr=2 Data 5

RWU Mute mode Normal mode Mute mode

MMRQ written to 1 Matching address Non-matching address

(RXNE was cleared)

Non-matching address
MSv31155V1

24.5.8 Modbus communication using USART

The USART offers basic support for the implementation of Modbus/RTU and Modbus/ASCII
protocols. Modbus/RTU is a half duplex, block transfer protocol. The control part of the
protocol (address recognition, block integrity control and command interpretation) must be
implemented in software.
The USART offers basic support for the end of the block detection, without software
overhead or other resources.

Modbus/RTU
In this mode, the end of one block is recognized by a “silence” (idle line) for more than 2
character times. This function is implemented through the programmable timeout function.
The timeout function and interrupt must be activated, through the RTOEN bit in the
USART_CR2 register and the RTOIE in the USART_CR1 register. The value corresponding
to a timeout of 2 character times (for example 22 x bit duration) must be programmed in the
RTO register. when the receive line is idle for this duration, after the last stop bit is received,
an interrupt is generated, informing the software that the current block reception is
completed.

Modbus/ASCII
In this mode, the end of a block is recognized by a specific (CR/LF) character sequence.
The USART manages this mechanism using the character match function.
By programming the LF ASCII code in the ADD[7:0] field and by activating the character
match interrupt (CMIE=1), the software is informed when a LF has been received and can
check the CR/LF in the DMA buffer.

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24.5.9 USART parity control

Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame
length defined by the M bits, the possible USART frame formats are as listed in Table 122.

Table 122. Frame formats

M bits PCE bit USART frame(1)

00 0 | SB | 8-bit data | STB |

00 1 | SB | 7-bit data | PB | STB |
01 0 | SB | 9-bit data | STB |
01 1 | SB | 8-bit data | PB | STB |
10 0 | SB | 7-bit data | STB |
10 1 | SB | 6-bit data | PB | STB |
1. Legends: SB: start bit, STB: stop bit, PB: parity bit. In the data register, the PB is always taking the MSB
position (9th, 8th or 7th, depending on the M bits value).

Even parity
The parity bit is calculated to obtain an even number of “1s” inside the frame of the 6, 7 or 8
LSB bits (depending on M bits values) and the parity bit.
As an example, if data=00110101, and 4 bits are set, then the parity bit will be 0 if even
parity is selected (PS bit in USART_CR1 = 0).

Odd parity
The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 6, 7
or 8 LSB bits (depending on M bits values) and the parity bit.
As an example, if data=00110101 and 4 bits set, then the parity bit will be 1 if odd parity is
selected (PS bit in USART_CR1 = 1).

Parity checking in reception

If the parity check fails, the PE flag is set in the USART_ISR register and an interrupt is
generated if PEIE is set in the USART_CR1 register. The PE flag is cleared by software
writing 1 to the PECF in the USART_ICR register.

Parity generation in transmission

If the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register
is transmitted but is changed by the parity bit (even number of “1s” if even parity is selected
(PS=0) or an odd number of “1s” if odd parity is selected (PS=1)).

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24.5.10 USART LIN (local interconnection network) mode

This section is relevant only when LIN mode is supported. Please refer to Section 24.4:
USART implementation on page 659.
The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN
mode, the following bits must be kept cleared:
• STOP[1:0] and CLKEN in the USART_CR2 register,
• SCEN, HDSEL and IREN in the USART_CR3 register.
For code example, refer to A.15.6: USART LIN mode code example.

LIN transmission
The procedure explained in Section 24.5.2: USART transmitter has to be applied for LIN
Master transmission. It must be the same as for normal USART transmission with the
following differences:
• Clear the M bits to configure 8-bit word length.
• Set the LINEN bit to enter LIN mode. In this case, setting the SBKRQ bit sends 13 ‘0’
bits as a break character. Then 2 bits of value ‘1’ are sent to allow the next start
detection.

LIN reception
When LIN mode is enabled, the break detection circuit is activated. The detection is totally
independent from the normal USART receiver. A break can be detected whenever it occurs,
during Idle state or during a frame.
When the receiver is enabled (RE=1 in USART_CR1), the circuit looks at the RX input for a
start signal. The method for detecting start bits is the same when searching break
characters or data. After a start bit has been detected, the circuit samples the next bits
exactly like for the data (on the 8th, 9th and 10th samples). If 10 (when the LBDL = 0 in
USART_CR2) or 11 (when LBDL=1 in USART_CR2) consecutive bits are detected as ‘0,
and are followed by a delimiter character, the LBDF flag is set in USART_ISR. If the LBDIE
bit=1, an interrupt is generated. Before validating the break, the delimiter is checked for as it
signifies that the RX line has returned to a high level.
If a ‘1’ is sampled before the 10 or 11 have occurred, the break detection circuit cancels the
current detection and searches for a start bit again.
If the LIN mode is disabled (LINEN=0), the receiver continues working as normal USART,
without taking into account the break detection.
If the LIN mode is enabled (LINEN=1), as soon as a framing error occurs (i.e. stop bit
detected at ‘0’, which will be the case for any break frame), the receiver stops until the break
detection circuit receives either a ‘1’, if the break word was not complete, or a delimiter
character if a break has been detected.
The behavior of the break detector state machine and the break flag is shown on the
Figure 222: Break detection in LIN mode (11-bit break length - LBDL bit is set) on page 682.
Examples of break frames are given on Figure 223: Break detection in LIN mode vs.
Framing error detection on page 683.

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Figure 222. Break detection in LIN mode (11-bit break length - LBDL bit is set)

Case 1: break signal not long enough => break discarded, LBDF is not set

Break frame
RX line

Capture strobe

Break state
Idle Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Idle
machine
Read samples 0 0 0 0 0 0 0 0 0 0 1

Case 2: break signal just long enough => break detected, LBDF is set

Break frame
RX line
Delimiter is immediate
Capture strobe

Break state
Idle Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 B10 Idle
machine
Read samples 0 0 0 0 0 0 0 0 0 0 0

LBDF

Case 3: break signal long enough => break detected, LBDF is set

Break frame
RX line

Capture strobe

Break state
Idle Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 wait delimiter Idle
machine
Read samples 0 0 0 0 0 0 0 0 0 0 0

LBDF

MSv31156V1

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Figure 223. Break detection in LIN mode vs. Framing error detection

Case 1: break occurring after an Idle

RX line data 1 IDLE BREAK data 2 (0x55) data 3 (header)

1 data time 1 data time

RXNE /FE

LBDF

Case 2: break occurring while data is being received

RX line data 1 data2 BREAK data 2 (0x55) data 3 (header)

1 data time 1 data time

RXNE /FE

LBDF

MSv31157V1

24.5.11 USART synchronous mode

The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to
1. In synchronous mode, the following bits must be kept cleared:
• LINEN bit in the USART_CR2 register,
• SCEN, HDSEL and IREN bits in the USART_CR3 register.
In this mode, the USART can be used to control bidirectional synchronous serial
communications in master mode. The CK pin is the output of the USART transmitter clock.
No clock pulses are sent to the CK pin during start bit and stop bit. Depending on the state
of the LBCL bit in the USART_CR2 register, clock pulses are, or are not, generated during
the last valid data bit (address mark). The CPOL bit in the USART_CR2 register is used to
select the clock polarity, and the CPHA bit in the USART_CR2 register is used to select the
phase of the external clock (see Figure 224, Figure 225 and Figure 226).
During the Idle state, preamble and send break, the external CK clock is not activated.
In synchronous mode the USART transmitter works exactly like in asynchronous mode. But
as CK is synchronized with TX (according to CPOL and CPHA), the data on TX is
synchronous.
In this mode the USART receiver works in a different manner compared to the
asynchronous mode. If RE=1, the data is sampled on CK (rising or falling edge, depending
on CPOL and CPHA), without any oversampling. A setup and a hold time must be
respected (which depends on the baud rate: 1/16 bit duration).

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Note: The CK pin works in conjunction with the TX pin. Thus, the clock is provided only if the
transmitter is enabled (TE=1) and data is being transmitted (the data register USART_TDR
written). This means that it is not possible to receive synchronous data without transmitting
data.
The LBCL, CPOL and CPHA bits have to be selected when the USART is disabled (UE=0)
to ensure that the clock pulses function correctly.
For code example, refer to A.15.6: USART LIN mode code example.

Figure 224. USART example of synchronous transmission

RX Data out
TX Data in
Synchronous device
USART
(slave SPI)

CK Clock

MSv31158V2

Figure 225. USART data clock timing diagram (M bits = 00)

Idle or preceding M bits = 00 (8 data bits) Idle or next

transmission Start Stop transmission

Clock (CPOL=0, CPHA=0) *

Clock (CPOL=0, CPHA=1)

*

Clock (CPOL=1, CPHA=0) *

Clock (CPOL=1, CPHA=1) *

Data on TX
0 1 2 3 4 5 6 7
(from master)
Start LSB MSB Stop
Data on RX
0 1 2 3 4 5 6 7
(from slave)
LSB MSB
*
Capture strobe
*LBCL bit controls last data pulse

MSv34709V2

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Figure 226. USART data clock timing diagram (M bits = 01)

Idle or
Idle or next
preceding Start M bits =01 (9 data bits) Stop
transmission
transmission

Clock (CPOL=0,
CPHA=0) *
Clock (CPOL=0,
CPHA=1) *

Clock (CPOL=1, *
CPHA=0)
Clock (CPOL=1, *
CPHA=1)

Data on TX
0 1 2 3 4 5 6 7 8
(from master)
Start LSB MSB Stop
Data on RX
0 1 2 3 4 5 6 7 8
(from slave)
LSB MSB
Capture *
strobe
*LBCL bit controls last data pulse

MSv34710V1

Figure 227. RX data setup/hold time

CK
(capture strobe on CK rising
edge in this example)

Data on RX (from slave) Valid DATA bit

tSETUP tHOLD

tSETUP=tHOLD 1/16 bit time

MSv31161V2

Note: The function of CK is different in Smartcard mode. Refer to Section 24.5.13: USART
Smartcard mode for more details.

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24.5.12 USART Single-wire Half-duplex communication

Single-wire Half-duplex mode is selected by setting the HDSEL bit in the USART_CR3
register. In this mode, the following bits must be kept cleared:
• LINEN and CLKEN bits in the USART_CR2 register,
• SCEN and IREN bits in the USART_CR3 register.
The USART can be configured to follow a Single-wire Half-duplex protocol where the TX
and RX lines are internally connected. The selection between half- and Full-duplex
communication is made with a control bit HDSEL in USART_CR3.
As soon as HDSEL is written to 1:
• The TX and RX lines are internally connected
• The RX pin is no longer used
• The TX pin is always released when no data is transmitted. Thus, it acts as a standard
I/O in idle or in reception. It means that the I/O must be configured so that TX is
configured as alternate function open-drain with an external pull-up.
Apart from this, the communication protocol is similar to normal USART mode. Any conflicts
on the line must be managed by software (by the use of a centralized arbiter, for instance).
In particular, the transmission is never blocked by hardware and continues as soon as data
is written in the data register while the TE bit is set.
For code example, refer to A.15.8: USART single-wire half-duplex code example.

24.5.13 USART Smartcard mode

This section is relevant only when Smartcard mode is supported. Please refer to
Section 24.4: USART implementation on page 659.
Smartcard mode is selected by setting the SCEN bit in the USART_CR3 register. In
Smartcard mode, the following bits must be kept cleared:
• LINEN bit in the USART_CR2 register,
• HDSEL and IREN bits in the USART_CR3 register.
Moreover, the CLKEN bit may be set in order to provide a clock to the smartcard.
The smartcard interface is designed to support asynchronous protocol for smartcards as
defined in the ISO 7816-3 standard. Both T=0 (character mode) and T=1 (block mode) are
supported.
The USART should be configured as:
• 8 bits plus parity: where word length is set to 8 bits and PCE=1 in the USART_CR1
register
• 1.5 stop bits when transmitting and receiving data: where STOP=11 in the
USART_CR2 register. It is also possible to choose 0.5 stop bit for receiving.
For code example, refer to A.15.9: USART smartcard mode code example.
In T=0 (character) mode, the parity error is indicated at the end of each character during the
guard time period.
Figure 228 shows examples of what can be seen on the data line with and without parity
error.

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Figure 228. ISO 7816-3 asynchronous protocol

Without Parity error

Guard time
S 0 1 2 3 4 5 6 7 p
Start bit

WithParity error
Guard time
S 0 1 2 3 4 5 6 7 p

Start bit
Line pulled low by receiver
during stop in case of parity error

MSv31162V1

When connected to a smartcard, the TX output of the USART drives a bidirectional line that
is also driven by the smartcard. The TX pin must be configured as open drain.
Smartcard mode implements a single wire half duplex communication protocol.
• Transmission of data from the transmit shift register is guaranteed to be delayed by a
minimum of 1/2 baud clock. In normal operation a full transmit shift register starts
shifting on the next baud clock edge. In Smartcard mode this transmission is further
delayed by a guaranteed 1/2 baud clock.
• In transmission, if the smartcard detects a parity error, it signals this condition to the
USART by driving the line low (NACK). This NACK signal (pulling transmit line low for 1
baud clock) causes a framing error on the transmitter side (configured with 1.5 stop
bits). The USART can handle automatic re-sending of data according to the protocol.
The number of retries is programmed in the SCARCNT bit field. If the USART
continues receiving the NACK after the programmed number of retries, it stops
transmitting and signals the error as a framing error. The TXE bit can be set using the
TXFRQ bit in the USART_RQR register.
• Smartcard auto-retry in transmission: a delay of 2.5 baud periods is inserted between
the NACK detection by the USART and the start bit of the repeated character. The TC
bit is set immediately at the end of reception of the last repeated character (no guard-
time). If the software wants to repeat it again, it must insure the minimum 2 baud
periods required by the standard.
• If a parity error is detected during reception of a frame programmed with a 1.5 stop bits
period, the transmit line is pulled low for a baud clock period after the completion of the
receive frame. This is to indicate to the smartcard that the data transmitted to the
USART has not been correctly received. A parity error is NACKed by the receiver if the
NACK control bit is set, otherwise a NACK is not transmitted (to be used in T=1 mode).
If the received character is erroneous, the RXNE/receive DMA request is not activated.
According to the protocol specification, the smartcard must resend the same character.
If the received character is still erroneous after the maximum number of retries
specified in the SCARCNT bit field, the USART stops transmitting the NACK and
signals the error as a parity error.
• Smartcard auto-retry in reception: the BUSY flag remains set if the USART NACKs the
card but the card doesn’t repeat the character.

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• In transmission, the USART inserts the Guard Time (as programmed in the Guard Time
register) between two successive characters. As the Guard Time is measured after the
stop bit of the previous character, the GT[7:0] register must be programmed to the
desired CGT (Character Guard Time, as defined by the 7816-3 specification) minus 12
(the duration of one character).
• The assertion of the TC flag can be delayed by programming the Guard Time register.
In normal operation, TC is asserted when the transmit shift register is empty and no
further transmit requests are outstanding. In Smartcard mode an empty transmit shift
register triggers the Guard Time counter to count up to the programmed value in the
Guard Time register. TC is forced low during this time. When the Guard Time counter
reaches the programmed value TC is asserted high.
• The TCBGT flag can be used to detect the end of data transfer without waiting for
guard time completion. This flag is set just after the end of frame transmission and if no
NACK has been received from the card. The TCGBT flag is available in category 1
devices only.
• The de-assertion of TC flag is unaffected by Smartcard mode.
• If a framing error is detected on the transmitter end (due to a NACK from the receiver),
the NACK is not detected as a start bit by the receive block of the transmitter.
According to the ISO protocol, the duration of the received NACK can be 1 or 2 baud
clock periods.
• On the receiver side, if a parity error is detected and a NACK is transmitted the receiver
does not detect the NACK as a start bit.
Note: A break character is not significant in Smartcard mode. A 0x00 data with a framing error is
treated as data and not as a break.
No Idle frame is transmitted when toggling the TE bit. The Idle frame (as defined for the
other configurations) is not defined by the ISO protocol.
Figure 229 details how the NACK signal is sampled by the USART. In this example the
USART is transmitting data and is configured with 1.5 stop bits. The receiver part of the
USART is enabled in order to check the integrity of the data and the NACK signal.

Figure 229. Parity error detection using the 1.5 stop bits

Bit 7 Parity bit 1.5 Stop bit

1 bit time 1.5 bit time

Sampling at Sampling at
8th, 9th, 10th 8th, 9th, 10th

0.5 bit time

Sampling at Sampling at
8th, 9th, 10th 8th, 9th, 10th
MSv31163V1

The USART can provide a clock to the smartcard through the CK output. In Smartcard
mode, CK is not associated to the communication but is simply derived from the internal
peripheral input clock through a 5-bit prescaler. The division ratio is configured in the

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prescaler register USART_GTPR. CK frequency can be programmed from fCK/2 to fCK/62,

where fCK is the peripheral input clock.

Block mode (T=1)

In T=1 (block) mode, the parity error transmission is deactivated, by clearing the NACK bit in
the UART_CR3 register.
When requesting a read from the smartcard, in block mode, the software must enable the
receiver Timeout feature by setting the RTOEN bit in the USART_CR2 register and program
the RTO bits field in the RTOR register to the BWT (block wait time) - 11 value. If no answer
is received from the card before the expiration of this period, the RTOF flag will be set and a
timeout interrupt will be generated (if RTOIE bit in the USART_CR1 register is set). If the
first character is received before the expiration of the period, it is signaled by the RXNE
interrupt.
Note: The RXNE interrupt must be enabled even when using the USART in DMA mode to read
from the smartcard in block mode. In parallel, the DMA must be enabled only after the first
received byte.
After the reception of the first character (RXNE interrupt), the RTO bit fields in the RTOR
register must be programmed to the CWT (character wait time) - 11 value, in order to allow
the automatic check of the maximum wait time between two consecutive characters. This
time is expressed in baudtime units. If the smartcard does not send a new character in less
than the CWT period after the end of the previous character, the USART signals this to the
software through the RTOF flag and interrupt (when RTOIE bit is set).
Note: The RTO counter starts counting:
- From the end of the stop bit in case STOP = 00.
- From the end of the second stop bit in case of STOP = 10.
- 1 bit duration after the beginning of the STOP bit in case STOP = 11.
- From the beginning of the STOP bit in case STOP = 01.
As in the Smartcard protocol definition, the BWT/CWT values are defined from the
beginning (start bit) of the last character. The RTO register must be programmed to BWT -
11 or CWT -11, respectively, taking into account the length of the last character itself.
A block length counter is used to count all the characters received by the USART. This
counter is reset when the USART is transmitting (TXE=0). The length of the block is
communicated by the smartcard in the third byte of the block (prologue field). This value
must be programmed to the BLEN field in the USART_RTOR register. when using DMA
mode, before the start of the block, this register field must be programmed to the minimum
value (0x0). with this value, an interrupt is generated after the 4th received character. The
software must read the LEN field (third byte), its value must be read from the receive buffer.
In interrupt driven receive mode, the length of the block may be checked by software or by
programming the BLEN value. However, before the start of the block, the maximum value of
BLEN (0xFF) may be programmed. The real value will be programmed after the reception of
the third character.
If the block is using the LRC longitudinal redundancy check (1 epilogue byte), the
BLEN=LEN. If the block is using the CRC mechanism (2 epilogue bytes), BLEN=LEN+1
must be programmed. The total block length (including prologue, epilogue and information
fields) equals BLEN+4. The end of the block is signaled to the software through the EOBF
flag and interrupt (when EOBIE bit is set).

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In case of an error in the block length, the end of the block is signaled by the RTO interrupt
(Character wait Time overflow).
Note: The error checking code (LRC/CRC) must be computed/verified by software.

Direct and inverse convention

The Smartcard protocol defines two conventions: direct and inverse.
The direct convention is defined as: LSB first, logical bit value of 1 corresponds to a H state
of the line and parity is even. In order to use this convention, the following control bits must
be programmed: MSBFIRST=0, DATAINV=0 (default values).
The inverse convention is defined as: MSB first, logical bit value 1 corresponds to an L state
on the signal line and parity is even. In order to use this convention, the following control bits
must be programmed: MSBFIRST=1, DATAINV=1.
Note: When logical data values are inverted (0=H, 1=L), the parity bit is also inverted in the same
way.
In order to recognize the card convention, the card sends the initial character, TS, as the
first character of the ATR (Answer To Reset) frame. The two possible patterns for the TS
are: LHHL LLL LLH and LHHL HHH LLH.
• (H) LHHL LLL LLH sets up the inverse convention: state L encodes value 1 and
moment 2 conveys the most significant bit (MSB first). when decoded by inverse
convention, the conveyed byte is equal to '3F'.
• (H) LHHL HHH LLH sets up the direct convention: state H encodes value 1 and
moment 2 conveys the least significant bit (LSB first). when decoded by direct
convention, the conveyed byte is equal to '3B'.
Character parity is correct when there is an even number of bits set to 1 in the nine
moments 2 to 10.
As the USART does not know which convention is used by the card, it needs to be able to
recognize either pattern and act accordingly. The pattern recognition is not done in
hardware, but through a software sequence. Moreover, supposing that the USART is
configured in direct convention (default) and the card answers with the inverse convention,
TS = LHHL LLL LLH => the USART received character will be ‘03’ and the parity will be odd.
Therefore, two methods are available for TS pattern recognition:
Method 1
The USART is programmed in standard Smartcard mode/direct convention. In this case, the
TS pattern reception generates a parity error interrupt and error signal to the card.
• The parity error interrupt informs the software that the card didn’t answer correctly in
direct convention. Software then reprograms the USART for inverse convention
• In response to the error signal, the card retries the same TS character, and it will be
correctly received this time, by the reprogrammed USART
Alternatively, in answer to the parity error interrupt, the software may decide to reprogram
the USART and to also generate a new reset command to the card, then wait again for the
TS.

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Method 2
The USART is programmed in 9-bit/no-parity mode, no bit inversion. In this mode it receives
any of the two TS patterns as:
(H) LHHL LLL LLH = 0x103 -> inverse convention to be chosen
(H) LHHL HHH LLH = 0x13B -> direct convention to be chosen
The software checks the received character against these two patterns and, if any of them
match, then programs the USART accordingly for the next character reception.
If none of the two is recognized, a card reset may be generated in order to restart the
negotiation.

24.5.14 USART IrDA SIR ENDEC block

This section is relevant only when IrDA mode is supported. Please refer to Section 24.4:
USART implementation on page 659.
IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA mode,
the following bits must be kept cleared:
• LINEN, STOP and CLKEN bits in the USART_CR2 register,
• SCEN and HDSEL bits in the USART_CR3 register.
The IrDA SIR physical layer specifies use of a Return to Zero, Inverted (RZI) modulation
scheme that represents logic 0 as an infrared light pulse (see Figure 230).
The SIR Transmit encoder modulates the Non Return to Zero (NRZ) transmit bit stream
output from USART. The output pulse stream is transmitted to an external output driver and
infrared LED. USART supports only bit rates up to 115.2 Kbps for the SIR ENDEC. In
normal mode the transmitted pulse width is specified as 3/16 of a bit period.
The SIR receive decoder demodulates the return-to-zero bit stream from the infrared
detector and outputs the received NRZ serial bit stream to the USART. The decoder input is
normally high (marking state) in the Idle state. The transmit encoder output has the opposite
polarity to the decoder input. A start bit is detected when the decoder input is low.
• IrDA is a half duplex communication protocol. If the Transmitter is busy (when the
USART is sending data to the IrDA encoder), any data on the IrDA receive line is
ignored by the IrDA decoder and if the Receiver is busy (when the USART is receiving
decoded data from the IrDA decoder), data on the TX from the USART to IrDA is not
encoded. while receiving data, transmission should be avoided as the data to be
transmitted could be corrupted.
• A 0 is transmitted as a high pulse and a 1 is transmitted as a 0. The width of the pulse
is specified as 3/16th of the selected bit period in normal mode (see Figure 231).
• The SIR decoder converts the IrDA compliant receive signal into a bit stream for
USART.
• The SIR receive logic interprets a high state as a logic one and low pulses as logic
zeros.
• The transmit encoder output has the opposite polarity to the decoder input. The SIR
output is in low state when Idle.

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• The IrDA specification requires the acceptance of pulses greater than 1.41 µs. The
acceptable pulse width is programmable. Glitch detection logic on the receiver end
filters out pulses of width less than 2 PSC periods (PSC is the prescaler value
programmed in the USART_GTPR). Pulses of width less than 1 PSC period are always
rejected, but those of width greater than one and less than two periods may be
accepted or rejected, those greater than 2 periods will be accepted as a pulse. The
IrDA encoder/decoder doesn’t work when PSC=0.
• The receiver can communicate with a low-power transmitter.
• In IrDA mode, the STOP bits in the USART_CR2 register must be configured to “1 stop
bit”.
For code example, refer to A.15.10: USART IrDA mode code example.

IrDA low-power mode

Transmitter
In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the
width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz.
Generally, this value is 1.8432 MHz (1.42 MHz < PSC< 2.12 MHz). A low-power mode
programmable divisor divides the system clock to achieve this value.
Receiver
Receiving in low-power mode is similar to receiving in normal mode. For glitch detection the
USART should discard pulses of duration shorter than 1 PSC period. A valid low is accepted
only if its duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in
the USART_GTPR).
Note: A pulse of width less than two and greater than one PSC period(s) may or may not be
rejected.
The receiver set up time should be managed by software. The IrDA physical layer
specification specifies a minimum of 10 ms delay between transmission and reception (IrDA
is a half duplex protocol).

Figure 230. IrDA SIR ENDEC- block diagram

SIREN
TX
OR USART_TX

SIR
Transmit IrDA_OUT
Encoder
USART

SIR
RX
Receive IrDA_IN
DEcoder

USART_RX

MSv31164V2

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Figure 231. IrDA data modulation (3/16) -Normal Mode

Start Stop
bit bit
0 1 0 1 0 0 1 1 0 1
TX

IrDA_OUT
Bit period 3/16
IrDA_IN

RX 0 1 0 1 0 0 1 1 0 1

MSv31165V1

24.5.15 USART continuous communication in DMA mode

The USART is capable of performing continuous communication using the DMA. The DMA
requests for Rx buffer and Tx buffer are generated independently.
Note: Please refer to Section 24.4: USART implementation on page 659 to determine if the DMA
mode is supported. If DMA is not supported, use the USART as explained in Section 24.5.2:
USART transmitter or Section 24.5.3: USART receiver. To perform continuous
communication, the user can clear the TXE/ RXNE flags In the USART_ISR register.
For code example, refer to A.15.11: USART DMA code example.

Transmission using DMA

DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3
register. Data is loaded from a SRAM area configured using the DMA peripheral (refer to
Section 10: Direct memory access controller (DMA) on page 241) to the USART_TDR
register whenever the TXE bit is set. To map a DMA channel for USART transmission, use
the following procedure (x denotes the channel number):
1. Write the USART_TDR register address in the DMA control register to configure it as
the destination of the transfer. The data is moved to this address from memory after
each TXE event.
2. Write the memory address in the DMA control register to configure it as the source of
the transfer. The data is loaded into the USART_TDR register from this memory area
after each TXE event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA register
5. Configure DMA interrupt generation after half/ full transfer as required by the
application.
6. Clear the TC flag in the USART_ISR register by setting the TCCF bit in the
USART_ICR register.
7. Activate the channel in the DMA register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.

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In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag
is set in the DMA_ISR register), the TC flag can be monitored to make sure that the USART
communication is complete. This is required to avoid corrupting the last transmission before
disabling the USART or entering Stop mode. Software must wait until TC=1. The TC flag
remains cleared during all data transfers and it is set by hardware at the end of transmission
of the last frame.

Figure 232. Transmission using DMA

Idle preamble Frame 1 Frame 2 Frame 3
TX line

Set by hardware Set by hardware

TXE flag cleared by DMA read cleared by DMA read Set by hardware

DMA request Ignored by the DMA because

the transfer is complete

USART_TDR F1 F2 F3

TC flag Set by
hardware
DMA writes
USART_TDR
Cleared
DMA TCIF flag by
Set by hardware software
(transfer
complete)

Software The DMA

configures DMA DMA writes DMA writes DMA writes transfer is
to send 3 data F1 into F2 into F3 into complete Software waits until TC=1
blocks and USART_TDR USART_TDR USART_TDR (TCIF=1 in
enables USART DMA_ISR)

ai17192b

Reception using DMA

DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register.
Data is loaded from the USART_RDR register to a SRAM area configured using the DMA
peripheral (refer to Section 10: Direct memory access controller (DMA) on page 241)
whenever a data byte is received. To map a DMA channel for USART reception, use the
following procedure:
1. Write the USART_RDR register address in the DMA control register to configure it as
the source of the transfer. The data is moved from this address to the memory after
each RXNE event.
2. Write the memory address in the DMA control register to configure it as the destination
of the transfer. The data is loaded from USART_RDR to this memory area after each
RXNE event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA control register
5. Configure interrupt generation after half/ full transfer as required by the application.
6. Activate the channel in the DMA control register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.

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Figure 233. Reception using DMA

Frame 1 Frame 2 Frame 3

TX line

Set by hardware
RXNE flag cleared by DMA read

DMA request

USART_RDR F1 F2 F3

DMA reads
USART_RDR
Cleared
DMA TCIF flag Set by hardware by
(transfer complete) software

Software configures the The DMA transfer

DMA to receive 3 data DMA reads F1 DMA reads F2 DMA reads F3 is complete
blocks and enables from USART_RDR from USART_RDR from USART_RDR (TCIF=1 in
the USART DMA_ISR)
ai17193c

Error flagging and interrupt generation in multibuffer communication

In multibuffer communication if any error occurs during the transaction the error flag is
asserted after the current byte. An interrupt is generated if the interrupt enable flag is set.
For framing error, overrun error and noise flag which are asserted with RXNE in single byte
reception, there is a separate error flag interrupt enable bit (EIE bit in the USART_CR3
register), which, if set, enables an interrupt after the current byte if any of these errors occur.

24.5.16 RS232 hardware flow control and RS485 driver enable

using USART
It is possible to control the serial data flow between 2 devices by using the CTS input and
the RTS output. The Figure 234 shows how to connect 2 devices in this mode:

Figure 234. Hardware flow control between 2 USARTs

USART 1 USART 2

TX RX
TX circuit RX circuit
CTS RTS

RX TX
RX circuit TX circuit
RTS CTS

MSv31169V2

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RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and
CTSE bits respectively to 1 (in the USART_CR3 register).

RS232 RTS flow control

If the RTS flow control is enabled (RTSE=1), then RTS is deasserted (tied low) as long as
the USART receiver is ready to receive a new data. When the receive register is full, RTS is
asserted, indicating that the transmission is expected to stop at the end of the current frame.
Figure 235 shows an example of communication with RTS flow control enabled.

Figure 235. RS232 RTS flow control

Start Stop Start Stop

RX Data 1 Idle Data 2
bit bit bit bit

RTS

RXNE Data 1 read RXNE

Data 2 can now be transmitted

MSv68794V1

RS232 CTS flow control

If the CTS flow control is enabled (CTSE=1), then the transmitter checks the CTS input
before transmitting the next frame. If CTS is deasserted (tied low), then the next data is
transmitted (assuming that data is to be transmitted, in other words, if TXE=0), else the
transmission does not occur. when CTS is asserted during a transmission, the current
transmission is completed before the transmitter stops.
When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the CTS
input toggles. It indicates when the receiver becomes ready or not ready for communication.
An interrupt is generated if the CTSIE bit in the USART_CR3 register is set. Figure 236
shows an example of communication with CTS flow control enabled.

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Figure 236. RS232 CTS flow control

CTS CTS

CTS

Transmit data register

TDR Data 2 empty Data 3 empty

Stop Start Stop Start

TX Data 1 Data 2 Idle Data 3
bit bit bit bit

Writing data 3 in TDR Transmission of Data 3 is

delayed until CTS = 0
MSv68793V1

Note: For correct behavior, CTS must be deasserted at least 3 USART clock source periods
before the end of the current character. In addition it should be noted that the CTSCF flag
may not be set for pulses shorter than 2 x PCLK periods.
For code example, refer to A.15.12: USART hardware flow control code example.

RS485 Driver Enable

The driver enable feature is enabled by setting bit DEM in the USART_CR3 control register.
This allows the user to activate the external transceiver control, through the DE (Driver
Enable) signal. The assertion time is the time between the activation of the DE signal and
the beginning of the START bit. It is programmed using the DEAT [4:0] bit fields in the
USART_CR1 control register. The de-assertion time is the time between the end of the last
stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed
using the DEDT [4:0] bit fields in the USART_CR1 control register. The polarity of the DE
signal can be configured using the DEP bit in the USART_CR3 control register.
In USART, the DEAT and DEDT are expressed in sample time units (1/8 or 1/16 bit duration,
depending on the oversampling rate).

24.5.17 Wakeup from Stop mode using USART

The USART is able to wake up the MCU from Stopmode when the UESM bit is set and the
USART clock is set to HSI or LSE (refer to Section Reset and clock control (RCC)).
• USART source clock is HSI
If during Stop mode the HSI clock is switched OFF, when a falling edge on the USART
receive line is detected, the USART interface requests the HSI clock to be switched
ON. The HSI clock is then used for the frame reception.
– If the wakeup event is verified, the MCU wakes up from low-power mode and data
reception goes on normally.
– If the wakeup event is not verified, the HSI clock is switched OFF again, the MCU
is not waken up and stays in low-power mode and the clock request is released.

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Note: If the USART kernel clock is kept ON during Stop mode, there is no constraint on the
maximum baud rate that allows waking up from Stop mode. It is the same as in Run mode.
• USART source clock is LSE
Same principle as described in case of USART source clock is HSI with the difference
that the LSE is ON in Stop mode, but the LSE clock is not propagated to USART if the
USART is not requesting it. The LSE clock is not OFF but there is a clock gating to
avoid useless consumption.
When the USART clock source is configured to be fLSE or fHSI, it is possible to keep enabled
this clock during STOP mode by setting the UCESM bit in USART_CR3 control register.
The MCU wakeup from Stop mode can be done using the standard RXNE interrupt. In this
case, the RXNEIE bit must be set before entering Stop mode.
Alternatively, a specific interrupt may be selected through the WUS bit fields.
In order to be able to wake up the MCU from Stop mode, the UESM bit in the USART_CR1
control register must be set prior to entering Stop mode.
When the wakeup event is detected, the WUF flag is set by hardware and a wakeup
interrupt is generated if the WUFIE bit is set.
Note: Before entering Stop mode, the user must ensure that the USART is not performing a
transfer. BUSY flag cannot ensure that Stop mode is never entered during a running
reception.
The WUF flag is set when a wakeup event is detected, independently of whether the MCU is
in Stop or in an active mode.
When entering Stop mode just after having initialized and enabled the receiver, the REACK
bit must be checked to ensure the USART is actually enabled.
When DMA is used for reception, it must be disabled before entering Stop mode and re-
enabled upon exit from Stop mode.
The wakeup from Stop mode feature is not available for all modes. For example it doesn’t
work in SPI mode because the SPI operates in master mode only.

Using Mute mode with Stop mode

If the USART is put into Mute mode before entering Stop mode:
• Wakeup from Mute mode on idle detection must not be used, because idle detection
cannot work in Stop mode.
• If the wakeup from Mute mode on address match is used, then the source of wake-up
from Stop mode must also be the address match. If the RXNE flag is set when entering
the Stop mode, the interface will remain in mute mode upon address match and wake
up from Stop.
• If the USART is configured to wake up the MCU from Stop mode on START bit
detection, the WUF flag is set, but the RXNE flag is not set.

Determining the maximum USART baud rate allowing to wakeup correctly

from Stop mode when the USART clock source is the HSI clock
The maximum baud rate allowing to wakeup correctly from Stop mode depends on:
• the parameter tWUUSART provided in the device datasheet
• the USART receiver tolerance provided in the Section 24.5.5: Tolerance of the USART
receiver to clock deviation.

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Let us take this example: OVER8 = 0, M bits = 10, ONEBIT = 1, BRR [3:0] = 0000.
In these conditions, according to Table 120: Tolerance of the USART receiver when BRR
[3:0] = 0000, the USART receiver tolerance is 4.86 %.
DTRA + DQUANT + DREC + DTCL + DWU < USART receiver's tolerance
DWU max = tWUUSART / (9 x Tbit Min)
Tbit Min = tWUUSART / (9 x DWU max)
If we consider an ideal case where the parameters DTRA, DQUANT, DREC and DTCL are
at 0%, the DWU max is 4.86 %. In reality, we need to consider at least the HSI inaccuracy.
Let us consider HSI inaccuracy = 1 %, tWUUSART = 8.1 μs (in case of Stop mode with main
regulator in Run mode, Range 1 ):
DWU max = 4.86 % - 1 % = 3.86 %
Tbit min = 8.1 µs / (9 ₓ 3.86 %) = 23.31 μs.
In these conditions, the maximum baud rate allowing to wakeup correctly from Stop mode is
1/23.31 μs = 42 kbaud.

24.6 USART in low-power modes

Table 123. Effect of low-power modes on the USART
Mode Description

Sleep No effect. USART interrupt causes the device to exit Sleep mode.
Low-power run No effect.
No effect. USART interrupt causes the device to exit Low-power sleep
Low-power sleep
mode.
The USART is able to wake up the MCU from Stop mode when the UESM
bit is set and the USART clock is set to HSI16 or LSE.
Stop
The MCU wakeup from Stop mode can be done using the standard RXNE
interrupt.
The USART is powered down and must be reinitialized when the device
Standby
has exited from Standby mode.

24.7 USART interrupts

Table 124. USART interrupt requests
Enable Control
Interrupt event Event flag
bit

Transmit data register empty TXE TXEIE

CTS interrupt CTSIF CTSIE
Transmission Complete TC TCIE
Receive data register not empty (data ready to be read) RXNE
RXNEIE
Overrun error detected ORE

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Table 124. USART interrupt requests (continued)

Enable Control
Interrupt event Event flag
bit

Idle line detected IDLE IDLEIE

Parity error PE PEIE
LIN break LBDF LBDIE
Noise Flag, Overrun error and Framing Error in multibuffer
NF or ORE or FE EIE
communication.
Character match CMF CMIE
Receiver timeout RTOF RTOIE
End of Block EOBF EOBIE
Wakeup from Stop mode WUF(1) WUFIE
Transmission complete before guard time TCBGT TCBGTIE
1. The WUF interrupt is active only in Stop mode.

The USART interrupt events are connected to the same interrupt vector (see Figure 237).
• During transmission: Transmission Complete, Transmission complete before guard
time, Clear to Send, Transmit data Register empty or Framing error (in Smartcard
mode) interrupt.
• During reception: Idle Line detection, Overrun error, Receive data register not empty,
Parity error, LIN break detection, Noise Flag, Framing Error, Character match, etc.
These events generate an interrupt if the corresponding Enable Control Bit is set.

Figure 237. USART interrupt mapping diagram

TC
TCIE
TXE
TXEIE
CTSIF
CTSIE
IDLE
IDLEIE
RXNEIE USART
ORE interrupt
RXNEIE
RXNE
PE
PEIE
LBDF
LBDIE
FE
NF
ORE EIE
CMF
CMIE
RTOF
RTOIE
EOBF
EOBIE
WUF
WUFIE

MSv19820V1

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24.8 USART registers

Refer to Section 1.2 on page 45 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32 bits).

24.8.1 USART control register 1 (USART_CR1)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. M1 EOBIE RTOIE DEAT[4:0] DEDT[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVER8 CMIE MME M0 WAKE PCE PS PEIE TXEIE TCIE RXNEIE IDLEIE TE RE UESM UE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bit 28 M1: Word length
This bit, with bit 12 (M0), determines the word length. It is set or cleared by software.
M[1:0] = 00: 1 Start bit, 8 data bits, n stop bits
M[1:0] = 01: 1 Start bit, 9 data bits, n stop bits
M[1:0] = 10: 1 Start bit, 7 data bits, n stop bits
This bit can only be written when the USART is disabled (UE=0).
Note: Not all modes are supported In 7-bit data length mode. Refer to Section 24.4: USART
implementation for details.
Bit 27 EOBIE: End of Block interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated when the EOBF flag is set in the USART_ISR register.
Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept
at reset value. Please refer to Section 24.4: USART implementation on page 659.
Bit 26 RTOIE: Receiver timeout interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated when the RTOF bit is set in the USART_ISR register.
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
must be kept at reset value. Section 24.4: USART implementation on page 659.
Bits 25:21 DEAT[4:0]: Driver Enable assertion time
This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and
the beginning of the start bit. It is expressed in sample time units (1/8 or 1/16 bit duration,
depending on the oversampling rate).
This bit field can only be written when the USART is disabled (UE=0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at
reset value. Please refer to Section 24.4: USART implementation on page 659.

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Bits 20:16 DEDT[4:0]: Driver Enable de-assertion time

This 5-bit value defines the time between the end of the last stop bit, in a transmitted
message, and the de-activation of the DE (Driver Enable) signal. It is expressed in sample
time units (1/8 or 1/16 bit duration, depending on the oversampling rate).
If the USART_TDR register is written during the DEDT time, the new data is transmitted only
when the DEDT and DEAT times have both elapsed.
This bit field can only be written when the USART is disabled (UE=0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at
reset value. Please refer to Section 24.4: USART implementation on page 659.
Bit 15 OVER8: Oversampling mode
0: Oversampling by 16
1: Oversampling by 8
This bit can only be written when the USART is disabled (UE=0).
Note: In LIN, IrDA and modes, this bit must be kept at reset value.
Bit 14 CMIE: Character match interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated when the CMF bit is set in the USART_ISR register.
Bit 13 MME: Mute mode enable
This bit activates the mute mode function of the USART. when set, the USART can switch
between the active and mute modes, as defined by the WAKE bit. It is set and cleared by
software.
0: Receiver in active mode permanently
1: Receiver can switch between mute mode and active mode.
Bit 12 M0: Word length
This bit, with bit 28 (M1), determines the word length. It is set or cleared by software. See Bit
28 (M1) description.
This bit can only be written when the USART is disabled (UE=0).
Bit 11 WAKE: Receiver wakeup method
This bit determines the USART wakeup method from Mute mode. It is set or cleared by
software.
0: Idle line
1: Address mark
This bit field can only be written when the USART is disabled (UE=0).
Bit 10 PCE: Parity control enable
This bit selects the hardware parity control (generation and detection). When the parity
control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit
if M=0) and parity is checked on the received data. This bit is set and cleared by software.
Once it is set, PCE is active after the current byte (in reception and in transmission).
0: Parity control disabled
1: Parity control enabled
This bit field can only be written when the USART is disabled (UE=0).
Bit 9 PS: Parity selection
This bit selects the odd or even parity when the parity generation/detection is enabled (PCE
bit set). It is set and cleared by software. The parity will be selected after the current byte.
0: Even parity
1: Odd parity
This bit field can only be written when the USART is disabled (UE=0).

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Bit 8 PEIE: PE interrupt enable

This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever PE=1 in the USART_ISR register
Bit 7 TXEIE: interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever TXE=1 in the USART_ISR register
Bit 6 TCIE: Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever TC=1 in the USART_ISR register
Bit 5 RXNEIE: RXNE interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever ORE=1 or RXNE=1 in the USART_ISR
register
Bit 4 IDLEIE: IDLE interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A USART interrupt is generated whenever IDLE=1 in the USART_ISR register
Bit 3 TE: Transmitter enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Note: During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble
(idle line) after the current word, except in Smartcard mode. In order to generate an idle
character, the TE must not be immediately written to 1. In order to ensure the required
duration, the software can poll the TEACK bit in the USART_ISR register.
In Smartcard mode, when TE is set there is a 1 bit-time delay before the transmission
starts.

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Bit 2 RE: Receiver enable

This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
Bit 1 UESM: USART enable in Stop mode
When this bit is cleared, the USART is not able to wake up the MCU from Stop mode.
When this bit is set, the USART is able to wake up the MCU from Stop mode, provided that
the USART clock selection is HSI16 or LSE in the RCC.
This bit is set and cleared by software.
0: USART not able to wake up the MCU from Stop mode.
1: USART able to wake up the MCU from Stop mode. When this function is active, the clock
source for the USART must be HSI16 or LSE (see Section Reset and clock control
(RCC).
Note: It is recommended to set the UESM bit just before entering Stop mode and clear it on
exit from Stop mode.
If the USART does not support the wakeup from Stop feature, this bit is reserved and
must be kept at reset value. Please refer to Section 24.4: USART implementation on
page 659.
Bit 0 UE: USART enable
When this bit is cleared, the USART prescalers and outputs are stopped immediately, and
current operations are discarded. The configuration of the USART is kept, but all the status
flags, in the USART_ISR are set to their default values. This bit is set and cleared by
software.
0: USART prescaler and outputs disabled, low-power mode
1: USART enabled
Note: In order to go into low-power mode without generating errors on the line, the TE bit
must be reset before and the software must wait for the TC bit in the USART_ISR to be
set before resetting the UE bit.
The DMA requests are also reset when UE = 0 so the DMA channel must be disabled
before resetting the UE bit.

24.8.2 USART control register 2 (USART_CR2)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSBFI
ADD[7:4] ADD[3:0] RTOEN ABRMOD[1:0] ABREN DATAINV TXINV RXINV
RST
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SWAP LINEN STOP[1:0] CLKEN CPOL CPHA LBCL Res. LBDIE LBDL ADDM7 Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:28 ADD[7:4]: Address of the USART node

This bit-field gives the address of the USART node or a character code to be recognized.
This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7-
bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1.
It may also be used for character detection during normal reception, Mute mode inactive (for
example, end of block detection in ModBus protocol). In this case, the whole received character (8-
bit) is compared to the ADD[7:0] value and CMF flag is set on match.
This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled
(UE=0)
Bits 27:24 ADD[3:0]: Address of the USART node
This bit-field gives the address of the USART node or a character code to be recognized.
This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with
address mark detection.
This bit field can only be written when reception is disabled (RE = 0) or the USART is disabled
(UE=0)
Bit 23 RTOEN: Receiver timeout enable
This bit is set and cleared by software.
0: Receiver timeout feature disabled.
1: Receiver timeout feature enabled.
When this feature is enabled, the RTOF flag in the USART_ISR register is set if the RX line is idle
(no reception) for the duration programmed in the RTOR (receiver timeout register).
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and must be
kept at reset value. Please refer to Section 24.4: USART implementation on page 659.
Bits 22:21 ABRMOD[1:0]: Auto baud rate mode
These bits are set and cleared by software.
00: Measurement of the start bit is used to detect the baud rate.
01: Falling edge to falling edge measurement. (the received frame must start with a single bit = 1 ->
Frame = Start10xxxxxx)
10: 0x7F frame detection.
11: 0x55 frame detection
This bit field can only be written when ABREN = 0 or the USART is disabled (UE=0).
Note: If DATAINV=1 and/or MSBFIRST=1 the patterns must be the same on the line, for example
0xAA for MSBFIRST)
If the USART does not support the auto baud rate feature, this bit is reserved and must be kept
at reset value. Please refer to Section 24.4: USART implementation on page 659.
Bit 20 ABREN: Auto baud rate enable
This bit is set and cleared by software.
0: Auto baud rate detection is disabled.
1: Auto baud rate detection is enabled.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and must be kept
at reset value. Please refer to Section 24.4: USART implementation on page 659.
Bit 19 MSBFIRST: Most significant bit first
This bit is set and cleared by software.
0: data is transmitted/received with data bit 0 first, following the start bit.
1: data is transmitted/received with the MSB (bit 7/8/9) first, following the start bit.
This bit field can only be written when the USART is disabled (UE=0).

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Bit 18 DATAINV: Binary data inversion

This bit is set and cleared by software.
0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)
1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The
parity bit is also inverted.
This bit field can only be written when the USART is disabled (UE=0).
Bit 17 TXINV: TX pin active level inversion
This bit is set and cleared by software.
0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark)
1: TX pin signal values are inverted. (VDD =0/mark, Gnd=1/idle).
This allows the use of an external inverter on the TX line.
This bit field can only be written when the USART is disabled (UE=0).
Bit 16 RXINV: RX pin active level inversion
This bit is set and cleared by software.
0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark)
1: RX pin signal values are inverted. (VDD =0/mark, Gnd=1/idle).
This allows the use of an external inverter on the RX line.
This bit field can only be written when the USART is disabled (UE=0).
Bit 15 SWAP: Swap TX/RX pins
This bit is set and cleared by software.
0: TX/RX pins are used as defined in standard pinout
1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired
connection to another USART.
This bit field can only be written when the USART is disabled (UE=0).
Bit 14 LINEN: LIN mode enable
This bit is set and cleared by software.
0: LIN mode disabled
1: LIN mode enabled
The LIN mode enables the capability to send LIN synchronous breaks (13 low bits) using the
SBKRQ bit in the USART_RQR register, and to detect LIN Sync breaks.
This bit field can only be written when the USART is disabled (UE=0).
Note: If the USART does not support LIN mode, this bit is reserved and must be kept at reset value.
Please refer to Section 24.4: USART implementation on page 659.
Bits 13:12 STOP[1:0]: STOP bits
These bits are used for programming the stop bits.
00: 1 stop bit
01: 0.5 stop bit
10: 2 stop bits
11: 1.5 stop bits
This bit field can only be written when the USART is disabled (UE=0).

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Bit 11 CLKEN: Clock enable

This bit allows the user to enable the CK pin.
0: CK pin disabled
1: CK pin enabled
This bit can only be written when the USART is disabled (UE=0).
Note: If neither synchronous mode nor Smartcard mode is supported, this bit is reserved and must
be kept at reset value. Please refer to Section 24.4: USART implementation on page 659.
In order to provide correctly the CK clock to the Smartcard when CK is always available When
CLKEN = 1, regardless of the UE bit value, the steps below must be respected:
- UE = 0
- SCEN = 1
- GTPR configuration (If PSC needs to be configured, it is recommended to configure PSC and
GT in a single access to USART_ GTPR register).
- CLKEN= 1
- UE = 1
Bit 10 CPOL: Clock polarity
This bit allows the user to select the polarity of the clock output on the CK pin in synchronous mode.
It works in conjunction with the CPHA bit to produce the desired clock/data relationship
0: Steady low value on CK pin outside transmission window
1: Steady high value on CK pin outside transmission window
This bit can only be written when the USART is disabled (UE=0).
Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value.
Please refer to Section 24.4: USART implementation on page 659.
Bit 9 CPHA: Clock phase
This bit is used to select the phase of the clock output on the CK pin in synchronous mode. It works
in conjunction with the CPOL bit to produce the desired clock/data relationship (see Figure 225 and
Figure 226)
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
This bit can only be written when the USART is disabled (UE=0).
Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value.
Please refer to Section 24.4: USART implementation on page 659.
Bit 8 LBCL: Last bit clock pulse
This bit is used to select whether the clock pulse associated with the last data bit transmitted (MSB)
has to be output on the CK pin in synchronous mode.
0: The clock pulse of the last data bit is not output to the CK pin
1: The clock pulse of the last data bit is output to the CK pin
Caution: The last bit is the 7th or 8th or 9th data bit transmitted depending on the 7 or 8 or 9 bit
format selected by the M bits in the USART_CR1 register.
This bit can only be written when the USART is disabled (UE=0).
Note: If synchronous mode is not supported, this bit is reserved and must be kept at reset value.
Please refer to Section 24.4: USART implementation on page 659.
Bit 7 Reserved, must be kept at reset value.
Bit 6 LBDIE: LIN break detection interrupt enable
Break interrupt mask (break detection using break delimiter).
0: Interrupt is inhibited
1: An interrupt is generated whenever LBDF=1 in the USART_ISR register
Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Please refer
to Section 24.4: USART implementation on page 659.

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Bit 5 LBDL: LIN break detection length

This bit is for selection between 11 bit or 10 bit break detection.
0: 10-bit break detection
1: 11-bit break detection
This bit can only be written when the USART is disabled (UE=0).
Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value. Please refer
to Section 24.4: USART implementation on page 659.
Bit 4 ADDM7:7-bit Address Detection/4-bit Address Detection
This bit is for selection between 4-bit address detection or 7-bit address detection.
0: 4-bit address detection
1: 7-bit address detection (in 8-bit data mode)
This bit can only be written when the USART is disabled (UE=0)
Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address
(ADD[5:0] and ADD[7:0]) respectively.
Bits 3:0 Reserved, must be kept at reset value.

Note: The 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled.

24.8.3 USART control register 3 (USART_CR3)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCBGT SCARC SCARC SCARC
Res. Res. Res. Res. Res. Res. Res. UCESM WUFIE WUS1 WUS0 Res.
IE NT2 NT1 NT0
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVRDI ONEBI
DEP DEM DDRE CTSIE CTSE RTSE DMAT DMAR SCEN NACK HDSEL IRLP IREN EIE
S T
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 TCBGTIE: Transmission complete before guard time interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever TCBGT=1 in the USART_ISR register.
Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value
(see Section 24.4: USART implementation).
Note: This bit is available on category 1 devices only.
Bit 23 UCESM: USART Clock Enable in Stop mode.
This bit is set and cleared by software.
0: USART Clock is disabled in STOP mode.
1: USART Clock is enabled in STOP mode.

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Bit 22 WUFIE: Wakeup from Stop mode interrupt enable

This bit is set and cleared by software.
0: Interrupt is inhibited
1: An USART interrupt is generated whenever WUF=1 in the USART_ISR register
Note: WUFIE must be set before entering in Stop mode.
The WUF interrupt is active only in Stop mode.
If the USART does not support the wakeup from Stop feature, this bit is reserved and
must be kept at reset value.
Bits 21:20 WUS[1:0]: Wakeup from Stop mode interrupt flag selection
This bit-field specify the event which activates the WUF (wakeup from Stop mode flag).
00: WUF active on address match (as defined by ADD[7:0] and ADDM7)
01:Reserved.
10: WuF active on Start bit detection
11: WUF active on RXNE.
This bit field can only be written when the USART is disabled (UE=0).
Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and
must be kept at reset value.
Bits 19:17 SCARCNT[2:0]: Smartcard auto-retry count
This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
In transmission mode, it specifies the number of automatic retransmission retries, before
generating a transmission error (FE bit set).
In reception mode, it specifies the number or erroneous reception trials, before generating a
reception error (RXNE and PE bits set).
This bit field must be programmed only when the USART is disabled (UE=0).
When the USART is enabled (UE=1), this bit field may only be written to 0x0, in order to stop
retransmission.
0x0: retransmission disabled - No automatic retransmission in transmit mode.
0x1 to 0x7: number of automatic retransmission attempts (before signaling error)
Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset
value. Please refer to Section 24.4: USART implementation on page 659.
Bit 16 Reserved, must be kept at reset value.
Bit 15 DEP: Driver enable polarity selection
0: DE signal is active high.
1: DE signal is active low.
This bit can only be written when the USART is disabled (UE=0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at
reset value. Please refer to Section 24.4: USART implementation on page 659.
Bit 14 DEM: Driver enable mode
This bit allows the user to activate the external transceiver control, through the DE signal.
0: DE function is disabled.
1: DE function is enabled. The DE signal is output on the RTS pin.
This bit can only be written when the USART is disabled (UE=0).
Note: If the Driver Enable feature is not supported, this bit is reserved and must be kept at
reset value. Section 24.4: USART implementation on page 659.

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Bit 13 DDRE: DMA Disable on Reception Error

0: DMA is not disabled in case of reception error. The corresponding error flag is set but
RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not
asserted, so the erroneous data is not transferred (no DMA request), but next correct
received data will be transferred (used for Smartcard mode).
1: DMA is disabled following a reception error. The corresponding error flag is set, as well as
RXNE. The DMA request is masked until the error flag is cleared. This means that the
software must first disable the DMA request (DMAR = 0) or clear RXNE before clearing the
error flag.
This bit can only be written when the USART is disabled (UE=0).
Note: The reception errors are: parity error, framing error or noise error.
Bit 12 OVRDIS: Overrun Disable
This bit is used to disable the receive overrun detection.
0: Overrun Error Flag, ORE, is set when received data is not read before receiving new data.
1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
the ORE flag is not set and the new received data overwrites the previous content of the
USART_RDR register.
This bit can only be written when the USART is disabled (UE=0).
Note: This control bit allows checking the communication flow without reading the data.
Bit 11 ONEBIT: One sample bit method enable
This bit allows the user to select the sample method. When the one sample bit method is
selected the noise detection flag (NF) is disabled.
0: Three sample bit method
1: One sample bit method
This bit can only be written when the USART is disabled (UE=0).
Note: ONEBIT feature applies only to data bits, It does not apply to Start bit.
Bit 10 CTSIE: CTS interrupt enable
0: Interrupt is inhibited
1: An interrupt is generated whenever CTSIF=1 in the USART_ISR register
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
kept at reset value. Please refer to Section 24.4: USART implementation on page 659.
Bit 9 CTSE: CTS enable
0: CTS hardware flow control disabled
1: CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0).
If the CTS input is asserted while data is being transmitted, then the transmission is
completed before stopping. If data is written into the data register while CTS is asserted, the
transmission is postponed until CTS is deasserted.
This bit can only be written when the USART is disabled (UE=0)
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
kept at reset value. Please refer to Section 24.4: USART implementation on page 659.
Bit 8 RTSE: RTS enable
0: RTS hardware flow control disabled
1: RTS output enabled, data is only requested when there is space in the receive buffer. The
transmission of data is expected to cease after the current character has been transmitted.
The RTS output is deasserted (pulled to 0) when data can be received.
This bit can only be written when the USART is disabled (UE=0).
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
kept at reset value. Please refer to Section 24.4: USART implementation on page 659.

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Bit 7 DMAT: DMA enable transmitter

This bit is set/reset by software
1: DMA mode is enabled for transmission
0: DMA mode is disabled for transmission
Bit 6 DMAR: DMA enable receiver
This bit is set/reset by software
1: DMA mode is enabled for reception
0: DMA mode is disabled for reception
Bit 5 SCEN: Smartcard mode enable
This bit is used for enabling Smartcard mode.
0: Smartcard Mode disabled
1: Smartcard Mode enabled
This bit field can only be written when the USART is disabled (UE=0).
Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept
at reset value. Please refer to Section 24.4: USART implementation on page 659.
Bit 4 NACK: Smartcard NACK enable
0: NACK transmission in case of parity error is disabled
1: NACK transmission during parity error is enabled
This bit field can only be written when the USART is disabled (UE=0).
Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept
at reset value. Please refer to Section 24.4: USART implementation on page 659.
Bit 3 HDSEL: Half-duplex selection
Selection of Single-wire Half-duplex mode
0: Half duplex mode is not selected
1: Half duplex mode is selected
This bit can only be written when the USART is disabled (UE=0).
Bit 2 IRLP: IrDA low-power
This bit is used for selecting between normal and low-power IrDA modes
0: Normal mode
1: Low-power mode
This bit can only be written when the USART is disabled (UE=0).
Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value.
Please refer to Section 24.4: USART implementation on page 659.
Bit 1 IREN: IrDA mode enable
This bit is set and cleared by software.
0: IrDA disabled
1: IrDA enabled
This bit can only be written when the USART is disabled (UE=0).
Note: If IrDA mode is not supported, this bit is reserved and must be kept at reset value.
Please refer to Section 24.4: USART implementation on page 659.
Bit 0 EIE: Error interrupt enable
Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing
error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USART_ISR register).
0: Interrupt is inhibited
1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USART_ISR register.

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24.8.4 USART baud rate register (USART_BRR)

This register can only be written when the USART is disabled (UE=0). It may be
automatically updated by hardware in auto baud rate detection mode.
Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:4 BRR[15:4]
BRR[15:4] = USARTDIV[15:4]
Bits 3:0 BRR[3:0]
When OVER8 = 0, BRR[3:0] = USARTDIV[3:0].
When OVER8 = 1:
BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right.
BRR[3] must be kept cleared.

24.8.5 USART guard time and prescaler register (USART_GTPR)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GT[7:0] PSC[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:16 Reserved, must be kept at reset value.

Bits 15:8 GT[7:0]: Guard time value
This bit-field is used to program the Guard time value in terms of number of baud clock
periods.
This is used in Smartcard mode. The Transmission Complete flag is set after this guard time
value.
This bit field can only be written when the USART is disabled (UE=0).
Note: If Smartcard mode is not supported, this bit is reserved and must be kept at reset value.
Please refer to Section 24.4: USART implementation on page 659.
Bits 7:0 PSC[7:0]: Prescaler value
In IrDA Low-power and normal IrDA mode:
PSC[7:0] = IrDA Normal and Low-Power Baud Rate
Used for programming the prescaler for dividing the USART source clock to achieve the low-
power frequency:
The source clock is divided by the value given in the register (8 significant bits):
00000000: Reserved - do not program this value
00000001: divides the source clock by 1
00000010: divides the source clock by 2
...
In Smartcard mode:
PSC[4:0]: Prescaler value
Used for programming the prescaler for dividing the USART source clock to provide the
Smartcard clock.
The value given in the register (5 significant bits) is multiplied by 2 to give the division factor
of the source clock frequency:
00000: Reserved - do not program this value
00001: divides the source clock by 2
00010: divides the source clock by 4
00011: divides the source clock by 6
...
This bit field can only be written when the USART is disabled (UE=0).
Note: Bits [7:5] must be kept at reset value if Smartcard mode is used.
This bit field is reserved and must be kept at reset value when the Smartcard and IrDA
modes are not supported. Please refer to Section 24.4: USART implementation on
page 659.

24.8.6 USART receiver timeout register (USART_RTOR)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BLEN[7:0] RTO[23:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTO[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:24 BLEN[7:0]: Block Length

This bit-field gives the Block length in Smartcard T=1 Reception. Its value equals the number
of information characters + the length of the Epilogue Field (1-LEC/2-CRC) - 1.
Examples:
BLEN = 0 -> 0 information characters + LEC
BLEN = 1 -> 0 information characters + CRC
BLEN = 255 -> 254 information characters + CRC (total 256 characters))
In Smartcard mode, the Block length counter is reset when TXE=0.
This bit-field can be used also in other modes. In this case, the Block length counter is reset
when RE=0 (receiver disabled) and/or when the EOBCF bit is written to 1.
Note: This value can be programmed after the start of the block reception (using the data
from the LEN character in the Prologue Field). It must be programmed only once per
received block.
Bits 23:0 RTO[23:0]: Receiver timeout value
This bit-field gives the Receiver timeout value in terms of number of bit duration.
In standard mode, the RTOF flag is set if, after the last received character, no new start bit is
detected for more than the RTO value.
In Smartcard mode, this value is used to implement the CWT and BWT. See Smartcard
section for more details.
In this case, the timeout measurement is done starting from the Start Bit of the last received
character.
Note: This value must only be programmed once per received character.

Note: RTOR can be written on the fly. If the new value is lower than or equal to the counter, the
RTOF flag is set.
This register is reserved and forced by hardware to “0x00000000” when the Receiver
timeout feature is not supported. Please refer to Section 24.4: USART implementation on
page 659.

24.8.7 USART request register (USART_RQR)

Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TXFRQ RXFRQ MMRQ SBKRQ ABRRQ
w w w w w

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Bits 31:5 Reserved, must be kept at reset value.

Bit 4 TXFRQ: Transmit data flush request
Writing 1 to this bit sets the TXE flag.
This allows to discard the transmit data. This bit must be used only in Smartcard mode,
when data has not been sent due to errors (NACK) and the FE flag is active in the
USART_ISR register.
If the USART does not support Smartcard mode, this bit is reserved and must be kept at
reset value. Please refer to Section 24.4: USART implementation on page 659.
Bit 3 RXFRQ: Receive data flush request
Writing 1 to this bit clears the RXNE flag.
This allows to discard the received data without reading it, and avoid an overrun condition.
Bit 2 MMRQ: Mute mode request
Writing 1 to this bit puts the USART in mute mode and sets the RWU flag.
Bit 1 SBKRQ: Send break request
Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as
the transmit machine is available.
Note: In the case the application needs to send the break character following all previously
inserted data, including the ones not yet transmitted, the software should wait for the
TXE flag assertion before setting the SBKRQ bit.
Bit 0 ABRRQ: Auto baud rate request
Writing 1 to this bit resets the ABRF and ABRE flags in the USART_ISR and request an
automatic baud rate measurement on the next received data frame.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and must
be kept at reset value. Please refer to Section 24.4: USART implementation on
page 659.

24.8.8 USART interrupt and status register (USART_ISR)

Address offset: 0x1C
Reset value: 0x0200 00C0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. TCBGT Res. Res. REACK TEACK WUF RWU SBKF CMF BUSY
r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ABRF ABRE Res. EOBF RTOF CTS CTSIF LBDF TXE TC RXNE IDLE ORE NF FE PE
r r r r r r r r r r r r r r r

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Bits 31:26 Reserved, must be kept at reset value.

Bit 25 TCBGT: Transmission complete before guard time completion.
This bit is used in Smartcard mode. It is set by hardware if the transmission of a frame
containing data has completed successfully (no NACK received from the card) and before
the guard time has elapsed (contrary to the TC flag which is set when the guard time has
elapsed).
An interrupt is generated if TCBGTIE=1 in USART_CR3 register. It is cleared by software,
by writing 1 to TCBGTCF in USART_ICR or by writing to the USART_TDR register.
0: Transmission not complete or transmission completed with error (i.e. NACK received from
the card)
1: Transmission complete (before Guard time has elapsed and no NACK received from the
smartcard).
Note: If the USART does not support the Smartcard mode, this bit is reserved and must be
kept at reset value. If the USART supports the Smartcard mode and the Smartcard
mode is enabled, the TCBGT reset value is 1.
Note: This bit is available on category 1 devices only.
Bits 24:23 Reserved, must be kept at reset value.
Bit 22 REACK: Receive enable acknowledge flag
This bit is set/reset by hardware, when the Receive Enable value is taken into account by
the USART.
When the wakeup from Stop mode is supported, the REACK flag can be used to verify that
the USART is ready for reception before entering Stop mode.
Bit 21 TEACK: Transmit enable acknowledge flag
This bit is set/reset by hardware, when the Transmit Enable value is taken into account by
the USART.
It can be used when an idle frame request is generated by writing TE=0, followed by TE=1
in the USART_CR1 register, in order to respect the TE=0 minimum period.
Bit 20 WUF: Wakeup from Stop mode flag
This bit is set by hardware, when a wakeup event is detected. The event is defined by the
WUS bit field. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register.
An interrupt is generated if WUFIE=1 in the USART_CR3 register.
Note: When UESM is cleared, WUF flag is also cleared.
The WUF interrupt is active only in Stop mode.
If the USART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value.
Bit 19 RWU: Receiver wakeup from Mute mode
This bit indicates if the USART is in mute mode. It is cleared/set by hardware when a
wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE)
is selected by the WAKE bit in the USART_CR1 register.
When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the
MMRQ bit in the USART_RQR register.
0: Receiver in active mode
1: Receiver in mute mode
Bit 18 SBKF: Send break flag
This bit indicates that a send break character was requested. It is set by software, by writing
1 to the SBKRQ bit in the USART_RQR register. It is automatically reset by hardware during
the stop bit of break transmission.
0: No break character is transmitted
1: Break character will be transmitted

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Bit 17 CMF: Character match flag

This bit is set by hardware, when the character defined by ADD[7:0] is received. It is cleared
by software, writing 1 to the CMCF in the USART_ICR register.
An interrupt is generated if CMIE=1in the USART_CR1 register.
0: No Character match detected
1: Character Match detected
Bit 16 BUSY: Busy flag
This bit is set and reset by hardware. It is active when a communication is ongoing on the
RX line (successful start bit detected). It is reset at the end of the reception (successful or
not).
0: USART is idle (no reception)
1: Reception on going
Bit 15 ABRF: Auto baud rate flag
This bit is set by hardware when the automatic baud rate has been set (RXNE will also be
set, generating an interrupt if RXNEIE = 1) or when the auto baud rate operation was
completed without success (ABRE=1) (ABRE, RXNE and FE are also set in this case)
It is cleared by software, in order to request a new auto baud rate detection, by writing 1 to
the ABRRQ in the USART_RQR register.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept
at reset value.
Bit 14 ABRE: Auto baud rate error
This bit is set by hardware if the baud rate measurement failed (baud rate out of range or
character comparison failed)
It is cleared by software, by writing 1 to the ABRRQ bit in the USART_RQR register.
Note: If the USART does not support the auto baud rate feature, this bit is reserved and kept
at reset value.
Bit 13 Reserved, must be kept at reset value.
Bit 12 EOBF: End of block flag
This bit is set by hardware when a complete block has been received (for example T=1
Smartcard mode). The detection is done when the number of received bytes (from the start
of the block, including the prologue) is equal or greater than BLEN + 4.
An interrupt is generated if EOBIE = 1 in the USART_CR1 register.
It is cleared by software, writing 1 to EOBCF in the USART_ICR register.
0: End of Block not reached
1: End of Block (number of characters) reached
Note: If Smartcard mode is not supported, this bit is reserved and kept at reset value. Please
refer to Section 24.4: USART implementation on page 659.

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Bit 11 RTOF: Receiver timeout

This bit is set by hardware when the timeout value, programmed in the RTOR register has
lapsed, without any communication. It is cleared by software, writing 1 to the RTOCF bit in
the USART_ICR register.
An interrupt is generated if RTOIE=1 in the USART_CR1 register.
In Smartcard mode, the timeout corresponds to the CWT or BWT timings.
0: Timeout value not reached
1: Timeout value reached without any data reception
Note: If a time equal to the value programmed in RTOR register separates 2 characters,
RTOF is not set. If this time exceeds this value + 2 sample times (2/16 or 2/8,
depending on the oversampling method), RTOF flag is set.
The counter counts even if RE = 0 but RTOF is set only when RE = 1. If the timeout has
already elapsed when RE is set, then RTOF will be set.
If the USART does not support the Receiver timeout feature, this bit is reserved and
kept at reset value.
Bit 10 CTS: CTS flag
This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin.
0: CTS line set
1: CTS line reset
Note: If the hardware flow control feature is not supported, this bit is reserved and kept at
reset value.
Bit 9 CTSIF: CTS interrupt flag
This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by
software, by writing 1 to the CTSCF bit in the USART_ICR register.
An interrupt is generated if CTSIE=1 in the USART_CR3 register.
0: No change occurred on the CTS status line
1: A change occurred on the CTS status line
Note: If the hardware flow control feature is not supported, this bit is reserved and kept at
reset value.
Bit 8 LBDF: LIN break detection flag
This bit is set by hardware when the LIN break is detected. It is cleared by software, by
writing 1 to the LBDCF in the USART_ICR.
An interrupt is generated if LBDIE = 1 in the USART_CR2 register.
0: LIN Break not detected
1: LIN break detected
Note: If the USART does not support LIN mode, this bit is reserved and kept at reset value.
Please refer to Section 24.4: USART implementation on page 659.
Bit 7 TXE: Transmit data register empty
This bit is set by hardware when the content of the USART_TDR register has been
transferred into the shift register. It is cleared by a write to the USART_TDR register.
The TXE flag can also be cleared by writing 1 to the TXFRQ in the USART_RQR register, in
order to discard the data (only in Smartcard T=0 mode, in case of transmission failure).
An interrupt is generated if the TXEIE bit =1 in the USART_CR1 register.
0: data is not transferred to the shift register
1: data is transferred to the shift register)
Note: This bit is used during single buffer transmission.

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Bit 6 TC: Transmission complete

This bit is set by hardware if the transmission of a frame containing data is complete and if
TXE is set. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is cleared by
software, writing 1 to the TCCF in the USART_ICR register or by a write to the USART_TDR
register.
An interrupt is generated if TCIE=1 in the USART_CR1 register.
0: Transmission is not complete
1: Transmission is complete
Note: If TE bit is reset and no transmission is on going, the TC bit will be set immediately.
Bit 5 RXNE: Read data register not empty
This bit is set by hardware when the content of the RDR shift register has been transferred
to the USART_RDR register. It is cleared by a read to the USART_RDR register. The RXNE
flag can also be cleared by writing 1 to the RXFRQ in the USART_RQR register.
An interrupt is generated if RXNEIE=1 in the USART_CR1 register.
0: data is not received
1: Received data is ready to be read.
Bit 4 IDLE: Idle line detected
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if
IDLEIE=1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in
the USART_ICR register.
0: No Idle line is detected
1: Idle line is detected
Note: The IDLE bit will not be set again until the RXNE bit has been set (i.e. a new idle line
occurs).
If mute mode is enabled (MME=1), IDLE is set if the USART is not mute (RWU=0),
whatever the mute mode selected by the WAKE bit. If RWU=1, IDLE is not set.
Bit 3 ORE: Overrun error
This bit is set by hardware when the data currently being received in the shift register is
ready to be transferred into the RDR register while RXNE=1. It is cleared by a software,
writing 1 to the ORECF, in the USART_ICR register.
An interrupt is generated if RXNEIE=1 or EIE = 1 in the USART_CR1 register.
0: No overrun error
1: Overrun error is detected
Note: When this bit is set, the RDR register content is not lost but the shift register is
overwritten. An interrupt is generated if the ORE flag is set during multibuffer
communication if the EIE bit is set.
This bit is permanently forced to 0 (no overrun detection) when the OVRDIS bit is set in
the USART_CR3 register.

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Bit 2 NF: START bit Noise detection flag

This bit is set by hardware when noise is detected on a received frame. It is cleared by
software, writing 1 to the NFCF bit in the USART_ICR register.
0: No noise is detected
1: Noise is detected
Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit
which itself generates an interrupt. An interrupt is generated when the NF flag is set
during multibuffer communication if the EIE bit is set.
Note: When the line is noise-free, the NF flag can be disabled by programming the ONEBIT
bit to 1 to increase the USART tolerance to deviations (Refer to Section 24.5.5:
Tolerance of the USART receiver to clock deviation on page 674).
Bit 1 FE: Framing error
This bit is set by hardware when a de-synchronization, excessive noise or a break character
is detected. It is cleared by software, writing 1 to the FECF bit in the USART_ICR register.
In Smartcard mode, in transmission, this bit is set when the maximum number of transmit
attempts is reached without success (the card NACKs the data frame).
An interrupt is generated if EIE = 1 in the USART_CR1 register.
0: No Framing error is detected
1: Framing error or break character is detected
Bit 0 PE: Parity error
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by
software, writing 1 to the PECF in the USART_ICR register.
An interrupt is generated if PEIE = 1 in the USART_CR1 register.
0: No parity error
1: Parity error

24.8.9 USART interrupt flag clear register (USART_ICR)

Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WUCF Res. Res. CMCF Res.
rc_w1 rc_w1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCBGT
Res. Res. Res. EOBCF RTOCF Res. CTSCF LBDCF TCCF Res. IDLECF ORECF NCF FECF PECF
CF
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 WUCF: Wakeup from Stop mode clear flag
Writing 1 to this bit clears the WUF flag in the USART_ISR register.
Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and
must be kept at reset value.
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 CMCF: Character match clear flag
Writing 1 to this bit clears the CMF flag in the USART_ISR register.
Bits 16:13 Reserved, must be kept at reset value.

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Bit 12 EOBCF: End of block clear flag

Writing 1 to this bit clears the EOBF flag in the USART_ISR register.
Note: If the USART does not support Smartcard mode, this bit is reserved and must be kept
at reset value. Please refer to Section 24.4: USART implementation on page 659.
Bit 11 RTOCF: Receiver timeout clear flag
Writing 1 to this bit clears the RTOF flag in the USART_ISR register.
Note: If the USART does not support the Receiver timeout feature, this bit is reserved and
must be kept at reset value. Please refer to Section 24.4: USART implementation on
page 659.
Bit 10 Reserved, must be kept at reset value.
Bit 9 CTSCF: CTS clear flag
Writing 1 to this bit clears the CTSIF flag in the USART_ISR register.
Note: If the hardware flow control feature is not supported, this bit is reserved and must be
kept at reset value. Please refer to Section 24.4: USART implementation on page 659.
Bit 8 LBDCF: LIN break detection clear flag
Writing 1 to this bit clears the LBDF flag in the USART_ISR register.
Note: If LIN mode is not supported, this bit is reserved and must be kept at reset value.
Please refer to Section 24.4: USART implementation on page 659.
Bit 7 TCBGTCF: Transmission completed before guard time clear flag
Writing 1 to this bit clears the TCBGT flag in the USART_ISR register.
Note: If the USART does not support SmartCard mode, this bit is reserved and forced by
hardware to 0. Please refer to Section 24.4: USART implementation on page 659).
Note: This bit is available on category 1 devices only.
Bit 6 TCCF: Transmission complete clear flag
Writing 1 to this bit clears the TC flag in the USART_ISR register.
Bit 5 Reserved, must be kept at reset value.
Bit 4 IDLECF: Idle line detected clear flag
Writing 1 to this bit clears the IDLE flag in the USART_ISR register.
Bit 3 ORECF: Overrun error clear flag
Writing 1 to this bit clears the ORE flag in the USART_ISR register.
Bit 2 NCF: Noise detected clear flag
Writing 1 to this bit clears the NF flag in the USART_ISR register.
Bit 1 FECF: Framing error clear flag
Writing 1 to this bit clears the FE flag in the USART_ISR register.
Bit 0 PECF: Parity error clear flag
Writing 1 to this bit clears the PE flag in the USART_ISR register.

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24.8.10 USART receive data register (USART_RDR)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. RDR[8:0]
r r r r r r r r r

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 RDR[8:0]: Receive data value
Contains the received data character.
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 213).
When receiving with the parity enabled, the value read in the MSB bit is the received parity
bit.

24.8.11 USART transmit data register (USART_TDR)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. TDR[8:0]
rw rw rw rw rw rw rw rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 TDR[8:0]: Transmit data value
Contains the data character to be transmitted.
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 213).
When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1 register),
the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect
because it is replaced by the parity.
Note: This register must be written only when TXE=1.

722/905 RM0377 Rev 10

 0x24
0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x1C
0x0C
Offset
RM0377

24.8.12

Register

Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

USART_ISR

USART_ICR
USART_CR3
USART_CR2
USART_CR1

USART_RDR
USART_BRR

USART_RQR
USART_GTPR

USART_RTOR

0
0
Res. Res. Res. Res. Res. Res. Res. Res. 31

0
0
Res. Res. Res. Res. Res. Res. Res. Res. 30

0
0
Res. Res. Res. Res. Res. Res. Res. Res. 29

ADD[7:4]

0
0
0
Res. Res. Res. Res. Res. Res. Res. M1 28

0
0
0
Res. Res. Res. Res. Res. Res. Res. EOBIE 27

BLEN[7:0]

0
0
0
Res. Res. Res. Res. Res. Res. Res. RTOIE 26

1
0
0
0
Res. Res. TCBGT Res. Res. Res. Res. DEAT4 25
USART register map

ADD[3:0]

0
0

0
0
Res. Res. Res. Res. Res. Res. TCBGTIE DEAT3 24

0
0

0
Res. Res. Res. Res. Res. Res. UCESM RTOEN 0 DEAT2 23

0
0
0

0
0
Res. Res. REACK Res. Res. Res. WUFIE ABRMOD1 DEAT1 22

0
0
0

0
0

Res. Res. TEACK Res. Res. Res. ABRMOD0 DEAT0 21

WUS

0
0
0
0

0
0

Res. WUCF WUF Res. Res. Res. ABREN DEDT4 20

0
0
0

0
0

Res. Res. RWU Res. Res. Res. MSBFIRST DEDT3 19

0
0
0

0
0

Res. Res. SBKF Res. Res. Res. SCARCNT2:0] DATAINV DEDT2 18

0
0
0
0

0
0

Res. CMCF CMF Res. Res. Res. TXINV DEDT1 17

RM0377 Rev 10
0
0
0
0

Res. Res. BUSY Res. Res. Res. Res. RXINV DEDT0 16

0
0
0

0
0

0
0
Res. Res. ABRF Res. DEP SWAP OVER8 15

0
0
0

0
0

0
0
Res. Res. ABRE Res. DEM LINEN CMIE 14

0
0

0
0

0
0
Res. Res. Res. Res. DDRE MME 13
[1:0]

0
0
0
0

0
0

0
0
STOP

Res. EOBCF EOBF Res. OVRDIS M0 12

0
0
0
0
0

0
0
0

GT[7:0]
Res. RTOCF RTOF Res. ONEBIT CLKEN WAKE 11

RTO[23:0]

0
0
0
0

0
0
0
Table 125. USART register map and reset values
The table below gives the USART register map and reset values.

Res. Res. CTS Res. CTSIE CPOL PCE 10

0
0
0
0

0
0
0
0

Res. CTSCF CTSIF Res. CTSE CPHA PS 9

0
0
0
0

0
0
0
0

LBDCF LBDF Res. RTSE LBCL PEIE 8

0
1
0
0

0
0
0

TCBGTCF TXE Res. DMAT Res. TXEIE 7

BRR[15:0]

0
1
0
0
0

0
0
0

TCCF TC Res. DMAR LBDIE TCIE 6

0
0
0

0
0
0

Res. RXNE Res. SCEN LBDL RXNEIE 5

0
0
0
0

0
0
0

0
IDLECF IDLE TXFRQ NACK ADDM7 IDLEIE 4

0
0
0
0

0
0
0

X X X X X X
RDR[8:0]
ORECF ORE RXFRQ HDSEL Res. TE 3
PSC[7:0]

0
0
0
0

0
0
0

X
NCF NF MMRQ IRLP Res. RE 2

0
0
0
0

0
0
0

X
FECF FE SBKRQ IREN Res. UESM 1

0
0
0
0

0
0
0

X
PECF PE ABRRQ EIE Res. UE 0
Universal synchronous/asynchronous receiver transmitter (USART/UART)

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Table 125. USART register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
USART_TDR TDR[8:0]
0x28

Reset value X X X X X X X X X

Refer to Section 2.2 on page 51 for the register boundary addresses.

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RM0377 Low-power universal asynchronous receiver transmitter (LPUART)

25 Low-power universal asynchronous receiver

transmitter (LPUART)

25.1 Introduction
The low-power universal asynchronous receiver transmitted (LPUART) is an UART which
allows Full-duplex UART communications with a limited power consumption. Only
32.768 kHz LSE clock is required to allow UART communications up to 9600 baud. Higher
baud rates can be reached when the LPUART is clocked by clock sources different from the
LSE clock.
Even when the microcontroller is in Stop mode, the LPUART can wait for an incoming UART
frame while having an extremely low energy consumption. The LPUART includes all
necessary hardware support to make asynchronous serial communications possible with
minimum power consumption.
It supports Half-duplex Single-wire communications and Modem operations (CTS/RTS).
It also supports multiprocessor communications.
DMA (direct memory access) can be used for data transmission/reception.

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25.2 LPUART main features

• Full-duplex asynchronous communications
• NRZ standard format (mark/space)
• Programmable baud rate from 300 baud to 9600 baud using a 32.768 kHz clock
source. Higher baud rates can be achieved by using a higher frequency clock source
• Dual clock domain allowing
– UART functionality and wakeup from Stop mode
– Convenient baud rate programming independent from the PCLK reprogramming
• Programmable data word length (7 or 8 or 9 bits)
• Programmable data order with MSB-first or LSB-first shifting
• Configurable stop bits (1 or 2 stop bits)
• Single-wire Half-duplex communications
• Continuous communications using DMA
• Received/transmitted bytes are buffered in reserved SRAM using centralized DMA.
• Separate enable bits for transmitter and receiver
• Separate signal polarity control for transmission and reception
• Swappable Tx/Rx pin configuration
• Hardware flow control for modem and RS-485 transceiver
• Transfer detection flags:
– Receive buffer full
– Transmit buffer empty
– Busy and end of transmission flags
• Parity control:
– Transmits parity bit
– Checks parity of received data byte
• Four error detection flags:
– Overrun error
– Noise detection
– Frame error
– Parity error
• Fourteen interrupt sources with flags
• Multiprocessor communications
The LPUART enters mute mode if the address does not match.
• Wakeup from mute mode (by idle line detection or address mark detection)

25.3 LPUART implementation

The STM32L0x1 devices embed one LPUART. Refer to Section 24.4: USART
implementation for LPUART supported features.

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Table 126. STM32L0x1 USART/LPUART features

USART2 USART2
USART modes/features(1) USART1 (category (category USART4 USART5 LPUART1
1 devices) 2, 3 and 5)

Hardware flow control for modem X X X X - X

Continuous communication using
X X X X X X
DMA
Multiprocessor communication X X X X X X
Synchronous mode X - X X X -
Smartcard mode X X X - - -
Single-wire Half-duplex
X X X X X X
communication
Ir SIR ENDEC block X X X - - -
LIN mode X - X - - -
Dual clock domain and wakeup from
X - X - - X
Stop mode
Receiver timeout interrupt X - X - - -
Modbus communication X - X - - -
Auto baud rate detection X - X - - -
Driver Enable X X X X X X
(2),
USART/LPUART data length 7 8 and 9 bits
1. X = supported.
2. In 7-bit data length mode, Smartcard mode, LIN master mode and Auto baud rate (0x7F and 0x55 frame detection) are not
supported.

25.4 LPUART functional description

Any LPUART bidirectional communication requires a minimum of two pins: Receive data In
(RX) and Transmit data Out (TX):
• RX: Receive data Input.
This is the serial data input.
• TX: Transmit data Output.
When the transmitter is disabled, the output pin returns to its I/O port configuration.
When the transmitter is enabled and nothing is to be transmitted, the TX pin is at high
level. In Single-wire mode, this I/O is used to transmit and receive the data.

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Through these pins, serial data is transmitted and received in normal LPUART mode as
frames comprising:
• An Idle Line prior to transmission or reception
• A start bit
• A data word (7 or 8 or 9 bits) least significant bit first
• 1, 2 stop bits indicating that the frame is complete
• The LPUART interface uses a baud rate generator
• A status register (LPUART_ISR)
• Receive and transmit data registers (LPUART_RDR, LPUART_TDR)
• A baud rate register (LPUART_BRR)
Refer to Section 25.7: LPUART registers for the definitions of each bit.
The following pins are required in RS232 Hardware flow control mode:
• CTS: Clear To Send blocks the data transmission at the end of the current transfer
when high
• RTS: Request to send indicates that the LPUART is ready to receive data (when low).
The following pin is required in RS485 Hardware control mode:
• DE: Driver Enable activates the transmission mode of the external transceiver.
Note: DE and RTS share the same pin.

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RM0377 Low-power universal asynchronous receiver transmitter (LPUART)

Figure 238. LPUART block diagram

PRDATA PWDATA
Read Write DR (data register)
(CPU or DMA) (CPU or DMA)

Transmit shift register Receive shift register

TX
Transmit data register Receive data register
(TDR) (RDR)

RX LPUART_GTPR register
GT PSC CK control CK

LPUARTx_CR3 register LPUARTx_CR2 register

LPUARTx_CR2 register
LPUARTx_CR1 register

RTS/ Hardware
DE flow
CTS controller Receiver
clock
Transmit Wakeup Receiver
control unit control

LPUARTx_CR1 register LPUARTx_ISR register

LPUART
interrupt
control

LPUARTx_BRR register
Transmitter
rate controller

Transmitter
/LPUARTDIV BRR[19:0]
clock

fCK ( fLSE , fHSI, Receiver rate

fPCLK or fSYS) controller

Conventional baud rate generator

LPUARTDIV = BBR[19:0] MSv31884V6
TR

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25.4.1 LPUART character description

Word length may be selected as being either 7 or 8 or 9 bits by programming the M[1:0] bits
in the LPUART_CR1 register (see Figure 239).
• 7-bit character length: M[1:0] = 10
• 8-bit character length: M[1:0] = 00
• 9-bit character length: M[1:0] = 01
By default, the signal (TX or RX) is in low state during the start bit. It is in high state during
the stop bit.
These values can be inverted, separately for each signal, through polarity configuration
control.
An Idle character is interpreted as an entire frame of “1”s. (The number of “1”s includes the
number of stop bits).
A Break character is interpreted on receiving “0”s for a frame period. At the end of the
break frame, the transmitter inserts 2 stop bits.
Transmission and reception are driven by a common baud rate generator, the clock for each
is generated when the enable bit is set respectively for the transmitter and receiver.
The details of each block is given below.

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Figure 239. Word length programming

9-bit word length (M = 01 ), 1 Stop bit

Possible
Data frame Parity
bit
Next
Start Stop Start
bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 bit bit

Clock **

Start
Idle frame bit

Break frame Stop Stop Start

bit bit bit

8-bit word length (M = 00 ), 1 Stop bit

Possible
Data frame Parity
bit
Next
Start Stop Start
bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 bit bit

Clock **

Start
Idle frame bit

Break frame Stop Stop Start

bit bit bit

7-bit word length (M = 10 ), 1 Stop bit

Possible
Data frame Parity
bit
Next
Start Stop Start
bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 bit bit

Clock **

Start
Idle frame bit

Break frame Stop Stop Start

bit bit bit

** LBCL bit controls last data clock pulse

MS33194V2

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25.4.2 LPUART transmitter

The transmitter can send data words of either 7 or 8 or 9 bits depending on the M bits status.
The Transmit Enable bit (TE) must be set in order to activate the transmitter function. The
data in the transmit shift register is output on the TX pin.

Character transmission
During an LPUART transmission, data shifts out least significant bit first (default
configuration) on the TX pin. In this mode, the LPUART_TDR register consists of a buffer
(TDR) between the internal bus and the transmit shift register (see Figure 213).
Every character is preceded by a start bit which is a logic level low for one bit period. The
character is terminated by a configurable number of stop bits.
The following stop bits are supported by LPUART: 1 and 2 stop bits.
Note: The TE bit must be set before writing the data to be transmitted to the LPUART_TDR.
The TE bit should not be reset during transmission of data. Resetting the TE bit during the
transmission will corrupt the data on the TX pin as the baud rate counters will get frozen.
The current data being transmitted will be lost.
An idle frame will be sent after the TE bit is enabled.
Configurable stop bits
The number of stop bits to be transmitted with every character can be programmed in
Control register 2, bits 13,12.
• 1 stop bit: This is the default value of number of stop bits.
• 2 stop bits: This will be supported by normal LPUART, Single-wire and Modem
modes.
An idle frame transmission will include the stop bits.
A break transmission will be 10 low bits (when M[1:0] = 00) or 11 low bits (when M[1:0] = 01)
or 9 low bits (when M[1:0] = 10) followed by 2 stop bits. It is not possible to transmit long
breaks (break of length greater than 9/10/11 low bits).

Figure 240. Configurable stop bits

8-bit Word length (M[1:0]=00 bit is reset)

a) 1 Stop bit
Possible
Data frame Next Next data frame
parity bit
start
Start bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Stop
bit
bit
CLOCK **

** LBCL bit controls last data clock pulse

b) 2 Stop bits
Possible
Data frame Next Next data frame
parity bit
start
Start bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 2
bit
Stop
bits
MS31885V1

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RM0377 Low-power universal asynchronous receiver transmitter (LPUART)

Character transmission procedure

1. Program the M bits in LPUART_CR1 to define the word length.
2. Select the desired baud rate using the LPUART_BRR register.
3. Program the number of stop bits in LPUART_CR2.
4. Enable the LPUART by writing the UE bit in LPUART_CR1 register to 1.
5. Select DMA enable (DMAT) in LPUART_CR3 if multibuffer Communication is to take
place. Configure the DMA register as explained in multibuffer communication.
6. Set the TE bit in LPUART_CR1 to send an idle frame as first transmission.
7. Write the data to send in the LPUART_TDR register (this clears the TXE bit). Repeat
this for each data to be transmitted in case of single buffer.
8. After writing the last data into the LPUART_TDR register, wait until TC=1. This
indicates that the transmission of the last frame is complete. This is required for
instance when the LPUART is disabled or enters the Halt mode to avoid corrupting the
last transmission.

Single byte communication

Clearing the TXE bit is always performed by a write to the transmit data register.
The TXE bit is set by hardware and it indicates:
• The data has been moved from the LPUART_TDR register to the shift register and the
data transmission has started.
• The LPUART_TDR register is empty.
• The next data can be written in the LPUART_TDR register without overwriting the
previous data.
This flag generates an interrupt if the TXEIE bit is set.
When a transmission is taking place, a write instruction to the LPUART_TDR register stores
the data in the TDR register; next, the data is copied in the shift register at the end of the
currently ongoing transmission.
When no transmission is taking place, a write instruction to the LPUART_TDR register
places the data in the shift register, the data transmission starts, and the TXE bit is set.
If a frame is transmitted (after the stop bit) and the TXE bit is set, the TC bit goes high. An
interrupt is generated if the TCIE bit is set in the LPUART_CR1 register.
After writing the last data in the LPUART_TDR register, it is mandatory to wait for TC=1
before disabling the LPUART or causing the microcontroller to enter the low-power mode
(see Figure 216: TC/TXE behavior when transmitting).

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Figure 241. TC/TXE behavior when transmitting

Idle preamble Frame 1 Frame 2 Frame 3

TX line
Set by hardware Set by hardware
TXE flag cleared by software cleared by software Set by hardware

LPUART_DR F1 F2 F3
Set by hardware
TC flag

Software
Software waits until TXE=1 TC is not set TC is not set TC is set
enables the and writes F2 into DR
LPUART because TXE=0 because TXE=0 because TXE=1

Software waits until

Software waits until TXE=1 Software waits until TC=1
and writes F1 into DR TXE=1 and writes
F3 into DR

MSv31889V1

Break characters
Setting the SBKRQ bit transmits a break character. The break frame length depends on the
M bits (see Figure 239).
If a ‘1’ is written to the SBKRQ bit, a break character is sent on the TX line after completing
the current character transmission. The SBKF bit is set by the write operation and it is reset
by hardware when the break character is completed (during the stop bits after the break
character). The LPUART inserts a logic 1 signal (STOP) for the duration of 2 bits at the end
of the break frame to guarantee the recognition of the start bit of the next frame.
In the case the application needs to send the break character following all previously
inserted data, including the ones not yet transmitted, the software should wait for the TXE
flag assertion before setting the SBKRQ bit.

Idle characters
Setting the TE bit drives the LPUART to send an idle frame before the first data frame.

25.4.3 LPUART receiver

The LPUART can receive data words of either 7 or 8 or 9 bits depending on the M bits in the
LPUART_CR1 register.

Start bit detection

In LPUART, for START bit detection, a falling edge should be detected first on the Rx line,
then a sample is taken in the middle of the start bit to confirm that it is still ‘0’. If the start
sample is at ‘1’, then the noise error flag (NF) is set, then the START bit is discarded and the
receiver waits for a new START bit. Else, the receiver continues to sample all incoming bits
normally.

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RM0377 Low-power universal asynchronous receiver transmitter (LPUART)

Character reception
During an LPUART reception, data shifts in least significant bit first (default configuration)
through the RX pin. In this mode, the LPUART_RDR register consists of a buffer (RDR)
between the internal bus and the received shift register.
Character reception procedure
1. Program the M bits in LPUART_CR1 to define the word length.
2. Select the desired baud rate using the baud rate register LPUART_BRR
3. Program the number of stop bits in LPUART_CR2.
4. Enable the LPUART by writing the UE bit in LPUART_CR1 register to 1.
5. Select DMA enable (DMAR) in LPUART_CR3 if multibuffer communication is to take
place. Configure the DMA register as explained in multibuffer communication.
6. Set the RE bit LPUART_CR1. This enables the receiver which begins searching for a
start bit.
When a character is received
• The RXNE bit is set. It indicates that the content of the shift register is transferred to the
RDR. In other words, data has been received and can be read (as well as its
associated error flags).
• An interrupt is generated if the RXNEIE bit is set.
• The error flags can be set if a frame error, noise or an overrun error has been detected
during reception. PE flag can also be set with RXNE.
• In multibuffer, RXNE is set after every byte received and is cleared by the DMA read of
the Receive data Register.
• In single buffer mode, clearing the RXNE bit is performed by a software read to the
LPUART_RDR register. The RXNE flag can also be cleared by writing 1 to the RXFRQ
in the LPUART_RQR register. The RXNE bit must be cleared before the end of the
reception of the next character to avoid an overrun error.

Break character
When a break character is received, the LPUART handles it as a framing error.

Idle character
When an idle frame is detected, there is the same procedure as for a received data
character plus an interrupt if the IDLEIE bit is set.

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Overrun error
An overrun error occurs when a character is received when RXNE has not been reset. Data
can not be transferred from the shift register to the RDR register until the RXNE bit is
cleared.
The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set
when the next data is received or the previous DMA request has not been serviced. When
an overrun error occurs:
• The ORE bit is set.
• The RDR content will not be lost. The previous data is available when a read to
LPUART_RDR is performed.
• The shift register will be overwritten. After that point, any data received during overrun
is lost.
• An interrupt is generated if either the RXNEIE bit is set or EIE bit is set.
• The ORE bit is reset by setting the ORECF bit in the ICR register.
Note: The ORE bit, when set, indicates that at least 1 data has been lost. There are two
possibilities:
- if RXNE=1, then the last valid data is stored in the receive register RDR and can be read,
- if RXNE=0, then it means that the last valid data has already been read and thus there is
nothing to be read in the RDR. This case can occur when the last valid data is read in the
RDR at the same time as the new (and lost) data is received.

Selecting the clock source

The choice of the clock source is done through the Reset and Clock Control system (RCC).
The clock source must be chosen before enabling the LPUART (by setting the UE bit).
The choice of the clock source must be done according to two criteria:
• Possible use of the LPUART in low-power mode
• Communication speed.
The clock source frequency is fCK.
When the dual clock domain and the wakeup from Stop mode features are supported, the
clock source can be one of the following sources: fPCLK (default), fLSE, fHSI or fSYS.
Otherwise, the LPUART clock source is fPCLK .
Choosing fLSE, fHSI as clock source may allow the LPUART to receive data while the MCU is
in low-power mode. Depending on the received data and wakeup mode selection, the
LPUART wakes up the MCU, when needed, in order to transfer the received data by
software reading the LPUART_RDR register or by DMA.
For the other clock sources, the system must be active in order to allow LPUART
communication.
The communication speed range (specially the maximum communication speed) is also
determined by the clock source.
The receiver samples each incoming bit as close as possible to the middle of the bit -period.
Only a single sample is taken of each of the incoming bit.
Note: There is no noise detection for data.

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Framing error
A framing error is detected when the stop bit is not recognized on reception at the expected
time, following either a de-synchronization or excessive noise.
When the framing error is detected:
• The FE bit is set by hardware.
• The invalid data is transferred from the Shift register to the LPUART_RDR register.
• No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of
multibuffer communication an interrupt will be issued if the EIE bit is set in the
LPUART_CR3 register.
The FE bit is reset by writing 1 to the FECF in the LPUART_ICR register.

Configurable stop bits during reception

The number of stop bits to be received can be configured through the control bits of Control
Register 2 - it can be either 1 or 2 in normal mode.
• 1 stop bit: Sampling for 1 stop Bit is done on the 8th, 9th and 10th samples.
• 2 stop bits: Sampling for the 2 stop bits is done in the middle of the second stop bit.
The RXNE and FE flags are set just after this sample i.e. during the second stop bit.
The first stop bit is not checked for framing error.

25.4.4 LPUART baud rate generation

The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as
programmed in the LPUART_BRR register.

256 × f CK
Tx/Rx baud = -----------------------------------
-
LPUARTDIV

LPUARTDIV is coded on the LPUART_BRR register.

Note: The baud counters are updated to the new value in the baud registers after a write operation
to LPUART_BRR. Hence the baud rate register value should not be changed during
communication.
It is forbidden to write values less than 0x300 in the LPUART_BRR register.
fck must be in the range [3 x baud rate, 4096 x baud rate].
The maximum baud rate that can be reached when the LPUART clock source is the LSE, is
9600 baud. Higher baud rates can be reached when the LPUART is clocked by clock
sources different than the LSE clock. For example, if the USART clock source is the system
clock (maximum is 32 MHz), the maximum baud rate that can be reached is 10 Mbaud.

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Table 127. Error calculation for programmed baud rates at fck = 32.768 kHz
Baud rate fCK = 32.768 kHz

Value programmed in the baud % Error = (Calculated - Desired)

S.No Desired Actual
rate register B.rate / Desired B.rate

1 300 baud 300 baud 0x6D3A 0

2 600 baud 600 baud 0x369D 0
3 1200 baud 1200.087 baud 0x1B4E 0.007
4 2400 baud 2400.17 baud 0xDA7 0.007
5 4800 baud 4801.72 baud 0x6D3 0.035
6 9600 baud 9608.94 baud 0x369 0.093

Table 128. Error calculation for programmed baud rates at fck = 32 MHz
Baud rate fCK = 32.768 kHz

Value programmed in the baud % Error = (Calculated - Desired)

Desired Actual
rate register B.rate / Desired B.rate

9600 baud 9608.94 baud D0555 0.00004

19200 19200,030 682AA 0,0001
38400 38400,06 34155 0,0001
57600 57600,09 22B8E 0,0001
115200 115200,18 115C7 0,0001
230400 230403,60 8AE3 0,0015
460800 460820,16 4571 0,004
921600 921692,17 22B8 0,01
4000000 4000000,00 800 0
10000000 10002442,00 333 0,024

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25.4.5 Tolerance of the LPUART receiver to clock deviation

The asynchronous receiver of the LPUART works correctly only if the total clock system
deviation is less than the tolerance of the LPUART receiver. The causes which contribute to
the total deviation are:
• DTRA: Deviation due to the transmitter error (which also includes the deviation of the
transmitter’s local oscillator)
• DQUANT: Error due to the baud rate quantization of the receiver
• DREC: Deviation of the receiver’s local oscillator
• DTCL: Deviation due to the transmission line (generally due to the transceivers which
can introduce an asymmetry between the low-to-high transition timing and the high-to-
low transition timing)

DTRA + DQUANT + DREC + DTCL + DWU < LPUART receiver tolerance

where
DWU is the error due to sampling point deviation when the wakeup from Stop mode is
used.
when M[1:0] = 01:
t WULPUART
DWU = -----------------------------
-
11 × Tbit

when M[1:0] = 00:

t WULPUART
DWU = -----------------------------
-
10 × Tbit

when M[1:0] = 10:

t WULPUART
DWU = -----------------------------
-
9 × Tbit

tWULPUART is the time between:

– The detection of start bit falling edge
– The instant when clock (requested by the peripheral) is ready and reaching the
peripheral and regulator is ready.
tWULPUART corresponds to tWUSTOP value provided in the datasheet.
The LPUART receiver can receive data correctly at up to the maximum tolerated deviation
specified in Table 129:
• 7, 8 or 9-bit character length defined by the M bits in the LPUARTx_CR1 register
• 1 or 2 stop bits

Table 129. Tolerance of the LPUART receiver

M bits 768 ≤ BRR <1024 1024 ≤ BRR < 2048 2048 ≤ BRR < 4096 4096 ≤ BRR

8 bits (M=00), 1 stop bit 1.82% 2.56% 3.90% 4.42%

9 bits (M=01), 1 stop bit 1.69% 2.33% 2.53% 4.14%
7 bits (M=10), 1 stop bit 2.08% 2.86% 4.35% 4.42%

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Table 129. Tolerance of the LPUART receiver (continued)

M bits 768 ≤ BRR <1024 1024 ≤ BRR < 2048 2048 ≤ BRR < 4096 4096 ≤ BRR

8 bits (M=00), 2 stop bit 2.08% 2.86% 4.35% 4.42%

9 bits (M=01), 2 stop bit 1.82% 2.56% 3.90% 4.42%
7 bits (M=10), 2stop bit 2.34% 3.23% 4.92% 4.42%

Note: The data specified in Table 129 may slightly differ in the special case when the received
frames contain some Idle frames of exactly 10-bit durations when M bits = 00 (11-bit
durations when M bits =01 or 9- bit durations when M bits = 10).

25.4.6 Multiprocessor communication using LPUART

It is possible to perform multiprocessor communication with the LPUART (with several
LPUARTs connected in a network). For instance one of the LPUARTs can be the master, its
TX output connected to the RX inputs of the other LPUARTs. The others are slaves, their
respective TX outputs are logically ANDed together and connected to the RX input of the
master.
In multiprocessor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant
LPUART service overhead for all non addressed receivers.
The non addressed devices may be placed in mute mode by means of the muting function.
In order to use the mute mode feature, the MME bit must be set in the LPUART_CR1
register.
In mute mode:
• None of the reception status bits can be set.
• All the receive interrupts are inhibited.
• The RWU bit in LPUART_ISR register is set to 1. RWU can be controlled automatically
by hardware or by software, through the MMRQ bit in the LPUART_RQR register,
under certain conditions.
The LPUART can enter or exit from mute mode using one of two methods, depending on
the WAKE bit in the LPUART_CR1 register:
• Idle Line detection if the WAKE bit is reset,
• Address Mark detection if the WAKE bit is set.

Idle line detection (WAKE=0)

The LPUART enters mute mode when the MMRQ bit is written to 1 and the RWU is
automatically set.
It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but
the IDLE bit is not set in the LPUART_ISR register. An example of mute mode behavior
using Idle line detection is given in Figure 220.

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Figure 242. Mute mode using Idle line detection

RXNE RXNE

RX Data 1 Data 2 Data 3 Data 4 IDLE Data 5 Data 6

RWU Mute mode Normal mode

MMRQ written to 1 Idle frame detected

MSv31154V1

Note: If the MMRQ is set while the IDLE character has already elapsed, mute mode will not be
entered (RWU is not set).
If the LPUART is activated while the line is IDLE, the idle state is detected after the duration
of one IDLE frame (not only after the reception of one character frame).

4-bit/7-bit address mark detection (WAKE=1)

In this mode, bytes are recognized as addresses if their MSB is a ‘1’ otherwise they are
considered as data. In an address byte, the address of the targeted receiver is put in the 4
or 7 LSBs. The choice of 7 or 4 bit address detection is done using the ADDM7 bit. This 4-
bit/7-bit word is compared by the receiver with its own address which is programmed in the
ADD bits in the LPUART_CR2 register.
Note: In 7-bit and 9-bit data modes, address detection is done on 6-bit and 8-bit addresses
(ADD[5:0] and ADD[7:0]) respectively.
The LPUART enters mute mode when an address character is received which does not
match its programmed address. In this case, the RWU bit is set by hardware. The RXNE
flag is not set for this address byte and no interrupt or DMA request is issued when the
LPUART enters mute mode.
The LPUART also enters mute mode when the MMRQ bit is written to 1. The RWU bit is
also automatically set in this case.
The LPUART exits from mute mode when an address character is received which matches
the programmed address. Then the RWU bit is cleared and subsequent bytes are received
normally. The RXNE bit is set for the address character since the RWU bit has been
cleared.
An example of mute mode behavior using address mark detection is given in Figure 221.

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Figure 243. Mute mode using address mark detection

In this example, the current address of the receiver is 1

(programmed in the LPUART_CR2 register)
RXNE RXNE RXNE

RX IDLE Addr=0 Data 1 Data 2 IDLE Addr=1 Data 3 Data 4 Addr=2 Data 5

RWU Mute mode Normal mode Mute mode

MMRQ written to 1 Matching address Non-matching address

(RXNE was cleared)

Non-matching address
MSv31888V2

25.4.7 LPUART parity control

Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the LPUART_CR1 register. Depending on the frame
length defined by the M bits, the possible LPUART frame formats are as listed in Table 122.

Table 130. Frame formats

M bits PCE bit LPUART frame(1)

00 0 | SB | 8-bit data | STB |

00 1 | SB | 7-bit data | PB | STB |
01 0 | SB | 9-bit data | STB |
01 1 | SB | 8-bit data | PB | STB |
10 0 | SB | 7-bit data | STB |
10 1 | SB | 6-bit data | PB | STB |
1. Legends: SB: start bit, STB: stop bit, PB: parity bit.
2. In the data register, the PB is always taking the MSB position (9th, 8th or 7th, depending on the M bits
value).

Even parity
The parity bit is calculated to obtain an even number of “1s” inside the frame which is made
of the 6, 7 or 8 LSB bits (depending on M bits values) and the parity bit.
As an example, if data=00110101, and 4 bits are set, then the parity bit will be 0 if even
parity is selected (PS bit in LPUART_CR1 = 0).

Odd parity
The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 6, 7
or 8 LSB bits (depending on M bits values) and the parity bit.
As an example, if data=00110101 and 4 bits set, then the parity bit will be 1 if odd parity is
selected (PS bit in LPUART_CR1 = 1).

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Parity checking in reception

If the parity check fails, the PE flag is set in the LPUART_ISR register and an interrupt is
generated if PEIE is set in the LPUART_CR1 register. The PE flag is cleared by software
writing 1 to the PECF in the LPUART_ICR register.

Parity generation in transmission

If the PCE bit is set in LPUARTx_CR1, then the MSB bit of the data written in the data
register is transmitted but is changed by the parity bit (even number of “1s” if even parity is
selected (PS=0) or an odd number of “1s” if odd parity is selected (PS=1)).

25.4.8 Single-wire Half-duplex communication using LPUART

Single-wire Half-duplex mode is selected by setting the HDSEL bit in the LPUART_CR3
register. In this mode, the following bits must be kept cleared:
• LINEN and CLKEN bits in the LPUART_CR2 register,
• SCEN and IREN bits in the LPUART_CR3 register.
The LPUART can be configured to follow a Single-wire Half-duplex protocol where the TX
and RX lines are internally connected. The selection between half- and Full-duplex
communication is made with a control bit HDSEL in LPUART_CR3.
As soon as HDSEL is written to 1:
• The TX and RX lines are internally connected
• The RX pin is no longer used
• The TX pin is always released when no data is transmitted. Thus, it acts as a standard
I/O in idle or in reception. It means that the I/O must be configured so that TX is
configured as alternate function open-drain with an external pull-up.
Apart from this, the communication protocol is similar to normal LPUART mode. Any
conflicts on the line must be managed by software (by the use of a centralized arbiter, for
instance). In particular, the transmission is never blocked by hardware and continues as
soon as data is written in the data register while the TE bit is set.
Note: In LPUART, in the case of 1-stop bit configuration, the RXNE flag is set in the middle of the
stop bit.

25.4.9 Continuous communication in DMA mode using LPUART

The LPUART is capable of performing continuous communication using the DMA. The DMA
requests for Rx buffer and Tx buffer are generated independently.
Note: Use the LPUART as explained in Section 25.4.3. To perform continuous communication,
you can clear the TXE/ RXNE flags In the LPUART_ISR register.

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Transmission using DMA

DMA mode can be enabled for transmission by setting DMAT bit in the LPUART_CR3
register. Data is loaded from a SRAM area configured using the DMA peripheral (refer to
Section Direct memory access controller (DMA)) to the LPUART_TDR register whenever
the TXE bit is set. To map a DMA channel for LPUART transmission, use the following
procedure (x denotes the channel number):
1. Write the LPUART_TDR register address in the DMA control register to configure it as
the destination of the transfer. The data is moved to this address from memory after
each TXE event.
2. Write the memory address in the DMA control register to configure it as the source of
the transfer. The data is loaded into the LPUART_TDR register from this memory area
after each TXE event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA register
5. Configure DMA interrupt generation after half/ full transfer as required by the
application.
6. Clear the TC flag in the LPUART_ISR register by setting the TCCF bit in the
LPUART_ICR register.
7. Activate the channel in the DMA register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.
In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag
is set in the DMA_ISR register), the TC flag can be monitored to make sure that the
LPUART communication is complete. This is required to avoid corrupting the last
transmission before disabling the LPUART or entering Stop mode. Software must wait until
TC=1. The TC flag remains cleared during all data transfers and it is set by hardware at the
end of transmission of the last frame.

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Figure 244. Transmission using DMA

Idle preamble Frame 1 Frame 2 Frame 3

TX line
Set by hardware cleared Set by hardware cleared by
by DMA read DMA read
TXE flag Set by hardware

DMA request Ignored by the DMA because the transfer

is complete

a
LPUART_TDR F1 F2 F3

TC flag Set by hardware

DMA writes
LPUART_TDR
Cleared by software
DMA TCIF flag(transfer complete) Set by hardware

Software
The DMA
configures DMA writes F1
DMA writes F2 DMA writes F3 transfer is
DMA to send 3 into Software waits until TC=1
into into complete
data blocks
and enables LPUART_TDR LPUART_TDR LPUART_TDR (TCIF=1 in
DMA_ISR)
LPUART

MSv31890V2

Reception using DMA

DMA mode can be enabled for reception by setting the DMAR bit in LPUART_CR3 register.
Data is loaded from the LPUART_RDR register to a SRAM area configured using the DMA
peripheral (refer Section Direct memory access controller (DMA)) whenever a data byte is
received. To map a DMA channel for LPUART reception, use the following procedure:
1. Write the LPUART_RDR register address in the DMA control register to configure it as
the source of the transfer. The data is moved from this address to the memory after
each RXNE event.
2. Write the memory address in the DMA control register to configure it as the destination
of the transfer. The data is loaded from LPUART_RDR to this memory area after each
RXNE event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA control register
5. Configure interrupt generation after half/ full transfer as required by the application.
6. Activate the channel in the DMA control register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.

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Figure 245. Reception using DMA

Frame 1 Frame 2 Frame 3

TX line
Set by hardware
RXNE flag cleared by DMA read

DMA request

LPUART_RDR F1 F2 F3
DMA reads
LPUART_RDR
Cleared by
DMA TCIF flag Set by hardware software
(transfer complete)

Software configures DMA transfer is

DMA reads F1 DMA reads F2 DMA reads F3
the DMA to receive 3 complete
from from from
datablocks and (TCIF=1 in
LPUART_RDR LPUART_RDR LPUART_RDR
enables the LPUART DMA_ISR)

MSv31891V3

Error flagging and interrupt generation in multibuffer communication

In multibuffer communication if any error occurs during the transaction the error flag is
asserted after the current byte. An interrupt is generated if the interrupt enable flag is set.
For framing error, overrun error and noise flag which are asserted with RXNE in single byte
reception, there is a separate error flag interrupt enable bit (EIE bit in the LPUART_CR3
register), which, if set, enables an interrupt after the current byte if any of these errors occur.

25.4.10 RS232 Hardware flow control and RS485 Driver Enable

using LPUART
It is possible to control the serial data flow between 2 devices by using the CTS input and
the RTS output. The Figure 234 shows how to connect 2 devices in this mode:

Figure 246. Hardware flow control between 2 LPUARTs

LPUART 1 LPUART 2
TX RX
TX circuit RX circuit
CTS RTS

RX TX
RX circuit TX circuit
RTS CTS

MSv31892V2

RS232 RTS and CTS flow control can be enabled independently by writing the RTSE and
CTSE bits respectively to 1 (in the LPUART_CR3 register).

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RS232 RTS flow control

If the RTS flow control is enabled (RTSE=1), then RTS is deasserted (tied low) as long as
the LPUART receiver is ready to receive a new data. when the receive register is full, RTS is
asserted, indicating that the transmission is expected to stop at the end of the current frame.
Figure 235 shows an example of communication with RTS flow control enabled.

Figure 247. RS232 RTS flow control

Start Stop Start Stop

RX Data 1 Idle Data 2
bit bit bit bit

RTS

RXNE Data 1 read RXNE

Data 2 can now be transmitted

MSv68794V1

RS232 CTS flow control

If the CTS flow control is enabled (CTSE=1), then the transmitter checks the CTS input
before transmitting the next frame. If CTS is deasserted (tied low), then the next data is
transmitted (assuming that data is to be transmitted, in other words, if TXE=0), else the
transmission does not occur. When CTS is asserted during a transmission, the current
transmission is completed before the transmitter stops.
When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the CTS
input toggles. It indicates when the receiver becomes ready or not ready for communication.
An interrupt is generated if the CTSIE bit in the LPUART_CR3 register is set. Figure 236
shows an example of communication with CTS flow control enabled.

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Figure 248. RS232 CTS flow control

CTS CTS

CTS

Transmit data register

TDR Data 2 empty Data 3 empty

Stop Start Stop Start

TX Data 1 Data 2 Idle Data 3
bit bit bit bit

Writing data 3 in TDR Transmission of Data 3 is

delayed until CTS = 0
MSv68793V1

Note: For correct behavior, CTS must be deasserted at least 3 LPUART clock source periods
before the end of the current character. In addition it should be noted that the CTSCF flag
may not be set for pulses shorter than 2 x PCLK periods.

RS485 Driver Enable

The driver enable feature is enabled by setting bit DEM in the LPUART_CR3 control
register. This allows the user to activate the external transceiver control, through the DE
(Driver Enable) signal. The assertion time is the time between the activation of the DE signal
and the beginning of the START bit. It is programmed using the DEAT [4:0] bit fields in the
LPUART_CR1 control register. The de-assertion time is the time between the end of the last
stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed
using the DEDT [4:0] bit fields in the LPUART_CR1 control register. The polarity of the DE
signal can be configured using the DEP bit in the LPUART_CR3 control register.
In LPUART, the DEAT and DEDT are expressed in USART clock source (fCK) cycles:
• The Driver enable assertion time =
– (1 + (DEAT x P)) x fCK , if P <> 0
– (1 + DEAT) x fCK , if P = 0
• The Driver enable de-assertion time =
– (1 + (DEDT x P)) x fCK , if P <> 0
– (1 + DEDT) x fCK , if P = 0
With P = BRR[14:11]

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25.4.11 Wakeup from Stop mode using LPUART

The LPUART is able to wake up the MCU from Stop modewhen the UESM bit is set and the
LPUART clock is set to HSI or LSE (refer to the Reset and clock control (RCC) section.
• LPUART source clock is HSI
If during Stop mode the HSI clock is switched OFF, when a falling edge on the LPUART
receive line is detected, the LPUART interface requests the HSI clock to be switched
ON. The HSI clock is then used for the frame reception.
– If the wakeup event is verified, the MCU wakes up from low-power mode and data
reception goes on normally.
– If the wakeup event is not verified, the HSI clock is switched OFF again, the MCU
is not waken up and stays in low-power mode and the clock request is released.
Note: If the LPUART kernel clock is kept ON during Stop mode, there is no constraint on the
maximum baud rate that allows waking up from Stop mode. It is the same as in Run mode.
• LPUART source clock is LSE
Same principle as described in case LPUART source clock is HSI with the difference
that the LSE is ON in Stop mode, but the LSE clock is not propagated to LPUART if the
LPUART is not requesting it. The LSE clock is not OFF but there is a clock gating to
avoid useless consumption.
When the LPUART clock source is configured to be fLSE or fHSI, it is possible to keep
enabled this clock during STOP mode by setting the UCESM bit in LPUART_CR3 control
register.
Note: When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source,
and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register
must be set.
The MCU wakeup from Stop mode can be done using the standard RXNE interrupt. In this
case, the RXNEIE bit must be set before entering Stop mode.
Alternatively, a specific interrupt may be selected through the WUS bit fields.
In order to be able to wake up the MCU from Stop mode, the UESM bit in the LPUART_CR1
control register must be set prior to entering Stop mode.
When the wakeup event is detected, the WUF flag is set by hardware and a wakeup
interrupt is generated if the WUFIE bit is set.
For code example, refer to A.16.1: LPUART receiver configuration code example and
A.16.2: LPUART receive byte code example.
Note: Before entering Stop mode, the user must ensure that the LPUART is not performing a
transfer. BUSY flag cannot ensure that Stop mode is never entered during a running
reception.
The WUF flag is set when a wakeup event is detected, independently of whether the MCU is
in Stop or in an active mode.
When entering Stop mode just after having initialized and enabled the receiver, the REACK
bit must be checked to ensure the LPUART is actually enabled.
When DMA is used for reception, it must be disabled before entering Stop mode and re-
enabled upon exit from Stop mode.
The wakeup from Stop mode feature is not available for all modes. For example it doesn’t
work in SPI mode because the SPI operates in master mode only.

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Using Mute mode with Stop mode

If the LPUART is put into Mute mode before entering Stop mode:
• Wakeup from Mute mode on idle detection must not be used, because idle detection
cannot work in Stop mode.
• If the wakeup from Mute mode on address match is used, then the source of wake-up
from Stop mode must also be the address match. If the RXNE flag is set when entering
the Stop mode, the interface will remain in mute mode upon address match and wake
up from Stop.
• If the LPUART is configured to wake up the MCU from Stop mode on START bit
detection, the WUF flag is set, but the RXNE flag is not set.

Determining the maximum LPUART baud rate allowing to wakeup correctly

from Stop mode when the LPUART clock source is the HSI clock
The maximum baud rate allowing to wakeup correctly from Stop mode depends on:
• the parameter tWULPUART (wakeup time from Stop mode) provided in the device
datasheet
• the LPUART receiver tolerance provided in the Section 25.4.5: Tolerance of the
LPUART receiver to clock deviation.
Let us take this example: M bits = 01, 2 stop bits, BRR ≥ 4096.
In these conditions, according to Table 129: Tolerance of the LPUART receiver, the
LPUART receiver tolerance is 4.42 %.
DTRA + DQUANT + DREC + DTCL + DWU < LPUART receiver tolerance
DWU max = tWULPUART / (11 x Tbit Min)
Tbit Min = tWULPUART / (11 x DWU max)
If we consider an ideal case where the parameters DTRA, DQUANT, DREC and DTCL are
at 0%, the DWU max is 4.42 %. In reality, we need to consider at least the HSI inaccuracy.
Let us consider the HSI inaccuracy = 1 %, tWULPUART = 8.1 μs (in case of Stop mode with
main regulator in Run mode, Range 1 ):
DWU max = 4.42 % - 1 % = 3.42 %
Tbit min = 8.1 µs / (11 ₓ 3.42 %) = 2.5 μs.
In these conditions, the maximum baud rate allowing to wakeup correctly from Stop mode is
1/ 21.5 μs = 46 kbaud.

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25.5 LPUART in low-power mode

Table 131. Effect of low-power modes on the LPUART
Mode Description

Sleep No effect. USART interrupt causes the device to exit Sleep mode.
Low-power run No effect.
No effect. USART interrupt causes the device to exit Low-power sleep
Low-power sleep
mode.
The LPUART is able to wake up the MCU from Stop mode when the
UESM bit is set and the LPUART clock is set to HSI16 or LSE.
Stop
The MCU wakeup from Stop mode can be done using either the standard
RXNE or the WUF interrupt.
The LPUART is powered down and must be reinitialized when the device
Standby
has exited from Standby mode.

25.6 LPUART interrupts

Table 132. LPUART interrupt requests
Enable
Interrupt event Event flag
Control bit

Transmit data register empty TXE TXEIE

CTS interrupt CTSIF CTSIE
Transmission Complete TC TCIE
Receive data register not empty (data ready to be read) RXNE
RXNEIE
Overrun error detected ORE
Idle line detected IDLE IDLEIE
Parity error PE PEIE
Noise Flag, Overrun error and Framing Error in multibuffer
NF or ORE or FE EIE
communication.
Character match CMF CMIE
(1)
Wakeup from Stop mode WUF WUFIE
1. The wUF interrupt is active only in Stop mode.

The LPUART interrupt events are connected to the same interrupt vector (see Figure 237).
• During transmission: Transmission Complete, Clear to Send, Transmit data Register
empty or Framing error interrupt.
• During reception: Idle Line detection, Overrun error, Receive data register not empty,
Parity error, Noise Flag, Framing Error, Character match, etc.
These events generate an interrupt if the corresponding Enable Control Bit is set.

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Figure 249. LPUART interrupt mapping diagram

TC
TCIE
TXE
TXEIE
CTSIF
CTSIE
IDLE
IDLEIE
LPUART
RXNEIE
ORE interrupt
RXNEIE
RXNE
PE
PEIE
LBDF
LBDIE
FE
NF
ORE EIE
CMF
CMIE

WUF
WUFIE

MS31886V1

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25.7 LPUART registers

Refer to Section 1.2 on page 45 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32 bits).

25.7.1 Control register 1 (LPUART_CR1)

Address offset: 0x00
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. M1 Res. Res. DEAT[4:0] DEDT[4:0]
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. CMIE MME M0 WAKE PCE PS PEIE TXEIE TCIE RXNEIE IDLEIE TE RE UESM UE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value

Bit 28 M1: Word length
This bit, with bit 12 (M0) determines the word length. It is set or cleared by software.
M[1:0] = 00: 1 Start bit, 8 data bits, n stop bits
M[1:0] = 01: 1 Start bit, 9 data bits, n stop bits
M[1:0] = 10: 1 Start bit, 7 data bits, n stop bits
This bit can only be written when the LPUART is disabled (UE=0).
Bit 27 Reserved, must be kept at reset value
Bit 26 Reserved, must be kept at reset value
Bits 25:21 DEAT[4:0]: Driver Enable assertion time
This 5-bit value defines the time between the activation of the DE (Driver Enable) signal and
the beginning of the start bit. It is expressed in UCLK (USART clock) clock cycles. For more
details, refer to RS485 Driver Enable paragraph.
This bit field can only be written when the LPUART is disabled (UE=0).
Bits 20:16 DEDT[4:0]: Driver Enable de-assertion time
This 5-bit value defines the time between the end of the last stop bit, in a transmitted
message, and the de-activation of the DE (Driver Enable) signal. It is expressed in UCLK
(USART clock) clock cycles. For more details, refer to RS485 Driver Enable paragraph.
If the LPUART_TDR register is written during the DEDT time, the new data is transmitted
only when the DEDT and DEAT times have both elapsed.
This bit field can only be written when the LPUART is disabled (UE=0).
Bit 15 Reserved, must be kept at reset value
Bit 14 CMIE: Character match interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: A LPUART interrupt is generated when the CMF bit is set in the LPUART_ISR register.

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Bit 13 MME: Mute mode enable

This bit activates the mute mode function of the LPUART. When set, the LPUART can switch
between the active and mute modes, as defined by the WAKE bit. It is set and cleared by
software.
0: Receiver in active mode permanently
1: Receiver can switch between mute mode and active mode.
Bit 12 M0: Word length
This bit, with bit 28 (M1) determines the word length. It is set or cleared by software. See Bit
28 (M1) description.
This bit can only be written when the LPUART is disabled (UE=0).
Bit 11 WAKE: Receiver wakeup method
This bit determines the LPUART wakeup method from Mute mode. It is set or cleared by
software.
0: Idle line
1: Address mark
This bit field can only be written when the LPUART is disabled (UE=0).
Bit 10 PCE: Parity control enable
This bit selects the hardware parity control (generation and detection). When the parity
control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit
if M=0) and parity is checked on the received data. This bit is set and cleared by software.
Once it is set, PCE is active after the current byte (in reception and in transmission).
0: Parity control disabled
1: Parity control enabled
This bit field can only be written when the LPUART is disabled (UE=0).
Bit 9 PS: Parity selection
This bit selects the odd or even parity when the parity generation/detection is enabled (PCE
bit set). It is set and cleared by software. The parity will be selected after the current byte.
0: Even parity
1: Odd parity
This bit field can only be written when the LPUART is disabled (UE=0).
Bit 8 PEIE: PE interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated whenever PE=1 in the LPUART_ISR register
Bit 7 TXEIE: interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated whenever TXE=1 in the LPUART_ISR register
Bit 6 TCIE: Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated whenever TC=1 in the LPUART_ISR register
Bit 5 RXNEIE: RXNE interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated whenever ORE=1 or RXNE=1 in the LPUART_ISR
register

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Bit 4 IDLEIE: IDLE interrupt enable

This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated whenever IDLE=1 in the LPUART_ISR register
Bit 3 TE: Transmitter enable
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Note: During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble
(idle line) after the current word. In order to generate an idle character, the TE must not
be immediately written to 1. In order to ensure the required duration, the software can
poll the TEACK bit in the LPUART_ISR register.
When TE is set there is a 1 bit-time delay before the transmission starts.
Bit 2 RE: Receiver enable
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
Bit 1 UESM: LPUART enable in Stop mode
When this bit is cleared, the LPUART is not able to wake up the MCU from Stop mode.
When this bit is set, the LPUART is able to wake up the MCU from Stop mode, provided that
the LPUART clock selection is HSI or LSE in the RCC.
This bit is set and cleared by software.
0: LPUART not able to wake up the MCU from Stop mode.
1: LPUART able to wake up the MCU from Stop mode. When this function is active, the
clock source for the LPUART must be HSI or LSE (see Section Reset and clock control
(RCC)).
Note: It is recommended to set the UESM bit just before entering Stop mode and clear it on
exit from Stop mode.
Bit 0 UE: LPUART enable
When this bit is cleared, the LPUART prescalers and outputs are stopped immediately, and
current operations are discarded. The configuration of the LPUART is kept, but all the status
flags, in the LPUART_ISR are reset. This bit is set and cleared by software.

0: LPUART prescaler and outputs disabled, low-power mode

1: LPUART enabled
Note: In order to go into low-power mode without generating errors on the line, the TE bit
must be reset before and the software must wait for the TC bit in the LPUART_ISR to
be set before resetting the UE bit.
The DMA requests are also reset when UE = 0 so the DMA channel must be disabled
before resetting the UE bit.

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25.7.2 Control register 2 (LPUART_CR2)

Address offset: 0x04
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSBFI
ADD[7:4] ADD[3:0] Res. Res. Res. Res. DATAINV TXINV RXINV
RST
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SWAP Res. STOP[1:0] Res. Res. Res. Res. Res. Res. Res. ADDM7 Res. Res. Res. Res.

rw rw rw rw

Bits 31:28 ADD[7:4]: Address of the LPUART node

This bit-field gives the address of the LPUART node or a character code to be recognized.
This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with 7-
bit address mark detection. The MSB of the character sent by the transmitter should be equal to 1.
It may also be used for character detection during normal reception, Mute mode inactive (for
example, end of block detection in Modbus protocol). In this case, the whole received character (8-
bit) is compared to the ADD[7:0] value and CMF flag is set on match.
This bit field can only be written when reception is disabled (RE = 0) or the LPUART is disabled
(UE=0)
Bits 27:24 ADD[3:0]: Address of the LPUART node
This bit-field gives the address of the LPUART node or a character code to be recognized.
This is used in multiprocessor communication during Mute mode or Stop mode, for wakeup with
address mark detection.
This bit field can only be written when reception is disabled (RE = 0) or the LPUART is disabled
(UE=0)
Bits 23:20 Reserved, must be kept at reset value
Bit 19 MSBFIRST: Most significant bit first
This bit is set and cleared by software.
0: data is transmitted/received with data bit 0 first, following the start bit.
1: data is transmitted/received with the MSB (bit 7/8/9) first, following the start bit.
This bit field can only be written when the LPUART is disabled (UE=0).
Bit 18 DATAINV: Binary data inversion
This bit is set and cleared by software.
0: Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L)
1: Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The
parity bit is also inverted.
This bit field can only be written when the LPUART is disabled (UE=0).
Bit 17 TXINV: TX pin active level inversion
This bit is set and cleared by software.
0: TX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark)
1: TX pin signal values are inverted. (VDD =0/mark, Gnd=1/idle).
This allows the use of an external inverter on the TX line.
This bit field can only be written when the LPUART is disabled (UE=0).

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Bit 16 RXINV: RX pin active level inversion

This bit is set and cleared by software.
0: RX pin signal works using the standard logic levels (VDD =1/idle, Gnd=0/mark)
1: RX pin signal values are inverted. ((VDD =0/mark, Gnd=1/idle).
This allows the use of an external inverter on the RX line.
This bit field can only be written when the LPUART is disabled (UE=0).
Bit 15 SWAP: Swap TX/RX pins
This bit is set and cleared by software.
0: TX/RX pins are used as defined in standard pinout
1: The TX and RX pins functions are swapped. This allows to work in the case of a cross-wired
connection to another UART.
This bit field can only be written when the LPUART is disabled (UE=0).
Bit 14 Reserved, must be kept at reset value
Bits 13:12 STOP[1:0]: STOP bits
These bits are used for programming the stop bits.
00: 1 stop bit
01: Reserved.
10: 2 stop bits
11: Reserved
This bit field can only be written when the LPUART is disabled (UE=0).
Bits 11:5 Reserved, must be kept at reset value
Bit 4 ADDM7:7-bit Address Detection/4-bit Address Detection
This bit is for selection between 4-bit address detection or 7-bit address detection.
0: 4-bit address detection
1: 7-bit address detection (in 8-bit data mode)
This bit can only be written when the LPUART is disabled (UE=0)
Note: In 7-bit and 9-bit data modes, the address detection is done on 6-bit and 8-bit address
(ADD[5:0] and ADD[7:0]) respectively.
Bits 3:0 Reserved, must be kept at reset value.

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25.7.3 Control register 3 (LPUART_CR3)

Address offset: 0x08
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. UCESM WUFIE WUS[2:0] Res. Res. Res. Res.
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVR HD
DEP DEM DDRE Res. CTSIE CTSE RTSE DMAT DMAR Res. Res. Res. Res. EIE
DIS SEL
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 UCESM: LPUART Clock Enable in Stop mode.
This bit is set and cleared by software.
0: LPUART Clock is disabled in STOP mode.
1: LPUART Clock is enabled in STOP mode.
Note: In order to be able to wakeup the MCU from Stop mode with LPUART at 9600 baud,
the UCESM bit must be set prior to entering the Stop mode.
Bit 22 WUFIE: Wakeup from Stop mode interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An LPUART interrupt is generated whenever WUF=1 in the LPUART_ISR register
Note: WUFIE must be set before entering in Stop mode.
The WUF interrupt is active only in Stop mode.
If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
must be kept at reset value.
Bits 21:20 WUS[1:0]: Wakeup from Stop mode interrupt flag selection
This bit-field specify the event which activates the WUF (wakeup from Stop mode flag).
00: WUF active on address match (as defined by ADD[7:0] and ADDM7)
01:Reserved.
10: WUF active on Start bit detection
11: WUF active on RXNE.
This bit field can only be written when the LPUART is disabled (UE=0).
Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
must be kept at reset value.
Bits 19:16 Reserved, must be kept at reset value.
Bit 15 DEP: Driver enable polarity selection
0: DE signal is active high.
1: DE signal is active low.
This bit can only be written when the LPUART is disabled (UE=0).
Bit 14 DEM: Driver enable mode
This bit allows the user to activate the external transceiver control, through the DE signal.
0: DE function is disabled.
1: DE function is enabled. The DE signal is output on the RTS pin.
This bit can only be written when the LPUART is disabled (UE=0).

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Bit 13 DDRE: DMA Disable on Reception Error

0: DMA is not disabled in case of reception error. The corresponding error flag is set but
RXNE is kept 0 preventing from overrun. As a consequence, the DMA request is not
asserted, so the erroneous data is not transferred (no DMA request), but next correct
received data will be transferred.
1: DMA is disabled following a reception error. The corresponding error flag is set, as well
as RXNE. The DMA request is masked until the error flag is cleared. This means that the
software must first disable the DMA request (DMAR = 0) or clear RXNE before clearing the
error flag.
This bit can only be written when the LPUART is disabled (UE=0).
Note: The reception errors are: parity error, framing error or noise error.
Bit 12 OVRDIS: Overrun Disable
This bit is used to disable the receive overrun detection.
0: Overrun Error Flag, ORE, is set when received data is not read before receiving new
data.
1: Overrun functionality is disabled. If new data is received while the RXNE flag is still set
the ORE flag is not set and the new received data overwrites the previous content of the
LPUART_RDR register.
This bit can only be written when the LPUART is disabled (UE=0).
Note: This control bit allows checking the communication flow without reading the data.
Bit 11 Reserved, must be kept at reset value.
Bit 10 CTSIE: CTS interrupt enable
0: Interrupt is inhibited
1: An interrupt is generated whenever CTSIF=1 in the LPUART_ISR register
Bit 9 CTSE: CTS enable
0: CTS hardware flow control disabled
1: CTS mode enabled, data is only transmitted when the CTS input is deasserted (tied to 0).
If the CTS input is asserted while data is being transmitted, then the transmission is
completed before stopping. If data is written into the data register while CTS is asserted, the
transmission is postponed until CTS is deasserted.
This bit can only be written when the LPUART is disabled (UE=0)
Bit 8 RTSE: RTS enable
0: RTS hardware flow control disabled
1: RTS output enabled, data is only requested when there is space in the receive buffer. The
transmission of data is expected to cease after the current character has been transmitted.
The RTS output is deasserted (pulled to 0) when data can be received.
This bit can only be written when the LPUART is disabled (UE=0).
Bit 7 DMAT: DMA enable transmitter
This bit is set/reset by software
1: DMA mode is enabled for transmission
0: DMA mode is disabled for transmission
Bit 6 DMAR: DMA enable receiver
This bit is set/reset by software
1: DMA mode is enabled for reception
0: DMA mode is disabled for reception
Bits 5:4 Reserved, must be kept at reset value.

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Bit 3 HDSEL: Half-duplex selection

Selection of Single-wire Half-duplex mode
0: Half duplex mode is not selected
1: Half duplex mode is selected
This bit can only be written when the LPUART is disabled (UE=0).
Bits 2:1 Reserved, must be kept at reset value.
Bit 0 EIE: Error interrupt enable
Error Interrupt Enable Bit is required to enable interrupt generation in case of a framing
error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUART_ISR register).
0: Interrupt is inhibited
1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUART_ISR register.

25.7.4 Baud rate register (LPUART_BRR)

This register can only be written when the LPUART is disabled (UE=0).
Address offset: 0x0C
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BRR[19:16]
rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BRR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:0 BRR[19:0]

Note: It is forbidden to write values less than 0x300 in the LPUART_BRR register.
Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, a care
should be taken when generating high baud rates using high fck values. fck must be in the
range [3 x baud rate,.4096 x baud rate].

25.7.5 Request register (LPUART_RQR)

Address offset: 0x18
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. RXFRQ MMRQ SBKRQ Res.
w w w

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Bits 31:4 Reserved, must be kept at reset value

Bit 3 RXFRQ: Receive data flush request
Writing 1 to this bit clears the RXNE flag.
This allows to discard the received data without reading it, and avoid an overrun condition.
Bit 2 MMRQ: Mute mode request
Writing 1 to this bit puts the LPUART in mute mode and resets the RWU flag.
Bit 1 SBKRQ: Send break request
Writing 1 to this bit sets the SBKF flag and request to send a BREAK on the line, as soon as
the transmit machine is available.
Note: In the case the application needs to send the break character following all previously
inserted data, including the ones not yet transmitted, the software should wait for the
TXE flag assertion before setting the SBKRQ bit.
Bit 0 Reserved, must be kept at reset value

25.7.6 Interrupt & status register (LPUART_ISR)

Address offset: 0x1C
Reset value: 0x00C0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RE TE
Res. Res. Res. Res. Res. Res. Res. Res. Res. WUF RWU SBKF CMF BUSY
ACK ACK
r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. CTS CTSIF Res. TXE TC RXNE IDLE ORE NF FE PE
r r r r r r r r r r

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 REACK: Receive enable acknowledge flag
This bit is set/reset by hardware, when the Receive Enable value is taken into account by
the LPUART.
It can be used to verify that the LPUART is ready for reception before entering Stop mode.
Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value.
Bit 21 TEACK: Transmit enable acknowledge flag
This bit is set/reset by hardware, when the Transmit Enable value is taken into account by
the LPUART.
It can be used when an idle frame request is generated by writing TE=0, followed by TE=1
in the LPUART_CR1 register, in order to respect the TE=0 minimum period.
Bit 20 WUF: Wakeup from Stop mode flag
This bit is set by hardware, when a wakeup event is detected. The event is defined by the
WUS bit field. It is cleared by software, writing a 1 to the WUCF in the LPUART_ICR register.
An interrupt is generated if WUFIE=1 in the LPUART_CR3 register.
Note: When UESM is cleared, WUF flag is also cleared.
The WUF interrupt is active only in Stop mode.
If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value.

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Bit 19 RWU: Receiver wakeup from Mute mode

This bit indicates if the LPUART is in mute mode. It is cleared/set by hardware when a
wakeup/mute sequence is recognized. The mute mode control sequence (address or IDLE)
is selected by the WAKE bit in the LPUART_CR1 register.
When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the
MMRQ bit in the LPUART_RQR register.
0: Receiver in active mode
1: Receiver in mute mode
Bit 18 SBKF: Send break flag
This bit indicates that a send break character was requested. It is set by software, by writing
1 to the SBKRQ bit in the LPUART_CR3 register. It is automatically reset by hardware
during the stop bit of break transmission.
0: No break character is transmitted
1: Break character will be transmitted
Bit 17 CMF: Character match flag
This bit is set by hardware, when the character defined by ADD[7:0] is received. It is cleared
by software, writing 1 to the CMCF in the LPUART_ICR register.
An interrupt is generated if CMIE=1in the LPUART_CR1 register.
0: No Character match detected
1: Character Match detected
Bit 16 BUSY: Busy flag
This bit is set and reset by hardware. It is active when a communication is ongoing on the
RX line (successful start bit detected). It is reset at the end of the reception (successful or
not).
0: LPUART is idle (no reception)
1: Reception on going
Bits 15:11 Reserved, must be kept at reset value.
Bit 10 CTS: CTS flag
This bit is set/reset by hardware. It is an inverted copy of the status of the CTS input pin.
0: CTS line set
1: CTS line reset
Note: If the hardware flow control feature is not supported, this bit is reserved and kept at
reset value.
Bit 9 CTSIF: CTS interrupt flag
This bit is set by hardware when the CTS input toggles, if the CTSE bit is set. It is cleared by
software, by writing 1 to the CTSCF bit in the LPUART_ICR register.
An interrupt is generated if CTSIE=1 in the LPUART_CR3 register.
0: No change occurred on the CTS status line
1: A change occurred on the CTS status line
Note: If the hardware flow control feature is not supported, this bit is reserved and kept at
reset value.
Bit 8 Reserved, must be kept at reset value.

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Bit 7 TXE: Transmit data register empty

This bit is set by hardware when the content of the LPUART_TDR register has been
transferred into the shift register. It is cleared by a write to the LPUART_TDR register.
An interrupt is generated if the TXEIE bit =1 in the LPUART_CR1 register.
0: data is not transferred to the shift register
1: data is transferred to the shift register)
Note: This bit is used during single buffer transmission.
Bit 6 TC: Transmission complete
This bit is set by hardware if the transmission of a frame containing data is complete and if
TXE is set. An interrupt is generated if TCIE=1 in the LPUART_CR1 register. It is cleared by
software, writing 1 to the TCCF in the LPUART_ICR register or by a write to the
LPUART_TDR register.
An interrupt is generated if TCIE=1 in the LPUART_CR1 register.
0: Transmission is not complete
1: Transmission is complete
Note: If TE bit is reset and no transmission is on going, the TC bit will be set immediately.
Bit 5 RXNE: Read data register not empty
This bit is set by hardware when the content of the RDR shift register has been transferred
to the LPUART_RDR register. It is cleared by a read to the LPUART_RDR register. The
RXNE flag can also be cleared by writing 1 to the RXFRQ in the LPUART_RQR register.
An interrupt is generated if RXNEIE=1 in the LPUART_CR1 register.
0: data is not received
1: Received data is ready to be read.
Bit 4 IDLE: Idle line detected
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if
IDLEIE=1 in the LPUART_CR1 register. It is cleared by software, writing 1 to the IDLECF in
the LPUART_ICR register.
0: No Idle line is detected
1: Idle line is detected
Note: The IDLE bit will not be set again until the RXNE bit has been set (i.e. a new idle line
occurs).
If mute mode is enabled (MME=1), IDLE is set if the LPUART is not mute (RWU=0),
whatever the mute mode selected by the WAKE bit. If RWU=1, IDLE is not set.
Bit 3 ORE: Overrun error
This bit is set by hardware when the data currently being received in the shift register is
ready to be transferred into the RDR register while RXNE=1. It is cleared by a software,
writing 1 to the ORECF, in the LPUART_ICR register.
An interrupt is generated if RXNEIE=1 or EIE = 1 in the LPUART_CR1 register.
0: No overrun error
1: Overrun error is detected
Note: When this bit is set, the RDR register content is not lost but the shift register is
overwritten. An interrupt is generated if the ORE flag is set during multibuffer
communication if the EIE bit is set.
This bit is permanently forced to 0 (no overrun detection) when the OVRDIS bit is set in
the LPUART_CR3 register.

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Bit 2 NF: START bit Noise detection flag

This bit is set by hardware when noise is detected on the START bit of a received frame. It is
cleared by software, writing 1 to the NFCF bit in the LPUART_ICR register.
0: No noise is detected
1: Noise is detected
Note: This bit does not generate an interrupt as it appears at the same time as the RXNE bit
which itself generates an interrupt. An interrupt is generated when the NF flag is set
during multibuffer communication if the EIE bit is set.
Bit 1 FE: Framing error
This bit is set by hardware when a de-synchronization, excessive noise or a break character
is detected. It is cleared by software, writing 1 to the FECF bit in the LPUART_ICR register.
An interrupt is generated if EIE = 1 in the LPUART_CR1 register.
0: No Framing error is detected
1: Framing error or break character is detected
Bit 0 PE: Parity error
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by
software, writing 1 to the PECF in the LPUART_ICR register.
An interrupt is generated if PEIE = 1 in the LPUART_CR1 register.
0: No parity error
1: Parity error

25.7.7 Interrupt flag clear register (LPUART_ICR)

Address offset: 0x20
Reset value: 0x0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WUCF Res. Res. CMCF Res.
w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. CTSCF Res. Res. TCCF Res. IDLECF ORECF NCF FECF PECF
w w w w w w w

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 WUCF: Wakeup from Stop mode clear flag
Writing 1 to this bit clears the WUF flag in the LPUART_ISR register.
Note: If the LPUART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value.
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 CMCF: Character match clear flag
Writing 1 to this bit clears the CMF flag in the LPUART_ISR register.
Bits 16:10 Reserved, must be kept at reset value.
Bit 9 CTSCF: CTS clear flag
Writing 1 to this bit clears the CTSIF flag in the LPUART_ISR register.
Bits 8:7 Reserved, must be kept at reset value.

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Bit 6 TCCF: Transmission complete clear flag

Writing 1 to this bit clears the TC flag in the LPUART_ISR register.
Bit 5 Reserved, must be kept at reset value.
Bit 4 IDLECF: Idle line detected clear flag
Writing 1 to this bit clears the IDLE flag in the LPUART_ISR register.
Bit 3 ORECF: Overrun error clear flag
Writing 1 to this bit clears the ORE flag in the LPUART_ISR register.
Bit 2 NCF: Noise detected clear flag
Writing 1 to this bit clears the NF flag in the LPUART_ISR register.
Bit 1 FECF: Framing error clear flag
Writing 1 to this bit clears the FE flag in the LPUART_ISR register.
Bit 0 PECF: Parity error clear flag
Writing 1 to this bit clears the PE flag in the LPUART_ISR register.

25.7.8 Receive data register (LPUART_RDR)

Address offset: 0x24
Reset value: Undefined

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. RDR[8:0]
r r r r r r r r r

Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 RDR[8:0]: Receive data value
Contains the received data character.
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 213).
When receiving with the parity enabled, the value read in the MSB bit is the received parity
bit.

25.7.9 Transmit data register (LPUART_TDR)

Address offset: 0x28
Reset value: Undefined

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. TDR[8:0]
rw rw rw rw rw rw rw rw rw

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Bits 31:9 Reserved, must be kept at reset value.

Bits 8:0 TDR[8:0]: Transmit data value
Contains the data character to be transmitted.
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 213).
When transmitting with the parity enabled (PCE bit set to 1 in the LPUART_CR1 register),
the value written in the MSB (bit 7 or bit 8 depending on the data length) has no effect
because it is replaced by the parity.
Note: This register must be written only when TXE=1.

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 0x28
0x24
0x20
0x18
0x14
0x08
0x04
0x00

0x1C
0x0C

0x10-
Offset
RM0377

25.7.10

CR3
CR2
CR1

TDR
BRR

RDR
RQR

LPUART_
LPUART_
LPUART_
LPUART_
LPUART_
LPUART_
LPUART_
Register

Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

LPUART_ISR

LPUART_ICR
0
Res. Res. Res. Res. Res. Res. Res. Res. 31

0
Res. Res. Res. Res. Res. Res. Res. Res. 30

0
Res. Res. Res. Res. Res. Res. Res. Res. 29

ADD[7:4]

0
0
Res. Res. Res. Res. Res. Res. Res. M1 28

0
Res. Res. Res. Res. Res. Res. Res. Res. 27

0
Res. Res. Res. Res. Res. Res. Res. Res. 26

0
0
Res. Res. Res. Res. Res. Res. Res. DEAT4 25

ADD[3:0]

0
0
Res. Res. Res. Res. Res. Res. Res. DEAT3 24
LPUART register map

0
Res. Res. Res. Res. Res. Res. UCESM Res. 0 DEAT2 23

0
0
0
Res. Res. Res. REACK Res. Res. WUFIE Res. DEAT1 22

0
0
0

Res. Res. Res. TEACK Res. Res. Res. DEAT0 21

[1:0]

0
0
0
0

WUS
Res. Res. WUCF WUF Res. Res. Res. DEDT4 20

0
0
0

Res. Res. Res. RWU Res. Res. MSBFIRST DEDT3 19

0
0
0

Res. Res. Res. SBKF Res. Res. DATAINV DEDT2 18

0
0
0
0

Res. Res. CMCF CMF Res. Res. TXINV DEDT1 17

Reserved

RM0377 Rev 10
0
0
0

Res. Res. Res. BUSY Res. Res. RXINV DEDT0 16

0
0

Res. Res. Res. Res. Res. DEP SWAP Res. 15

0
0
0

Res. Res. Res. Res. Res. DEM Res. CMIE 14

0
0
0
0

Res. Res. Res. Res. Res. DDRE MME 13

[1:0]

0
0
0
0

STOP

Res. Res. Res. Res. Res. OVRDIS M 12

0
0

Res. Res. Res. Res. Res. Res. Res. WAKE 11

0
0
0
0

Res. Res. Res. CTS Res. CTSIE Res. PCE 10

Table 133. LPUART register map and reset values
The table below gives the LPUART register map and reset values.

0
0
0
0

0
Res. Res. CTSCF CTSIF Res. CTSE Res. PS 9
BRR[19:0]

Refer to Section 2.2 on page 51 for the register boundary addresses.

0
0
0

X
X
Res. Res. Res. RTSE Res. PEIE 8

1
0
0
0

X
X
Res. TXE Res. DMAT Res. TXEIE 7

0
1
0
0
0

X
X
TCCF TC Res. DMAR Res. TCIE 6

0
0
0

X
X
Res. RXNE Res. Res. Res. RXNEIE 5

0
0
0
0

X
X
Res. IDLE Res. Res. ADDM7 IDLEIE 4
0

0
0
0
0

X
X

TDR[8:0]
RDR[8:0]
ORECF ORE RXFRQ HDSEL Res. TE 3
0

0
0
0

X
X
NCF NF MMRQ Res. Res. RE 2
0

0
0
0

X
X
FECF FE SBKRQ Res. Res. UESM 1

0
0
0
0

X
X
Low-power universal asynchronous receiver transmitter (LPUART)

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26 Serial peripheral interface/ inter-IC sound (SPI/I2S)

26.1 Introduction
The SPI/I²S interface can be used to communicate with external devices using the SPI
protocol or the I2S audio protocol. SPI or I2S mode is selectable by software. SPI mode is
selected by default after a device reset.
The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex
synchronous, serial communication with external devices. The interface can be configured
as master and in this case it provides the communication clock (SCK) to the external slave
device. The interface is also capable of operating in multimaster configuration.
The Inter-IC sound (I2S) protocol is also a synchronous serial communication interface. It
can operate in slave or master mode with half-duplex communication. Full duplex
operations are possible by combining two I2S blocks.
It can address four different audio standards including the Philips I2S standard, the MSB-
and LSB-justified standards and the PCM standard.

26.1.1 SPI main features

• Master or slave operation
• Full-duplex synchronous transfers on three lines
• Half-duplex synchronous transfer on two lines (with bidirectional data line)
• Simplex synchronous transfers on two lines (with unidirectional data line)
• 8-bit to 16-bit transfer frame format selection
• Multimaster mode capability
• 8 master mode baud rate prescalers up to fPCLK/2.
• Slave mode frequency up to fPCLK/2.
• NSS management by hardware or software for both master and slave: dynamic change
of master/slave operations
• Programmable clock polarity and phase
• Programmable data order with MSB-first or LSB-first shifting
• Dedicated transmission and reception flags with interrupt capability
• SPI bus busy status flag
• SPI Motorola support
• Hardware CRC feature for reliable communication:
– CRC value can be transmitted as last byte in Tx mode
– Automatic CRC error checking for last received byte
• Master mode fault, overrun flags with interrupt capability
• CRC Error flag
• 1-byte/word transmission and reception buffer with DMA capability: Tx and Rx requests

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26.1.2 SPI extended features

• SPI TI mode support

26.1.3 I2S features

• Half-duplex communication (only transmitter or receiver)
• Master or slave operations
• 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from
8 kHz to 192 kHz)
• Data format may be 16-bit, 24-bit or 32-bit
• Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data
frame) by audio channel
• Programmable clock polarity (steady state)
• Underrun flag in slave transmission mode, overrun flag in reception mode (master and
slave) and Frame Error Flag in reception and transmitter mode (slave only)
• 16-bit register for transmission and reception with one data register for both channel
sides
• Supported I2S protocols:
– I2S Philips standard
– MSB-Justified standard (Left-Justified)
– LSB-Justified standard (Right-Justified)
– PCM standard (with short and long frame synchronization on 16-bit channel frame
or 16-bit data frame extended to 32-bit channel frame)
• Data direction is always MSB first
• DMA capability for transmission and reception (16-bit wide)
• Master clock can be output to drive an external audio component. Ratio is fixed at
256 × FS (where FS is the audio sampling frequency)

26.2 SPI/I2S implementation

This manual describes the full set of features implemented in SPI1 and SPI2.

Table 134. STM32L0x1 SPI implementation

SPI Features(1) SPI1 SPI2

Hardware CRC calculation X X

I2S mode - X
TI mode X X
1. X = supported.

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26.3 SPI functional description

26.3.1 General description

The SPI allows synchronous, serial communication between the MCU and external devices.
Application software can manage the communication by polling the status flag or using
dedicated SPI interrupt. The main elements of SPI and their interactions are shown in the
following block diagram Figure 250.

Figure 250. SPI block diagram

Address and data bus

Read
Rx
buffer
CRC controller
MOSI
MISO Shift register
LSBFIRST CRCEN
CPOL CRCNEXT
CPHA
DFF
TX
buffer
Write Communication
BIDIOE controller
BIDIMODE
RXOLNY
Baud rate
SCK Internal NSS
generator BR[2:0]

NSS
NSS logic
MSv33711V1

Four I/O pins are dedicated to SPI communication with external devices.
• MISO: Master In / Slave Out data. In the general case, this pin is used to transmit data
in slave mode and receive data in master mode.
• MOSI: Master Out / Slave In data. In the general case, this pin is used to transmit data
in master mode and receive data in slave mode.
• SCK: Serial Clock output pin for SPI masters and input pin for SPI slaves.
• NSS: Slave select pin. Depending on the SPI and NSS settings, this pin can be used to
either:
– select an individual slave device for communication
– synchronize the data frame or
– detect a conflict between multiple masters
See Section 26.3.5: Slave select (NSS) pin management for details.
The SPI bus allows the communication between one master device and one or more slave
devices. The bus consists of at least two wires - one for the clock signal and the other for
synchronous data transfer. Other signals can be added depending on the data exchange
between SPI nodes and their slave select signal management.

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26.3.2 Communications between one master and one slave

The SPI allows the MCU to communicate using different configurations, depending on the
device targeted and the application requirements. These configurations use 2 or 3 wires
(with software NSS management) or 3 or 4 wires (with hardware NSS management).
Communication is always initiated by the master.

Full-duplex communication
By default, the SPI is configured for full-duplex communication. In this configuration, the
shift registers of the master and slave are linked using two unidirectional lines between the
MOSI and the MISO pins. During SPI communication, data is shifted synchronously on the
SCK clock edges provided by the master. The master transmits the data to be sent to the
slave via the MOSI line and receives data from the slave via the MISO line. When the data
frame transfer is complete (all the bits are shifted) the information between the master and
slave is exchanged.

Figure 251. Full-duplex single master/ single slave application

MISO MISO
Rx shift register Tx shift register
MOSI MOSI
Tx shift register Rx shift register

SPI clock SCK SCK

generator
NSS(1) NSS (1)
Master Slave

MSv39623V1

1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the
pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and
slave. For more details see Section 26.3.5: Slave select (NSS) pin management.

Half-duplex communication
The SPI can communicate in half-duplex mode by setting the BIDIMODE bit in the
SPIx_CR1 register. In this configuration, one single cross connection line is used to link the
shift registers of the master and slave together. During this communication, the data is
synchronously shifted between the shift registers on the SCK clock edge in the transfer
direction selected reciprocally by both master and slave with the BDIOE bit in their
SPIx_CR1 registers. In this configuration, the master’s MISO pin and the slave’s MOSI pin
are free for other application uses and act as GPIOs.

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Figure 252. Half-duplex single master/ single slave application

(2)
MISO MISO
Rx shift register Tx shift register
(3)
MOSI 1kΩ (2)
Tx shift register MOSI Rx shift register

SPI clock SCK SCK

generator
NSS (1) NSS(1)
Master Slave

MSv39624V1

1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the
pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and
slave. For more details see Section 26.3.5: Slave select (NSS) pin management.
2. In this configuration, the master’s MISO pin and the slave’s MOSI pin can be used as GPIOs.
3. A critical situation can happen when communication direction is changed not synchronously between two
nodes working at bidirectionnal mode and new transmitter accesses the common data line while former
transmitter still keeps an opposite value on the line (the value depends on SPI configuration and
communication data). Both nodes then fight while providing opposite output levels on the common line
temporary till next node changes its direction settings correspondingly, too. It is suggested to insert a serial
resistance between MISO and MOSI pins at this mode to protect the outputs and limit the current blowing
between them at this situation.

Simplex communications
The SPI can communicate in simplex mode by setting the SPI in transmit-only or in receive-
only using the RXONLY bit in the SPIx_CR2 register. In this configuration, only one line is
used for the transfer between the shift registers of the master and slave. The remaining
MISO and MOSI pins pair is not used for communication and can be used as standard
GPIOs.
• Transmit-only mode (RXONLY=0): The configuration settings are the same as for full-
duplex. The application has to ignore the information captured on the unused input pin.
This pin can be used as a standard GPIO.
• Receive-only mode (RXONLY=1): The application can disable the SPI output function
by setting the RXONLY bit. In slave configuration, the MISO output is disabled and the
pin can be used as a GPIO. The slave continues to receive data from the MOSI pin
while its slave select signal is active (see 26.3.5: Slave select (NSS) pin management).
Received data events appear depending on the data buffer configuration. In the master
configuration, the MOSI output is disabled and the pin can be used as a GPIO. The
clock signal is generated continuously as long as the SPI is enabled. The only way to
stop the clock is to clear the RXONLY bit or the SPE bit and wait until the incoming
pattern from the MISO pin is finished and fills the data buffer structure, depending on its
configuration.

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Figure 253. Simplex single master/single slave application (master in transmit-only/

slave in receive-only mode)

(2) MISO MISO

Rx shift register Tx shift register
MOSI MOSI
Tx shift register Rx shift register

SPI clock SCK SCK

generator
NSS(1) NSS(1)
Master Slave

MSv39625V1

1. The NSS pins can be used to provide a hardware control flow between master and slave. Optionally, the
pins can be left unused by the peripheral. Then the flow has to be handled internally for both master and
slave. For more details see Section 26.3.5: Slave select (NSS) pin management.
2. An accidental input information is captured at the input of transmitter Rx shift register. All the events
associated with the transmitter receive flow must be ignored in standard transmit only mode (e.g. OVF
flag).
3. In this configuration, both the MISO pins can be used as GPIOs.
Note: Any simplex communication can be alternatively replaced by a variant of the half-duplex
communication with a constant setting of the transaction direction (bidirectional mode is
enabled while BDIO bit is not changed).

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26.3.3 Standard multi-slave communication

In a configuration with two or more independent slaves, the master uses GPIO pins to
manage the chip select lines for each slave (see Figure 254.). The master must select one
of the slaves individually by pulling low the GPIO connected to the slave NSS input. When
this is done, a standard master and dedicated slave communication is established.

Figure 254. Master and three independent slaves

NSS (1)

MISO MISO
Rx shift register Tx shift register
MOSI MOSI
Tx shift register Rx shift register

SPI clock SCK SCK

generator
IO1 NSS
Master Slave 1
IO2
IO3

MISO
Tx shift register
MOSI
Rx shift register
SCK

NSS
Slave 2

MISO
Tx shift register
MOSI
Rx shift register
SCK

NSS
Slave 3
MSv39626V1

1. NSS pin is not used on master side at this configuration. It has to be managed internally (SSM=1, SSI=1) to
prevent any MODF error.
2. As MISO pins of the slaves are connected together, all slaves must have the GPIO configuration of their
MISO pin set as alternate function open-drain (see Section 8.3.7: I/O alternate function input/output on
page 221).

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26.3.4 Multi-master communication

Unless SPI bus is not designed for a multi-master capability primarily, the user can use build
in feature which detects a potential conflict between two nodes trying to master the bus at
the same time. For this detection, NSS pin is used configured at hardware input mode.
The connection of more than two SPI nodes working at this mode is impossible as only one
node can apply its output on a common data line at time.
When nodes are non active, both stay at slave mode by default. Once one node wants to
overtake control on the bus, it switches itself into master mode and applies active level on
the slave select input of the other node via dedicated GPIO pin. After the session is
completed, the active slave select signal is released and the node mastering the bus
temporary returns back to passive slave mode waiting for next session start.
If potentially both nodes raised their mastering request at the same time a bus conflict event
appears (see mode fault MODF event). Then the user can apply some simple arbitration
process (e.g. to postpone next attempt by predefined different time-outs applied at both
nodes).

Figure 255. Multi-master application

MISO MISO
Rx (Tx) shift register Rx (Tx) shift register
MOSI MOSI
Tx (Rx) shift register Tx (Rx) shift register

SPI clock SCK SCK SPI clock

generator generator
(1)
GPIO NSS

Master NSS(1) GPIO Master

(Slave) (Slave)

MSv39628V1

1. The NSS pin is configured at hardware input mode at both nodes. Its active level enables the MISO line
output control as the passive node is configured as a slave.

26.3.5 Slave select (NSS) pin management

In slave mode, the NSS works as a standard “chip select” input and lets the slave
communicate with the master. In master mode, NSS can be used either as output or input.
As an input it can prevent multimaster bus collision, and as an output it can drive a slave
select signal of a single slave.
Hardware or software slave select management can be set using the SSM bit in the
SPIx_CR1 register:
• Software NSS management (SSM = 1): in this configuration, slave select information
is driven internally by the SSI bit value in register SPIx_CR1. The external NSS pin is
free for other application uses.
• Hardware NSS management (SSM = 0): in this case, there are two possible
configurations. The configuration used depends on the NSS output configuration
(SSOE bit in register SPIx_CR1).

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– NSS output enable (SSM=0,SSOE = 1): this configuration is only used when the
MCU is set as master. The NSS pin is managed by the hardware. The NSS signal
is driven low as soon as the SPI is enabled in master mode (SPE=1), and is kept
low until the SPI is disabled (SPE =0).
– NSS output disable (SSM=0, SSOE = 0): if the microcontroller is acting as the
master on the bus, this configuration allows multimaster capability. If the NSS pin
is pulled low in this mode, the SPI enters master mode fault state and the device is
automatically reconfigured in slave mode. In slave mode, the NSS pin works as a
standard “chip select” input and the slave is selected while NSS line is at low level.

Figure 256. Hardware/software slave select management

SSI control bit

SSM control bit

NSS Master
Slave mode
Inp. mode
Vdd OK Non active
1 Vss Conflict Active

NSS Input
0
NSS GPIO
pin logic

NSS NSS Output

Output
Control (used in Master mode & NSS
HW management only)

SSOE control bit

NSS external logic NSS internal logic

aiv14746e

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26.3.6 Communication formats

During SPI communication, receive and transmit operations are performed simultaneously.
The serial clock (SCK) synchronizes the shifting and sampling of the information on the data
lines. The communication format depends on the clock phase, the clock polarity and the
data frame format. To be able to communicate together, the master and slaves devices must
follow the same communication format.

Clock phase and polarity controls

Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits in the SPIx_CR1 register. The CPOL (clock polarity) bit controls the idle state value of
the clock when no data is being transferred. This bit affects both master and slave modes. If
CPOL is reset, the SCK pin has a low-level idle state. If CPOL is set, the SCK pin has a
high-level idle state.
If the CPHA bit is set, the second edge on the SCK pin captures the first data bit transacted
(falling edge if the CPOL bit is reset, rising edge if the CPOL bit is set). Data are latched on
each occurrence of this clock transition type. If the CPHA bit is reset, the first edge on the
SCK pin captures the first data bit transacted (falling edge if the CPOL bit is set, rising edge
if the CPOL bit is reset). Data are latched on each occurrence of this clock transition type.
The combination of CPOL (clock polarity) and CPHA (clock phase) bits selects the data
capture clock edge.
Figure 257, shows an SPI full-duplex transfer with the four combinations of the CPHA and
CPOL bits.
Note: Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit.
The idle state of SCK must correspond to the polarity selected in the SPIx_CR1 register (by
pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).

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Figure 257. Data clock timing diagram

CPHA =1
CPOL = 1

CPOL = 0

MOSI MSBit LSBit

MISO MSBit LSBit

NSS
(to slave)

Capture strobe

CPHA =0

CPOL = 1

CPOL = 0

MOSI MSBit LSBit

MISO MSBit LSBit

NSS
(to slave)

Capture strobe

ai17154d

Note: The order of data bits depends on LSBFIRST bit setting.

Data frame format

The SPI shift register can be set up to shift out MSB-first or LSB-first, depending on the
value of the LSBFIRST bit. Each data frame is 8 or 16 bit long depending on the size of the
data programmed using the DFF bit in the SPI_CR1 register. The selected data frame
format is applicable both for transmission and reception.

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26.3.7 SPI configuration

The configuration procedure is almost the same for master and slave. For specific mode
setups, follow the dedicated chapters. When a standard communication is to be initialized,
perform these steps:
1. Write proper GPIO registers: Configure GPIO for MOSI, MISO and SCK pins.
2. Write to the SPI_CR1 register:
a) Configure the serial clock baud rate using the BR[2:0] bits (Note: 3).
b) Configure the CPOL and CPHA bits combination to define one of the four
relationships between the data transfer and the serial clock. (Note: 2 - except the
case when CRC is enabled at TI mode).
c) Select simplex or half-duplex mode by configuring RXONLY or BIDIMODE and
BIDIOE (RXONLY and BIDIMODE can't be set at the same time).
d) Configure the LSBFIRST bit to define the frame format (Note: 2).
e) Configure the CRCEN and CRCEN bits if CRC is needed (while SCK clock signal
is at idle state).
f) Configure SSM and SSI (Note: 2).
g) Configure the MSTR bit (in multimaster NSS configuration, avoid conflict state on
NSS if master is configured to prevent MODF error).
h) Set the DFF bit to configure the data frame format (8 or 16 bits).
3. Write to SPI_CR2 register:
a) Configure SSOE (Note: 1 & 2).
b) Set the FRF bit if the TI protocol is required.
4. Write to SPI_CRCPR register: Configure the CRC polynomial if needed.
5. Write proper DMA registers: Configure DMA streams dedicated for SPI Tx and Rx in
DMA registers if the DMA streams are used.
Note: (1) Step is not required in slave mode.
(2) Step is not required in TI mode.
(3) The step is not required in slave mode except slave working at TI mode.
For code example, refer to A.17.1: SPI master configuration code example and A.17.2: SPI
slave configuration code example.

26.3.8 Procedure for enabling SPI

It is recommended to enable the SPI slave before the master sends the clock. Otherwise,
undesired data transmission might occur. The slave data register must already contain data
to be sent before starting communication with the master (either on the first edge of the
communication clock, or before the end of the ongoing communication if the clock signal is
continuous). The SCK signal must be settled at an idle state level corresponding to the
selected polarity before the SPI slave is enabled.
At full-duplex (or in any transmit-only mode), the master starts communicating when the SPI
is enabled and data to be sent is written in the Tx Buffer.
In any master receive-only mode (RXONLY=1 or BIDIMODE=1 & BIDIOE=0), the master
starts communicating and the clock starts running immediately after the SPI is enabled.
The slave starts communicating when it receives a correct clock signal from the master. The
slave software must write the data to be sent before the SPI master initiates the transfer.

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Refer to Section 26.3.11: Communication using DMA (direct memory addressing) for details
on how to handle DMA.

26.3.9 Data transmission and reception procedures

Rx and Tx buffers
In reception, data are received and then stored into an internal Rx buffer while in
transmission, data are first stored into an internal Tx buffer before being transmitted. A read
access to the SPI_DR register returns the Rx buffered value whereas a write access to the
SPI_DR stores the written data into the Tx buffer.

Tx buffer handling
The data frame is loaded from the Tx buffer into the shift register during the first bit
transmission. Bits are then shifted out serially from the shift register to a dedicated output
pin depending on LSBFIRST bit setting.The TXE flag (Tx buffer empty) is set when the data
are transferred from the Tx buffer to the shift register. It indicates that the internal Tx buffer is
ready to be loaded with the next data. An interrupt can be generated if the TXEIE bit of the
SPI_CR2 register is set. Clearing the TXE bit is performed by writing to the SPI_DR register.
A continuous transmit stream can be achieved if the next data to be transmitted are stored
in the Tx buffer while previous frame transmission is still ongoing. When the software writes
to Tx buffer while the TXE flag is not set, the data waiting for transaction is overwritten.

Rx buffer handling
The RXNE flag (Rx buffer not empty) is set on the last sampling clock edge, when the data
are transferred from the shift register to the Rx buffer. It indicates that data are ready to be
read from the SPI_DR register. An interrupt can be generated if the RXNEIE bit in the
SPI_CR2 register is set. Clearing the RXNE bit is performed by reading the SPI_DR
register.
If a device has not cleared the RXNE bit resulting from the previous data byte transmitted,
an overrun condition occurs when the next value is buffered. The OVR bit is set and an
interrupt is generated if the ERRIE bit is set.
Another way to manage the data exchange is to use DMA (see Section 10.2: DMA main
features).

Sequence handling
The BSY bit is set when a current data frame transaction is ongoing. When the clock signal
runs continuously, the BSY flag remains set between data frames on the master side.
However, on the slave side, it becomes low for a minimum duration of one SPI clock cycle
between each data frame transfer.
For some configurations, the BSY flag can be used during the last data transfer to wait until
the completion of the transfer.
When a receive-only mode is configured on the master side, either in half-duplex
(BIDIMODE=1, BIDIOE=0) or simplex configuration (BIDIMODE=0, RXONLY=1), the
master starts the receive sequence as soon as the SPI is enabled. Then the clock signal is
provided by the master and it does not stop until either the SPI or the receive-only mode is
disabled by the master. The master receives data frames continuously up to this moment.

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While the master can provide all the transactions in continuous mode (SCK signal is
continuous), it has to respect slave capability to handle data flow and its content at anytime.
When necessary, the master must slow down the communication and provide either a
slower clock or separate frames or data sessions with sufficient delays. Be aware there is no
underflow error signal for slave operating in SPI mode, and that data from the slave are
always transacted and processed by the master even if the slave cannot not prepare them
correctly in time. It is preferable for the slave to use DMA, especially when data frames are
shorter and bus rate is high.
Each sequence must be encased by the NSS pulse in parallel with the multislave system to
select just one of the slaves for communication. In single slave systems, using NSS to
control the slave is not necessary. However, the NSS pulse can be used to synchronize the
slave with the beginning of each data transfer sequence. NSS can be managed either by
software or by hardware (see Section 26.3.4: Multi-master communication).
Refer to Figure 258 and Figure 259 for a description of continuous transfers in master / full-
duplex and slave full-duplex mode.

Figure 258. TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0,

RXONLY=0) in the case of continuous transfers
Example in Master mode with CPOL=1, CPHA=1

SCK

DATA1 = 0xF1 DATA2 = 0xF2 DATA3 = 0xF3

MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7

set by hardware set by hardware

TXE flag cleared by software cleared by software set by hardware

Tx buffer 0xF1 0xF2 0xF3

(write SPI_DR)

BSY flag set by hardware reset by hardware

DATA 1 = 0xA1 DATA 2 = 0xA2 DATA 3 = 0xA3

MISO/MOSI (in) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7

set by hardware cleared by software

RXNE flag

Rx buffer 0xA1 0xA2 0xA3

(read SPI_DR)

software software waits software waits software waits software waits software waits
writes 0xF1 until TXE=1 and until RXNE=1 until TXE=1 and until RXNE=1 until RXNE=1
into SPI_DR writes 0xF2 into and reads 0xA1 writes 0xF3 into and reads 0xA2 and reads 0xA3
SPI_DR from SPI_DR SPI_DR from SPI_ DR from SPI_DR
ai17343

For code example, refer to A.17.3: SPI full duplex communication code example.

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Figure 259. TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0,

RXONLY=0) in the case of continuous transfers
Example in Slave mode with CPOL=1, CPHA=1

SCK

DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3

MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7

set by hardware set by hardware

TXE flag cleared by software cleared by software set by hardware

Tx buffer 0xF1 0xF2 0xF3

(write to SPI_DR)

BSY flag set by cleared by software reset by hardware

DATA 1 = 0xA1 DATA 2 = 0xA2 DATA 3 = 0xA3

MISO/MOSI (in) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7

set by hardware cleared by software

RXNE flag

Rx buffer 0xA1 0xA2 0xA3

(read from SPI_DR)

software software waits software waits software waits software waits software waits
writes 0xF1 until TXE=1 and until RXNE=1 until TXE=1 and until RXNE=1 until RXNE=1
into SPI_DR writes 0xF2 into and reads 0xA1 writes 0xF3 into and reads 0xA2 and reads 0xA3
SPI_DR from SPI_DR SPI_DR from SPI_ DR from SPI_DR
ai17344

26.3.10 Procedure for disabling the SPI

When SPI is disabled, it is mandatory to follow the disable procedures described in this
paragraph. It is important to do this before the system enters a low-power mode when the
peripheral clock is stopped. Ongoing transactions can be corrupted in this case. In some
modes the disable procedure is the only way to stop continuous communication running.
Master in full-duplex or transmit only mode can finish any transaction when it stops
providing data for transmission. In this case, the clock stops after the last data transaction.
Standard disable procedure is based on pulling BSY status together with TXE flag to check
if a transmission session is fully completed. This check can be done in specific cases, too,
when it is necessary to identify the end of ongoing transactions, for example:
• When NSS signal is managed by an arbitrary GPIO toggle and the master has to
provide proper end of NSS pulse for slave, or
• When transactions’ streams from DMA are completed while the last data frame or CRC
frame transaction is still ongoing in the peripheral bus.
The correct disable procedure is (except when receive-only mode is used):
1. Wait until RXNE=1 to receive the last data.
2. Wait until TXE=1 and then wait until BSY=0 before disabling the SPI.
3. Read received data.

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Note: During discontinuous communications, there is a 2 APB clock period delay between the
write operation to the SPI_DR register and BSY bit setting. As a consequence it is
mandatory to wait first until TXE is set and then until BSY is cleared after writing the last
data.
The correct disable procedure for certain receive-only modes is:
1. Interrupt the receive flow by disabling SPI (SPE=0) in the specific time window while
the last data frame is ongoing.
2. Wait until BSY=0 (the last data frame is processed).
3. Read received data.
Note: To stop a continuous receive sequence, a specific time window must be respected during
the reception of the last data frame. It starts when the first bit is sampled and ends before
the last bit transfer starts.

26.3.11 Communication using DMA (direct memory addressing)

To operate at its maximum speed and to facilitate the data register read/write process
required to avoid overrun, the SPI features a DMA capability, which implements a simple
request/acknowledge protocol.
A DMA access is requested when the TXE or RXNE enable bit in the SPIx_CR2 register is
set. Separate requests must be issued to the Tx and Rx buffers.
• In transmission, a DMA request is issued each time TXE is set to 1. The DMA then
writes to the SPIx_DR register.
• In reception, a DMA request is issued each time RXNE is set to 1. The DMA then reads
the SPIx_DR register.
Refer to Figure 260 and Figure 261 for a description of the DMA transmission and reception
waveforms.
When the SPI is used only to transmit data, it is possible to enable only the SPI Tx DMA
channel. In this case, the OVR flag is set because the data received is not read. When the
SPI is used only to receive data, it is possible to enable only the SPI Rx DMA channel.
In transmission mode, when the DMA has written all the data to be transmitted (the TCIF
flag is set in the DMA_ISR register), the BSY flag can be monitored to ensure that the SPI
communication is complete. This is required to avoid corrupting the last transmission before
disabling the SPI or entering the Stop mode. The software must first wait until TXE = 1 and
then until BSY = 0.
When starting communication using DMA, to prevent DMA channel management raising
error events, these steps must be followed in order:
1. Enable DMA Rx buffer in the RXDMAEN bit in the SPI_CR2 register, if DMA Rx is
used.
2. Enable DMA streams for Tx and Rx in DMA registers, if the streams are used.
3. Enable DMA Tx buffer in the TXDMAEN bit in the SPI_CR2 register, if DMA Tx is used.
4. Enable the SPI by setting the SPE bit.
For code example, refer to A.17.4: SPI master configuration with DMA code example and
A.17.5: SPI slave configuration with DMA code example.

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To close communication it is mandatory to follow these steps in order:

1. Disable DMA streams for Tx and Rx in the DMA registers, if the streams are used.
2. Disable the SPI by following the SPI disable procedure.
3. Disable DMA Tx and Rx buffers by clearing the TXDMAEN and RXDMAEN bits in the
SPI_CR2 register, if DMA Tx and/or DMA Rx are used.

Figure 260. Transmission using DMA

Example with CPOL=1, CPHA=1

SCK

DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3

MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7

set by hardware set by hardware

TXE flag cleared by DMA write clear by DMA write set by hardware

reset
BSY flag set by hardware by hardware

DMA request ignored by the DMA because

DMA transfer is complete

Tx buffer 0xF1 0xF2 0xF3

(write to SPI_DR)

DMA writes to SPI_DR

set by hardware clear by software

DMA TCIF flag
(DMA transfer complete)

software configures the DMA writes DMA writes DMA writes DMA transfer is software waits software waits until BSY=0
DMA SPI Tx channel DATA1 into DATA2 into DATA3 into complete (TCIF=1 in until TXE=1
to send 3 data items SPI_DR SPI_DR SPI_DR DMA_ISR)
and enables the SPI
ai17349

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Figure 261. Reception using DMA

Example with CPOL=1, CPHA=1

SCK

DATA 1 = 0xA1 DATA 2 = 0xA2 DATA 3 = 0xA3

MISO/MOSI (in) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7

set by hardware clear by DMA read

RXNE flag

DMA request

Rx buffer
0xA1 0xA2 0xA3
(read from SPI_DR)

DMA read from SPI_DR

clear
set by hardware
flag DMA TCIF by software
(DMA transfer complete)

software configures the DMA reads DMA reads DMA reads The DMA transfer is
DMA SPI Rx channel DATA1 from DATA2 from DATA3 from complete (TCIF=1 in
to receive 3 data items SPI_DR SPI_DR SPI_DR DMA_ISR)
and enables the SPI
ai17350

26.3.12 SPI status flags

Three status flags are provided for the application to completely monitor the state of the SPI
bus.

Tx buffer empty flag (TXE)

When it is set, the TXE flag indicates that the Tx buffer is empty and that the next data to be
transmitted can be loaded into the buffer. The TXE flag is cleared by writing to the SPI_DR
register.

Rx buffer not empty (RXNE)

When set, the RXNE flag indicates that there are valid received data in the Rx buffer. It is
cleared by reading from the SPI_DR register.

Busy flag (BSY)

The BSY flag is set and cleared by hardware (writing to this flag has no effect).
When BSY is set, it indicates that a data transfer is in progress on the SPI (the SPI bus is
busy). There is one exception in master bidirectional receive mode (MSTR=1 and BDM=1
and BDOE=0) where the BSY flag is kept low during reception.
The BSY flag can be used in certain modes to detect the end of a transfer, thus preventing
corruption of the last transfer when the SPI peripheral clock is disabled before entering a
low-power mode or an NSS pulse end is handled by software.
The BSY flag is also useful for preventing write collisions in a multimaster system.

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The BSY flag is cleared under any one of the following conditions:
• When the SPI is correctly disabled
• When a fault is detected in Master mode (MODF bit set to 1)
• In Master mode, when it finishes a data transmission and no new data is ready to be
sent
• In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
each data transfer.
Note: It is recommended to use always the TXE and RXNE flags (instead of the BSY flags) to
handle data transmission or reception operations.

26.3.13 SPI error flags

An SPI interrupt is generated if one of the following error flags is set and interrupt is enabled
by setting the ERRIE bit.

Overrun flag (OVR)

An overrun condition occurs when the master or the slave completes the reception of the
next data frame while the read operation of the previous frame from the Rx buffer has not
completed (case RXNE flag is set).
In this case, the content of the Rx buffer is not updated with the new data received. A read
operation from the SPI_DR register returns the frame previously received. All other
subsequently transmitted data are lost.
Clearing the OVR bit is done by a read access to the SPI_DR register followed by a read
access to the SPI_SR register.

Mode fault (MODF)

Mode fault occurs when the master device has its internal NSS signal (NSS pin in NSS
hardware mode, or SSI bit in NSS software mode) pulled low. This automatically sets the
MODF bit. Master mode fault affects the SPI interface in the following ways:
• The MODF bit is set and an SPI interrupt is generated if the ERRIE bit is set.
• The SPE bit is cleared. This blocks all output from the device and disables the SPI
interface.
• The MSTR bit is cleared, thus forcing the device into slave mode.
Use the following software sequence to clear the MODF bit:
1. Make a read or write access to the SPIx_SR register while the MODF bit is set.
2. Then write to the SPIx_CR1 register.
To avoid any multiple slave conflicts in a system comprising several MCUs, the NSS pin
must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits can
be restored to their original state after this clearing sequence. As a security, hardware does
not allow the SPE and MSTR bits to be set while the MODF bit is set. In a slave device the
MODF bit cannot be set except as the result of a previous multimaster conflict.

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CRC error (CRCERR)

This flag is used to verify the validity of the value received when the CRCEN bit in the
SPIx_CR1 register is set. The CRCERR flag in the SPIx_SR register is set if the value
received in the shift register does not match the receiver SPIx_RXCRC value. The flag is
cleared by the software.

TI mode frame format error (FRE)

A TI mode frame format error is detected when an NSS pulse occurs during an ongoing
communication when the SPI is operating in slave mode and configured to conform to the TI
mode protocol. When this error occurs, the FRE flag is set in the SPIx_SR register. The SPI
is not disabled when an error occurs, the NSS pulse is ignored, and the SPI waits for the
next NSS pulse before starting a new transfer. The data may be corrupted since the error
detection may result in the loss of two data bytes.
The FRE flag is cleared when SPIx_SR register is read. If the ERRIE bit is set, an interrupt
is generated on the NSS error detection. In this case, the SPI should be disabled because
data consistency is no longer guaranteed and communications should be re-initiated by the
master when the slave SPI is enabled again.

26.4 SPI special features

26.4.1 TI mode
TI protocol in master mode
The SPI interface is compatible with the TI protocol. The FRF bit of the SPIx_CR2 register
can be used to configure the SPI to be compliant with this protocol.
The clock polarity and phase are forced to conform to the TI protocol requirements whatever
the values set in the SPIx_CR1 register. NSS management is also specific to the TI protocol
which makes the configuration of NSS management through the SPIx_CR1 and SPIx_CR2
registers (SSM, SSI, SSOE) impossible in this case.
In slave mode, the SPI baud rate prescaler is used to control the moment when the MISO
pin state changes to HiZ when the current transaction finishes (see Figure 262). Any baud
rate can be used, making it possible to determine this moment with optimal flexibility.
However, the baud rate is generally set to the external master clock baud rate. The delay for
the MISO signal to become HiZ (trelease) depends on internal resynchronization and on the
baud rate value set in through the BR[2:0] bits in the SPIx_CR1 register. It is given by the
formula:

t baud_rate t baud_rate
---------------------- + 4 × t pclk < t release < ---------------------
- + 6 × t pclk
2 2
If the slave detects a misplaced NSS pulse during a data frame transaction the TIFRE flag is
set.
This feature is not available for Motorola SPI communications (FRF bit set to 0).

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Note: To detect TI frame errors in slave transmitter only mode by using the Error interrupt
(ERRIE=1), the SPI must be configured in 2-line unidirectional mode by setting BIDIMODE
and BIDIOE to 1 in the SPI_CR1 register. When BIDIMODE is set to 0, OVR is set to 1
because the data register is never read and error interrupts are always generated, while
when BIDIMODE is set to 1, data are not received and OVR is never set.
Figure 262 shows the SPI communication waveforms when TI mode is selected.

Figure 262. TI mode transfer

NSS
tri ng

g
t RELEASE
in

in
i
er

er

sa r
pl

pl

pl
e
gg

gg

gg
m

m
sa

sa
tri

tr i

SCK

MOSI Do not care MSB LSB MSB LSB

MISO 1 or 0 MSB LSB MSB LSB

FRAME 1 FRAME 2

MS19835V2

26.4.2 CRC calculation

Two separate CRC calculators (on transmission and reception data flows) are implemented
in order to check the reliability of transmitted and received data. The SPI offers CRC8 or
CRC16 calculation depending on the data format selected through the DFF bit. The CRC is
calculated serially using the polynomial programmed in the SPI_CRCPR register.

CRC principle
CRC calculation is enabled by setting the CRCEN bit in the SPIx_CR1 register before the
SPI is enabled (SPE = 1). The CRC value is calculated using an odd programmable
polynomial on each bit. The calculation is processed on the sampling clock edge defined by
the CPHA and CPOL bits in the SPIx_CR1 register. The calculated CRC value is checked
automatically at the end of the data block as well as for transfer managed by CPU or by the
DMA. When a mismatch is detected between the CRC calculated internally on the received
data and the CRC sent by the transmitter, a CRCERR flag is set to indicate a data corruption
error. The right procedure for handling the CRC calculation depends on the SPI
configuration and the chosen transfer management.
Note: The polynomial value should only be odd. No even values are supported.

CRC transfer managed by CPU

Communication starts and continues normally until the last data frame has to be sent or
received in the SPIx_DR register. Then CRCNEXT bit has to be set in the SPIx_CR1
register to indicate that the CRC frame transaction will follow after the transaction of the
currently processed data frame. The CRCNEXT bit must be set before the end of the last
data frame transaction. CRC calculation is frozen during CRC transaction.

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The received CRC is stored in the Rx buffer like any other data frame.
A CRC-format transaction takes one more data frame to communicate at the end of data
sequence.
When the last CRC data is received, an automatic check is performed comparing the
received value and the value in the SPIx_RXCRC register. Software has to check the
CRCERR flag in the SPIx_SR register to determine if the data transfers were corrupted or
not. Software clears the CRCERR flag by writing '0' to it.
After the CRC reception, the CRC value is stored in the Rx buffer and must be read in the
SPIx_DR register in order to clear the RXNE flag.

CRC transfer managed by DMA

When SPI communication is enabled with CRC communication and DMA mode, the
transmission and reception of the CRC at the end of communication is automatic (with the
exception of reading CRC data in receive-only mode). The CRCNEXT bit does not have to
be handled by the software. The counter for the SPI transmission DMA channel has to be
set to the number of data frames to transmit excluding the CRC frame. On the receiver side,
the received CRC value is handled automatically by DMA at the end of the transaction but
user must take care to flush out the CRC frame received from SPI_DR as it is always loaded
into it.
At the end of the data and CRC transfers, the CRCERR flag in the SPIx_SR register is set if
corruption occurred during the transfer.

Resetting the SPIx_TXCRC and SPIx_RXCRC values

The SPIx_TXCRC and SPIx_RXCRC values are cleared automatically when CRC
calculation is enabled.
When the SPI is configured in slave mode with the CRC feature enabled, a CRC calculation
is performed even if a high level is applied on the NSS pin. This may happen for example in
case of a multislave environment where the communication master addresses slaves
alternately.
Between a slave disabling (high level on NSS) and a new slave enabling (low level on NSS),
the CRC value should be cleared on both master and slave sides to resynchronize the
master and slave respective CRC calculation.
To clear the CRC, follow the below sequence:
1. Disable the SPI
2. Clear the CRCEN bit
3. Enable the CRCEN bit
4. Enable the SPI
Note: When the SPI interface is configured as a slave, the NSS internal signal needs to be kept
low during transaction of the CRC phase once the CRCNEXT signal is released, (see more
details at the product errata sheet).
At TI mode, despite the fact that the clock phase and clock polarity setting is fixed and
independent on the SPIx_CR1 register, the corresponding setting CPOL=0 CPHA=1 has to
be kept at the SPIx_CR1 register anyway if CRC is applied. In addition, the CRC calculation
has to be reset between sessions by the SPI disable sequence by re-enabling the CRCEN
bit described above at both master and slave sides, else the CRC calculation can be
corrupted at this specific mode.

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26.5 SPI interrupts

During SPI communication an interrupts can be generated by the following events:
• Transmit Tx buffer ready to be loaded
• Data received in Rx buffer
• Master mode fault
• Overrun error
• TI frame format error
Interrupts can be enabled and disabled separately.

Table 135. SPI interrupt requests

Interrupt event Event flag Enable Control bit

Transmit Tx buffer ready to be loaded TXE TXEIE

Data received in Rx buffer RXNE RXNEIE
Master Mode fault event MODF
Overrun error OVR
ERRIE
CRC error CRCERR
TI frame format error FRE

For code example, refer to A.17.6: SPI interrupt code example.

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26.6 I2S functional description

26.6.1 I2S general description

The block diagram of the I2S is shown in Figure 263.

Figure 263. I2S block diagram

Address and data bus

Tx buffer

CRC CH
16-bit BSY OVR MODF UDR TxE RxNE FRE
ERR SIDE

MOSI/SD

Shift register
MISO LSB first Communication
16-bit control
Rx buffer

NSS/WS

I2SCFG I2SSTD CK DATLEN CH

[1:0] [1:0] POL [1:0] LEN

I2S
I2SE
MOD

Master control logic

Bidi Bidi CRC CRC Rx

SSM SSI
mode OE EN Next DFF only

SPI LSB
SPE BR2 BR1 BR0 MSTR CPOL CPHA
baud rate generator First

CK

I2S clock generator

I2S_CK

I2SMOD

MCK I2SxCLK
MCKOE ODD I2SDIV[7:0]

MS32126V1

1. MCK is mapped on the MISO pin.

The SPI can function as an audio I2S interface when the I2S capability is enabled (by setting
the I2SMOD bit in the SPIx_I2SCFGR register). This interface mainly uses the same pins,
flags and interrupts as the SPI.

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The I2S shares three common pins with the SPI:

• SD: Serial Data (mapped on the MOSI pin) to transmit or receive the two time-
multiplexed data channels (in half-duplex mode only).
• WS: Word Select (mapped on the NSS pin) is the data control signal output in master
mode and input in slave mode.
• CK: Serial Clock (mapped on the SCK pin) is the serial clock output in master mode
and serial clock input in slave mode.
An additional pin can be used when a master clock output is needed for some external
audio devices:
• MCK: Master Clock (mapped separately) is used, when the I2S is configured in master
mode (and when the MCKOE bit in the SPIx_I2SPR register is set), to output this
additional clock generated at a preconfigured frequency rate equal to 256 × fS, where
fS is the audio sampling frequency.
The I2S uses its own clock generator to produce the communication clock when it is set in
master mode. This clock generator is also the source of the master clock output. Two
additional registers are available in I2S mode. One is linked to the clock generator
configuration SPIx_I2SPR and the other one is a generic I2S configuration register
SPIx_I2SCFGR (audio standard, slave/master mode, data format, packet frame, clock
polarity, etc.).
The SPIx_CR1 register and all CRC registers are not used in the I2S mode. Likewise, the
SSOE bit in the SPIx_CR2 register and the MODF and CRCERR bits in the SPIx_SR are
not used.
The I2S uses the same SPI register for data transfer (SPIx_DR) in 16-bit wide mode.

26.6.2 I2S full-duplex

Figure 264 shows how to perform full-duplex communications using two SPI/I2S instances.
In this case, the WS and CK IOs of both SPI2S must be connected together.
For the master full-duplex mode, one of the SPI2S block must be programmed in master
(I2SCFG = ‘10’ or ‘11’), and the other SPI2S block must be programmed in slave (I2SCFG =
‘00’ or ‘01’). The MCK can be generated or not, depending on the application needs.
For the slave full-duplex mode, both SPI2S blocks must be programmed in slave. One of
them in the slave receiver (I2SCFG = ‘01’), and the other in the slave transmitter (I2SCFG =
‘00’). The master external device then provides the bit clock (CK) and the frame
synchronization (WS).
Note that the full-duplex mode can be used for all the supported standards: I2S Philips, MSB
justified, LSB justified and PCM.
For the full-duplex mode, both SPI2S instances must use the same standard, with the same
parameters: I2SMOD, I2SSTD, CKPOL, PCMSYNC, DATLEN and CHLEN must contain the
same value on both instances.

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Figure 264. Full-duplex communication

MASTER full-duplex configurations

STM32 STM32
MCK (O) MCK (O)
spix_tx_dm SD (O) spix_rx_dm SD (I)
a SPI2Sx a SPI2Sx
(MASTER-TX) CK (O) (MASTER-RX) CK (O)
External External
WS (O) WS (O)
slave slave
device device
WS (I) WS (I)
spix_rx_dm SPI2Sy CK (I) spix_tx_dm SPI2Sy CK (I)
a (SLAVE-RX) a (SLAVE-TX)
SD (I) SD (O)

SLAVE full-duplex configurations

STM32
SD (O)
spix_tx_dm
SPI2Sx
a CK (I)
(SLAVE-TX)
External
WS (I)
master
WS (I) device
Optional
Master spix_rx_dm SPI2Sy CK (I)
Slave a (SLAVE-RX)
SD (I)

MSv42093V1

26.6.3 Supported audio protocols

The three-line bus has to handle only audio data generally time-multiplexed on two
channels: the right channel and the left channel. However there is only one 16-bit register
for transmission or reception. So, it is up to the software to write into the data register the
appropriate value corresponding to each channel side, or to read the data from the data
register and to identify the corresponding channel by checking the CHSIDE bit in the
SPIx_SR register. Channel left is always sent first followed by the channel right (CHSIDE
has no meaning for the PCM protocol).
Four data and packet frames are available. Data may be sent with a format of:
• 16-bit data packed in a 16-bit frame
• 16-bit data packed in a 32-bit frame
• 24-bit data packed in a 32-bit frame
• 32-bit data packed in a 32-bit frame
When using 16-bit data extended on 32-bit packet, the first 16 bits (MSB) are the significant
bits, the 16-bit LSB is forced to 0 without any need for software action or DMA request (only
one read/write operation).
The 24-bit and 32-bit data frames need two CPU read or write operations to/from the
SPIx_DR register or two DMA operations if the DMA is preferred for the application. For 24-
bit data frame specifically, the 8 non significant bits are extended to 32 bits with 0-bits (by
hardware).
For all data formats and communication standards, the most significant bit is always sent
first (MSB first).

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The I2S interface supports four audio standards, configurable using the I2SSTD[1:0] and
PCMSYNC bits in the SPIx_I2SCFGR register.

I2S Philips standard

For this standard, the WS signal is used to indicate which channel is being transmitted. It is
activated one CK clock cycle before the first bit (MSB) is available.

Figure 265. I2S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0)
CK

WS transmission reception

Can be 16-bit or 32-bit

SD MSB LSB MSB

Channel left
Channel
right
MS19591V1

Data are latched on the falling edge of CK (for the transmitter) and are read on the rising
edge (for the receiver). The WS signal is also latched on the falling edge of CK.

Figure 266. I2S Philips standard waveforms (24-bit frame with CPOL = 0)

CK

WS Transmission Reception

24-bit data 8-bit remaining 0 forced

SD
MSB LSB

Channel left 32-bit

Channel right

MS19592V1

This mode needs two write or read operations to/from the SPIx_DR register.

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• In transmission mode:
If 0x8EAA33 has to be sent (24-bit):

Figure 267. Transmitting 0x8EAA33

First write to Data register Second write to Data register

0x8EAA 0x33XX
Only the 8 MSB are sent
to compare the 24 bits
8 LSBs have no meaning
and can be anything

MS19593V1

• In reception mode:
If data 0x8EAA33 is received:

Figure 268. Receiving 0x8EAA33

First read to Data register Second read to Data register
0x8EAA 0x33XX
Only the 8 MSB are sent
to compare the 24 bits
8 LSBs have no meaning
and can be anything

MS19594V1

Figure 269. I2S Philips standard (16-bit extended to 32-bit packet frame with
CPOL = 0)
CK

WS Transmission Reception

16-bit data 16-bit remaining 0 forced

SD
MSB LSB

Channel left 32-bit

Channel right

MS19599V1

When 16-bit data frame extended to 32-bit channel frame is selected during the I2S
configuration phase, only one access to the SPIx_DR register is required. The 16 remaining
bits are forced by hardware to 0x0000 to extend the data to 32-bit format.
If the data to transmit or the received data are 0x76A3 (0x76A30000 extended to 32-bit), the
operation shown in Figure 270 is required.

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Figure 270. Example of 16-bit data frame extended to 32-bit channel frame

Only one access to SPIx_DR

0x76A3

MS19595V1

For transmission, each time an MSB is written to SPIx_DR, the TXE flag is set and its
interrupt, if allowed, is generated to load the SPIx_DR register with the new value to send.
This takes place even if 0x0000 have not yet been sent because it is done by hardware.
For reception, the RXNE flag is set and its interrupt, if allowed, is generated when the first
16 MSB half-word is received.
In this way, more time is provided between two write or read operations, which prevents
underrun or overrun conditions (depending on the direction of the data transfer).

MSB justified standard

For this standard, the WS signal is generated at the same time as the first data bit, which is
the MSBit.

Figure 271. MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0

CK

WS Transmission Reception

16- or 32 bit data

SD
MSB LSB MSB

Channel left
Channel right

MS30100 V1

Data are latched on the falling edge of CK (for transmitter) and are read on the rising edge
(for the receiver).

Figure 272. MSB justified 24-bit frame length with CPOL = 0

CK

WS Transmission Reception

24 bit data 8-bit remaining

SD 0 forced
MSB LSB
Channel left 32-bit

Channel right

MS30101V1

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Figure 273. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0

CK

WS Transmission Reception

16-bit data 16-bit remaining

SD 0 forced
MSB LSB
Channel left 32-bit

Channel right

MS30102V1

LSB justified standard

This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit
full-accuracy frame formats).

Figure 274. LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0

CK

WS
Transmission Reception
16- or 32-bit data
SD
MSB LSB MSB
Channel left

Channel right
MS30103V1

Figure 275. LSB justified 24-bit frame length with CPOL = 0

CK

WS Reception
Transmission
8-bit data 24-bit remaining
SD 0 forced
MSB LSB

Channel left 32-bit

Channel right

MS30104V1

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• In transmission mode:
If data 0x3478AE have to be transmitted, two write operations to the SPIx_DR register
are required by software or by DMA. The operations are shown below.

Figure 276. Operations required to transmit 0x3478AE

First write to Data register Second write to Data register

conditioned by TXE=1 conditioned by TXE=1

0xXX34 0x78AE

Only the 8 LSB of the

half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs. MS19596V1

• In reception mode:
If data 0x3478AE are received, two successive read operations from the SPIx_DR
register are required on each RXNE event.

Figure 277. Operations required to receive 0x3478AE

First read from Data register Second read from Data register
conditioned by RXNE=1 conditioned by RXNE=1

0xXX34 0x78AE

Only the 8 LSB of the

half-word are significant.
A field of 0x00 is forced
instead of the 8 MSBs.

MS19597V1

Figure 278. LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0

CK

Reception
WS
Transmission
16-bit data 16-bit remaining
SD 0 forced
MSB LSB

Channel left 32-bit

Channel right
MS30105V1

When 16-bit data frame extended to 32-bit channel frame is selected during the I2S
configuration phase, Only one access to the SPIx_DR register is required. The 16 remaining
bits are forced by hardware to 0x0000 to extend the data to 32-bit format. In this case it
corresponds to the half-word MSB.
If the data to transmit or the received data are 0x76A3 (0x0000 76A3 extended to 32-bit),
the operation shown in Figure 279 is required.

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Figure 279. Example of 16-bit data frame extended to 32-bit channel frame
Only one access to the SPIx-DR register

0x76A3

MS19598V1

In transmission mode, when a TXE event occurs, the application has to write the data to be
transmitted (in this case 0x76A3). The 0x000 field is transmitted first (extension on 32-bit).
The TXE flag is set again as soon as the effective data (0x76A3) is sent on SD.
In reception mode, RXNE is asserted as soon as the significant half-word is received (and
not the 0x0000 field).
In this way, more time is provided between two write or read operations to prevent underrun
or overrun conditions.

PCM standard
For the PCM standard, there is no need to use channel-side information. The two PCM
modes (short and long frame) are available and configurable using the PCMSYNC bit in
SPIx_I2SCFGR register.

Figure 280. PCM standard waveforms (16-bit)

CK

WS
short frame
13-bits
WS
long frame

SD MSB LSB MSB

MS30106V1

For long frame synchronization, the WS signal assertion time is fixed to 13 bits in master
mode.
For short frame synchronization, the WS synchronization signal is only one cycle long.

Figure 281. PCM standard waveforms (16-bit extended to 32-bit packet frame)

CK

WS
short frame
Up to 13-bits
WS
long frame
16 bits

SD MSB LSB

MS30107V1

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Note: For both modes (master and slave) and for both synchronizations (short and long), the
number of bits between two consecutive pieces of data (and so two synchronization signals)
needs to be specified (DATLEN and CHLEN bits in the SPIx_I2SCFGR register) even in
slave mode.

26.6.4 Clock generator

The I2S bitrate determines the data flow on the I2S data line and the I2S clock signal
frequency.
I2S bitrate = number of bits per channel × number of channels × sampling audio frequency
For a 16-bit audio, left and right channel, the I2S bitrate is calculated as follows:
I2S bitrate = 16 × 2 × fS
It will be: I2S bitrate = 32 x 2 x fS if the packet length is 32-bit wide.

Figure 282. Audio sampling frequency definition

16-or 32-bit left 16-or 32-bit

channel right channel

32- or 64-bits
FS
sampling point sampling point

FS : audio sampling frequency

MS30108V1

When the master mode is configured, a specific action needs to be taken to properly
program the linear divider in order to communicate with the desired audio frequency.
Figure 283 presents the communication clock architecture. The I2SxCLK clock is provided
by the RCC block, refer to the RCC section for details.

Figure 283. I2S clock generator architecture

MCK

I²SxCLK 8-bit linear divider

+ reshaping stage 0
Div2 0
Divider by 4 1 CK
1

MCKOE
I²SMOD

CHLEN

MCKOE ODD I²SDIV[7:0]

MS30109V1

1. Where x = 2.

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The audio sampling frequency may be 192 KHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz,
22.05 kHz, 16 kHz, 11.025 kHz or 8 kHz (or any other value within this range). In order to
reach the desired frequency, the linear divider needs to be programmed according to the
formulas below:
When the master clock is generated (MCKOE in the SPIx_I2SPR register is set):
fS = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16-bit wide
fS = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32-bit wide
When the master clock is disabled (MCKOE bit cleared):
fS = I2SxCLK / [(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16-bit wide
fS = I2SxCLK / [(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32-bit wide
Table 136 provides example precision values for different clock configurations.
Note: Other configurations are possible that allow optimum clock precision.

Table 136. Audio-frequency precision using standard 8 MHz HSE

I2SxCLK Data
I2SDIV I2SODD MCLK Target fs(Hz) Real fs (kHz) Error
(MHz) length

32 16 5 0 No 96000 100 4.1667%

32 32 2 0 No 96000 100 4.1667%
32 16 10 1 No 48000 47.619 0.7937%
32 32 5 0 No 48000 50 4.1667%
32 16 11 1 No 44100 43.478 1.4098%
32 32 5 1 No 44100 45.454 3.0715%
32 16 15 1 No 32000 32.258 0.8065%
32 32 8 0 No 32000 31.25 2.3430%
32 16 22 1 No 22050 22.222 0.7811%
32 32 11 1 No 22050 21.739 1.4098%
32 16 31 1 No 16000 15.873 0.7937%
32 32 15 1 No 16000 16.129 0.8065%
32 16 45 1 No 11025 10.989 0.3264%
32 32 22 1 No 11025 11.111 0.7811%
32 16 62 1 No 8000 8 0.0000%
32 32 31 1 No 8000 7.936 0.7937%
32 16 2 0 Yes 32000 31.25 2.3430%
32 32 2 0 Yes 32000 31.25 2.3430%
32 16 3 0 Yes 22050 20.833 5.5170%
32 32 3 0 Yes 22050 20.833 5.5170%
32 16 4 0 Yes 16000 15.625 2.3428%
32 32 4 0 Yes 16000 15.625 2.3428%
32 16 5 1 Yes 11025 11.363 3.0715%

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Table 136. Audio-frequency precision using standard 8 MHz HSE (continued)

I2SxCLK Data
I2SDIV I2SODD MCLK Target fs(Hz) Real fs (kHz) Error
(MHz) length

32 32 5 1 Yes 11025 11.363 3.0715%

32 16 8 0 Yes 8000 7.812 2.3428%
32 32 8 0 Yes 8000 7.812 2.3428%

26.6.5 I2S master mode

The I2S can be configured in master mode. This means that the serial clock is generated on
the CK pin as well as the Word Select signal WS. Master clock (MCK) may be output or not,
controlled by the MCKOE bit in the SPIx_I2SPR register.

Procedure
1. Select the I2SDIV[7:0] bits in the SPIx_I2SPR register to define the serial clock baud
rate to reach the proper audio sample frequency. The ODD bit in the SPIx_I2SPR
register also has to be defined.
2. Select the CKPOL bit to define the steady level for the communication clock. Set the
MCKOE bit in the SPIx_I2SPR register if the master clock MCK needs to be provided
to the external ADC audio component (the I2SDIV and ODD values should be
computed depending on the state of the MCK output, for more details refer to
Section 26.6.4: Clock generator).
3. Set the I2SMOD bit in the SPIx_I2SCFGR register to activate the I2S functions and
choose the I2S standard through the I2SSTD[1:0] and PCMSYNC bits, the data length
through the DATLEN[1:0] bits and the number of bits per channel by configuring the
CHLEN bit. Select also the I2S master mode and direction (Transmitter or Receiver)
through the I2SCFG[1:0] bits in the SPIx_I2SCFGR register.
4. If needed, select all the potential interrupt sources and the DMA capabilities by writing
the SPIx_CR2 register.
5. The I2SE bit in SPIx_I2SCFGR register must be set.
WS and CK are configured in output mode. MCK is also an output, if the MCKOE bit in
SPIx_I2SPR is set.

Transmission sequence
The transmission sequence begins when a half-word is written into the Tx buffer.
Lets assume the first data written into the Tx buffer corresponds to the left channel data.
When data are transferred from the Tx buffer to the shift register, TXE is set and data
corresponding to the right channel have to be written into the Tx buffer. The CHSIDE flag
indicates which channel is to be transmitted. It has a meaning when the TXE flag is set
because the CHSIDE flag is updated when TXE goes high.
A full frame has to be considered as a left channel data transmission followed by a right
channel data transmission. It is not possible to have a partial frame where only the left
channel is sent.
The data half-word is parallel loaded into the 16-bit shift register during the first bit
transmission, and then shifted out, serially, to the MOSI/SD pin, MSB first. The TXE flag is

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set after each transfer from the Tx buffer to the shift register and an interrupt is generated if
the TXEIE bit in the SPIx_CR2 register is set.
For more details about the write operations depending on the I2S Standard-mode selected,
refer to Section 26.6.3: Supported audio protocols).
To ensure a continuous audio data transmission, it is mandatory to write the SPIx_DR
register with the next data to transmit before the end of the current transmission.
To switch off the I2S, by clearing I2SE, it is mandatory to wait for TXE = 1 and BSY = 0.

Reception sequence
The operating mode is the same as for transmission mode except for the point 3 (refer to the
procedure described in Section 26.6.5: I2S master mode), where the configuration should
set the master reception mode through the I2SCFG[1:0] bits.
Whatever the data or channel length, the audio data are received by 16-bit packets. This
means that each time the Rx buffer is full, the RXNE flag is set and an interrupt is generated
if the RXNEIE bit is set in SPIx_CR2 register. Depending on the data and channel length
configuration, the audio value received for a right or left channel may result from one or two
receptions into the Rx buffer.
Clearing the RXNE bit is performed by reading the SPIx_DR register.
CHSIDE is updated after each reception. It is sensitive to the WS signal generated by the
I2S cell.
For more details about the read operations depending on the I2S Standard-mode selected,
refer to Section 26.6.3: Supported audio protocols.
If data are received while the previously received data have not been read yet, an overrun is
generated and the OVR flag is set. If the ERRIE bit is set in the SPIx_CR2 register, an
interrupt is generated to indicate the error.
To switch off the I2S, specific actions are required to ensure that the I2S completes the
transfer cycle properly without initiating a new data transfer. The sequence depends on the
configuration of the data and channel lengths, and on the audio protocol mode selected. In
the case of:
• 16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1)
using the LSB justified mode (I2SSTD = 10)
a) Wait for the second to last RXNE = 1 (n – 1)
b) Then wait 17 I2S clock cycles (using a software loop)
c) Disable the I2S (I2SE = 0)
• 16-bit data length extended on 32-bit channel length (DATLEN = 00 and CHLEN = 1) in
MSB justified, I2S or PCM modes (I2SSTD = 00, I2SSTD = 01 or I2SSTD = 11,
respectively)
a) Wait for the last RXNE
b) Then wait 1 I2S clock cycle (using a software loop)
c) Disable the I2S (I2SE = 0)

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• For all other combinations of DATLEN and CHLEN, whatever the audio mode selected
through the I2SSTD bits, carry out the following sequence to switch off the I2S:
a) Wait for the second to last RXNE = 1 (n – 1)
b) Then wait one I2S clock cycle (using a software loop)
c) Disable the I2S (I2SE = 0)
Note: The BSY flag is kept low during transfers.

26.6.6 I2S slave mode

For the slave configuration, the I2S can be configured in transmission or reception mode.
The operating mode is following mainly the same rules as described for the I2S master
configuration. In slave mode, there is no clock to be generated by the I2S interface. The
clock and WS signals are input from the external master connected to the I2S interface.
There is then no need, for the user, to configure the clock.
The configuration steps to follow are listed below:
1. Set the I2SMOD bit in the SPIx_I2SCFGR register to select I2S mode and choose the
I2S standard through the I2SSTD[1:0] bits, the data length through the DATLEN[1:0]
bits and the number of bits per channel for the frame configuring the CHLEN bit. Select
also the mode (transmission or reception) for the slave through the I2SCFG[1:0] bits in
SPIx_I2SCFGR register.
2. If needed, select all the potential interrupt sources and the DMA capabilities by writing
the SPIx_CR2 register.
3. The I2SE bit in SPIx_I2SCFGR register must be set.

Transmission sequence
The transmission sequence begins when the external master device sends the clock and
when the NSS_WS signal requests the transfer of data. The slave has to be enabled before
the external master starts the communication. The I2S data register has to be loaded before
the master initiates the communication.
For the I2S, MSB justified and LSB justified modes, the first data item to be written into the
data register corresponds to the data for the left channel. When the communication starts,
the data are transferred from the Tx buffer to the shift register. The TXE flag is then set in
order to request the right channel data to be written into the I2S data register.
The CHSIDE flag indicates which channel is to be transmitted. Compared to the master
transmission mode, in slave mode, CHSIDE is sensitive to the WS signal coming from the
external master. This means that the slave needs to be ready to transmit the first data
before the clock is generated by the master. WS assertion corresponds to left channel
transmitted first.
Note: The I2SE has to be written at least two PCLK cycles before the first clock of the master
comes on the CK line.
The data half-word is parallel-loaded into the 16-bit shift register (from the internal bus)
during the first bit transmission, and then shifted out serially to the MOSI/SD pin MSB first.
The TXE flag is set after each transfer from the Tx buffer to the shift register and an interrupt
is generated if the TXEIE bit in the SPIx_CR2 register is set.
Note that the TXE flag should be checked to be at 1 before attempting to write the Tx buffer.

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For more details about the write operations depending on the I2S Standard-mode selected,
refer to Section 26.6.3: Supported audio protocols.
To secure a continuous audio data transmission, it is mandatory to write the SPIx_DR
register with the next data to transmit before the end of the current transmission. An
underrun flag is set and an interrupt may be generated if the data are not written into the
SPIx_DR register before the first clock edge of the next data communication. This indicates
to the software that the transferred data are wrong. If the ERRIE bit is set into the SPIx_CR2
register, an interrupt is generated when the UDR flag in the SPIx_SR register goes high. In
this case, it is mandatory to switch off the I2S and to restart a data transfer starting from the
left channel.
To switch off the I2S, by clearing the I2SE bit, it is mandatory to wait for TXE = 1 and
BSY = 0.

Reception sequence
The operating mode is the same as for the transmission mode except for the point 1 (refer to
the procedure described in Section 26.6.6: I2S slave mode), where the configuration should
set the master reception mode using the I2SCFG[1:0] bits in the SPIx_I2SCFGR register.
Whatever the data length or the channel length, the audio data are received by 16-bit
packets. This means that each time the RX buffer is full, the RXNE flag in the SPIx_SR
register is set and an interrupt is generated if the RXNEIE bit is set in the SPIx_CR2
register. Depending on the data length and channel length configuration, the audio value
received for a right or left channel may result from one or two receptions into the RX buffer.
The CHSIDE flag is updated each time data are received to be read from the SPIx_DR
register. It is sensitive to the external WS line managed by the external master component.
Clearing the RXNE bit is performed by reading the SPIx_DR register.
For more details about the read operations depending the I2S Standard-mode selected,
refer to Section 26.6.3: Supported audio protocols.
If data are received while the preceding received data have not yet been read, an overrun is
generated and the OVR flag is set. If the bit ERRIE is set in the SPIx_CR2 register, an
interrupt is generated to indicate the error.
To switch off the I2S in reception mode, I2SE has to be cleared immediately after receiving
the last RXNE = 1.
Note: The external master components should have the capability of sending/receiving data in 16-
bit or 32-bit packets via an audio channel.

26.6.7 I2S status flags

Three status flags are provided for the application to fully monitor the state of the I2S bus.

Busy flag (BSY)

The BSY flag is set and cleared by hardware (writing to this flag has no effect). It indicates
the state of the communication layer of the I2S.
When BSY is set, it indicates that the I2S is busy communicating. There is one exception in
master receive mode (I2SCFG = 11) where the BSY flag is kept low during reception.

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The BSY flag is useful to detect the end of a transfer if the software needs to disable the I2S.
This avoids corrupting the last transfer. For this, the procedure described below must be
strictly respected.
The BSY flag is set when a transfer starts, except when the I2S is in master receiver mode.
The BSY flag is cleared:
• When a transfer completes (except in master transmit mode, in which the
communication is supposed to be continuous)
• When the I2S is disabled
When communication is continuous:
• In master transmit mode, the BSY flag is kept high during all the transfers
• In slave mode, the BSY flag goes low for one I2S clock cycle between each transfer
Note: Do not use the BSY flag to handle each data transmission or reception. It is better to use the
TXE and RXNE flags instead.

Tx buffer empty flag (TXE)

When set, this flag indicates that the Tx buffer is empty and the next data to be transmitted
can then be loaded into it. The TXE flag is reset when the Tx buffer already contains data to
be transmitted. It is also reset when the I2S is disabled (I2SE bit is reset).

RX buffer not empty (RXNE)

When set, this flag indicates that there are valid received data in the RX Buffer. It is reset
when SPIx_DR register is read.

Channel Side flag (CHSIDE)

In transmission mode, this flag is refreshed when TXE goes high. It indicates the channel
side to which the data to transfer on SD has to belong. In case of an underrun error event in
slave transmission mode, this flag is not reliable and I2S needs to be switched off and
switched on before resuming the communication.
In reception mode, this flag is refreshed when data are received into SPIx_DR. It indicates
from which channel side data have been received. Note that in case of error (like OVR) this
flag becomes meaningless and the I2S should be reset by disabling and then enabling it
(with configuration if it needs changing).
This flag has no meaning in the PCM standard (for both Short and Long frame modes).
When the OVR or UDR flag in the SPIx_SR is set and the ERRIE bit in SPIx_CR2 is also
set, an interrupt is generated. This interrupt can be cleared by reading the SPIx_SR status
register (once the interrupt source has been cleared).

26.6.8 I2S error flags

There are three error flags for the I2S cell.

Underrun flag (UDR)

In slave transmission mode this flag is set when the first clock for data transmission appears
while the software has not yet loaded any value into SPIx_DR. It is available when the
I2SMOD bit in the SPIx_I2SCFGR register is set. An interrupt may be generated if the

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ERRIE bit in the SPIx_CR2 register is set.

The UDR bit is cleared by a read operation on the SPIx_SR register.

Overrun flag (OVR)

This flag is set when data are received and the previous data have not yet been read from
the SPIx_DR register. As a result, the incoming data are lost. An interrupt may be generated
if the ERRIE bit is set in the SPIx_CR2 register.
In this case, the receive buffer contents are not updated with the newly received data from
the transmitter device. A read operation to the SPIx_DR register returns the previous
correctly received data. All other subsequently transmitted half-words are lost.
Clearing the OVR bit is done by a read operation on the SPIx_DR register followed by a
read access to the SPIx_SR register.

Frame error flag (FRE)

This flag can be set by hardware only if the I2S is configured in Slave mode. It is set if the
external master is changing the WS line while the slave is not expecting this change. If the
synchronization is lost, the following steps are required to recover from this state and
resynchronize the external master device with the I2S slave device:
1. Disable the I2S.
2. Enable it again when the correct level is detected on the WS line (WS line is high in I2S
mode or low for MSB- or LSB-justified or PCM modes.
Desynchronization between master and slave devices may be due to noisy environment on
the SCK communication clock or on the WS frame synchronization line. An error interrupt
can be generated if the ERRIE bit is set. The desynchronization flag (FRE) is cleared by
software when the status register is read.

26.6.9 I2S interrupts

Table 137 provides the list of I2S interrupts.

Table 137. I2S interrupt requests

Interrupt event Event flag Enable control bit

Transmit buffer empty flag TXE TXEIE

Receive buffer not empty flag RXNE RXNEIE
Overrun error OVR
Underrun error UDR ERRIE
Frame error flag FRE

26.6.10 DMA features

In I2S mode, the DMA works in exactly the same way as it does in SPI mode. There is no
difference except that the CRC feature is not available in I2S mode since there is no data
transfer protection system.

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26.7 SPI and I2S registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). In
addition, SPI_DR can be accessed by 8-bit.
Refer to Section 1.2 for a list of abbreviations used in register descriptions.

26.7.1 SPI control register 1 (SPI_CR1) (not used in I2S mode)

Address offset: 0x00
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIDI BIDI CRC CRC RX LSB
DFF SSM SSI SPE BR [2:0] MSTR CPOL CPHA
MODE OE EN NEXT ONLY FIRST
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 BIDIMODE: Bidirectional data mode enable

This bit enables half-duplex communication using common single bidirectional data line.
Keep RXONLY bit clear when bidirectional mode is active.
0: 2-line unidirectional data mode selected
1: 1-line bidirectional data mode selected
Note: This bit is not used in I2S mode
Bit 14 BIDIOE: Output enable in bidirectional mode
This bit combined with the BIDIMODE bit selects the direction of transfer in bidirectional
mode
0: Output disabled (receive-only mode)
1: Output enabled (transmit-only mode)
Note: In master mode, the MOSI pin is used while the MISO pin is used in slave mode.
This bit is not used in I2S mode.
Bit 13 CRCEN: Hardware CRC calculation enable
0: CRC calculation disabled
1: CRC calculation enabled
Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.
It is not used in I2S mode.
Bit 12 CRCNEXT: CRC transfer next
0: Data phase (no CRC phase)
1: Next transfer is CRC (CRC phase)
Note: When the SPI is configured in full-duplex or transmitter only modes, CRCNEXT must be
written as soon as the last data is written to the SPI_DR register.
When the SPI is configured in receiver only mode, CRCNEXT must be set after the
second last data reception.
This bit should be kept cleared when the transfers are managed by DMA.
It is not used in I2S mode.
Bit 11 DFF: Data frame format
0: 8-bit data frame format is selected for transmission/reception
1: 16-bit data frame format is selected for transmission/reception
Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation.
It is not used in I2S mode.

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Bit 10 RXONLY: Receive only mode enable

This bit enables simplex communication using a single unidirectional line to receive data
exclusively. Keep BIDIMODE bit clear when receive only mode is active.
This bit is also useful in a multislave system in which this particular slave is not accessed, the
output from the accessed slave is not corrupted.
0: full-duplex (Transmit and receive)
1: Output disabled (Receive-only mode)
Note: This bit is not used in I2S mode
Bit 9 SSM: Software slave management
When the SSM bit is set, the NSS pin input is replaced with the value from the SSI bit.
0: Software slave management disabled
1: Software slave management enabled
Note: This bit is not used in I2S mode and SPI TI mode
Bit 8 SSI: Internal slave select
This bit has an effect only when the SSM bit is set. The value of this bit is forced onto the
NSS pin and the IO value of the NSS pin is ignored.
Note: This bit is not used in I2S mode and SPI TI mode
Bit 7 LSBFIRST: Frame format
0: MSB transmitted first
1: LSB transmitted first
Note: This bit should not be changed when communication is ongoing.
It is not used in I2S mode and SPI TI mode
Bit 6 SPE: SPI enable
0: Peripheral disabled
1: Peripheral enabled
Note: When disabling the SPI, follow the procedure described in Section 26.3.10: Procedure
for disabling the SPI.
This bit is not used in I2S mode.
Bits 5:3 BR[2:0]: Baud rate control
000: fPCLK/2
001: fPCLK/4
010: fPCLK/8
011: fPCLK/16
100: fPCLK/32
101: fPCLK/64
110: fPCLK/128
111: fPCLK/256
Note: These bits should not be changed when communication is ongoing.
They are not used in I2S mode.

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Bit 2 MSTR: Master selection

0: Slave configuration
1: Master configuration
Note: This bit should not be changed when communication is ongoing.
It is not used in I2S mode.
Bit1 CPOL: Clock polarity
0: CK to 0 when idle
1: CK to 1 when idle
Note: This bit should not be changed when communication is ongoing.
It is not used in I2S mode and SPI TI mode except the case when CRC is applied
at TI mode.
Bit 0 CPHA: Clock phase
0: The first clock transition is the first data capture edge
1: The second clock transition is the first data capture edge
Note: This bit should not be changed when communication is ongoing.
It is not used in I2S mode and SPI TI mode except the case when CRC is applied
at TI mode.

26.7.2 SPI control register 2 (SPI_CR2)

Address offset: 0x04
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. TXEIE RXNEIE ERRIE FRF Res. SSOE TXDMAEN RXDMAEN

rw rw rw rw rw rw rw

Bits 15:8 Reserved, must be kept at reset value.

Bit 7 TXEIE: Tx buffer empty interrupt enable
0: TXE interrupt masked
1: TXE interrupt not masked. Used to generate an interrupt request when the TXE flag is set.
Bit 6 RXNEIE: RX buffer not empty interrupt enable
0: RXNE interrupt masked
1: RXNE interrupt not masked. Used to generate an interrupt request when the RXNE flag is
set.
Bit 5 ERRIE: Error interrupt enable
This bit controls the generation of an interrupt when an error condition occurs (OVR,
CRCERR, MODF, FRE in SPI mode, and UDR, OVR, FRE in I2S mode).
0: Error interrupt is masked
1: Error interrupt is enabled
Bit 4 FRF: Frame format
0: SPI Motorola mode
1 SPI TI mode
Note: This bit is not used in I2S mode.
Bit 3 Reserved. Forced to 0 by hardware.

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Bit 2 SSOE: SS output enable

0: SS output is disabled in master mode and the cell can work in multimaster configuration
1: SS output is enabled in master mode and when the cell is enabled. The cell cannot work
in a multimaster environment.
Note: This bit is not used in I2S mode and SPI TI mode.
Bit 1 TXDMAEN: Tx buffer DMA enable
When this bit is set, the DMA request is made whenever the TXE flag is set.
0: Tx buffer DMA disabled
1: Tx buffer DMA enabled
Bit 0 RXDMAEN: Rx buffer DMA enable
When this bit is set, the DMA request is made whenever the RXNE flag is set.
0: Rx buffer DMA disabled
1: Rx buffer DMA enabled

26.7.3 SPI status register (SPI_SR)

Address offset: 0x08
Reset value: 0x0002
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRC
Res. Res. Res. Res. Res. Res. Res. FRE BSY OVR MODF UDR CHSIDE TXE RXNE
ERR
r r r r rc_w0 r r r r

Bits 15:9 Reserved. Forced to 0 by hardware.

Bit 8 FRE: Frame Error
0: No frame error
1: Frame error occurred.
This bit is set by hardware and cleared by software when the SPI_SR register is read.
This bit is used in SPI TI mode or in I2S mode whatever the audio protocol selected. It
detects a change on NSS or WS line which takes place in slave mode at a non expected
time, informing about a desynchronization between the external master device and the
slave.
Bit 7 BSY: Busy flag
0: SPI (or I2S) not busy
1: SPI (or I2S) is busy in communication or Tx buffer is not empty
This flag is set and cleared by hardware.
Note: BSY flag must be used with caution: refer to Section 26.3.12: SPI status flags and
Section 26.3.10: Procedure for disabling the SPI.
Bit 6 OVR: Overrun flag
0: No overrun occurred
1: Overrun occurred
This flag is set by hardware and reset by a software sequence. Refer to Section 26.3.13: SPI
error flags for the software sequence.

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Bit 5 MODF: Mode fault

0: No mode fault occurred
1: Mode fault occurred
This flag is set by hardware and reset by a software sequence. Refer to Section 26.4 on
page 787 for the software sequence.
Note: This bit is not used in I2S mode
Bit 4 CRCERR: CRC error flag
0: CRC value received matches the SPI_RXCRCR value
1: CRC value received does not match the SPI_RXCRCR value
This flag is set by hardware and cleared by software writing 0.
Note: This bit is not used in I2S mode.
Bit 3 UDR: Underrun flag
0: No underrun occurred
1: Underrun occurred
This flag is set by hardware and reset by a software sequence. Refer to Section 26.6.8: I2S
error flags for the software sequence.
Note: This bit is not used in SPI mode.
Bit 2 CHSIDE: Channel side
0: Channel Left has to be transmitted or has been received
1: Channel Right has to be transmitted or has been received
Note: This bit is not used for SPI mode and is meaningless in PCM mode.
Bit 1 TXE: Transmit buffer empty
0: Tx buffer not empty
1: Tx buffer empty
Bit 0 RXNE: Receive buffer not empty
0: Rx buffer empty
1: Rx buffer not empty

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26.7.4 SPI data register (SPI_DR)

Address offset: 0x0C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 DR[15:0]: Data register

Data received or to be transmitted.
The data register is split into 2 buffers - one for writing (Transmit Buffer) and another one for
reading (Receive buffer). A write to the data register will write into the Tx buffer and a read
from the data register will return the value held in the Rx buffer.
Note: These notes apply to SPI mode:
Depending on the data frame format selection bit (DFF in SPI_CR1 register), the data
sent or received is either 8-bit or 16-bit. This selection has to be made before enabling
the SPI to ensure correct operation.
For an 8-bit data frame, the buffers are 8-bit and only the LSB of the register
(SPI_DR[7:0]) is used for transmission/reception. When in reception mode, the MSB of
the register (SPI_DR[15:8]) is forced to 0.
For a 16-bit data frame, the buffers are 16-bit and the entire register, SPI_DR[15:0] is
used for transmission/reception.

26.7.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I2S

mode)
Address offset: 0x10
Reset value: 0x0007
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCPOLY[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CRCPOLY[15:0]: CRC polynomial register

This register contains the polynomial for the CRC calculation.
The CRC polynomial (0007h) is the reset value of this register. Another polynomial can be
configured as required.
Note: These bits are not used for the I2S mode.

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26.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I2S mode)

Address offset: 0x14
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RXCRC[15:0]
r r r r r r r r r r r r r r r r

Bits 15:0 RXCRC[15:0]: Rx CRC register

When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of
the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1
register is written to 1. The CRC is calculated serially using the polynomial programmed in
the SPI_CRCPR register.
Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF
bit of SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard.
The entire 16-bits of this register are considered when a 16-bit data frame format is selected
(DFF bit of the SPI_CR1 register is set). CRC calculation is done based on any CRC16
standard.
Note: A read to this register when the BSY Flag is set could return an incorrect value.These
bits are not used for I2S mode.

26.7.7 SPI TX CRC register (SPI_TXCRCR) (not used in I2S mode)

Address offset: 0x18
Reset value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCRC[15:0]
r r r r r r r r r r r r r r r r

Bits 15:0 TXCRC[15:0]: Tx CRC register

When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of
the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1
is written to 1. The CRC is calculated serially using the polynomial programmed in the
SPI_CRCPR register.
Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF
bit of SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard.
The entire 16-bits of this register are considered when a 16-bit data frame format is selected
(DFF bit of the SPI_CR1 register is set). CRC calculation is done based on any CRC16
standard.
Note: A read to this register when the BSY flag is set could return an incorrect value. These
bits are not used for I2S mode.

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26.7.8 SPI_I2S configuration register (SPI_I2SCFGR)

Address offset: 0x1C
Reset value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCMSY
Res. Res. Res. Res. I2SMOD I2SE I2SCFG Res. I2SSTD CKPOL DATLEN CHLEN
NC
rw rw rw rw rw rw rw rw rw rw rw

Bits 15:12 Reserved, must be kept at reset value.

Bit 11 I2SMOD: I2S mode selection
0: SPI mode is selected
1: I2S mode is selected
Note: This bit should be configured when the SPI or I2S is disabled
Bit 10 I2SE: I2S Enable
0: I2S peripheral is disabled
1: I2S peripheral is enabled
Note: This bit is not used in SPI mode.
Bits 9:8 I2SCFG: I2S configuration mode
00: Slave - transmit
01: Slave - receive
10: Master - transmit
11: Master - receive
Note: This bit should be configured when the I2S is disabled.
It is not used in SPI mode.
Bit 7 PCMSYNC: PCM frame synchronization
0: Short frame synchronization
1: Long frame synchronization
Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used)
It is not used in SPI mode.
Bit 6 Reserved: forced at 0 by hardware
Bits 5:4 I2SSTD: I2S standard selection
00: I2S Philips standard.
01: MSB justified standard (left justified)
10: LSB justified standard (right justified)
11: PCM standard
For more details on I2S standards, refer to Section 26.6.3 on page 793. Not used in SPI mode.
Note: For correct operation, these bits should be configured when the I2S is disabled.

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Bit 3 CKPOL: Steady state clock polarity

0: I2S clock steady state is low level
1: I2S clock steady state is high level
Note: For correct operation, this bit should be configured when the I2S is disabled.
This bit is not used in SPI mode
Bits 2:1 DATLEN: Data length to be transferred
00: 16-bit data length
01: 24-bit data length
10: 32-bit data length
11: Not allowed
Note: For correct operation, these bits should be configured when the I2S is disabled.
This bit is not used in SPI mode.
Bit 0 CHLEN: Channel length (number of bits per audio channel)
0: 16-bit wide
1: 32-bit wide
The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to
32-bit by hardware whatever the value filled in. Not used in SPI mode.
Note: For correct operation, this bit should be configured when the I2S is disabled.

26.7.9 SPI_I2S prescaler register (SPI_I2SPR)

Address offset: 0x20
Reset value: 0000 0010 (0x0002)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. MCKOE ODD I2SDIV
rw rw rw

Bits 15:10 Reserved, must be kept at reset value.

Bit 9 MCKOE: Master clock output enable
0: Master clock output is disabled
1: Master clock output is enabled
Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master
mode.
This bit is not used in SPI mode.
Bit 8 ODD: Odd factor for the prescaler
0: real divider value is = I2SDIV *2
1: real divider value is = (I2SDIV * 2)+1
Refer to Section 26.6.4 on page 800. Not used in SPI mode.
Note: This bit should be configured when the I2S is disabled. It is used only when the I2S is in master
mode.
Bits 7:0 I2SDIV: I2S Linear prescaler
I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values.
Refer to Section 26.6.4 on page 800. Not used in SPI mode.
Note: These bits should be configured when the I2S is disabled. It is used only when the I2S is in
master mode.

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 0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x1C
0x0C
Offset
RM0377

26.7.10

SPI_SR

SPI_DR
Register

SPI_CR2
SPI_CR1

SPI_I2SPR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

Reset value

SPI_CRCPR

SPI_TXCRCR
SPI_RXCRCR

SPI_I2SCFGR
Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
SPI register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. 18

RM0377 Rev 10
Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. 16
Res. Res. Res. Res. BIDIMODE 15
Res. Res. Res. Res. BIDIOE 14
Res. Res. Res. Res. CRCEN 13
Res. Res. Res. Res. CRCNEXT 12
Table 138. SPI register map and reset values

Res. I2SMOD Res. Res. DFF 11

The table provides shows the SPI register map and reset values.

Res. I2SE Res. Res. RXONLY 10

MCKOE Res. Res. SSM

Refer to Section 2.2 on page 51 for the register boundary addresses.

I2SCFG 9
ODD FRE Res. SSI 8

0 0 0 0 0
PCMSYNC BSY TXEIE LSBFIRST 7
DR[15:0]

Res. OVR RXNEIE SPE 6

TxCRC[15:0]
RxCRC[15:0]
MODF ERRIE
CRCPOLY[15:0]

I2SSTD 5
0 0 0 0

CRCERR FRF
BR

4
[2:0]

CKPOL UDR Res. 3

I2SDIV
CHSIDE SSOE MSTR 2
DATLEN
TXE TXDMAEN CPOL 1
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 1 0
0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0
0 0 0
Serial peripheral interface/ inter-IC sound (SPI/I2S)

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27 Debug support (DBG)

27.1 Overview
The STM32L0x1 devices are built around a Cortex®-M0+ core which contains hardware
extensions for advanced debugging features. The debug extensions allow the core to be
stopped either on a given instruction fetch (breakpoint) or data access (watchpoint). When
stopped, the core’s internal state and the system’s external state may be examined. Once
examination is complete, the core and the system may be restored and program execution
resumed.
The debug features are used by the debugger host when connecting to and debugging the
STM32L0x1 MCUs.
One interface for debug is available:
• Serial wire

Figure 284. Block diagram of STM32L0x1 MCU and Cortex®-M0+-level debug support

STM32 MCU debug suppo rt

Cortex-M0 debug support

Bus matrix
System
interface

Cortex-M0
Core

Debug AP

SWDIO Bridge DBGMCU

SW-DP
SWCLK
Debug AP
NVIC

DWT

BPU

MS19240V2

1. The debug features embedded in the Cortex®-M0+ core are a subset of the Arm® CoreSight Design Kit.
® ®
The Arm Cortex -M0+ core provides integrated on-chip debug support. It is comprised of:
• SW-DP: Serial wire
• BPU: Break point unit
• DWT: Data watchpoint trigger

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It also includes debug features dedicated to the STM32L0x1 microcontrollers:

• Flexible debug pinout assignment
• MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on debug functionality supported by the Arm® Cortex®-M0+ core,
refer to the Cortex®-M0+ Technical Reference Manual (see Section 27.2: Reference Arm®
documentation).

27.2 Reference Arm® documentation

• Cortex®-M0+ Technical Reference Manual (TRM)
It is available from www.infocenter.arm.com
• Arm® Debug Interface V5
• Arm® CoreSight Design Kit revision r1p1 Technical Reference Manual

27.3 Pinout and debug port pins

The STM32L0x1 MCUs are available in various packages with different numbers of
available pins.

27.3.1 SWD port pins

Two pins are used as outputs for the SW-DP as alternate functions of general purpose I/Os.
These pins are available on all packages.

Table 139. SW debug port pins

SW debug port
Pin
SW-DP pin name
assignment
Type Debug assignment

SWDIO IO Serial Wire Data Input/Output PA13

SWCLK I Serial Wire Clock PA14

27.3.2 SW-DP pin assignment

After reset (SYSRESETn or PORESETn), the pins used for the SW-DP are assigned as
dedicated pins which are immediately usable by the debugger host.
However, the MCU offers the possibility to disable the SWD port and can then release the
associated pins for general-purpose I/O (GPIO) usage. For more details on how to disable
SW-DP port pins, please refer to Section 8.3.2: I/O pin alternate function multiplexer and
mapping on page 219.

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27.3.3 Internal pull-up & pull-down on SWD pins

Once the SW I/O is released by the user software, the GPIO controller takes control of these
pins. The reset states of the GPIO control registers put the I/Os in the equivalent states:
• SWDIO: input pull-up
• SWCLK: input pull-down
Embedded pull-up and pull-down resistors remove the need to add external resistors.

27.4 ID codes and locking mechanism

There are several ID codes inside the MCU. ST strongly recommends the tool
manufacturers to lock their debugger using the MCU device ID located at address
0x40015800.

27.4.1 MCU device ID code

The STM32L0x1 products integrate an MCU ID code. This ID identifies the ST MCU part
number and the die revision.
This code is accessible by the software debug port (two pins) or by the user software.
Only the DEV_ID[15:0] should be used for identification by the debugger/programmer tools
(the revision ID must not be taken into account).
For code example, refer to A.18.1: DBG read device Id code example.

DBG_IDCODE
Address: 0x4001 5800
Only 32-bit access supported. Read-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REV_ID
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. DEV_ID
r r r r r r r r r r r

Bits 31:16 REV_ID[15:0] Revision identifier

This field indicates the revision of the device (see Table 140: REV_ID values).
Bits 15:12 Reserved: read 0b0110.
Bits 11:0 DEV_ID[11:0]: Device identifier
This field indicates the device ID:
Category 1 devices: 0x457
Category 2 devices: 0x425
Category 3 devices: 0x417
Category 5 devices: 0x447

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Table 140. REV_ID values

REV_ID Cat. 1 devices Cat. 2 devices Cat. 3 devices Cat. 5 devices

0x1000 Rev A
0x1008 Rev 1, Z - Rev Z -
0x1018 - - Rev Y -
0x1038 - - Rev 1, P, Q, X -
0x2000 - Rev B - Rev B
0x2008 - Rev Y - Rev 1, P, Q, Z
0x2018 - Rev 1, X - -

27.5 SWD port

27.5.1 SWD protocol introduction

This synchronous serial protocol uses two pins:
• SWCLK: clock from host to target
• SWDIO: bidirectional
The protocol allows two banks of registers (DPACC registers and APACC registers) to be
read and written to.
Bits are transferred LSB-first on the wire.
For SWDIO bidirectional management, the line must be pulled-up on the board (100 kΩ
recommended by Arm®). These pull-up resistors can be configured internally. No external
pull-up resistors are required. .
Each time the direction of SWDIO changes in the protocol, a turnaround time is inserted
where the line is not driven by the host nor the target. By default, this turnaround time is one
bit time, however this can be adjusted by configuring the SWCLK frequency.

27.5.2 SWD protocol sequence

Each sequence consist of three phases:
1. Packet request (8 bits) transmitted by the host
2. Acknowledge response (3 bits) transmitted by the target
3. Data transfer phase (33 bits) transmitted by the host or the target

Table 141. Packet request (8-bits)

Bit Name Description

0 Start Must be “1”

0: DP Access
1 APnDP
1: AP Access
0: Write Request
2 RnW
1: Read Request

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Table 141. Packet request (8-bits) (continued)

Bit Name Description

Address field of the DP or AP registers (refer to Table 145 on

4:3 A[3:2]
page 824)
5 Parity Single bit parity of preceding bits
6 Stop 0
Not driven by the host. Must be read as “1” by the target
7 Park
because of the pull-up

Refer to the Cortex®-M0+ TRM for a detailed description of DPACC and APACC registers.
The packet request is always followed by the turnaround time (default 1 bit) where neither
the host nor target drive the line.

Table 142. ACK response (3 bits)

Bit Name Description

001: FAULT
0..2 ACK 010: WAIT
100: OK

The ACK Response must be followed by a turnaround time only if it is a READ transaction
or if a WAIT or FAULT acknowledge has been received.

Table 143. DATA transfer (33 bits)

Bit Name Description

WDATA or
0..31 Write or Read data
RDATA
32 Parity Single parity of the 32 data bits

The DATA transfer must be followed by a turnaround time only if it is a READ transaction.

27.5.3 SW-DP state machine (reset, idle states, ID code)

The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It
follows the JEP-106 standard. This ID code is the default Arm® one and is set to
0x0BC1 1477 (corresponding to Cortex®-M0+).
Note: Note that the SW-DP state machine is inactive until the target reads this ID code.
• The SW-DP state machine is in RESET STATE either after power-on reset, or after the
line is high for more than 50 cycles
• The SW-DP state machine is in IDLE STATE if the line is low for at least two cycles
after RESET state.
• After RESET state, it is mandatory to first enter into an IDLE state AND to perform a
READ access of the DP-SW ID CODE register. Otherwise, the target will issue a
FAULT acknowledge response on another transactions.

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Further details of the SW-DP state machine can be found in the Cortex®-M0+ TRM and the
CoreSight Design Kit r1p0 TRM.

27.5.4 DP and AP read/write accesses

• Read accesses to the DP are not posted: the target response can be immediate (if
ACK=OK) or can be delayed (if ACK=WAIT).
• Read accesses to the AP are posted. This means that the result of the access is
returned on the next transfer. If the next access to be done is NOT an AP access, then
the DP-RDBUFF register must be read to obtain the result.
The READOK flag of the DP-CTRL/STAT register is updated on every AP read access
or RDBUFF read request to know if the AP read access was successful.
• The SW-DP implements a write buffer (for both DP or AP writes), that enables it to
accept a write operation even when other transactions are still outstanding. If the write
buffer is full, the target acknowledge response is “WAIT”. With the exception of
IDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write
buffer is full.
• Because of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK
cycles are needed after a write transaction (after the parity bit) to make the write
effective internally. These cycles should be applied while driving the line low (IDLE
state)
This is particularly important when writing the CTRL/STAT for a power-up request. If the
next transaction (requiring a power-up) occurs immediately, it will fail.

27.5.5 SW-DP registers

Access to these registers are initiated when APnDP=0

Table 144. SW-DP registers

CTRLSEL bit
A[3:2] R/W of SELECT Register Notes
register

The manufacturer code is set to the default

00 Read IDCODE Arm® code for Cortex®-M0+:
0x0BC1 1477 (identifies the SW-DP)
00 Write ABORT
Purpose is to:
– request a system or debug power-up
– configure the transfer operation for AP
accesses
01 Read/Write 0 DP-CTRL/STAT
– control the pushed compare and pushed
verify operations.
– read some status flags (overrun, power-up
acknowledges)
Purpose is to configure the physical serial
WIRE
01 Read/Write 1 port protocol (like the duration of the
CONTROL
turnaround time)

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Table 144. SW-DP registers (continued)

CTRLSEL bit
A[3:2] R/W of SELECT Register Notes
register

Enables recovery of the read data from a

READ
10 Read corrupted debugger transfer, without
RESEND
repeating the original AP transfer.
The purpose is to select the current access
10 Write SELECT
port and the active 4-words register window
This read buffer is useful because AP
accesses are posted (the result of a read AP
request is available on the next AP
11 Read/Write READ BUFFER transaction).
This read buffer captures data from the AP,
presented as the result of a previous read,
without initiating a new transaction

27.5.6 SW-AP registers

Access to these registers are initiated when APnDP=1
There are many AP Registers addressed as the combination of:
• The shifted value A[3:2]
• The current value of the DP SELECT register.

Table 145. 32-bit debug port registers addressed through the shifted value A[3:2]
Address A[3:2] value Description

0x0 00 Reserved, must be kept at reset value.

DP CTRL/STAT register. Used to:
– Request a system or debug power-up
0x4 01 – Configure the transfer operation for AP accesses
– Control the pushed compare and pushed verify operations.
– Read some status flags (overrun, power-up acknowledges)
DP SELECT register: Used to select the current access port and the
active 4-words register window.
– Bits 31:24: APSEL: select the current AP
0x8 10 – Bits 23:8: reserved
– Bits 7:4: APBANKSEL: select the active 4-words register window on the
current AP
– Bits 3:0: reserved
DP RDBUFF register: Used to allow the debugger to get the final result
0xC 11 after a sequence of operations (without requesting new JTAG-DP
operation)

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27.6 Core debug

Core debug is accessed through the core debug registers. Debug access to these registers
is by means of the debug access port. It consists of four registers:

Table 146. Core debug registers

Register Description

The 32-bit Debug Halting Control and Status Register

DHCSR This provides status information about the state of the processor enable core debug
halt and step the processor
The 17-bit Debug Core Register Selector Register:
DCRSR
This selects the processor register to transfer data to or from.
The 32-bit Debug Core Register Data Register:
DCRDR This holds data for reading and writing registers to and from the processor selected
by the DCRSR (Selector) register.
The 32-bit Debug Exception and Monitor Control Register:
DEMCR
This provides Vector Catching and Debug Monitor Control.

These registers are not reset by a system reset. They are only reset by a power-on reset.
Refer to the Cortex®-M0+ TRM for further details.
To Halt on reset, it is necessary to:
• enable the bit0 (VC_CORRESET) of the Debug and Exception Monitor Control
Register
• enable the bit0 (C_DEBUGEN) of the Debug Halting Control and Status Register

27.7 BPU (Break Point Unit)

The Cortex®-M0+ BPU implementation provides four breakpoint registers. The BPU is a
subset of the Flash Patch and Breakpoint (FPB) block available in Armv7-M (Cortex®-M3
and Cortex®-M4).

27.7.1 BPU functionality

The processor breakpoints implement PC based breakpoint functionality.
Refer the Armv6-M Arm® and the Arm® CoreSight Components Technical Reference
Manual for more information about the BPU CoreSight identification registers, and their
addresses and access types.

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27.8 DWT (Data Watchpoint)

The Cortex®-M0+ DWT implementation provides two watchpoint register sets.

27.8.1 DWT functionality

The processor watchpoints implement both data address and PC based watchpoint
functionality, a PC sampling register, and support comparator address masking, as
described in the Armv6-M Arm®.

27.8.2 DWT Program Counter Sample Register

A processor that implements the data watchpoint unit also implements the Armv6-M
optional DWT Program Counter Sample Register (DWT_PCSR). This register permits a
debugger to periodically sample the PC without halting the processor. This provides coarse
grained profiling. See the Armv6-M Arm® for more information.
The Cortex®-M0+ DWT_PCSR records both instructions that pass their condition codes and
those that fail.

27.9 MCU debug component (DBG)

The MCU debug component helps the debugger provide support for:
• Low-power modes
• Clock control for timers, watchdog and I2C during a breakpoint

27.9.1 Debug support for low-power modes

To enter low-power mode, the instruction WFI or WFE must be executed.
The MCU implements several low-power modes which can either deactivate the CPU clock
or reduce the power of the CPU.
The core does not allow FCLK or HCLK to be turned off during a debug session. As these
are required for the debugger connection, during a debug, they must remain active. The
MCU integrates special means to allow the user to debug software in low-power modes.
For this, the debugger host must first set some debug configuration registers to change the
low-power mode behavior:
• In Sleep mode: FCLK and HCLK are still active. Consequently, this mode does not
impose any restrictions on the standard debug features.
• In Stop/Standby mode, the DBG_STOP bit must be previously set by the debugger.
This enables the internal RC oscillator clock to feed FCLK and HCLK in Stop mode.
When one of the DBG_STANDBY, DBG_STOP and DBG_SLEEP bit is set and the internal
reference voltage is stopped in low-power mode (ULP bit set in PWR_CR register), then the
Fast wakeup must be enabled (FWU bit set in PWR_CR).
For code example, refer to A.18.2: DBG debug in LPM code example.

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27.9.2 Debug support for timers, watchdog and I2C

During a breakpoint, it is necessary to choose how the counter of timers and watchdog
should behave:
• They can continue to count inside a breakpoint. This is usually required when a PWM is
controlling a motor, for example.
• They can stop to count inside a breakpoint. This is required for watchdog purposes.
For the I2C, the user can choose to block the SMBUS timeout during a breakpoint.

27.9.3 Debug MCU configuration register (DBG_CR)

The DBG_CR register allows to configure the low-power modes when the MCU is under
debug. When one of DBG_CR bits is set, if ULP bit is set in PWR_CR, then FWU bit of
PWR_CR must be set.
It is mapped at address 0x4001 5804.
This register is asynchronously reset by the PORESET (and not the system reset). It can be
written by the debugger under system reset.
If the debugger host does not support these features, it is still possible for the user software
to write to these registers.
Address: 0x04
Only 32-bit access supported
POR Reset: 0x0000 0000 (not reset by system reset)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_
DBG_ DBG_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. STAND
STOP SLEEP
BY
rw rw rw

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Bits 31:3 Reserved, must be kept at reset value.

Bit 2 DBG_STANDBY: Debug Standby mode
0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
From software point of view, exiting from Standby is identical than fetching reset vector
(except a few status bit indicated that the MCU is resuming from Standby)
1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and FCLK and
HCLK are provided by the internal RC oscillator which remains active. In addition, the MCU
generate a system reset during Standby mode so that exiting from Standby is identical than
fetching from reset
Bit 1 DBG_STOP: Debug Stop mode
0: (FCLK=Off, HCLK=Off) In Stop mode, the clock controller disables all clocks (including
HCLK and FCLK). When exiting from Stop mode, the clock configuration is identical to the
one after RESET. Consequently, the software must reprogram the clock controller to enable
the PLL, the Xtal, etc.
1: (FCLK=On, HCLK=On) In this case, when entering Stop mode, FCLK and HCLK are
provided by the internal RC oscillator which remains active in Stop mode. When exiting Stop
mode, the software must reprogram the clock controller to enable the PLL, the Xtal, etc. (in
the same way it would do in case of DBG_STOP=0)
Bit 0 DBG_SLEEP: Debug Sleep mode
0: In Sleep mode, FCLK is clocked by the system clock previously configured by the
software while HCLK is disabled. The clock controller configuration is not reset and remains
in its previously programmed state. As a consequence, when exiting from Sleep mode, the
software does not need to reconfigure the clock controller.
1: In this case, when entering in Sleep mode, HCLK is fed by the same clock that is provided
to FCLK (system clock previously configured by the software).

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27.9.4 Debug MCU APB1 freeze register (DBG_APB1_FZ)

The DBG_APB1_FZ register is used to configure the following APB peripherals, when the
MCU under debug:
• Timer clock counter freeze
• I2C SMBUS timeout freeze
• System window watchdog and independent watchdog counter freeze support.
This register is mapped at address 0x4001 5808.
The register is asynchronously reset by the POR (and not the system reset). It can be
written by the debugger under system reset.
Address offset: 0X08
Only 32-bit access are supported.
Power on reset (POR): 0x0000 0000 (not reset by system reset)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DBG_LPTIMER_STO

DBG_I2C3_STOP

DBG_I2C1_STOP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
P

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBG_WWDG_STOP
DBG_IWDG_STOP

.DBG_TIM3_STOP

.DBG_TIM2_STOP
DBG_TIM7_STOP

DBG_TIM6_STOP
DBG_RTC_STOP

Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw

Bit 31 DBG_LPTIMER_STOP: LPTIM1 counter stopped when core is halted

0: LPTIM1 counter clock is fed even if the core is halted
1: LPTIM1 counter clock is stopped when the core is halted
Bit 30 DBG_I2C3_STOP: I2C3 SMBUS timeout mode stopped when core is halted
0: Same behavior as in normal mode
1: I2C3 SMBUS timeout is frozen
Bits 29:22 Reserved, must be kept at reset value.
Bit 21 DBG_I2C1_STOP: I2C1 SMBUS timeout mode stopped when core is halted
0: Same behavior as in normal mode
1: I2C1 SMBUS timeout is frozen
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 DBG_IWDG_STOP: Debug independent watchdog stopped when core is halted
0: The independent watchdog counter clock continues even if the core is halted
1: The independent watchdog counter clock is stopped when the core is halted

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Bit 11 DBG_WWDG_STOP: Debug window watchdog stopped when core is halted

0: The window watchdog counter clock continues even if the core is halted
1: The window watchdog counter clock is stopped when the core is halted
Bit 10 DBG_RTC_STOP: Debug RTC stopped when core is halted
0: The clock of the RTC counter is fed even if the core is halted
1: The clock of the RTC counter is stopped when the core is halted
Bits 9:6 Reserved, must be kept at reset value.
Bit 5 DBG_TIM7_STOP: TIM7 counter stopped when core is halted
0: The counter clock of TIM7 is fed even if the core is halted
1: The counter clock of TIM7 is stopped when the core is halted
Bit 4 DBG_TIM6_STOP: TIM6 counter stopped when core is halted
0: The counter clock of TIM6 is fed even if the core is halted
1: The counter clock of TIM6 is stopped when the core is halted
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 DBG_TIM3_STOP: TIM3 counter stopped when core is halted
0: The counter clock of TIM3 is fed even if the core is halted
1: The counter clock of TIM3 is stopped when the core is halted
Bit 0 DBG_TIM2_STOP: TIM2 counter stopped when core is halted
0: The counter clock of TIM2 is fed even if the core is halted
1: The counter clock of TIM2 is stopped when the core is halted

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27.9.5 Debug MCU APB2 freeze register (DBG_APB2_FZ)

The DBG_APB2_FZ register is used to configure some APB peripheral features when the
MCU is under DEBUG:
• Timer clock counter freeze.
This register is mapped at address 0x4001580C.
It is asynchronously reset by the POR (and not the system reset). It can be written by the
debugger under system reset.
Address: 0x0C
Only 32-bit access is supported.
POR: 0x0000 0000 (not reset by system reset)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DBG_TIM22_STOP

DBG_TIM21_STOP
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bit 5 DBG_TIM22_STOP: TIM22 counter stopped when core is halted
0: The counter clock of TIM22 is fed even if the core is halted
1: The counter clock of TIM22 is stopped when the core is halted
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 DBG_TIM21_STOP: TIM21 counter stopped when core is halted
0: The counter clock of TIM21 is fed even if the core is halted
1: The counter clock of TIM21 is stopped when the core is halted
Bits 1:0 Reserved, must be kept at reset value.

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 0x4001580C 0x40015808 0x40015804 0x40015800

Addr.

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27.10

DBG_
DBG_
DBG_
IDCODE

DBG_CR

APB2_FZ
APB1_FZ
Register

Reset value
Reset value

Reset value
Reset value(1)

0
DBG_LPTIMER_STO

X
Res. Res. 31
Debug support (DBG)

0
X
Res. DBG_I2C3_STOP. Res. 30

X
Res. Res. Res. 29

X
Res. Res. Res. 28

X
Res. Res. Res. 27

X
Res. Res. Res. 26

X
Res. Res. Res. 25
DBG register map

Res. Res. Res. 24

Res. Res. Res. 23
REV_ID

Res. Res. Res. 22

0
X X X X

Res. DBG_I2C1_STOP Res. 21

X

Res. Res. Res. 20

X

Res. Res. Res. 19

X

Res. Res. Res. 18

X

Res. Res. Res. 17

RM0377 Rev 10
X

Res. Res. Res. 16

Res. Res. Res. Res. 15
The following table summarizes the Debug registers.

Res. Res. Res. Res. 14

Res. Res. Res. Res. 13

0
Res. DBG_IWDG_STOP Res. Res. 12
0
X

Res. DBG_WWDG_STOP Res. 11

Table 147. DBG register map and reset values

0
X

Res. DBG_RTC_STOP Res. 10

X

Res. Res. Res. 9

X

Res. Res. Res. 8

X

Res. Res. Res. 7

X

Res. Res. Res. 6

0
0
X

DBG_TIM22_STOP DBG_TIM7_STOP Res. 5

DEV_ID

0
X

Res. DBG_TIM6_STOP Res. 4

X

Res. Res. Res. 3

0
0
X

DBG_TIM21_STOP Res. DBG_STANDBY

1. The reset value is product dependent. For more information, refer to Section 27.4.1: MCU device ID code.
2
0
0
X

Res. DBG_TIM3_STOP DBG_STOP 1

0
0
X

Res. DBG_TIM2_STOP DBG_SLEEP 0

RM0377
RM0377 Device electronic signature

28 Device electronic signature

This section applies to all STM32L0x1 devices, unless otherwise specified.

The electronic signature is stored in the System memory area in the Flash memory module,
and can be read using the JTAG/SWD or the CPU. It contains factory-programmed
identification data that allow the user firmware or other external devices to automatically
match its interface to the characteristics of the STM32L0x1 microcontroller.

28.1 Memory size register

28.1.1 Flash size register

Base address: 0x1FF8 007C
Read only = 0xXXXX where X is factory-programmed

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F_SIZE
r r r r r r r r r r r r r r r r

Bits 15:0 F_SIZE: Flash memory size

The value stored in this field indicates the Flash memory size of the device expressed in
Kbytes.
Example: 0x0040 = 64 Kbytes.

28.2 Unique device ID registers (96 bits)

The unique device identifier is ideally suited:
• for use as serial numbers
• for use as security keys in order to increase the security of code in Flash memory while
using and combining this unique ID with software cryptographic primitives and
protocols before programming the internal Flash memory
• to activate secure boot processes, etc.
The 96-bit unique device identifier provides a reference number which is unique for any
device and in any context. These bits can never be altered by the user.
The 96-bit unique device identifier can also be read in single bytes/half-words/words in
different ways and then be concatenated using a custom algorithm.

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Base address: 0x1FF8 0050

Address offset: 0x00
Read only = 0xXXXX XXXX where X is factory-programmed

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
U_ID(31:16)
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U_ID(15:0)
r r r r r r r r r r r r r r r r

Bits 31:0 U_ID(31:24): WAF_NUM[7:0]

Wafer number (8-bit unsigned number)
U_ID(23:0): LOT_NUM[55:32]
Lot number (ASCII code)

Address offset: 0x04

Read only = 0xXXXX XXXX where X is factory-programmed

63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
U_ID(63:48)
r r r r r r r r r r r r r r r r
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
U_ID(47:32)
r r r r r r r r r r r r r r r r

Bits 63:32 U_ID(63:32): LOT_NUM[31:0]

Lot number (ASCII code)

Address offset: 0x14

Read only = 0xXXXX XXXX where X is factory-programmed

95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
U_ID(95:80)
r r r r r r r r r r r r r r r r
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
U_ID(79:64)
r r r r r r r r r r r r r r r r

Bits 95:64 U_ID(95:64): 95:64 unique ID bits

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Appendix A Code examples

A.1 Introduction
This appendix shows the code examples of the sequence described in this Reference
Manual.
These code examples are extracted from the STM32L0xx Snippet firmware package
STM32SnippetsL0 available on www.st.com.
These code examples used the peripheral bit and register description from the CMSIS
header file (stm32l0xx.h).
Code lines starting with // should be uncommented if the given register has been modified
before.

A.2 NVM/RCC Operation code example

A.2.1 Increasing the CPU frequency preparation sequence code

/* (1) Set one wait state in Latency bit of FLASH_ACR */
/* (2) Check the latency is set */
/* (3) Switch the clock on HSI16/4 and disable PLL */
/* (4) Set PLLMUL to 16 to get 32MHz on CPU clock */
/* (5) Enable and switch on PLL */
FLASH->ACR |= FLASH_ACR_LATENCY; /* (1) */
while ((FLASH->ACR & FLASH_ACR_LATENCY) == 0); /* (2) */
SwitchFromPLLtoHSI(); /* (3) */
RCC->CFGR = (RCC->CFGR & (~(uint32_t)RCC_CFGR_PLLMUL))
| RCC_CFGR_PLLMUL16; /* (4) */
SwitchOnPLL(); /* (5) */

A.2.2 Decreasing the CPU frequency preparation sequence code

/* (1) Switch the clock on HSI16/4 and disable PLL */
/* (2) Set PLLMUL to 4 to get 8MHz on CPU clock */
/* (3) Enable and switch on PLL */
/* (4) Set one wait state in Latency bit of FLASH_ACR */
/* (5) Check the latency is set */
SwitchFromPLLtoHSI(); /* (1) */
RCC->CFGR = (RCC->CFGR & (~(uint32_t)RCC_CFGR_PLLMUL))
| RCC_CFGR_PLLMUL4; /* (2) */
SwitchOnPLL(); /* (3) */
FLASH->ACR &= ~FLASH_ACR_LATENCY; /* (4) */
while ((FLASH->ACR & FLASH_ACR_LATENCY) != 0); /* (5) */

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A.2.3 Switch from PLL to HSI16 sequence code

uint32_t tickstart;
/* (1) Switch the clock on HSI16/4 */
/* (2) Wait for clock switched on HSI16/4 */
/* (3) Disable the PLL by resetting PLLON */
/* (4) Wait until PLLRDY is cleared */
RCC->CFGR = (RCC->CFGR & (~RCC_CFGR_SW)) | RCC_CFGR_SW_HSI; /* (1) */
tickstart = Tick;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) /* (2) */
{
if ((Tick - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
/* Manage error */
return;
}
}
RCC->CR &= ~RCC_CR_PLLON; /* (3) */
tickstart = Tick;
while ((RCC->CR & RCC_CR_PLLRDY) != 0) /* (4) */
{
if ((Tick - tickstart ) > PLL_TIMEOUT_VALUE)
{
/* Manage error */
}
}
Note: Tick is a global variable incremented in the SysTick ISR each millisecond.

A.2.4 Switch to PLL sequence code

uint32_t tickstart;
/* (1) Switch on the PLL */
/* (2) Wait for PLL ready */
/* (3) Switch the clock to the PLL */
/* (4) Wait until the clock is switched to the PLL */
RCC->CR |= RCC_CR_PLLON; /* (1) */
tickstart = Tick;
while ((RCC->CR & RCC_CR_PLLRDY) == 0) /* (2) */
{
if ((Tick - tickstart ) > PLL_TIMEOUT_VALUE)
{
error = ERROR_PLL_TIMEOUT; /* Report an error */
return;
}
}
RCC->CFGR = (RCC->CFGR & (~RCC_CFGR_SW)) | RCC_CFGR_SW_PLL; /* (3) */

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tickstart = Tick;
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) /* (4) */
{
if ((Tick - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
error = ERROR_CLKSWITCH_TIMEOUT; /* Report an error */
return;
}
}
Note: Tick is a global variable incremented in the SysTick ISR each millisecond.

A.3 NVM Operation code example

A.3.1 Unlocking the data EEPROM and FLASH_PECR register

code example
/* (1) Wait till no operation is on going */
/* (2) Check if the PELOCK is unlocked */
/* (3) Perform unlock sequence */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (1) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->PECR & FLASH_PECR_PELOCK) != 0) /* (2) */
{
FLASH->PEKEYR = FLASH_PEKEY1; /* (3) */
FLASH->PEKEYR = FLASH_PEKEY2;
}

A.3.2 Locking data EEPROM and FLASH_PECR register code example

/* (1) Wait till no operation is on going */
/* (2) Locks the NVM by setting PELOCK in PECR */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (1) */
{
/* For robust implementation, add here time-out management */
}
FLASH->PECR |= FLASH_PECR_PELOCK; /* (2) */

A.3.3 Unlocking the NVM program memory code example

/* (1) Wait till no operation is on going */
/* (2) Check that the PELOCK is unlocked */
/* (3) Check if the PRGLOCK is unlocked */
/* (4) Perform unlock sequence */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (1) */

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{
/* For robust implementation, add here time-out management */
}
if ((FLASH->PECR & FLASH_PECR_PELOCK) == 0) /* (2) */
{
if ((FLASH->PECR & FLASH_PECR_PRGLOCK) != 0) /* (3) */
{
FLASH->PRGKEYR = FLASH_PRGKEY1; /* (4) */
FLASH->PRGKEYR = FLASH_PRGKEY2;
}
}

A.3.4 Unlocking the option bytes area code example

/* (1) Wait till no operation is on going */
/* (2) Check that the PELOCK is unlocked */
/* (3) Check if the OPTLOCK is unlocked */
/* (4) Perform unlock sequence */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (1) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->PECR & FLASH_PECR_PELOCK) == 0) /* (2) */
{
if ((FLASH->PECR & FLASH_PECR_OPTLOCK) != 0) /* (2) */
{
FLASH->OPTKEYR = FLASH_OPTKEY1; /* (3) */
FLASH->OPTKEYR = FLASH_OPTKEY2;
}
}

A.3.5 Write to data EEPROM code example

*(uint8_t *)(DATA_E2_ADDR+i) = DATA_BYTE;
*(uint16_t *)(DATA_E2_ADDR+j) = DATA_16B_WORD;
*(uint32_t *)(DATA_E2_ADDR) = DATA_32B_WORD;
DATA_E2_ADDR is an aligned address in the data EEPROM area.
i can be any integer.
j must be an even integer.

A.3.6 Erase to data EEPROM code example

/* (1) Set the ERASE and DATA bits in the FLASH_PECR register
to enable page erasing */
/* (2) Write a 32-bit word value at the desired address
to start the erase sequence */

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/* (3) Enter in wait for interrupt. The EOP check is done in the Flash ISR
*/
/* (6) Reset the ERASE and DATA bits in the FLASH_PECR register
to disable the page erase */
FLASH->PECR |= FLASH_PECR_ERASE | FLASH_PECR_DATA; /* (1) */
*(__IO uint32_t *)addr = (uint32_t)0; /* (2) */
__WFI(); /* (3) */
FLASH->PECR &= ~(FLASH_PECR_ERASE | FLASH_PECR_DATA); /* (4) */

A.3.7 Program Option byte code example

/**
* This function programs a 16-bit option byte and its complement word.
* Param None
* Retval None
*/
__INLINE __RAM_FUNC void OptionByteProg(uint8_t index, uint16_t data)
{
/* (1) Write a 32-bit word value at the option byte address,
the 16-bit data is extended with its compemented value */
/* (3) Wait until the BSY bit is reset in the FLASH_SR register */
/* (4) Check the EOP flag in the FLASH_SR register */
/* (5) Clear EOP flag by software by writing EOP at 1 */
*(__IO uint32_t *)(OB_BASE + index) = (uint32_t)((~data << 16) | data);
/* (1) */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (2) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (3) */
{
FLASH->SR = FLASH_SR_EOP; /* (4) */
}
else
{
/* Manage the error cases */
}
}
Note: This function must be loaded in RAM.

A.3.8 Erase Option byte code example

/**
* This function erases a 16-bit option byte and its complement
word.
* Param None

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* Retval None
*/
__INLINE __RAM_FUNC void OptionByteErase(uint8_t index)
{
/* (1) Set the ERASE bit in the FLASH_PECR register
to enable option byte erasing */
/* (2) Write a 32-bit word value at the option byte address to be erased
to start the erase sequence */
/* (3) Wait until the BSY bit is reset in the FLASH_SR register */
/* (4) Check the EOP flag in the FLASH_SR register */
/* (5) Clear EOP flag by software by writing EOP at 1 */
/* (6) Reset the ERASE and PROG bits in the FLASH_PECR register
to disable the page erase */
FLASH->PECR |= FLASH_PECR_ERASE; /* (1) */
*(__IO uint32_t *)(OB_BASE + index) = 0; /* (2) */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (3) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (4) */
{
FLASH->SR |= FLASH_SR_EOP; /* (5) */
}
else
{
/* Manage the error cases */
}
FLASH->PECR &= ~(FLASH_PECR_ERASE); /* (6) */
}
Note: This function must be loaded in RAM.

A.3.9 Program a single word to Flash program memory code example

/* (1) Perform the data write (32-bit word) at the desired address */
/* (2) Wait until the BSY bit is reset in the FLASH_SR register */
/* (3) Check the EOP flag in the FLASH_SR register */
/* (4) clear it by software by writing it at 1 */
*(__IO uint32_t*)(flash_addr) = data; /* (1) */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (2) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (3) */
{
FLASH->SR = FLASH_SR_EOP; /* (4) */

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}
else
{
/* Manage the error cases */
}

A.3.10 Program half-page to Flash program memory code example

/**
* This function programs a half page. It is executed from the RAM.
* The Programming bit (PROG) and half-page programming bit (FPRG)
* is set at the beginning and reset at the end of the function,
* in case of successive programming, these two operations
* could be performed outside the function.
* This function waits the end of programming, clears the appropriate
* bit in the Status register and eventually reports an error.
* Param flash_addr is the first address of the half-page to be programmed
* data is the 32-bit word array to program
* Retval None
*/
__RAM_FUNC void FlashHalfPageProg(uint32_t flash_addr, uint32_t *data)
{
uint8_t i;
/* (1) Set the PROG and FPRG bits in the FLASH_PECR register
to enable a half page programming */
/* (2) Perform the data write (half-word) at the desired address */
/* (3) Wait until the BSY bit is reset in the FLASH_SR register */
/* (4) Check the EOP flag in the FLASH_SR register */
/* (5) clear it by software by writing it at 1 */
/* (6) Reset the PROG and FPRG bits to disable programming */
FLASH->PECR |= FLASH_PECR_PROG | FLASH_PECR_FPRG; /* (1) */
for (i = 0; i < ((FLASH_PAGE_SIZE/2) / 4); i++)
{
*(__IO uint32_t*)(flash_addr) = *data++; /* (2) */
}
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (3) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (4) */
{
FLASH->SR = FLASH_SR_EOP; /* (5) */
}
else
{

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/* Manage the error cases */

}
FLASH->PECR &= ~(FLASH_PECR_PROG | FLASH_PECR_FPRG); /* (6) */
}
Note: This function must be loaded in RAM.

A.3.11 Erase a page in Flash program memory code example

/**
* This function erases a page of flash.
* The Page Erase bit (PER) is set at the beginning and reset
* at the end of the function, in case of successive erase,
* these two operations could be performed outside the function.
* Param page_addr is an address inside the page to erase
* Retval None
*/
__INLINE void FlashErase(uint32_t page_addr)
{
/* (1) Set the ERASE and PROG bits in the FLASH_PECR register
to enable page erasing */
/* (2) Write a 32-bit word value in an address of the selected page
to start the erase sequence */
/* (3) Wait until the BSY bit is reset in the FLASH_SR register */
/* (4) Check the EOP flag in the FLASH_SR register */
/* (5) Clear EOP flag by software by writing EOP at 1 */
/* (6) Reset the ERASE and PROG bits in the FLASH_PECR register
to disable the page erase */
FLASH->PECR |= FLASH_PECR_ERASE | FLASH_PECR_PROG; /* (1) */
*(__IO uint32_t *)page_addr = (uint32_t)0; /* (2) */
while ((FLASH->SR & FLASH_SR_BSY) != 0) /* (3) */
{
/* For robust implementation, add here time-out management */
}
if ((FLASH->SR & FLASH_SR_EOP) != 0) /* (4) */
{
FLASH->SR = FLASH_SR_EOP; /* (5) */
}
else
{
/* Manage the error cases */
}
FLASH->PECR &= ~(FLASH_PECR_ERASE | FLASH_PECR_PROG); /* (6) */
}

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A.3.12 Mass erase code example

/**
* This function performs a mass erase of the flash.
* This function is loaded in RAM.
* Param None
* Retval while successful, the function never returns except if executed
from RAM
*/
__RAM_FUNC void FlashMassErase(void)
{
/* (1) Check if the read protection is not level 2 */
/* (2) Check if the read protection is not level 1 */
/* (3) Erase the Option byte containing the read protection */
/* (4) Reload the Option bytes */
/* (5) Program read protection to level 1 by writing 0xAA
to start the mass erase */
/* (6) Lock the NVM by setting the PELOCK bit */
if ((FLASH->OPTR & 0x000000FF) == 0xCC) /* (1) */
{
/* Report the error and abort*/
return;
}
else if ((FLASH->OPTR & 0x000000FF) == 0xAA) /* (2) */
{
OptionByteErase(FLASH_OPTR0); /* (3) */
FLASH->PECR |= FLASH_PECR_OBL_LAUNCH; /* (4) */
/* The MCU will reset while executing the option bytes reloading */
}
OptionByteProg(FLASH_OPTR0, 0x00AA); /* (5) */
if (*(uint32_t *)(FLASH_MAIN_ADDR ) != (uint32_t)0) /* Check the erasing
of the page by reading all the page value */
{
/* Report the error */
}
LockNVM(); /* (6) */
while (1) /* Infinite loop */
{
}
}
Note: This function uses two other ones in A.3.7: Program Option byte code example and A.3.8:
Erase Option byte code example.

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A.4 Clock Controller

A.4.1 HSE start sequence code example

/**
* This function enables the interrupton HSE ready,
* and start the HSE as external clock.
* Param None
* Retval None
*/
__INLINE void StartHSE(void)
{
/* Configure NVIC for RCC */
/* (1) Enable Interrupt on RCC */
/* (2) Set priority for RCC */
NVIC_EnableIRQ(RCC_CRS_IRQn); /* (1) */
NVIC_SetPriority(RCC_CRS_IRQn,0); /* (2) */

/* (1) Enable interrupt on HSE ready */

/* (2) Enable the CSS
Enable the HSE and set HSEBYP to use the external clock
instead of an oscillator
Enable HSE */
/* Note : the clock is switched to HSE in the RCC_CRS_IRQHandler ISR */
RCC->CIER |= RCC_CIER_HSERDYIE; /* (1) */
RCC->CR |= RCC_CR_CSSHSEON | RCC_CR_HSEBYP | RCC_CR_HSEON; /* (2) */
}

/**
* This function handles RCC interrupt request
* and switch the system clock to HSE.
* Param None
* Retval None
*/
void RCC_CRS_IRQHandler(void)
{
/* (1) Check the flag HSE ready */
/* (2) Clear the flag HSE ready */
/* (3) Switch the system clock to HSE */
if ((RCC->CifR & RCC_CifR_HSERDYF) != 0) /* (1) */
{
RCC->CICR |= RCC_CICR_HSERDYC; /* (2) */
RCC->CFGR = ((RCC->CFGR & (~RCC_CFGR_SW)) | RCC_CFGR_SW_HSE); /* (3) */
}
else

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{
/* Manage error */
}
}

A.4.2 PLL configuration modification code example

/* (1) Test if PLL is used as System clock */
/* (2) Select HSI as system clock */
/* (3) Wait for HSI switched */
/* (4) Disable the PLL */
/* (5) Wait until PLLRDY is cleared */
/* (6) Set latency to 1 wait state */
/* (7) Set the PLL multiplier to 24 and divider by 3 */
/* (8) Enable the PLL */
/* (9) Wait until PLLRDY is set */
/* (10) Select PLL as system clock */
/* (11) Wait until the PLL is switched on */
if ((RCC->CFGR & RCC_CFGR_SWS) == RCC_CFGR_SWS_PLL) /* (1) */
{
RCC->CFGR = (RCC->CFGR & (uint32_t) (~RCC_CFGR_SW))
| RCC_CFGR_SW_HSI; /* (2) */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) /* (3) */
{
/* For robust implementation, add here time-out management */
}
}
RCC->CR &= (uint32_t)(~RCC_CR_PLLON);/* (4) */
while((RCC->CR & RCC_CR_PLLRDY) != 0) /* (5) */
{
/* For robust implementation, add here time-out management */
}
FLASH->ACR |= FLASH_ACR_LATENCY; /* (6) */
RCC->CFGR = RCC->CFGR & (~(RCC_CFGR_PLLMUL| RCC_CFGR_PLLDIV ))
| (RCC_CFGR_PLLMUL24 | RCC_CFGR_PLLDIV2); /* (7) */
RCC->CR |= RCC_CR_PLLON; /* (8) */
while ((RCC->CR & RCC_CR_PLLRDY) == 0) /* (9) */
{
/* For robust implementation, add here time-out management */
}
RCC->CFGR |= (uint32_t) (RCC_CFGR_SW_PLL); /* (10) */
while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) /* (11) */
{
/* For robust implementation, add here time-out management */
}

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A.4.3 MCO selection code example

/* (1) Clear the MCO selection bits */
/* (2)Select system clock/4 to be output on the MCO without prescaler */
RCC->CFGR &= (uint32_t) RCC_CFGR_MCOSEL; /* (1) */
RCC->CFGR |= RCC_CFGR_MCO_SYSCLK | RCC_CFGR_MCO_PRE_4; /* (2) */

A.5 GPIOs

A.5.1 Locking mechanism code example

/* (1) Write LCKK bit to 1 and set the pin bits to lock */
/* (2) Write LCKK bit to 0 and set the pin bits to lock */
/* (3) Write LCKK bit to 1 and set the pin bits to lock */
/* (4) Read the Lock register */
/* (5) Check the Lock register (optionnal) */
GPIOA->LCKR = GPIO_LCKR_LCKK + lock; /* (1) */
GPIOA->LCKR = lock; /* (2) */
GPIOA->LCKR = GPIO_LCKR_LCKK + lock; /* (3) */
GPIOA->LCKR; /* (4) */
if ((GPIOA->LCKR & GPIO_LCKR_LCKK) == 0) /* (5) */
{
/* Manage error */
}

A.5.2 Alternate function selection sequence code example

/* (1) Enable the peripheral clock of Timer 2 */
/* (2) Enable the peripheral clock of GPIOA */
/* (3) Select Alternate function mode (10) on GPIOA pin 0 */
/* (4) Select TIM2_CH1 on PA0 by enabling AF2 for pin 0 in GPIOA AFRL
register */
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; /* (1) */
RCC->IOPENR |= RCC_IOPENR_GPIOAEN; /* (2) */
GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODE0)) \
| (GPIO_MODER_MODE0_1); /* (3) */
GPIOA->AFR[0] |= 0x2; /* (4) */

A.5.3 Analog GPIO configuration code example

/* (1) Enable the peripheral clock of GPIOA */
/* (2) Select Input Float (00- default) on GPIOA pin 0 */
RCC->IOPENR |= RCC_IOPENR_GPIOAEN; /* (1) */
GPIOA->MODER &= ~(GPIO_MODER_MODE0); /* (2) */

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A.6 DMA

A.6.1 DMA Channel Configuration sequence code example

/* (1) Enable the peripheral clock on DMA */
/* (2) Remap DMA channel1 on ADC (reset value) */
/* (3) Enable DMA transfer on ADC */
/* (4) Configure the peripheral data register address */
/* (5) Configure the memory address */
/* (6) Configure the number of DMA tranfer to be performs on channel 1 */
/* (7) Configure increment, size and interrupts */
/* (8) Enable DMA Channel 1 */
RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
//DMA1_CSELR->CSELR &= (uint32_t)(~DMA_CSELR_C1S); /* (2) */
ADC1->CFGR1 |= ADC_CFGR1_DMAEN; /* (3) */
DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR)); /* (4) */
DMA1_Channel1->CMAR = (uint32_t)(ADC_array); /* (5) */
DMA1_Channel1->CNDTR = 3; /* (6) */
DMA1_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 \
| DMA_CCR_TEIE | DMA_CCR_TCIE ; /* (7) */
DMA1_Channel1->CCR |= DMA_CCR_EN; /* (8) */

/* Configure NVIC for DMA */

/* (1) Enable Interrupt on DMA Channel 1 */
/* (2) Set priority for DMA Channel 1 */
NVIC_EnableIRQ(DMA1_Channel1_IRQn); /* (1) */
NVIC_SetPriority(DMA1_Channel1_IRQn,0); /* (2) */

A.7 Interrupts and event

A.7.1 NVIC initialization example

/* Configure NVIC for ADC */
/* (1) Enable Interrupt on ADC */
/* (2) Set priority for ADC */
NVIC_EnableIRQ(ADC1_COMP_IRQn); /* (1) */
NVIC_SetPriority(ADC1_COMP_IRQn,0); /* (2) */

A.7.2 Extended interrupt selection code example

/* (1) Enable the peripheral clock of GPIOA */
/* (2) Select input mode (00) on GPIOA pin 0 */
/* (3) Select Port A for pin 0 extended interrupt by writing 0000
in EXTI0 (reset value) */
/* (4) Configure the corresponding mask bit in the EXTI_IMR register */

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/* (5) Configure the Trigger Selection bits of the Interrupt line

on rising edge */
/* (6) Configure the Trigger Selection bits of the Interrupt line
on falling edge */
RCC->IOPENR |= RCC_IOPENR_GPIOAEN; /* (1) */
GPIOA->MODER = (GPIOA->MODER & ~(GPIO_MODER_MODE0)); /* (2) */
//SYSCFG->EXTICR[0] &= (uint16_t)~SYSCFG_EXTICR1_EXTI0_PA; /* (3) */
EXTI->IMR |= 0x0001; /* (4) */
EXTI->RTSR |= 0x0001; /* (5) */
//EXTI->FTSR |= 0x0001; /* (6) */

/* Configure NVIC for Extended Interrupt */

/* (7) Enable Interrupt on EXTI0_1 */
/* (8) Set priority for EXTI0_1 */
NVIC_EnableIRQ(EXTI0_1_IRQn); /* (7) */
NVIC_SetPriority(EXTI0_1_IRQn,0); /* (8) */

A.8 ADC

A.8.1 Calibration code example

/* (1) Ensure that ADEN = 0 */
/* (2) Clear ADEN */
/* (3) Set ADCAL=1 */
/* (4) Wait until EOCAL=1 */
/* (5) Clear EOCAL */
if ((ADC1->CR & ADC_CR_ADEN) != 0) /* (1) */
{
ADC1->CR |= ADC_CR_ADDIS; /* (2) */
}
ADC1->CR |= ADC_CR_ADCAL; /* (3) */
while ((ADC1->ISR & ADC_ISR_EOCAL) == 0) /* (4) */
{
/* For robust implementation, add here time-out management */
}
ADC1->ISR |= ADC_ISR_EOCAL; /* (5) */

A.8.2 ADC enable sequence code example

/* (1) Clear the ADRDY bit */
/* (2) Enable the ADC */
/* (3) Wait until ADC ready */
ADC1->ISR |= ADC_ISR_ADRDY; /* (1) */
ADC1->CR |= ADC_CR_ADEN; /* (2) */
if ((ADC1->CFGR1 & ADC_CFGR1_AUTOFF) == 0)

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{
while ((ADC1->ISR & ADC_ISR_ADRDY) == 0) /* (3) */
{
/* For robust implementation, add here time-out management */
}
}

A.8.3 ADC disable sequence code example

/* (1) Ensure that no conversion on going */
/* (2) Stop any ongoing conversion */
/* (3) Wait until ADSTP is reset by hardware i.e. conversion is stopped */
/* (4) Disable the ADC */
/* (5) Wait until the ADC is fully disabled */
if ((ADC1->CR & ADC_CR_ADSTART) != 0) /* (1) */
{
ADC1->CR |= ADC_CR_ADSTP; /* (2) */
}
while ((ADC1->CR & ADC_CR_ADSTP) != 0) /* (3) */
{
/* For robust implementation, add here time-out management */
}
ADC1->CR |= ADC_CR_ADDIS; /* (4) */
while ((ADC1->CR & ADC_CR_ADEN) != 0) /* (5) */
{
/* For robust implementation, add here time-out management */
}

A.8.4 ADC clock selection code example

/* (1) Select PCLK by writing 11 in CKMODE */
ADC1->CFGR2 |= ADC_CFGR2_CKMODE; /* (1) */

A.8.5 Single conversion sequence code example - Software trigger

/* (1) Select HSI16 by writing 00 in CKMODE (reset value) */
/* (2) Select the auto off mode */
/* (3) Select CHSEL17 for VRefInt */
/* (4) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater than
17.1us */
/* (5) Wake-up the VREFINT (only for Temp sensor and VRefInt) */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_AUTOFF; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL17; /* (3) */
ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (4) */
ADC->CCR |= ADC_CCR_VREFEN; /* (5) */
…

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/* Performs the AD conversion */

ADC1->CR |= ADC_CR_ADSTART; /* start the ADC conversion */
while ((ADC1->ISR & ADC_ISR_EOC) == 0) /* wait end of conversion */
{
/* For robust implementation, add here time-out management */
}

A.8.6 Continuous conversion sequence code example - Software trigger

/* (1) Select HSI16 by writing 00 in CKMODE (reset value) */
/* (2) Select the continuous mode and scanning direction */
/* (3) Select CHSEL4, CHSEL9 and CHSEL17 */
/* (4) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater
than 5 us */
/* (5) Enable interrupts on EOC, EOSEQ and overrrun */
/* (6) Wake-up the VREFINT (only for Temp sensor and VRefInt) */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_WAIT |ADC_CFGR1_CONT | ADC_CFGR1_SCANDIR;/* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL4 | ADC_CHSELR_CHSEL9 \
| ADC_CHSELR_CHSEL17; /* (3) */
ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (4) */
ADC1->IER = ADC_IER_EOCIE | ADC_IER_EOSEQIE | ADC_IER_OVRIE; /* (5) */
ADC->CCR |= ADC_CCR_VREFEN; /* (6) */

/* Configure NVIC for ADC */

/* (1) Enable Interrupt on ADC */
/* (2) Set priority for ADC */
NVIC_EnableIRQ(ADC1_COMP_IRQn); /* (1) */
NVIC_SetPriority(ADC1_COMP_IRQn,0); /* (2) */

A.8.7 Single conversion sequence code example - Hardware trigger

/* (1) Select HSI16 by writing 00 in CKMODE (reset value) */
/* (2) Select the external trigger on falling edge and external trigger on
TIM22_TRGO by selecting TRG4 (EXTSEL = 100) */
/* (3) Select CHSEL17 for VRefInt */
/* (4) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater
than 5us */
/* (5) Wake-up the VREFINT (only for Temp sensor and VRefInt) */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_EXTEN_0 | ADC_CFGR1_EXTSEL_2 ; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL17; /* (3) */
ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (4) */
ADC->CCR |= ADC_CCR_VREFEN; /* (5) */
Note: Then TIM22 must be configured to generate an external trigger on TRG0 periodically.

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A.8.8 Continuous conversion sequence code example - Hardware trigger

/* (1) Select HSI16 by writing 00 in CKMODE (reset value) */
/* (2) Select the external trigger on TIM22_TRGO (TRG4 i.e. EXTSEL = 100
and rising edge, the continuous mode and scanning direction */
/* (3) Select CHSEL4, CHSEL9 and CHSEL17 */
/* (4) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater
than 5us */
/* (5) Enable interrupts on EOC, EOSEQ and overrrun */
/* (6) Wake-up the VREFINT (only for Temp sensor and VRefInt) */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_EXTEN_0 | ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_CONT \
| ADC_CFGR1_SCANDIR; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL4 | ADC_CHSELR_CHSEL9 \
| ADC_CHSELR_CHSEL17; /* (3 */
ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (4) */
ADC1->IER = ADC_IER_EOCIE | ADC_IER_EOSEQIE | ADC_IER_OVRIE; /* (5) */
ADC->CCR |= ADC_CCR_VREFEN; /* (6) */
/* Configure NVIC for ADC */
/* (1) Enable Interrupt on ADC */
/* (2) Set priority for ADC */
NVIC_EnableIRQ(ADC1_COMP_IRQn); /* (1) */
NVIC_SetPriority(ADC1_COMP_IRQn,0); /* (2) */

A.8.9 DMA one shot mode sequence code example

/* (1) Enable the peripheral clock on DMA */
/* (2) Enable DMA transfer on ADC - DMACFG is kept at 0 for one shot mode */
/* (3) Configure the peripheral data register address */
/* (4) Configure the memory address */
/* (5) Configure the number of DMA transfer to be performs
on DMA channel 1 */
/* (6) Configure increment, size and interrupts */
/* (7) Enable DMA Channel 1 */
RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_DMAEN; /* (2) */
DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR)); /* (3) */
DMA1_Channel1->CMAR = (uint32_t)(ADC_array); /* (4) */
DMA1_Channel1->CNDTR = NUMBER_OF_ADC_CHANNEL; /* (5) */
DMA1_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 \
| DMA_CCR_TEIE | DMA_CCR_TCIE ; /* (6) */
DMA1_Channel1->CCR |= DMA_CCR_EN; /* (7) */

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A.8.10 DMA circular mode sequence code example

/* (1) Enable the peripheral clock on DMA */
/* (2) Enable DMA transfer on ADC and circular mode */
/* (3) Configure the peripheral data register address */
/* (4) Configure the memory address */
/* (5) Configure the number of DMA tranfer to be performs
on DMA channel 1 */
/* (6) Configure increment, size, interrupts and circular mode */
/* (7) Enable DMA Channel 1 */
RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG; /* (2) */
DMA1_Channel1->CPAR = (uint32_t) (&(ADC1->DR)); /* (3) */
DMA1_Channel1->CMAR = (uint32_t)(ADC_array); /* (4) */
DMA1_Channel1->CNDTR = NUMBER_OF_ADC_CHANNEL; /* (5) */
DMA1_Channel1->CCR |= DMA_CCR_MINC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 \
| DMA_CCR_TEIE | DMA_CCR_CIRC; /* (6) */
DMA1_Channel1->CCR |= DMA_CCR_EN; /* (7) */

A.8.11 Wait mode sequence code example

/* (1) Select PCLK by writing 11 in CKMODE */
/* (2) Select the continuous mode and the wait mode */
/* (3) Select CHSEL4, CHSEL9 and CHSEL17 */
/* (4) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater
than 17.1us */
/* (5) Enable interrupts on overrrun */
/* (6) Wake-up the VREFINT (only for Temp sensor and VRefInt) */
ADC1->CFGR2 |= ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_CONT | ADC_CFGR1_WAIT; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL4 | ADC_CHSELR_CHSEL9 \
| ADC_CHSELR_CHSEL17; /* (3 */
ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (4) */
ADC1->IER = ADC_IER_OVRIE; /* (5) */
ADC->CCR |= ADC_CCR_VREFEN; /* (6) */

A.8.12 Auto off and no wait mode sequence code example

/* (1) Select HSI16 by writing 00 in CKMODE (reset value) */
/* (2) Select the external trigger on TIM22_TRGO and falling edge,
the continuous mode, scanning direction and auto off */
/* (3) Select CHSEL4, CHSEL9 and CHSEL17 */
/* (4) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater
than 5us */
/* (5) Enable interrupts on EOC, EOSEQ and overrrun */
/* (6) Wake-up the VREFINT (only for Temp sensor and VRefInt) */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */

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ADC1->CFGR1 |= ADC_CFGR1_EXTEN_0 | ADC_CFGR1_EXTSEL_2 \

| ADC_CFGR1_SCANDIR | ADC_CFGR1_AUTOFF; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL4 | ADC_CHSELR_CHSEL9 \
| ADC_CHSELR_CHSEL17; /* (3) */
ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (4) */
ADC1->IER = ADC_IER_EOCIE | ADC_IER_EOSEQIE | ADC_IER_OVRIE; /* (5) */
ADC->CCR |= ADC_CCR_VREFEN; /* (6) */

A.8.13 Auto off and wait mode sequence code example

/* (1) Select HSI16 by writing 00 in CKMODE (reset value) */
/* (2) Select the continuous mode, the wait mode and the Auto off */
/* (3) Select CHSEL4, CHSEL9 and CHSEL17 */
/* (4) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater
than 5us */
/* (5) Enable interrupt on overrrun */
/* (6) Wake-up the VREFINT (only for Temp sensor and VRefInt) */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_CONT | ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF;/* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL4 | ADC_CHSELR_CHSEL9 \
| ADC_CHSELR_CHSEL17; /* (3) */
ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (4) */
ADC1->IER = ADC_IER_OVRIE; /* (5) */
ADC->CCR |= ADC_CCR_VREFEN; /* (6) */

A.8.14 Analog watchdog code example

/* Define the upper limit 15% above the factory value
the value is adapted according to the application power supply
versus the factory calibration power supply */
uint16_t vrefint_high = (*VREFINT_CAL_ADDR)* VDD_CALIB / VDD_APPLI * 115 /
100;

/* Define the lower limit 15% below the factory value

the value is adapted according to the application power supply
versus the factory calibration power supply */
uint16_t vrefint_low = (*VREFINT_CAL_ADDR) * VDD_CALIB / VDD_APPLI * 85 /
100;

/* (1) Select HSI16 by writing 00 in CKMODE (reset value) */

/* (2) Select the continuous mode
and configure the Analog watchdog to monitor only CH17 */
/* (3) Define analog watchdog range : 16b-MSW is the high limit
and 16b-LSW is the low limit */
/* (4) Select CHSEL4, CHSEL9 and CHSEL17 */
/* (5) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater
than 5us */

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/* (6) Enable interrupts on EOC, EOSEQ and Analog Watchdog */

/* (7) Wake-up the VREFINT (only for VBAT, Temp sensor and VRefInt) */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_CONT \
| (17<<26) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL; /* (2) */
ADC1->TR = (vrefint_high << 16) + vrefint_low; /* (3 */
ADC1->CHSELR = ADC_CHSELR_CHSEL4 | ADC_CHSELR_CHSEL9
| ADC_CHSELR_CHSEL17; /* (4) */
ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* (5) */
ADC1->IER = ADC_IER_EOCIE | ADC_IER_EOSEQIE | ADC_IER_AWDIE; /* (6) */
ADC->CCR |= ADC_CCR_VREFEN; /* (7) */

A.8.15 Oversampling code example

/* (1) Select HSI16 by writing 00 in CKMODE (reset value)
Enable oversampling with ratio 16 and shifted by 1,
without trigger */
ADC1->CFGR2 = (ADC1->CFGR2 & (~ADC_CFGR2_CKMODE))
| (ADC_CFGR2_OVSE | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0
| ADC_CFGR2_OVSS_0); /* (1) */

A.8.16 Temperature configuration code example

/* (1) Select HSI16 by writing 00 in CKMODE (reset value) */
/* (2) Select continuous mode */
/* (3) Select CHSEL18 for temperature sensor */
/* (4) Select a sampling mode of 111 i.e. 239.5 ADC clk to be greater
than 2.2us */
/* (5) Wake-up the Temperature sensor (only for Temp sensor and
VRefInt) */
//ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* (1) */
ADC1->CFGR1 |= ADC_CFGR1_CONT; /* (2) */
ADC1->CHSELR = ADC_CHSELR_CHSEL18; /* (3) */
ADC1->SMPR |= ADC_SMPR_SMP; /* (4) */
ADC->CCR |= ADC_CCR_TSEN; /* (5) */

A.8.17 Temperature computation code example

/* Temperature sensor calibration value address */
#define TEMP130_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FF8007E))
#define TEMP30_CAL_ADDR ((uint16_t*) ((uint32_t) 0x1FF8007A))
#define VDD_CALIB ((uint16_t) (300))
#define VDD_APPLI ((uint16_t) (330))
int32_t ComputeTemperature(uint32_t measure)
{
int32_t temperature;
temperature = ((measure * VDD_APPLI / VDD_CALIB)

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- (int32_t) *TEMP30_CAL_ADDR );
temperature = temperature * (int32_t)(130 - 30);
temperature = temperature / (int32_t)(*TEMP130_CAL_ADDR -
*TEMP30_CAL_ADDR);
temperature = temperature + 30;
return(temperature);
}

A.9 Timers

A.9.1 Upcounter on TI2 rising edge code example

/* (1) Configure channel 1 to detect rising edges on the TI1 input
by writing CC1S = ‘01’, and configure the input filter
duration by writing the IC1F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).*/
/* (2) Select rising edge polarity by writing CC1P=0 in the TIMx_CCER
register
Not necessary as it keeps the reset value. */
/* (3) Configure the timer in external clock mode 1 by writing SMS=111
Select TI1 as the trigger input source by writing TS=101
in the TIMx_SMCR register. */
/* (4) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
TIMx->CCMR1 |= TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_1
| TIM_CCMR1_CC1S_0; /* (1 */
//TIMx->CCER &= (uint16_t)(~TIM_CCER_CC1P); /* (2) */
TIMx->SMCR |= TIM_SMCR_SMS | TIM_SMCR_TS_2 | TIM_SMCR_TS_0; /* (3) */
TIMx->CR1 |= TIM_CR1_CEN; /* (4) */

A.9.2 Up counter on each 2 ETR rising edges code example

/* (1) As no filter is needed in this example, write ETF[3:0]=0000
in the TIMx_SMCR register. Keep the reset value.
Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR
register.
Select rising edge detection on the ETR pin by writing ETP=0
in the TIMx_SMCR register. Keep the reset value.
Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR
register. */
/* (2) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
TIMx->SMCR |= TIM_SMCR_ETPS_0 | TIM_SMCR_ECE; /* (1) */
TIMx->CR1 |= TIM_CR1_CEN; /* (2) */

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A.9.3 Input capture configuration code example

/* (1) Select the active input TI1 (CC1S = 01),
program the input filter for 8 clock cycles (IC1F = 0011),
select the rising edge on CC1 (CC1P = 0, reset value)
and prescaler at each valid transition (IC1PS = 00, reset value) */
/* (2) Enable capture by setting CC1E */
/* (3) Enable interrupt on Capture/Compare */
/* (4) Enable counter */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0 \
| TIM_CCMR1_IC1F_0 | TIM_CCMR1_IC1F_1; /* (1 */
TIMx->CCER |= TIM_CCER_CC1E; /* (2) */
TIMx->DIER |= TIM_DIER_CC1IE; /* (3) */
TIMx->CR1 |= TIM_CR1_CEN; /* (4) */

A.9.4 Input capture data management code example

This code must be inserted in the timer interrupt subroutine.
if ((TIMx->SR & TIM_SR_CC1IF) != 0)
{
if ((TIMx->SR & TIM_SR_CC1OF) != 0) /* Check the overflow */
{
/* Overflow error management */
gap = 0; /* Reinitialize the laps computing */
TIMx->SR = ~(TIM_SR_CC1OF | TIM_SR_CC1IF); /* Clear the flags */
return;
}
if (gap == 0) /* Test if it is the first rising edge */
{
counter0 = TIMx->CCR1; /* Read the capture counter which clears the
CC1ICF */
gap = 1; /* Indicate that the first rising edge has yet been detected */
}
else
{
counter1 = TIMx->CCR1; /* Read the capture counter which clears the
CC1ICF */
if (counter1 > counter0) /* Check capture counter overflow */
{
Counter = counter1 - counter0;
}
else
{
Counter = counter1 + 0xFFFF - counter0 + 1;
}
counter0 = counter1;

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}
}
else
{
/* Manage error */
}

Note: This code manages only single counter overflows. To manage several counter overflows,
the update interrupt must be enabled (UIE = 1) and properly managed.

A.9.5 PWM input configuration code example

/* (1) Select the active input TI1 for TIMx_CCR1 (CC1S = 01),
select the active input TI1 for TIMx_CCR2 (CC2S = 10) */
/* (2) Select TI1FP1 as valid trigger input (TS = 101)
configure the slave mode in reset mode (SMS = 100) */
/* (3) Enable capture by setting CC1E and CC2E
select the rising edge on CC1 and CC1N (CC1P = 0 and CC1NP = 0,
reset value),
select the falling edge on CC2 (CC2P = 1). */
/* (4) Enable interrupt on Capture/Compare 1 */
/* (5) Enable counter */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_1; /* (1 */
TIMx->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_TS_0 \
| TIM_SMCR_SMS_2; /* (2) */
TIMx->CCER |= TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC2P; /* (3) */
TIMx->DIER |= TIM_DIER_CC1IE; /* (4) */
TIMx->CR1 |= TIM_CR1_CEN; /* (5) */

A.9.6 PWM input with DMA configuration code example

/* (1) Enable the peripheral clock on DMA */
/* (2) Remap DMA channel5 and 7 on TIM2_CH1 and TIM2_CH2
by writing 1000 in DMA_CSELR_C5S and DMA_CSELR_C7S */
/* (3) Configure the peripheral data register address for DMA channel x */
/* (4) Configure the memory address for DMA channel x */
/* (5) Configure the number of DMA tranfer to be performed
on DMA channel x */
/* (6) Configure no increment (reset value), size (16-bits), interrupts,
transfer from peripheral to memory and circular mode
for DMA channel x */
/* (7) Enable DMA Channel x */
RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
DMA1_CSELR->CSELR |= 8 << (4 * (5-1)) | 8 << (4 * (7-1)); /* (2) */
DMA1_Channel5->CPAR = (uint32_t) (&(TIMx->CCR1)); /* (3) */

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DMA1_Channel5->CMAR = (uint32_t)(&Period); /* (4) */

DMA1_Channel5->CNDTR = 1; /* (5) */
DMA1_Channel5->CCR |= DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 \
| DMA_CCR_TEIE | DMA_CCR_CIRC; /* (6) */
DMA1_Channel5->CCR |= DMA_CCR_EN; /* (7) */
/* repeat (3) to (6) for channel 6 */
DMA1_Channel7->CPAR = (uint32_t) (&(TIMx->CCR2)); /* (2) */
DMA1_Channel7->CMAR = (uint32_t)(&DutyCycle); /* (3) */
DMA1_Channel7->CNDTR = 1; /* (4) */
DMA1_Channel7->CCR |= DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_0 \
| DMA_CCR_TEIE | DMA_CCR_CIRC; /* (5) */
DMA1_Channel7->CCR |= DMA_CCR_EN; /* (6) */

/* Configure NVIC for DMA */

/* (1) Enable Interrupt on DMA Channels x */
/* (2) Set priority for DMA Channels x */
NVIC_EnableIRQ(DMA1_Channel4_5_6_7_IRQn); /* (1) */
NVIC_SetPriority(DMA1_Channel4_5_6_7_IRQn,3); /* (2) */

A.9.7 Output compare configuration code example

/* (1) Set prescaler to 3, so APBCLK/4 i.e 4MHz */

/* (2) Set ARR = 4000 - 1 */
/* (3) Set CCRx = ARR, as timer clock is 4MHz, an event occurs each 1 ms */
/* (4) Select toggle mode on OC1 (OC1M = 011),
disable preload register on OC1 (OC1PE = 0, reset value) */
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1 */
/* (6) Enable output (MOE = 1 */
/* (7) Enable counter */
TIMx->PSC |= 3; /* (1) */
TIMx->ARR = 4000 - 1; /* (2) */
TIMx->CCR1 = 4000 - 1; /* (3) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1; /* (4) */
TIMx->CCER |= TIM_CCER_CC1E; /* (5 */
TIMx->CR1 |= TIM_CR1_CEN; /* (6) */

A.9.8 Edge-aligned PWM configuration example

/* (1) Set prescaler to 15, so APBCLK/16 i.e 1MHz */
/* (2) Set ARR = 8, as timer clock is 1MHz the period is 9 us */
/* (3) Set CCRx = 4, , the signal will be high during 4 us */
/* (4) Select PWM mode 1 on OC1 (OC1M = 110),
enable preload register on OC1 (OC1PE = 1) */
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),

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enable the output on OC1 (CC1E = 1) */

/* (6) Enable output (MOE = 1)- optional*/
/* (7) Enable counter (CEN = 1)
select edge aligned mode (CMS = 00, reset value)
select direction as upcounter (DIR = 0, reset value) */
/* (8) Force update generation (UG = 1) */
TIMx->PSC = 15; /* (1) */
TIMx->ARR = 8; /* (2) */
TIMx->CCR1 = 4; /* (3) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1
| TIM_CCMR1_OC1PE; /* (4) */
TIMx->CCER |= TIM_CCER_CC1E; /* (5) */
TIMx->CR1 |= TIM_CR1_CEN; /* (6) */
TIMx->EGR |= TIM_EGR_UG; /* (7) */

A.9.9 Center-aligned PWM configuration example

/* (1) Set prescaler to 15, so APBCLK/16 i.e 1MHz */
/* (2) Set ARR = 8, as timer clock is 1MHz and center-aligned counting,
the period is 16 us */
/* (3) Set CCRx = 7, the signal will be high during 14 us */
/* (4) Select PWM mode 1 on OC1 (OC1M = 110),
enable preload register on OC1 (OC1PE = 1, reset value) */
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1 */
/* (6) Enable output (MOE = 1 */
/* (7) Enable counter (CEN = 1)
select center-aligned mode 1 (CMS = 01) */
/* (8) Force update generation (UG = 1) */
TIMx->PSC = 15; /* (1) */
TIMx->ARR = 8; /* (2) */
TIMx->CCR1 = 7; /* (3) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1
| TIM_CCMR1_OC1PE; /* (4) */
TIMx->CCER |= TIM_CCER_CC1E; /* (5) */
TIMx->CR1 |= TIM_CR1_CMS_0 | TIM_CR1_CEN; /* (6) */
TIMx->EGR |= TIM_EGR_UG; /* (7) */

A.9.10 ETR configuration to clear OCxREF code example

/* (1) Set prescaler to 15, so APBCLK/16 i.e 1MHz */
/* (2) Set ARR = 8, as timer clock is 1MHz the period is 9 us */
/* (3) Set CCRx = 4, , the signal will be high during 4 us */
/* (4) Select PWM mode 1 on OC1 (OC1M = 110),
enable preload register on OC1 (OC1PE = 1)
enable clearing on OC1 for ETR clearing (OC1CE = 1)*/
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),

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enable the output on OC1 (CC1E = 1)*/

/* (6) Select ETR as OCREF clear source (reserved bit = 1)
select External Trigger Prescaler off (ETPS = 00, reset value)
disable external clock mode 2 (ECE = 0, reset value)
select active at high level (ETP = 0, reset value) */
/* (7) Enable counter (CEN = 1)
select edge aligned mode (CMS = 00, reset value)
select direction as upcounter (DIR = 0, reset value) */
/* (8) Force update generation (UG = 1) */

TIMx->PSC = 15; /* (1) */

TIMx->ARR = 8; /* (2) */
TIMx->CCR1 = 4; /* (3) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE \
| TIM_CCMR1_OC1CE; /* (4) */
TIMx->CCER |= TIM_CCER_CC1E; /* (5) */
TIMx->SMCR |= (1<<3); /* (6) */
TIMx->CR1 |= TIM_CR1_CEN; /* (7) */
TIMx->EGR |= TIM_EGR_UG; /* (8) */

A.9.11 Encoder interface code example

/* (1) Configure TI1FP1 on TI1 (CC1S = 01)
configure TI1FP2 on TI2 (CC2S = 01) */
/* (2) Configure TI1FP1 and TI1FP2 non inverted (CC1P = CC2P = 0, reset
value) */
/* (3) Configure both inputs are active on both rising and falling edges
(SMS = 011) */
/* (4) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; /* (1 */
//TIMx->CCER &= (uint16_t)(~(TIM_CCER_CC21 | TIM_CCER_CC2P); /* (2) */
TIMx->SMCR |= TIM_SMCR_SMS_0 | TIM_SMCR_SMS_1; /* (3) */
TIMx->CR1 |= TIM_CR1_CEN; /* (4) */

A.9.12 Reset mode code example

/* (1) Configure channel 1 to detect rising edges on the TI1 input
by writing CC1S = ‘01’,
and configure the input filter duration by writing the IC1F[3:0]
bits
in the TIMx_CCMR1 register (if no filter is needed, keep
IC1F=0000).*/
/* (2) Select rising edge polarity by writing CC1P=0 in the TIMx_CCER
register
Not necessary as it keeps the reset value. */

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/* (3) Configure the timer in reset mode by writing SMS=100

Select TI1 as the trigger input source by writing TS=101
in the TIMx_SMCR register.*/
/* (4) Set prescaler to 16000-1 in order to get an increment each 1ms */
/* (5) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0; /* (1 */
//TIMx->CCER &= (uint16_t)(~TIM_CCER_CC1P); /* (2) */
TIMx->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_TS_2 | TIM_SMCR_TS_0; /* (3) */
TIMx->PSC = 15999; /* (4) */
TIMx->CR1 |= TIM_CR1_CEN; /* (5) */

A.9.13 Gated mode code example

/* (1) Configure channel 1 to detect low level on the TI1 input
by writing CC1S = ‘01’,
and configure the input filter duration by writing the IC1F[3:0]
bits
in the TIMx_CCMR1 register (if no filter is needed, keep
IC1F=0000).*/
/* (2) Select polarity by writing CC1P=1 in the TIMx_CCER register */
/* (3) Configure the timer in gated mode by writing SMS=101
Select TI1 as the trigger input source by writing TS=101
in the TIMx_SMCR register.*/
/* (4) Set prescaler to 4000-1 in order to get an increment each 250us */
/* (5) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0; /* (1 */
TIMx->CCER |= TIM_CCER_CC1P; /* (2) */
TIMx->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0 \
| TIM_SMCR_TS_2 | TIM_SMCR_TS_0; /* (3) */
TIMx->PSC = 3999; /* (4) */
TIMx->CR1 |= TIM_CR1_CEN; /* (5) */

A.9.14 Trigger mode code example

/* (1) Configure channel 2 to detect rising edge on the TI2 input
by writing CC2S = ‘01’,
and configure the input filter duration by writing the IC1F[3:0]
bits
in the TIMx_CCMR1 register (if no filter is needed, keep
IC1F=0000).*/
/* (2) Select polarity by writing CC2P=0 (reset value) in the TIMx_CCER
register */
/* (3) Configure the timer in trigger mode by writing SMS=110
Select TI2 as the trigger input source by writing TS=110
in the TIMx_SMCR register.*/
/* (4) Set prescaler to 4000-1 in order to get an increment each 250us */

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TIMx->CCMR1 |= TIM_CCMR1_CC2S_0; /* (1 */
//TIMx->CCER &= ~TIM_CCER_CC2P; /* (2) */
TIMx->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 \
| TIM_SMCR_TS_2 | TIM_SMCR_TS_1; /* (3) */
TIMx->PSC = 3999; /* (4) */

A.9.15 External clock mode 2 + trigger mode code example

/* (1) Configure no input filter (ETF=0000, reset value)
configure prescaler disabled (ETPS = 0, reset value)
select detection on rising edge on ETR (ETP = 0, reset value)
enable external clock mode 2 (ECE = 1 */
/* (2) Configure no input filter (IC1F=0000, reset value)
select input capture source on TI1 (CC1S = 01) */
/* (3) Select polarity by writing CC1P=0 (reset value) in the TIMx_CCER
register */
/* (4) Configure the timer in trigger mode by writing SMS=110
Select TI1 as the trigger input source by writing TS=101
in the TIMx_SMCR register.*/
TIMx->SMCR |= TIM_SMCR_ECE; /* (1) */
TIMx->CCMR1 |= TIM_CCMR1_CC1S_0; /* (2 */
//TIMx->CCER &= ~TIM_CCER_CC1P; /* (3) */
TIMx->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 \
| TIM_SMCR_TS_2 | TIM_SMCR_TS_0; /* (4) */

A.9.16 One-Pulse mode code example

/* The OPM waveform is defined by writing the compare registers */
/* (1) Set prescaler to 15, so APBCLK/16 i.e 1MHz */
/* (2) Set ARR = 7, as timer clock is 1MHz the period is 8 us */
/* (3) Set CCRx = 5, the burst will be delayed for 5 us (must be > 0 */
/* (4) Select PWM mode 2 on OC1 (OC1M = 111),
enable preload register on OC1 (OC1PE = 1, reset value)
enable fast enable (no delay) if PULSE_WITHOUT_DELAY is set*/
/* (5) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1 */
/* (6) Enable output (MOE = 1) */
/* (7) Write '1 in the OPM bit in the TIMx_CR1 register to stop the
counter
at the next update event (OPM = 1)
enable auto-reload register(ARPE = 1) */
TIMx->PSC = 15; /* (1) */
TIMx->ARR = 7; /* (2) */
TIMx->CCR1 = 5; /* (3) */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0

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| TIM_CCMR1_OC1PE
#if PULSE_WITHOUT_DELAY > 0
| TIM_CCMR1_OC1FE
#endif
; /* (4) */
TIMx->CCER |= TIM_CCER_CC1E; /* (5) */
TIMx->CR1 |= TIM_CR1_OPM | TIM_CR1_ARPE; /* (6) */

A.9.17 Timer prescaling another timer code example

/* (1) Select Update Event as Trigger output (TRG0) by writing MMS = 010
in TIMx_CR2. */
/* (2) Configure TIMy in slave mode using ITR1 as internal trigger
by writing TS = 000 in TIMy_SMCR (reset value)
Configure TIMy in external clock mode 1, by writing SMS=111 in the
TIMy_SMCR register. */
/* (3) Set TIMx prescaler to 15999 in order to get an increment each 1ms */
/* (4) Set TIMx Autoreload to 999 in order to get an overflow (so an UEV)
each second */
/* (5) Set TIMx Autoreload to 24*3600-1 in order to get an overflow
each 24-hour */
/* (6) Enable the counter by writing CEN=1 in the TIMx_CR1 register. */
/* (7) Enable the counter by writing CEN=1 in the TIMy_CR1 register. */
TIMx->CR2 |= TIM_CR2_MMS_1; /* (1 */
TIMy->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; /* (2) */
TIMx->PSC = 15999; /* (3) */
TIMx->ARR = 999; /* (4) */
TIMy->ARR = (24 * 3600) - 1; /* (5) */
TIMx->CR1 |= TIM_CR1_CEN; /* (6) */
TIMy->CR1 |= TIM_CR1_CEN; /* (7) */

A.9.18 Timer enabling another timer code example

/* (1) Configure Timer x master mode to send its Output Compare 1
Reference (OC1REF)
signal as trigger output (MMS=100 in the TIMx_CR2 register). */
/* (2) Configure the Timer x OC1REF waveform (TIMx_CCMR1 register)
Channel 1 is in PWM mode 1 when the counter is less than the
capture/compare
register (write OC1M = 110) */
/* (3) Configure TIMy in slave mode using ITR1 as internal trigger
by writing TS = 000 in TIMy_SMCR (reset value)
Configure TIMy in gated mode, by writing SMS=101 in the
TIMy_SMCR register. */
/* (4) Set TIMx prescaler to 2 */
/* (5) Set TIMy prescaler to 2 */

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/* (6) Set TIMx Autoreload to 999 in order to get an overflow (so an UEV)
each 100ms */
/* (7) Set capture compare register to a value between 0 and 999 */
TIMx->CR2 |= TIM_CR2_MMS_2; /* (1 */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; /* (2) */
TIMy->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0; /* (3) */
TIMx->PSC = 2; /* (4) */
TIMy->PSC = 2; /* (5) */
TIMx->ARR = 999; /* (6) */
TIMx-> CCR1 = 700; /* (7) */

/* Configure the slave timer to generate toggling on each count */

/* (1) Configure the Timer 2 in PWM mode 1 (write OC1M = 110) */
/* (2) Set TIMx Autoreload to 1 */
/* (3) Set capture compare register to 1 */
TIMy->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; /* (1) */
TIMy->ARR = 1; /* (2) */
TIMy-> CCR1 = 1; /* (3) */
/* Enable the output of TIMx OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1 */
/* (2) Enable output (MOE = 1 */
TIMx->CCER |= TIM_CCER_CC1E;

/* Enable the output of TIMy OC1 */

/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1 */
/* (2) Enable output (MOE = 1 */
TIMy->CCER |= TIM_CCER_CC1E;

/* (1) Enable the slave counter first by writing CEN=1 in the TIMy_CR1
register. */
/* (2) Enable the master counter by writing CEN=1 in the TIMx_CR1
register. */
TIMy->CR1 |= TIM_CR1_CEN; /* (1) */
TIMx->CR1 |= TIM_CR1_CEN; /* (2) */

A.9.19 Master and slave synchronization code example

/* (1) Configure Timer x in master mode to send its enable signal
as trigger output (MMS=001 in the TIMx_CR2 register). */
/* (2) Configure the Timer x Channel 1 waveform (TIMx_CCMR1 register)
is in PWM mode 1 (write OC1M = 110) */
/* (3) Configure TIMy in slave mode using ITR1 as internal trigger
by writing TS = 000 in TIMy_SMCR (reset value)
Configure TIMy in gated mode, by writing SMS=101 in the

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TIMy_SMCR register. */
/* (4) Set TIMx prescaler to 2 */
/* (5) Set TIMy prescaler to 2 */
/* (6) Set TIMx Autoreload to 99 in order to get an overflow (so an UEV)
each 10ms */
/* (7) Set capture compare register to a value between 0 and 99 */
TIMx->CR2 |= TIM_CR2_MMS_0; /* (1 */
TIMx->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; /* (2) */
TIMy->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0; /* (3) */
TIMx->PSC = 2; /* (4) */
TIMy->PSC = 2; /* (5) */
TIMx->ARR = 99; /* (6) */
TIMx-> CCR1 = 25; /* (7) */

/* Configure the slave timer Channel 1 as PWM as Timer to show

synchronicity */
/* (1) Configure the Timer y in PWM mode 1 (write OC1M = 110) */
/* (2) Set TIMx Autoreload to 99 */
/* (3) Set capture compare register to 25 */
TIMy->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; /* (1) */
TIMy->ARR = 99; /* (2) */
TIMy-> CCR1 = 25; /* (3) */

/* Enable the output of TIMx OC1 */

/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1 */
/* (2) Enable output (MOE = 1 */
TIMx->CCER |= TIM_CCER_CC1E;
/* Enable the output of TIMy OC1 */
/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1 */
/* (2) Enable output (MOE = 1 */
TIMy->CCER |= TIM_CCER_CC1E;
/* (1) Reset Timer x by writing ‘1 in UG bit (TIMx_EGR register) */
/* (2) Reset Timer y by writing ‘1 in UG bit (TIMy_EGR register) */
TIMx->EGR |= TIM_EGR_UG;
TIMy->EGR |= TIM_EGR_UG;
/* (1) Enable the slave counter first by writing CEN=1
in the TIMy_CR1 register.
TIMy will start synchronously with the master timer*/
/* (2) Start the master counter by writing CEN=1 in the TIMx_CR1
register. */
TIMy->CR1 |= TIM_CR1_CEN; /* (1) */
TIMx->CR1 |= TIM_CR1_CEN; /* (2) */

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A.9.20 Two timers synchronized by an external trigger code example

/* (1) Configure TIMx master mode to send its enable signal
as trigger output (MMS=001 in the TIMx_CR2 register). */
/* (2) Configure TIMx in slave mode to get the input trigger from TI1
by writing TS = 100 in TIMx_SMCR
Configure TIMx in trigger mode, by writing SMS=110 in the
TIMx_SMCR register.
Configure TIMx in Master/Slave mode by writing MSM = 1
in TIMx_SMCR */
/* (3) Configure TIMy in slave mode to get the input trigger from Timer1
by writing TS = 000 in TIMy_SMCR (reset value)
Configure TIMy in trigger mode, by writing SMS=110 in the
TIMy_SMCR register. */
/* (4) Reset Timer x counter by writing '1' in UG bit (TIMx_EGR register) */
/* (5) Reset Timer y counter by writing '1' in UG bit (TIMy_EGR register) */
TIMx->CR2 |= TIM_CR2_MMS_0; /* (1 */
TIMx->SMCR |= TIM_SMCR_TS_2 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1
| TIM_SMCR_MSM; /* (2) */
TIMy->SMCR |= TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1; /* (3) */
TIMx->EGR |= TIM_EGR_UG; /* (4) */
TIMy->EGR |= TIM_EGR_UG; /* (5) */

/* Configure the Timer Channel 2 as PWM as PWM */

/* (1) Configure the Timer 1 Channel 2 waveform (TIM1_CCMR1 register)
is in PWM mode 1 (write OC2M = 110) */
/* (2) Set TIMx prescaler to 2 */
/* (3) Set TIMx Autoreload to 99 in order to get an overflow (so an UEV)
each 10ms */
/* (4) Set capture compare register to a value between 0 and 99 */
TIMx->CCMR1 |= TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1; /* (1) */
TIMx->PSC = 2; /* (2) */
TIMx->ARR = 99; /* (3) */
TIMx-> CCR2 = 25; /* (4) */

/* Configure the slave timer Channel 1 as PWM as Timer

to show synchronicity */
/* (1) Configure the Timer 2 in PWM mode 1 (write OC1M = 110) */
/* (2) Set TIMy prescaler to 2 */
/* (3) Set TIMx Autoreload to 99 */
/* (4) Set capture compare register to 25 */
TIMy->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1; /* (1) */
TIMy->PSC = 2; /* (2) */
TIMy->ARR = 99; /* (2) */
TIMy-> CCR1 = 25; /* (3) */

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/* Enable the output of TIMx OC1 */

/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1 */
/* (2) Enable output (MOE = 1 */
TIMx->CCER |= TIM_CCER_CC2E;

/* Enable the output of TIMy OC1 */

/* (1) Select active high polarity on OC1 (CC1P = 0, reset value),
enable the output on OC1 (CC1E = 1 */
/* (2) Enable output (MOE = 1 */
TIMy->CCER |= TIM_CCER_CC1E;

A.9.21 DMA burst feature code example

/* Configure DMA Burst Feature */
/* Configure the corresponding DMA channel */
/* (1) Enable the peripheral clocks of Timer x and DMA*/
/* (2) Remap DMA channel2 on TIM2_UP by writing 1000 in DMA_CSELR_C2S */
/* (3) Set DMA channel peripheral address is the DMAR register address */
/* (4) Set DMA channel memory address is the address of the buffer in the
RAM containing the data to be transferred by DMA into CCRx
registers */
/* (5) Set the number of data transfer to sizeof(Duty_Cycle_Table) */
/* (6) Configure DMA transfer in CCR register
enable the circular mode by setting CIRC bit (optional)
set memory size to 16_bits MSIZE = 01
set peripheral size to 32_bits PSIZE = 10
enable memory increment mode by setting MINC
set data transfer direction read from memory by setting DIR */
/* (7) Configure TIMx_DCR register with DBL = 3 transfers
and DBA = (@TIMx->CCR2 - @TIMx->CR1) >> 2 = 0xE */
/* (8) Enable the TIMx update DMA request by setting UDE bit in DIER
register */
/* (9) Enable TIMx */
/* (10)Enable DMA channel */
RCC->AHBENR |= RCC_AHBENR_DMA1EN; /* (1) */
DMA1_CSELR->CSELR |= 8 << (4 * (2-1)); /* (2) */
DMA1_Channel2->CPAR = (uint32_t)(&(TIMx->DMAR)); /* (3) */
DMA1_Channel2->CMAR = (uint32_t)(Duty_Cycle_Table); /* (4) */
DMA1_Channel2->CNDTR = 10*3; /* (5) */
DMA1_Channel2->CCR |= DMA_CCR_CIRC | DMA_CCR_MSIZE_0 | DMA_CCR_PSIZE_1
| DMA_CCR_MINC | DMA_CCR_DIR; /* (6) */
TIMx->DCR = (3 << 8)
+ ((((uint32_t)(&TIM2->CCR2)) - ((uint32_t)(&TIM2->CR1))) >> 2)
; /* (7) */

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TIMx->DIER |= TIM_DIER_UDE; /* (8) */

TIMx->CR1 |= TIM_CR1_CEN; /* (9) */
DMA1_Channel2->CCR |= DMA_CCR_EN; /* (10) */

A.10 Low-power timer (LPTIM)

A.10.1 Pulse counter configuration code example

/* (1) Configure LPTimer in Counter on External Input1.*/
/* (2) Enable interrupt on Autoreload match */
/* (3) Enable LPTimer */
/* (4) Set Autoreload to 4 in order to get an interrupt after 10 pulses
because the 5 first pulses don't increment the counter */
LPTIM1->CFGR |= LPTIM_CFGR_COUNTMODE | LPTIM_CFGR_CKSEL; /* (1 */
LPTIM1->IER |= LPTIM_IER_ARRMIE; /* (2) */
LPTIM1->CR |= LPTIM_CR_ENABLE; /* (3) */
LPTIM1->ARR = 4; /* (4) */
LPTIM1->CR |= LPTIM_CR_CNTSTRT; /* start the counter in continuous */

A.11 IWDG code example

A.11.1 IWDG configuration code example

/* (1) Activate IWDG (not needed if done in option bytes) */
/* (2) Enable write access to IWDG registers */
/* (3) Set prescaler by 8 */
/* (4) Set reload value to have a rollover each 100ms */
/* (5) Check if flags are reset */
/* (6) Refresh counter */
IWDG->KR = IWDG_START; /* (1) */
IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
IWDG->PR = IWDG_PR_PR_0; /* (3) */
IWDG->RLR = IWDG_RELOAD; /* (4) */
while(IWDG->SR) /* (5) */
{
/* add time out here for a robust application */
}
IWDG->KR = IWDG_REFRESH; /* (6) */

A.11.2 IWDG configuration with window code example

/* (1) Activate IWDG (not needed if done in option bytes) */
/* (2) Enable write access to IWDG registers */
/* (3) Set prescaler by 8 */
/* (4) Set reload value to have a rollover each 100ms */

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/* (5) Check if flags are reset */

/* (6) Set a 50ms window, this will refresh the IWDG */
IWDG->KR = IWDG_START; /* (1) */
IWDG->KR = IWDG_WRITE_ACCESS; /* (2) */
IWDG->PR = IWDG_PR_PR_0; /* (3) */
IWDG->RLR = IWDG_RELOAD; /* (4) */
while(IWDG->SR) /* (5) */
{
/* add time out here for a robust application */
}
IWDG->WINR = IWDG_RELOAD >> 1; /* (6) */

A.12 WWDG code example

A.12.1 WWDG configuration code example

/* (1) set prescaler to have a rollover each about 16.5ms, set window
value (about 7.5ms) */
/* (2) Refresh WWDG before activate it */
/* (3) Activate WWDG */
WWDG->CFR = 0x0060; /* (1) */
WWDG->CR = WWDG_REFRESH; /* (2) */
WWDG->CR |= WWDG_CR_WDGA; /* (3) */

A.13 RTC code example

A.13.1 RTC calendar configuration code example

/* (1) Write access for RTC registers */
/* (2) Enable init phase */
/* (3) Wait until it is allow to modify RTC register values */
/* (4) set prescaler, 40kHz/64 => 625Hz, 625Hz/625 => 1Hz */
/* (5) New time in TR */
/* (6) Disable init phase */
/* (7) Disable write access for RTC registers */
RTC->WPR = 0xCA; /* (1) */
RTC->WPR = 0x53; /* (1) */
RTC->ISR = RTC_ISR_INIT; /* (2) */
while((RTC->ISR & RTC_ISR_INITF)!=RTC_ISR_INITF) /* (3) */
{
/* add time out here for a robust application */
}
RTC->PRER = 0x003F0270; /* (4) */
RTC->TR = RTC_TR_PM | Time; /* (5) */
RTC->ISR =~ RTC_ISR_INIT; /* (6) */

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RTC->WPR = 0xFE; /* (7) */

RTC->WPR = 0x64; /* (7) */

A.13.2 RTC alarm configuration code example

/* (1) Write access for RTC registers */
/* (2) Disable alarm A to modify it */
/* (3) Wait until it is allow to modify alarm A value */
/* (4) Modify alarm A mask to have an interrupt each 1Hz */
/* (5) Enable alarm A and alarm A interrupt */
/* (6) Disable write access */
RTC->WPR = 0xCA; /* (1) */
RTC->WPR = 0x53; /* (1) */
RTC->CR &=~ RTC_CR_ALRAE; /* (2) */
while((RTC->ISR & RTC_ISR_ALRAWF) != RTC_ISR_ALRAWF) /* (3) */
{
/* add time out here for a robust application */
}
RTC->ALRMAR = RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 |
RTC_ALRMAR_MSK1; /* (4) */
RTC->CR = RTC_CR_ALRAIE | RTC_CR_ALRAE; /* (5) */
RTC->WPR = 0xFE; /* (6) */
RTC->WPR = 0x64; /* (6) */

A.13.3 RTC WUT configuration code example

/* (1) Write access for RTC registers */
/* (2) Disable wake up timerto modify it */
/* (3) Wait until it is allow to modify wake up reload value */
/* (4) Modify wake up value reload counter to have a wake up each 1Hz */
/* (5) Enable wake up counter and wake up interrupt */
/* (6) Disable write access */
RTC->WPR = 0xCA; /* (1) */
RTC->WPR = 0x53; /* (1) */
RTC->CR &=~ RTC_CR_WUTE; /* (2) */
while((RTC->ISR & RTC_ISR_WUTWF) != RTC_ISR_WUTWF) /* (3) */
{
/* add time out here for a robust application */
}
RTC->WUTR = 0x9C0; /* (4) */
RTC->CR = RTC_CR_WUTE | RTC_CR_WUTIE; /* (5) */
RTC->WPR = 0xFE; /* (6) */
RTC->WPR = 0x64; /* (6) */

A.13.4 RTC read calendar code example

if((RTC->ISR & RTC_ISR_RSF) == RTC_ISR_RSF)

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{
TimeToCompute = RTC->TR; /* get time */
DateToCompute = RTC->DR; /* need to read date also */
}

A.13.5 RTC calibration code example

/* (1) Write access for RTC registers */
/* (2) Enable init phase */
/* (3) Wait until it is allow to modify RTC register values */
/* (4) set prescaler, 40kHz/125 => 320 Hz, 320Hz/320 => 1Hz */
/* (5) New time in TR */
/* (6) Disable init phase */
/* (7) Wait until it's allow to modify calibartion register */
/* (8) Set calibration to around +20ppm, which is a standard value @25°C */
/* Note: the calibration is relevant when LSE is selected for RTC clock */
/* (9) Disable write access for RTC registers */
RTC->WPR = 0xCA; /* (1) */
RTC->WPR = 0x53; /* (1) */
RTC->ISR = RTC_ISR_INIT; /* (2) */
while((RTC->ISR & RTC_ISR_INITF)!=RTC_ISR_INITF) /* (3) */
{
/* add time out here for a robust application */
}
RTC->PRER = (124<<16) | 319; /* (4) */
RTC->TR = RTC_TR_PM | Time; /* (5) */
RTC->ISR &=~ RTC_ISR_INIT; /* (6) */
while((RTC->ISR & RTC_ISR_RECALPF) == RTC_ISR_RECALPF) /* (7) */
{
/* add time out here for a robust application */
}
RTC->CALR = RTC_CALR_CALP | 482; /* (8) */
RTC->WPR = 0xFE; /* (9) */
RTC->WPR = 0x64; /* (9) */

A.13.6 RTC tamper and time stamp configuration code example

/* Tamper configuration:
- Disable precharge (PU)
- RTCCLK/256 tamper sampling frequency
- Activate time stamp on tamper detection
- input rising edge trigger detection on RTC_TAMP2 (PA0)
- Tamper interrupt enable */
RTC->TAFCR = RTC_TAFCR_TAMPPUDIS | RTC_TAFCR_TAMPFREQ | RTC_TAFCR_TAMPTS
| RTC_TAFCR_TAMP2E | RTC_TAFCR_TAMPIE;

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A.13.7 RTC tamper and time stamp code example

/* Check tamper and timestamp flag */
if(((RTC->ISR & (RTC_ISR_TAMP2F)) == (RTC_ISR_TAMP2F)) && ((RTC->ISR &
(RTC_ISR_TSF)) == (RTC_ISR_TSF)))
{
RTC->ISR =~ (RTC_ISR_TAMP2F); /* clear tamper flag */
EXTI->PR = EXTI_PR_PR19; /* clear exti line 19 flag */
TimeToCompute = RTC->TSTR; /* get tamper time in timestamp register */
RTC->ISR =~ (RTC_ISR_TSF); /* clear timestamp flag */
}

A.13.8 RTC clock output code example

/* (1) Write access for RTC registers */
/* (2) Disable alarm A to modify it */
/* (3) Wait until it is allow to modify alarm A value */
/* (4) Modify alarm A mask to have an interrupt each 1Hz */
/* (5) Enable alarm A and alarm A interrupt, calibration output (1Hz)
enable */
/* (6) Disable write access */
RTC->WPR = 0xCA; /* (1) */
RTC->WPR = 0x53; /* (1) */
RTC->CR &=~ RTC_CR_ALRAE; /* (2) */
while((RTC->ISR & RTC_ISR_ALRAWF) != RTC_ISR_ALRAWF) /* (3) */
{
/* add time out here for a robust application */
}
RTC->ALRMAR = RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 |
RTC_ALRMAR_MSK1; /* (4) */
RTC->CR = RTC_CR_ALRAIE | RTC_CR_ALRAE | RTC_CR_COE | RTC_CR_COSEL; /*(5 */
RTC->WPR = 0xFE; /* (6) */
RTC->WPR = 0x64; /* (6) */

A.14 I2C code example

A.14.1 I2C configured in slave mode code example

/* (1) Timing register value is computed with the AN4235 xls file,
fast Mode @400kHz with I2CCLK = 16MHz, rise time = 100ns,
fall time = 10ns */
/* (2) Periph enable, address match interrupt enable */
/* (3) 7-bit address = 0x5A */
/* (4) Enable own address 1 */
I2C1->TIMINGR = (uint32_t)0x00300619; /* (1) */
I2C1->CR1 = I2C_CR1_PE | I2C_CR1_ADDRIE; /* (2) */

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I2C1->OAR1 |= (uint32_t)(I2C1_OWN_ADDRESS << 1); /* (3) */

I2C1->OAR1 |= I2C_OAR1_OA1EN; /* (4) */

A.14.2 I2C slave transmitter code example

uint32_t I2C_InterruptStatus = I2C1->ISR; /* Get interrupt status */
/* Check address match */
if((I2C_InterruptStatus & I2C_ISR_ADDR) == I2C_ISR_ADDR)
{
I2C1->ICR |= I2C_ICR_ADDRCF; /* Clear address match flag */
/* Check if transfer direction is read (slave transmitter) */
if((I2C1->ISR & I2C_ISR_DIR) == I2C_ISR_DIR)
{
I2C1->CR1 |= I2C_CR1_TXIE; /* Set transmit IT */
}
}
else if((I2C_InterruptStatus & I2C_ISR_TXIS) == I2C_ISR_TXIS)
{
I2C1->CR1 &=~ I2C_CR1_TXIE; /* Disable transmit IT */
I2C1->TXDR = I2C_BYTE_TO_SEND; /* Byte to send */
}

A.14.3 I2C slave receiver code example

uint32_t I2C_InterruptStatus = I2C1->ISR; /* Get interrupt status */
if((I2C_InterruptStatus & I2C_ISR_ADDR) == I2C_ISR_ADDR)
{
I2C1->ICR |= I2C_ICR_ADDRCF; /* Address match event */
}
else if((I2C_InterruptStatus & I2C_ISR_RXNE) == I2C_ISR_RXNE)
{
/* Read receive register, will clear RXNE flag */
if(I2C1->RXDR == I2C_BYTE_TO_SEND)
{
/* Process */
}
}

A.14.4 I2C configured in master mode to receive code example

/* (1) Timing register value is computed with the AN4235 xls file,
fast Mode @400kHz with I2CCLK = 16MHz, rise time = 100ns, fall time =
10ns */
/* (2) Periph enable, receive interrupt enable */
/* (3) Slave address = 0x5A, read transfer, 1 byte to receive, autoend */
I2C2->TIMINGR = (uint32_t)0x00300619; /* (1) */
I2C2->CR1 = I2C_CR1_PE | I2C_CR1_RXIE; /* (2) */

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I2C2->CR2 = I2C_CR2_AUTOEND | (1<<16) | I2C_CR2_RD_WRN |

(I2C1_OWN_ADDRESS<<1); /* (3) */

A.14.5 I2C configured in master mode to transmit code example

/* (1) Timing register value is computed with the AN4235 xls file,
fast Mode @400kHz with I2CCLK = 16MHz, rise time = 100ns, fall time =
10ns */
/* (2) Periph enable */
/* (3) Slave address = 0x5A, write transfer, 1 byte to transmit, autoend */
I2C2->TIMINGR = (uint32_t)0x00300619; /* (1) */
I2C2->CR1 = I2C_CR1_PE; /* (2) */
I2C2->CR2 = I2C_CR2_AUTOEND | (1<<16) | (I2C1_OWN_ADDRESS<<1); /* (3) */

A.14.6 I2C master transmitter code example

/* Check Tx empty */
if((I2C2->ISR & I2C_ISR_TXE) == (I2C_ISR_TXE))
{
I2C2->TXDR = I2C_BYTE_TO_SEND; /* Byte to send */
I2C2->CR2 |= I2C_CR2_START; /* Go */
}

A.14.7 I2C master receiver code example

if((I2C2->ISR & I2C_ISR_RXNE) == I2C_ISR_RXNE)
{
/* Read receive register, will clear RXNE flag */
if(I2C2->RXDR == I2C_BYTE_TO_SEND)
{
/* Process */
}
}

A.14.8 I2C configured in master mode to transmit with DMA code example
/* (1) Timing register value is computed with the AN4235 xls file,
fast Mode @400kHz with I2CCLK = 16MHz, rise time = 100ns, fall time =
10ns */
/* (2) Periph enable */
/* (3) Slave address = 0x5A, write transfer, 2 bytes to transmit, autoend */
I2C2->TIMINGR = (uint32_t)0x00300619; /* (1) */
I2C2->CR1 = I2C_CR1_PE | I2C_CR1_TXDMAEN; /* (2) */
I2C2->CR2 = I2C_CR2_AUTOEND | (SIZE_OF_DATA << 16) |
(I2C1_OWN_ADDRESS<<1); /* (3) */

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A.14.9 I2C configured in slave mode to receive with DMA code example
/* (1) Timing register value is computed with the AN4235 xls file,
fast Mode @400kHz with I2CCLK = 16MHz, rise time = 100ns, fall time =
10ns */
/* (2) Periph enable, receive DMA enable */
/* (3) 7-bit address = 0x5A */
/* (4) Enable own address 1 */
I2C1->TIMINGR = (uint32_t)0x00300619; /* (1) */
I2C1->CR1 = I2C_CR1_PE | I2C_CR1_RXDMAEN | I2C_CR1_ADDRIE; /* (2) */
I2C1->OAR1 |= (uint32_t)(I2C1_OWN_ADDRESS << 1); /* (3) */
I2C1->OAR1 |= I2C_OAR1_OA1EN; /* (4) */

A.15 USART code example

A.15.1 USART transmitter configuration code example

/* (1) oversampling by 16, 9600 baud */
/* (2) 8 data bit, 1 start bit, 1 stop bit, no parity */
USART1->BRR = 160000 / 96; /* (1) */
USART1->CR1 = USART_CR1_TE | USART_CR1_UE; /* (2) */

A.15.2 USART transmit byte code example

/* start USART transmission */
USART1->TDR = stringtosend[send++]; /* Will inititiate TC if TXE */

A.15.3 USART transfer complete code example

if((USART1->ISR & USART_ISR_TC) == USART_ISR_TC)
{
if(send == sizeof(stringtosend))
{
send=0;
USART1->ICR = USART_ICR_TCCF; /* Clear transfer complete flag */
}
else
{
/* clear transfer complete flag and fill TDR with a new char */
USART1->TDR = stringtosend[send++];
}
}

A.15.4 USART receiver configuration code example

/* (1) oversampling by 16, 9600 baud */
/* (2) 8 data bit, 1 start bit, 1 stop bit, no parity, reception mode */

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USART1->BRR = 160000 / 96; /* (1) */

USART1->CR1 = USART_CR1_RXNEIE | USART_CR1_RE | USART_CR1_UE; /* (2) */

A.15.5 USART receive byte code example

if((USART1->ISR & USART_ISR_RXNE) == USART_ISR_RXNE)
{
chartoreceive = (uint8_t)(USART1->RDR); /* Receive data, clear flag */
}

A.15.6 USART LIN mode code example

/* (1) oversampling by 16, 9600 baud */
/* (2) LIN mode */
/* (3) 8 data bit, 1 start bit, 1 stop bit, no parity, reception and
transmission enabled */
USART1->BRR = 160000 / 96; /* (1) */
USART1->CR2 = USART_CR2_LINEN | USART_CR2_LBDIE; /* (2) */
USART1->CR1 = USART_CR1_TE | USART_CR1_RXNEIE | USART_CR1_RE |
USART_CR1_UE; /* (3) */
while((USART1->ISR & USART_ISR_TC) != USART_ISR_TC)/* polling idle frame
Transmission */
{
/* add time out here for a robust application */
}
USART1->ICR = USART_ICR_TCCF;/* Clear TC flag */
USART1->CR1 |= USART_CR1_TCIE;/* Enable TC interrupt */

A.15.7 USART synchronous mode code example

/* (1) oversampling by 16, 9600 baud */
/* (2) Synchronous mode */
/* CPOL and CPHA = 0 => rising first edge */
/* Last bit clock pulse */
/* Most significant bit first in transmit/receive */
/* (3) 8 data bit, 1 start bit, 1 stop bit, no parity */
/* Transmission enabled, reception enabled */
USART1->BRR = 160000 / 96; /* (1) */
USART1->CR2 = USART_CR2_MSBFIRST | USART_CR2_CLKEN | USART_CR2_LBCL; /* (2)
*/
USART1->CR1 = USART_CR1_TE | USART_CR1_RXNEIE | USART_CR1_RE |
USART_CR1_UE; /* (3) */
/* polling idle frame Transmission w/o clock */
while((USART1->ISR & USART_ISR_TC) != USART_ISR_TC)
{
/* add time out here for a robust application */
}
USART1->ICR = USART_ICR_TCCF;/* clear TC flag */

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USART1->CR1 |= USART_CR1_TCIE;/* enable TC interrupt */

A.15.8 USART single-wire half-duplex code example

/* (1) oversampling by 16, 9600 baud */
/* (2) Single-wire half-duplex mode */
/* (3) 8 data bit, 1 start bit, 1 stop bit, no parity, reception and
transmission enabled */
USART1->BRR = 160000 / 96; /* (1) */
USART1->CR3 = USART_CR3_HDSEL; /* (2) */
USART1->CR1 = USART_CR1_TE | USART_CR1_RXNEIE | USART_CR1_RE |
USART_CR1_UE; /* (3) */
while((USART1->ISR & USART_ISR_TC) != USART_ISR_TC)/* polling idle frame
Transmission */
{
/* add time out here for a robust application */
}
USART1->ICR = USART_ICR_TCCF;/* Clear TC flag */
USART1->CR1 |= USART_CR1_TCIE;/* Enable TC interrupt */

A.15.9 USART smartcard mode code example

/* (1) oversampling by 16, 9600 baud */
/* (2) Clock divided by 16 = 1MHz */
/* (3) Samrt card mode enable */
/* (4) 1.5 stop bits, clock enable */
/* (5) 8-data bit plus parity, 1 start bit */
USART1->BRR = 160000 / 96; /* (1) */
USART1->GTPR = 16 >> 1; /* (2) */
USART1->CR3 = USART_CR3_SCEN; /* (3) */
USART1->CR2 = USART_CR2_STOP_1 | USART_CR2_STOP_0 | USART_CR2_CLKEN;/*(4 */
USART1->CR1 = USART_CR1_M | USART_CR1_PCE | USART_CR1_TE |
USART_CR1_UE;/* (5) */
/* Polling idle frame transmission transfer complete (this frame is not
sent) */
while((USART1->ISR & USART_ISR_TC) != USART_ISR_TC)
{
/* add time out here for a robust application */
}
USART1->ICR = USART_ICR_TCCF;/* clear TC flag */
USART1->CR1 |= USART_CR1_TCIE;/* enable TC interrupt */

A.15.10 USART IrDA mode code example

/* (1) oversampling by 16, 9600 baud */
/* (2) Divide by 24 to achieve the low power frequency */
/* (3) Enable IrDA */
/* (4) 8 data bit, 1 start bit, 1 stop bit, no parity */

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USART1->BRR = 160000 / 96; /* (1) */

USART1->GTPR = 24; /* (2) */
USART1->CR3 = USART_CR3_IREN; /* (3) */
USART1->CR1 = USART_CR1_TE | USART_CR1_UE; /* (4) */
/* polling idle frame Transmission */
while((USART1->ISR & USART_ISR_TC) != USART_ISR_TC)
{
/* add time out here for a robust application */
}
USART1->ICR = USART_ICR_TCCF;/* clear TC flag */
USART1->CR1 |= USART_CR1_TCIE;/* enable TC interrupt */

A.15.11 USART DMA code example

/* (1) oversampling by 16, 9600 baud */
/* (2) Enable DMA in reception and transmission */
/* (3) 8 data bit, 1 start bit, 1 stop bit, no parity, reception and
transmission enabled */
USART1->BRR = 160000 / 96; /* (1) */
USART1->CR3 = USART_CR3_DMAT | USART_CR3_DMAR; /* (2) */
USART1->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE; /* (3) */
while((USART1->ISR & USART_ISR_TC) != USART_ISR_TC)/* polling idle frame
Transmission */
{
/* add time out here for a robust application */
}
USART1->ICR = USART_ICR_TCCF;/* Clear TC flag */

A.15.12 USART hardware flow control code example

/* (1) oversampling by 16, 9600 baud */
/* (2) RTS and CTS enabled */
/* (3) 8 data bit, 1 start bit, 1 stop bit, no parity, reception and
transmission enabled */
USART1->BRR = 160000 / 96; /* (1) */
USART1->CR3 = USART_CR3_RTSE | USART_CR3_CTSE; /* (2) */
USART1->CR1 = USART_CR1_TE | USART_CR1_RXNEIE | USART_CR1_RE |
USART_CR1_UE; /* (3) */
while((USART1->ISR & USART_ISR_TC) != USART_ISR_TC)/* polling idle frame
Transmission */
{
/* add time out here for a robust application */
}
USART1->ICR = USART_ICR_TCCF;/* Clear TC flag */
USART1->CR1 |= USART_CR1_TCIE;/* Enable TC interrupt */

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A.16 LPUART code example

A.16.1 LPUART receiver configuration code example

/* (1) oversampling by 16, 9600 baud */
/* (2) Enable STOP mode, 8 data bit, 1 start bit, 1 stop bit, no parity,
reception mode */
LPUART1->BRR = 0x369; /* (1) */
LPUART1->CR1 = USART_CR1_UESM | USART_CR1_RXNEIE | USART_CR1_RE |
USART_CR1_UE; /* (2) */

A.16.2 LPUART receive byte code example

if((LPUART1->ISR & USART_ISR_RXNE) == USART_ISR_RXNE)
{
chartoreceive = (uint8_t)(LPUART1->RDR); /* Receive data, clear flag */
}

A.17 SPI code example

A.17.1 SPI master configuration code example

/* (1) Master selection, BR: Fpclk/256,
CPOL and CPHA at zero (rising first edge) */
/* (2) Slave select output enabled, RXNE IT, 8-bit Rx fifo */
/* (3) Enable SPI1 */
SPI1->CR1 = SPI_CR1_MSTR | SPI_CR1_BR; /* (1) */
SPI1->CR2 = SPI_CR2_SSOE | SPI_CR2_RXNEIE; /* (2) */
SPI1->CR1 |= SPI_CR1_SPE; /* (3) */

A.17.2 SPI slave configuration code example

/* nSS hard, slave, CPOL and CPHA at zero (rising first edge) */
/* (1) RXNE IT, 8-bit Rx fifo */
/* (2) Enable SPI2 */
SPI2->CR2 = SPI_CR2_RXNEIE; /* (1) */
SPI2->CR1 |= SPI_CR1_SPE; /* (2) */

A.17.3 SPI full duplex communication code example

if((SPI1->SR & SPI_SR_TXE) == SPI_SR_TXE) /* Test Tx empty */
{
/* Will inititiate 8-bit transmission if TXE */
*(uint8_t *)&(SPI1->DR) = SPI1_DATA;
}

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A.17.4 SPI master configuration with DMA code example

/* (1) Master selection, BR: Fpclk/256
CPOL and CPHA at zero (rising first edge) */
/* (2) TX and RX with DMA, slave select output enabled, RXNE IT, 8-bit Rx
fifo */
/* (3) Enable SPI1 */
SPI1->CR1 = SPI_CR1_MSTR | SPI_CR1_BR; /* (1) */
SPI1->CR2 = SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN | SPI_CR2_SSOE;; /* (2) */
SPI1->CR1 |= SPI_CR1_SPE; /* (3) */

A.17.5 SPI slave configuration with DMA code example

/* nSS hard, slave, CPOL and CPHA at zero (rising first edge) */
/* (1) TX and RX with DMA, RXNE IT, 8-bit Rx fifo */
/* (2) Enable SPI2 */
SPI2->CR2 = SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN; /* (1) */
SPI2->CR1 |= SPI_CR1_SPE; /* (2) */

A.17.6 SPI interrupt code example

if((SPI1->SR & SPI_SR_RXNE) == SPI_SR_RXNE)
{
SPI1_Data = (uint8_t)SPI1->DR; /* receive data, clear flag */
/* Process */
}

A.18 DBG code example

A.18.1 DBG read device Id code example

MCU_Id = DBGMCU->IDCODE; /* Read MCU Id, 32-bit access */

A.18.2 DBG debug in LPM code example

DBGMCU->CR |= DBGMCU_CR_DBG_STOP; /* To be able to debug in stop mode */

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Revision history

Table 148. Document revision history

Date Revision Changes

29-Apr-2014 1 Initial release.

Section 1.3: Peripheral availability: added features
corresponding to category 2 and 5 (STM32L031x/7xx/8xx),
updated Table 2: Overview of features per category.
Added Appendix A: Code examples.

System and memory overview

Added features corresponding to category 2 and 5.
Updated TIMER 7 register addresses in Table 3: STM32L0x1
peripheral register boundary addresses.

Flash memory/data EEPROM

Added features corresponding to category 2 and 5.
Replaced FLASH_WRPROT by FLASH_WRPROT1 and added
FLASH_WRPROT2 register. Updated BOR_LEV description and
renamed BOOT1 into nBOOT1 in FLASH_OPTCR register.
Updated READY flag description in FLASH_SR register.

CRC
04-May-2015 2 Updated Section 4.2: CRC main features and Section :
Polynomial programmability.

FIREWALL
Updated Section 5.3.5: Firewall initialization.

PWR
Removed limitation related to 1.8V minimum VDDA for ADC and
updated VREF+ in Section 6.1: Power supplies. Updated
packages in Section 6.1.1: Independent A/D converter supply
and reference voltage. Updated Figure 10: Power supply
overview. Updated Range 1 description in Section 6.1.4:
Dynamic voltage scaling management.
Updated Table 34: Summary of low-power modes.
Added Section 6.3.5: Entering low-power mode and Section
6.3.6: Exiting low-power mode.
Updated Section 6.3.7: Sleep mode to remove details on mode
entry and exit and updated Table 35: Sleep-now and Table 36:
Sleep-on-exit.

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Table 148. Document revision history (continued)

Date Revision Changes

PWR (continued)
Updated Section 6.3.8: Low-power sleep mode (LP sleep) to
remove details on mode entry and exit and updated Table 37:
Sleep-now (Low-power sleep) and Table 38: Sleep-on-exit (Low-
power sleep).
Updated Section 6.3.9: Stop mode to remove details on mode
entry and exit and updated Table 39: Stop mode.
Updated Section 6.3.10: Standby mode to remove details on
mode entry and exit and updated Table 40: Standby mode
Updated LPRUN bit description in Section 6.4.1: PWR power
control register (PWR_CR).
Added EWUP3 bit in Section 6.4.2: PWR power control/status
register (PWR_CSR).

RCC
Updated ADC clock in Section 7.2: Clocks.
Added HSE failure in Section 7.2.9: HSE clock security system
(CSS).
Section 7.3.6: Clock interrupt clear register (RCC_CICR):
changed all bit access type to ‘w, renamed USB bit into UFB and
bit moved to bit 3.
04-May-2015 2 (continued)
Renamed MIFIEN into FWEN and description updated in Section
7.3.13: APB2 peripheral clock enable register (RCC_APB2ENR).
Updated Section 7.3.20: Control/status register (RCC_CSR).
Section 7.3.10: APB1 peripheral reset register
(RCC_APB1RSTR): Added USART4RST, USART5RST,
TIM3RST, TIM7RST and I2C3RST. Renamed UARTxRST bits
into USARTxRST.
Added IOPERST in Section 7.3.7: GPIO reset register
(RCC_IOPRSTR), IOPEENR in Section 7.3.11: GPIO clock
enable register (RCC_IOPENR), and IOPESMEN in Section
7.3.15: GPIO clock enable in Sleep mode register
(RCC_IOPSMENR).
Section 7.3.14: APB1 peripheral clock enable register
(RCC_APB1ENR): Added USART4EN, USART5EN, TIM3EN
and TIM7EN and I2C3EN. Renamed UARTxEN bits into
USARTxEN.
Section 7.3.18: APB1 peripheral clock enable in Sleep mode
register (RCC_APB1SMENR): Added USART4SMEN,
USART5SMEN, TIM3SMEN, TIM7SMEN and I2C3SMEN.
Renamed UARTxSMEN bits into USARTxSMEN.
Added I2C3SEL bits in Section 7.3.19: Clock configuration
register (RCC_CCIPR).

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Table 148. Document revision history (continued)

Date Revision Changes

GPIOs
Add Port E for category 2 and 5 devices.

SYSCFG
Updated Figure 1: System architecture to add STM32L07/08
peripherals. Added UBS bit in Section 9.2.1: SYSCFG memory
remap register (SYSCFG_CFGR1). Replaced REF_CFGR3 by
SYSCFG_CFGR3. Added I2C3_FMP bit and updated CAPA bits
in Section 9.2.2: SYSCFG peripheral mode configuration register
(SYSCFG_CFGR2).
Updated Section 9.2.4: SYSCFG external interrupt configuration
register 1 (SYSCFG_EXTICR1), Section 9.2.5: SYSCFG
external interrupt configuration register 2 (SYSCFG_EXTICR2),
Section 9.2.6: SYSCFG external interrupt configuration register
3 (SYSCFG_EXTICR3) and Section 9.2.7: SYSCFG external
interrupt configuration register 4 (SYSCFG_EXTICR4).

DMA
Updated DMA mapping/channel selection for category 2 and 5
devices. Updated Figure 26: DMA request mapping to add AES.

INTERRUPTS
Changed number of priority levels from 16 to 4.
04-May-2015 2 (continued)
Updated Table 52: List of vectors and Table 53: EXTI lines
connections to add peripherals for category 2 and 5 devices and
update vectors 17 and 18.
Added bit24 in all EXTI registers.

ADC
Updated Figure 28: ADC block diagram.
Section 13.4.1: ADC voltage regulator (ADVREGEN): changed
REF_CTRL into REF_CFGR3 and ENBUF_EN_VREFINT_ADC
into ENBUF_VREFINT_ADC.
Removed limitation related to 1.8 V VDDA minimum value.
Changed VDDA= 3.3 V into 3 V in Section 13.10: Temperature
sensor and internal reference voltage.
Updated AWDCH bitfield definition in Section 13.12.4: ADC
configuration register 1 (ADC_CFGR1).

COMP
Updated Figure 51: Comparator 1 and 2 block diagrams.
Added COMP1LPTIMIN1 in Section 14.5.1: Comparator 1
control and status register (COMP1_CSR). Added
COMP2LPTIMIN2 and COMP2LPTIMIN1, and updated
COMP2INSEL definition in Section 14.5.2: Comparator 2 control
and status register (COMP2_CSR).

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Table 148. Document revision history (continued)

Date Revision Changes

Added Section 15: Advanced encryption standard hardware

accelerator (AES).

General-purpose timers (TIM2/3)

Added TIMER3.
Removed 32-bit option.
Updated sequence to use TI2FP2 as trigger 1 in Section 16.3.10:
One-pulse mode.
Added note related to slave timer clock in Section 16.3.15: Timer
synchronization.
Updated MMS bit description in Section 16.4.2: TIMx control
register 2 (TIMx_CR2) to add note related to slave timer clock.
Updated SMS bits and Table 76: TIM2/TIM3 internal trigger
connection in Section 16.4.3: TIMx slave mode control register
(TIMx_SMCR) and added note related to slave timer clock.
Updated ETR_RMP description in Section 16.4.19: TIM2 option
register (TIM2_OR).

General-purpose timers (TIM21/22)

Updated sequence to use TI2FP2 as trigger 1 in Section 17.3.11:
One-pulse mode.
04-May-2015 2 (continued) Removed note related to TIMx_BDTR in OC1M and OC1PE bit
description of Section 16.4.7: TIMx capture/compare mode
register 1 (TIMx_CCMR1)/output compare.

Basic timers
Added TIMER7.

LPTIM
Updated TRIGSEL description in Section 19.6.4: LPTIM
configuration register (LPTIM_CFGR). Added ext_trig5 in Table
82: LPTIM external trigger connection.

WWDG
Updated Figure 174: Watchdog block diagram and timeout
formula and example in Section 21.3.4: How to program the
watchdog timeout.

RTC
Added tamper 3 event (category 5 devices only).
Updated WUCKSEL bits in Figure 173: RTC block diagram.
Section 22.4.5: Programmable alarms: Changed MSK0 to MSK1
in caution note.

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Table 148. Document revision history (continued)

Date Revision Changes

I2C
Updated NOSTRECH definition in Section 23.7.1: Control
register 1 (I2C_CR1).

USART
Added USART4/5 for category 2 and 5 devices.
Updated Figure 209: USART block diagram.
Added Low-power modes sections.
Updated Section : Single byte communication.
Updated Table 106: Error calculation for programmed baud rates
at fCK = 32 MHz in both cases of oversampling by 16 or by 8.
Updated Figure 226: IrDA SIR ENDEC- block diagram, Figure
228: Transmission using DMA and Figure 229: Reception using
DMA.
Removed UCESM bit from USARTx_CR3 as well as the
capability to keep enabled USART clock during Stop mode.
Updated REACK flag description in USARTx_ISR register.

LPUART
Updated Figure 234: LPUART block diagram.
04-May-2015 2 (continued)
Added Low-power modes sections.
Removed note in Section 25.4.1: LPUART character description.
Updated Table 113: Error calculation for programmed baudrates
at fck = 32,768 KHz
Updated Table 127: LPUART interrupt requests.
Changed LPUARTx_RDR and LPUARTx_TDR reset values in
Table 128: LPUART register map and reset values.
Removed UCESM bit from LPUART_CR3 as well as the
capability to keep enabled LPUART clock during Stop mode.

SPI
Updated Table 131: Audio-frequency precision using standard 8
MHz HSE.

DEBUG
Updated REV_ID bitfield in Section : DBG_IDCODE. Added bits
to support I2C3, TIM3 and TIM7 in Section 27.9.4: Debug MCU
APB1 freeze register (DBG_APB1_FZ).

Updated Appendix A: Code examples.

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Table 148. Document revision history (continued)

Date Revision Changes

Added category 1 devices (STM32L011xx and STM32L021xx)

and related features.
UpdatedTable 12: NVM organization for UFB = 0 (64 Kbyte
category 5 devices): BOOT0= 0 and UBS = 1 configuration
forbidden.

GPIOs:
Updated OSPEEDy[1:0] definition in Section 8.4.3: GPIO port
output speed register (GPIOx_OSPEEDR) (x = A..E and H).

ADC:
Replaced AUTDLY by WAIT in Figure 28: ADC block diagram.
Updated Section : Analog reference for the ADC internal voltage
regulator. Updated ADC enable sequence in Section 13.4.3:
ADC on-off control (ADEN, ADDIS, ADRDY). Changed EXTSEL
into EXTEN in Section 13.4.10: Starting conversions (ADSTART)
and ADSTART bit description in Section 13.12.3: ADC control
register (ADC_CR).

LPTIM:
Updated Section 19.4.7: Operating mode.
Added Section Figure 168.: LPTIM output waveform, single
counting mode configuration, Section Figure 169.: LPTIM output
03-Aug-2015 3 waveform, Single counting mode configuration and Set-once
mode activated (WAVE bit is set) and Section Figure 170.:
LPTIM output waveform, Continuous counting mode
configuration.
Updated CNT bitfield definition in Section 19.6.8: LPTIM counter
register (LPTIM_CNT).

RTC:
Updated step 3 in Section : Programming the wakeup timer.
Modified WUTWF description in Section 22.7.4: RTC
initialization and status register (RTC_ISR)

I2C:
Added information on the stretch mechanism in Section : I2C
timings.
Updated definition of SCLDEL[3:0] and SDADEL[3:0] bits in
Timing register (I2C_TIMINGR).

USART:
Updated note related to RTO counter in Section : Block mode
(T=1).

LPUART:
Updated Figure 234: LPUART block diagram.

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Table 148. Document revision history (continued)

Date Revision Changes

DEBUG:
Updated SWDIO bidirectional management in Section 27.5.1:
SWD protocol introduction.
03-Aug-2015 3 (continued)

Updated Section 28.2: Unique device ID registers (96 bits).

Updated Appendix A.8.2: ADC enable sequence code example.
Updated IWDG in Table 2: Overview of features per category.

Flash program memory and data EEPROM

Split NVM memory organization table for category 5 devices into
2 tables: NVM organization for UFB = 0 and Flash memory and
data EEPROM remapping.
Replaced bus error by hard fault in the whole section.
Updated description of Level 1 memory read protection in
Section 3.4.1: RDP (Read Out Protection).
Renamed UBS bit of SYSCFG_CFGR1 into UFB.
Removed IWDG_ULP bit and updated reset value in Section
3.7.8: Option bytes register (FLASH_OPTR).
Updated reset value in Section 3.7.9: Write protection register 1
(FLASH_WRPROT1) and Section 3.7.10: Write protection
register 2 (FLASH_WRPROT2).

Power controller (PWR)

Updated Section 6.2.4: Internal voltage reference (VREFINT) to
add exit from Standby mode on an NRST pulse.
20-Nov-2015 4 Added note related to HSI16 in Stop mode in Table 34: Summary
of low-power modes.
Updated DS_EE_KOFF bit definition in PWR power control
register (PWR_CR).

Reset and clock controller (RCC)

Updated Section 7.1.2: Power reset and Figure 16: Simplified
diagram of the reset circuit.
Suppressed capability to stop IWDG in Stop/Standby mode on
category 1 devices:
Updated Section 7.2.12: Watchdog clock.
Removed LSIIWDGLP bit in Control/status register (RCC_CSR).
Modified HSI16OUTEN bit definition and HSI16KERON and
HSI16RDYF access type in Clock control register (RCC_CR).
Updated GPIO clock enable in Sleep mode register
(RCC_IOPSMENR), AHB peripheral clock enable in Sleep mode
register (RCC_AHBSMENR), APB2 peripheral clock enable in
Sleep mode register (RCC_APB2SMENR) and APB1 peripheral
clock enable in Sleep mode register (RCC_APB1SMENR) reset
values.

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Table 148. Document revision history (continued)

Date Revision Changes

General-purpose I/Os (GPIOS)

Added GPIOH.

System configuration controller (SYSCFG)

Updated definition of BOOT_MODE and MEM_MOD bits in
SYSCFG memory remap register (SYSCFG_CFGR1) to replace
BOOT pins by boot configuration.
Updated SYSCFG peripheral mode configuration register
(SYSCFG_CFGR2) reset value.
Removed EN_VERFINT, VREFINT_COMP_RDYF,
VREFINT_ADC_RDYF and SENSOR_ADC_RDYF bits in
Reference control and status register (SYSCFG_CFGR3).

Nested vector interrupt controller (NVIC)

MemManage_Handler, BusFault_Handler,Usagefault _Handler
and DebugMon_Handler changed to reserved in Table 52: List of
vectors.

Comparators (COMP)
Updated COMP2INPSEL bit definition to add PA7 (see Section
14.5.2: Comparator 2 control and status register
(COMP2_CSR)).

TIM2/3
20-Nov-2015 4 (continued)
Updated ETR_RMP bit definition in TIM2 option register
(TIM2_OR).

Independent watchdog (IWDG)

Suppressed capability to stop IWDG in Stop/Standby mode on
category 1 devices (see Section 20.3.4: Behavior in Stop and
Standby modes).

Real-time clock (RTC2)

Updated Figure 173: RTC block diagram and related note.
Updated RTC_OUT_RMP and RTC_ALARM_TYPE definition in
Section 22.7.19: RTC option register (RTC_OR).

Universal synchronous asynchronous receiver transmitter

(USART)
Replaced nCTS by CTS - nRTS by RTS - SCLK by CK.
Added Section : Determining the maximum USART baud rate
allowing to wakeup correctly from Stop mode when the USART
clock source is the HSI clock..
Updated Table 119: Effect of low-power modes on the USART.
Updated RTOF bit definition in Section 24.8.8: Interrupt and
status register (USART_ISR).
Replaced "w" by "rc_w1" in Section 24.8.9: Interrupt flag clear
register (USART_ICR).

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Table 148. Document revision history (continued)

Date Revision Changes

Low-power UART (LPUART)

Updated Figure 234: LPUART block diagram.
Removed LPTIM1_OR and LPTIM2_OR.
Updated Table 126: Effect of low-power modes on the LPUART.
Removed TFQRX in Table 128: LPUART register map and reset
values.

SPI/I2S:
Updated Figure 247, Figure 248, Figure 249 and Figure 250.
Updated and added notes below Figure 247, Figure 248 and
Figure 249.
Added Section 26.3.4: Multi-master communication.

Code examples:
Updated Section A.3.7: Program Option byte code example and
Section A.3.9: Program a single word to Flash program memory
code example, Section A.3.10: Program half-page to Flash
program memory code example and Section A.3.11: Erase a
page in Flash program memory code example.
Updated Section A.8.5: Single conversion sequence code
example - Software trigger, Section A.8.6: Continuous
20-Nov-2015 4 (continued) conversion sequence code example - Software trigger, Section
A.8.7: Single conversion sequence code example - Hardware
trigger, Section A.8.8: Continuous conversion sequence code
example - Hardware trigger, Section A.8.11: Wait mode
sequence code example, Section A.8.12: Auto off and no wait
mode sequence code example, Section A.8.13: Auto off and wait
mode sequence code example, Section A.8.14: Analog
watchdog code example and Section A.8.16: Temperature
configuration code example.
Updated Section A.9.4: Input capture data management code
example and Section A.9.10: ETR configuration to clear
OCxREF code example.
Updated Section A.13.1: RTC calendar configuration code
example, Section A.13.5: RTC calibration code example and
Section A.13.7: RTC tamper and time stamp code example.
Updated Section A.15.3: USART transfer complete code
example, Section A.15.6: USART LIN mode code example,
Section A.15.7: USART synchronous mode code example,
Section A.15.8: USART single-wire half-duplex code example,
Section A.15.9: USART smartcard mode code example, Section
A.15.10: USART IrDA mode code example, Section A.15.11:
USART DMA code example and Section A.15.12: USART
hardware flow control code example.

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Table 148. Document revision history (continued)

Date Revision Changes

Updated Section 2.3: Embedded SRAM.

Flash program memory and data EEPROM

Updated Table 9: Flash memory and data EEPROM remapping
(192 Kbyte category 5 devices) and Table 11: Flash memory and
data EEPROM remapping (128 Kbyte category 5 devices).
Updated Section 3.3.2: Dual-bank boot capability.
Updated BFB2 bit description in Section 3.7.8: Option bytes
register (FLASH_OPTR).

Power control (PWR)

Updated condition for entering low-power mode in Section 6.3.5:
Entering low-power mode, Table 35: Sleep-now, Table 36: Sleep-
on-exit, Table 37: Sleep-now (Low-power sleep), Table 38:
Sleep-on-exit (Low-power sleep), Table 39: Stop mode and Table
40: Standby mode.
Updated DS_EE_KOFF bit definition in PWR power control
register (PWR_CR).

Reset and clock control (RCC)

Updated Section 7.1.2: Power reset and Figure 16: Simplified
diagram of the reset circuit.
Updated Section 7.2.6: LSI clock and Section 7.2.12: Watchdog
clock.
19-Feb-2016 5
System configuration controller (SYSCFG)
Updated UFB bit description in SYSCFG memory remap register
(SYSCFG_CFGR1).

Nested vector interrupt controller

Updated EXTI_IMR reset value.

Analog-to-digital converter (ADC)

Updated EOSMP bit description in Section 13.12.1: ADC
interrupt and status register (ADC_ISR).
Updated Section 13.4.10: Starting conversions (ADSTART) and
ADSTART bit description in Section 13.12.3: ADC control
register (ADC_CR).

TIMER21/22
Updated SMS bit definition in Section 17.4.3: TIM21/22 slave
mode control register (TIMx_SMCR).
Restricted Table 82: TIM21/22 register map and reset values to
16 bits instead of 32.

TIMER6/7
Restricted Table 83: TIM6/7 register map and reset values to 16
bits instead of 32.

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Table 148. Document revision history (continued)

Date Revision Changes

Real-time clock (RTC)

Updated behavior of RTC under system reset in Section 22.4.9:
Resetting the RTC.

Inter-integrated circuit interface (I2C)

Added description of stretch mechanism that guarantees setup
and hold times in Section : I2C timings and SCDEL bit
description in Section 23.7.5: Timing register (I2C_TIMINGR).

Universal synchronous asynchronous receiver transmitter

(USART)
Changed tWUSTOP to tWUUSART in Section 24.5.5: Tolerance
of the USART receiver to clock deviation.
Updated Section 24.5.10: USART LIN (local interconnection
network) mode.
19-Feb-2016 5 (continued)
Updated Section 24.8.3: Control register 3 (USART_CR3)
‘ONEBIT’ bit 11 description adding a note.

Low-power UART (LPUART)

Updated Section 25.4.4: LPUART baud rate generation.
Added Section 25.4.5: Tolerance of the LPUART receiver to
clock deviation and Section : Determining the maximum
LPUART baud rate allowing to wakeup correctly from Stop mode
when the LPUART clock source is the HSI clock.

Debug
Updated Section 27.9.1: Debug support for low-power modes.
Updated Section 27.9.3: Debug MCU configuration register
(DBG_CR).
Added Table 135: REV-ID values in Section : DBG_IDCODE.

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Table 148. Document revision history (continued)

Date Revision Changes

FIREWALL
Updated LENG bitfield description in Section 5.4.6: Volatile data
segment length (FW_VDSL).

Power control (PWR)

Updated voltage regulator status in Stop mode in Table 34:
Summary of low-power modes.
Updated power consumption methods in Stop mode in Section :
Entering Stop mode.
Updated PDDS bit description in Section 6.4.1: PWR power
control register (PWR_CR).

Reset and clock control (RCC)

HSE RTC clock source frequency changed to 4 MHz.
Section 7.1.2: Power reset: added internal pull-up deactivation in
case of internal reset and updated Figure 16: Simplified diagram
of the reset circuit.
Updated Section 7.2.10: LSE Clock Security System to add
condition on LSE oscillator minimum frequency.

30-Aug-2016 6 System configuration controller (SYSCFG)

Updated ENBUF_VREFINT_COMP bit description in Reference
control and status register (SYSCFG_CFGR3).

Analog-to-digital converter (ADC)

Updated calibration software procedure in Section 13.4.2:
Calibration (ADCAL).
Changed EXTEN value from 00 to 01 in the note related to HW
trigger selection in Section 13.4.10: Starting conversions
(ADSTART).

General-purpose timers (TIM2/3)

Replace TIM2_SMCR by TIMy_SMCR in Section : Using one
timer to start another timer and Section : Starting 2 timers
synchronously in response to an external trigger.
Updated PSC[15:0] bitfield definition in Section 16.4.11: TIMx
prescaler (TIMx_PSC).
Changed TIMx capture/compare register 1 (TIMx_CCR1), TIMx
capture/compare register 2 (TIMx_CCR2), TIMx
capture/compare register 3 (TIMx_CCR3) and TIMx
capture/compare register 4 (TIMx_CCR4) registers to read-only
when CCy channel is configured as input.

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Table 148. Document revision history (continued)

Date Revision Changes

Lite timers (TIM21/22)

Updated PSC[15:0] bitfield definition in Section 17.4.10:
TIM21/22 prescaler (TIMx_PSC).
Changed TIMx_ARR reset value to 0xFFFF FFFF in Section
17.4.11.
Changed TIM21/22 control register 1 (TIMx_CR1) and TIM21/22
control register 2 (TIMx_CR2) registers to read-only when CCy
channel is configured as input.

Basic timers (TIM6/7)

Updated PSC[15:0] bitfield definition in Section 18.4.7: TIM6/7
prescaler (TIMx_PSC).
Changed TIMx_ARR reset value to 0xFFFF FFFF in Section
18.4.8.

Real-time clock (RTC)

Updated Section 22.4.15: Calibration clock output.
Section 22.7.3: RTC control register (RTC_CR):
Added caution note at the end of the section.
Updated ADD1H and SUB1H descriptions
30-Aug-2016 6 (continued) Updated caution note at the end of Section 22.7.16: RTC tamper
configuration register (RTC_TAMPCR).
Removed capability to reset RTC_BKPxR registers when the
Flash readout protection is disabled in Section : RTC backup
registers and Section 22.7.20: RTC backup registers
(RTC_BKPxR).

Inter-integrated circuit interface (I2C)

Updated Section 23.4.5: I2C initialization, Section 23.4.8: I2C
slave mode and Section 23.7.5: Timing register (I2C_TIMINGR).
Updated:
Note on Section 23.4.9: I2C master mode
Bit 13 on Section 23.7.2: Control register 2 (I2C_CR2)

Universal synchronous asynchronous receiver transmitter

(USART)
Updated Section 24.5.17: Wakeup from Stop mode using
USART.
Added bit USESM in Section 24.5.17: Wakeup from Stop mode
using USART and Section 24.8.3: Control register 3
(USART_CR3).

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Table 148. Document revision history (continued)

Date Revision Changes

Low-power UART (LPUART)

Updated Section 25.4.11: Wakeup from Stop mode using
LPUART.
Added bit USESM in Section 25.4.11: Wakeup from Stop mode
using LPUART and Section 25.7.3: Control register 3
30-Aug-2016 6 (continued) (LPUART_CR3).
Updated RWU bit description to remove the note related to
wakeup from Stop in Interrupt & status register (LPUART_ISR).

Debug support (DBG)

Added revision X in Table 135: REV-ID values.
Flash program memory and data EEPROM
In Section 3.4.1: RDP (Read Out Protection), for protection level
2, added note related to debug feature disabled under reset.

System configuration controller (SYSCFG)

Updated Reference control and status register
(SYSCFG_CFGR3):
Added EN_VREFINT
Renamed ENBUF_VREFINT_COMP into
ENBUF_VREFINT_COMP2 and description updated.
Updated ENBUF_SENSOR_ADC and ENBUF_VREFINT_ADC

DMA controller (DMA)

Removed DMA_REQx from Figure 26: DMA request mapping.

Analog-to-digital converter (ADC)

Replaced ADVREFEN by ADVREGEN in Section : Analog
14-Nov-2016 7 reference for the ADC internal voltage regulator.

Comparator (COMP)
Updated COMPx_CSR to add a note related to VREFINT in
COMP2INNSEL bit description.

Real-time clock (RTC)

Replaced HSE/32 by HSE prescaled in Figure 173: RTC block
diagram.
Updated Section 22.2: RTC main features to support the fact that
RTC_TAMP3 is available on cat. 2 in addition to 1 and 5.
Added Section 22.3: RTC implementation. Removed notes
related to RTC_TAMP3 availability depending on categories in
RTC_ISR and RTC_TAMPCR.
Updated Section 22.4.15: Calibration clock output.
Updated ADD1H and SUB1H description in RTC control register
(RTC_CR).
Updated RTC backup registers (RTC_BKPxR) register
description.

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Table 148. Document revision history (continued)

Date Revision Changes

Flash program memory and data EEPROM

Updated Section 3.4: Memory protection.
Updated level 1 description in Section 3.4.1: RDP (Read Out
Protection).
Improved read while write description in Section 3.6.2: Sequence
of operations and Table 20: Boot pin and BFB2 bit configuration.

Power controller
Updated Section 6.2.3: Programmable voltage detector (PVD).
Updated Section : Exiting Standby mode.
Updated VOSF bit description in Section 6.4.2: PWR power
control/status register (PWR_CSR).

Reset and clock controller

Updated Section 7.2.5: LSE clock.
Updated HSI16RDYF description in Section 7.3.1: Clock control
register (RCC_CR).

System configuration controller (SYSCFG)

Updated EN_VREFINT bit description in Section 9.2.3:
Reference control and status register (SYSCFG_CFGR3).
30-Nov-2017 8
Analog-to-digital converted (ADC)
Renamed EOSEQ, EOSEQIE, EXTENSEL bits into EOS,
EOSIE, EXTEN. Replaced tADC by tCONV in the whole
document.
Changed number of internal analog inputs to 2 instead of 3
(temperature sensor and int. reference voltage).
Added ADC_AWDx_OUT in Table 55: ADC internal signals.
Updated step 2 of calibration software procedure in Section
13.3.3: Calibration (ADCAL).
Updated Section 13.3.3: Calibration (ADCAL).
Updated tCONV unit in Table 60: tSAR timings depending on
resolution.
Added note related to the management of the internal oscillator
in Section 13.6.2: Auto-off mode (AUTOFF).
Replaced ADC_HTR and ADC_LTR registers by HT[11:0] and
LT[11:0] in Section 13.7: Analog window watchdog (AWDEN,
AWDSGL, AWDCH, ADC_TR, AWD) and updated Figure 46:
Analog watchdog guarded area.
Removed all references to DMA double buffer mode.

AES hardware accelerator (AES)

General update.

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Table 148. Document revision history (continued)

Date Revision Changes

Window watchdog (WWDG)

Updated Figure 290.
Updated Section 31.3.5: Debug mode.
Updated Table 172: WWDG register map and reset values.

Real-time clock (RTC)

Updated Section 29.4.2: GPIOs controlled by the RTC.

Inter-integrated circuit interface (I2C)

Updated OA1[7:1] and OA2[7:1] bit descriptions in Section
32.7.3: Own address 1 register (I2C_OAR1) and Section 32.7.4:
Own address 2 register (I2C_OAR2), respectively.
Updated NACKCF bit definition in Section 32.7.8: Interrupt clear
register (I2C_ICR).

Universal synchronous asynchronous receiver transmitter

(USART)
Added definition of tWUUSART in Section 24.5.5: Tolerance of
30-Nov-2017 8 (continued) the USART receiver to clock deviation.
Restored PSC bit description for Section 24.8.5: Guard time and
prescaler register (USART_GTPR).

Low-power UART (LPUART)

Added definition of tWLPUART in Section 25.4.5: Tolerance of
the LPUART receiver to clock deviation.
Added Note in Section 25.4.11: Wakeup from Stop mode using
LPUART.
Note related to 7-bit data length removed in Section 25.7.1:
Control register 1 (LPUART_CR1).

Debug
Updated Cortex-M0+ ID code in Section 27.5.3: SW-DP state
machine (reset, idle states, ID code) and Section 27.5.5: SW-DP
registers.

Updated Appendix A.3.10: Program half-page to Flash program

memory code example and A.8.1: Calibration code example.

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RM0377 Revision history

Table 148. Document revision history (continued)

Date Revision Changes

Introduction:
Added errata sheet in the list of reference documents.
Added indication that patents apply to the devices.
Removed Arm logo.

Added Section 1.1: General information. Updated Section 1.2:

List of abbreviations for registers. Removed note related to
product under development in Table 1: STM32L0x1 memory
density.

In Section : Empty check (category 1 devices only), modified

address related to empty check enabling.

Section 3: Flash program memory and data EEPROM

(FLASH)
Added data EEPROM granularity in Section 3.2: NVM main
features.
Added Erase/write endurance cycles in Section 3.3.1: NVM
organization, Section : Write to data EEPROM and Section :
Program a single word to Flash program memory.

Section 4: Cyclic redundancy check calculation unit (CRC)

Added note in Section : Polynomial programmability to clarify
what is an even and an odd polynomial.
26-Mar-2021 9
Section 6: Power control (PWR)
In Section 6.1.1: Independent A/D and DAC converter supply
and reference voltage, replaced distinction between packages
with more or less and 64 pins by packages with and without
VREF+.
Changed bit to disable the ADC and DAC from ADON of
ADC_CR2 to ADDIS of ADC_CR in Section : Entering Stop
mode.
Replaced all occurrences of “power voltage detector” by
“programmable voltage detector” in Section 6.4: Power control
registers.

Section 7: Reset and clock control (RCC)

Updated Figure 16: Simplified diagram of the reset circuit.
Updated Section 7.1.1: System reset to indicate that registers
are reset by System reset unless otherwise specified.
Changed bit access type to rw in Section 7.3.5: Clock interrupt
enable register (RCC_CIER).
Replaced CSSHSE by CSSLSE in RTCSEL description in
Section 7.3.21: Control/status register (RCC_CSR).

Section 9: System configuration controller (SYSCFG)

Updated note in EN_VREFINT bit of Section 9.2.3: Reference
control and status register (SYSCFG_CFGR3).

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Revision history RM0377

Table 148. Document revision history (continued)

Date Revision Changes

Section 10: Direct memory access controller (DMA)

General update.

Section 12: Extended interrupt and event controller (EXTI)

Changed bit 18 of EXTI_EMR and EXTI_IMR to reserved.
Updated EXTI_PR register reset value.

Section 13: Analog-to-digital converter (ADC)

Changed number of multiplexed channels to 18 and number of
internal channels to 2. Removed LCD/VLCD from the whole
section. Replaced Low-power Sleep and Low-power run by
LPSleep and LPRun.
Updated Figure 30: ADC block diagram to show VIN[x], remove
JOFFSETx and JOFFSETx_CH and replace VTS by VSENSE.
Renamed and updated Table 68: ADC input/output pins and
Table 69: ADC internal input/output signals.
Updated Figure 34: ADC clock scheme.
Moved Table 70: External triggers to Section 13.3.1: ADC pins
and internal signals, updated note 1., and replaced reference to
Table ADC interconnections by Table 70: External triggers in
26-Mar-2021 9 (continued) Section 13.4: Conversion on external trigger and trigger polarity
(EXTSEL, EXTEN).
Updated Section 13.3.2: ADC voltage regulator (ADVREGEN) to
indicate that power consumption can be further disabled by
disabling the ADC regulator.
Changed programmable factor to 1, 2 and 4 in Section 13.3.5:
ADC clock (CKMODE, PRESC[3:0], LFMEN).
Added Section 13.3.6: ADC connectivity.
Added Section 13.7.2: ADC_AWD1_OUT output signal
generation and Section 13.7.3: Analog watchdog threshold
control.
Updated formula used for temperature calculation in Section :
Reading the temperature. Updated Section : Calculating the
actual VDDA voltage using the internal reference voltage to
replace specific voltage value by VDDA_Charac. Same
modification done in the formula to compute VCHANNELx in
Section : Converting a supply-relative ADC measurement to an
absolute voltage value.
Changed bit 8 and 9 access type from ‘r_w1’ to ‘rc_w1’ in ADC
interrupt and status register (ADC_ISR). Replaced OVS by
OVSE in ADC configuration register 2 (ADC_CFGR2).

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RM0377 Revision history

Table 148. Document revision history (continued)

Date Revision Changes

Section 17: General-purpose timers (TIM21/22)

Updated Figure 930: Capture/compare channel 1 main circuit.
Updated Section 17.3.6: PWM input mode.

Section 19: Low-power timer (LPTIM)

Updated Section 19.2: LPTIM main features.
Updated Section 19.4.3: LPTIM reset and clocks and Section
19.4.4: Glitch filter. Added note to Section 19.4.6: Trigger
multiplexer.
Updated Section 19.4.8: Timeout function and Section 19.4.14:
Encoder mode.
Added Section 19.4.15: Debug mode and Section 19.5: LPTIM
low-power modes.
Updated Section 19.7.1: LPTIM interrupt and status register
(LPTIM_ISR), Section 19.7.2: LPTIM interrupt clear register
(LPTIM_ICR), Section 19.7.4: LPTIM configuration register
(LPTIM_CFGR).

Section 22: Real-time clock (RTC)

Changed the time interval at which the current calendar value is
copied into the shadow registers to one RTCCLK period in
26-Mar-2021 9 (continued) Section 22.4.9: Real-time clock and calendar and Section :
When BYPSHAD control bit is cleared in the RTC_CR register.
Updated Section 22.7.4: RTC initialization and status register
(RTC_ISR).

Section 23: Inter-integrated circuit (I2C) interface

Updated Section 23.2: I2C main features: SMBUS specification
rev 2.0 replaced by 3.0 and PMBus rev 1.1 by 1.3.
Updated Section 23.3: I2C implementation to indicate that: Fast-
mode Plus available for I2C1/2/3.
Updated Figure 630: I2C block diagram. Added Table 378: I2C
input/output pins and Table 379: I2C internal input/output signals
Changed HSI to HSI16 in Section 23.4.15: Wakeup from Stop
mode on address match.
Updated Section 23.5: I2C low-power modes.
Section 23.6: I2C interrupts:
Updated Table 393: I2C Interrupt requests.
Removed the sequence to enable the I2C interrupts and figure:
I2C interrupt mapping diagram.
Updated Section 23.7.2: I2C control register 2 (I2C_CR2),
Section 23.7.3: I2C own address 1 register (I2C_OAR1) and
Section 23.7.8: I2C interrupt clear register (I2C_ICR).

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Revision history RM0377

Table 148. Document revision history (continued)

Date Revision Changes

Section 24: Universal synchronous/asynchronous receiver

transmitter (USART/UART)
Updated section title.
Updated Figure 248: USART block diagram.
Updated example 1 in Section : How to derive USARTDIV from
USART_BRR register values.
Changed USART_TDR into USART_RDR in Figure 268:
Reception using DMA.
Added note related to the maximum baud rate to wake up from
Stop mode, and updated Tbit Min in Section 24.5.17: Wakeup
from Stop mode using USART.
Updated Section 24.8: USART registers to indicate that USART
registers are accessed by words.
Added ABRE bit in ABRRQ bit definition of USART request
register (USART_RQR).
USART interrupt and status register (USART_ISR):
Updated EOBF bit description (EOBIE belongs to USART_CR1
instead of USART_CR2).
Updated ABRE bit description (ABRRQ belongs to USART_RQR
instead of USART_CR3).
26-Mar-2021 9 (continued)
Changed USART transmit data register (USART_TDR) reset
value from undefined to 0x0000 0000.

Section 25: Low-power universal asynchronous receiver

transmitter (LPUART)
Updated Figure 273: LPUART block diagram.
Added Section 27.4: USART implementation.
Changed LPUART_TDR into LPUART_RDR in Figure 280:
Reception using DMA.
Added note related to the maximum baud rate to wake up from
Stop mode in Section 25.4.11: Wakeup from Stop mode using
LPUART.
Updated Section 25.7: LPUART registers to indicate that
LPUART registers are accessed by words.

Section 26: Serial peripheral interface/ inter-IC sound

(SPI/I2S)
Updated note in Section 26.4.2: CRC calculation. Updated
Section 26.6.4: Clock generator and Table 172: Audio-frequency
precision using standard 8 MHz HSE.

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RM0377 Revision history

Table 148. Document revision history (continued)

Date Revision Changes

Section 2.2.2: Memory map and register boundary

addresses and Section 2.3: Embedded SRAM
Changed SRAM size to “up to 20 Kbytes”.

Section 4: Cyclic redundancy check calculation unit (CRC)

Added CRC register access granularity in Section 4.2: CRC
main features and Section 4.4: CRC registers.
Updated Figure 7: CRC calculation unit block diagram.

Section 13: Analog-to-digital converter (ADC)

Removed ADC supply requirements from Section 13.2: ADC
main features.
In Section 13.3.7: Configuring the ADC, ADC configuration
register 1 (ADC_CFGR1) and ADC configuration register 2
(ADC_CFGR2), specified that ADC_CFGR1/2 must be
03-Feb-2022 10
configured only when ADCEN = 0.
Updated note related to ADSTART clearing in Section 13.3.12:
Starting conversions (ADSTART).
Removed temperature range from the list of main features in
Section 13.9: Temperature sensor and internal reference
voltage.
Added reference to Section 13.3.6: ADC connectivity in CHSELx
description of ADC channel selection register (ADC_CHSELR).

Section 22: Real-time clock (RTC)

Update note in Section 22.4.15: Calibration clock output and
Section 22.4.16: Alarm output.

Section 27: Debug support (DBG)

Updated REV_ID in DBG_IDCODE register.

RM0377 Rev 10 901/905

901
Index RM0377

Index

A EXTI_IMR . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
EXTI_PR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
ADC_CALFACT . . . . . . . . . . . . . . . . . . . . . . .325
EXTI_RTSR . . . . . . . . . . . . . . . . . . . . . . . . . . 274
ADC_CCR . . . . . . . . . . . . . . . . . . . . . . . . . . .326
EXTI_SWIER . . . . . . . . . . . . . . . . . . . . . . . . . 275
ADC_CFGR1 . . . . . . . . . . . . . . . . . . . . . . . . .318
ADC_CFGR2 . . . . . . . . . . . . . . . . . . . . . . . . .322
ADC_CHSELR . . . . . . . . . . . . . . . . . . . . . . . .324 F
ADC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 FLASH_ACR . . . . . . . . . . . . . . . . . . . . . . . . . 101
ADC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 FLASH_CR . . . . . . . . . . . . . . . . . . . . . . . . . . 106
ADC_IER . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 FLASH_KEYR . . . . . . . . . . . . . . . . . . . . . . . . 102
ADC_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . .313 FLASH_OPTKEYR . . . . . . . . . . . . . . . . 106-107
ADC_SMPR . . . . . . . . . . . . . . . . . . . . . . . . . .323 FLASH_OPTR . . . . . . . . . . . . . . . . . . . . . . . . 110
ADC_TR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324 FLASH_PDKEYR . . . . . . . . . . . . . . . . . . . . . 106
AES_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 FLASH_PECR . . . . . . . . . . . . . . . . . . . . . . . . 102
AES_DINR . . . . . . . . . . . . . . . . . . . . . . . . . . .365 FLASH_PEKEYR . . . . . . . . . . . . . . . . . . . . . 106
AES_DOUTR . . . . . . . . . . . . . . . . . . . . . . . . .365 FLASH_PRGKEYR . . . . . . . . . . . . . . . . . . . . 106
AES_IVR . . . . . . . . . . . . . . . . . . . . . . . . . . . .368 FLASH_SR . . . . . . . . . . . . . . . . . . . . . . 106, 108
AES_KEYRx . . . . . . . . . . . . . . . . . . . . . . . . .366 FLASH_WRPROT1 . . . . . . . . . . . . . . . . . . . . 112
AES_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364 FLASH_WRPROT2 . . . . . . . . . . . . . . . . . . . . 113
FW_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
C FW_CSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
FW_CSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
COMP1_CSR . . . . . . . . . . . . . . . . . . . . . . . . .331
FW_NVDSL . . . . . . . . . . . . . . . . . . . . . . . . . . 132
COMP2_CSR . . . . . . . . . . . . . . . . . . . . . . . . .333
FW_NVDSSA . . . . . . . . . . . . . . . . . . . . . . . . 132
CRC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
FW_VDSL . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
CRC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
FW_VDSSA . . . . . . . . . . . . . . . . . . . . . . . . . . 133
CRC_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
CRC_INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
CRC_POL . . . . . . . . . . . . . . . . . . . . . . . . . . .122 G
GPIOx_AFRH . . . . . . . . . . . . . . . . . . . . . . . . 230
D GPIOx_AFRL . . . . . . . . . . . . . . . . . . . . . . . . 229
GPIOx_BRR . . . . . . . . . . . . . . . . . . . . . . . . . 230
DBG_APB1_FZ . . . . . . . . . . . . . . . . . . . . . . .829
GPIOx_BSRR . . . . . . . . . . . . . . . . . . . . . . . . 228
DBG_APB2_FZ . . . . . . . . . . . . . . . . . . . . . . .831
GPIOx_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . 227
DBG_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .827
GPIOx_LCKR . . . . . . . . . . . . . . . . . . . . . . . . 228
DBG_IDCODE . . . . . . . . . . . . . . . . . . . . . . . .820
GPIOx_MODER . . . . . . . . . . . . . . . . . . . . . . 225
DBGMCU_CR . . . . . . . . . . . . . . . . . . . . . . . .827
GPIOx_ODR . . . . . . . . . . . . . . . . . . . . . . . . . 227
DMA_CCRx . . . . . . . . . . . . . . . . . . . . . . . . . .256
GPIOx_OSPEEDR . . . . . . . . . . . . . . . . . . . . 226
DMA_CMARx . . . . . . . . . . . . . . . . . . . . . . . . .260
GPIOx_OTYPER . . . . . . . . . . . . . . . . . . . . . . 225
DMA_CNDTRx . . . . . . . . . . . . . . . . . . . . . . . .259
GPIOx_PUPDR . . . . . . . . . . . . . . . . . . . . . . . 226
DMA_CPARx . . . . . . . . . . . . . . . . . . . . . . . . .260
DMA_IFCR . . . . . . . . . . . . . . . . . . . . . . . . . . .255
DMA_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 I
DMA1_CSELR . . . . . . . . . . . . . . . . . . . . . . . .262 I2C_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
I2C_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
E I2C_ICR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
I2C_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
EXTI_EMR . . . . . . . . . . . . . . . . . . . . . . . . . . .273
I2C_OAR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
EXTI_FTSR . . . . . . . . . . . . . . . . . . . . . . . . . .275
I2C_OAR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

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RM0377 Index

I2C_PECR . . . . . . . . . . . . . . . . . . . . . . . . . . .653 RCC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

I2C_RXDR . . . . . . . . . . . . . . . . . . . . . . . . . . .654 RCC_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
I2C_TIMEOUTR . . . . . . . . . . . . . . . . . . . . . . .649 RCC_ICSCR . . . . . . . . . . . . . . . . . . . . . . . . . 184
I2C_TIMINGR . . . . . . . . . . . . . . . . . . . . . . . .648 RCC_IOPENR . . . . . . . . . . . . . . . . . . . . . . . . 196
I2C_TXDR . . . . . . . . . . . . . . . . . . . . . . . . . . .654 RCC_IOPRSTR . . . . . . . . . . . . . . . . . . . . . . . 191
I2Cx_CR2 . . . . . . . . . . . . . . . . . . . . . . . . 131-134 RCC_IOPSMENR . . . . . . . . . . . . . . . . . . . . . 203
IWDG_KR . . . . . . . . . . . . . . . . . . . . . . . . . . .531 RTC_ALRMAR . . . . . . . . . . . . . . . . . . . . . . . 571
IWDG_PR . . . . . . . . . . . . . . . . . . . . . . . . . . .532 RTC_ALRMASSR . . . . . . . . . . . . . . . . . . . . . 582
IWDG_RLR . . . . . . . . . . . . . . . . . . . . . . . . . .533 RTC_ALRMBR . . . . . . . . . . . . . . . . . . . . . . . 572
IWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . . .534 RTC_ALRMBSSR . . . . . . . . . . . . . . . . . . . . . 583
IWDG_WINR . . . . . . . . . . . . . . . . . . . . . . . . .535 RTC_BKPxR . . . . . . . . . . . . . . . . . . . . . . . . . 585
RTC_CALR . . . . . . . . . . . . . . . . . . . . . . . . . . 578
RTC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
L
RTC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
LPTIM_ARR . . . . . . . . . . . . . . . . . . . . . . . . . .526 RTC_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
LPTIM_CFGR . . . . . . . . . . . . . . . . . . . . . . . .521 RTC_OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
LPTIM_CMP . . . . . . . . . . . . . . . . . . . . . . . . . .525 RTC_PRER . . . . . . . . . . . . . . . . . . . . . . . . . . 569
LPTIM_CNT . . . . . . . . . . . . . . . . . . . . . . . . . .526 RTC_SHIFTR . . . . . . . . . . . . . . . . . . . . . . . . 574
LPTIM_CR . . . . . . . . . . . . . . . . . . . . . . . . . . .524 RTC_SSR . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
LPTIM_ICR . . . . . . . . . . . . . . . . . . . . . . . . . .520 RTC_TAMPCR . . . . . . . . . . . . . . . . . . . . . . . 579
LPTIM_IER . . . . . . . . . . . . . . . . . . . . . . . . . . .520 RTC_TR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
LPTIM_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . .519 RTC_TSDR . . . . . . . . . . . . . . . . . . . . . . . . . . 576
LPUART_BRR . . . . . . . . . . . . . . . . . . . . . . . .760 RTC_TSSSR . . . . . . . . . . . . . . . . . . . . . . . . . 577
LPUART_CR1 . . . . . . . . . . . . . . . . . . . . . . . .753 RTC_TSTR . . . . . . . . . . . . . . . . . . . . . . . . . . 575
LPUART_CR2 . . . . . . . . . . . . . . . . . . . . . . . .756 RTC_WPR . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
LPUART_CR3 . . . . . . . . . . . . . . . . . . . . . . . .758 RTC_WUTR . . . . . . . . . . . . . . . . . . . . . . . . . 570
LPUART_ICR . . . . . . . . . . . . . . . . . . . . . . . . .764
LPUART_ISR . . . . . . . . . . . . . . . . . . . . . . . . .761
LPUART_RDR . . . . . . . . . . . . . . . . . . . . . . . .765 S
LPUART_RQR . . . . . . . . . . . . . . . . . . . . . . . .760 SPI_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
LPUART_TDR . . . . . . . . . . . . . . . . . . . . . . . .765 SPI_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
SPI_CRCPR . . . . . . . . . . . . . . . . . . . . . . . . . 813
SPI_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
P
SPI_I2SCFGR . . . . . . . . . . . . . . . . . . . . . . . . 815
PWR_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . .161 SPI_I2SPR . . . . . . . . . . . . . . . . . . . . . . . . . . 816
PWR_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . .164 SPI_RXCRCR . . . . . . . . . . . . . . . . . . . . . . . . 814
SPI_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
R SPI_TXCRCR . . . . . . . . . . . . . . . . . . . . . . . . 814
SYSCFG_CFGR1 . . . . . . . . . . . . . . . . . . . . . 234
RCC_AHBENR . . . . . . . . . . . . . . . . . . . . . . .198 SYSCFG_CFGR2 . . . . . . . . . . . . . . . . . . . . . 235
RCC_AHBRSTR . . . . . . . . . . . . . . . . . . . . . .192 SYSCFG_CFGR3 . . . . . . . . . . . . . . . . . . . . . 236
RCC_AHBSMENR . . . . . . . . . . . . . . . . . . . . .204 SYSCFG_EXTICR1 . . . . . . . . . . . . . . . . . . . 237
RCC_APB1ENR . . . . . . . . . . . . . . . . . . . . . . .201 SYSCFG_EXTICR2 . . . . . . . . . . . . . . . . . . . 238
RCC_APB1RSTR . . . . . . . . . . . . . . . . . . . . .194 SYSCFG_EXTICR3 . . . . . . . . . . . . . . . . . . . 238
RCC_APB1SMENR . . . . . . . . . . . . . . . . . . . .206 SYSCFG_EXTICR4 . . . . . . . . . . . . . . . . . . . 239
RCC_APB2ENR . . . . . . . . . . . . . . . . . . . . . . .199
RCC_APB2RSTR . . . . . . . . . . . . . . . . . . . . .193
RCC_APB2SMENR . . . . . . . . . . . . . . . . . . . .205 T
RCC_CCIPR . . . . . . . . . . . . . . . . . . . . . . . . .208 TIM2_OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
RCC_CFGR . . . . . . . . . . . . . . . . . . . . . . . . . .185 TIM21_OR . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
RCC_CICR . . . . . . . . . . . . . . . . . . . . . . . . . . .190 TIM22_OR . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
RCC_CIER . . . . . . . . . . . . . . . . . . . . . . . . . . .187 TIM3_OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
RCC_CIFR . . . . . . . . . . . . . . . . . . . . . . . . . . .189 TIMx_ARR . . . . . . . . . . . . . . . . . . . 430, 488, 505

RM0377 Rev 10 903/905

Index RM0377

TIMx_CCER . . . . . . . . . . . . . . . . . . . . . .428, 487

TIMx_CCMR1 . . . . . . . . . . . . . . . . . . . .424, 484
TIMx_CCMR2 . . . . . . . . . . . . . . . . . . . . . . . .427
TIMx_CCR1 . . . . . . . . . . . . . . . . . . . . . .431, 489
TIMx_CCR2 . . . . . . . . . . . . . . . . . . . . . .431, 489
TIMx_CCR3 . . . . . . . . . . . . . . . . . . . . . . . . . .432
TIMx_CCR4 . . . . . . . . . . . . . . . . . . . . . . . . . .432
TIMx_CNT . . . . . . . . . . . . . . . . . . 430, 488, 504
TIMx_CR1 . . . . . . . . . . . . . . . . . . 415, 475, 502
TIMx_CR2 . . . . . . . . . . . . . . . . . . 417, 477, 503
TIMx_DCR . . . . . . . . . . . . . . . . . . . . . . . . . . .433
TIMx_DIER . . . . . . . . . . . . . . . . . . 420, 481, 503
TIMx_DMAR . . . . . . . . . . . . . . . . . . . . . . . . . .433
TIMx_EGR . . . . . . . . . . . . . . . . . . 423, 483, 504
TIMx_PSC . . . . . . . . . . . . . . . . . . 430, 488, 505
TIMx_SMCR . . . . . . . . . . . . . . . . . . . . . .418, 478
TIMx_SR . . . . . . . . . . . . . . . . . . . 421, 481, 504

U
USART_BRR . . . . . . . . . . . . . . . . . . . . . . . . .712
USART_CR1 . . . . . . . . . . . . . . . . . . . . . . . . .701
USART_CR2 . . . . . . . . . . . . . . . . . . . . . . . . .704
USART_CR3 . . . . . . . . . . . . . . . . . . . . . . . . .708
USART_GTPR . . . . . . . . . . . . . . . . . . . . . . . .712
USART_ICR . . . . . . . . . . . . . . . . . . . . . . . . . .720
USART_ISR . . . . . . . . . . . . . . . . . . . . . . . . . .715
USART_RDR . . . . . . . . . . . . . . . . . . . . . . . . .722
USART_RQR . . . . . . . . . . . . . . . . . . . . . . . . .714
USART_RTOR . . . . . . . . . . . . . . . . . . . . . . . .713
USART_TDR . . . . . . . . . . . . . . . . . . . . . . . . .722

W
WWDG_CFR . . . . . . . . . . . . . . . . . . . . . . . . .541
WWDG_CR . . . . . . . . . . . . . . . . . . . . . . . . . .540
WWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . .541

904/905 RM0377 Rev 10

RM0377

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RM0377 Rev 10 905/905

905