Palestine Polytechnic University

College of Applied Sciences

Applied Physics and Electronics Department

Class Notes for The Course

Electronics II

Prepared by
Dr. Saleh Al-Takrouri

Based on the book

Electronic Devices (Floyd)

Fall 2011
Course Outline

Add outline here.

i
Contents

Course Outline i

Contents ii

1 Introduction 1
1.1 Section One . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Power Amplifiers 2
2.1 Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Class A Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2.1 DC and AC load lines for common-emitter amplifier . . . . . . 3
2.2.2 Transconductance curve . . . . . . . . . . . . . . . . . . . . . 4
2.2.3 Power and efficiency . . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Class B and Class AB Push-Pull Amplifiers . . . . . . . . . . . . . . 5
2.3.1 Class B amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3.2 Class AB push-pull amplifier . . . . . . . . . . . . . . . . . . . 6
2.3.3 DC and AC analysis . . . . . . . . . . . . . . . . . . . . . . . 6
2.3.4 Power and efficiency . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Class C Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Field-Effect Transistors and Biasing 8

3.1 The Junction Field-Effect Transistor (JFET) . . . . . . . . . . . . . . 8
3.2 JFET Characteristics and Parameters . . . . . . . . . . . . . . . . . . 9
3.2.1 JFET transfer characteristics . . . . . . . . . . . . . . . . . . 9
3.2.2 JFET forward transconductance . . . . . . . . . . . . . . . . . 10
3.2.3 Input resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3 JFET Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3.1 Self bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3.2 Voltage divider bias . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.3 Q-point stability . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) . . . 12
3.4.1 D-MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4.2 E-MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

ii
CONTENTS iii

3.4.3 Power MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5 MOSFET Characteristics and Parameters . . . . . . . . . . . . . . . 14
3.6 MOSFET Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6.1 D-MOSFET Bias . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6.2 E-MOSFET Bias . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Small Signal FET Amplifiers 16

4.1 FET Amplifier Operation . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 FET Amplification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2.1 Voltage gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3 Common Source Amplifiers . . . . . . . . . . . . . . . . . . . . . . . 17
4.3.1 Common source (CS) JFET amplifier . . . . . . . . . . . . . . 17
4.3.2 Common source (CS) MOSFET amplifier . . . . . . . . . . . . 18
4.4 Common Drain Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . 19
4.5 Common Gate Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . 19

5 Amplifier Frequency Response 20

5.1 General Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2 The Decibel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.1 0dB Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2.2 The critical frequency . . . . . . . . . . . . . . . . . . . . . . 22
5.3 Low Frequency Amplifier Response . . . . . . . . . . . . . . . . . . . 22
Chapter 1

Introduction

1.1 Section One

1
Chapter 2

Power Amplifiers

2.1 Power Amplifiers

Power amplifiers are large-signal amplifiers that generally use larger portion of the
load line during signal operation than small-signal amplifiers.
A power amplifier can be:

• common-emitter (inverting)

• common-collector

• common-base

Four classes of power amplifiers will be considered emphasizing power amplification:

1. Class A amplifier: an amplifier that operates entirely in the linear region of

the transistor’s characteristic curves. The transistor conducts during the full
360◦ of the input cycle.
Note: the small-signal amplifiers in the previous chapter are class A amplifiers.

2. Class B amplifier: an amplifier that operates in the linear region for 180◦ of
the input cycle and is in cutoff for the other 180◦ of the input cycle.

3. Class AB amplifier: an amplifier that is biased slightly above cutoff and

operates in the linear region for slightly more than 180◦ of the input cycle.

4. Class C amplifier: an amplifier that operates in the linear region for only a
small part of the input cycle.

2.2 Class A Amplifiers

• Class A amplifiers operate in the linear region for the full 360◦ of the input
cycle.

2
2.2 Class A Amplifiers 3

• Maximum class A signal can be obtained when the Q-point is at the center of
the AC load line.

• If the input signal is too large, the amplifier is driven into cutoff and saturation.

• If the Q-point is not centered, then Vce is limited by cutoff or saturation (the
one closer to the Q-point).

2.2.1 DC and AC load lines for common-emitter amplifier

DC load line :
At saturation VCE ≈ 0
VCC
⇒ IC(sat) =
RC + RE
At cutoff IC ≈ 0
⇒ VCE(cutof f ) = VCC

AC load line : Q-point coordinates obtained from DC analysis: VCEQ , ICQ .

From Q-point to saturation:
∆VCE = VCEQ − 0 = VCEQ
V
∆IC = R∆V CE
C kRL
= RCCEQ
kRL

VCEQ
⇒ Ic(sat) = ICQ +
RC k RL
From Q-point to cutoff:
∆IC = ICQ − 0 = ICQ
∆VCE = ∆IC (RC k RL ) = ICQ (RC k RL )

⇒ Vce(cutof f ) = VCEQ + ICQ (RC k RL )

Condition for centering the Q-point on the AC load line :

At center:
V V +I (RC kRL )
VCEQ = ce(cutof
2
f)
= CEQ CQ2
V
Ic(sat) ICQ + R CEQ
kR
or ICQ = 2
= 2
C L

⇒ VCEQ = ICQ (RC k RL )

If the Q-point is not centered :

change the value of RE to get a new Q-point at the center.
VCC = ICQ RC + VCEQ + ICQ RE
ICQ RE = VCC − VCEQ − ICQ RC
VCC − VCEQ
⇒ RE = − RC
ICQ
2.2 Class A Amplifiers 4

Example: Draw the DC and AC load lines for the CE amplifier given: VCC =
10V , R1 = 10kΩ, R2 = 4.7kΩ, RC = 1kΩ, RE = 470Ω, RL = 1.5kΩ, βac = 200. If
the Q-point is not at the center, change the value of RE to center the Q-point.
Solution:

2.2.2 Transconductance curve

• When the collector current swings over a large portion of the curve, distortion
occurs because of the nonlinearity.

• The distortion is reduced by keeping a higher Q-point (on the more linear
part).

• re0 = ∆V BE
∆IC
non-linear curve ⇒ re0 6= 25mV
IE

RC kRL
• Voltage gain (CE): same as small signal case Av = re0

• Current gain: assume Ai ≈ βDC

• Power gain: Ap = Av Ai = βDC RCrkR

0
L
e

2.2.3 Power and efficiency

Quiescent power : The power dissipation of a transistor with no signal input (at
Q-point)
PDQ = ICQ VCEQ
Quiescent power is the maximum power that the class A transistor must han-
dle; therefore its power rating should exceed this value.

Output power (CE) : Pout = Vce Ic (rms values)

1. Q-point closer to saturation:

Peak values: Vce = VCEQ , Ic = VCEQ /(RC k RL )
2
1 1 VCEQ VCEQ
⇒ Pout = ( √ VCEQ )( √ )=
2 2 (RC k RL ) 2(RC k RL )

2. Q-point closer to cutoff:

Peak values: Vce = ICQ (RC k RL ), Ic = ICQ

1 1 1 2
⇒ Pout = ( √ ICQ (RC k RL ))( √ ICQ ) = ICQ (RC k RL )
2 2 2
2.3 Class B and Class AB Push-Pull Amplifiers 5

3. Q-point at the center:

Peak values: Vce = VCEQ , Ic = ICQ

1 1 1
⇒ Pout = ( √ VCEQ )( √ ICQ ) = VCEQ ICQ
2 2 2

(maximum AC output power from class A amplifiers)

Efficiency (η) :
The ratio of AC output power to DC input power.

• DC input power PDC = VCC ICC

• Average ICC = ICQ
• When Q-point is at the center of the AC load line, at least VCC = 2VCEQ
1 1
Pout V I
2 CEQ CQ
VCEQ ICQ 1
⇒ ηmax = = = 2 = = 0.25
Pin VCC ICC 2VCEQ ICQ 4
⇒ ηmax = 25% centered Q − point

Maximum load power (Q-point centered)

Peak values: VL = VCEQ , IL = VCEQ /RL
2
1 1 VCEQ VCEQ
⇒ PL = ( √ VCEQ )( √ )=
2 2 RL 2RL

Example: Given a CE amplifier with: VCC = 24V , RC = 330Ω, RE = 100Ω,

R1 = 4.7kΩ, R2 = 1kΩ, RL = 330Ω, βDC = 150. Find: (a) Minimum power rating,
(b) AC output power, (c) efficiency, (d) maximum load power. Solution:

2.3 Class B and Class AB Push-Pull Amplifiers

2.3.1 Class B amplifier
• The class B amplifier is biased at cutoff point.

⇒ ICQ = 0, VCEQ = VCE(cutof f )

• It operates in the linear region for 180◦ of input cycle and is in cutoff for 180◦ .
The output is not a replica of the input.

Push-Pull class B operation (CC)

This amplifier is called complementary amplifier because one CC uses npn
transistor and the other CC uses a matching pnp transistor.
2.3 Class B and Class AB Push-Pull Amplifiers 6

2.3.2 Class AB push-pull amplifier

• To eliminate the crossover distortion, both transistors must be biased slightly
above cutoff when there is no signal.

• Diode bias is used for thermal stabilization.

• R1 = R2 , D1 and D2 are identical, Q1 and Q2 are complimentary pair.

• Dual-polarity VCC is eliminated when RL is capacitively coupled.

2.3.3 DC and AC analysis

DC analysis : R1 = R2 ⇒ VA = 12 VCC
(Q1 ) : VD1 = VBE (Q2 ) : VD2 = VBE

VCC
⇒ VE = (Q1 & Q2 )
2
Q-point:
VCC
VCEQ1 = VCEQ2 = ICQ ≈ 0 (near cutoff)
2
AC analysis : Maximum signal:

• Positive half-cycle (Q1 ): VE changes from 21 VCC to VCC

• Negative half-cycle (Q2 ): VE changes from 12 VCC to 0

⇒ Vce changes from 12 VCC to 0 for Q1 and Q2 .

V
Peak voltage = VCEQ , ⇒ Ic(sat) = CEQRL
VCEQ
Output current =Ie ≈ Ic , ⇒ Iout(peak) = RL

2.3.4 Power and efficiency

Maximum output power :

Pout = Vout(rms) Iout(rms)

= √12 Vout(peak) √12 Iout(peak)
= 12 VCEQ Ic(sat)
= 14 VCC Ic(sat) ≈ 81 VRCC
L

DC input power :
Ic(sat)
Average of half-wave signal: ICC = π

VCC Ic(sat)
PDC = VCC ICC =
π
2.4 Class C Amplifiers 7

Efficiency :
Pout 0.25VCC Ic(sat) π
ηmax = = =
PDC VCC Ic(sat) /π 4
⇒ ηmax = 0.79 = 79%
(Advantage over class A amplifier’s 25%)

Input resistance (CC):

Rin = βac (re0 + RE )
For push-pull configuration RE = RL

Rin = βac (re0 + RL )

Example: For the class AB push-pull amplifier shown in the figure, given
VD1 = VD2 = VBE = 0.7V . Find (a) VB , VE , VC EQ, (b) the maximum ideal
peak values for Vout and Iout and the maximum Pout (c) ηmax and the input resis-
tance (βac = 50, re0 = 6Ω) Solution:

2.4 Class C Amplifiers

• A CE class C amplifier is biased below cutoff with −VBB supply. The AC
source voltage should have a peak value grater than VBB + VBE .

• The base voltage exceeds the barrier potential of the base-emitter junction for
a short time near the positive peak.

2.4.1 Power dissipation

• Class C amplifiers have low power dissipation (amplifier is on for a small
percentage of the input cycle). maximum collector current = Ic(sat) , minimum
collector voltage = Vce(sat) .

• Power dissipation during ”on” time: PD(on) = Vce(sat) Ic(sat) . assuming 100% of
the load line is used:
 
ton ton
PD(average) = PD(on) = Vce(sat) Ic(sat)
T T

Example: A class C amplifier is driven by a 200kHz signal. The transistor is on

for 1µs, and the amplifier is operating over 100% of its load line. If Ic(sat) = 100mA
and VCE(sat) = 0.2V , find the average power dissipation. Solution:
Chapter 3

Field-Effect Transistors and

Biasing

• Field-effect transistors (FET) are unipolar devices because they operate only
with one type of charge carriers.

• There are two main types of FETs:

1. Junction Field-Effect Transistor (JFET)

2. Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)

• A FET is a voltage controlled device.

3.1 The Junction Field-Effect Transistor (JFET)

1. The JFET is always operated with the gate-source junction reverse-biased.

2. VGG sets the reverse-bias voltage between G and S.

3. VDD provides D to S voltage and supplies current from D to S (n-channel) or

from S to D (p-channel).

4. Basic operation (n-channel)

• Reverse-biasing the G-S junction produces a depletion region along the

junction.
• The depletion region extends into the channel, and increases its resistance
by restricting the channel width.
• The voltage VGG controls the channel width and the current ID .
• A greater (-ve) VGG narrows the channel and decreases ID .
• A less (-ve) VGG widens the channel and increases ID .

8
3.2 JFET Characteristics and Parameters 9

3.2 JFET Characteristics and Parameters

• In the ohmic region: As VDD increases (and thus VDC increases) from zero, ID
increases proportionally through the n-channel.

• Pinch-off voltage (Vp ): the value of VDS at which ID becomes constant.

• IDSS : the maximum drain current that JFET can produce when VGS = 0.

• In the constant-current region, reverse-bias voltage VGD produces a depletion

region large enough to offset the increase in VDS and keep ID relatively con-
stant.

• At breakdown, ID increases rapidly and JFET is damaged.

• JFET is always operated below breakdown and within constant-current region.

• VGS controls ID : As VGS is increased to more negative values:

– Pinch-off occurs at a lower VDS than Vp .

– ID decreases.

• Cutoff voltage (VGS(of f ) ):

– Cutoff voltage: the value of VGS that makes ID ≈ 0

– At VGS(of f ) the JFET channel is completely closed.
– VGS(of f ) = −Vp

Example: Given VGS(of f ) = −4V and IDSS = 12mA, find the minimum VDD to
put JFET in the constant-current region.
Solution:

3.2.1 JFET transfer characteristics

The curve (VGS , ID ) is nearly parabolic
 2
VGS
ID = IDSS 1 −
VGS(of f )

ID = 0 when VGS = VGS(of f )

ID = IDSS when VGS = 0
⇒ JFET and MOSFET are square-law devices.
3.3 JFET Biasing 10

3.2.2 JFET forward transconductance

∆ID
gm =
∆VGS
gm = gf s = yf s
∆ID1 ∆ID2
gm1 = ∆V GS1
, gm2 = ∆VGS2
gm1 < gm2 ⇒ non-linear curve
2IDSS
gm0 = gm |VGS =0 =
|VGS(of f ) |
 
VGS
gm ≈ gm0 1 −
VGS(of f )

3.2.3 Input resistance

• JFET input resistance at gate is very high (VGS is reverse biased).

• Datasheets specify the gate reverse current IGSS at certain VGS .

VGS
⇒ RIN =
IGSS

• IGSS increases with temperature.

• Drain to source resistance: (on drain characteristic curve)

0 ∆VDS
rds =
∆ID

3.3 JFET Biasing

3.3.1 Self bias
• RG does not affect the bias.

• VG = 0

• IS = ID (in all FETs)

• VGS = VG − VS = 0 − VS

n-channel : VGS = −ID RS

p-channel : VGS = +ID RS

• VD = VDD − ID RD
VDS = VD − VS = VDD − ID (RD + RS )
3.3 JFET Biasing 11

Example: Given ID = 5mA. Find VDS , VGS

Solution:

Setting the Q-point of self biased JFET

• For a desired VGS , find ID .

• For a desired ID , find VGS .
• The values are found from
1. the transfer characteristic curve,
2. equation ID = IDSS (1 − VGS /VGS(of f ) )2
VGS
• Calculate the required RS = ID

Example: Given the transfer characteristic curve in the figure, find RS for self
biased n-channel JFET at VGS = −5V .
Solution:

Example: For a self-biased p channel JFET, IDSS = 25mA and VGS(of f ) = 15V .
Find RS at VGS = 5V .
Solution:

Setting the Q-point of self biased JFET at midpoint

ID = 21 IDSS , VD = 21 VDD .
ID swings from 0 to IDSS , VD swings from VDD to 0.
1
ID = IDSS ⇒ VGS = 0.293VGS(of f )
2
to verify
 2
VGS
ID = IDSS 1 − = IDSS (1 − 0.293)2 = 0.5IDSS
VGS(of f )
1
VD = VDD = VDD − ID RD
2
VD D VD D
⇒ RD = =
2ID IDSS
Choose RG to be large.
Example: Given IDSS = 15mA, VGS(of f ) = −8V , VDD = +12V , choose RD and
RS for midpoint bias.
Solution:
3.4 Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) 12

Graphical analysis of self biased JFET (Example)

At ID = 0, VGS = −ID RS = 0
At ID = IDSS , VGS = −ID RS = −4mA × 680Ω = −2.72V
Q-point: ID = 2.25mA, VGS = −1.5V

3.3.2 Voltage divider bias

(n-channel JFET with voltage divider)

VS > VG

VS = ID RS = VG − VGS
R1
VG = VDD
R1 + R2
VG − VGS
ID =
RS
Example: For a voltage divider bias circuit with R1 = 6.8M Ω, R2 = 1M Ω,
RD = 3.3kΩ, RS = 1.8kΩ, VDD = 12V . Find ID and VGS when VD = 7V
Solution:

Graphical analysis of voltage divider biased JFET (Example)

At ID = 0, VGS = VG = R1R+R
1
2
VDD = 6.8M6.8M Ω
Ω+3.3kΩ
× 8V = 4V
VG −VGS VG 4V
At VGS = 0, ID = RS = RS = 3.3kΩ = 1.2mA

3.3.3 Q-point stability

• The transfer characteristic curve of JFET differs considerably from one device
to another of the same device.

• ID is more stable with voltage divider bias than self bias.

• VGS varies for both bias methods.

3.4 Metal Oxide Semiconductor Field-Effect Tran-

sistor (MOSFET)
• MOSFET gate is insulated by a silicon dioxide (SiO2 ) layer.

• There are two types of MOSFET: depletion (D) and enhancement (E).

• MOSFET is also called Isolated Gate Field-Effect Transistor (IGFET).

3.4 Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) 13

3.4.1 D-MOSFET
• VGS = −ve:

– n-channel: depletion mode

– p-channel: enhancement mode

• VGS = +ve:

– n-channel: enhancement mode

– p-channel: depletion mode
– D-MOSFET are usually operated in depletion mode.

Depletion Mode :

• The gate/channel act as a capacitor.

• The negative charges on the gate repel electrons in the n-channel, leaving
positive charges.
• The n-channel is depleted of some electrons, decreasing its conductivity.
• At VGS(of f ) (negative voltage), the channel is totally depleted and ID = 0.

Enhancement Mode :

• The positive charges on the gate attract electrons into the n-channel,
increasing the conductivity in the channel.
• VGS is positive.

D-MOSFET Symbol :

3.4.2 E-MOSFET
• E-MOSFET is operated only in enhancement mode.

• There is no structural channel.

• The positive VGS above a threshold value induces a channel by creating a thin
layer of negative charges.

• Greater positive VGS pulls more electrons into the channel, enhancing its con-
ductivity.

• For any VGS below the threshold value, there is no induced channel.

• E-MOSFET symbol:
3.5 MOSFET Characteristics and Parameters 14

3.4.3 Power MOSFET

• Conventional E-MOSFET has a long thin channel ⇒ relatively high drain-
to-source resistance.

• Power E-MOSFET:

– Lateral Double Diffusion (LDMOSFET)

– V-groove (VMOSFET)
– TMOSFET

3.5 MOSFET Characteristics and Parameters

D-MOSFET transfer characteristic curve :
 2
VGS
ID = IDSS 1 −
VGS(of f )

E-MOSFET transfer characteristic curve :

2
ID = K VGS − VGS(th)

K: constant
From Datasheet: ID(on) at VGS

ID(on)
⇒ K=
(VGS − VGS(th) )2

3.6 MOSFET Bias

3.6.1 D-MOSFET Bias
Zero bias :

DC analysis:
VGS = 0 ⇒ ID = IDSS
VDS = VDD − IDSS RD
RG is used to isolate the AC input from ground.
3.6 MOSFET Bias 15

3.6.2 E-MOSFET Bias

VGS > VGS(th)

Voltage divider bias :

R2
VGS = VDD
R1 + R2
VDS = VDD − ID RD

2
ID = K VGS − VGS(th)

Drain feedback bias :

IG ≈ 0 ⇒ VGS = VDS
VDD − VGS
ID =
RD
Chapter 4

Small Signal FET Amplifiers

4.1 FET Amplifier Operation

JFET Amplifier

MOSFET Amplifier

4.2 FET Amplification

• Transconductance gm
 
∆ID VGS
gm = = gm0 1 −
∆VGS VGS(of f )

2IDSS
gm0 =
|VGS(of f ) |

• In AC quantities
Id
gm = ⇒ Id = gm Vgs
Vgs

• Equivalent circuit

4.2.1 Voltage gain

Ideal :
Vout = Vds , Vin = Vgs
Id = gm Vgs
Vout Vds Id Rd
Av = = = = gm Rd
Vin Vgs Id /gm

16
4.3 Common Source Amplifiers 17

0 0
Effect of rds : rds is in parallel with Rd
0
 
Rd rds
Av = gm 0
Rd + rds

Effect of RS :
Vin = Vgs + Id RS
Vout Id Rd gm Vgs Rd gm Rd
Av = = = =
Vin Vgs + Id RS Vgs + gm Vgs RS 1 + gm RS

4.3 Common Source Amplifiers

4.3.1 Common source (CS) JFET amplifier
DC equivalent circuit:
 2
ID RS
ID = IDSS 1−
VGS(of f )
VS = −VGS = ID RS
VD = VDD − ID RD
VDS = VD − VS
AC equivalent circuit:
Vgs = Vin
Vds = Vout
Rd = RD k RL
Av = gm Rd
Vout = gm Rd Vin , (rms)
The AC load RL reduces the unloaded voltage gain.

Rd < RD , RL

Phase inversion : the voltage gain is −Av .

Input resistance :

• ideally = inf
• produced by the reverse biased pn-junction
• at a specific VGS , IGSS is given in the datasheet (IGSS : reverse leakage
current)
 
• ⇒ Ri n = RG k IVGSS GS
4.3 Common Source Amplifiers 18

Example: From the datasheet: IDSS = 8mA, VGS(of f ) = −10V , IGSS =

30nA @ VGS = 10V
(a) Find the unloaded voltage output.
(b) Find the loaded voltage output.
(c) Find the input resistance as seen by the signal source.
Solution:

4.3.2 Common source (CS) MOSFET amplifier

D-MOSFET (zero bias)
DC analysis:
VGS = 0 ⇒ ID = IDSS
VD = VDD − ID RD
AC analysis:
Rd = RD k RL
Av = gm Rd
Vout = gm Rd Vin , (rms)
Example: For the amplifier shown in the figure, given IDSS = 12mA, gm =
3.2mS, Vin = 500mV (rms). Find VD and Vout .
Solution:

E-MOSFET (voltage divider bias)

DC analysis:
R2
VGS = VG = VDD
R1 + R2

2
ID = K VGS − VGS(th)
VDS = VD = VDD − ID RD
AC analysis:
Rd = RD k RL
Av = gm Rd
Vout = gm Rd Vin , (rms)
VGS |IGSS
RIN (gate) =
IGSS
Rin = R1 k R2 k RIN (gate)
Example: For the amplifier shown in the figure, given ID(on) = 5mA @ VGS =
10V , VGS(th) = 4V , gm = 5.5mS, Vin = 50mV (rms). Find VGS , ID , VDS and Vout .
Solution:
4.4 Common Drain Amplifiers 19

4.4 Common Drain Amplifiers

Common drain (CD) JFET amplifier (source follower)

Input: gate
Output: source
AC ground: drain
Self biased

Vout = Id (RS k RL )
Vin = Vgs + Id (RS k RL )
Id = gm Vgs
Vout gm (RS k RL )
Av = = ≈1
Vin 1 + gm (RS k RL )
VGS |IGSS
RIN (gate) =
IGSS
Rin = RG k RIN (gate)

4.5 Common Gate Amplifiers

Common gate (CG) JFET amplifier

Input: source
Output: drain
AC ground: gate
Self biased

Note: Low input resistance.

Rd = RD k RL
Vin = Vgs
Iin = Is = Id = gm Vgs
Vout Vd Id Rd gm Vgs Rd
Av = = = =− = −gm Rd
Vin Vs −Vgs Vgs
Vin Vgs 1
Rin(source) = = =
Iin gm Vgs gm
Rin = Rin(source) k RS
Chapter 5

Amplifier Frequency Response

5.1 General Concepts

• The capacitive reactance of the coupling and bypass capacitors was assumed
to be 0Ω.

• The internal transistor capacitances were assumed to be small and neglected.

• Frequency response of an amplifier: the change in gain or phase shift over a

specified range of input signal frequencies.

Effect of coupling capacitors :

1
XC =
2πf C

At lower frequencies (e.g. below 10Hz), capacitively coupled amplifiers

• have less voltage gain than at higher frequencies,

• the output voltage leads the input voltage.

Effect of bypass capacitors : At lower frequencies, XC  0Ω. For CE ampli-

fiers:
RC k RL
Av = 0
re + Ze
Effect of internal transistor capacitances :

• As frequency increases, the internal capacitances reduce the gain and

introduce phase shift.
• At lower frequencies, the internal capacitances have very high reactance
values and can be considered as open circuits.

20
5.2 The Decibel 21

5.2 The Decibel

A measurement of the ration of one power to another, or one voltage to another.

Power gain (dB):

Pout
Ap(dB) = 10 log Ap , Ap =
Pin
Voltage gain (dB):
Vout
Av(dB) = 20 log Av , Av =
Vin
Av > 1 ⇒ Av(dB) > 0
Av < 1 ⇒ Av(dB) < 0 (attenuation)

log x = y ⇔ 10y = x
Examples:
log 100 = 2 102 = 100
log 1 = 0 100 = 1
log 0.1 = −1 10−1 = 0.1
Av = 1200 → Av(dB) = 61.6
Ap = 50 → Ap(dB) = 17

5.2.1 0dB Reference

• In amplifier analysis, a certain value of gain is usually assigned as the 0dB
reference (gain values are normalized by dividing the values by the reference
gain).

• The actual reference voltage gain is not necessarily 1 (which is 0dB).

• The reference gain regardless of its value is assigned 0dB and is used for
comparison with other values of gain.

• Midrange gain: the maximum gain exhibited by an amplifier over a certain

range of frequencies. For frequencies above and below this range the gain is
reduced.

• The midrange gain is selected as reference (0dB) and any lower gain is ex-
pressed as negative dB value.

Voltage gain Av dB [20 log Av ]

32 30 dB
16 24 dB
8 18 dB
4 12 dB
5.3 Low Frequency Amplifier Response 22

2
√ 6 dB
2 3 dB
1 0 dB
√1 −3 dB
2
1
2
−6 dB
1
4
−12 dB
1
8
−18 dB
1
16
−24 dB
1
32
−30 dB

5.2.2 The critical frequency

(cutoff frequency, corner frequency): the frequency at which the output power drops
to one-half of its midrange value.

Ap(dB) = 10 log(0.5) = −3dB

1
Av(dB) = 20 log( √ ) = −3dB
2
Example: An amplifier has a midrange rms output voltage of 10V . Find the
rms output voltage for each of the following dB gain reductions with a constant rms
input voltage.
(a) −3dB, (b) −6dB, (c) −12dB, (a) −24dB
Solution:

5.3 Low Frequency Amplifier Response