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Chapter 2 – Netlist and System Partitioning

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning

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 Chapter 2 – Netlist and System Partitioning

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2.1 Introduction
2.2 Terminology
2.3 Optimization Goals
2.4 Partitioning Algorithms
2.4.1 Kernighan-Lin (KL) Algorithm
2.4.2 Extensions of the Kernighan-Lin Algorithm
2.4.3 Fiduccia-Mattheyses (FM) Algorithm
2.5 Framework for Multilevel Partitioning
2.5.1 Clustering
2.5.2 Multilevel Partitioning
2.6 System Partitioning onto Multiple FPGAs

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 2

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 2.1 Introduction

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System Specification

Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design Chip Planning
and Logic Design

Circuit Design Placement

Physical Design
Clock Tree Synthesis

Physical Verification
DRC and Signoff
LVS Signal Routing
ERC
Fabrication

Timing Closure

© 2022 Springer Verlag

Packaging and Testing

Chip

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 3

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 2.1 Introduction

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Circuit: 1 Cut cb
3
2
7 8
4
6
5
Cut ca

Block A Block B Block A Block B

8 3 4 1 8 5 4 1

7 6 5 2 7 6 3 2

© 2022 Springer Verlag

Cut ca: four external connections Cut cb: two external connections

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 4

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 2.2 Terminology

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Block (Partition) Graph G1: Nodes 3, 4, 5.

4 4
1 1
5 6 3 5 6
3
2 2

Cells
Graph G2: Nodes 1, 2, 6.

Collection of cut edges

Cut set: (1,3), (2,3), (5,6),

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 5

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 2.3 Optimization Goals

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• Given a graph G(V,E) with |V| nodes and |E| edges where each node v ∈ V
and each edge e ∈ E.

• Each node has area s(v) and each edge has cost or weight w(e).

• The objective is to divide the graph G into k disjoint subgraphs such that all
optimization goals are achieved and all original edge relations are respected.

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 2.3 Optimization Goals

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• In detail, what are the optimization goals?
− Number of connections between partitions is minimized
− Each partition meets all design constraints (size, number of external connections..)
− Balance every partition as well as possible

• How can we meet these goals?

− Unfortunately, this problem is NP-hard
− Efficient heuristics are developed in the 1970s and 1980s.
They are high quality and in low-order polynomial time.

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 7

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 Chapter 2 – Netlist and System Partitioning

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2.1 Introduction
2.2 Terminology
2.3 Optimization Goals
2.4 Partitioning Algorithms
2.4.1 Kernighan-Lin (KL) Algorithm
2.4.2 Extensions of the Kernighan-Lin Algorithm
2.4.3 Fiduccia-Mattheyses (FM) Algorithm
2.5 Framework for Multilevel Partitioning
2.5.1 Clustering
2.5.2 Multilevel Partitioning
2.6 System Partitioning onto Multiple FPGAs

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 2.4.1 Kernighan-Lin (KL) Algorithm

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Given: A graph with 2n nodes where each node has the same weight.
Goal: A partition (division) of the graph into two disjoint subsets A and B with
minimum cut cost and |A| = |B| = n.

Example: n = 4 1 5

2 6
Block A Block B
3 7

4 8

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 2.4.1 Kernighan-Lin (KL) Algorithm – Terminology

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Cost D(v) of moving a node v 1 5

D(v) = |Ec(v)| – |Enc(v)| , 2 6

where 3 7
Ec(v) is the set of v’s incident edges that are cut by the Node 3:
cut line, and D(3) = 3-1=2 4 8
Enc(v) is the set of v’s incident edges that are not cut by
the cut line.

Node 7:
High costs (D > 0) indicate that the node
should move, while low costs (D < 0) indicate D(7) = 2-1=1
that the node should stay within the same
partition.

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Gain of swapping a pair of nodes a und b 1 5

∆g = D(a) + D(b) - 2* c(a,b), 2 6

where 3 7
• D(a), D(b) are the respective costs of nodes a, b
• c(a,b) is the connection weight between a and b: 4 8
If an edge exists between a and b,
then c(a,b) = edge weight (here 1),
otherwise, c(a,b) = 0.

The gain ∆g indicates how useful the swap between two

nodes will be

The larger ∆g, the more the total cut cost will be reduced

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 2.4.1 Kernighan-Lin (KL) Algorithm – Terminology

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Node 7:
Gain of swapping a pair of nodes a und b D(7) = 2-1=1 1 5

∆g = D(a) + D(b) - 2* c(a,b), 2 6

where 3 7
• D(a), D(b) are the respective costs of nodes a, b Node 3:
• c(a,b) is the connection weight between a and b: D(3) = 3-1=2 4 8
If an edge exists between a and b,
then c(a,b) = edge weight (here 1),
otherwise, c(a,b) = 0.
1 5

∆g (3,7) = D(3) + D(7) - 2* c(a,b) = 2 + 1 – 2 = 1

2 6

=> Swapping nodes 3 and 7 would reduce the cut size by 1

3 7

4 8

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Node 5:
Gain of swapping a pair of nodes a und b D(5) = 2-1=1 1 5

∆g = D(a) + D(b) - 2* c(a,b), 2 6

where 3 7
• D(a), D(b) are the respective costs of nodes a, b Node 3:
• c(a,b) is the connection weight between a and b: D(3) = 3-1=2 4 8
If an edge exists between a and b,
then c(a,b) = edge weight (here 1),
otherwise, c(a,b) = 0.
1 5

∆g (3,5) = D(3) + D(5) - 2* c(a,b) = 2 + 1 – 0 = 3

2 6

=> Swapping nodes 3 and 5 would reduce the cut size by 3

3 7

4 8

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 2.4.1 Kernighan-Lin (KL) Algorithm – Terminology

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Gain of swapping a pair of nodes a und b

The goal is to find a pair of nodes a and b to exchange such that ∆g is

maximized and swap them.

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 2.4.1 Kernighan-Lin (KL) Algorithm – Terminology

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Maximum positive gain Gm of a pass

The maximum positive gain Gm corresponds to the best prefix of m swaps

within the swap sequence of a given pass.

These m swaps lead to the partition with the minimum cut cost
encountered during the pass.

Gm is computed as the sum of Δg values over the first m swaps of the

pass, with m chosen such that Gm is maximized.

m
Gm = ∑ ∆g
i =1
i

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 2.4.1 Kernighan-Lin (KL) Algorithm – One pass

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Step 0:
– V = 2n nodes
– {A, B} is an initial arbitrary partitioning
Step 1:
– i=1
– Compute D(v) for all nodes v∈V
Step 2:
– Choose ai and bi such that ∆gi = D(ai) + D(bi) – 2 * c(aibi) is maximized
– Swap and fix ai and bi
Step 3:
– If all nodes are fixed, go to Step 4. Otherwise
– Compute and update D values for all nodes that are connected to ai and bi and are not fixed.
– i=i+1
– Go to Step 2
Step 4:
– ∑
m
Find the move sequence 1...m (1 ≤ m ≤ i), such that Gm =
i =1
Δg i is maximized
– If Gm > 0, go to Step 5. Otherwise, END
Step 5:
– Execute m swaps, reset remaining nodes
– Go to Step 1

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 16

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 2.4.1 Kernighan-Lin (KL) Algorithm – Example

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1 5

2 6

3 7

4 8

Cut cost: 9
Not fixed:
1,2,3,4,5,6,7,8

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1 5

2 6

3 7

4 8

Cut cost: 9
Not fixed:
1,2,3,4,5,6,7,8

Costs D(v) of each node:

D(1) = 1 D(5) = 1
D(2) = 1 D(6) = 2 Nodes that lead to
D(3) = 2 D(7) = 1 maximum gain
D(4) = 1 D(8) = 1

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 18

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 2.4.1 Kernighan-Lin (KL) Algorithm – Example

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1 5

2 6

3 7

4 8

Cut cost: 9
Not fixed:
1,2,3,4,5,6,7,8

Costs D(v) of each node:

D(1) = 1 D(5) = 1
D(2) = 1 D(6) = 2 Nodes that lead to
D(3) = 2 D(7) = 1 maximum gain
D(4) = 1 D(8) = 1

∆g1 = 2+1-0 = 3 Gain after node swapping

Swap (3,5)
G1 = ∆g1 =3 Gain in the current pass

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 2.4.1 Kernighan-Lin (KL) Algorithm – Example

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1 5 1 5

2 6 2 6

3 7 3 7

4 8 4 8

Cut cost: 9
Not fixed:
1,2,3,4,5,6,7,8

D(1) = 1 D(5) = 1
D(2) = 1 D(6) = 2 Nodes that lead to
D(3) = 2 D(7) = 1 maximum gain
D(4) = 1 D(8) = 1

∆g1 = 2+1-0 = 3 Gain after node swapping

Swap (3,5)
G1 = ∆g1 =3 Gain in the current pass

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 2.4.1 Kernighan-Lin (KL) Algorithm – Example

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1 5 1 5

2 6 2 6

3 7 3 7

4 8 4 8

Cut cost: 9 Cut cost: 6

Not fixed: Not fixed:
1,2,3,4,5,6,7,8 1,2,4,6,7,8

D(1) = 1 D(5) = 1
D(2) = 1 D(6) = 2
D(3) = 2 D(7) = 1
D(4) = 1 D(8) = 1

∆g1 = 2+1-0 = 3
Swap (3,5)
G1 = ∆g1 =3

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 2.4.1 Kernighan-Lin (KL) Algorithm – Example

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1 5 1 5

2 6 2 6

3 7 3 7

4 8 4 8

Cut cost: 9 Cut cost: 6

Not fixed: Not fixed:
1,2,3,4,5,6,7,8 1,2,4,6,7,8

D(1) = 1 D(5) = 1 D(1) = -1 D(6) = 2

D(2) = 1 D(6) = 2 D(2) = -1 D(7)=-1
D(3) = 2 D(7) = 1 D(4) = 3 D(8)=-1
D(4) = 1 D(8) = 1

∆g1 = 2+1-0 = 3
Swap (3,5)
G1 = ∆g1 =3

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 22

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 2.4.1 Kernighan-Lin (KL) Algorithm – Example

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1 5 1 5 1 5

2 6 2 6 2 6

3 7 3 7 3 7

4 8 4 8 4 8

Cut cost: 9 Cut cost: 6

Not fixed: Not fixed:
1,2,3,4,5,6,7,8 1,2,4,6,7,8

D(1) = 1 D(5) = 1 D(1) = -1 D(6) = 2

D(2) = 1 D(6) = 2 D(2) = -1 D(7)=-1 Nodes that lead to
D(3) = 2 D(7) = 1 D(4) = 3 D(8)=-1 maximum gain
D(4) = 1 D(8) = 1

∆g1 = 2+1-0 = 3 ∆g2 = 3+2-0 = 5 Gain after node swapping

Swap (3,5) Swap (4,6)
G1 = ∆g1 =3 G2 = G1+∆g2 =8 Gain in the current pass

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 2.4.1 Kernighan-Lin (KL) Algorithm – Example

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1 5 1 5 1 5 1 5

2 6 2 6 2 6 2 6

3 7 3 7 3 7 3 7

4 8 4 8 4 8 4 8

Cut cost: 9 Cut cost: 6 Cut cost: 1 Cut cost: 7

Not fixed: Not fixed: Not fixed: Not fixed:
1,2,3,4,5,6,7,8 1,2,4,6,7,8 1,2,7,8 2,8

D(1) = 1 D(5) = 1 D(1) = -1 D(6) = 2 D(1) = -3 D(7)=-3

D(2) = 1 D(6) = 2 D(2) = -1 D(7)=-1 D(2) = -3 D(8)=-3 Nodes that lead to
D(3) = 2 D(7) = 1 D(4) = 3 D(8)=-1 maximum gain
D(4) = 1 D(8) = 1

∆g1 = 2+1-0 = 3 ∆g2 = 3+2-0 = 5 ∆g3 = -3-3-0 = -6 Gain after node swapping
Swap (3,5) Swap (4,6) Swap (1,7)
G1 = ∆g1 =3 G2 = G1+∆g2 =8 G3= G2 +∆g3 = 2 Gain in the current pass

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 2.4.1 Kernighan-Lin (KL) Algorithm – Example

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1 5 1 5 1 5 1 5 1 5

2 6 2 6 2 6 2 6 2 6

3 7 3 7 3 7 3 7 3 7

4 8 4 8 4 8 4 8 4 8

Cut cost: 9 Cut cost: 6 Cut cost: 1 Cut cost: 7 Cut cost: 9
Not fixed: Not fixed: Not fixed: Not fixed: Not fixed:
1,2,3,4,5,6,7,8 1,2,4,6,7,8 1,2,7,8 2,8 –

D(1) = 1 D(5) = 1 D(1) = -1 D(6) = 2 D(1) = -3 D(7)=-3 D(2) = -1 D(8)=-1

D(2) = 1 D(6) = 2 D(2) = -1 D(7)=-1 D(2) = -3 D(8)=-3
D(3) = 2 D(7) = 1 D(4) = 3 D(8)=-1

© 2022 Springer Verlag

D(4) = 1 D(8) = 1

∆g1 = 2+1-0 = 3 ∆g2 = 3+2-0 = 5 ∆g3 = -3-3-0 = -6 ∆g4 = -1-1-0 = -2

Swap (3,5) Swap (4,6) Swap (1,7) Swap (2,8)
G1 = ∆g1 =3 G2 = G1+∆g2 =8 G3= G2 +∆g3 = 2 G4 = G3 +∆g4 = 0

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 2.4.1 Kernighan-Lin (KL) Algorithm – Example

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D(1) = 1 D(5) = 1 D(1) = -1 D(6) = 2 D(1) = -3 D(7)=-3 D(2) = -1 D(8)=-1
D(2) = 1 D(6) = 2 D(2) = -1 D(7)=-1 D(2) = -3 D(8)=-3
D(3) = 2 D(7) = 1 D(4) = 3 D(8)=-1
D(4) = 1 D(8) = 1

∆g1 = 2+1-0 = 3 ∆g2 = 3+2-0 = 5 ∆g3 = -3-3-0 = -6 ∆g4 = -1-1-0 = -2

Swap (3,5) Swap (4,6) Swap (1,7) Swap (2,8)
G1 = ∆g1 =3 G2 = G1+∆g2 =8 G3= G2 +∆g3 = 2 G4 = G3 +∆g4 = 0

Maximum positive gain Gm = 8 with m = 2.

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 26

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 2.4.1 Kernighan-Lin (KL) Algorithm – Example

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D(1) = 1 D(5) = 1 D(1) = -1 D(6) = 2 D(1) = -3 D(7)=-3 D(2) = -1 D(8)=-1
D(2) = 1 D(6) = 2 D(2) = -1 D(7)=-1 D(2) = -3 D(8)=-3
D(3) = 2 D(7) = 1 D(4) = 3 D(8)=-1
D(4) = 1 D(8) = 1

∆g1 = 2+1-0 = 3 ∆g2 = 3+2-0 = 5 ∆g3 = -3-3-0 = -6 ∆g4 = -1-1-0 = -2

Swap (3,5) Swap (4,6) Swap (1,7) Swap (2,8)
G1 = ∆g1 =3 G2 = G1+∆g2 =8 G3= G2 +∆g3 = 2 G4 = G3 +∆g4 = 0

Maximum positive gain Gm = 8 with m = 2.

1 5
Since Gm > 0, the first m = 2 swaps
(3,5) and (4,6) are executed.
2 6

3 7
Since Gm > 0, more passes are needed until
Gm ≤ 0.
4 8

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 27

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 2.4.2 Extensions of the Kernighan-Lin (KL) Algorithm

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• Unequal partition sizes
− Apply the KL algorithm with only min(|A|,|B|) pairs swapped

• Unequal node weights

− Try to rescale weights to integers, e.g., as multiples
of the greatest common divisor of all node weights
− Maintain area balance or allow a one-move deviation from balance

• k-way partitioning (generating k partitions)

− Apply the KL two-way partitioning algorithm to all possible pairs of partitions
− Recursive partitioning (convenient when k is a power of two)
− Direct k-way extensions exist

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 28

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 2.4.3 Fiduccia-Mattheyses (FM) Algorithm

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• Single cells are moved independently instead of swapping pairs of cells ---
cannot and do not need to maintain exact partition balance
• The area of each individual cell is taken into account
• Applicable to partitions of unequal size
and in the presence of initially fixed cells

• Cut costs are extended to include hypergraphs

• nets with 2+ pins
• While the KL algorithm aims to minimize cut costs based on edges,
the FM algorithm minimizes cut costs based on nets

• Nodes and subgraphs are referred to as cells and blocks, respectively

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 2.4.3 Fiduccia-Mattheyses (FM) Algorithm

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Given: a hypergraph G(V,H) with nodes and weighted hyperedges
partition size constraints

Goal: to assign all nodes to disjoint partitions,

so as to minimize the total cost (weight) of all cut nets
while satisfying partition size constraints

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 2.4.3 Fiduccia-Mattheyses (FM) Algorithm – Terminology

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Gain ∆g(c) for cell c 2 3
b e
∆g(c) = FS(c) – TE(c) , a 4

where c
d
1 5
the “moving force“ FS(c) is the number of nets connected
to c but not connected to any other cells within c’s
partition, i.e., cut nets that connect only to c, and

the “retention force“ TE(c) is the number of uncut nets

connected to c. Cell 2: FS(2) = 0 TE(2) = 1 ∆g(2) = -1

The higher the gain ∆g(c), the higher is the

priority to move the cell c to the other partition.

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Gain ∆g(c) for cell c 2 3
b e
∆g(c) = FS(c) – TE(c) , a 4

where c
d
1 5
the “moving force“ FS(c) is the number of nets connected
to c but not connected to any other cells within c’s
partition, i.e., cut nets that connect only to c, and

the “retention force“ TE(c) is the number of uncut nets

connected to c.
2 3
Cell 1: FS(1) = 2 TE(1) = 1 ∆g(1) = 1
b e
Cell 2: FS(2) = 0 TE(2) = 1 ∆g(2) = -1 a 4
Cell 3: FS(3) = 1 TE(3) = 1 ∆g(3) = 0
Cell 4: FS(4) = 1 TE(4) = 1 ∆g(4) = 0
c
d
Cell 5: FS(5) = 1 TE(5) = 0 ∆g(5) = 1 1 5

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Maximum positive gain Gm of a pass

The maximum positive gain Gm is the cumulative cell gain of m moves

that produce a minimum cut cost.

Gm is determined by the maximum sum of cell gains ∆g over a prefix of

m moves in a pass
m
Gm = ∑ ∆g
i =1
i

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 2.4.3 Fiduccia-Mattheyses (FM) Algorithm – Terminology

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Ratio factor

The ratio factor is the relative balance between the two partitions
with respect to cell area

It is used to prevent all cells from clustering into one partition.

The ratio factor r is defined as

area( A)
r=
area( A) + area( B )

where area(A) and area(B) are the total respective areas of partitions A and B

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Balance criterion

The balance criterion enforces the ratio factor.

To ensure feasibility, the maximum cell area areamax(V)

must be taken into account.

A partitioning of V into two partitions A and B is said to be balanced if

[ r ∙ area(V) – areamax(V) ] ≤ area(A) ≤ [ r ∙ area(V) + areamax(V) ]

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Base cell

A base cell is a cell c that has the greatest cell gain ∆g(c) among all free cells,
and whose move does not violate the balance criterion.

Base cell

Cell 1: FS(1) = 2 TE(1) = 1 ∆g(1) = 1

Cell 2: FS(2) = 0 TE(2) = 1 ∆g(2) = -1
Cell 3: FS(3) = 1 TE(3) = 1 ∆g(3) = 0
Cell 4: FS(4) = 1 TE(4) = 1 ∆g(4) = 0

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 36

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 2.4.3 Fiduccia-Mattheyses (FM) Algorithm - One pass

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Step 0: Compute the balance criterion
Step 1: Compute the cell gain ∆g1 of each cell
Step 2: i = 1
– Choose base cell c1 that has maximal gain ∆g1 , move this cell
Step 3:
– Fix the base cell ci
– Update all cells’ gains that are connected to critical nets via the base cell ci
Step 4:
– If all cells are fixed, go to Step 5. If not:
– Choose next base cell ci with maximal gain ∆gi and move this cell
– i = i + 1, go to Step 3
Step 5:
– Determine the best move sequence c1, c2, .., cm (1 ≤ m ≤ i) , so that Gm = ∑
m
i =1
Δg i is maximized
– If Gm > 0, go to Step 6. Otherwise, END
Step 6:

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 37

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 2.4.3 Fiduccia-Mattheyses (FM) Algorithm – Example

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A 2 3 B
Given:
b e Ratio factor r = 0,375
a 4 area(Cell_1) = 2
area(Cell_2) = 4
c
area(Cell_3) = 1
d
1 5 area(Cell_4) = 4
area(Cell_5) = 5.

Step 0: Compute the balance criterion

[ r ∙ area(V) – areamax(V) ] ≤ area(A) ≤ [ r ∙ area(V) + areamax(V) ]

0,375 * 16 – 5 = 1 ≤ area(A) ≤ 11 = 0,375 * 16 +5.

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 2.4.3 Fiduccia-Mattheyses (FM) Algorithm – Example

© KLMH
A 2 3 B
b e
a 4
c
d
1 5

Step 1: Compute the gains of each cell

Cell 1: FS(Cell_1) = 2 TE(Cell_1) = 1 ∆g(Cell_1) = 1

Cell 2: FS(Cell_2) = 0 TE(Cell_2) = 1 ∆g(Cell_2) = -1
Cell 3: FS(Cell_3) = 1 TE(Cell_3) = 1 ∆g(Cell_3) = 0
Cell 4: FS(Cell_4) = 1 TE(Cell_4) = 1 ∆g(Cell_4) = 0
Cell 5: FS(Cell_5) = 1 TE(Cell_5) = 0 ∆g(Cell_5) = 1

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 2.4.3 Fiduccia-Mattheyses (FM) Algorithm – Example

© KLMH
A 2 3 B
Cell1: FS(Cell_1) = 2 TE(Cell_1) = 1 ∆g(Cell_1) = 1
b e Cell 2: FS(Cell_2) = 0 TE(Cell_2) = 1 ∆g(Cell_2) = -1
a 4 Cell 3: FS(Cell_3) = 1 TE(Cell_3) = 1 ∆g(Cell_3) = 0
Cell 4: FS(Cell_4) = 1 TE(Cell_4) = 1 ∆g(Cell_4) = 0
c Cell 5: FS(Cell_5) = 1 TE(Cell_5) = 0 ∆g(Cell_5) = 1
d
1 5

Step 2: Select the base cell

Possible base cells are Cell 1 and Cell 5

Balance criterion after moving Cell 1: area(A) = area(Cell_2) = 4
Balance criterion after moving Cell 5: area(A) = area(Cell_1) + area(Cell_2) + area(Cell_5) = 11
Both moves respect the balance criterion, but Cell 1 is selected, moved,
and fixed as a result of the tie-breaking criterion.

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 2.4.3 Fiduccia-Mattheyses (FM) Algorithm – Example

© KLMH
A 2 3 B
b e
a 4
c
d
1 5

Step 3: Fix base cell, update ∆g values

Cell 2: FS(Cell_2) = 2 TE(Cell_2) = 0 ∆g(Cell_2) = 2

Cell 3: FS(Cell_3) = 0 TE(Cell_3) = 1 ∆g(Cell_3) = -1
Cell 4: FS(Cell_4) = 0 TE(Cell_4) = 2 ∆g(Cell_4) = -2
Cell 5: FS(Cell_5) = 0 TE(Cell_5) = 1 ∆g(Cell_5) = -1

After Iteration i = 1: Partition A1 = 2, Partition B1 = 1,3,4,5, with fixed cell 1.

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 2.4.3 Fiduccia-Mattheyses (FM) Algorithm – Example

© KLMH
Iteration i = 1
A 2 3 B
Cell 2: FS(Cell_2) = 2 TE(Cell_2) = 0 ∆g(Cell_2) = 2
b e Cell 3: FS(Cell_3) = 0 TE(Cell_3) = 1 ∆g(Cell_3) = -1
a 4 Cell 4: FS(Cell_4) = 0 TE(Cell_4) = 2 ∆g(Cell_4) = -2
c Cell 5: FS(Cell_5) = 0 TE(Cell_5) = 1 ∆g(Cell_5) = -1
d
1 5

Iteration i = 2

Cell 2 has maximum gain ∆g2 = 2, area(A) = 0, balance criterion is violated.

Cell 3 has next maximum gain ∆g2 = -1, area(A) = 5, balance criterion is met.
Cell 5 has next maximum gain ∆g2= -1, area(A) = 9, balance criterion is met.

Move cell 3, updated partitions: A2 = {2,3}, B2 = {1,4,5}, with fixed cells {1,3}

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 2.4.3 Fiduccia-Mattheyses (FM) Algorithm – Example

© KLMH
Iteration i = 2
A 2 3
Cell 2: ∆g(Cell_2) = 1
e
a b B Cell 4: ∆g(Cell_4) = 0
4
Cell 5: ∆g(Cell_5) = -1
c
d
1 5

Iteration i = 3

Cell 2 has maximum gain ∆g3 = 1, area(A) = 1, balance criterion is met.

Move cell 2, updated partitions: A3 = {3}, B3 = {1,2,4,5}, with fixed cells {1,2,3}

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 43

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 2.4.3 Fiduccia-Mattheyses (FM) Algorithm – Example

© KLMH
Iteration i = 3
B 2 3 A
e Cell 4: ∆g(Cell_4) = 0
a b
4 Cell 5: ∆g(Cell_5) = -1
c
d
1 5

Iteration i = 4

Cell 4 has maximum gain ∆g4 = 0, area(A) = 5, balance criterion is met.

Move cell 4, updated partitions: A4 = {3,4}, B3 = {1,2,5}, with fixed cells {1,2,3,4}

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 44

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 2.4.3 Fiduccia-Mattheyses (FM) Algorithm – Example

© KLMH
Iteration i = 4
B 2 3 A
e
a b Cell 5: ∆g(Cell_5) = -1
4
c
d
1 5

Iteration i = 5

Cell 5 has maximum gain ∆g5 = -1, area(A) = 10, balance criterion is met.

Move cell 5, updated partitions: A4 = {3,4,5}, B3 = {1,2}, all cells {1,2,3,4,5} fixed.

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 2.4.3 Fiduccia-Mattheyses (FM) Algorithm – Example

© KLMH
Step 5: Find best move sequence c1 … cm
B 2 3 A
G1 = ∆g1 = 1
G2 = ∆g1 + ∆g2 = 0 e
a b
G3 = ∆g1 + ∆g2 + ∆g3 = 1 4
G4 = ∆g1 + ∆g2 + ∆g3 + ∆g4 = 1 c
G5 = ∆g1 + ∆g2 + ∆g3 + ∆g4 + ∆g5 = 0. d
1 5

m
Maximum positive cumulative gain G =
m ∑ ∆g
i =1
i =1

found in iterations 1, 3 and 4.

The move prefix m = 4 is selected due to the better balance ratio (area(A) = 5);
the four cells 1, 2, 3 and 4 are then moved.

Result of Pass 1: Current partitions: A = {3,4}, B = {1,2,5}, cut cost reduced from 3 to 2.

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 Runtime difference between KL & FM

© KLMH
• Runtime of partitioning algorithms
− KL is sensitive to the number of nodes and edges
− FM is sensitive to the number of nodes and nets (hyperedges)

• Asymptotic complexity of partitioning algorithms

− KL has cubic time complexity per pass
− FM has linear time complexity per pass

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 47

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 Chapter 2 – Netlist and System Partitioning

© KLMH
2.1 Introduction
2.2 Terminology
2.3 Optimization Goals
2.4 Partitioning Algorithms
2.4.1 Kernighan-Lin (KL) Algorithm
2.4.2 Extensions of the Kernighan-Lin Algorithm
2.4.3 Fiduccia-Mattheyses (FM) Algorithm
2.5 Framework for Multilevel Partitioning
2.5.1 Clustering
2.5.2 Multilevel Partitioning
2.6 System Partitioning onto Multiple FPGAs

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 2.5.1 Clustering

© KLMH
• To simplify the problem, groups of tightly-connected nodes can be clustered,
absorbing connections between these nodes

• Size of each cluster is often limited so as to prevent degenerate clustering,

i.e. a single large cluster dominates other clusters

• Refinement should satisfy balance criteria

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 2.5.1 Clustering

© KLMH
a d d a d

a,b,c

b c e b c,e
e

Initital graph Possible clustering hierarchies of the graph

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 50

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 2.5.2 Multilevel Partitioning

© KLMH
© 2022 Springer Verlag
VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 51

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 2.6 System Partitioning onto Multiple FPGAs

© KLMH
FPGA FPGA
FPGA FPGA FPGA FPGA RAM Logic Logic

FPIC FPIC FPIC FPIC

Reconfigurable system with multiple Mapping of a typical system architecture

FPGA and FPIC devices onto multiple FPGAs

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 Summary of Chapter 2

© KLMH
• Circuit netlists can be represented by graphs
• Partitioning a graph means assigning nodes to disjoint partitions
− Total size of each partition (number/area of nodes) is limited
− Objective: minimize the number connections between partitions

• Basic partitioning algorithms

− Move-based, move are organized into passes
− KL swaps pairs of nodes from different partitions
− FM re-assigns one node at a time
− FM is faster, usually more successful

• Multilevel partitioning
− Clustering
− FM partitioning
− Refinement (also uses FM partitioning)

• Application: system partitioning into FPGAs

− Each FPGA is represented by a partition

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 2: Netlist and System Partitioning 53

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