ADS1252

ADS
1 252

SBAS127D – SEPTEMBER 2000 – REVISED JUNE 2006

24-Bit, 40kHz
ANALOG-TO-DIGITAL CONVERTER

FEATURES DESCRIPTION
● 24 BITS—NO MISSING CODES The ADS1252 is a precision, wide dynamic range, delta-
sigma, Analog-to-Digital (A/D) converter with 24-bit resolu-
● 19 BITS EFFECTIVE RESOLUTION UP TO
tion operating from a single +5V supply. The delta-sigma
40kHz DATA RATE
architecture is used for wide dynamic range and to ensure 24
● LOW NOISE: 2.5ppm bits of no missing code performance. An effective resolution
● DIFFERENTIAL INPUTS of 19 bits (2.5ppm of rms noise) is achieved for conversion
rates up to 40kHz.
● INL: 0.0015% (max)
The ADS1252 is designed for high-resolution measurement
● EXTERNAL REFERENCE (0.5V to 5V) applications in cardiac diagnostics, smart transmitters, indus-
● POWER-DOWN MODE trial process control, weight scales, chromatography, and
● SYNC MODE portable instrumentation. The converter includes a flexible,
2-wire synchronous serial interface for low-cost isolation.
The ADS1252 is a single-channel converter and is offered in
APPLICATIONS an SO-8 package.
● CARDIAC DIAGNOSTICS
● DIRECT THERMOCOUPLE INTERFACES
● BLOOD ANALYSIS
● INFRARED PYROMETERS
● LIQUID/GAS CHROMATOGRAPHY
● PRECISION PROCESS CONTROL

ADS1252
VREF

CLK

+VIN 4th-Order
Digital Serial SCLK
∆Σ
Filter Interface DOUT/DRDY
–VIN Modulator

+VDD
GND

Control

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 2000-2006, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

www.ti.com
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
Analog Input: Current ............................................... ±100mA, Momentary
±10mA, Continuous DISCHARGE SENSITIVITY
Voltage .................................... GND – 0.3V to VDD + 0.3V
VDD to GND ............................................................................ –0.3V to 6V
This integrated circuit can be damaged by ESD. Texas Instru-
VREF Voltage to GND ............................................... –0.3V to VDD + 0.3V ments recommends that all integrated circuits be handled with
Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V appropriate precautions. Failure to observe proper handling
Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V and installation procedures can cause damage.
Lead Temperature (soldering, 10s) .............................................. +300°C
Power Dissipation (any package) ................................................. 500mW ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade more susceptible to damage because very small parametric
device reliability. changes could cause the device not to meet its published
specifications.

PACKAGE/ORDERING INFORMATION(1)
SPECIFIED
PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
ADS1252 SO-8 D –40°C to +85°C ADS1252U ADS1252U Rails, 100
" " " " " ADS1252U/2K5 Tape and Reel, 2500

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

PIN CONFIGURATION PIN DESCRIPTIONS

Top View SO PIN NAME PIN DESCRIPTION
1 +VIN Analog Input: Positive Input of the Differen-
tial Analog Input
2 –VIN Analog Input: Negative Input of the Differ-
ential Analog Input
3 +VDD Input: Power-Supply Voltage, +5V
4 CLK Digital Input: Device System Clock. The
system clock is in the form of a CMOS-
compatible clock. This is a Schmitt-Trigger
+VIN 1 8 VREF input.
5 DOUT/DRDY Digital Output: Serial Data Output/Data
Ready. A logic LOW on this output indi-
–VIN 2 7 GND cates that a new output word is available
ADS1252U from the ADS1252 data output register.
+VDD 3 6 SCLK The serial data is clocked out of the serial
data output shift register using SCLK.
6 SCLK Digital Input: Serial Clock. The serial clock
CLK 4 5 DOUT/DRDY
is in the form of a CMOS-compatible clock.
The serial clock operates independently
from the system clock, therefore, it is pos-
sible to run SCLK at a higher frequency
than CLK. The normal state of SCLK is
LOW. Holding SCLK HIGH will either ini-
tiate a modulator reset for synchronizing
multiple converters or enter power-down
mode. This is a Schmitt-Trigger input.
7 GND Input: Ground
8 VREF Analog Input: Reference Voltage Input

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ELECTRICAL CHARACTERISTICS
All specifications at TMIN to TMAX, VDD = +5V, CLK = 16MHz, and VREF = 4.096V, unless otherwise specified.

ADS1252U
PARAMETER CONDITIONS MIN TYP MAX UNITS
ANALOG INPUT
Full-Scale Input Voltage 0 ±VREF V
Absolute Input Voltage +VIN or –VIN to GND –0.3 VDD V
Differential Input Impedance CLK = 3.84kHz 125 MΩ
CLK = 1MHz 480 kΩ
CLK = 16MHz 30 kΩ
Input Capacitance 20 pF
Input Leakage At +25°C 5 50 pA
At TMIN to TMAX 1 nA
DYNAMIC CHARACTERISTICS
Data Rate 41.7 kHz
Bandwidth –3dB 9 kHz
Serial Clock (SCLK) 16 MHz
System Clock Input (CLK) 16 MHz
ACCURACY
Integral Nonlinearity(1) ±0.0003 ±0.0015 % of FSR
THD 1kHz Input; 0.1dB below FS 97 dB
Noise 2.5 3.8 ppm of FSR, rms
Resolution 24 Bits
No Missing Codes 24 Bits
Common-Mode Rejection(2) at DC 90 100 dB
Gain Error 0.4 1 % of FSR
Offset Error ±100 ±200 ppm of FSR
Gain Sensitivity to VREF VREF = 4.096V ±0.1V 1:1
Power-Supply Rejection Ratio 60 80 dB
PERFORMANCE OVER TEMPERATURE
Offset Drift 0.07 ppm/°C
Gain Drift CLK = 16MHz 7.5 ppm/°C
CLK = 14MHz 5.2 ppm/°C
CLK = 12MHz 3.9 ppm/°C
CLK < 10MHz 3.4 ppm/°C
VOLTAGE REFERENCE
VREF 0.5 4.096 VDD V
Load Current 220 µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS
Logic Level: VIH +4.0 +VDD + 0.3 V
VIL –0.3 +0.8 V
VOH IOH = –500µA +4.5 V
VOL IOL = 500µA 0.4 V
Input (SCLK, CLK) Hysteresis 0.6 V
Data Format Offset Binary Two’s Complement
POWER-SUPPLY REQUIREMENTS
Operation +4.75 +5 +5.25 V
Quiescent Current VDD = +5VDC 8 10 mA
Operating Power 40 50 mW
Power-Down Current 1 10 µA
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –60 +100 °C

NOTES: (1) Applies to full-differential signals.

(2) The common-mode rejection test is performed with a 100mV differential input.

ADS1252 3
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TYPICAL CHARACTERISTICS
At TA = +25°C, VDD = +5V, CLK = 16MHz, and VREF = 4.096V, unless otherwise specified.

RMS NOISE vs DATA OUTPUT RATE EFFECTIVE RESOLUTION vs DATA OUTPUT RATE
3.0 19.50

2.5

Effective Resolution (bits)

RMS Noise (ppm of FS)

19.25
2.0

1.5 19.00

1.0
18.75
0.5

0 18.5
100 1k 10k 100k 100 1k 10k 100k
Data Output Rate (Hz) Data Output Rate (Hz)

RMS NOISE vs TEMPERATURE EFFECTIVE RESOLUTION vs TEMPERATURE

3.0 19.0
18.9
2.5
18.8
Effective Resolution (bits)
RMS Noise (ppm of FS)

2.0 18.7
18.6
1.5 18.5
18.4
1.0
18.3

0.5 18.2
18.1
0 18.0
–40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100
Temperature (°C) Temperature (°C)

RMS NOISE vs VREF VOLTAGE RMS NOISE vs VREF VOLTAGE

25 10
9
20 8
RMS Noise (ppm of FS)

7
RMS Noise (µV)

15 6
5
10 4
3
5 2
1
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
VREF (V) VREF (V)

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ADS1252
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TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VDD = +5V, CLK = 16MHz, and VREF = 4.096V, unless otherwise specified.

RMS NOISE vs INPUT VOLTAGE EFFECTIVE RESOLUTION vs VREF

3.0 19.00

2.5
18.50

Effective Resolution (Bits)

RMS Noise (ppm of FS)

2.0
18.00
1.5
17.50
1.0

17.00
0.5

0 16.50
–5 –4 –3 –2 –1 0 1 2 3 4 5 0 1 2 3 4 5 6
Differential Input Voltage (V) VREF (V)

INTEGRAL NON-LINEARITY vs TEMPERATURE INTEGRAL NON-LINEARITY vs DATA OUTPUT RATE

4.0 4

3.5

3.0 3
INL (ppm of FS)
INL (ppm of FS)

2.5

2.0 2

1.5

1.0 1

0.5

0 0
–40 –20 0 20 40 60 80 100 100 1k 10k 100k
Temperature (°C) Data Output Rate (Hz)

OFFSET DRIFT vs TEMPERATURE GAIN DRIFT vs TEMPERATURE

10 800
8 CLK = 16MHz
600
6
Offset Drift (ppm of FS)

4
400
CLK = 14.3MHz
Drift (ppm)

2
0 200
–2 CLK < 10MHz
0
–4
CLK < 10MHz
–6
–200
–8 CLK = 16MHz
–10 –400
–40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100
Temperature (°C) Temperature (°C)

ADS1252 5
SBAS127D www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VDD = +5V, CLK = 16MHz, and VREF = 4.096V, unless otherwise specified.

POWER-SUPPLY REJECTION RATIO COMMON-MODE REJECTION RATIO

vs CLK FREQUENCY vs CLK FREQUENCY
100 110

95
105
90
100
85

CMRR (dB)
PSRR (dB)

80 95

75
90
70
85
65

60 80
0 5 10 15 20 0 5 10 15 20
CLK Frequency (MHz) CLK Frequency (MHz)

CURRENT vs TEMPERATURE POWER DISSIPATION vs CLOCK FREQUENCY

9.5 45

9.0 40

8.5 35
Power Dissipation (mW)
Supply Current (mA)

8.0 30

7.5 25

7.0 20

6.5 15

6.0 10

5.5 5

5.0 0
–40 –20 0 20 40 60 80 100 0 5 10 15 20
Temperature (°C) CLK Frequency (MHz)

TYPICAL FFT ANALYSIS

OF THE 1kHz fS INPUT SIGNAL
0
–20
–40
Dynamic Range (dB)

–60
–80

–100
–120
–140
–160
–180
0 2000 4000 6000 8000 10000 12000 14000
Imput Signal Frequency (Hz)

6
ADS1252
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THEORY OF OPERATION Third, to prevent aliasing of the input signal, the bandwidth of
the analog input signal must be band limited; the bandwidth
The ADS1252 is a precision, high-dynamic range, 24-bit, delta- is a function of the system clock frequency. With a system
sigma, A/D converter capable of achieving very high-resolution clock frequency of 16MHz, the data-output rate is 41.667kHz
digital results at high data rates. The analog-input signal with a –3dB frequency of 9kHz, where the –3dB frequency
is sampled at a rate determined by the frequency of the system scales with the system clock frequency.
clock (CLK). The sampled analog input is modulated by
To ensure the best linearity of the ADS1252, a fully differen-
the delta-sigma A/D modulator, which is followed by a digital
tial signal is recommended.
filter. A Sinc5 digital low-pass filter processes the output of
the delta-sigma modulator and writes the result into the data-
output register. The DOUT/DRDY pin is pulled LOW, indicating BIPOLAR INPUT
that new data is available to be read by the external The differential inputs of the ADS1252 are designed to
microcontroller/microprocessor. As shown in the block dia- accept differential signals; however, each analog input volt-
gram, the main functional blocks of the ADS1252 are the age must stay between –0.3V and VDD. With a reference
4th-order delta-sigma modulator, a digital filter, control logic, voltage at less than half of VDD, one input can be tied to the
and a serial interface. Each of these functional blocks is reference voltage, and the other input can range from 0V to
described below. 2 • VREF. By using a single op amp circuit featuring a single
amplifier and four external resistors, the ADS1252 can be
ANALOG INPUT configured to accept bipolar inputs referenced to ground. The
conventional ±2.5V, ±5V, and ±10V input ranges can be
The ADS1252 contains a fully differential analog input. In
interfaced to the ADS1252 using the resistor values shown in
order to provide low system noise, common-mode rejection
Figure 1.
of 100dB, and excellent power-supply rejection, the design
topology is based on a fully differential switched-capacitor
architecture. The bipolar input voltage range is from –4.096
to +4.096V, when the reference input voltage equals +4.096V; R1

the bipolar range is with respect to –VIN, and not with respect
to GND.
10kΩ
With regard to the analog input signal, the overall analog
performance of the device is affected by three items. First, 20kΩ OPA2350 +IN ADS1252
Bipolar Input –IN
the input impedance can affect accuracy; therefore, if the VREF

source impedance of the input signal is significant, or if there

R2
is passive filtering prior to the ADS1252, a significant portion
of the signal can be lost across this external impedance. The
magnitude of the effect is dependent on the desired system
OPA2350
performance. See application note Understanding the
BIPOLAR INPUT R1 R2
ADS1251, ADS1253, and ADS1254 Input Circuitry
±10V 2.5kΩ 5kΩ
(SBAA086), available for download from TI’s web site, ±5V 5kΩ 10kΩ
REF
www.ti.com. ±2.5V 10kΩ 20kΩ
2.5V

Second, the current into or out of the analog inputs must be

limited. Under no conditions should the current into or out of
FIGURE 1. Level Shift Circuit for Bipolar Input Ranges.
the analog inputs exceed 10mA.

ADS1252 7
SBAS127D www.ti.com
DELTA-SIGMA MODULATOR REFERENCE INPUT
The ADS1252 operates from a nominal system clock fre- Reference input takes an average current of 220µA with a
quency of 16MHz which is fixed in relation to the system 16MHz system clock; this current will be proportional to the
clock frequency that is divided by 6 to derive the modulator system clock. A buffered reference is recommended for
frequency; therefore, with a system clock frequency of 16MHz, ADS1252. The recommended reference circuit is shown in
the modulator frequency is 2.667MHz. Furthermore, the Figure 2.
oversampling ratio of the modulator is fixed in relation to the Reference voltages higher than 4.096V will increase the full-
modulator frequency. The oversampling ratio of the modula- scale range, whereas the absolute internal circuit noise of the
tor is 64, and with the modulator frequency running at converter remains the same. This will decrease the noise in
2.667MHz, the data rate is 41.667kHz; thus, using a slower terms of ppm of full scale, which increases the effective
system clock frequency will result in a lower data output rate, resolution (see the typical characteristic curve, RMS Noise vs
as shown in Table I. VREF).

CLK (MHz) DATA OUTPUT RATE (Hz) DIGITAL FILTER

16.000(1) 41 667 The digital filter of the ADS1252, referred to as a sinc5 filter,
15.360(1) 40 000
computes the digital result based on the most recent outputs
15.000(1) 30 063
14.745600(1) 38 400 from the delta-sigma modulator. At the most basic level, the
14.318180(1) 37 287 digital filter can be thought of as simply averaging the
12.288000(1) 32 000
modulator results in a weighted form and presenting this
12.000000(1) 31 250
11.059220(1) 28 800 average as the digital output. The digital output rate, or data
10.000000(1) 26 042 rate, scales directly with the system CLK frequency, this
9.600000 25 000
allows the data output rate to be changed over a very wide
7.372800(1) 19 200
6.144000(1) 16 000 range (five orders of magnitude) by changing the system
6.000000(1) 15 625 CLK frequency. However, it is important to note that the
4.915200(1) 12 800
–3dB point of the filter is 0.216 times the data output rate, so
3.686400(1) 9 600
3.072000(1) 8 000 the data output rate must allow for sufficient margin to
2.457600(1) 6 400 prevent attenuation of the signal of interest.
1.843200(1) 4 800
0.921600 2 400 As the conversion result is essentially an average, the
0.460800 1 200 data-output rate determines the location of the resulting
0.384000 1 000
notches in the digital filter (see Figure 3). Note that the first
0.192000 500
0.038400 100 notch is located at the data-output rate frequency, and
0.023040 60 subsequent notches are located at integer multiples of the
0.019200 50
data-output rate to allow for rejection of not only the funda-
0.011520 30
0.009600 25 mental frequency, but also harmonic frequencies. In this
0.007680 20 manner, the data-output rate can be used to set specific
0.006400 16.67
notch frequencies in the digital filter response.
0.005760 15
0.004800 12.50
0.003840 10
NOTE: (1) Standard Clock Oscillator.

TABLE I. CLK Rate versus Data Output Rate.

+5V

+5V
0.10µF
7
0.1µF

2
1 6 To VREF
10kΩ OPA350 Pin 8 of
2 3
REF3140 + the ADS1252
+ 4 10µF 0.1µF
0.1µF 10µF 0.10µF
3

FIGURE 2. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the ADS1252.

8
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For example, if the rejection of power-line frequencies is The digital filter requires five conversions to fully settle. The
desired, then the data-output rate can simply be set to the modulator has an oversampling ratio of 64; therefore, it
power-line frequency. For 50Hz rejection, the system CLK requires 5 • 64, or 320 modulator results, or clocks, to fully
frequency must be 19.200kHz, and this will set the data- settle. As the modulator clock is derived from the system
clock (CLK) (modulator clock = CLK ÷ 6), the number of
output rate to 50Hz (see Table I and Figure 4). For 60Hz
system clocks required for the digital filter to fully settle is
rejection, the system CLK frequency must be 20.040kHz, 5 • 64 • 6, or 1920 CLKs. This means that any significant step
and this will set the data-output rate to 60Hz (see Table I and change at the analog input requires five full conversions to
Figure 5). If both 50Hz and 60Hz rejection is required, then settle. However, if the analog input change occurs asynchro-
the system CLK must be 3.840kHz; this will set the data- nously to the DOUT/DRDY pulse, then six conversions are
output rate to 10Hz and reject both 50Hz and 60Hz (see Table required to ensure full settling.
I and Figure 6).
There is an additional benefit in using a lower data-output CONTROL LOGIC
rate: it provides better rejection of signals in the frequency The control logic is used for communications and control of
band of interest. For example, with a 50Hz data-output rate, the ADS1252.
a significant signal at 75Hz can alias back into the passband
Power-Up Sequence
at 25Hz; this is due to the fact that rejection at 75Hz must
only be 66dB in the stopband—frequencies higher than the Prior to power-up, all digital and analog-input pins must be
first-notch frequency (see Figure 4). However, setting the LOW. At the time of power-up, these signal inputs can be
data-output rate to 10Hz will provide 135dB rejection at 75Hz biased to a voltage other than 0V, however, they must never
(see Figure 6). A similar benefit is gained at frequencies near exceed +VDD.
the data-output rate (see Figures 7, 8, 9, and 10). For Once the ADS1252 powers up, the DOUT/DRDY line pulses
example, with a 50Hz data-output rate, rejection at 55Hz may LOW on the first conversion; this data is not valid. The sixth
only be 105dB (see Figure 7); however, with a 10Hz data- pulse of DOUT/DRDY is valid data from the analog input
output rate, rejection at 55Hz will be 122dB (see Figure 8). signal.
If a slower data-output rate does not meet the system
requirements, then the analog front end can be designed to
provide the needed attenuation to prevent aliasing. Addition-
DOUT/ DRDY
ally, the data-output rate can be increased and additional The DOUT/DRDY output signal alternates between two
digital filtering can be done in the processor or controller. modes of operation. The first mode of operation is the Data
Application note SBAA103, A Spreadsheet to Calculate the Ready (DRDY) mode to indicate that new data has been
Frequency Response of the ADS1250-54 (available for down- loaded into the data-output register and is ready to be read.
load at www.ti.com) provides a simple tool for calculating the The second mode of operation is the Data Output (DOUT)
ADS1250 frequency response for any CLK frequency. mode and is used to serially shift data out of the Data Output
Register (DOR). See Figure 11 for the time domain partition-
The digital filter is described by the following transfer func-
ing of the DRDY and DOUT function.
tion:
See Figure 12 for the basic timing of DOUT/DRDY. During
5 the time defined by t2, t 3, and t 4, the DOUT/DRDY
 π • f • 64  pin functions in DRDY mode. The state of the
sin  
 fMOD  DOUT/DRDY pin is HIGH prior to the internal transfer of new
H(f) =
 π•f  data to the DOR. The result of the A/D conversion is written
64 • sin  
 fMOD 
or
5
 
1 – z –64
H(z) =  
 (
 64 • 1 – z –1 ) 


ADS1252 9
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 NORMALIZED DIGITAL FILTER RESPONSE DIGITAL FILTER RESPONSE
0 0
–20 –20
–40 –40
–60 –60
–80 –80
Gain (dB)

Gain (dB)
–100 –100
–120 –120
–140 –140
–160 –160
–180 –180
–200 –200
0 1 2 3 4 5 6 7 8 9 10 0 50 100 150 200 250 300
Frequency (Hz) Frequency (Hz)

FIGURE 3. Normalized Digital Filter Response. FIGURE 4. Digital Filter Response (50Hz).

DIGITAL FILTER RESPONSE DIGITAL FILTER RESPONSE

0 0
–20 –20
–40 –40
–60 –60
–80
Gain (dB)

–80
Gain (dB)

–100 –100
–120 –120
–140 –140
–160 –160
–180 –180
–200 –200
0 50 100 150 200 250 300 0 10 20 30 40 50 60 70 80 90 100
Frequency (Hz)
Frequency (Hz)

FIGURE 5. Digital Filter Response (60Hz). FIGURE 6. Digital Filter Response (10Hz Multiples).

DIGITAL FILTER RESPONSE DIGITAL FILTER RESPONSE

0 0
–20 –20
–40 –40
–60 –60
–80 –80
Gain (dB)
Gain (dB)

–100 –100
–120 –120
–140 –140
–160 –160
–180 –180
–200 –200
45 46 47 48 49 50 51 52 53 54 55 45 46 47 48 49 50 51 52 53 54 55
Frequency (Hz) Frequency (Hz)

FIGURE 7. Expanded Digital Filter Response (50Hz with a FIGURE 8. Expanded Digital Filter Response (50Hz with a
50Hz Notch). 10Hz Notch).

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 to the DOR from MSB to LSB in the time defined by t1 (see
Figures 11 and 12). The DOUT/DRDY line then drives the
DIGITAL FILTER RESPONSE
0 line LOW for the time defined by t2, and then drives the line
–20 HIGH for the time defined by t3 to indicate that new data is
–40 available to be read. At this point, the function of the DOUT/
–60 DRDY pin changes to DOUT mode, and data is shifted out
–80
on the pin after t7. If the MSB is high (because of a negative
Gain (dB)

–100
result) the DOUT/DRDY signal will stay HIGH after the end
of time t3. The device communicating with the ADS1252 can
–120
provide SCLKs to the ADS1252 after the time defined by t6.
–140
The normal mode of reading data from the ADS1252 is for
–160
the device reading the ADS1252 to latch the data on the
–180
rising edge of SCLK (since data is shifted out of the ADS1252
–200
55 56 57 58 59 60 61 62 63 64 65
on the falling edge of SCLK). In order to retrieve valid data,
Frequency (Hz)
the entire DOR must be read before the DOUT/DRDY pin
reverts back to DRDY mode.
If SCLKs are not provided to the ADS1252 during the DOUT
FIGURE 9. Expanded Digital Filter Response (60Hz with a mode, the MSB of the DOR is present on the DOUT/DRDY
60Hz Notch). line until the beginning of the time defined by t4. If an
incomplete read of the ADS1252 takes place in DOUT mode
(that is, fewer than 24 SCLKs are provided), the state of the
last bit read is present on the DOUT/DRDY line until the
DIGITAL FILTER RESPONSE
0 beginning of the time defined by t4. If more than 24 SCLKs
–20
are provided during DOUT mode, the DOUT/DRDY line
–40
stays LOW until the beginning of the time defined by t4.
–60 The internal data pointer for shifting data out on
–80 DOUT/DRDY is reset on the falling edge of the time defined
Gain (dB)

–100 by t1 and t4. This ensures that the first bit of data shifted out
–120
of the ADS1252 after DRDY mode is always the MSB of new
–140
data.
–160
–180 SYNCHRONIZING MULTIPLE CONVERTERS
–200 The normal state of SCLK is LOW; however, by holding SCLK
55 56 57 58 59 60 61 62 63 64 65 HIGH, multiple ADS1252s can be synchronized. This is ac-
Frequency (Hz) complished by holding SCLK HIGH for at least four, but less
than 20, consecutive DOUT/DRDY cycles (see Figure 13).
FIGURE 10. Expanded Digital Filter Response (60Hz with a After the ADS1252 circuitry detects that SCLK has been held
10Hz Notch). HIGH for four consecutive DOUT/DRDY cycles, the DOUT/
DRDY pin pulses LOW for 3 CLK cycles and then held HIGH,
and the modulator is held in a reset state. The modulator
is released from reset and synchronization occurs on the
falling edge of SCLK. It is important to note that prior
to synchronization, the DOUT/DRDY pulse of multiple
ADS1252s in the system can have a difference in timing up
to one DRDY period. Therefore, to ensure synchronization,
the SCLK must be held HIGH for at least five DRDY cycles.
The first DOUT/DRDY pulse after the falling edge of
SCLK occurs at t14. Valid data is not present until the sixth
DOUT/DRDY pulse.

ADS1252 11
SBAS127D www.ti.com
POWER-DOWN MODE SERIAL INTERFACE
The normal state of SCLK is LOW; however, by holding The ADS1252 includes a simple serial interface which can be
SCLK HIGH, the ADS1252 enters power-down mode. This is connected to microcontrollers and digital signal processors in
accomplished by holding SCLK HIGH for at least 20 con- a variety of ways. Communications with the ADS1252 can
secutive DOUT/DRDY periods (see Figure 14). After the commence on the first detection of the DOUT/DRDY pulse
ADS1252 circuitry detects that SCLK is held HIGH for four after power up, although data is valid until the sixth conver-
consecutive DOUT/DRDY cycles, the DOUT/DRDY pin pulses sion.
LOW for three CLK cycles, then held HIGH, and the modu- It is important to note that the data from the ADS1252 is a
lator will be held in a reset state. If SCLK is held HIGH for an 24-bit result transmitted MSB-first in Offset Binary Two’s
additional 16 DOUT/DRDY periods, the ADS1252 enters Complement format, as shown in Table III.
power-down mode and the part is released from power-down
The data must be clocked out before the ADS1252 enters
mode on the falling edge of SCLK. It is important to note that
DRDY mode to ensure reception of valid data, as described
the DOUT/DRDY pin is held HIGH after four DOUT/DRDY
in the DOUT/DRDY section of this data sheet.
cycles, but power-down mode is not entered for an additional
16 DOUT/DRDY periods. The first DOUT/DRDY pulse after
the falling edge of SCLK occurs at t16; however, subsequent DIFFERENTIAL VOLTAGE INPUT DIGITAL OUTPUT (HEX)
DOUT/DRDY pulses occur normally. Valid data is not present +Full-Scale 7FFFFFH
until the sixth DOUT/DRDY pulse. Zero 000000H
–Full-Scale 800000H

TABLE III. ADS1252 Data Format (Offset Binary Two's

Complement).

SYMBOL DESCRIPTION MIN TYP MAX UNITS

tDRDY Conversion Cycle 384 • CLK ns
DRDY Mode DRDY Mode 36 • CLK ns
DOUT Mode DOUT Mode 348 • CLK ns
t1 DOR Write Time 6 • CLK ns
t2 DOUT/DRDY LOW Time 6 • CLK ns
t3 DOUT/DRDY HIGH Time (Prior to Data Out) 6 • CLK ns
t4 DOUT/DRDY HIGH Time (Prior to Data Ready) 24 • CLK ns
t5 Rising Edge of CLK to Falling Edge of DOUT/DRDY 30 ns
t6 End of DRDY Mode to Rising Edge of First SCLK 30 ns
t7 End of DRDY Mode to Data Valid (Propagation Delay) 30 ns
t8 Falling Edge of SCLK to Data Valid (Hold Time) 5 ns
t9 Falling Edge of SCLK to Next Data Out Valid (Propagation Delay) 30 ns
t10 SCLK Setup Time for Synchronization or Power Down 30 ns
t11 DOUT/DRDY Pulse for Synchronization or Power Down 3 • CLK ns
t12 Rising Edge of SCLK Until Start of Synchronization 1537 • CLK 7679 • CLK ns
t13 Synchronization Time 0.5 • CLK 6143.5 • CLK ns
t14 Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode 2042.5 • CLK ns
t15 Rising Edge of SCLK Until Start of Power Down 7681 • CLK ns
t16 Falling Edge of CLK (After SCLK Goes LOW) Until Start of DRDY Mode 591.5 • CLK 592.5 • CLK ns
t17 Falling Edge of Last DOUT/DRDY to Start of Power Down 6143.5 • CLK ns

TABLE II. Digital Timing.

DOUT Mode DRDY Mode DOUT Mode DRDY Mode

t4 t2 t3

DOUT/DRDY DATA DATA DATA

t1

FIGURE 11. DOUT/DRDY Partitioning.

12
ADS1252
www.ti.com SBAS127D
 ADS1252
SBAS127D

CLK

t5 t6
SCLK
t7
t1 t8
t9
DOUT/DRDY MSB LSB
t4 t2 t3
DRDY Mode DOUT Mode
tDRDY

FIGURE 12. DOUT/DRDY Timing.

Synchronization Mode Starts Here

CLK
t10 Synchronization Begins Here
www.ti.com

SCLK
t12

DOUT/DRDY DATA DATA DATA

t2 t3 DOUT t4 t11 t2 t3 DOUT t4

Mode Mode
tDRDY t13 t14 tDRDY
4 tDRDY

FIGURE 13. Synchronization Mode.

Power Down Occurs Here

CLK
t10 t17
SCLK
t15

DOUT/DRDY DATA DATA DATA

t2 t3 DOUT t4 t11 t11 t2 t3 DOUT t4

Mode Mode
tDRDY t16 tDRDY
4 tDRDY
13

FIGURE 14. Power-Down Mode.

ISOLATION SYSTEM CONSIDERATIONS
The serial interface of the ADS1252 provides for simple
isolation methods. The CLK signal can be local to the The recommendations for power supplies and grounding
ADS1252, which then only requires two signals (SCLK and change depending on the requirements and specific design
DOUT/DRDY) to be used for isolated data acquisition. of the overall system. Achieving 24 bits of noise performance
is a great deal more difficult than achieving 12 bits of noise
performance. In general, a system can be broken up into four
LAYOUT different stages:
POWER SUPPLY • Analog Processing
The power supply should be well regulated and low noise. • Analog Portion of the ADS1252
For designs requiring very high resolution from the ADS1252, • Digital Portion of the ADS1252
power-supply rejection will be a concern. Avoid running • Digital Processing
digital lines under the device because they can couple noise
For the simplest system consisting of minimal analog signal
onto the die. High-frequency noise can capacitively couple
processing (basic filtering and gain), a microcontroller, and
into the analog portion of the device and will alias back into
one clock source, one can achieve high resolution by power-
the passband of the digital filter, affecting the conversion
ing all components by a common power supply. In addition,
result.
all components can share a common ground plane; thus,
there would be no distinctions between analog power and
GROUNDING ground, and digital power and ground. The layout must still
The analog and digital sections of the system design must be include a power plane, a ground plane, and careful decoupling.
carefully and cleanly partitionedl; each section must have its In a more extreme case, the design can include:
own ground plane with no overlap between them. GND must • Multiple ADS1252s
be connected to the analog ground plane, as well as all other • Extensive Analog Signal Processing
analog grounds. Do not join the analog and digital ground • One or More Microcontrollers, Digital Signal Processors, or
planes on the board, but instead connect the two with a Microprocessors
moderate signal trace. For multiple converters, connect the • Many Different Clock Sources
two ground planes at one location as central to all of the • Interconnections to Various Other Systems
converters as possible. In some cases, experimentation is
required to find the best point to connect the two planes High resolution will be very difficult to achieve for this design.
together. The printed circuit board can be designed to pro- The approach would be to break the system into as many
vide different analog/digital ground connections via short different parts as possible. For example, each ADS1252 may
jumpers; the initial prototype can be used to establish which have its own analog processing front end.
connection works best.
DEFINITION OF TERMS
DECOUPLING An attempt has been made to be consistent with the termi-
Good decoupling practices must be used for the ADS1252 nology used in this data sheet. In that regard, the definition
and for all components in the design. All decoupling capaci- of each term is given as follows:
tors, and specifically the 0.1µF ceramic capacitors, must be Analog-Input Differential Voltage—for an analog signal
placed as close as possible to the pin being decoupled. A that is fully differential, the voltage range can be compared to
1µF to 10µF capacitor, in parallel with a 0.1µF ceramic that of an instrumentation amplifier. For example, if both
capacitor, must be used to decouple VDD to GND. analog inputs of the ADS1252 are at 2.048V, the differential
voltage is 0V; however, if one analog input is at 0V and the
other analog input is at 4.096V, then the differential voltage
magnitude is 4.096V. This is the case regardless of which
input is at 0V and which is at 4.096V. The digital-output

14
ADS1252
www.ti.com SBAS127D
result, however, is quite different. The analog-input differen- each is a statistical calculation based on a given number of
tial voltage is given by the following equation: results. Noise occurs randomly; the rms value represents a
statistical measure which is one standard deviation. The ER
+VIN – (–VIN) in bits can be computed as follows:
A positive digital output is produced whenever the
 2 • VREF 
analog-input differential voltage is positive, whereas negative 20 • log  
 Vrms noise 
digital output is produced whenever the differential is nega- ER in bits rms =
tive. For example, a positive full-scale output is produced 6.02
when the converter is configured with a 4.096V reference, The 2 • VREF figure in each calculation represents the
and the analog-input differential is 4.096V, the negative full- full-scale range of the ADS1252, this means that both units
scale output is produced when the differential voltage is are absolute expressions of resolution—the performance in
–4.096V. In each case, the actual input voltages must remain different configurations can be directly compared, regardless
within the –0.3V to +VDD range. of the units.
Actual Analog-Input Voltage—the voltage at any one ana- Noise Reduction—for random noise, the ER can be im-
log input relative to GND. proved with averaging. The result is the reduction in noise by
Full-Scale Range (FSR)—as with most A/D converters, the the factor √N, where N is the number of averages, as shown
full-scale range of the ADS1252 is defined as the input which in Table IV; this can be used to achieve true 24-bit perfor-
produces the positive full-scale digital output minus the input mance at a lower data rate. To achieve 24 bits of resolution,
which produces the negative full-scale digital output. For more than 24 bits must be accumulated. A 36-bit accumula-
example, when the converter is configured with a 4.096V tor is required to achieve an ER of 24 bits. The following uses
reference, the differential full-scale range is: VREF = 4.096V, with the ADS1252 outputting data at 40kHz,
a 4096 point average takes 102.4ms. The benefits of averag-
[4.096V (positive full-scale) – (–4.096V) (negative full-scale)] = 8.192V
ing is degraded if the input signal drifts during that 100ms.
Least Significant Bit (LSB) Weight—this is the theoretical
amount of voltage that the differential voltage at the analog
N NOISE ER ER
input has to change in order to observe a change in the (NUMBER REDUCTION IN IN
output data of one least significant bit. It is computed as OF AVERAGES) FACTOR µVrms BITS rms
follows: 1 1 31.3µV 18
2 1.414 22.1µV 18.5
Full−ScaleRange
LSB Weight = 4 2 15.6µV 19
2N 8 2.82 11.1µV 19.5
16 4 7.82µV 20
where N is the number of bits in the digital output. 32 5.66 5.53µV 20.5
Conversion Cycle—as used here, a conversion cycle refers 64 8 3.91µV 21
128 11.3 2.77µV 21.5
to the time period between DOUT/DRDY pulses.
256 16 1.96µV 22
Effective Resolution (ER)—of the ADS1252 in a particular 512 22.6 1.38µV 22.5
configuration can be expressed in two different units: 1024 32 978nV 23
bits rms (referenced to output) and µVrms (referenced to 2048 45.25 692nV 23.5
4096 64 489nV 24
input). Computed directly from the converter output data,
TABLE IV. Averaging.

ADS1252 15
SBAS127D www.ti.com
 Revision History

DATE REVISION PAGE SECTION DESCRIPTION

6/06 D 11 DOUT/DRDY Text changes to DOUT/DRDY section.

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

16
ADS1252
www.ti.com SBAS127D
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

ADS1252U ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
1252U
ADS1252U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
1252U
ADS1252U/2K5G4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
1252U
ADS1252UG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 ADS
1252U

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ADS1252U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS1252U/2K5 SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
ADS1252U D SOIC 8 75 506.6 8 3940 4.32
ADS1252UG4 D SOIC 8 75 506.6 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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