0% found this document useful (0 votes)
33 views10 pagesDE. Logic Gates
Uploaded by
Ng HitmanCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
0% found this document useful (0 votes)
33 views10 pagesDE. Logic Gates
Uploaded by
Ng HitmanCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
/ 10
Chapter
Logic Gates and
Logic Circuits
Syllabus
| Basic and Universal gates.
Chapter Contents
2.1 Binary Logic and Logic Levels,
22 Logic Gates
23 NOT Gate or Inverter
AND Gate
The OR Gate
Universal Gates
Special Type of Gates or Derived Gates
@ scanned with OKEN Scanner nd Logi
gle C208 ad L2H Cray
DL&A (Sem_1/8.ScT/ MU)
Log!
2.1__Binary Logic and Logic Levels :
A logic statement, is defined as a statement which is
true if some condition is satisfied and false if that
condition is not satisfied
~ For example, a bulb tums ON, if we close the switch,
otheewise itis OFF
24.4 Positive Logic Ti
Discuss active high and active low signal
Tina
tron s7, 2 mar |
at
~ A “LOW” voltage level represents “logic 0° state and a
comparatively “HIGH* output voltage level represents
“logic 1” state, as shown in Fig. 21.1(2),
5
cutout | Logie 1
voltage
ov: ~ Logie 0
(8-439)Fig. 2.1.1(0): Positive logic
~ For example, 0 Volt represent a logic 0 state and
+5 Vepresent logic 1. This is called as “positive logic”.
Positive Logic :
Logic 0 (Low) = ov,
Logic 1 (HIGH) = +5 v.
ieee
2.1.2 Negative Logi
Discuss active high and active low signal
(April 17, 2 Marks)
= A “LOW” voltage level represents “logic 1” state and a
“HIGH” output voltage level represents. “logic 0° state,
‘as shown in Fig. 21.100).
Logic 0
ov Logie 1
(@-429)Fig. 2.1.1(b) : Negative logic
= For example, 0 Volts represent a “logic 1" state and
+5 V represent “logic 0° state. This is called as ‘negative
logic*.
Negative Logic :
Logic 0 (LOW) = + 5 V, Logic 1 (HIGH) = OV.
Ii this book, we are going to consider only the
positive logic. Also we will assume the logic 0 level
comesponds to 0 Volts and logic 1 level
Definition = ae
je ccs which act a8 the by.
th
any digital stern
9 ONE OF MOFE than gy
Logic gates
building blo
input and the outpy
pis logic, the gates aTe named 25 toy
t!
Depending 0” ato, NOR
‘AND gate,
io diferent laws, rules and theorems 4,
We have to use
analy the aigital rus
ng te gates mentioned eater, in deren
sy connect
an build circuits that €2n perform arithmetic
‘ways, we can it
Ow pena ith he Buren in
wd
ecause they simulate mental PrOCeSSES, GALES ae often
caus
called as logic circuits.
224 Classification of Logic Gates :
‘As shown in Fig. 2.21, the logic gates are classified into
thvee categories namely, the basic gates, the universal
gates and the special purpose gates.
Logie Gatos
‘Special Purpose Gates|
(@-448ia) Fig. 22.1: Classification of gates
NNAND gate
NOR gato
EX-OR gato
EX-NOR gate
2.3 _ NOT Gate or Inverter
_NOTGateorinverter:
Definition :
: :
he NOT gates a logic gate that produces an inverted
Yersion or‘complement” ofits input
also known as an Inverter.
corresponds to + 5 V.
Te
@ scanned with OKEN Scanner DUBA (Sem 1
i) a
Lopleal symbol and Truth Table
The NOT gat
ate OF Inverter is a logic gate having one
inp (9 and one out
Ns symbol and truth table are shown in Fig. 2.3.1.
[lui rot rron
Symmes Wt © D3 may
Wotan
cyan
ruth ble o
vipat
1
[ve
(b)
: iy (© Equivalent circults
(0-480) Fig. 2.3.1: Symbol, truth table and equivalent clcult
of aNOT gate
The expression rel
Pression felating the inputs A and output (¥) of
an inverter is called as its Boolean expression. The
Boolean expression for an inverter is,
gece
AND Gate
won Trem
(2) Logical symbo!
(0459 Fig. 24.1
{) Truth table
Boolean expression
— The expression relating the inputs (A,B) and output ()
of a gate is called as the Boolean expression.
~The Boolean expression for an AND gate is
v=AB
— where the ‘dot between A and B represents
‘multiplication.
2.4.1. Multiple Input AND Gates : (aan
Pel
1.1 Draw the output waveform of AND gate and
explain is operation. Also discuss about 4 input
AND gate, (Dec. 17, 5 Marks)
Q.1 Describe the AND gate and the XOR gate with the
symbol, the logical statement, the Boolean
‘expression and its logical circuit diagram.
(Apri 18, 5 Marks)
= AND is one of the logic operators. It performs the
logical multiplication on its inputs.
= The output is high (¥ = 1) if and only if all the inputs to
the AND gate are high (2).
= The output is low (0), if any one or more inputs are
ow (0.
— AND gate can have two or more inputs and only one
output.
Logical symbol and Truth Tabl
= The logical symbol of a two input AND gate is as shown
in Fig. 24100).
= The truth table of a two input AND gat
Fig, 24.16).
~ Note that the output is HIGH (1) only when both the
inputs are HIGH (1).
‘Symbol and Truth table :
~The symbol for a 3 input AND gate is shown in
Fig. 24.200.
= The same figure shows the symbol of a 4 input AND
gate as well
= Fig. 2442(b) shows the truth table of a 3 input AND gate.
The output is HIGH (1) if and only if all the inputs are
HIGH (1) simultaneously.
symbole: Truth tablo
io Taputs | output
=| y [ale y
AALS esp AL e £
‘Taree input AND gato oto
efols[
a» o[7[e[ e
Tpus 8 y [|e i[o
c:
.D °
(2) Four input AND gate °
°
‘Outputs 1 only when}
alltha inputs are 4 $f
(6) Truth table for 3-input AND gate
(6-455) Fig. 2.4.2 Symbols and truth tables fora 3Input
AND gate
Techknouledy
@ scanned with OKEN Scanner WF ousaison 1/0 seit at)
Booiean expression
The Boolean expression for a 3-input and 4-input AND
Logic G&tES SPE Logic ¢,
ical addition o
pe logical iS
can pe high (2) if any ong 5")
“Or wi ill be low
OF tr ouput wil Be ow
thereon Hil Og simultaneously lw
the ip s
nthe
iy i
gates are, 1 Iogical symbol OF 0 ing
Y = A-B-C and Y=A-B-C-D | Log! 00 the %
2.4.2 Operation with Pulsed Inputs ia
oa!
[wu 006.17] 7 table for 3 160 in
Truth tab sis the eruth ey
fig. 2530 ee
Draw the output waveform of AND gate and gate Inputs _| Ouipan
‘explain it's operation. Also discuss about 4 input ais ¥
AND gate, (Dec. 17, 5 Marks) ofol os
~The operating principle of an AND gate remains same 7 yout) = Pott] +
Fig, 24.30 ty
= The input and output waveforms for the pulsed ant (b) Truth table
ee Fig. 2
js LOW (0) if and only if
ALS} [ee 2 ite that the output Ys LOW 0) ly if both,
a DW (0).
Inputs. 14 1 inputs are LO"
{ 5 ° oO any one or both the inputs are HIGH (1), then ty
‘output ¥is HIGH (2)
Interval <—+e—te—vg tote
Loomwy ww
1 1
(2) Timing diagrams for the pulsed operation
‘of a two input AND gate
2
‘Symbol and Truth table =
Boolean equation:
‘The Boolean expression for a two input OR gate is,
y = A+B
5.1 Multiple Input OR Gate :
Fig, 25.2(a) shows the logical symbols of 3 input ad
Inputs | Output
Interval ree Out 4 input OR gates
otatoo Fig. 25.2(b) shows the truth table of a 3 input OR git
a ce a which shows that the output is 0 if all the inputs ae
i ololo O and output is 1 (HIGH) if at least one input is 1
w fols]o Symbols :
Ce ee
Tapats —] Oupat
“
w fifo} o SD. Epr
w [ole] o ‘i efefol
(6) Summary of the pulsed operation Twweimpaton Foto ba ta
2.5 The OR Gate [ar “ fafa fr Jounies
° Pepe pop iatins
ooo np
9 Fe ee
Q.1 Describe the NAND and the OR gate with the k Oo |
symbol, the logical statement, the boolean meneoe Ca La 7
‘expression and its logical circuit diagram. @ (b)Three input OR gate
(2-482 Fig, 25.2: Symbo
(April 19, 5 Marks) ‘Symbols, Boolean equations and trut
tables for mult
a an
ile input OR gate
wee
@ scanned with OKEN Scanner DLAA |
mm 1/B SoAT/ MU)
N equations :
y
Book
ASBSC Yeas BeCeD
2.5.2 Timing Diagram (Pulsed Operation) :
The input any
‘pt and output voltage waveforms fr the pulsed
operation of
" two input OR gate are as shown in
Fig, 25300,
From the we
he waveforms, we conclude that the OR gate will
obey’ its tn
Hs truth table for the pulse operation as well
1 1
we oT Yo of 1
1 1
nee HES
om BETTE
wronat bo
Logic Gates and Logie Circuits
er will have 10
1 advantage because @
make a stock of only NAND or NOR gate ICs with him
2.6.1 The NAND Gate :
Tin
Q.4 White short notes on
input bubbled OR gate.
Describe the NAND and the OR gate with the
the boolean
This is a at
input bubbled AND gate and
(Dec. 18, 6 Marks)
a2
‘symbol, the logical statement,
expression and its logical circuit diagram.
(April 19, 5 Marks)
Logical symbol :
‘The term NAND can be split as NOT-AND which means
that the NAND operation can be implemented with the
combination of an AND gate and a NOT gate ie.
Do
(b) Equivalent circuit
inverter.
{@) Timing diagra
oe ee sect = ‘Thus @ NAND gate is equivalent to an AND gate
Intervat |Puts_| Output foowedy anv stow in Fi 26100).
Ajet y “mvoon
! ofolo
* |
7 1[o] 4 ° Y(Output) :
me bart
{2) Logical symbol
wo fo} o Logical symt §
Vober bos at
{(&) Summary ofthe pulsed operation
(€250 Fig. 25.3
6 Universal Gates Tamim
uD ms
1.1 What is meant by universal logic gate ? Draw logic
circuits showing construction of Ex-OR gate using
NAND gate and using NOR gate.
(April 17, 5 Marks)
Sor
Definition:
~The logie gate using which we can realize any Boolean
expression is known as a universal gate
The NAND and NOR gates are called as “Universal
Gates" because itis possible to implement any Boolean
expression with the help of only NAND or only NOR
ates.
Therefore a user can build any logical circuit with the
(@ Truth table
(0-467 Fig. 2.6.1: Two input NAND gate
The symbol of a two input NAND gate is shown in
Fig. 26:1@) where a bubble (o) on the output side
represents inversion.
‘Truth table:
= The truth table of a two input NAND gate is shown in
Fig. 26:(0), which shows that the output is low (0) if
and only if both the inputs are high (1) simultaneously.
For all other input combinations the output voltage will
be high (a).
‘ANAND gate is called as “Universal Gate" because we
can construct AND, OR and NOT gates using only
'NAND gates.
help of only NAND gates or only NOR gates.
Techno
@ scanned with OKEN Scanner Wow (Sem 1/B Se-1T/ MU)
Boolean expression :
The Boolean expression forthe two input NAND gate i,
You
\Where the line (bar) over the expression A.B represents
an inversion,
2.6.2 Multiple Input NAND Gate :
Logical symbol and truth table :
‘input NAND gates.
least one input is low.
st
oe
; ae
&D- EEE
ee WT
; co
c - 1 one input
: it:
Four input NAND 1 ik
‘only it all inputs are 1] a
(8-468) Fig. 26.2(a) and (b) : Three input NAND gates
Boolean equations ;
Y= hee
Y= RBOD
2.6.3 The NOR Gate :
1 Write short notes on input bubbled AND gate and
input bubbled OR gate, (Dec. 18, 5 Marks)
Logical symbol :
This is another universal gate. The word NOR can be
split as NOT-OR which means that a NOR operation can
be implemented with the combination of an OR gate
and a NOT gate, ie. inverter.
Hc,
0 ——C—C F—=—E_, «CC is FE
nen”, ee — —L—<—
F'9. 262(a) shows the circuit symbols of 3 input and 4
Fig, 262(b) shows the truth table for a 3 input NAND
‘9ate which shows that the output is LOW (0) if all the
Inputs are HIGH (1), whereas the output is HIGH (1) if at
Loge G3te$ 20 Lop.
sjvalert 10 39 OR gang
te 5 3(b),
NOR OFF wn in 9-25
sto
‘hus
ty ges pt NOR Sate is oy
2 ‘
_ re spb * pybble (0) 09 the op,
263 .
fa
represent ie
‘symbols? ppresers
ese
fan aoa
x Paes pad
B: 4 a
(ap tonlst70= a
‘ ert (Truth tbe
copeeunater i
‘wo input NOR gate
oar Fig. 26
Truth table:
he nah tbe of 2140 HUE NOR GE Is shag
fig, 263, which shows that “the output of a yo,
tei igh (1 and only if alts iMpULS are toy
simultaneously”
The output ofa two input NOR gate is Jw (0) if nye
‘or all the inputs are at high (1) level.
NOR gate, ke NAND gate can be used 35 a univeny
gate
Boolean expres
The Boolean expression for the two input NOR gate s
siven by,
Y= AB
2.6.4 Multiple Input NOR Gate :
Logical symbol and truth table :
Fig. 264(a) shows the logical symbols of 3 input and
input NOR gates, and their Boolean expressions.
9. 264() shows the truth table of a3 input NOR gat
‘ch shows that ts output is HIGH (2) if all he inp
‘te LOW (0) whereas its output is LOW(0 if atleast one
input is
AE Techterat
@ scanned with OKEN Scanner 18 Sem MU)
symbole
Twn tate
oan
Y
©
||
© oxtptis tow
0 |tattastene
annie
ll
2
(©) Three input NOR gate
(6.472) Fig. 2.6.4: Symbols, Boolean equations and truth
table for multiple input NOR gate
Boolean equations
Y= Reeve
y
Special Type of Gat
Gates ites or Derived
27
EX-OR and EX-NOR gates are special type of gates. They
can be used for applications such as half adder, full
adder and subtractors.
These gates are also called as the derived gates,
2.7.1 The EX-OR Gate :
@.4 Describe the AND gate and the XOR gate with the
symbol, the logical statement, the Boolean
expression and its logical circuit diagram.
(April 18, 5 Marks)
‘Symbol and Truth table :
= The exclusive-OR gate is abbreviated as EX-OR gate or
sometimes as X-OR gate.
‘An EX-OR gate can have two oF more than two input
terminals and one output terminal as shown in
Figs. 27.(@) and (b).
The truth table of a two input EX-OR gate is shown in
Fig, 27.1(0), which shows that, when both the inputs are
at identical logic levels (A = B), the output is low (0) ie
Y=0for A= B= 0 or A= B= 1,and the output is high
(1) when A » B.
27 Logi Gates and Logic Circuits
pee ipa | Ovteut
® A B Y
(2) Symbol of to
‘Input EX-OR gate o > =
: on 7
i < 1 oO 1
¢
6 fans |e
{)Trth table ofa two Input
b) Symbol of four
pat 1EX-OR gate
Input EX-OR gate
(0.475) Fig. 27.2
Boolean expression:
~The Boolean expression for the two input EX-OR gate is,
Y=A@B.
‘The alternate Boolean expression for a two input EX-OR
gate can be as follows
Y = AB+AB
2.7.2. Multiple Input EX-OR Gate :
‘Symbol and Truth table :
= BEOR gates having more than two inputs and one
‘output are available in market.
‘Symbols of such EX-OR gates are shown in Fig. 27.2(0)
‘and the truth table of a three input EX-OR gate is shown
in Fig, 27200
‘This truth table shows that the output of an EX-OR gate
is high (1) if odd number of inputs are held at logic
high (2),
‘Symbols :
Spee operas
Tica
: ceo POP Pe oun
: te ties
B- vy eacesozp ie oi is [number of
(@) Multiple input —_(b) Truth table ofa three input
econ gees Seon ast
(8-477) Fig. 2.7.2
@ scanned with OKEN Scanner WF oxen com so sera)
Boolean equations :
Y = A@Bac
Y = A@Bw@caD
Applications of EX-OR :
ae 3
Some of the applications of an EX-OR gate are %
follows
1. Asa magnitude comparator,
2 Inthe binary to gray code converter
3. Inthe adder and subtractor circuits
1. Inthe parity generator.
5. As amodulo-2 adder.
2.7.3. The EX-NOR Gate :
The word EX-NOR is a short form of exclusive-NOR.
Exclusive-NOR means NOT-exclusive OR, so EX-NOR
gate is equivalent to an EX-OR gate followed by a NOT
gate
‘Symbol and Truth table :
‘The symbol for @ two input EX-NOR gate is as shown in
Fig, 273(@) and its truth table is given in Fig. 27.31),
Which shows that the output of an EX-NOR gate is high
11) if both the inputs are identical (A = 8) and the
‘output is Low (0 if the inputs are not identical (A+ B).
7B
x
B
{2) Symbol ofa two Input EX-NOR gate
¥=kOEOCOD
20 o>
{®)A four Input EX-NOR gate
(6) Truth table of a two input
EX-NOR gate
(0-47 Fig..27.3
Res he
ook
multiple Input EX-NOR Gate ;
more than two inputs ar,
ot of ate input NOR QBte i sy,
a = and its truth table is a5 shay,
fig. 27400 :
ig. 27.40)
Fig. 2 ouputis!
number
when even rarer
otnpute aro HIGH (1)
ap
“Three Input EXNOR
: Y
°
°
Four input EX:NOR
(©) Truth table of three
Input EX:NOR gates
(8-420) Fig. 2.7.4
= Looking at the truth table we conclude that the outpu
(2) Muttiple input
EXANOR gates
of an EX-NOR gate is high (1) when even number ¢
inputs are high (1) or when all inputs are zeros.
Boolean equations :
Y = A@BaC
Y = A@BSCED
Applications of EX-NOR :
1. Aseven parity generator.
2 Asa comparator.
3. Aseven parity
ae renee
@ scanned with OKEN Scanner Wonton tresses :
Ex. 27-4: Prove that EX.NOR gate is complement of | 2 5
EX-OR gate, Draw symbo and truth table for both
soln. = 2 EXOR Gate
0.6 Draw the sy and tu tae for
Refer Sections
